diff -Nru libdrm-2.4.102/amdgpu/amdgpu_gpu_info.c libdrm-2.4.105/amdgpu/amdgpu_gpu_info.c --- libdrm-2.4.102/amdgpu/amdgpu_gpu_info.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/amdgpu/amdgpu_gpu_info.c 2021-04-07 14:09:24.163843400 +0000 @@ -331,3 +331,18 @@ return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info)); } + +drm_public int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type, + unsigned size, void *value) +{ + struct drm_amdgpu_info request; + + memset(&request, 0, sizeof(request)); + request.return_pointer = (uintptr_t)value; + request.return_size = size; + request.query = AMDGPU_INFO_VIDEO_CAPS; + request.sensor_info.type = cap_type; + + return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, + sizeof(struct drm_amdgpu_info)); +} diff -Nru libdrm-2.4.102/amdgpu/amdgpu.h libdrm-2.4.105/amdgpu/amdgpu.h --- libdrm-2.4.102/amdgpu/amdgpu.h 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/amdgpu/amdgpu.h 2021-04-07 14:09:24.163843400 +0000 @@ -1238,6 +1238,23 @@ unsigned size, void *value); /** + * Query information about video capabilities + * + * The return sizeof(struct drm_amdgpu_info_video_caps) + * + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * \param caps_type - \c [in] AMDGPU_INFO_VIDEO_CAPS_DECODE(ENCODE) + * \param size - \c [in] Size of the returned value. + * \param value - \c [out] Pointer to the return value. + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type, + unsigned size, void *value); + +/** * Read a set of consecutive memory-mapped registers. * Not all registers are allowed to be read by userspace. * diff -Nru libdrm-2.4.102/amdgpu/amdgpu-symbols.txt libdrm-2.4.105/amdgpu/amdgpu-symbols.txt --- libdrm-2.4.102/amdgpu/amdgpu-symbols.txt 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/amdgpu/amdgpu-symbols.txt 2021-04-07 14:09:24.163843400 +0000 @@ -66,6 +66,7 @@ amdgpu_query_hw_ip_info amdgpu_query_info amdgpu_query_sensor_info +amdgpu_query_video_caps_info amdgpu_read_mm_registers amdgpu_va_range_alloc amdgpu_va_range_free diff -Nru libdrm-2.4.102/amdgpu/meson.build libdrm-2.4.105/amdgpu/meson.build --- libdrm-2.4.102/amdgpu/meson.build 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/amdgpu/meson.build 2021-04-07 14:09:24.163843400 +0000 @@ -21,7 +21,7 @@ datadir_amdgpu = join_paths(get_option('prefix'), get_option('datadir'), 'libdrm') -libdrm_amdgpu = shared_library( +libdrm_amdgpu = library( 'drm_amdgpu', [ files( @@ -36,7 +36,7 @@ ], include_directories : [inc_root, inc_drm], link_with : libdrm, - dependencies : [dep_pthread_stubs, dep_atomic_ops], + dependencies : [dep_pthread_stubs, dep_atomic_ops, dep_rt], version : '1.0.0', install : true, ) diff -Nru libdrm-2.4.102/core-symbols.txt libdrm-2.4.105/core-symbols.txt --- libdrm-2.4.102/core-symbols.txt 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/core-symbols.txt 2021-04-07 14:09:24.163843400 +0000 @@ -83,6 +83,7 @@ drmHashLookup drmHashNext drmIoctl +drmIsKMS drmIsMaster drmMalloc drmMap diff -Nru libdrm-2.4.102/data/amdgpu.ids libdrm-2.4.105/data/amdgpu.ids --- libdrm-2.4.102/data/amdgpu.ids 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/data/amdgpu.ids 2021-04-07 14:09:24.163843400 +0000 @@ -4,10 +4,67 @@ # device_id, revision_id, product_name <-- single tab after comma 1.0.0 +15DD, C3, AMD Radeon(TM) Vega 3 Graphics +15DD, CB, AMD Radeon(TM) Vega 3 Graphics +15DD, CE, AMD Radeon(TM) Vega 3 Graphics +15DD, D8, AMD Radeon(TM) Vega 3 Graphics +15DD, CC, AMD Radeon(TM) Vega 6 Graphics +15DD, D9, AMD Radeon(TM) Vega 6 Graphics +15DD, C2, AMD Radeon(TM) Vega 8 Graphics +15DD, C4, AMD Radeon(TM) Vega 8 Graphics +15DD, C8, AMD Radeon(TM) Vega 8 Graphics +15DD, CA, AMD Radeon(TM) Vega 8 Graphics +15DD, D1, AMD Radeon(TM) Vega 8 Graphics +15DD, D5, AMD Radeon(TM) Vega 8 Graphics +15DD, D7, AMD Radeon(TM) Vega 8 Graphics +15DD, C3, AMD Radeon(TM) Vega 10 Graphics +15DD, D0, AMD Radeon(TM) Vega 10 Graphics +15DD, C1, AMD Radeon(TM) Vega 11 Graphics +15DD, C6, AMD Radeon(TM) Vega 11 Graphics +15DD, C9, AMD Radeon(TM) Vega 11 Graphics +15DD, D3, AMD Radeon(TM) Vega 11 Graphics +15DD, D6, AMD Radeon(TM) Vega 11 Graphics 15DD, 81, AMD Ryzen Embedded V1807B with Radeon Vega Gfx 15DD, 82, AMD Ryzen Embedded V1756B with Radeon Vega Gfx 15DD, 83, AMD Ryzen Embedded V1605B with Radeon Vega Gfx 15DD, 85, AMD Ryzen Embedded V1202B with Radeon Vega Gfx +15D8, 93, AMD Radeon(TM) Vega 1 Graphics +15D8, C4, AMD Radeon(TM) Vega 3 Graphics +15D8, C5, AMD Radeon(TM) Vega 3 Graphics +15D8, CC, AMD Radeon(TM) Vega 3 Graphics +15D8, CE, AMD Radeon(TM) Vega 3 Graphics +15D8, CF, AMD Radeon(TM) Vega 3 Graphics +15D8, D4, AMD Radeon(TM) Vega 3 Graphics +15D8, DC, AMD Radeon(TM) Vega 3 Graphics +15D8, DD, AMD Radeon(TM) Vega 3 Graphics +15D8, DE, AMD Radeon(TM) Vega 3 Graphics +15D8, DF, AMD Radeon(TM) Vega 3 Graphics +15D8, E3, AMD Radeon(TM) Vega 3 Graphics +15D8, E4, AMD Radeon(TM) Vega 3 Graphics +15D8, A3, AMD Radeon(TM) Vega 6 Graphics +15D8, B3, AMD Radeon(TM) Vega 6 Graphics +15D8, C3, AMD Radeon(TM) Vega 6 Graphics +15D8, D3, AMD Radeon(TM) Vega 6 Graphics +15D8, A2, AMD Radeon(TM) Vega 8 Graphics +15D8, B2, AMD Radeon(TM) Vega 8 Graphics +15D8, C2, AMD Radeon(TM) Vega 8 Graphics +15D8, C9, AMD Radeon(TM) Vega 8 Graphics +15D8, CB, AMD Radeon(TM) Vega 8 Graphics +15D8, D2, AMD Radeon(TM) Vega 8 Graphics +15D8, D9, AMD Radeon(TM) Vega 8 Graphics +15D8, DB, AMD Radeon(TM) Vega 8 Graphics +15D8, A1, AMD Radeon(TM) Vega 10 Graphics +15D8, B1, AMD Radeon(TM) Vega 10 Graphics +15D8, C1, AMD Radeon(TM) Vega 10 Graphics +15D8, D1, AMD Radeon(TM) Vega 10 Graphics +15D8, C8, AMD Radeon(TM) Vega 11 Graphics +15D8, CA, AMD Radeon(TM) Vega 11 Graphics +15D8, D8, AMD Radeon(TM) Vega 11 Graphics +15D8, DA, AMD Radeon(TM) Vega 11 Graphics +15D8, 91, AMD Ryzen Embedded R1606G with Radeon Vega Gfx +15D8, 92, AMD Ryzen Embedded R1505G with Radeon Vega Gfx +15D8, CF, AMD Ryzen Embedded R1305G with Radeon Vega Gfx +15D8, E4, AMD Ryzen Embedded R1102G with Radeon Vega Gfx 6600, 0, AMD Radeon HD 8600/8700M 6600, 81, AMD Radeon (TM) R7 M370 6601, 0, AMD Radeon (TM) HD 8500M/8700M @@ -45,6 +102,7 @@ 6665, 83, AMD Radeon (TM) R5 M320 6667, 0, AMD Radeon R5 M200 Series 666F, 0, AMD Radeon HD 8500M +66A1, 06, AMD Radeon (TM) Pro VII 66AF, C1, AMD Radeon VII 6780, 0, ATI FirePro V (FireGL V) Graphics Adapter 678A, 0, ATI FirePro V (FireGL V) Graphics Adapter @@ -181,6 +239,7 @@ 6985, 00, AMD Radeon Pro WX3100 6987, 80, AMD Embedded Radeon E9171 6987, C0, Radeon 550X Series +6987, C1, AMD Radeon RX 640 6987, C3, Radeon 540X Series 6995, 00, AMD Radeon Pro WX2100 6997, 00, Radeon Pro WX2100 @@ -195,6 +254,8 @@ 7300, CB, AMD Radeon (TM) R9 Fury Series 7300, CA, AMD Radeon (TM) R9 Fury Series 7312, 00, AMD Radeon Pro W5700 +731E, C6, AMD Radeon RX 5700XTB +731E, C7, AMD Radeon RX 5700B 731F, C0, AMD Radeon RX 5700 XT 50th Anniversary 731F, C1, AMD Radeon RX 5700 XT 731F, C2, AMD Radeon RX 5600M @@ -206,8 +267,13 @@ 7340, C1, Radeon RX 5500M 7340, C5, Radeon RX 5500 XT 7340, C7, Radeon RX 5500 +7340, C9, AMD Radeon RX 5500XTB +7340, CF, Radeon RX 5300 7341, 00, AMD Radeon Pro W5500 7347, 00, AMD Radeon Pro W5500M +73BF, C0, AMD Radeon RX 6900 XT +73BF, C1, AMD Radeon RX 6800 XT +73BF, C3, AMD Radeon RX 6800 9874, C4, AMD Radeon R7 Graphics 9874, C5, AMD Radeon R6 Graphics 9874, C6, AMD Radeon R6 Graphics @@ -217,4 +283,5 @@ 9874, 87, AMD Radeon R5 Graphics 9874, 85, AMD Radeon R6 Graphics 9874, 84, AMD Radeon R7 Graphics +6FDF, E7, AMD Radeon RX 590 GME 6FDF, EF, AMD Radeon RX 580 2048SP diff -Nru libdrm-2.4.102/debian/changelog libdrm-2.4.105/debian/changelog --- libdrm-2.4.102/debian/changelog 2020-09-17 09:29:42.000000000 +0000 +++ libdrm-2.4.105/debian/changelog 2021-05-19 08:15:08.000000000 +0000 @@ -1,14 +1,53 @@ -libdrm (2.4.102-1ubuntu1~20.04.1) focal; urgency=medium +libdrm (2.4.105-3~20.04.1) focal; urgency=medium - * Backport to focal. (LP: #1902244) + * Backport to focal. (LP: #1923880, #1925320) - -- Timo Aaltonen Thu, 17 Sep 2020 12:29:42 +0300 + -- Timo Aaltonen Wed, 19 May 2021 11:15:08 +0300 -libdrm (2.4.102-1ubuntu1) groovy; urgency=medium +libdrm (2.4.105-3) experimental; urgency=medium - * patches: Add support for Intel Rocket Lake. + * Revert a commit causing additional dependencies to be added to *.pc.in. + Also drop libpciaccess-dev from libdrm-dev Depends. - -- Timo Aaltonen Thu, 27 Aug 2020 12:40:12 +0300 + -- Timo Aaltonen Sat, 08 May 2021 22:52:07 +0300 + +libdrm (2.4.105-2) experimental; urgency=medium + + * control: Add libpciaccess-dev to libdrm-dev depends. + * revert-set-fb-modifiers-flag.diff: Revert a commit which broke + chrome on certain setups. + + -- Timo Aaltonen Wed, 05 May 2021 18:04:17 +0300 + +libdrm (2.4.105-1) experimental; urgency=medium + + * New upstream release. (LP: #1923880) + * symbols: Updated. + + -- Timo Aaltonen Thu, 15 Apr 2021 08:45:32 +0300 + +libdrm (2.4.104-1) unstable; urgency=medium + + * New upstream release. + * Add signing-key from Simon Ser. + * control: Manpages now need python3-docutils instead of docbook-xsl + to build, make it so. + + -- Timo Aaltonen Thu, 28 Jan 2021 12:18:32 +0200 + +libdrm (2.4.103-2) unstable; urgency=medium + + * hurd-port.diff: Dropped. (Closes: #975658) + + -- Timo Aaltonen Fri, 27 Nov 2020 09:32:38 +0200 + +libdrm (2.4.103-1) unstable; urgency=medium + + * New upstream release. (Closes: #970304) + * control, rules, hurd-port.diff: Add support for Hurd. (Closes: + #909436) + + -- Timo Aaltonen Tue, 10 Nov 2020 19:51:20 +0200 libdrm (2.4.102-1) unstable; urgency=medium diff -Nru libdrm-2.4.102/debian/control libdrm-2.4.105/debian/control --- libdrm-2.4.102/debian/control 2020-08-27 08:47:23.000000000 +0000 +++ libdrm-2.4.105/debian/control 2021-05-08 19:51:34.000000000 +0000 @@ -7,12 +7,12 @@ meson, quilt, xsltproc, - docbook-xsl, libx11-dev, pkg-config, xutils-dev (>= 1:7.6+2), libudev-dev [linux-any], libpciaccess-dev, + python3-docutils, valgrind [amd64 armhf i386 mips mipsel powerpc s390x], Standards-Version: 4.5.0 Section: libs @@ -22,10 +22,10 @@ Package: libdrm-dev Section: libdevel -Architecture: linux-any kfreebsd-any +Architecture: linux-any kfreebsd-any hurd-any Depends: libdrm2 (= ${binary:Version}), - libdrm-intel1 (= ${binary:Version}) [amd64 i386 kfreebsd-amd64 kfreebsd-i386 x32], + libdrm-intel1 (= ${binary:Version}) [amd64 i386 kfreebsd-amd64 kfreebsd-i386 hurd-i386 x32], libdrm-radeon1 (= ${binary:Version}), libdrm-nouveau2 (= ${binary:Version}) [linux-any], libdrm-amdgpu1 (= ${binary:Version}), @@ -46,7 +46,7 @@ This package provides the development environment for libdrm. Package: libdrm2 -Architecture: linux-any kfreebsd-any +Architecture: linux-any kfreebsd-any hurd-any Depends: libdrm-common (>= ${source:Version}), ${shlibs:Depends}, @@ -95,7 +95,7 @@ Package: libdrm2-udeb Package-Type: udeb Section: debian-installer -Architecture: linux-any kfreebsd-any +Architecture: linux-any kfreebsd-any hurd-any Depends: ${shlibs:Depends}, ${misc:Depends}, @@ -103,7 +103,7 @@ This is a udeb, or a microdeb, for the debian-installer. Package: libdrm-intel1 -Architecture: amd64 i386 kfreebsd-amd64 kfreebsd-i386 x32 +Architecture: amd64 i386 kfreebsd-amd64 kfreebsd-i386 hurd-i386 x32 Depends: ${shlibs:Depends}, ${misc:Depends}, @@ -130,7 +130,7 @@ OpenGL drivers. Package: libdrm-radeon1 -Architecture: linux-any kfreebsd-any +Architecture: linux-any kfreebsd-any hurd-any Depends: ${shlibs:Depends}, ${misc:Depends}, @@ -200,7 +200,7 @@ OpenGL drivers. Package: libdrm-amdgpu1 -Architecture: linux-any kfreebsd-any +Architecture: linux-any kfreebsd-any hurd-any Depends: ${shlibs:Depends}, ${misc:Depends}, diff -Nru libdrm-2.4.102/debian/libdrm2.symbols libdrm-2.4.105/debian/libdrm2.symbols --- libdrm-2.4.102/debian/libdrm2.symbols 2020-08-27 08:47:23.000000000 +0000 +++ libdrm-2.4.105/debian/libdrm2.symbols 2021-04-26 16:32:49.000000000 +0000 @@ -84,6 +84,7 @@ drmHashLookup@Base 2.3.1 drmHashNext@Base 2.3.1 drmIoctl@Base 2.4.3 + drmIsKMS@Base 2.4.105 drmIsMaster@Base 2.4.99 drmMalloc@Base 2.3.1 drmMap@Base 2.3.1 diff -Nru libdrm-2.4.102/debian/libdrm-amdgpu1.symbols libdrm-2.4.105/debian/libdrm-amdgpu1.symbols --- libdrm-2.4.102/debian/libdrm-amdgpu1.symbols 2020-08-27 08:47:23.000000000 +0000 +++ libdrm-2.4.105/debian/libdrm-amdgpu1.symbols 2021-04-26 16:32:49.000000000 +0000 @@ -67,6 +67,7 @@ amdgpu_query_info@Base 2.4.63 amdgpu_query_sensor_info@Base 2.4.80 amdgpu_query_sw_info@Base 2.4.90 + amdgpu_query_video_caps_info@Base 2.4.105 amdgpu_read_mm_registers@Base 2.4.63 amdgpu_va_range_alloc@Base 2.4.63 amdgpu_va_range_free@Base 2.4.63 diff -Nru libdrm-2.4.102/debian/patches/i915-rkl-1.diff libdrm-2.4.105/debian/patches/i915-rkl-1.diff --- libdrm-2.4.102/debian/patches/i915-rkl-1.diff 2020-08-27 09:39:29.000000000 +0000 +++ libdrm-2.4.105/debian/patches/i915-rkl-1.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,43 +0,0 @@ -commit 669e1087ab60637744ae0f3f15b8c1608d2a8653 -Author: José Roberto de Souza -Date: Wed Jul 8 10:44:53 2020 -0700 - - intel: sync i915_pciids.h with kernel - - Two new patches landed in kernel adding new PCI ids: - 123f62de419f ("drm/i915/rkl: Add RKL platform info and PCI ids") - 52797a8e8529 ("drm/i915/ehl: Add new PCI ids") - - Cc: Matt Roper - Signed-off-by: José Roberto de Souza - -diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h -index 662d8351..d6cb2899 100644 ---- a/intel/i915_pciids.h -+++ b/intel/i915_pciids.h -@@ -588,7 +588,11 @@ - INTEL_VGA_DEVICE(0x4551, info), \ - INTEL_VGA_DEVICE(0x4541, info), \ - INTEL_VGA_DEVICE(0x4E71, info), \ -+ INTEL_VGA_DEVICE(0x4557, info), \ -+ INTEL_VGA_DEVICE(0x4555, info), \ - INTEL_VGA_DEVICE(0x4E61, info), \ -+ INTEL_VGA_DEVICE(0x4E57, info), \ -+ INTEL_VGA_DEVICE(0x4E55, info), \ - INTEL_VGA_DEVICE(0x4E51, info) - - /* TGL */ -@@ -605,4 +609,13 @@ - INTEL_VGA_DEVICE(0x9AD9, info), \ - INTEL_VGA_DEVICE(0x9AF8, info) - -+/* RKL */ -+#define INTEL_RKL_IDS(info) \ -+ INTEL_VGA_DEVICE(0x4C80, info), \ -+ INTEL_VGA_DEVICE(0x4C8A, info), \ -+ INTEL_VGA_DEVICE(0x4C8B, info), \ -+ INTEL_VGA_DEVICE(0x4C8C, info), \ -+ INTEL_VGA_DEVICE(0x4C90, info), \ -+ INTEL_VGA_DEVICE(0x4C9A, info) -+ - #endif /* _I915_PCIIDS_H */ diff -Nru libdrm-2.4.102/debian/patches/i915-rkl-2.diff libdrm-2.4.105/debian/patches/i915-rkl-2.diff --- libdrm-2.4.102/debian/patches/i915-rkl-2.diff 2020-08-27 09:39:29.000000000 +0000 +++ libdrm-2.4.105/debian/patches/i915-rkl-2.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,26 +0,0 @@ -commit a84caff71be99989858c42b275faf4720b41ab84 -Author: sunil kumar dora sermsity -Date: Fri Aug 21 20:02:53 2020 +0000 - - intel: Add PCI ID support to RKL platform - - Missing RKL PCI ID preventing below test cases to succeed on RKL Platform. - igt@kms_frontbuffer_tracking - igt@kms_draw-crc - igt@kms_big_fb - - Signed-off-by: sunil kumar dora sermsity - Reviewed-by: Matt Roper - -diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c -index f6e37ee7..c3ce8f51 100644 ---- a/intel/intel_chipset.c -+++ b/intel/intel_chipset.c -@@ -35,6 +35,7 @@ static const struct pci_device { - uint16_t gen; - } pciids[] = { - /* Keep ids sorted by gen; latest gen first */ -+ INTEL_RKL_IDS(12), - INTEL_TGL_12_IDS(12), - INTEL_EHL_IDS(11), - INTEL_ICL_11_IDS(11), diff -Nru libdrm-2.4.102/debian/patches/Revert-meson-use-library-instead-of-shared_library.patch libdrm-2.4.105/debian/patches/Revert-meson-use-library-instead-of-shared_library.patch --- libdrm-2.4.102/debian/patches/Revert-meson-use-library-instead-of-shared_library.patch 1970-01-01 00:00:00.000000000 +0000 +++ libdrm-2.4.105/debian/patches/Revert-meson-use-library-instead-of-shared_library.patch 2021-05-19 08:09:05.000000000 +0000 @@ -0,0 +1,166 @@ +From f91aa47da756f020f02ce8db7dfc08aa52039d2b Mon Sep 17 00:00:00 2001 +From: Timo Aaltonen +Date: Sat, 8 May 2021 22:42:51 +0300 +Subject: [PATCH] Revert "meson: use library() instead of shared_library()." + +This reverts commit 52f05d3d896480ee5431dcd444f53bb2a8e41cce. +--- + amdgpu/meson.build | 2 +- + etnaviv/meson.build | 2 +- + exynos/meson.build | 2 +- + freedreno/meson.build | 2 +- + intel/meson.build | 2 +- + libkms/meson.build | 2 +- + meson.build | 2 +- + nouveau/meson.build | 2 +- + omap/meson.build | 2 +- + radeon/meson.build | 2 +- + tegra/meson.build | 2 +- + 11 files changed, 11 insertions(+), 11 deletions(-) + +diff --git a/amdgpu/meson.build b/amdgpu/meson.build +index 3301a10e..d5c5f397 100644 +--- a/amdgpu/meson.build ++++ b/amdgpu/meson.build +@@ -21,7 +21,7 @@ + + datadir_amdgpu = join_paths(get_option('prefix'), get_option('datadir'), 'libdrm') + +-libdrm_amdgpu = library( ++libdrm_amdgpu = shared_library( + 'drm_amdgpu', + [ + files( +diff --git a/etnaviv/meson.build b/etnaviv/meson.build +index 8b82ed07..6040cf63 100644 +--- a/etnaviv/meson.build ++++ b/etnaviv/meson.build +@@ -19,7 +19,7 @@ + # SOFTWARE. + + +-libdrm_etnaviv = library( ++libdrm_etnaviv = shared_library( + 'drm_etnaviv', + [ + files( +diff --git a/exynos/meson.build b/exynos/meson.build +index 7d1edfea..40d66fc1 100644 +--- a/exynos/meson.build ++++ b/exynos/meson.build +@@ -18,7 +18,7 @@ + # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + # SOFTWARE. + +-libdrm_exynos = library( ++libdrm_exynos = shared_library( + 'drm_exynos', + [files('exynos_drm.c', 'exynos_fimg2d.c'), config_file], + c_args : libdrm_c_args, +diff --git a/freedreno/meson.build b/freedreno/meson.build +index 49e66593..63b84fc9 100644 +--- a/freedreno/meson.build ++++ b/freedreno/meson.build +@@ -39,7 +39,7 @@ if with_freedreno_kgsl + ) + endif + +-libdrm_freedreno = library( ++libdrm_freedreno = shared_library( + 'drm_freedreno', + [files_freedreno, config_file], + c_args : libdrm_c_args, +diff --git a/intel/meson.build b/intel/meson.build +index 5fa06c28..4d3f1ebd 100644 +--- a/intel/meson.build ++++ b/intel/meson.build +@@ -18,7 +18,7 @@ + # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + # SOFTWARE. + +-libdrm_intel = library( ++libdrm_intel = shared_library( + 'drm_intel', + [ + files( +diff --git a/libkms/meson.build b/libkms/meson.build +index 8d17bb2e..216be4df 100644 +--- a/libkms/meson.build ++++ b/libkms/meson.build +@@ -41,7 +41,7 @@ if with_exynos + libkms_include += include_directories('../exynos') + endif + +-libkms = library( ++libkms = shared_library( + 'kms', + [files_libkms, config_file], + c_args : libdrm_c_args, +diff --git a/meson.build b/meson.build +index 30f1c2e5..36d48ce0 100644 +--- a/meson.build ++++ b/meson.build +@@ -294,7 +294,7 @@ add_project_arguments('-include', '@0@'.format(config_file), language : 'c') + inc_root = include_directories('.') + inc_drm = include_directories('include/drm') + +-libdrm = library( ++libdrm = shared_library( + 'drm', + [files( + 'xf86drm.c', 'xf86drmHash.c', 'xf86drmRandom.c', 'xf86drmSL.c', +diff --git a/nouveau/meson.build b/nouveau/meson.build +index af45336c..9bd58fca 100644 +--- a/nouveau/meson.build ++++ b/nouveau/meson.build +@@ -19,7 +19,7 @@ + # SOFTWARE. + + +-libdrm_nouveau = library( ++libdrm_nouveau = shared_library( + 'drm_nouveau', + [files( 'nouveau.c', 'pushbuf.c', 'bufctx.c', 'abi16.c'), config_file], + c_args : libdrm_c_args, +diff --git a/omap/meson.build b/omap/meson.build +index bfd59f05..53330b61 100644 +--- a/omap/meson.build ++++ b/omap/meson.build +@@ -18,7 +18,7 @@ + # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + # SOFTWARE. + +-libdrm_omap = library( ++libdrm_omap = shared_library( + 'drm_omap', + [files('omap_drm.c'), config_file], + include_directories : [inc_root, inc_drm], +diff --git a/radeon/meson.build b/radeon/meson.build +index 31fe9cd0..ca128329 100644 +--- a/radeon/meson.build ++++ b/radeon/meson.build +@@ -19,7 +19,7 @@ + # SOFTWARE. + + +-libdrm_radeon = library( ++libdrm_radeon = shared_library( + 'drm_radeon', + [ + files( +diff --git a/tegra/meson.build b/tegra/meson.build +index edddf72b..88613b9c 100644 +--- a/tegra/meson.build ++++ b/tegra/meson.build +@@ -18,7 +18,7 @@ + # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + # SOFTWARE. + +-libdrm_tegra = library( ++libdrm_tegra = shared_library( + 'drm_tegra', + [files('tegra.c'), config_file], + include_directories : [inc_root, inc_drm], +-- +2.30.2 + diff -Nru libdrm-2.4.102/debian/patches/revert-set-fb-modifiers-flag.diff libdrm-2.4.105/debian/patches/revert-set-fb-modifiers-flag.diff --- libdrm-2.4.102/debian/patches/revert-set-fb-modifiers-flag.diff 1970-01-01 00:00:00.000000000 +0000 +++ libdrm-2.4.105/debian/patches/revert-set-fb-modifiers-flag.diff 2021-05-19 08:09:05.000000000 +0000 @@ -0,0 +1,29 @@ +commit 40f73d0b0b3936ccadc693edc25aad70c1225766 +Author: Bas Nieuwenhuizen +Date: Wed Apr 21 21:31:06 2021 +0200 + + Revert "xf86drmMode: set FB_MODIFIERS flag when modifiers are supplied" + + This reverts commit b362850689d1b0048b7f4641cc236128b5a43773. + + This breaks when the kernel driver does not support modifiers and the + application properly zeroes the modifiers. + + Acked-by: Simon Ser + +diff --git a/xf86drmMode.c b/xf86drmMode.c +index dc177241..c3920b91 100644 +--- a/xf86drmMode.c ++++ b/xf86drmMode.c +@@ -289,10 +289,8 @@ drm_public int drmModeAddFB2WithModifiers(int fd, uint32_t width, + memcpy(f.handles, bo_handles, 4 * sizeof(bo_handles[0])); + memcpy(f.pitches, pitches, 4 * sizeof(pitches[0])); + memcpy(f.offsets, offsets, 4 * sizeof(offsets[0])); +- if (modifier) { +- f.flags |= DRM_MODE_FB_MODIFIERS; ++ if (modifier) + memcpy(f.modifier, modifier, 4 * sizeof(modifier[0])); +- } + + if ((ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_ADDFB2, &f))) + return ret; diff -Nru libdrm-2.4.102/debian/patches/series libdrm-2.4.105/debian/patches/series --- libdrm-2.4.102/debian/patches/series 2020-08-27 09:39:29.000000000 +0000 +++ libdrm-2.4.105/debian/patches/series 2021-05-19 08:09:05.000000000 +0000 @@ -1,3 +1,3 @@ 01_default_perms.diff -i915-rkl-1.diff -i915-rkl-2.diff +revert-set-fb-modifiers-flag.diff +Revert-meson-use-library-instead-of-shared_library.patch diff -Nru libdrm-2.4.102/debian/rules libdrm-2.4.105/debian/rules --- libdrm-2.4.102/debian/rules 2020-08-27 08:46:51.000000000 +0000 +++ libdrm-2.4.105/debian/rules 2021-04-26 16:32:49.000000000 +0000 @@ -31,7 +31,7 @@ # Intel is only on x86: ifneq (,$(filter amd64 i386,$(DEB_HOST_ARCH_CPU))) -ifneq (,$(filter linux kfreebsd,$(DEB_HOST_ARCH_OS))) +ifneq (,$(filter linux kfreebsd hurd,$(DEB_HOST_ARCH_OS))) INTEL = yes endif endif diff -Nru libdrm-2.4.102/debian/upstream/signing-key.asc libdrm-2.4.105/debian/upstream/signing-key.asc --- libdrm-2.4.102/debian/upstream/signing-key.asc 2020-08-27 08:47:23.000000000 +0000 +++ libdrm-2.4.105/debian/upstream/signing-key.asc 2021-04-26 16:32:49.000000000 +0000 @@ -773,3 +773,82 @@ wNccR+xcxTdj6e9FqhfeCHZC2kSBFtvfNcXBnnpGNDZSUVM= =ssHY -----END PGP PUBLIC KEY BLOCK----- +-----BEGIN PGP PUBLIC KEY BLOCK----- + +mQINBFb+7ZIBEADKchyt5QILvWeM/fi5Jf9SQ+2f4ltU7DVtC9Y2pWrG/Bua6Yoc +wWMEo/XeT7yu/4cMDTH2aRR+9mSir3sVTIjfX+Pnfxdds3/zKZgrMrK0jvBRoWxi +RTIkFw0L7FqEj0D1LkzXqysLQshRn11AbijoYPaqksr9g6Zk1RgA1p/51mEMLL9v +AOULKbRoxhTNcfQQwnzhNRygocOJ3QF4ZyVUBkxOfxun7aZQz0OfW8YskincoUGk +piaQH08VPU6aZQsA8g2xEZLOTAGE9O7ffkDlCH40jp7KmRwutnXiJpGNN4dzUtHg +R/7LGqQJgxpf0FboM/TATRCEPTfPOkzEGaw6j3q9FN2+OVz4yxFR1FlVr6Klcua1 +jxNWXQ2MmhrArUmNN8mcLKKSLc+deURgX8IsCEi66lmV74YBc2MXr2XfIgOyzimc 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20:37:16.000000000 +0000 +++ libdrm-2.4.105/exynos/meson.build 2021-04-07 14:09:24.163843400 +0000 @@ -18,7 +18,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -libdrm_exynos = shared_library( +libdrm_exynos = library( 'drm_exynos', [files('exynos_drm.c', 'exynos_fimg2d.c'), config_file], c_args : libdrm_c_args, diff -Nru libdrm-2.4.102/freedreno/meson.build libdrm-2.4.105/freedreno/meson.build --- libdrm-2.4.102/freedreno/meson.build 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/freedreno/meson.build 2021-04-07 14:09:24.167843300 +0000 @@ -39,7 +39,7 @@ ) endif -libdrm_freedreno = shared_library( +libdrm_freedreno = library( 'drm_freedreno', [files_freedreno, config_file], c_args : libdrm_c_args, diff -Nru libdrm-2.4.102/include/drm/amdgpu_drm.h libdrm-2.4.105/include/drm/amdgpu_drm.h --- libdrm-2.4.102/include/drm/amdgpu_drm.h 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/include/drm/amdgpu_drm.h 2021-04-07 14:09:24.167843300 +0000 @@ -125,13 +125,19 @@ /* Flag that BO sharing will be explicitly synchronized */ #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) /* Flag that indicates allocating MQD gart on GFX9, where the mtype - * for the second page onward should be set to NC. + * for the second page onward should be set to NC. It should never + * be used by user space applications. */ -#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) +#define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) /* Flag that BO may contain sensitive data that must be wiped before * releasing the memory */ #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) +/* Flag that BO will be encrypted and that the TMZ bit should be + * set in the PTEs when mapping this buffer via GPUVM or + * accessing it with various hw blocks + */ +#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) struct drm_amdgpu_gem_create_in { /** the requested memory size */ @@ -345,6 +351,10 @@ #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 +#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 +#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 +#define AMDGPU_TILING_SCANOUT_SHIFT 63 +#define AMDGPU_TILING_SCANOUT_MASK 0x1 /* Set/Get helpers for tiling flags. */ #define AMDGPU_TILING_SET(field, value) \ @@ -492,14 +502,16 @@ #define AMDGPU_VM_MTYPE_MASK (0xf << 5) /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) -/* Use NC MTYPE instead of default MTYPE */ +/* Use Non Coherent MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_NC (1 << 5) -/* Use WC MTYPE instead of default MTYPE */ +/* Use Write Combine MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_WC (2 << 5) -/* Use CC MTYPE instead of default MTYPE */ +/* Use Cache Coherent MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_CC (3 << 5) -/* Use UC MTYPE instead of default MTYPE */ +/* Use UnCached MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_UC (4 << 5) +/* Use Read Write MTYPE instead of default MTYPE */ +#define AMDGPU_VM_MTYPE_RW (5 << 5) struct drm_amdgpu_gem_va { /** GEM object handle */ @@ -552,7 +564,7 @@ /** Handle of resource list associated with CS */ __u32 bo_list_handle; __u32 num_chunks; - __u32 _pad; + __u32 flags; /** this points to __u64 * which point to cs chunks */ __u64 chunks; }; @@ -586,6 +598,14 @@ */ #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) +/* Flag the IB as secure (TMZ) + */ +#define AMDGPU_IB_FLAGS_SECURE (1 << 5) + +/* Tell KMD to flush and invalidate caches + */ +#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) + struct drm_amdgpu_cs_chunk_ib { __u32 _pad; /** AMDGPU_IB_FLAG_* */ @@ -647,12 +667,13 @@ }; }; -/** +/* * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU * */ #define AMDGPU_IDS_FLAGS_FUSION 0x1 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 +#define AMDGPU_IDS_FLAGS_TMZ 0x4 /* indicate if acceleration can be working */ #define AMDGPU_INFO_ACCEL_WORKING 0x00 @@ -701,6 +722,11 @@ /* Subquery id: Query DMCU firmware version */ #define AMDGPU_INFO_FW_DMCU 0x12 #define AMDGPU_INFO_FW_TA 0x13 + /* Subquery id: Query DMCUB firmware version */ + #define AMDGPU_INFO_FW_DMCUB 0x14 + /* Subquery id: Query TOC firmware version */ + #define AMDGPU_INFO_FW_TOC 0x15 + /* number of bytes moved for TTM migration */ #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f /* the used VRAM size */ @@ -756,6 +782,12 @@ #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F /* query ras mask of enabled features*/ #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 +/* query video encode/decode caps */ +#define AMDGPU_INFO_VIDEO_CAPS 0x21 + /* Subquery id: Decode */ + #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 + /* Subquery id: Encode */ + #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 /* RAS MASK: UMC (VRAM) */ #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) @@ -852,6 +884,10 @@ struct { __u32 type; } sensor_info; + + struct { + __u32 type; + } video_cap; }; }; @@ -922,6 +958,7 @@ #define AMDGPU_VRAM_TYPE_DDR3 7 #define AMDGPU_VRAM_TYPE_DDR4 8 #define AMDGPU_VRAM_TYPE_GDDR6 9 +#define AMDGPU_VRAM_TYPE_DDR5 10 struct drm_amdgpu_info_device { /** PCI Device ID */ @@ -1047,6 +1084,30 @@ __u32 pad; }; +/* query video encode/decode caps */ +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 + +struct drm_amdgpu_info_video_codec_info { + __u32 valid; + __u32 max_width; + __u32 max_height; + __u32 max_pixels_per_frame; + __u32 max_level; + __u32 pad; +}; + +struct drm_amdgpu_info_video_caps { + struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; +}; + /* * Supported GPU families */ @@ -1059,6 +1120,7 @@ #define AMDGPU_FAMILY_AI 141 /* Vega10 */ #define AMDGPU_FAMILY_RV 142 /* Raven */ #define AMDGPU_FAMILY_NV 143 /* Navi10 */ +#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ #if defined(__cplusplus) } diff -Nru libdrm-2.4.102/include/drm/drm_fourcc.h libdrm-2.4.105/include/drm/drm_fourcc.h --- libdrm-2.4.102/include/drm/drm_fourcc.h 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/include/drm/drm_fourcc.h 2021-04-07 14:09:24.167843300 +0000 @@ -58,6 +58,30 @@ * may preserve meaning - such as number of planes - from the fourcc code, * whereas others may not. * + * Modifiers must uniquely encode buffer layout. In other words, a buffer must + * match only a single modifier. A modifier must not be a subset of layouts of + * another modifier. For instance, it's incorrect to encode pitch alignment in + * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel + * aligned modifier. That said, modifiers can have implicit minimal + * requirements. + * + * For modifiers where the combination of fourcc code and modifier can alias, + * a canonical pair needs to be defined and used by all drivers. Preferred + * combinations are also encouraged where all combinations might lead to + * confusion and unnecessarily reduced interoperability. An example for the + * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. + * + * There are two kinds of modifier users: + * + * - Kernel and user-space drivers: for drivers it's important that modifiers + * don't alias, otherwise two drivers might support the same format but use + * different aliases, preventing them from sharing buffers in an efficient + * format. + * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users + * see modifiers as opaque tokens they can check for equality and intersect. + * These users musn't need to know to reason about the modifier value + * (i.e. they are not expected to extract information out of the modifier). + * * Vendors should document their modifier usage in as much detail as * possible, to ensure maximum compatibility across devices, drivers and * applications. @@ -69,7 +93,7 @@ #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ ((__u32)(c) << 16) | ((__u32)(d) << 24)) -#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ +#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ /* Reserve 0 for the invalid format specifier */ #define DRM_FORMAT_INVALID 0 @@ -155,6 +179,12 @@ #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +/* + * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits + * of unused padding per component: + */ +#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ + /* packed YCbCr */ #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ @@ -236,6 +266,12 @@ #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ +/* + * 2 plane YCbCr + * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian + * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian + */ +#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ /* * 2 plane YCbCr MSB aligned @@ -265,6 +301,22 @@ */ #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ +/* 3 plane non-subsampled (444) YCbCr + * 16 bits per component, but only 10 bits are used and 6 bits are padded + * index 0: Y plane, [15:0] Y:x [10:6] little endian + * index 1: Cb plane, [15:0] Cb:x [10:6] little endian + * index 2: Cr plane, [15:0] Cr:x [10:6] little endian + */ +#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') + +/* 3 plane non-subsampled (444) YCrCb + * 16 bits per component, but only 10 bits are used and 6 bits are padded + * index 0: Y plane, [15:0] Y:x [10:6] little endian + * index 1: Cr plane, [15:0] Cr:x [10:6] little endian + * index 2: Cb plane, [15:0] Cb:x [10:6] little endian + */ +#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') + /* * 3 plane YCbCr * index 0: Y plane, [7:0] Y @@ -298,7 +350,6 @@ */ /* Vendor Ids: */ -#define DRM_FORMAT_MOD_NONE 0 #define DRM_FORMAT_MOD_VENDOR_NONE 0 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 @@ -309,6 +360,7 @@ #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 +#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a /* add more to the end as needed */ @@ -323,8 +375,33 @@ * When adding a new token please document the layout with a code comment, * similar to the fourcc codes above. drm_fourcc.h is considered the * authoritative source for all of these. + * + * Generic modifier names: + * + * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names + * for layouts which are common across multiple vendors. To preserve + * compatibility, in cases where a vendor-specific definition already exists and + * a generic name for it is desired, the common name is a purely symbolic alias + * and must use the same numerical value as the original definition. + * + * Note that generic names should only be used for modifiers which describe + * generic layouts (such as pixel re-ordering), which may have + * independently-developed support across multiple vendors. + * + * In future cases where a generic layout is identified before merging with a + * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor + * 'NONE' could be considered. This should only be for obvious, exceptional + * cases to avoid polluting the 'GENERIC' namespace with modifiers which only + * apply to a single vendor. + * + * Generic names should not be used for cases where multiple hardware vendors + * have implementations of the same standardised compression scheme (such as + * AFBC). In those cases, all implementations should use the same format + * modifier(s), reflecting the vendor of the standard. */ +#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE + /* * Invalid Modifier * @@ -344,6 +421,16 @@ */ #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) +/* + * Deprecated: use DRM_FORMAT_MOD_LINEAR instead + * + * The "none" format modifier doesn't actually mean that the modifier is + * implicit, instead it means that the layout is linear. Whether modifiers are + * used is out-of-band information carried in an API-specific way (e.g. in a + * flag for drm_mode_fb_cmd2). + */ +#define DRM_FORMAT_MOD_NONE 0 + /* Intel framebuffer modifiers */ /* @@ -354,9 +441,12 @@ * a platform-dependent stride. On top of that the memory can apply * platform-depending swizzling of some higher address bits into bit6. * - * This format is highly platforms specific and not useful for cross-driver - * sharing. It exists since on a given platform it does uniquely identify the - * layout in a simple way for i915-specific userspace. + * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. + * On earlier platforms the is highly platforms specific and not useful for + * cross-driver sharing. It exists since on a given platform it does uniquely + * identify the layout in a simple way for i915-specific userspace, which + * facilitated conversion of userspace to modifiers. Additionally the exact + * format on some really old platforms is not known. */ #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) @@ -369,9 +459,12 @@ * memory can apply platform-depending swizzling of some higher address bits * into bit6. * - * This format is highly platforms specific and not useful for cross-driver - * sharing. It exists since on a given platform it does uniquely identify the - * layout in a simple way for i915-specific userspace. + * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. + * On earlier platforms the is highly platforms specific and not useful for + * cross-driver sharing. It exists since on a given platform it does uniquely + * identify the layout in a simple way for i915-specific userspace, which + * facilitated conversion of userspace to modifiers. Additionally the exact + * format on some really old platforms is not known. */ #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) @@ -411,6 +504,30 @@ #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) /* + * Intel color control surfaces (CCS) for Gen-12 render compression. + * + * The main surface is Y-tiled and at plane index 0, the CCS is linear and + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in + * main surface. In other words, 4 bits in CCS map to a main surface cache + * line pair. The main surface pitch is required to be a multiple of four + * Y-tile widths. + */ +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) + +/* + * Intel color control surfaces (CCS) for Gen-12 media compression + * + * The main surface is Y-tiled and at plane index 0, the CCS is linear and + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in + * main surface. In other words, 4 bits in CCS map to a main surface cache + * line pair. The main surface pitch is required to be a multiple of four + * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the + * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, + * planes 2 and 3 for the respective CCS. + */ +#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) + +/* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * * Macroblocks are laid in a Z-shape, and each pixel data is following the @@ -497,7 +614,113 @@ #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) /* - * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later + * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, + * and Tegra GPUs starting with Tegra K1. + * + * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies + * based on the architecture generation. GOBs themselves are then arranged in + * 3D blocks, with the block dimensions (in terms of GOBs) always being a power + * of two, and hence expressible as their log2 equivalent (E.g., "2" represents + * a block depth or height of "4"). + * + * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format + * in full detail. + * + * Macro + * Bits Param Description + * ---- ----- ----------------------------------------------------------------- + * + * 3:0 h log2(height) of each block, in GOBs. Placed here for + * compatibility with the existing + * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. + * + * 4:4 - Must be 1, to indicate block-linear layout. Necessary for + * compatibility with the existing + * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. + * + * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block + * size). Must be zero. + * + * Note there is no log2(width) parameter. Some portions of the + * hardware support a block width of two gobs, but it is impractical + * to use due to lack of support elsewhere, and has no known + * benefits. + * + * 11:9 - Reserved (To support 2D-array textures with variable array stride + * in blocks, specified via log2(tile width in blocks)). Must be + * zero. + * + * 19:12 k Page Kind. This value directly maps to a field in the page + * tables of all GPUs >= NV50. It affects the exact layout of bits + * in memory and can be derived from the tuple + * + * (format, GPU model, compression type, samples per pixel) + * + * Where compression type is defined below. If GPU model were + * implied by the format modifier, format, or memory buffer, page + * kind would not need to be included in the modifier itself, but + * since the modifier should define the layout of the associated + * memory buffer independent from any device or other context, it + * must be included here. + * + * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed + * starting with Fermi GPUs. Additionally, the mapping between page + * kind and bit layout has changed at various points. + * + * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping + * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping + * 2 = Gob Height 8, Turing+ Page Kind mapping + * 3 = Reserved for future use. + * + * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further + * bit remapping step that occurs at an even lower level than the + * page kind and block linear swizzles. This causes the layout of + * surfaces mapped in those SOC's GPUs to be incompatible with the + * equivalent mapping on other GPUs in the same system. + * + * 0 = Tegra K1 - Tegra Parker/TX2 Layout. + * 1 = Desktop GPU and Tegra Xavier+ Layout + * + * 25:23 c Lossless Framebuffer Compression type. + * + * 0 = none + * 1 = ROP/3D, layout 1, exact compression format implied by Page + * Kind field + * 2 = ROP/3D, layout 2, exact compression format implied by Page + * Kind field + * 3 = CDE horizontal + * 4 = CDE vertical + * 5 = Reserved for future use + * 6 = Reserved for future use + * 7 = Reserved for future use + * + * 55:25 - Reserved for future use. Must be zero. + */ +#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ + fourcc_mod_code(NVIDIA, (0x10 | \ + ((h) & 0xf) | \ + (((k) & 0xff) << 12) | \ + (((g) & 0x3) << 20) | \ + (((s) & 0x1) << 22) | \ + (((c) & 0x7) << 23))) + +/* To grandfather in prior block linear format modifiers to the above layout, + * the page kind "0", which corresponds to "pitch/linear" and hence is unusable + * with block-linear layouts, is remapped within drivers to the value 0xfe, + * which corresponds to the "generic" kind used for simple single-sample + * uncompressed color formats on Fermi - Volta GPUs. + */ +static __inline__ __u64 +drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) +{ + if (!(modifier & 0x10) || (modifier & (0xff << 12))) + return modifier; + else + return modifier | (0xfe << 12); +} + +/* + * 16Bx2 Block Linear layout, used by Tegra K1 and later * * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked * vertically by a power of 2 (1 to 32 GOBs) to form a block. @@ -518,20 +741,20 @@ * in full detail. */ #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ - fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ - fourcc_mod_code(NVIDIA, 0x10) + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ - fourcc_mod_code(NVIDIA, 0x11) + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ - fourcc_mod_code(NVIDIA, 0x12) + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ - fourcc_mod_code(NVIDIA, 0x13) + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ - fourcc_mod_code(NVIDIA, 0x14) + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ - fourcc_mod_code(NVIDIA, 0x15) + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) /* * Some Broadcom modifiers take parameters, for example the number of @@ -648,7 +871,21 @@ * Further information on the use of AFBC modifiers can be found in * Documentation/gpu/afbc.rst */ -#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode) + +/* + * The top 4 bits (out of the 56 bits alloted for specifying vendor specific + * modifiers) denote the category for modifiers. Currently we have only two + * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen + * different categories. + */ +#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ + fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) + +#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 +#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 + +#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) /* * AFBC superblock size @@ -742,6 +979,28 @@ */ #define AFBC_FORMAT_MOD_BCH (1ULL << 11) +/* AFBC uncompressed storage mode + * + * Indicates that the buffer is using AFBC uncompressed storage mode. + * In this mode all superblock payloads in the buffer use the uncompressed + * storage mode, which is usually only used for data which cannot be compressed. + * The buffer layout is the same as for AFBC buffers without USM set, this only + * affects the storage mode of the individual superblocks. Note that even a + * buffer without USM set may use uncompressed storage mode for some or all + * superblocks, USM just guarantees it for all. + */ +#define AFBC_FORMAT_MOD_USM (1ULL << 12) + +/* + * Arm 16x16 Block U-Interleaved modifier + * + * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image + * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels + * in the block are reordered. + */ +#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) + /* * Allwinner tiled modifier * @@ -756,6 +1015,220 @@ */ #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) +/* + * Amlogic Video Framebuffer Compression modifiers + * + * Amlogic uses a proprietary lossless image compression protocol and format + * for their hardware video codec accelerators, either video decoders or + * video input encoders. + * + * It considerably reduces memory bandwidth while writing and reading + * frames in memory. + * + * The underlying storage is considered to be 3 components, 8bit or 10-bit + * per component YCbCr 420, single plane : + * - DRM_FORMAT_YUV420_8BIT + * - DRM_FORMAT_YUV420_10BIT + * + * The first 8 bits of the mode defines the layout, then the following 8 bits + * defines the options changing the layout. + * + * Not all combinations are valid, and different SoCs may support different + * combinations of layout and options. + */ +#define __fourcc_mod_amlogic_layout_mask 0xf +#define __fourcc_mod_amlogic_options_shift 8 +#define __fourcc_mod_amlogic_options_mask 0xf + +#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ + fourcc_mod_code(AMLOGIC, \ + ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ + (((__options) & __fourcc_mod_amlogic_options_mask) \ + << __fourcc_mod_amlogic_options_shift)) + +/* Amlogic FBC Layouts */ + +/* + * Amlogic FBC Basic Layout + * + * The basic layout is composed of: + * - a body content organized in 64x32 superblocks with 4096 bytes per + * superblock in default mode. + * - a 32 bytes per 128x64 header block + * + * This layout is transferrable between Amlogic SoCs supporting this modifier. + */ +#define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) + +/* + * Amlogic FBC Scatter Memory layout + * + * Indicates the header contains IOMMU references to the compressed + * frames content to optimize memory access and layout. + * + * In this mode, only the header memory address is needed, thus the + * content memory organization is tied to the current producer + * execution and cannot be saved/dumped neither transferrable between + * Amlogic SoCs supporting this modifier. + * + * Due to the nature of the layout, these buffers are not expected to + * be accessible by the user-space clients, but only accessible by the + * hardware producers and consumers. + * + * The user-space clients should expect a failure while trying to mmap + * the DMA-BUF handle returned by the producer. + */ +#define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) + +/* Amlogic FBC Layout Options Bit Mask */ + +/* + * Amlogic FBC Memory Saving mode + * + * Indicates the storage is packed when pixel size is multiple of word + * boudaries, i.e. 8bit should be stored in this mode to save allocation + * memory. + * + * This mode reduces body layout to 3072 bytes per 64x32 superblock with + * the basic layout and 3200 bytes per 64x32 superblock combined with + * the scatter layout. + */ +#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) + +/* + * AMD modifiers + * + * Memory layout: + * + * without DCC: + * - main surface + * + * with DCC & without DCC_RETILE: + * - main surface in plane 0 + * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) + * + * with DCC & DCC_RETILE: + * - main surface in plane 0 + * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) + * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) + * + * For multi-plane formats the above surfaces get merged into one plane for + * each format plane, based on the required alignment only. + * + * Bits Parameter Notes + * ----- ------------------------ --------------------------------------------- + * + * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* + * 12:8 TILE Values are AMD_FMT_MOD_TILE__* + * 13 DCC + * 14 DCC_RETILE + * 15 DCC_PIPE_ALIGN + * 16 DCC_INDEPENDENT_64B + * 17 DCC_INDEPENDENT_128B + * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* + * 20 DCC_CONSTANT_ENCODE + * 23:21 PIPE_XOR_BITS Only for some chips + * 26:24 BANK_XOR_BITS Only for some chips + * 29:27 PACKERS Only for some chips + * 32:30 RB Only for some chips + * 35:33 PIPE Only for some chips + * 55:36 - Reserved for future use, must be zero + */ +#define AMD_FMT_MOD fourcc_mod_code(AMD, 0) + +#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) + +/* Reserve 0 for GFX8 and older */ +#define AMD_FMT_MOD_TILE_VER_GFX9 1 +#define AMD_FMT_MOD_TILE_VER_GFX10 2 +#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 + +/* + * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical + * version. + */ +#define AMD_FMT_MOD_TILE_GFX9_64K_S 9 + +/* + * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has + * GFX9 as canonical version. + */ +#define AMD_FMT_MOD_TILE_GFX9_64K_D 10 +#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 +#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 +#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 + +#define AMD_FMT_MOD_DCC_BLOCK_64B 0 +#define AMD_FMT_MOD_DCC_BLOCK_128B 1 +#define AMD_FMT_MOD_DCC_BLOCK_256B 2 + +#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 +#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF +#define AMD_FMT_MOD_TILE_SHIFT 8 +#define AMD_FMT_MOD_TILE_MASK 0x1F + +/* Whether DCC compression is enabled. */ +#define AMD_FMT_MOD_DCC_SHIFT 13 +#define AMD_FMT_MOD_DCC_MASK 0x1 + +/* + * Whether to include two DCC surfaces, one which is rb & pipe aligned, and + * one which is not-aligned. + */ +#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 +#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 + +/* Only set if DCC_RETILE = false */ +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 + +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 + +/* + * DCC supports embedding some clear colors directly in the DCC surface. + * However, on older GPUs the rendering HW ignores the embedded clear color + * and prefers the driver provided color. This necessitates doing a fastclear + * eliminate operation before a process transfers control. + * + * If this bit is set that means the fastclear eliminate is not needed for these + * embeddable colors. + */ +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 + +/* + * The below fields are for accounting for per GPU differences. These are only + * relevant for GFX9 and later and if the tile field is *_X/_T. + * + * PIPE_XOR_BITS = always needed + * BANK_XOR_BITS = only for TILE_VER_GFX9 + * PACKERS = only for TILE_VER_GFX10_RBPLUS + * RB = only for TILE_VER_GFX9 & DCC + * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) + */ +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 +#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 +#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 +#define AMD_FMT_MOD_PACKERS_SHIFT 27 +#define AMD_FMT_MOD_PACKERS_MASK 0x7 +#define AMD_FMT_MOD_RB_SHIFT 30 +#define AMD_FMT_MOD_RB_MASK 0x7 +#define AMD_FMT_MOD_PIPE_SHIFT 33 +#define AMD_FMT_MOD_PIPE_MASK 0x7 + +#define AMD_FMT_MOD_SET(field, value) \ + ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) +#define AMD_FMT_MOD_GET(field, value) \ + (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) +#define AMD_FMT_MOD_CLEAR(field) \ + (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) + #if defined(__cplusplus) } #endif diff -Nru libdrm-2.4.102/include/drm/drm_mode.h libdrm-2.4.105/include/drm/drm_mode.h --- libdrm-2.4.102/include/drm/drm_mode.h 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/include/drm/drm_mode.h 2021-04-07 14:09:24.167843300 +0000 @@ -33,6 +33,15 @@ extern "C" { #endif +/** + * DOC: overview + * + * DRM exposes many UAPI and structure definition to have a consistent + * and standardized interface with user. + * Userspace can refer to these structure definitions and UAPI formats + * to communicate to driver + */ + #define DRM_CONNECTOR_NAME_LEN 32 #define DRM_DISPLAY_MODE_LEN 32 #define DRM_PROP_NAME_LEN 32 @@ -323,14 +332,19 @@ /* This is for connectors with multiple signal types. */ /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ enum drm_mode_subconnector { - DRM_MODE_SUBCONNECTOR_Automatic = 0, - DRM_MODE_SUBCONNECTOR_Unknown = 0, - DRM_MODE_SUBCONNECTOR_DVID = 3, - DRM_MODE_SUBCONNECTOR_DVIA = 4, - DRM_MODE_SUBCONNECTOR_Composite = 5, - DRM_MODE_SUBCONNECTOR_SVIDEO = 6, - DRM_MODE_SUBCONNECTOR_Component = 8, - DRM_MODE_SUBCONNECTOR_SCART = 9, + DRM_MODE_SUBCONNECTOR_Automatic = 0, /* DVI-I, TV */ + DRM_MODE_SUBCONNECTOR_Unknown = 0, /* DVI-I, TV, DP */ + DRM_MODE_SUBCONNECTOR_VGA = 1, /* DP */ + DRM_MODE_SUBCONNECTOR_DVID = 3, /* DVI-I DP */ + DRM_MODE_SUBCONNECTOR_DVIA = 4, /* DVI-I */ + DRM_MODE_SUBCONNECTOR_Composite = 5, /* TV */ + DRM_MODE_SUBCONNECTOR_SVIDEO = 6, /* TV */ + DRM_MODE_SUBCONNECTOR_Component = 8, /* TV */ + DRM_MODE_SUBCONNECTOR_SCART = 9, /* TV */ + DRM_MODE_SUBCONNECTOR_DisplayPort = 10, /* DP */ + DRM_MODE_SUBCONNECTOR_HDMIA = 11, /* DP */ + DRM_MODE_SUBCONNECTOR_Native = 15, /* DP */ + DRM_MODE_SUBCONNECTOR_Wireless = 18, /* DP */ }; #define DRM_MODE_CONNECTOR_Unknown 0 @@ -352,6 +366,7 @@ #define DRM_MODE_CONNECTOR_DSI 16 #define DRM_MODE_CONNECTOR_DPI 17 #define DRM_MODE_CONNECTOR_WRITEBACK 18 +#define DRM_MODE_CONNECTOR_SPI 19 struct drm_mode_get_connector { @@ -487,7 +502,7 @@ * In case of planar formats, this ioctl allows up to 4 * buffer objects with offsets and pitches per plane. * The pitch and offset order is dictated by the fourcc, - * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: + * e.g. NV12 (https://fourcc.org/yuv.php#NV12) is described as: * * YUV 4:2:0 image with a plane of 8 bit Y samples * followed by an interleaved U/V plane containing @@ -630,6 +645,92 @@ __u16 reserved; }; +/** + * struct hdr_metadata_infoframe - HDR Metadata Infoframe Data. + * + * HDR Metadata Infoframe as per CTA 861.G spec. This is expected + * to match exactly with the spec. + * + * Userspace is expected to pass the metadata information as per + * the format described in this structure. + */ +struct hdr_metadata_infoframe { + /** + * @eotf: Electro-Optical Transfer Function (EOTF) + * used in the stream. + */ + __u8 eotf; + /** + * @metadata_type: Static_Metadata_Descriptor_ID. + */ + __u8 metadata_type; + /** + * @display_primaries: Color Primaries of the Data. + * These are coded as unsigned 16-bit values in units of + * 0.00002, where 0x0000 represents zero and 0xC350 + * represents 1.0000. + * @display_primaries.x: X cordinate of color primary. + * @display_primaries.y: Y cordinate of color primary. + */ + struct { + __u16 x, y; + } display_primaries[3]; + /** + * @white_point: White Point of Colorspace Data. + * These are coded as unsigned 16-bit values in units of + * 0.00002, where 0x0000 represents zero and 0xC350 + * represents 1.0000. + * @white_point.x: X cordinate of whitepoint of color primary. + * @white_point.y: Y cordinate of whitepoint of color primary. + */ + struct { + __u16 x, y; + } white_point; + /** + * @max_display_mastering_luminance: Max Mastering Display Luminance. + * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, + * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. + */ + __u16 max_display_mastering_luminance; + /** + * @min_display_mastering_luminance: Min Mastering Display Luminance. + * This value is coded as an unsigned 16-bit value in units of + * 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF + * represents 6.5535 cd/m2. + */ + __u16 min_display_mastering_luminance; + /** + * @max_cll: Max Content Light Level. + * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, + * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. + */ + __u16 max_cll; + /** + * @max_fall: Max Frame Average Light Level. + * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, + * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. + */ + __u16 max_fall; +}; + +/** + * struct hdr_output_metadata - HDR output metadata + * + * Metadata Information to be passed from userspace + */ +struct hdr_output_metadata { + /** + * @metadata_type: Static_Metadata_Descriptor_ID. + */ + __u32 metadata_type; + /** + * @hdmi_metadata_type1: HDR Metadata Infoframe. + */ + union { + struct hdr_metadata_infoframe hdmi_metadata_type1; + }; +}; + #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 @@ -803,6 +904,10 @@ }; /** + * struct drm_mode_create_blob - Create New block property + * @data: Pointer to data to copy. + * @length: Length of data to copy. + * @blob_id: new property ID. * Create a new 'blob' data property, copying length bytes from data pointer, * and returning new blob ID. */ @@ -816,13 +921,27 @@ }; /** + * struct drm_mode_destroy_blob - Destroy user blob + * @blob_id: blob_id to destroy * Destroy a user-created blob property. + * + * User-space can release blobs as soon as they do not need to refer to them by + * their blob object ID. For instance, if you are using a MODE_ID blob in an + * atomic commit and you will not make another commit re-using the same ID, you + * can destroy the blob as soon as the commit has been issued, without waiting + * for it to complete. */ struct drm_mode_destroy_blob { __u32 blob_id; }; /** + * struct drm_mode_create_lease - Create lease + * @object_ids: Pointer to array of object ids. + * @object_count: Number of object ids. + * @flags: flags for new FD. + * @lessee_id: unique identifier for lessee. + * @fd: file descriptor to new drm_master file. * Lease mode resources, creating another drm_master. */ struct drm_mode_create_lease { @@ -840,6 +959,10 @@ }; /** + * struct drm_mode_list_lessees - List lessees + * @count_lessees: Number of lessees. + * @pad: pad. + * @lessees_ptr: Pointer to lessess. * List lesses from a drm_master */ struct drm_mode_list_lessees { @@ -860,6 +983,10 @@ }; /** + * struct drm_mode_get_lease - Get Lease + * @count_objects: Number of leased objects. + * @pad: pad. + * @objects_ptr: Pointer to objects. * Get leased objects */ struct drm_mode_get_lease { @@ -880,6 +1007,8 @@ }; /** + * struct drm_mode_revoke_lease - Revoke lease + * @lessee_id: Unique ID of lessee. * Revoke lease */ struct drm_mode_revoke_lease { diff -Nru libdrm-2.4.102/intel/i915_pciids.h libdrm-2.4.105/intel/i915_pciids.h --- libdrm-2.4.102/intel/i915_pciids.h 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/intel/i915_pciids.h 2021-04-07 14:09:24.167843300 +0000 @@ -170,9 +170,9 @@ #define INTEL_HSW_ULT_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ - INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0A06, info) /* ULT GT1 mobile */ + INTEL_VGA_DEVICE(0x0A0B, info) /* ULT GT1 reserved */ #define INTEL_HSW_ULX_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */ @@ -181,26 +181,26 @@ INTEL_HSW_ULT_GT1_IDS(info), \ INTEL_HSW_ULX_GT1_IDS(info), \ INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ - INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ + INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ + INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \ INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ - INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */ + INTEL_VGA_DEVICE(0x0D0E, info) /* CRW GT1 reserved */ #define INTEL_HSW_ULT_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ - INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0A16, info) /* ULT GT2 mobile */ + INTEL_VGA_DEVICE(0x0A1B, info) /* ULT GT2 reserved */ \ #define INTEL_HSW_ULX_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \ @@ -209,45 +209,45 @@ INTEL_HSW_ULT_GT2_IDS(info), \ INTEL_HSW_ULX_GT2_IDS(info), \ INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ - INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ + INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ + INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \ INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ - INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ - INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ - INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */ + INTEL_VGA_DEVICE(0x0D1E, info) /* CRW GT2 reserved */ #define INTEL_HSW_ULT_GT3_IDS(info) \ INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */ #define INTEL_HSW_GT3_IDS(info) \ INTEL_HSW_ULT_GT3_IDS(info), \ INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ - INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ + INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \ + INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \ INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0D26, info), /* CRW GT3 mobile */ \ INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ - INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ - INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ - INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ + INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ #define INTEL_HSW_IDS(info) \ INTEL_HSW_GT1_IDS(info), \ @@ -258,9 +258,7 @@ INTEL_VGA_DEVICE(0x0f30, info), \ INTEL_VGA_DEVICE(0x0f31, info), \ INTEL_VGA_DEVICE(0x0f32, info), \ - INTEL_VGA_DEVICE(0x0f33, info), \ - INTEL_VGA_DEVICE(0x0157, info), \ - INTEL_VGA_DEVICE(0x0155, info) + INTEL_VGA_DEVICE(0x0f33, info) #define INTEL_BDW_ULT_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ @@ -331,17 +329,20 @@ INTEL_VGA_DEVICE(0x22b3, info) #define INTEL_SKL_ULT_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */ + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ + INTEL_VGA_DEVICE(0x1913, info) /* ULT GT1.5 */ #define INTEL_SKL_ULX_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */ + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ + INTEL_VGA_DEVICE(0x1915, info) /* ULX GT1.5 */ #define INTEL_SKL_GT1_IDS(info) \ INTEL_SKL_ULT_GT1_IDS(info), \ INTEL_SKL_ULX_GT1_IDS(info), \ INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ + INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \ INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ - INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ + INTEL_VGA_DEVICE(0x1917, info) /* DT GT1.5 */ #define INTEL_SKL_ULT_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \ @@ -354,26 +355,26 @@ INTEL_SKL_ULT_GT2_IDS(info), \ INTEL_SKL_ULX_GT2_IDS(info), \ INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \ - INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ #define INTEL_SKL_ULT_GT3_IDS(info) \ - INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */ + INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3e */ \ + INTEL_VGA_DEVICE(0x1927, info) /* ULT GT3e */ #define INTEL_SKL_GT3_IDS(info) \ INTEL_SKL_ULT_GT3_IDS(info), \ - INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ - INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */ + INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \ + INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3e */ \ + INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3e */ #define INTEL_SKL_GT4_IDS(info) \ INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \ - INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \ - INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \ - INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \ - INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */ + INTEL_VGA_DEVICE(0x193A, info), /* SRV GT4e */ \ + INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4e */ \ + INTEL_VGA_DEVICE(0x193D, info) /* WKS GT4e */ #define INTEL_SKL_IDS(info) \ INTEL_SKL_GT1_IDS(info), \ @@ -405,8 +406,8 @@ INTEL_KBL_ULX_GT1_IDS(info), \ INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \ - INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \ - INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */ + INTEL_VGA_DEVICE(0x590A, info), /* SRV GT1 */ \ + INTEL_VGA_DEVICE(0x590B, info) /* Halo GT1 */ #define INTEL_KBL_ULT_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ @@ -418,10 +419,10 @@ #define INTEL_KBL_GT2_IDS(info) \ INTEL_KBL_ULT_GT2_IDS(info), \ INTEL_KBL_ULX_GT2_IDS(info), \ - INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ - INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \ INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */ #define INTEL_KBL_ULT_GT3_IDS(info) \ @@ -446,10 +447,10 @@ /* CML GT1 */ #define INTEL_CML_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x9BA5, info), \ - INTEL_VGA_DEVICE(0x9BA8, info), \ + INTEL_VGA_DEVICE(0x9BA2, info), \ INTEL_VGA_DEVICE(0x9BA4, info), \ - INTEL_VGA_DEVICE(0x9BA2, info) + INTEL_VGA_DEVICE(0x9BA5, info), \ + INTEL_VGA_DEVICE(0x9BA8, info) #define INTEL_CML_U_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x9B21, info), \ @@ -458,11 +459,11 @@ /* CML GT2 */ #define INTEL_CML_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x9BC5, info), \ - INTEL_VGA_DEVICE(0x9BC8, info), \ - INTEL_VGA_DEVICE(0x9BC4, info), \ INTEL_VGA_DEVICE(0x9BC2, info), \ + INTEL_VGA_DEVICE(0x9BC4, info), \ + INTEL_VGA_DEVICE(0x9BC5, info), \ INTEL_VGA_DEVICE(0x9BC6, info), \ + INTEL_VGA_DEVICE(0x9BC8, info), \ INTEL_VGA_DEVICE(0x9BE6, info), \ INTEL_VGA_DEVICE(0x9BF6, info) @@ -496,8 +497,8 @@ INTEL_VGA_DEVICE(0x3E9C, info) #define INTEL_CFL_H_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ - INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ + INTEL_VGA_DEVICE(0x3E94, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x3E9B, info) /* Halo GT2 */ /* CFL U GT2 */ #define INTEL_CFL_U_GT2_IDS(info) \ @@ -542,67 +543,106 @@ /* CNL */ #define INTEL_CNL_PORT_F_IDS(info) \ - INTEL_VGA_DEVICE(0x5A54, info), \ - INTEL_VGA_DEVICE(0x5A5C, info), \ INTEL_VGA_DEVICE(0x5A44, info), \ - INTEL_VGA_DEVICE(0x5A4C, info) + INTEL_VGA_DEVICE(0x5A4C, info), \ + INTEL_VGA_DEVICE(0x5A54, info), \ + INTEL_VGA_DEVICE(0x5A5C, info) #define INTEL_CNL_IDS(info) \ INTEL_CNL_PORT_F_IDS(info), \ - INTEL_VGA_DEVICE(0x5A51, info), \ - INTEL_VGA_DEVICE(0x5A59, info), \ + INTEL_VGA_DEVICE(0x5A40, info), \ INTEL_VGA_DEVICE(0x5A41, info), \ - INTEL_VGA_DEVICE(0x5A49, info), \ - INTEL_VGA_DEVICE(0x5A52, info), \ - INTEL_VGA_DEVICE(0x5A5A, info), \ INTEL_VGA_DEVICE(0x5A42, info), \ + INTEL_VGA_DEVICE(0x5A49, info), \ INTEL_VGA_DEVICE(0x5A4A, info), \ INTEL_VGA_DEVICE(0x5A50, info), \ - INTEL_VGA_DEVICE(0x5A40, info) + INTEL_VGA_DEVICE(0x5A51, info), \ + INTEL_VGA_DEVICE(0x5A52, info), \ + INTEL_VGA_DEVICE(0x5A59, info), \ + INTEL_VGA_DEVICE(0x5A5A, info) /* ICL */ #define INTEL_ICL_PORT_F_IDS(info) \ INTEL_VGA_DEVICE(0x8A50, info), \ - INTEL_VGA_DEVICE(0x8A5C, info), \ - INTEL_VGA_DEVICE(0x8A59, info), \ - INTEL_VGA_DEVICE(0x8A58, info), \ INTEL_VGA_DEVICE(0x8A52, info), \ + INTEL_VGA_DEVICE(0x8A53, info), \ + INTEL_VGA_DEVICE(0x8A54, info), \ + INTEL_VGA_DEVICE(0x8A56, info), \ + INTEL_VGA_DEVICE(0x8A57, info), \ + INTEL_VGA_DEVICE(0x8A58, info), \ + INTEL_VGA_DEVICE(0x8A59, info), \ INTEL_VGA_DEVICE(0x8A5A, info), \ INTEL_VGA_DEVICE(0x8A5B, info), \ - INTEL_VGA_DEVICE(0x8A57, info), \ - INTEL_VGA_DEVICE(0x8A56, info), \ - INTEL_VGA_DEVICE(0x8A71, info), \ + INTEL_VGA_DEVICE(0x8A5C, info), \ INTEL_VGA_DEVICE(0x8A70, info), \ - INTEL_VGA_DEVICE(0x8A53, info), \ - INTEL_VGA_DEVICE(0x8A54, info) + INTEL_VGA_DEVICE(0x8A71, info) #define INTEL_ICL_11_IDS(info) \ INTEL_ICL_PORT_F_IDS(info), \ INTEL_VGA_DEVICE(0x8A51, info), \ INTEL_VGA_DEVICE(0x8A5D, info) -/* EHL/JSL */ +/* EHL */ #define INTEL_EHL_IDS(info) \ - INTEL_VGA_DEVICE(0x4500, info), \ - INTEL_VGA_DEVICE(0x4571, info), \ - INTEL_VGA_DEVICE(0x4551, info), \ INTEL_VGA_DEVICE(0x4541, info), \ - INTEL_VGA_DEVICE(0x4E71, info), \ + INTEL_VGA_DEVICE(0x4551, info), \ + INTEL_VGA_DEVICE(0x4555, info), \ + INTEL_VGA_DEVICE(0x4557, info), \ + INTEL_VGA_DEVICE(0x4571, info) + +/* JSL */ +#define INTEL_JSL_IDS(info) \ + INTEL_VGA_DEVICE(0x4E51, info), \ + INTEL_VGA_DEVICE(0x4E55, info), \ + INTEL_VGA_DEVICE(0x4E57, info), \ INTEL_VGA_DEVICE(0x4E61, info), \ - INTEL_VGA_DEVICE(0x4E51, info) + INTEL_VGA_DEVICE(0x4E71, info) /* TGL */ -#define INTEL_TGL_12_IDS(info) \ +#define INTEL_TGL_12_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info) + +#define INTEL_TGL_12_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x9A40, info), \ INTEL_VGA_DEVICE(0x9A49, info), \ INTEL_VGA_DEVICE(0x9A59, info), \ - INTEL_VGA_DEVICE(0x9A60, info), \ - INTEL_VGA_DEVICE(0x9A68, info), \ - INTEL_VGA_DEVICE(0x9A70, info), \ INTEL_VGA_DEVICE(0x9A78, info), \ INTEL_VGA_DEVICE(0x9AC0, info), \ INTEL_VGA_DEVICE(0x9AC9, info), \ INTEL_VGA_DEVICE(0x9AD9, info), \ INTEL_VGA_DEVICE(0x9AF8, info) +#define INTEL_TGL_12_IDS(info) \ + INTEL_TGL_12_GT1_IDS(info), \ + INTEL_TGL_12_GT2_IDS(info) + +/* RKL */ +#define INTEL_RKL_IDS(info) \ + INTEL_VGA_DEVICE(0x4C80, info), \ + INTEL_VGA_DEVICE(0x4C8A, info), \ + INTEL_VGA_DEVICE(0x4C8B, info), \ + INTEL_VGA_DEVICE(0x4C8C, info), \ + INTEL_VGA_DEVICE(0x4C90, info), \ + INTEL_VGA_DEVICE(0x4C9A, info) + +/* DG1 */ +#define INTEL_DG1_IDS(info) \ + INTEL_VGA_DEVICE(0x4905, info), \ + INTEL_VGA_DEVICE(0x4906, info), \ + INTEL_VGA_DEVICE(0x4907, info), \ + INTEL_VGA_DEVICE(0x4908, info) + +/* ADL-S */ +#define INTEL_ADLS_IDS(info) \ + INTEL_VGA_DEVICE(0x4680, info), \ + INTEL_VGA_DEVICE(0x4681, info), \ + INTEL_VGA_DEVICE(0x4682, info), \ + INTEL_VGA_DEVICE(0x4683, info), \ + INTEL_VGA_DEVICE(0x4690, info), \ + INTEL_VGA_DEVICE(0x4691, info), \ + INTEL_VGA_DEVICE(0x4692, info), \ + INTEL_VGA_DEVICE(0x4693, info) + #endif /* _I915_PCIIDS_H */ diff -Nru libdrm-2.4.102/intel/intel_bufmgr_gem.c libdrm-2.4.105/intel/intel_bufmgr_gem.c --- libdrm-2.4.102/intel/intel_bufmgr_gem.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/intel/intel_bufmgr_gem.c 2021-04-07 14:09:24.171843300 +0000 @@ -1732,6 +1732,82 @@ return drm_intel_gem_bo_unmap(bo); } +static bool is_cache_coherent(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_caching arg = {}; + + arg.handle = bo_gem->gem_handle; + if (drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_CACHING, &arg)) + assert(false); + return arg.caching != I915_CACHING_NONE; +} + +static void set_domain(drm_intel_bo *bo, uint32_t read, uint32_t write) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_set_domain arg = {}; + + arg.handle = bo_gem->gem_handle; + arg.read_domains = read; + arg.write_domain = write; + if (drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &arg)) + assert(false); +} + +static int mmap_write(drm_intel_bo *bo, unsigned long offset, + unsigned long length, const void *buf) +{ + void *map = NULL; + + if (!length) + return 0; + + if (is_cache_coherent(bo)) { + map = drm_intel_gem_bo_map__cpu(bo); + if (map) + set_domain(bo, I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU); + } + if (!map) { + map = drm_intel_gem_bo_map__wc(bo); + if (map) + set_domain(bo, I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC); + } + + assert(map); + memcpy((char *)map + offset, buf, length); + drm_intel_gem_bo_unmap(bo); + return 0; +} + +static int mmap_read(drm_intel_bo *bo, unsigned long offset, + unsigned long length, void *buf) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + void *map = NULL; + + if (!length) + return 0; + + if (bufmgr_gem->has_llc || is_cache_coherent(bo)) { + map = drm_intel_gem_bo_map__cpu(bo); + if (map) + set_domain(bo, I915_GEM_DOMAIN_CPU, 0); + } + if (!map) { + map = drm_intel_gem_bo_map__wc(bo); + if (map) + set_domain(bo, I915_GEM_DOMAIN_WC, 0); + } + + assert(map); + memcpy(buf, (char *)map + offset, length); + drm_intel_gem_bo_unmap(bo); + return 0; +} + static int drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset, unsigned long size, const void *data) @@ -1752,14 +1828,20 @@ ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite); - if (ret != 0) { + if (ret) ret = -errno; + + if (ret != 0 && ret != -EOPNOTSUPP) { DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n", __FILE__, __LINE__, bo_gem->gem_handle, (int)offset, (int)size, strerror(errno)); + return ret; } - return ret; + if (ret == -EOPNOTSUPP) + mmap_write(bo, offset, size, data); + + return 0; } static int @@ -1807,14 +1889,20 @@ ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PREAD, &pread); - if (ret != 0) { + if (ret) ret = -errno; + + if (ret != 0 && ret != -EOPNOTSUPP) { DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n", __FILE__, __LINE__, bo_gem->gem_handle, (int)offset, (int)size, strerror(errno)); + return ret; } - return ret; + if (ret == -EOPNOTSUPP) + mmap_read(bo, offset, size, data); + + return 0; } /** Waits for all GPU rendering with the object to have completed. */ diff -Nru libdrm-2.4.102/intel/intel_chipset.c libdrm-2.4.105/intel/intel_chipset.c --- libdrm-2.4.102/intel/intel_chipset.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/intel/intel_chipset.c 2021-04-07 14:09:24.171843300 +0000 @@ -35,7 +35,11 @@ uint16_t gen; } pciids[] = { /* Keep ids sorted by gen; latest gen first */ + INTEL_ADLS_IDS(12), + INTEL_RKL_IDS(12), + INTEL_DG1_IDS(12), INTEL_TGL_12_IDS(12), + INTEL_JSL_IDS(11), INTEL_EHL_IDS(11), INTEL_ICL_11_IDS(11), INTEL_CNL_IDS(10), diff -Nru libdrm-2.4.102/intel/meson.build libdrm-2.4.105/intel/meson.build --- libdrm-2.4.102/intel/meson.build 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/intel/meson.build 2021-04-07 14:09:24.171843300 +0000 @@ -18,7 +18,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -libdrm_intel = shared_library( +libdrm_intel = library( 'drm_intel', [ files( diff -Nru libdrm-2.4.102/libkms/meson.build libdrm-2.4.105/libkms/meson.build --- libdrm-2.4.102/libkms/meson.build 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/libkms/meson.build 2021-04-07 14:09:24.171843300 +0000 @@ -41,7 +41,7 @@ libkms_include += include_directories('../exynos') endif -libkms = shared_library( +libkms = library( 'kms', [files_libkms, config_file], c_args : libdrm_c_args, diff -Nru libdrm-2.4.102/man/drm.7.rst libdrm-2.4.105/man/drm.7.rst --- libdrm-2.4.102/man/drm.7.rst 1970-01-01 00:00:00.000000000 +0000 +++ libdrm-2.4.105/man/drm.7.rst 2021-04-07 14:09:24.175843200 +0000 @@ -0,0 +1,91 @@ +=== +drm +=== + +------------------------ +Direct Rendering Manager +------------------------ + +:Date: September 2012 +:Manual section: 7 +:Manual group: Direct Rendering Manager + +Synopsis +======== + +``#include `` + +Description +=========== + +The *Direct Rendering Manager* (DRM) is a framework to manage *Graphics +Processing Units* (GPUs). It is designed to support the needs of complex +graphics devices, usually containing programmable pipelines well suited +to 3D graphics acceleration. Furthermore, it is responsible for memory +management, interrupt handling and DMA to provide a uniform interface to +applications. + +In earlier days, the kernel framework was solely used to provide raw +hardware access to privileged user-space processes which implement all +the hardware abstraction layers. But more and more tasks were moved into +the kernel. All these interfaces are based on **ioctl**\ (2) commands on +the DRM character device. The *libdrm* library provides wrappers for these +system-calls and many helpers to simplify the API. + +When a GPU is detected, the DRM system loads a driver for the detected +hardware type. Each connected GPU is then presented to user-space via a +character-device that is usually available as ``/dev/dri/card0`` and can +be accessed with **open**\ (2) and **close**\ (2). However, it still +depends on the graphics driver which interfaces are available on these +devices. If an interface is not available, the syscalls will fail with +``EINVAL``. + +Authentication +-------------- + +All DRM devices provide authentication mechanisms. Only a DRM master is +allowed to perform mode-setting or modify core state and only one user +can be DRM master at a time. See **drmSetMaster**\ (3) for information +on how to become DRM master and what the limitations are. Other DRM users +can be authenticated to the DRM-Master via **drmAuthMagic**\ (3) so they +can perform buffer allocations and rendering. + +Mode-Setting +------------ + +Managing connected monitors and displays and changing the current modes +is called *Mode-Setting*. This is restricted to the current DRM master. +Historically, this was implemented in user-space, but new DRM drivers +implement a kernel interface to perform mode-setting called *Kernel Mode +Setting* (KMS). If your hardware-driver supports it, you can use the KMS +API provided by DRM. This includes allocating framebuffers, selecting +modes and managing CRTCs and encoders. See **drm-kms**\ (7) for more. + +Memory Management +----------------- + +The most sophisticated tasks for GPUs today is managing memory objects. +Textures, framebuffers, command-buffers and all other kinds of commands +for the GPU have to be stored in memory. The DRM driver takes care of +managing all memory objects, flushing caches, synchronizing access and +providing CPU access to GPU memory. All memory management is hardware +driver dependent. However, two generic frameworks are available that are +used by most DRM drivers. These are the *Translation Table Manager* +(TTM) and the *Graphics Execution Manager* (GEM). They provide generic +APIs to create, destroy and access buffers from user-space. However, +there are still many differences between the drivers so driver-depedent +code is still needed. Many helpers are provided in *libgbm* (Graphics +Buffer Manager) from the *Mesa* project. For more information on DRM +memory management, see **drm-memory**\ (7). + +Reporting Bugs +============== + +Bugs in this manual should be reported to +https://gitlab.freedesktop.org/mesa/drm/-/issues. + +See Also +======== + +**drm-kms**\ (7), **drm-memory**\ (7), **drmSetMaster**\ (3), +**drmAuthMagic**\ (3), **drmAvailable**\ (3), **drmOpen**\ (3) diff -Nru libdrm-2.4.102/man/drmAvailable.3.rst libdrm-2.4.105/man/drmAvailable.3.rst --- libdrm-2.4.102/man/drmAvailable.3.rst 1970-01-01 00:00:00.000000000 +0000 +++ libdrm-2.4.105/man/drmAvailable.3.rst 2021-04-07 14:09:24.175843200 +0000 @@ -0,0 +1,41 @@ +============ +drmAvailable +============ + +----------------------------------------------------- +determine whether a DRM kernel driver has been loaded +----------------------------------------------------- + +:Date: September 2012 +:Manual section: 3 +:Manual group: Direct Rendering Manager + +Synopsis +======== + +``#include `` + +``int drmAvailable(void);`` + +Description +=========== + +``drmAvailable`` allows the caller to determine whether a kernel DRM +driver is loaded. + +Return Value +============ + +``drmAvailable`` returns 1 if a DRM driver is currently loaded. +Otherwise 0 is returned. + +Reporting Bugs +============== + +Bugs in this function should be reported to +https://gitlab.freedesktop.org/mesa/drm/-/issues + +See Also +======== + +**drm**\ (7), **drmOpen**\ (3) diff -Nru libdrm-2.4.102/man/drmAvailable.xml libdrm-2.4.105/man/drmAvailable.xml --- libdrm-2.4.102/man/drmAvailable.xml 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/man/drmAvailable.xml 1970-01-01 00:00:00.000000000 +0000 @@ -1,75 +0,0 @@ - - - - - - - - Direct Rendering Manager - libdrm - September 2012 - - - Developer - David - Herrmann - dh.herrmann@googlemail.com - - - - - - drmAvailable - 3 - - - - drmAvailable - determine whether a DRM kernel driver has been - loaded - - - - - - #include <xf86drm.h> - - - int drmAvailable - void - - - - - - - Description - drmAvailable allows the caller to determine - whether a kernel DRM driver is loaded. - - - - Return Value - drmAvailable returns 1 if a DRM driver is - currently loaded. Otherwise 0 is returned. - - - - Reporting Bugs - Bugs in this function should be reported to - https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm - under the "DRI" product, component "libdrm" - - - - See Also - - drm7, - drmOpen3 - - - diff -Nru libdrm-2.4.102/man/drmHandleEvent.3.rst libdrm-2.4.105/man/drmHandleEvent.3.rst --- libdrm-2.4.102/man/drmHandleEvent.3.rst 1970-01-01 00:00:00.000000000 +0000 +++ libdrm-2.4.105/man/drmHandleEvent.3.rst 2021-04-07 14:09:24.175843200 +0000 @@ -0,0 +1,62 @@ +============== +drmHandleEvent +============== + +----------------------------------- +read and process pending DRM events +----------------------------------- + +:Date: September 2012 +:Manual section: 3 +:Manual group: Direct Rendering Manager + +Synopsis +======== + +``#include `` + +``int drmHandleEvent(int fd, drmEventContextPtr evctx);`` + +Description +=========== + +``drmHandleEvent`` processes outstanding DRM events on the DRM +file-descriptor passed as ``fd``. This function should be called after +the DRM file-descriptor has polled readable; it will read the events and +use the passed-in ``evctx`` structure to call function pointers with the +parameters noted below: + +:: + + typedef struct _drmEventContext { + int version; + void (*vblank_handler) (int fd, + unsigned int sequence, + unsigned int tv_sec, + unsigned int tv_usec, + void *user_data) + void (*page_flip_handler) (int fd, + unsigned int sequence, + unsigned int tv_sec, + unsigned int tv_usec, + void *user_data) + } drmEventContext, *drmEventContextPtr; + +Return Value +============ + +``drmHandleEvent`` returns 0 on success, or if there is no data to +read from the file-descriptor. Returns -1 if the read on the +file-descriptor fails or returns less than a full event record. + +Reporting Bugs +============== + +Bugs in this function should be reported to +https://gitlab.freedesktop.org/mesa/drm/-/issues + +See Also +======== + +**drm**\ (7), **drm-kms**\ (7), **drmModePageFlip**\ (3), +**drmWaitVBlank**\ (3) diff -Nru libdrm-2.4.102/man/drmHandleEvent.xml libdrm-2.4.105/man/drmHandleEvent.xml --- libdrm-2.4.102/man/drmHandleEvent.xml 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/man/drmHandleEvent.xml 1970-01-01 00:00:00.000000000 +0000 @@ -1,102 +0,0 @@ - - - - - - - - Direct Rendering Manager - libdrm - September 2012 - - - Developer - David - Herrmann - dh.herrmann@googlemail.com - - - - - - drmHandleEvent - 3 - - - - drmHandleEvent - read and process pending DRM events - - - - - - #include <xf86drm.h> - - - int drmHandleEvent - int fd - drmEventContextPtr evctx - - - - - - - Description - drmHandleEvent processes outstanding DRM events - on the DRM file-descriptor passed as fd. This - function should be called after the DRM file-descriptor has polled - readable; it will read the events and use the passed-in - evctx structure to call function pointers - with the parameters noted below: - - -typedef struct _drmEventContext { - int version; - void (*vblank_handler) (int fd, - unsigned int sequence, - unsigned int tv_sec, - unsigned int tv_usec, - void *user_data) - void (*page_flip_handler) (int fd, - unsigned int sequence, - unsigned int tv_sec, - unsigned int tv_usec, - void *user_data) -} drmEventContext, *drmEventContextPtr; - - - - - - - - Return Value - drmHandleEvent returns 0 on - success, or if there is no data to read from the file-descriptor. - Returns -1 if the read on the file-descriptor fails - or returns less than a full event record. - - - - Reporting Bugs - Bugs in this function should be reported to - https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm - under the "DRI" product, component "libdrm" - - - - See Also - - drm7, - drm-kms7, - drmModePageFlip3, - drmWaitVBlank3 - - - diff -Nru libdrm-2.4.102/man/drm-kms.7.rst libdrm-2.4.105/man/drm-kms.7.rst --- libdrm-2.4.102/man/drm-kms.7.rst 1970-01-01 00:00:00.000000000 +0000 +++ libdrm-2.4.105/man/drm-kms.7.rst 2021-04-07 14:09:24.175843200 +0000 @@ -0,0 +1,229 @@ +======= +drm-kms +======= + +------------------- +Kernel Mode-Setting +------------------- + +:Date: September 2012 +:Manual section: 7 +:Manual group: Direct Rendering Manager + +Synopsis +======== + +``#include `` + +``#include `` + +Description +=========== + +Each DRM device provides access to manage which monitors and displays are +currently used and what frames to be displayed. This task is called *Kernel +Mode-Setting* (KMS). Historically, this was done in user-space and called +*User-space Mode-Setting* (UMS). Almost all open-source drivers now provide the +KMS kernel API to do this in the kernel, however, many non-open-source binary +drivers from different vendors still do not support this. You can use +**drmModeSettingSupported**\ (3) to check whether your driver supports this. To +understand how KMS works, we need to introduce 5 objects: *CRTCs*, *Planes*, +*Encoders*, *Connectors* and *Framebuffers*. + +CRTCs + A *CRTC* short for *CRT Controller* is an abstraction representing a part of + the chip that contains a pointer to a scanout buffer. Therefore, the number + of CRTCs available determines how many independent scanout buffers can be + active at any given time. The CRTC structure contains several fields to + support this: a pointer to some video memory (abstracted as a frame-buffer + object), a list of driven connectors, a display mode and an (x, y) offset + into the video memory to support panning or configurations where one piece + of video memory spans multiple CRTCs. A CRTC is the central point where + configuration of displays happens. You select which objects to use, which + modes and which parameters and then configure each CRTC via + **drmModeCrtcSet**\ (3) to drive the display devices. + +Planes + A *plane* respresents an image source that can be blended with or overlayed + on top of a CRTC during the scanout process. Planes are associated with a + frame-buffer to crop a portion of the image memory (source) and optionally + scale it to a destination size. The result is then blended with or overlayed + on top of a CRTC. Planes are not provided by all hardware and the number of + available planes is limited. If planes are not available or if not enough + planes are available, the user should fall back to normal software blending + (via GPU or CPU). + +Encoders + An *encoder* takes pixel data from a CRTC and converts it to a format + suitable for any attached connectors. On some devices, it may be possible to + have a CRTC send data to more than one encoder. In that case, both encoders + would receive data from the same scanout buffer, resulting in a *cloned* + display configuration across the connectors attached to each encoder. + +Connectors + A *connector* is the final destination of pixel-data on a device, and + usually connects directly to an external display device like a monitor or + laptop panel. A connector can only be attached to one encoder at a time. The + connector is also the structure where information about the attached display + is kept, so it contains fields for display data, *EDID* data, *DPMS* and + *connection status*, and information about modes supported on the attached + displays. + +Framebuffers + *Framebuffers* are abstract memory objects that provide a source of pixel + data to scanout to a CRTC. Applications explicitly request the creation of + framebuffers and can control their behavior. Framebuffers rely on the + underneath memory manager for low-level memory operations. When creating a + framebuffer, applications pass a memory handle through the API which is used + as backing storage. The framebuffer itself is only an abstract object with + no data. It just refers to memory buffers that must be created with the + **drm-memory**\ (7) API. + +Mode-Setting +------------ + +Before mode-setting can be performed, an application needs to call +**drmSetMaster**\ (3) to become *DRM-Master*. It then has exclusive access to +the KMS API. A call to **drmModeGetResources**\ (3) returns a list of *CRTCs*, +*Connectors*, *Encoders* and *Planes*. + +Normal procedure now includes: First, you select which connectors you want to +use. Users are mostly interested in which monitor or display-panel is active so +you need to make sure to arrange them in the correct logical order and select +the correct ones to use. For each connector, you need to find a CRTC to drive +this connector. If you want to clone output to two or more connectors, you may +use a single CRTC for all cloned connectors (if the hardware supports this). To +find a suitable CRTC, you need to iterate over the list of encoders that are +available for each connector. Each encoder contains a list of CRTCs that it can +work with and you simply select one of these CRTCs. If you later program the +CRTC to control a connector, it automatically selects the best encoder. +However, this procedure is needed so your CRTC has at least one working encoder +for the selected connector. See the *Examples* section below for more +information. + +All valid modes for a connector can be retrieved with a call to +drmModeGetConnector3 You need to select the mode you want to use and save it. +The first mode in the list is the default mode with the highest resolution +possible and often a suitable choice. + +After you have a working connector+CRTC+mode combination, you need to create a +framebuffer that is used for scanout. Memory buffer allocation is +driver-depedent and described in **drm-memory**\ (7). You need to create a +buffer big enough for your selected mode. Now you can create a framebuffer +object that uses your memory-buffer as scanout buffer. You can do this with +**drmModeAddFB**\ (3) and **drmModeAddFB2**\ (3). + +As a last step, you want to program your CRTC to drive your selected connector. +You can do this with a call to **drmModeSetCrtc**\ (3). + +Page-Flipping +------------- + +A call to **drmModeSetCrtc**\ (3) is executed immediately and forces the CRTC +to use the new scanout buffer. If you want smooth-transitions without tearing, +you probably use double-buffering. You need to create one framebuffer object +for each buffer you use. You can then call **drmModeSetCrtc**\ (3) on the next +buffer to flip. If you want to synchronize your flips with *vertical-blanks*, +you can use **drmModePageFlip**\ (3) which schedules your page-flip for the +next *vblank*. + +Planes +------ + +Planes are controlled independently from CRTCs. That is, a call to +**drmModeSetCrtc**\ (3) does not affect planes. Instead, you need to call +**drmModeSetPlane**\ (3) to configure a plane. This requires the plane ID, a +CRTC, a framebuffer and offsets into the plane-framebuffer and the +CRTC-framebuffer. The CRTC then blends the content from the plane over the CRTC +framebuffer buffer during scanout. As this does not involve any +software-blending, it is way faster than traditional blending. However, plane +resources are limited. See **drmModeGetPlaneResources**\ (3) for more +information. + +Cursors +------- + +Similar to planes, many hardware also supports cursors. A cursor is a very +small buffer with an image that is blended over the CRTC framebuffer. You can +set a different cursor for each CRTC with **drmModeSetCursor**\ (3) and move it +on the screen with **drmModeMoveCursor**\ (3). This allows to move the cursor +on the screen without rerendering. If no hardware cursors are supported, you +need to rerender for each frame the cursor is moved. + +Examples +======== + +Some examples of how basic mode-setting can be done. See the man-page of each +DRM function for more information. + +CRTC/Encoder Selection +---------------------- + +If you retrieved all display configuration information via +**drmModeGetResources**\ (3) as ``drmModeRes *res``, selected a connector from +the list in ``res->connectors`` and retrieved the connector-information as +``drmModeConnector *conn`` via **drmModeGetConnector**\ (3) then this example +shows, how you can find a suitable CRTC id to drive this connector. This +function takes a file-descriptor to the DRM device (see **drmOpen**\ (3)) as +``fd``, a pointer to the retrieved resources as ``res`` and a pointer to the +selected connector as ``conn``. It returns an integer smaller than 0 on +failure, otherwise, a valid CRTC id is returned. + +:: + + static int modeset_find_crtc(int fd, drmModeRes *res, drmModeConnector *conn) + { + drmModeEncoder *enc; + unsigned int i, j; + + /* iterate all encoders of this connector */ + for (i = 0; i < conn->count_encoders; ++i) { + enc = drmModeGetEncoder(fd, conn->encoders[i]); + if (!enc) { + /* cannot retrieve encoder, ignoring... */ + continue; + } + + /* iterate all global CRTCs */ + for (j = 0; j < res->count_crtcs; ++j) { + /* check whether this CRTC works with the encoder */ + if (!(enc->possible_crtcs & (1 << j))) + continue; + + + /* Here you need to check that no other connector + * currently uses the CRTC with id "crtc". If you intend + * to drive one connector only, then you can skip this + * step. Otherwise, simply scan your list of configured + * connectors and CRTCs whether this CRTC is already + * used. If it is, then simply continue the search here. */ + if (res->crtcs[j] "is unused") { + drmModeFreeEncoder(enc); + return res->crtcs[j]; + } + } + + drmModeFreeEncoder(enc); + } + + /* cannot find a suitable CRTC */ + return -ENOENT; + } + +Reporting Bugs +============== + +Bugs in this manual should be reported to +https://gitlab.freedesktop.org/mesa/drm/-/issues + +See Also +======== + +**drm**\ (7), **drm-memory**\ (7), **drmModeGetResources**\ (3), +**drmModeGetConnector**\ (3), **drmModeGetEncoder**\ (3), +**drmModeGetCrtc**\ (3), **drmModeSetCrtc**\ (3), **drmModeGetFB**\ (3), +**drmModeAddFB**\ (3), **drmModeAddFB2**\ (3), **drmModeRmFB**\ (3), +**drmModePageFlip**\ (3), **drmModeGetPlaneResources**\ (3), +**drmModeGetPlane**\ (3), **drmModeSetPlane**\ (3), **drmModeSetCursor**\ (3), +**drmModeMoveCursor**\ (3), **drmSetMaster**\ (3), **drmAvailable**\ (3), +**drmCheckModesettingSupported**\ (3), **drmOpen**\ (3) diff -Nru libdrm-2.4.102/man/drm-kms.xml libdrm-2.4.105/man/drm-kms.xml --- libdrm-2.4.102/man/drm-kms.xml 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/man/drm-kms.xml 1970-01-01 00:00:00.000000000 +0000 @@ -1,342 +0,0 @@ - - - - - - - - Direct Rendering Manager - libdrm - September 2012 - - - Developer - David - Herrmann - dh.herrmann@googlemail.com - - - - - - drm-kms - 7 - - - - drm-kms - Kernel Mode-Setting - - - - - #include <xf86drm.h> - #include <xf86drmMode.h> - - - - - Description - Each DRM device provides access to manage which monitors and displays - are currently used and what frames to be displayed. This task is - called Kernel Mode-Setting (KMS). Historically, - this was done in user-space and called - User-space Mode-Setting (UMS). Almost all - open-source drivers now provide the KMS kernel API to do this in the - kernel, however, many non-open-source binary drivers from different - vendors still do not support this. You can use - drmModeSettingSupported3 - to check whether your driver supports this. To understand how KMS - works, we need to introduce 5 objects: CRTCs, - Planes, Encoders, - Connectors and - Framebuffers. - - - - CRTCs - - A CRTC short for - CRT Controller is an abstraction - representing a part of the chip that contains a pointer to a - scanout buffer. Therefore, the number of CRTCs available - determines how many independent scanout buffers can be active - at any given time. The CRTC structure contains several fields - to support this: a pointer to some video memory (abstracted as - a frame-buffer object), a list of driven connectors, a display - mode and an (x, y) offset into the video memory to support - panning or configurations where one piece of video memory - spans multiple CRTCs. A CRTC is the central point where - configuration of displays happens. You select which objects to - use, which modes and which parameters and then configure each - CRTC via - drmModeCrtcSet3 - to drive the display devices. - - - - Planes - - A plane respresents an image source that - can be blended with or overlayed on top of a CRTC during the - scanout process. Planes are associated with a frame-buffer to - crop a portion of the image memory (source) and optionally - scale it to a destination size. The result is then blended - with or overlayed on top of a CRTC. Planes are not provided by - all hardware and the number of available planes is limited. If - planes are not available or if not enough planes are - available, the user should fall back to normal software - blending (via GPU or CPU). - - - - Encoders - - An encoder takes pixel data from a CRTC - and converts it to a format suitable for any attached - connectors. On some devices, it may be possible to have a CRTC - send data to more than one encoder. In that case, both - encoders would receive data from the same scanout buffer, - resulting in a cloned display - configuration across the connectors attached to each - encoder. - - - - Connectors - - A connector is the final destination of - pixel-data on a device, and usually connects directly to an - external display device like a monitor or laptop panel. A - connector can only be attached to one encoder at a time. The - connector is also the structure where information about the - attached display is kept, so it contains fields for display - data, EDID data, - DPMS and - connection status, and information about - modes supported on the attached displays. - - - - Framebuffers - - Framebuffers are abstract memory objects - that provide a source of pixel data to scanout to a CRTC. - Applications explicitly request the creation of framebuffers - and can control their behavior. Framebuffers rely on the - underneath memory manager for low-level memory operations. - When creating a framebuffer, applications pass a memory handle - through the API which is used as backing storage. The - framebuffer itself is only an abstract object with no data. It - just refers to memory buffers that must be created with the - drm-memory7 - API. - - - - - - - Mode-Setting - Before mode-setting can be performed, an application needs to call - drmSetMaster3 - to become DRM-Master. It then has exclusive - access to the KMS API. A call to - drmModeGetResources3 - returns a list of CRTCs, - Connectors, Encoders and - Planes. - - Normal procedure now includes: First, you select which connectors - you want to use. Users are mostly interested in which monitor or - display-panel is active so you need to make sure to arrange them in - the correct logical order and select the correct ones to use. For - each connector, you need to find a CRTC to drive this connector. If - you want to clone output to two or more connectors, you may use a - single CRTC for all cloned connectors (if the hardware supports - this). To find a suitable CRTC, you need to iterate over the list of - encoders that are available for each connector. Each encoder - contains a list of CRTCs that it can work with and you simply select - one of these CRTCs. If you later program the CRTC to control a - connector, it automatically selects the best encoder. However, this - procedure is needed so your CRTC has at least one working encoder - for the selected connector. See the Examples - section below for more information. - - All valid modes for a connector can be retrieved with a call to - drmModeGetConnector3 - You need to select the mode you want to use and save it. The first - mode in the list is the default mode with the highest resolution - possible and often a suitable choice. - - After you have a working connector+CRTC+mode combination, you need - to create a framebuffer that is used for scanout. Memory buffer - allocation is driver-depedent and described in - drm-memory7. - You need to create a buffer big enough for your selected mode. Now - you can create a framebuffer object that uses your memory-buffer as - scanout buffer. You can do this with - drmModeAddFB3 - and - drmModeAddFB23. - - As a last step, you want to program your CRTC to drive your selected - connector. You can do this with a call to - drmModeSetCrtc3. - - - - Page-Flipping - A call to - drmModeSetCrtc3 - is executed immediately and forces the CRTC to use the new scanout - buffer. If you want smooth-transitions without tearing, you probably - use double-buffering. You need to create one framebuffer object for - each buffer you use. You can then call - drmModeSetCrtc3 - on the next buffer to flip. If you want to synchronize your flips - with vertical-blanks, you can use - drmModePageFlip3 - which schedules your page-flip for the next - vblank. - - - - Planes - Planes are controlled independently from CRTCs. That is, a call to - drmModeSetCrtc3 - does not affect planes. Instead, you need to call - drmModeSetPlane3 - to configure a plane. This requires the plane ID, a CRTC, a - framebuffer and offsets into the plane-framebuffer and the - CRTC-framebuffer. The CRTC then blends the content from the plane - over the CRTC framebuffer buffer during scanout. As this does not - involve any software-blending, it is way faster than traditional - blending. However, plane resources are limited. See - drmModeGetPlaneResources3 - for more information. - - - - Cursors - Similar to planes, many hardware also supports cursors. A cursor is - a very small buffer with an image that is blended over the CRTC - framebuffer. You can set a different cursor for each CRTC with - drmModeSetCursor3 - and move it on the screen with - drmModeMoveCursor3. - This allows to move the cursor on the screen without rerendering. If - no hardware cursors are supported, you need to rerender for each - frame the cursor is moved. - - - - - - Examples - Some examples of how basic mode-setting can be done. See the man-page - of each DRM function for more information. - - - CRTC/Encoder Selection - If you retrieved all display configuration information via - drmModeGetResources3 - as drmModeRes *res, - selected a connector from the list in - res->connectors - and retrieved the connector-information as - drmModeConnector *conn - via - drmModeGetConnector3 - then this example shows, how you can find a suitable CRTC id to - drive this connector. This function takes a file-descriptor to the - DRM device (see - drmOpen3) - as fd, a pointer to the retrieved resources as - res and a pointer to the selected connector as - conn. It returns an integer smaller than 0 on - failure, otherwise, a valid CRTC id is returned. - - -static int modeset_find_crtc(int fd, drmModeRes *res, drmModeConnector *conn) -{ - drmModeEncoder *enc; - unsigned int i, j; - - /* iterate all encoders of this connector */ - for (i = 0; i < conn->count_encoders; ++i) { - enc = drmModeGetEncoder(fd, conn->encoders[i]); - if (!enc) { - /* cannot retrieve encoder, ignoring... */ - continue; - } - - /* iterate all global CRTCs */ - for (j = 0; j < res->count_crtcs; ++j) { - /* check whether this CRTC works with the encoder */ - if (!(enc->possible_crtcs & (1 << j))) - continue; - - - /* Here you need to check that no other connector - * currently uses the CRTC with id "crtc". If you intend - * to drive one connector only, then you can skip this - * step. Otherwise, simply scan your list of configured - * connectors and CRTCs whether this CRTC is already - * used. If it is, then simply continue the search here. */ - if (res->crtcs[j] "is unused") { - drmModeFreeEncoder(enc); - return res->crtcs[j]; - } - } - - drmModeFreeEncoder(enc); - } - - /* cannot find a suitable CRTC */ - return -ENOENT; -} - - - - - - - - Reporting Bugs - Bugs in this manual should be reported to - https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm - under the "DRI" product, component "libdrm" - - - - See Also - - drm7, - drm-memory7, - drmModeGetResources3, - drmModeGetConnector3, - drmModeGetEncoder3, - drmModeGetCrtc3, - drmModeSetCrtc3, - drmModeGetFB3, - drmModeAddFB3, - drmModeAddFB23, - drmModeRmFB3, - drmModePageFlip3, - drmModeGetPlaneResources3, - drmModeGetPlane3, - drmModeSetPlane3, - drmModeSetCursor3, - drmModeMoveCursor3, - drmSetMaster3, - drmAvailable3, - drmCheckModesettingSupported3, - drmOpen3 - - - diff -Nru libdrm-2.4.102/man/drm-memory.7.rst libdrm-2.4.105/man/drm-memory.7.rst --- libdrm-2.4.102/man/drm-memory.7.rst 1970-01-01 00:00:00.000000000 +0000 +++ libdrm-2.4.105/man/drm-memory.7.rst 2021-04-07 14:09:24.175843200 +0000 @@ -0,0 +1,322 @@ +========== +drm-memory +========== + +--------------------- +DRM Memory Management +--------------------- + +:Date: September 2012 +:Manual section: 7 +:Manual group: Direct Rendering Manager + +Synopsis +======== + +``#include `` + +Description +=========== + +Many modern high-end GPUs come with their own memory managers. They even +include several different caches that need to be synchronized during access. +Textures, framebuffers, command buffers and more need to be stored in memory +that can be accessed quickly by the GPU. Therefore, memory management on GPUs +is highly driver- and hardware-dependent. + +However, there are several frameworks in the kernel that are used by more than +one driver. These can be used for trivial mode-setting without requiring +driver-dependent code. But for hardware-accelerated rendering you need to read +the manual pages for the driver you want to work with. + +Dumb-Buffers +------------ + +Almost all in-kernel DRM hardware drivers support an API called *Dumb-Buffers*. +This API allows to create buffers of arbitrary size that can be used for +scanout. These buffers can be memory mapped via **mmap**\ (2) so you can render +into them on the CPU. However, GPU access to these buffers is often not +possible. Therefore, they are fine for simple tasks but not suitable for +complex compositions and renderings. + +The ``DRM_IOCTL_MODE_CREATE_DUMB`` ioctl can be used to create a dumb buffer. +The kernel will return a 32-bit handle that can be used to manage the buffer +with the DRM API. You can create framebuffers with **drmModeAddFB**\ (3) and +use it for mode-setting and scanout. To access the buffer, you first need to +retrieve the offset of the buffer. The ``DRM_IOCTL_MODE_MAP_DUMB`` ioctl +requests the DRM subsystem to prepare the buffer for memory-mapping and returns +a fake-offset that can be used with **mmap**\ (2). + +The ``DRM_IOCTL_MODE_CREATE_DUMB`` ioctl takes as argument a structure of type +``struct drm_mode_create_dumb``: + +:: + + struct drm_mode_create_dumb { + __u32 height; + __u32 width; + __u32 bpp; + __u32 flags; + + __u32 handle; + __u32 pitch; + __u64 size; + }; + +The fields *height*, *width*, *bpp* and *flags* have to be provided by the +caller. The other fields are filled by the kernel with the return values. +*height* and *width* are the dimensions of the rectangular buffer that is +created. *bpp* is the number of bits-per-pixel and must be a multiple of 8. You +most commonly want to pass 32 here. The flags field is currently unused and +must be zeroed. Different flags to modify the behavior may be added in the +future. After calling the ioctl, the handle, pitch and size fields are filled +by the kernel. *handle* is a 32-bit gem handle that identifies the buffer. This +is used by several other calls that take a gem-handle or memory-buffer as +argument. The *pitch* field is the pitch (or stride) of the new buffer. Most +drivers use 32-bit or 64-bit aligned stride-values. The size field contains the +absolute size in bytes of the buffer. This can normally also be computed with +``(height * pitch + width) * bpp / 4``. + +To prepare the buffer for **mmap**\ (2) you need to use the +``DRM_IOCTL_MODE_MAP_DUMB`` ioctl. It takes as argument a structure of type +``struct drm_mode_map_dumb``: + +:: + + struct drm_mode_map_dumb { + __u32 handle; + __u32 pad; + + __u64 offset; + }; + +You need to put the gem-handle that was previously retrieved via +``DRM_IOCTL_MODE_CREATE_DUMB`` into the *handle* field. The *pad* field is +unused padding and must be zeroed. After completion, the *offset* field will +contain an offset that can be used with **mmap**\ (2) on the DRM +file-descriptor. + +If you don't need your dumb-buffer, anymore, you have to destroy it with +``DRM_IOCTL_MODE_DESTROY_DUMB``. If you close the DRM file-descriptor, all open +dumb-buffers are automatically destroyed. This ioctl takes as argument a +structure of type ``struct drm_mode_destroy_dumb``: + +:: + + struct drm_mode_destroy_dumb { + __u32 handle; + }; + +You only need to put your handle into the *handle* field. After this call, the +handle is invalid and may be reused for new buffers by the dumb-API. + +TTM +--- + +*TTM* stands for *Translation Table Manager* and is a generic memory-manager +provided by the kernel. It does not provide a common user-space API so you need +to look at each driver interface if you want to use it. See for instance the +radeon man pages for more information on memory-management with radeon and TTM. + +GEM +--- + +*GEM* stands for *Graphics Execution Manager* and is a generic DRM +memory-management framework in the kernel, that is used by many different +drivers. GEM is designed to manage graphics memory, control access to the +graphics device execution context and handle essentially NUMA environment +unique to modern graphics hardware. GEM allows multiple applications to share +graphics device resources without the need to constantly reload the entire +graphics card. Data may be shared between multiple applications with gem +ensuring that the correct memory synchronization occurs. + +GEM provides simple mechanisms to manage graphics data and control execution +flow within the linux DRM subsystem. However, GEM is not a complete framework +that is fully driver independent. Instead, if provides many functions that are +shared between many drivers, but each driver has to implement most of +memory-management with driver-dependent ioctls. This manpage tries to describe +the semantics (and if it applies, the syntax) that is shared between all +drivers that use GEM. + +All GEM APIs are defined as **ioctl**\ (2) on the DRM file descriptor. An +application must be authorized via **drmAuthMagic**\ (3) to the current +DRM-Master to access the GEM subsystem. A driver that does not support GEM will +return ``ENODEV`` for all these ioctls. Invalid object handles return +``EINVAL`` and invalid object names return ``ENOENT``. + +Gem provides explicit memory management primitives. System pages are allocated +when the object is created, either as the fundamental storage for hardware +where system memory is used by the graphics processor directly, or as backing +store for graphics-processor resident memory. + +Objects are referenced from user-space using handles. These are, for all +intents and purposes, equivalent to file descriptors but avoid the overhead. +Newer kernel drivers also support the **drm-prime** (7) infrastructure which +can return real file-descriptor for GEM-handles using the linux DMA-BUF API. +Objects may be published with a name so that other applications and processes +can access them. The name remains valid as long as the object exists. +GEM-objects are reference counted in the kernel. The object is only destroyed +when all handles from user-space were closed. + +GEM-buffers cannot be created with a generic API. Each driver provides its own +API to create GEM-buffers. See for example ``DRM_I915_GEM_CREATE``, +``DRM_NOUVEAU_GEM_NEW`` or ``DRM_RADEON_GEM_CREATE``. Each of these ioctls +returns a GEM-handle that can be passed to different generic ioctls. The +*libgbm* library from the *mesa3D* distribution tries to provide a +driver-independent API to create GBM buffers and retrieve a GBM-handle to them. +It allows to create buffers for different use-cases including scanout, +rendering, cursors and CPU-access. See the libgbm library for more information +or look at the driver-dependent man-pages (for example **drm-intel**\ (7) or +**drm-radeon**\ (7)). + +GEM-buffers can be closed with the ``DRM_IOCTL_GEM_CLOSE`` ioctl. It takes as +argument a structure of type ``struct drm_gem_close``: + +:: + + struct drm_gem_close { + __u32 handle; + __u32 pad; + }; + +The *handle* field is the GEM-handle to be closed. The *pad* field is unused +padding. It must be zeroed. After this call the GEM handle cannot be used by +this process anymore and may be reused for new GEM objects by the GEM API. + +If you want to share GEM-objects between different processes, you can create a +name for them and pass this name to other processes which can then open this +GEM-object. Names are currently 32-bit integer IDs and have no special +protection. That is, if you put a name on your GEM-object, every other client +that has access to the DRM device and is authenticated via +**drmAuthMagic**\ (3) to the current DRM-Master, can *guess* the name and open +or access the GEM-object. If you want more fine-grained access control, you can +use the new **drm-prime**\ (7) API to retrieve file-descriptors for +GEM-handles. To create a name for a GEM-handle, you use the +``DRM_IOCTL_GEM_FLINK`` ioctl. It takes as argument a structure of type +``struct drm_gem_flink``: + +:: + + struct drm_gem_flink { + __u32 handle; + __u32 name; + }; + +You have to put your handle into the *handle* field. After completion, the +kernel has put the new unique name into the name field. You can now pass +this name to other processes which can then import the name with the +``DRM_IOCTL_GEM_OPEN`` ioctl. It takes as argument a structure of type +``struct drm_gem_open``: + +:: + + struct drm_gem_open { + __u32 name; + + __u32 handle; + __u32 size; + }; + +You have to fill in the *name* field with the name of the GEM-object that you +want to open. The kernel will fill in the *handle* and *size* fields with the +new handle and size of the GEM-object. You can now access the GEM-object via +the handle as if you created it with the GEM API. + +Besides generic buffer management, the GEM API does not provide any generic +access. Each driver implements its own functionality on top of this API. This +includes execution-buffers, GTT management, context creation, CPU access, GPU +I/O and more. The next higher-level API is *OpenGL*. So if you want to use more +GPU features, you should use the *mesa3D* library to create OpenGL contexts on +DRM devices. This does *not* require any windowing-system like X11, but can +also be done on raw DRM devices. However, this is beyond the scope of this +man-page. You may have a look at other mesa3D man pages, including libgbm and +libEGL. 2D software-rendering (rendering with the CPU) can be achieved with the +dumb-buffer-API in a driver-independent fashion, however, for +hardware-accelerated 2D or 3D rendering you must use OpenGL. Any other API that +tries to abstract the driver-internals to access GEM-execution-buffers and +other GPU internals, would simply reinvent OpenGL so it is not provided. But if +you need more detailed information for a specific driver, you may have a look +into the driver-manpages, including **drm-intel**\ (7), **drm-radeon**\ (7) and +**drm-nouveau**\ (7). However, the **drm-prime**\ (7) infrastructure and the +generic GEM API as described here allow display-managers to handle +graphics-buffers and render-clients without any deeper knowledge of the GPU +that is used. Moreover, it allows to move objects between GPUs and implement +complex display-servers that don't do any rendering on their own. See its +man-page for more information. + +Examples +======== + +This section includes examples for basic memory-management tasks. + +Dumb-Buffers +------------ + +This examples shows how to create a dumb-buffer via the generic DRM API. +This is driver-independent (as long as the driver supports dumb-buffers) +and provides memory-mapped buffers that can be used for scanout. This +example creates a full-HD 1920x1080 buffer with 32 bits-per-pixel and a +color-depth of 24 bits. The buffer is then bound to a framebuffer which +can be used for scanout with the KMS API (see **drm-kms**\ (7)). + +:: + + struct drm_mode_create_dumb creq; + struct drm_mode_destroy_dumb dreq; + struct drm_mode_map_dumb mreq; + uint32_t fb; + int ret; + void *map; + + /* create dumb buffer */ + memset(&creq, 0, sizeof(creq)); + creq.width = 1920; + creq.height = 1080; + creq.bpp = 32; + ret = drmIoctl(fd, DRM_IOCTL_MODE_CREATE_DUMB, &creq); + if (ret < 0) { + /* buffer creation failed; see "errno" for more error codes */ + ... + } + /* creq.pitch, creq.handle and creq.size are filled by this ioctl with + * the requested values and can be used now. */ + + /* create framebuffer object for the dumb-buffer */ + ret = drmModeAddFB(fd, 1920, 1080, 24, 32, creq.pitch, creq.handle, &fb); + if (ret) { + /* frame buffer creation failed; see "errno" */ + ... + } + /* the framebuffer "fb" can now used for scanout with KMS */ + + /* prepare buffer for memory mapping */ + memset(&mreq, 0, sizeof(mreq)); + mreq.handle = creq.handle; + ret = drmIoctl(fd, DRM_IOCTL_MODE_MAP_DUMB, &mreq); + if (ret) { + /* DRM buffer preparation failed; see "errno" */ + ... + } + /* mreq.offset now contains the new offset that can be used with mmap() */ + + /* perform actual memory mapping */ + map = mmap(0, creq.size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, mreq.offset); + if (map == MAP_FAILED) { + /* memory-mapping failed; see "errno" */ + ... + } + + /* clear the framebuffer to 0 */ + memset(map, 0, creq.size); + +Reporting Bugs +============== + +Bugs in this manual should be reported to +https://gitlab.freedesktop.org/mesa/drm/-/issues + +See Also +======== + +**drm**\ (7), **drm-kms**\ (7), **drm-prime**\ (7), **drmAvailable**\ (3), +**drmOpen**\ (3), **drm-intel**\ (7), **drm-radeon**\ (7), **drm-nouveau**\ (7) diff -Nru libdrm-2.4.102/man/drm-memory.xml libdrm-2.4.105/man/drm-memory.xml --- libdrm-2.4.102/man/drm-memory.xml 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/man/drm-memory.xml 1970-01-01 00:00:00.000000000 +0000 @@ -1,430 +0,0 @@ - - - - - - - - Direct Rendering Manager - libdrm - September 2012 - - - Developer - David - Herrmann - dh.herrmann@googlemail.com - - - - - - drm-memory - 7 - - - - drm-memory - drm-mm - drm-gem - drm-ttm - DRM Memory Management - - - - - #include <xf86drm.h> - - - - - Description - Many modern high-end GPUs come with their own memory managers. They - even include several different caches that need to be synchronized - during access. Textures, framebuffers, command buffers and more need - to be stored in memory that can be accessed quickly by the GPU. - Therefore, memory management on GPUs is highly driver- and - hardware-dependent. - - However, there are several frameworks in the kernel that are used by - more than one driver. These can be used for trivial mode-setting - without requiring driver-dependent code. But for - hardware-accelerated rendering you need to read the manual pages for - the driver you want to work with. - - - Dumb-Buffers - Almost all in-kernel DRM hardware drivers support an API called - Dumb-Buffers. This API allows to create buffers - of arbitrary size that can be used for scanout. These buffers can be - memory mapped via - mmap2 - so you can render into them on the CPU. However, GPU access to these - buffers is often not possible. Therefore, they are fine for simple - tasks but not suitable for complex compositions and - renderings. - - The DRM_IOCTL_MODE_CREATE_DUMB ioctl can be - used to create a dumb buffer. The kernel will return a 32bit handle - that can be used to manage the buffer with the DRM API. You can - create framebuffers with - drmModeAddFB3 - and use it for mode-setting and scanout. To access the buffer, you - first need to retrieve the offset of the buffer. The - DRM_IOCTL_MODE_MAP_DUMB ioctl requests the DRM - subsystem to prepare the buffer for memory-mapping and returns a - fake-offset that can be used with - mmap2. - - The DRM_IOCTL_MODE_CREATE_DUMB ioctl takes as - argument a structure of type - struct drm_mode_create_dumb: - - -struct drm_mode_create_dumb { - __u32 height; - __u32 width; - __u32 bpp; - __u32 flags; - - __u32 handle; - __u32 pitch; - __u64 size; -}; - - - The fields height, - width, bpp and - flags have to be provided by the caller. - The other fields are filled by the kernel with the return values. - height and - width are the dimensions of the - rectangular buffer that is created. bpp - is the number of bits-per-pixel and must be a multiple of - 8. You most commonly want to pass - 32 here. The flags - field is currently unused and must be zeroed. Different flags to - modify the behavior may be added in the future. After calling the - ioctl, the handle, - pitch and size - fields are filled by the kernel. handle - is a 32bit gem handle that identifies the buffer. This is used by - several other calls that take a gem-handle or memory-buffer as - argument. The pitch field is the - pitch (or stride) of the new buffer. Most drivers use 32bit or 64bit - aligned stride-values. The size field - contains the absolute size in bytes of the buffer. This can normally - also be computed with - (height * pitch + width) * bpp / 4. - - To prepare the buffer for - mmap2 - you need to use the DRM_IOCTL_MODE_MAP_DUMB - ioctl. It takes as argument a structure of type - struct drm_mode_map_dumb: - - -struct drm_mode_map_dumb { - __u32 handle; - __u32 pad; - - __u64 offset; -}; - - - You need to put the gem-handle that was previously retrieved via - DRM_IOCTL_MODE_CREATE_DUMB into the - handle field. The - pad field is unused padding and must be - zeroed. After completion, the offset - field will contain an offset that can be used with - mmap2 - on the DRM file-descriptor. - - If you don't need your dumb-buffer, anymore, you have to destroy it - with DRM_IOCTL_MODE_DESTROY_DUMB. If you close - the DRM file-descriptor, all open dumb-buffers are automatically - destroyed. This ioctl takes as argument a structure of type - struct drm_mode_destroy_dumb: - - -struct drm_mode_destroy_dumb { - __u32 handle; -}; - - - You only need to put your handle into the - handle field. After this call, the handle - is invalid and may be reused for new buffers by the dumb-API. - - - - - TTM - TTM stands for - Translation Table Manager and is a generic - memory-manager provided by the kernel. It does not provide a common - user-space API so you need to look at each driver interface if you - want to use it. See for instance the radeon manpages for more - information on memory-management with radeon and TTM. - - - - GEM - GEM stands for - Graphics Execution Manager and is a generic DRM - memory-management framework in the kernel, that is used by many - different drivers. Gem is designed to manage graphics memory, - control access to the graphics device execution context and handle - essentially NUMA environment unique to modern graphics hardware. Gem - allows multiple applications to share graphics device resources - without the need to constantly reload the entire graphics card. Data - may be shared between multiple applications with gem ensuring that - the correct memory synchronization occurs. - - Gem provides simple mechanisms to manage graphics data and control - execution flow within the linux DRM subsystem. However, gem is not a - complete framework that is fully driver independent. Instead, if - provides many functions that are shared between many drivers, but - each driver has to implement most of memory-management with - driver-dependent ioctls. This manpage tries to describe the - semantics (and if it applies, the syntax) that is shared between all - drivers that use gem. - - All GEM APIs are defined as - ioctl2 - on the DRM file descriptor. An application must be authorized via - drmAuthMagic3 - to the current DRM-Master to access the GEM subsystem. A driver that - does not support gem will return ENODEV for all - these ioctls. Invalid object handles return - EINVAL and invalid object names return - ENOENT. - - Gem provides explicit memory management primitives. System pages are - allocated when the object is created, either as the fundamental - storage for hardware where system memory is used by the graphics - processor directly, or as backing store for graphics-processor - resident memory. - - Objects are referenced from user-space using handles. These are, for - all intents and purposes, equivalent to file descriptors but avoid - the overhead. Newer kernel drivers also support the - drm-prime7 - infrastructure which can return real file-descriptor for gem-handles - using the linux dma-buf API. Objects may be published with a name so - that other applications and processes can access them. The name - remains valid as long as the object exists. Gem-objects are - reference counted in the kernel. The object is only destroyed when - all handles from user-space were closed. - - Gem-buffers cannot be created with a generic API. Each driver - provides its own API to create gem-buffers. See for example - DRM_I915_GEM_CREATE, - DRM_NOUVEAU_GEM_NEW or - DRM_RADEON_GEM_CREATE. Each of these ioctls - returns a gem-handle that can be passed to different generic ioctls. - The libgbm library from the - mesa3D distribution tries to provide a - driver-independent API to create gbm buffers and retrieve a - gbm-handle to them. It allows to create buffers for different - use-cases including scanout, rendering, cursors and CPU-access. See - the libgbm library for more information or look at the - driver-dependent man-pages (for example - drm-intel7 - or - drm-radeon7). - - Gem-buffers can be closed with the - DRM_IOCTL_GEM_CLOSE ioctl. It takes as argument - a structure of type struct drm_gem_close: - - -struct drm_gem_close { - __u32 handle; - __u32 pad; -}; - - - The handle field is the gem-handle to be - closed. The pad field is unused padding. - It must be zeroed. After this call the gem handle cannot be used by - this process anymore and may be reused for new gem objects by the - gem API. - - If you want to share gem-objects between different processes, you - can create a name for them and pass this name to other processes - which can then open this gem-object. Names are currently 32bit - integer IDs and have no special protection. That is, if you put a - name on your gem-object, every other client that has access to the - DRM device and is authenticated via - drmAuthMagic3 - to the current DRM-Master, can guess the name - and open or access the gem-object. If you want more fine-grained - access control, you can use the new - drm-prime7 - API to retrieve file-descriptors for gem-handles. To create a name - for a gem-handle, you use the - DRM_IOCTL_GEM_FLINK ioctl. It takes as argument - a structure of type struct drm_gem_flink: - - -struct drm_gem_flink { - __u32 handle; - __u32 name; -}; - - - You have to put your handle into the - handle field. After completion, the - kernel has put the new unique name into the - name field. You can now pass this name to - other processes which can then import the name with the - DRM_IOCTL_GEM_OPEN ioctl. It takes as argument - a structure of type struct drm_gem_open: - - -struct drm_gem_open { - __u32 name; - - __u32 handle; - __u32 size; -}; - - - You have to fill in the name field with - the name of the gem-object that you want to open. The kernel will - fill in the handle and - size fields with the new handle and size - of the gem-object. You can now access the gem-object via the handle - as if you created it with the gem API. - - Besides generic buffer management, the GEM API does not provide any - generic access. Each driver implements its own functionality on top - of this API. This includes execution-buffers, GTT management, - context creation, CPU access, GPU I/O and more. The next - higher-level API is OpenGL. So if you want to - use more GPU features, you should use the - mesa3D library to create OpenGL contexts on DRM - devices. This does not require any - windowing-system like X11, but can also be done on raw DRM devices. - However, this is beyond the scope of this man-page. You may have a - look at other mesa3D manpages, including libgbm and libEGL. 2D - software-rendering (rendering with the CPU) can be achieved with the - dumb-buffer-API in a driver-independent fashion, however, for - hardware-accelerated 2D or 3D rendering you must use OpenGL. Any - other API that tries to abstract the driver-internals to access - GEM-execution-buffers and other GPU internals, would simply reinvent - OpenGL so it is not provided. But if you need more detailed - information for a specific driver, you may have a look into the - driver-manpages, including - drm-intel7, - drm-radeon7 - and - drm-nouveau7. - However, the - drm-prime7 - infrastructure and the generic gem API as described here allow - display-managers to handle graphics-buffers and render-clients - without any deeper knowledge of the GPU that is used. Moreover, it - allows to move objects between GPUs and implement complex - display-servers that don't do any rendering on their own. See its - man-page for more information. - - - - - Examples - This section includes examples for basic memory-management - tasks. - - - Dumb-Buffers - This examples shows how to create a dumb-buffer via the generic - DRM API. This is driver-independent (as long as the driver - supports dumb-buffers) and provides memory-mapped buffers that can - be used for scanout. This example creates a full-HD 1920x1080 - buffer with 32 bits-per-pixel and a color-depth of 24 bits. The - buffer is then bound to a framebuffer which can be used for - scanout with the KMS API (see - drm-kms7). - - -struct drm_mode_create_dumb creq; -struct drm_mode_destroy_dumb dreq; -struct drm_mode_map_dumb mreq; -uint32_t fb; -int ret; -void *map; - -/* create dumb buffer */ -memset(&creq, 0, sizeof(creq)); -creq.width = 1920; -creq.height = 1080; -creq.bpp = 32; -ret = drmIoctl(fd, DRM_IOCTL_MODE_CREATE_DUMB, &creq); -if (ret < 0) { - /* buffer creation failed; see "errno" for more error codes */ - ... -} -/* creq.pitch, creq.handle and creq.size are filled by this ioctl with - * the requested values and can be used now. */ - -/* create framebuffer object for the dumb-buffer */ -ret = drmModeAddFB(fd, 1920, 1080, 24, 32, creq.pitch, creq.handle, &fb); -if (ret) { - /* frame buffer creation failed; see "errno" */ - ... -} -/* the framebuffer "fb" can now used for scanout with KMS */ - -/* prepare buffer for memory mapping */ -memset(&mreq, 0, sizeof(mreq)); -mreq.handle = creq.handle; -ret = drmIoctl(fd, DRM_IOCTL_MODE_MAP_DUMB, &mreq); -if (ret) { - /* DRM buffer preparation failed; see "errno" */ - ... -} -/* mreq.offset now contains the new offset that can be used with mmap() */ - -/* perform actual memory mapping */ -map = mmap(0, creq.size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, mreq.offset); -if (map == MAP_FAILED) { - /* memory-mapping failed; see "errno" */ - ... -} - -/* clear the framebuffer to 0 */ -memset(map, 0, creq.size); - - - - - - - - Reporting Bugs - Bugs in this manual should be reported to - https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm - under the "DRI" product, component "libdrm" - - - - See Also - - drm7, - drm-kms7, - drm-prime7, - drmAvailable3, - drmOpen3, - drm-intel7, - drm-radeon7, - drm-nouveau7 - - - diff -Nru libdrm-2.4.102/man/drmModeGetResources.3.rst libdrm-2.4.105/man/drmModeGetResources.3.rst --- libdrm-2.4.102/man/drmModeGetResources.3.rst 1970-01-01 00:00:00.000000000 +0000 +++ libdrm-2.4.105/man/drmModeGetResources.3.rst 2021-04-07 14:09:24.175843200 +0000 @@ -0,0 +1,92 @@ +=================== +drmModeGetResources +=================== + +-------------------------------------------------- +retrieve current display configuration information +-------------------------------------------------- + +:Date: September 2012 +:Manual section: 3 +:Manual group: Direct Rendering Manager + +Synopsis +======== + +``#include `` + +``#include `` + +``drmModeResPtr drmModeGetResources(int fd);`` + +Description +=========== + +``drmModeGetResources`` allocates, populates, and returns a drmModeRes +structure containing information about the current display +configuration. The structure contains the following fields: + +:: + + typedef struct _drmModeRes { + int count_fbs; + uint32_t *fbs; + + int count_crtcs; + uint32_t *crtcs; + + int count_connectors; + uint32_t *connectors; + + int count_encoders; + uint32_t *encoders; + + uint32_t min_width, max_width; + uint32_t min_height, max_height; + } drmModeRes, *drmModeResPtr; + +The *count_fbs* and *fbs* fields indicate the number of currently allocated +framebuffer objects (i.e., objects that can be attached to a given CRTC +or sprite for display). + +The *count_crtcs* and *crtcs* fields list the available CRTCs in the +configuration. A CRTC is simply an object that can scan out a +framebuffer to a display sink, and contains mode timing and relative +position information. CRTCs drive encoders, which are responsible for +converting the pixel stream into a specific display protocol (e.g., MIPI +or HDMI). + +The *count_connectors* and *connectors* fields list the available physical +connectors on the system. Note that some of these may not be exposed +from the chassis (e.g., LVDS or eDP). Connectors are attached to +encoders and contain information about the attached display sink (e.g., +width and height in mm, subpixel ordering, and various other +properties). + +The *count_encoders* and *encoders* fields list the available encoders on +the device. Each encoder may be associated with a CRTC, and may be used +to drive a particular encoder. + +The *min_\** and *max_\** fields indicate the maximum size of a framebuffer +for this device (i.e., the scanout size limit). + +Return Value +============ + +``drmModeGetResources`` returns a drmModeRes structure pointer on +success, NULL on failure. The returned structure must be freed with +**drmModeFreeResources**\ (3). + +Reporting Bugs +============== + +Bugs in this function should be reported to +https://gitlab.freedesktop.org/mesa/drm/-/issues + +See Also +======== + +**drm**\ (7), **drm-kms**\ (7), **drmModeGetFB**\ (3), **drmModeAddFB**\ (3), +**drmModeAddFB2**\ (3), **drmModeRmFB**\ (3), **drmModeDirtyFB**\ (3), +**drmModeGetCrtc**\ (3), **drmModeSetCrtc** (3), **drmModeGetEncoder** (3), +**drmModeGetConnector**\ (3) diff -Nru libdrm-2.4.102/man/drmModeGetResources.xml libdrm-2.4.105/man/drmModeGetResources.xml --- libdrm-2.4.102/man/drmModeGetResources.xml 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/man/drmModeGetResources.xml 1970-01-01 00:00:00.000000000 +0000 @@ -1,139 +0,0 @@ - - - - - - - - Direct Rendering Manager - libdrm - September 2012 - - - Developer - David - Herrmann - dh.herrmann@googlemail.com - - - - - - drmModeGetResources - 3 - - - - drmModeGetResources - retrieve current display configuration information - - - - - - #include <xf86drm.h> - #include <xf86drmMode.h> - - - drmModeResPtr drmModeGetResources - int fd - - - - - - - Description - drmModeGetResources allocates, populates, and - returns a drmModeRes structure containing - information about the current display configuration. The structure - contains the following fields: - - -typedef struct _drmModeRes { - int count_fbs; - uint32_t *fbs; - - int count_crtcs; - uint32_t *crtcs; - - int count_connectors; - uint32_t *connectors; - - int count_encoders; - uint32_t *encoders; - - uint32_t min_width, max_width; - uint32_t min_height, max_height; -} drmModeRes, *drmModeResPtr; - - - - - The count_fbs and - fbs fields indicate the number of currently - allocated framebuffer objects (i.e., objects that can be attached to - a given CRTC or sprite for display). - - The count_crtcs and - crtcs fields list the available CRTCs in - the configuration. A CRTC is simply an object that can scan out a - framebuffer to a display sink, and contains mode timing and relative - position information. CRTCs drive encoders, which are responsible for - converting the pixel stream into a specific display protocol (e.g., - MIPI or HDMI). - - The count_connectors and - connectors fields list the available - physical connectors on the system. Note that some of these may not be - exposed from the chassis (e.g., LVDS or eDP). Connectors are attached - to encoders and contain information about the attached display sink - (e.g., width and height in mm, subpixel ordering, and various other - properties). - - The count_encoders and - encoders fields list the available encoders - on the device. Each encoder may be associated with a CRTC, and may be - used to drive a particular encoder. - - The min* and - max* fields indicate the maximum size of a - framebuffer for this device (i.e., the scanout size limit). - - - - Return Value - drmModeGetResources returns a drmModeRes - structure pointer on success, NULL on failure. The - returned structure must be freed with - drmModeFreeResources3. - - - - Reporting Bugs - Bugs in this function should be reported to - https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm - under the "DRI" product, component "libdrm" - - - - See Also - - drm7, - drm-kms7, - drmModeGetFB3, - drmModeAddFB3, - drmModeAddFB23, - drmModeRmFB3, - drmModeDirtyFB3, - drmModeGetCrtc3, - drmModeSetCrtc3, - drmModeGetEncoder3, - drmModeGetConnector3 - - - diff -Nru libdrm-2.4.102/man/drm.xml libdrm-2.4.105/man/drm.xml --- libdrm-2.4.102/man/drm.xml 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/man/drm.xml 1970-01-01 00:00:00.000000000 +0000 @@ -1,137 +0,0 @@ - - - - - - - - Direct Rendering Manager - libdrm - September 2012 - - - Developer - David - Herrmann - dh.herrmann@googlemail.com - - - - - - drm - 7 - - - - drm - Direct Rendering Manager - - - - - #include <xf86drm.h> - - - - - Description - The Direct Rendering Manager (DRM) is a framework - to manage Graphics Processing Units (GPUs). It is - designed to support the needs of complex graphics devices, usually - containing programmable pipelines well suited to 3D graphics - acceleration. Furthermore, it is responsible for memory management, - interrupt handling and DMA to provide a uniform interface to - applications. - - In earlier days, the kernel framework was solely used to provide raw - hardware access to privileged user-space processes which implement - all the hardware abstraction layers. But more and more tasks were - moved into the kernel. All these interfaces are based on - ioctl2 - commands on the DRM character device. The libdrm - library provides wrappers for these system-calls and many helpers to - simplify the API. - - When a GPU is detected, the DRM system loads a driver for the detected - hardware type. Each connected GPU is then presented to user-space via - a character-device that is usually available as - /dev/dri/card0 and can be accessed with - open2 - and - close2. - However, it still depends on the graphics driver which interfaces are - available on these devices. If an interface is not available, the - syscalls will fail with EINVAL. - - - Authentication - All DRM devices provide authentication mechanisms. Only a DRM-Master - is allowed to perform mode-setting or modify core state and only one - user can be DRM-Master at a time. See - drmSetMaster3 - for information on how to become DRM-Master and what the limitations - are. Other DRM users can be authenticated to the DRM-Master via - drmAuthMagic3 - so they can perform buffer allocations and rendering. - - - - Mode-Setting - Managing connected monitors and displays and changing the current - modes is called Mode-Setting. This is - restricted to the current DRM-Master. Historically, this was - implemented in user-space, but new DRM drivers implement a kernel - interface to perform mode-setting called - Kernel Mode Setting (KMS). If your - hardware-driver supports it, you can use the KMS API provided by - DRM. This includes allocating framebuffers, selecting modes and - managing CRTCs and encoders. See - drm-kms7 - for more. - - - - Memory Management - The most sophisticated tasks for GPUs today is managing memory - objects. Textures, framebuffers, command-buffers and all other kinds - of commands for the GPU have to be stored in memory. The DRM driver - takes care of managing all memory objects, flushing caches, - synchronizing access and providing CPU access to GPU memory. All - memory management is hardware driver dependent. However, two generic - frameworks are available that are used by most DRM drivers. These - are the Translation Table Manager (TTM) and the - Graphics Execution Manager (GEM). They provide - generic APIs to create, destroy and access buffers from user-space. - However, there are still many differences between the drivers so - driver-depedent code is still needed. Many helpers are provided in - libgbm (Graphics Buffer Manager) from the - mesa-project. For more information on DRM - memory-management, see - drm-memory7. - - - - - Reporting Bugs - Bugs in this manual should be reported to - https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm - under the "DRI" product, component "libdrm" - - - - See Also - - drm-kms7, - drm-memory7, - drmSetMaster3, - drmAuthMagic3, - drmAvailable3, - drmOpen3 - - - diff -Nru libdrm-2.4.102/man/meson.build libdrm-2.4.105/man/meson.build --- libdrm-2.4.102/man/meson.build 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/man/meson.build 2021-04-07 14:09:24.175843200 +0000 @@ -18,50 +18,23 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -xsltproc_args = [ - '--stringparam', 'man.authors.section.enabled', '0', - '--stringparam', 'man.copyright.section.enabled', '0', - '--stringparam', 'funcsynopsis.style', 'ansi', - '--stringparam', 'man.output.quietly', '1', - '--nonet', manpage_style, +rst_pages = [ + ['drm', '7'], + ['drm-kms', '7'], + ['drm-memory', '7'], + ['drmAvailable', '3'], + ['drmHandleEvent', '3'], + ['drmModeGetResources', '3'], ] - -xmls = [ - ['drm', '7'], ['drm-kms', '7'], ['drm-memory', '7'], ['drmAvailable', '3'], - ['drmHandleEvent', '3'], ['drmModeGetResources', '3'] -] -foreach x : xmls - m = x[0] - s = x[1] - custom_target( - m, - input : files('@0@.xml'.format(m)), - output : '@0@.@1@'.format(m, s), - command : [prog_xslt, '-o', '@OUTPUT@', xsltproc_args, '@INPUT0@'], - install : true, - install_dir : join_paths(get_option('mandir'), 'man@0@'.format(s)), - build_by_default : true, - ) -endforeach - -foreach x : ['drm-mm', 'drm-gem', 'drm-ttm'] - gen = custom_target( - 'gen-@0@'.format(x), - input : 'drm-memory.xml', - output : '@0@.xml'.format(x), - command : [ - prog_sed, '-e', 's@^\.so \([a-z_]\+\)\.\([0-9]\)$$@\.so man\2\/\1\.\2@', - '@INPUT@', - ], - capture : true, - ) +foreach page : rst_pages + name = page[0] + '.' + page[1] + rst = files(name + '.rst') custom_target( - '@0@.7'.format(x), - input : gen, - output : '@0@.7'.format(x, '7'), - command : [prog_xslt, '-o', '@OUTPUT@', xsltproc_args, '@INPUT@'], + name, + input : rst, + output : name, + command : [prog_rst2man, '@INPUT@', '@OUTPUT@'], install : true, - install_dir : join_paths(get_option('mandir'), 'man7'), - build_by_default : true, + install_dir : join_paths(get_option('mandir'), 'man' + page[1]), ) endforeach diff -Nru libdrm-2.4.102/meson.build libdrm-2.4.105/meson.build --- libdrm-2.4.102/meson.build 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/meson.build 2021-04-07 14:09:24.175843200 +0000 @@ -21,7 +21,7 @@ project( 'libdrm', ['c'], - version : '2.4.102', + version : '2.4.105', license : 'MIT', meson_version : '>= 0.43', default_options : ['buildtype=debugoptimized', 'c_std=gnu99'], @@ -261,18 +261,8 @@ endif with_man_pages = get_option('man-pages') -prog_xslt = find_program('xsltproc', required : with_man_pages == 'true') -prog_sed = find_program('sed', required : with_man_pages == 'true') -manpage_style = 'http://docbook.sourceforge.net/release/xsl/current/manpages/docbook.xsl' -if prog_xslt.found() - if run_command(prog_xslt, '--nonet', manpage_style).returncode() != 0 - if with_man_pages == 'true' - error('Manpage style sheet cannot be found') - endif - with_man_pages = 'false' - endif -endif -with_man_pages = with_man_pages != 'false' and prog_xslt.found() and prog_sed.found() +prog_rst2man = find_program('rst2man', 'rst2man.py', required: with_man_pages == 'true') +with_man_pages = with_man_pages != 'false' and prog_rst2man.found() config.set10('HAVE_VISIBILITY', cc.compiles('''int foo_hidden(void) __attribute__((visibility(("hidden"))));''', @@ -304,7 +294,7 @@ inc_root = include_directories('.') inc_drm = include_directories('include/drm') -libdrm = shared_library( +libdrm = library( 'drm', [files( 'xf86drm.c', 'xf86drmHash.c', 'xf86drmRandom.c', 'xf86drmSL.c', diff -Nru libdrm-2.4.102/nouveau/meson.build libdrm-2.4.105/nouveau/meson.build --- libdrm-2.4.102/nouveau/meson.build 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/nouveau/meson.build 2021-04-07 14:09:24.175843200 +0000 @@ -19,7 +19,7 @@ # SOFTWARE. -libdrm_nouveau = shared_library( +libdrm_nouveau = library( 'drm_nouveau', [files( 'nouveau.c', 'pushbuf.c', 'bufctx.c', 'abi16.c'), config_file], c_args : libdrm_c_args, diff -Nru libdrm-2.4.102/omap/meson.build libdrm-2.4.105/omap/meson.build --- libdrm-2.4.102/omap/meson.build 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/omap/meson.build 2021-04-07 14:09:24.175843200 +0000 @@ -18,7 +18,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -libdrm_omap = shared_library( +libdrm_omap = library( 'drm_omap', [files('omap_drm.c'), config_file], include_directories : [inc_root, inc_drm], diff -Nru libdrm-2.4.102/radeon/meson.build libdrm-2.4.105/radeon/meson.build --- libdrm-2.4.102/radeon/meson.build 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/radeon/meson.build 2021-04-07 14:09:24.175843200 +0000 @@ -19,7 +19,7 @@ # SOFTWARE. -libdrm_radeon = shared_library( +libdrm_radeon = library( 'drm_radeon', [ files( diff -Nru libdrm-2.4.102/tegra/meson.build libdrm-2.4.105/tegra/meson.build --- libdrm-2.4.102/tegra/meson.build 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tegra/meson.build 2021-04-07 14:09:24.175843200 +0000 @@ -18,7 +18,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -libdrm_tegra = shared_library( +libdrm_tegra = library( 'drm_tegra', [files('tegra.c'), config_file], include_directories : [inc_root, inc_drm], diff -Nru libdrm-2.4.102/tests/amdgpu/amdgpu_test.c libdrm-2.4.105/tests/amdgpu/amdgpu_test.c --- libdrm-2.4.102/tests/amdgpu/amdgpu_test.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/amdgpu_test.c 2021-04-07 14:09:24.175843200 +0000 @@ -58,6 +58,7 @@ #define VM_TESTS_STR "VM Tests" #define RAS_TESTS_STR "RAS Tests" #define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests" +#define SECURITY_TESTS_STR "Security Tests" /** * Open handles for amdgpu devices @@ -130,6 +131,12 @@ .pCleanupFunc = suite_syncobj_timeline_tests_clean, .pTests = syncobj_timeline_tests, }, + { + .pName = SECURITY_TESTS_STR, + .pInitFunc = suite_security_tests_init, + .pCleanupFunc = suite_security_tests_clean, + .pTests = security_tests, + }, CU_SUITE_INFO_NULL, }; @@ -149,7 +156,7 @@ static Suites_Active_Status suites_active_stat[] = { { .pName = BASIC_TESTS_STR, - .pActive = always_active, + .pActive = suite_basic_tests_enable, }, { .pName = BO_TESTS_STR, @@ -187,6 +194,10 @@ .pName = SYNCOBJ_TIMELINE_TESTS_STR, .pActive = suite_syncobj_timeline_tests_enable, }, + { + .pName = SECURITY_TESTS_STR, + .pActive = suite_security_tests_enable, + }, }; @@ -485,12 +496,6 @@ "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - if (amdgpu_set_test_active(BASIC_TESTS_STR, "bo eviction Test", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - /* This test was ran on GFX8 and GFX9 only */ if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV) if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency Test", CU_FALSE)) diff -Nru libdrm-2.4.102/tests/amdgpu/amdgpu_test.h libdrm-2.4.105/tests/amdgpu/amdgpu_test.h --- libdrm-2.4.102/tests/amdgpu/amdgpu_test.h 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/amdgpu_test.h 2021-04-07 14:09:24.175843200 +0000 @@ -55,6 +55,11 @@ int suite_basic_tests_clean(); /** + * Decide if the suite is enabled by default or not. + */ +CU_BOOL suite_basic_tests_enable(void); + +/** * Tests in basic test suite */ extern CU_TestInfo basic_tests[]; @@ -243,6 +248,32 @@ void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring); /** + * Initialize security test suite + */ +int suite_security_tests_init(); + +/** + * Deinitialize security test suite + */ +int suite_security_tests_clean(); + +/** + * Decide if the suite is enabled by default or not. + */ +CU_BOOL suite_security_tests_enable(void); + +/** + * Tests in security test suite + */ +extern CU_TestInfo security_tests[]; + +extern void +amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle + device, + unsigned ip_type, + bool secure); + +/** * Helper functions */ static inline amdgpu_bo_handle gpu_mem_alloc( @@ -418,4 +449,26 @@ return r; } +static inline bool asic_is_arcturus(uint32_t asic_id) +{ + switch(asic_id) { + /* Arcturus asic DID */ + case 0x738C: + case 0x7388: + case 0x738E: + return true; + default: + return false; + } +} + +void amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle device_handle, + amdgpu_context_handle context_handle, + unsigned ip_type, int instance, int pm4_dw, + uint32_t *pm4_src, int res_cnt, + amdgpu_bo_handle *resources, + struct amdgpu_cs_ib_info *ib_info, + struct amdgpu_cs_request *ibs_request, + bool secure); + #endif /* #ifdef _AMDGPU_TEST_H_ */ diff -Nru libdrm-2.4.102/tests/amdgpu/basic_tests.c libdrm-2.4.105/tests/amdgpu/basic_tests.c --- libdrm-2.4.102/tests/amdgpu/basic_tests.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/basic_tests.c 2021-04-07 14:09:24.175843200 +0000 @@ -39,6 +39,7 @@ #include "amdgpu_test.h" #include "amdgpu_drm.h" +#include "amdgpu_internal.h" #include "util_math.h" static amdgpu_device_handle device_handle; @@ -69,7 +70,7 @@ int res_cnt, amdgpu_bo_handle *resources, struct amdgpu_cs_ib_info *ib_info, struct amdgpu_cs_request *ibs_request); - + CU_TestInfo basic_tests[] = { { "Query Info Test", amdgpu_query_info_test }, { "Userptr Test", amdgpu_userptr_test }, @@ -106,6 +107,20 @@ #define SDMA_OPCODE_COPY 1 # define SDMA_COPY_SUB_OPCODE_LINEAR 0 +#define SDMA_OPCODE_ATOMIC 10 +# define SDMA_ATOMIC_LOOP(x) ((x) << 0) + /* 0 - single_pass_atomic. + * 1 - loop_until_compare_satisfied. + */ +# define SDMA_ATOMIC_TMZ(x) ((x) << 2) + /* 0 - non-TMZ. + * 1 - TMZ. + */ +# define SDMA_ATOMIC_OPCODE(x) ((x) << 9) + /* TC_OP_ATOMIC_CMPSWAP_RTN_32 0x00000008 + * same as Packet 3 + */ + #define GFX_COMPUTE_NOP 0xffff1000 #define SDMA_NOP 0x0 @@ -157,6 +172,20 @@ * 2 - ce */ +#define PACKET3_ATOMIC_MEM 0x1E +#define TC_OP_ATOMIC_CMPSWAP_RTN_32 0x00000008 +#define ATOMIC_MEM_COMMAND(x) ((x) << 8) + /* 0 - single_pass_atomic. + * 1 - loop_until_compare_satisfied. + */ +#define ATOMIC_MEM_CACHEPOLICAY(x) ((x) << 25) + /* 0 - lru. + * 1 - stream. + */ +#define ATOMIC_MEM_ENGINESEL(x) ((x) << 30) + /* 0 - micro_engine. + */ + #define PACKET3_DMA_DATA 0x50 /* 1. header * 2. CONTROL @@ -586,6 +615,43 @@ +CU_BOOL suite_basic_tests_enable(void) +{ + uint32_t asic_id; + + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle)) + return CU_FALSE; + + asic_id = device_handle->info.asic_id; + + if (amdgpu_device_deinitialize(device_handle)) + return CU_FALSE; + + /* disable gfx engine basic test cases for Arturus due to no CPG */ + if (asic_is_arcturus(asic_id)) { + if (amdgpu_set_test_active("Basic Tests", + "Command submission Test (GFX)", + CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", + CU_get_error_msg()); + + if (amdgpu_set_test_active("Basic Tests", + "Command submission Test (Multi-Fence)", + CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", + CU_get_error_msg()); + + if (amdgpu_set_test_active("Basic Tests", + "Sync dependency Test", + CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", + CU_get_error_msg()); + } + + return CU_TRUE; +} + int suite_basic_tests_init(void) { struct amdgpu_gpu_info gpu_info = {0}; @@ -857,6 +923,15 @@ 0, &vram_info); CU_ASSERT_EQUAL(r, 0); + r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, + 0, >t_info); + CU_ASSERT_EQUAL(r, 0); + + if (vram_info.max_allocation > gtt_info.heap_size/3) { + vram_info.max_allocation = gtt_info.heap_size/3; + gtt_info.max_allocation = vram_info.max_allocation; + } + r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[0]); CU_ASSERT_EQUAL(r, 0); @@ -864,10 +939,6 @@ AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[1]); CU_ASSERT_EQUAL(r, 0); - r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, - 0, >t_info); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096, AMDGPU_GEM_DOMAIN_GTT, 0, >t_max[0]); CU_ASSERT_EQUAL(r, 0); @@ -1232,12 +1303,15 @@ * pm4_src, resources, ib_info, and ibs_request * submit command stream described in ibs_request and wait for this IB accomplished */ -static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, - unsigned ip_type, - int instance, int pm4_dw, uint32_t *pm4_src, - int res_cnt, amdgpu_bo_handle *resources, - struct amdgpu_cs_ib_info *ib_info, - struct amdgpu_cs_request *ibs_request) +void +amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle device_handle, + amdgpu_context_handle context_handle, + unsigned ip_type, int instance, int pm4_dw, + uint32_t *pm4_src, int res_cnt, + amdgpu_bo_handle *resources, + struct amdgpu_cs_ib_info *ib_info, + struct amdgpu_cs_request *ibs_request, + bool secure) { int r; uint32_t expired; @@ -1269,6 +1343,8 @@ ib_info->ib_mc_address = ib_result_mc_address; ib_info->size = pm4_dw; + if (secure) + ib_info->flags |= AMDGPU_IB_FLAGS_SECURE; ibs_request->ip_type = ip_type; ibs_request->ring = instance; @@ -1310,7 +1386,24 @@ CU_ASSERT_EQUAL(r, 0); } -static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) +static void +amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, + unsigned ip_type, int instance, int pm4_dw, + uint32_t *pm4_src, int res_cnt, + amdgpu_bo_handle *resources, + struct amdgpu_cs_ib_info *ib_info, + struct amdgpu_cs_request *ibs_request) +{ + amdgpu_test_exec_cs_helper_raw(device_handle, context_handle, + ip_type, instance, pm4_dw, pm4_src, + res_cnt, resources, ib_info, + ibs_request, false); +} + +void +amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle + device, unsigned + ip_type, bool secure) { const int sdma_write_length = 128; const int pm4_dw = 256; @@ -1322,6 +1415,7 @@ struct amdgpu_cs_request *ibs_request; uint64_t bo_mc; volatile uint32_t *bo_cpu; + uint32_t bo_cpu_origin; int i, j, r, loop, ring_id; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle va_handle; @@ -1336,10 +1430,14 @@ ibs_request = calloc(1, sizeof(*ibs_request)); CU_ASSERT_NOT_EQUAL(ibs_request, NULL); - r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info); + r = amdgpu_query_hw_ip_info(device, ip_type, 0, &hw_ip_info); CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_ctx_create(device_handle, &context_handle); + for (i = 0; secure && (i < 2); i++) + gtt_flags[i] |= AMDGPU_GEM_CREATE_ENCRYPTED; + + r = amdgpu_cs_ctx_create(device, &context_handle); + CU_ASSERT_EQUAL(r, 0); /* prepare resource */ @@ -1350,7 +1448,7 @@ loop = 0; while(loop < 2) { /* allocate UC bo for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, + r = amdgpu_bo_alloc_and_map(device, sdma_write_length * sizeof(uint32_t), 4096, AMDGPU_GEM_DOMAIN_GTT, gtt_flags[loop], &bo, (void**)&bo_cpu, @@ -1370,8 +1468,9 @@ sdma_write_length); else pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, - SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - pm4[i++] = 0xffffffff & bo_mc; + SDMA_WRITE_SUB_OPCODE_LINEAR, + secure ? SDMA_ATOMIC_TMZ(1) : 0); + pm4[i++] = 0xfffffffc & bo_mc; pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; if (family_id >= AMDGPU_FAMILY_AI) pm4[i++] = sdma_write_length - 1; @@ -1389,16 +1488,99 @@ pm4[i++] = 0xdeadbeaf; } - amdgpu_test_exec_cs_helper(context_handle, - ip_type, ring_id, - i, pm4, - 1, resources, - ib_info, ibs_request); + amdgpu_test_exec_cs_helper_raw(device, context_handle, + ip_type, ring_id, i, pm4, + 1, resources, ib_info, + ibs_request, secure); /* verify if SDMA test result meets with expected */ i = 0; - while(i < sdma_write_length) { - CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); + if (!secure) { + while(i < sdma_write_length) { + CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); + } + } else if (ip_type == AMDGPU_HW_IP_GFX) { + memset((void*)pm4, 0, pm4_dw * sizeof(uint32_t)); + pm4[i++] = PACKET3(PACKET3_ATOMIC_MEM, 7); + /* atomic opcode for 32b w/ RTN and ATOMIC_SWAPCMP_RTN + * command, 1-loop_until_compare_satisfied. + * single_pass_atomic, 0-lru + * engine_sel, 0-micro_engine + */ + pm4[i++] = (TC_OP_ATOMIC_CMPSWAP_RTN_32 | + ATOMIC_MEM_COMMAND(1) | + ATOMIC_MEM_CACHEPOLICAY(0) | + ATOMIC_MEM_ENGINESEL(0)); + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = 0x12345678; + pm4[i++] = 0x0; + pm4[i++] = 0xdeadbeaf; + pm4[i++] = 0x0; + pm4[i++] = 0x100; + amdgpu_test_exec_cs_helper_raw(device, context_handle, + ip_type, ring_id, i, pm4, + 1, resources, ib_info, + ibs_request, true); + } else if (ip_type == AMDGPU_HW_IP_DMA) { + /* restore the bo_cpu to compare */ + bo_cpu_origin = bo_cpu[0]; + memset((void*)pm4, 0, pm4_dw * sizeof(uint32_t)); + /* atomic opcode for 32b w/ RTN and ATOMIC_SWAPCMP_RTN + * loop, 1-loop_until_compare_satisfied. + * single_pass_atomic, 0-lru + */ + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_ATOMIC, + 0, + SDMA_ATOMIC_LOOP(1) | + SDMA_ATOMIC_TMZ(1) | + SDMA_ATOMIC_OPCODE(TC_OP_ATOMIC_CMPSWAP_RTN_32)); + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = 0x12345678; + pm4[i++] = 0x0; + pm4[i++] = 0xdeadbeaf; + pm4[i++] = 0x0; + pm4[i++] = 0x100; + amdgpu_test_exec_cs_helper_raw(device, context_handle, + ip_type, ring_id, i, pm4, + 1, resources, ib_info, + ibs_request, true); + /* DMA's atomic behavir is unlike GFX + * If the comparing data is not equal to destination data, + * For GFX, loop again till gfx timeout(system hang). + * For DMA, loop again till timer expired and then send interrupt. + * So testcase can't use interrupt mechanism. + * We take another way to verify. When the comparing data is not + * equal to destination data, overwrite the source data to the destination + * buffer. Otherwise, original destination data unchanged. + * So if the bo_cpu data is overwritten, the result is passed. + */ + CU_ASSERT_NOT_EQUAL(bo_cpu[0], bo_cpu_origin); + + /* compare again for the case of dest_data != cmp_data */ + i = 0; + /* restore again, here dest_data should be */ + bo_cpu_origin = bo_cpu[0]; + memset((void*)pm4, 0, pm4_dw * sizeof(uint32_t)); + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_ATOMIC, + 0, + SDMA_ATOMIC_LOOP(1) | + SDMA_ATOMIC_TMZ(1) | + SDMA_ATOMIC_OPCODE(TC_OP_ATOMIC_CMPSWAP_RTN_32)); + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = 0x87654321; + pm4[i++] = 0x0; + pm4[i++] = 0xdeadbeaf; + pm4[i++] = 0x0; + pm4[i++] = 0x100; + amdgpu_test_exec_cs_helper_raw(device, context_handle, + ip_type, ring_id, i, pm4, + 1, resources, ib_info, + ibs_request, true); + /* here bo_cpu[0] should be unchanged, still is 0x12345678, otherwise failed*/ + CU_ASSERT_EQUAL(bo_cpu[0], bo_cpu_origin); } r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, @@ -1418,6 +1600,13 @@ CU_ASSERT_EQUAL(r, 0); } +static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) +{ + amdgpu_command_submission_write_linear_helper_with_secure(device_handle, + ip_type, + false); +} + static void amdgpu_command_submission_sdma_write_linear(void) { amdgpu_command_submission_write_linear_helper(AMDGPU_HW_IP_DMA); diff -Nru libdrm-2.4.102/tests/amdgpu/bo_tests.c libdrm-2.4.105/tests/amdgpu/bo_tests.c --- libdrm-2.4.102/tests/amdgpu/bo_tests.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/bo_tests.c 2021-04-07 14:09:24.179843000 +0000 @@ -168,7 +168,7 @@ struct amdgpu_bo_info info = {0}; int r; - meta.size_metadata = 1; + meta.size_metadata = 4; meta.umd_metadata[0] = 0xdeadbeef; r = amdgpu_bo_set_metadata(buffer_handle, &meta); @@ -177,7 +177,7 @@ r = amdgpu_bo_query_info(buffer_handle, &info); CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(info.metadata.size_metadata, 1); + CU_ASSERT_EQUAL(info.metadata.size_metadata, 4); CU_ASSERT_EQUAL(info.metadata.umd_metadata[0], 0xdeadbeef); } diff -Nru libdrm-2.4.102/tests/amdgpu/cs_tests.c libdrm-2.4.105/tests/amdgpu/cs_tests.c --- libdrm-2.4.102/tests/amdgpu/cs_tests.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/cs_tests.c 2021-04-07 14:09:24.179843000 +0000 @@ -64,17 +64,21 @@ CU_BOOL suite_cs_tests_enable(void) { + uint32_t asic_id; + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, &device_handle)) return CU_FALSE; family_id = device_handle->info.family_id; + asic_id = device_handle->info.asic_id; if (amdgpu_device_deinitialize(device_handle)) return CU_FALSE; - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI || + asic_is_arcturus(asic_id)) { printf("\n\nThe ASIC NOT support UVD, suite disabled\n"); return CU_FALSE; } diff -Nru libdrm-2.4.102/tests/amdgpu/deadlock_tests.c libdrm-2.4.105/tests/amdgpu/deadlock_tests.c --- libdrm-2.4.102/tests/amdgpu/deadlock_tests.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/deadlock_tests.c 2021-04-07 14:09:24.179843000 +0000 @@ -124,6 +124,7 @@ CU_BOOL suite_deadlock_tests_enable(void) { CU_BOOL enable = CU_TRUE; + uint32_t asic_id; if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, &device_handle)) @@ -140,6 +141,15 @@ enable = CU_FALSE; } + asic_id = device_handle->info.asic_id; + if (asic_is_arcturus(asic_id)) { + if (amdgpu_set_test_active("Deadlock Tests", + "gfx ring block test (set amdgpu.lockup_timeout=50)", + CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", + CU_get_error_msg()); + } + if (device_handle->info.family_id >= AMDGPU_FAMILY_AI) use_uc_mtype = 1; diff -Nru libdrm-2.4.102/tests/amdgpu/decode_messages.h libdrm-2.4.105/tests/amdgpu/decode_messages.h --- libdrm-2.4.102/tests/amdgpu/decode_messages.h 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/decode_messages.h 2021-04-07 14:09:24.179843000 +0000 @@ -361,7 +361,7 @@ }; static const uint8_t avc_decode_msg[] = { - 0x02,0x00,0x00,0x00,0x1e,0x00,0x00,0x00,0x05,0x00,0x00,0x00,0x88,0x00,0x00,0x00, + 0x02,0x00,0x00,0x00,0x1e,0x00,0x00,0x00,0x85,0x00,0x00,0x00,0x88,0x00,0x00,0x00, 0x01,0x00,0x00,0x01,0x00,0x03,0x02,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, @@ -826,7 +826,7 @@ 0x28,0x00,0x00,0x00,0x90,0x06,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0x00,0x00,0x00, 0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x38,0x00,0x00,0x00, 0xb4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0xec,0x00,0x00,0x00, - 0x5c,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x5c,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,0x80,0x05,0x00,0x00,0x00,0x94,0x6b,0x00, 0x96,0x4e,0x0b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x50,0x00, 0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, diff -Nru libdrm-2.4.102/tests/amdgpu/meson.build libdrm-2.4.105/tests/amdgpu/meson.build --- libdrm-2.4.102/tests/amdgpu/meson.build 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/meson.build 2021-04-07 14:09:24.179843000 +0000 @@ -24,7 +24,7 @@ files( 'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c', 'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c', - 'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c', + 'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c', 'security_tests.c', ), dependencies : [dep_cunit, dep_threads, dep_atomic_ops], include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')], diff -Nru libdrm-2.4.102/tests/amdgpu/security_tests.c libdrm-2.4.105/tests/amdgpu/security_tests.c --- libdrm-2.4.102/tests/amdgpu/security_tests.c 1970-01-01 00:00:00.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/security_tests.c 2021-04-07 14:09:24.179843000 +0000 @@ -0,0 +1,485 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "CUnit/Basic.h" + +#include "amdgpu_test.h" +#include "amdgpu_drm.h" +#include "amdgpu_internal.h" + +#include +#include +#ifdef __FreeBSD__ +#include +#else +#include +#endif +#include +#include + +static amdgpu_device_handle device_handle; +static uint32_t major_version; +static uint32_t minor_version; + +static struct drm_amdgpu_info_hw_ip sdma_info; + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(_Arr) (sizeof(_Arr)/sizeof((_Arr)[0])) +#endif + + +/* --------------------- Secure bounce test ------------------------ * + * + * The secure bounce test tests that we can evict a TMZ buffer, + * and page it back in, via a bounce buffer, as it encryption/decryption + * depends on its physical address, and have the same data, i.e. data + * integrity is preserved. + * + * The steps are as follows (from Christian K.): + * + * Buffer A which is TMZ protected and filled by the CPU with a + * certain pattern. That the GPU is reading only random nonsense from + * that pattern is irrelevant for the test. + * + * This buffer A is then secure copied into buffer B which is also + * TMZ protected. + * + * Buffer B is moved around, from VRAM to GTT, GTT to SYSTEM, + * etc. + * + * Then, we use another secure copy of buffer B back to buffer A. + * + * And lastly we check with the CPU the pattern. + * + * Assuming that we don't have memory contention and buffer A stayed + * at the same place, we should still see the same pattern when read + * by the CPU. + * + * If we don't see the same pattern then something in the buffer + * migration code is not working as expected. + */ + +#define SECURE_BOUNCE_TEST_STR "secure bounce" +#define SECURE_BOUNCE_FAILED_STR SECURE_BOUNCE_TEST_STR " failed" + +#define PRINT_ERROR(_Res) fprintf(stderr, "%s:%d: %s (%d)\n", \ + __func__, __LINE__, strerror(-(_Res)), _Res) + +#define PACKET_LCOPY_SIZE 7 +#define PACKET_NOP_SIZE 12 + +struct sec_amdgpu_bo { + struct amdgpu_bo *bo; + struct amdgpu_va *va; +}; + +struct command_ctx { + struct amdgpu_device *dev; + struct amdgpu_cs_ib_info cs_ibinfo; + struct amdgpu_cs_request cs_req; + struct amdgpu_context *context; + int ring_id; +}; + +/** + * amdgpu_bo_alloc_map -- Allocate and map a buffer object (BO) + * @dev: The AMDGPU device this BO belongs to. + * @size: The size of the BO. + * @alignment: Alignment of the BO. + * @gem_domain: One of AMDGPU_GEM_DOMAIN_xyz. + * @alloc_flags: One of AMDGPU_GEM_CREATE_xyz. + * @sbo: the result + * + * Allocate a buffer object (BO) with the desired attributes + * as specified by the argument list and write out the result + * into @sbo. + * + * Return 0 on success and @sbo->bo and @sbo->va are set, + * or -errno on error. + */ +static int amdgpu_bo_alloc_map(struct amdgpu_device *dev, + unsigned size, + unsigned alignment, + unsigned gem_domain, + uint64_t alloc_flags, + struct sec_amdgpu_bo *sbo) +{ + void *cpu; + uint64_t mc_addr; + + return amdgpu_bo_alloc_and_map_raw(dev, + size, + alignment, + gem_domain, + alloc_flags, + 0, + &sbo->bo, + &cpu, &mc_addr, + &sbo->va); +} + +static void amdgpu_bo_unmap_free(struct sec_amdgpu_bo *sbo, + const uint64_t size) +{ + (void) amdgpu_bo_unmap_and_free(sbo->bo, + sbo->va, + sbo->va->address, + size); + sbo->bo = NULL; + sbo->va = NULL; +} + +static void amdgpu_sdma_lcopy(uint32_t *packet, + const uint64_t dst, + const uint64_t src, + const uint32_t size, + const int secure) +{ + /* Set the packet to Linear copy with TMZ set. + */ + packet[0] = htole32(secure << 18 | 1); + packet[1] = htole32(size-1); + packet[2] = htole32(0); + packet[3] = htole32((uint32_t)(src & 0xFFFFFFFFU)); + packet[4] = htole32((uint32_t)(src >> 32)); + packet[5] = htole32((uint32_t)(dst & 0xFFFFFFFFU)); + packet[6] = htole32((uint32_t)(dst >> 32)); +} + +static void amdgpu_sdma_nop(uint32_t *packet, uint32_t nop_count) +{ + /* A packet of the desired number of NOPs. + */ + packet[0] = htole32(nop_count << 16); + for ( ; nop_count > 0; nop_count--) + packet[nop_count-1] = 0; +} + +/** + * amdgpu_bo_lcopy -- linear copy with TMZ set, using sDMA + * @dev: AMDGPU device to which both buffer objects belong to + * @dst: destination buffer object + * @src: source buffer object + * @size: size of memory to move, in bytes. + * @secure: Set to 1 to perform secure copy, 0 for clear + * + * Issues and waits for completion of a Linear Copy with TMZ + * set, to the sDMA engine. @size should be a multiple of + * at least 16 bytes. + */ +static void amdgpu_bo_lcopy(struct command_ctx *ctx, + struct sec_amdgpu_bo *dst, + struct sec_amdgpu_bo *src, + const uint32_t size, + int secure) +{ + struct amdgpu_bo *bos[] = { dst->bo, src->bo }; + uint32_t packet[PACKET_LCOPY_SIZE]; + + amdgpu_sdma_lcopy(packet, + dst->va->address, + src->va->address, + size, secure); + amdgpu_test_exec_cs_helper_raw(ctx->dev, ctx->context, + AMDGPU_HW_IP_DMA, ctx->ring_id, + ARRAY_SIZE(packet), packet, + ARRAY_SIZE(bos), bos, + &ctx->cs_ibinfo, &ctx->cs_req, + secure == 1); +} + +/** + * amdgpu_bo_move -- Evoke a move of the buffer object (BO) + * @dev: device to which this buffer object belongs to + * @bo: the buffer object to be moved + * @whereto: one of AMDGPU_GEM_DOMAIN_xyz + * @secure: set to 1 to submit secure IBs + * + * Evokes a move of the buffer object @bo to the GEM domain + * descibed by @whereto. + * + * Returns 0 on sucess; -errno on error. + */ +static int amdgpu_bo_move(struct command_ctx *ctx, + struct amdgpu_bo *bo, + uint64_t whereto, + int secure) +{ + struct amdgpu_bo *bos[] = { bo }; + struct drm_amdgpu_gem_op gop = { + .handle = bo->handle, + .op = AMDGPU_GEM_OP_SET_PLACEMENT, + .value = whereto, + }; + uint32_t packet[PACKET_NOP_SIZE]; + int res; + + /* Change the buffer's placement. + */ + res = drmIoctl(ctx->dev->fd, DRM_IOCTL_AMDGPU_GEM_OP, &gop); + if (res) + return -errno; + + /* Now issue a NOP to actually evoke the MM to move + * it to the desired location. + */ + amdgpu_sdma_nop(packet, PACKET_NOP_SIZE); + amdgpu_test_exec_cs_helper_raw(ctx->dev, ctx->context, + AMDGPU_HW_IP_DMA, ctx->ring_id, + ARRAY_SIZE(packet), packet, + ARRAY_SIZE(bos), bos, + &ctx->cs_ibinfo, &ctx->cs_req, + secure == 1); + return 0; +} + +/* Safe, O Sec! + */ +static const uint8_t secure_pattern[] = { 0x5A, 0xFE, 0x05, 0xEC }; + +#define SECURE_BUFFER_SIZE (4 * 1024 * sizeof(secure_pattern)) + +static void amdgpu_secure_bounce(void) +{ + struct sec_amdgpu_bo alice, bob; + struct command_ctx sb_ctx; + long page_size; + uint8_t *pp; + int res; + + page_size = sysconf(_SC_PAGESIZE); + + memset(&sb_ctx, 0, sizeof(sb_ctx)); + sb_ctx.dev = device_handle; + res = amdgpu_cs_ctx_create(sb_ctx.dev, &sb_ctx.context); + if (res) { + PRINT_ERROR(res); + CU_FAIL(SECURE_BOUNCE_FAILED_STR); + return; + } + + /* Use the first present ring. + */ + res = ffs(sdma_info.available_rings) - 1; + if (res == -1) { + PRINT_ERROR(-ENOENT); + CU_FAIL(SECURE_BOUNCE_FAILED_STR); + goto Out_free_ctx; + } + sb_ctx.ring_id = res; + + /* Allocate a buffer named Alice in VRAM. + */ + res = amdgpu_bo_alloc_map(device_handle, + SECURE_BUFFER_SIZE, + page_size, + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_ENCRYPTED, + &alice); + if (res) { + PRINT_ERROR(res); + CU_FAIL(SECURE_BOUNCE_FAILED_STR); + return; + } + + /* Fill Alice with a pattern. + */ + for (pp = alice.bo->cpu_ptr; + pp < (typeof(pp)) alice.bo->cpu_ptr + SECURE_BUFFER_SIZE; + pp += sizeof(secure_pattern)) + memcpy(pp, secure_pattern, sizeof(secure_pattern)); + + /* Allocate a buffer named Bob in VRAM. + */ + res = amdgpu_bo_alloc_map(device_handle, + SECURE_BUFFER_SIZE, + page_size, + AMDGPU_GEM_DOMAIN_VRAM, + 0 /* AMDGPU_GEM_CREATE_ENCRYPTED */, + &bob); + if (res) { + PRINT_ERROR(res); + CU_FAIL(SECURE_BOUNCE_FAILED_STR); + goto Out_free_Alice; + } + + /* sDMA clear copy from Alice to Bob. + */ + amdgpu_bo_lcopy(&sb_ctx, &bob, &alice, SECURE_BUFFER_SIZE, 0); + + /* Move Bob to the GTT domain. + */ + res = amdgpu_bo_move(&sb_ctx, bob.bo, AMDGPU_GEM_DOMAIN_GTT, 0); + if (res) { + PRINT_ERROR(res); + CU_FAIL(SECURE_BOUNCE_FAILED_STR); + goto Out_free_all; + } + + /* sDMA clear copy from Bob to Alice. + */ + amdgpu_bo_lcopy(&sb_ctx, &alice, &bob, SECURE_BUFFER_SIZE, 0); + + /* Verify the contents of Alice. + */ + for (pp = alice.bo->cpu_ptr; + pp < (typeof(pp)) alice.bo->cpu_ptr + SECURE_BUFFER_SIZE; + pp += sizeof(secure_pattern)) { + res = memcmp(pp, secure_pattern, sizeof(secure_pattern)); + if (res) { + fprintf(stderr, SECURE_BOUNCE_FAILED_STR); + CU_FAIL(SECURE_BOUNCE_FAILED_STR); + break; + } + } + +Out_free_all: + amdgpu_bo_unmap_free(&bob, SECURE_BUFFER_SIZE); +Out_free_Alice: + amdgpu_bo_unmap_free(&alice, SECURE_BUFFER_SIZE); +Out_free_ctx: + res = amdgpu_cs_ctx_free(sb_ctx.context); + CU_ASSERT_EQUAL(res, 0); +} + +/* ----------------------------------------------------------------- */ + +static void amdgpu_security_alloc_buf_test(void) +{ + amdgpu_bo_handle bo; + amdgpu_va_handle va_handle; + uint64_t bo_mc; + int r; + + /* Test secure buffer allocation in VRAM */ + bo = gpu_mem_alloc(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_ENCRYPTED, + &bo_mc, &va_handle); + + r = gpu_mem_free(bo, va_handle, bo_mc, 4096); + CU_ASSERT_EQUAL(r, 0); + + /* Test secure buffer allocation in system memory */ + bo = gpu_mem_alloc(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_CREATE_ENCRYPTED, + &bo_mc, &va_handle); + + r = gpu_mem_free(bo, va_handle, bo_mc, 4096); + CU_ASSERT_EQUAL(r, 0); + + /* Test secure buffer allocation in invisible VRAM */ + bo = gpu_mem_alloc(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_CREATE_ENCRYPTED | + AMDGPU_GEM_CREATE_NO_CPU_ACCESS, + &bo_mc, &va_handle); + + r = gpu_mem_free(bo, va_handle, bo_mc, 4096); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_security_gfx_submission_test(void) +{ + amdgpu_command_submission_write_linear_helper_with_secure(device_handle, + AMDGPU_HW_IP_GFX, + true); +} + +static void amdgpu_security_sdma_submission_test(void) +{ + amdgpu_command_submission_write_linear_helper_with_secure(device_handle, + AMDGPU_HW_IP_DMA, + true); +} + +/* ----------------------------------------------------------------- */ + +CU_TestInfo security_tests[] = { + { "allocate secure buffer test", amdgpu_security_alloc_buf_test }, + { "graphics secure command submission", amdgpu_security_gfx_submission_test }, + { "sDMA secure command submission", amdgpu_security_sdma_submission_test }, + { SECURE_BOUNCE_TEST_STR, amdgpu_secure_bounce }, + CU_TEST_INFO_NULL, +}; + +CU_BOOL suite_security_tests_enable(void) +{ + CU_BOOL enable = CU_TRUE; + + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle)) + return CU_FALSE; + + if (device_handle->info.family_id != AMDGPU_FAMILY_RV) { + printf("\n\nDon't support TMZ (trust memory zone), security suite disabled\n"); + enable = CU_FALSE; + } + + if ((major_version < 3) || + ((major_version == 3) && (minor_version < 37))) { + printf("\n\nDon't support TMZ (trust memory zone), kernel DRM version (%d.%d)\n", + major_version, minor_version); + printf("is older, security suite disabled\n"); + enable = CU_FALSE; + } + + if (amdgpu_device_deinitialize(device_handle)) + return CU_FALSE; + + return enable; +} + +int suite_security_tests_init(void) +{ + int res; + + res = amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle); + if (res) { + PRINT_ERROR(res); + return CUE_SINIT_FAILED; + } + + res = amdgpu_query_hw_ip_info(device_handle, + AMDGPU_HW_IP_DMA, + 0, &sdma_info); + if (res) { + PRINT_ERROR(res); + return CUE_SINIT_FAILED; + } + + return CUE_SUCCESS; +} + +int suite_security_tests_clean(void) +{ + int res; + + res = amdgpu_device_deinitialize(device_handle); + if (res) + return CUE_SCLEAN_FAILED; + + return CUE_SUCCESS; +} diff -Nru libdrm-2.4.102/tests/amdgpu/syncobj_tests.c libdrm-2.4.105/tests/amdgpu/syncobj_tests.c --- libdrm-2.4.102/tests/amdgpu/syncobj_tests.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/syncobj_tests.c 2021-04-07 14:09:24.179843000 +0000 @@ -99,7 +99,7 @@ uint32_t expired; int i, r; uint64_t seq_no; - static uint32_t *ptr; + uint32_t *ptr; r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); diff -Nru libdrm-2.4.102/tests/amdgpu/vce_tests.c libdrm-2.4.105/tests/amdgpu/vce_tests.c --- libdrm-2.4.102/tests/amdgpu/vce_tests.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/vce_tests.c 2021-04-07 14:09:24.179843000 +0000 @@ -96,7 +96,7 @@ CU_BOOL suite_vce_tests_enable(void) { - uint32_t version, feature; + uint32_t version, feature, asic_id; CU_BOOL ret_mv = CU_FALSE; if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, @@ -107,6 +107,7 @@ chip_rev = device_handle->info.chip_rev; chip_id = device_handle->info.chip_external_rev; ids_flags = device_handle->info.ids_flags; + asic_id = device_handle->info.asic_id; amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0, 0, &version, &feature); @@ -114,7 +115,8 @@ if (amdgpu_device_deinitialize(device_handle)) return CU_FALSE; - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI || + asic_is_arcturus(asic_id)) { printf("\n\nThe ASIC NOT support VCE, suite disabled\n"); return CU_FALSE; } diff -Nru libdrm-2.4.102/tests/amdgpu/vcn_tests.c libdrm-2.4.105/tests/amdgpu/vcn_tests.c --- libdrm-2.4.102/tests/amdgpu/vcn_tests.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/vcn_tests.c 2021-04-07 14:09:24.179843000 +0000 @@ -56,7 +56,11 @@ static uint32_t major_version; static uint32_t minor_version; static uint32_t family_id; +static uint32_t chip_rev; +static uint32_t chip_id; static uint32_t asic_id; +static uint32_t chip_rev; +static uint32_t chip_id; static amdgpu_context_handle context_handle; static amdgpu_bo_handle ib_handle; @@ -90,6 +94,8 @@ CU_BOOL suite_vcn_tests_enable(void) { + struct drm_amdgpu_info_hw_ip info; + int r; if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, &device_handle)) @@ -97,18 +103,30 @@ family_id = device_handle->info.family_id; asic_id = device_handle->info.asic_id; + chip_rev = device_handle->info.chip_rev; + chip_id = device_handle->info.chip_external_rev; + + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_DEC, 0, &info); if (amdgpu_device_deinitialize(device_handle)) return CU_FALSE; - - if (family_id < AMDGPU_FAMILY_RV) { + if (r != 0 || !info.available_rings || + (family_id < AMDGPU_FAMILY_RV && + (family_id == AMDGPU_FAMILY_AI && + chip_id != (chip_rev + 0x32)))) { /* Arcturus */ printf("\n\nThe ASIC NOT support VCN, suite disabled\n"); return CU_FALSE; } + if (family_id == AMDGPU_FAMILY_AI) { + amdgpu_set_test_active("VCN Tests", "VCN ENC create", CU_FALSE); + amdgpu_set_test_active("VCN Tests", "VCN ENC decode", CU_FALSE); + amdgpu_set_test_active("VCN Tests", "VCN ENC destroy", CU_FALSE); + } + if (family_id == AMDGPU_FAMILY_RV) { - if (asic_id == 0x1636) { + if (chip_id >= (chip_rev + 0x91)) { reg.data0 = 0x504; reg.data1 = 0x505; reg.cmd = 0x503; @@ -122,11 +140,28 @@ reg.cntl = 0x81c6; } } else if (family_id == AMDGPU_FAMILY_NV) { - reg.data0 = 0x504; - reg.data1 = 0x505; - reg.cmd = 0x503; - reg.nop = 0x53f; - reg.cntl = 0x506; + if (chip_id == (chip_rev + 0x28) || + chip_id == (chip_rev + 0x32) || + chip_id == (chip_rev + 0x3c)) { + reg.data0 = 0x10; + reg.data1 = 0x11; + reg.cmd = 0xf; + reg.nop = 0x29; + reg.cntl = 0x26d; + } + else { + reg.data0 = 0x504; + reg.data1 = 0x505; + reg.cmd = 0x503; + reg.nop = 0x53f; + reg.cntl = 0x506; + } + } else if (family_id == AMDGPU_FAMILY_AI) { + reg.data0 = 0x10; + reg.data1 = 0x11; + reg.cmd = 0xf; + reg.nop = 0x29; + reg.cntl = 0x26d; } else return CU_FALSE; diff -Nru libdrm-2.4.102/tests/amdgpu/vm_tests.c libdrm-2.4.105/tests/amdgpu/vm_tests.c --- libdrm-2.4.102/tests/amdgpu/vm_tests.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/amdgpu/vm_tests.c 2021-04-07 14:09:24.179843000 +0000 @@ -104,6 +104,14 @@ amdgpu_bo_list_handle bo_list; amdgpu_va_handle va_handle; static uint32_t *ptr; + struct amdgpu_gpu_info gpu_info = {0}; + unsigned gc_ip_type; + + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + + gc_ip_type = (asic_is_arcturus(gpu_info.asic_id)) ? + AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX; r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); @@ -133,7 +141,7 @@ ib_info.size = 16; memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); - ibs_request.ip_type = AMDGPU_HW_IP_GFX; + ibs_request.ip_type = gc_ip_type; ibs_request.ring = 0; ibs_request.number_of_ibs = 1; ibs_request.ibs = &ib_info; @@ -146,7 +154,7 @@ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); fence_status.context = context_handle; - fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_type = gc_ip_type; fence_status.ip_instance = 0; fence_status.ring = 0; fence_status.fence = ibs_request.seq_no; diff -Nru libdrm-2.4.102/tests/etnaviv/etnaviv_2d_test.c libdrm-2.4.105/tests/etnaviv/etnaviv_2d_test.c --- libdrm-2.4.102/tests/etnaviv/etnaviv_2d_test.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/etnaviv/etnaviv_2d_test.c 2021-04-07 14:09:24.179843000 +0000 @@ -147,6 +147,27 @@ etna_set_state(stream, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_PE2D); } +int etna_check_image(uint32_t *p, int width, int height) +{ + int i; + uint32_t expected; + + for (i = 0; i < width * height; i++) { + if (i%8 < 4 && i%(width*8) < width*4 && i%width < 8*16 && i < width*8*16) + expected = 0xff40ff40; + else + expected = 0x00000000; + + if (p[i] != expected) { + fprintf(stderr, "Offset %d: expected: 0x%08x, got: 0x%08x\n", + i, expected, p[i]); + return -1; + } + } + + return 0; +} + int main(int argc, char *argv[]) { const int width = 256; @@ -161,10 +182,19 @@ drmVersionPtr version; int fd, ret = 0; + uint64_t feat; + int core = 0; + + if (argc < 2) { + fprintf(stderr, "Usage: %s /dev/dri/ []\n", argv[0]); + return 1; + } fd = open(argv[1], O_RDWR); - if (fd < 0) + if (fd < 0) { + perror(argv[1]); return 1; + } version = drmGetVersion(fd); if (version) { @@ -178,25 +208,44 @@ dev = etna_device_new(fd); if (!dev) { + perror("etna_device_new"); ret = 2; goto out; } - /* TODO: we assume that core 0 is a 2D capable one */ - gpu = etna_gpu_new(dev, 0); - if (!gpu) { - ret = 3; - goto out_device; - } + do { + gpu = etna_gpu_new(dev, core); + if (!gpu) { + perror("etna_gpu_new"); + ret = 3; + goto out_device; + } + + if (etna_gpu_get_param(gpu, ETNA_GPU_FEATURES_0, &feat)) { + perror("etna_gpu_get_param"); + ret = 4; + goto out_device; + } + + if ((feat & (1 << 9)) == 0) { + /* GPU not 2D capable. */ + etna_gpu_del(gpu); + gpu = NULL; + } + + core++; + } while (!gpu); pipe = etna_pipe_new(gpu, ETNA_PIPE_2D); if (!pipe) { + perror("etna_pipe_new"); ret = 4; goto out_gpu; } bmp = etna_bo_new(dev, bmp_size, ETNA_BO_UNCACHED); if (!bmp) { + perror("etna_bo_new"); ret = 5; goto out_pipe; } @@ -204,6 +253,7 @@ stream = etna_cmd_stream_new(pipe, 0x300, NULL, NULL); if (!stream) { + perror("etna_cmd_stream_new"); ret = 6; goto out_bo; } @@ -213,7 +263,11 @@ etna_cmd_stream_finish(stream); - bmp_dump32(etna_bo_map(bmp), width, height, false, "/tmp/etna.bmp"); + if (argc > 2) + bmp_dump32(etna_bo_map(bmp), width, height, false, argv[2]); + + if (etna_check_image(etna_bo_map(bmp), width, height)) + ret = 7; etna_cmd_stream_del(stream); diff -Nru libdrm-2.4.102/tests/modetest/modetest.c libdrm-2.4.105/tests/modetest/modetest.c --- libdrm-2.4.102/tests/modetest/modetest.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/modetest/modetest.c 2021-04-07 14:09:24.183843000 +0000 @@ -457,7 +457,7 @@ if (connector->count_modes) { printf(" modes:\n"); printf("\tindex name refresh (Hz) hdisp hss hse htot vdisp " - "vss vse vtot)\n"); + "vss vse vtot\n"); for (j = 0; j < connector->count_modes; j++) dump_mode(&connector->modes[j], j); } diff -Nru libdrm-2.4.102/tests/util/kms.c libdrm-2.4.105/tests/util/kms.c --- libdrm-2.4.102/tests/util/kms.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/util/kms.c 2021-04-07 14:09:24.183843000 +0000 @@ -147,6 +147,9 @@ "stm", "sun4i-drm", "armada-drm", + "komeda", + "imx-dcss", + "mxsfb-drm", }; int util_open(const char *device, const char *module) diff -Nru libdrm-2.4.102/tests/util/pattern.c libdrm-2.4.105/tests/util/pattern.c --- libdrm-2.4.102/tests/util/pattern.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/tests/util/pattern.c 2021-04-07 14:09:24.183843000 +0000 @@ -985,7 +985,6 @@ unsigned int stride) { const struct util_rgb_info *rgb = &info->rgb; - void *mem_base = mem; unsigned int x, y; /* TODO: Give this actual fp16 precision */ @@ -1113,7 +1112,7 @@ unsigned int width, unsigned int height, unsigned int stride) { - int i, j; + unsigned int i, j; for (i = 0; i < height / 2; i++) { uint32_t *row = mem; @@ -1141,7 +1140,7 @@ unsigned int width, unsigned int height, unsigned int stride) { - int i, j; + unsigned int i, j; for (i = 0; i < height / 2; i++) { uint64_t *row = mem; diff -Nru libdrm-2.4.102/xf86drm.c libdrm-2.4.105/xf86drm.c --- libdrm-2.4.102/xf86drm.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/xf86drm.c 2021-04-07 14:09:24.183843000 +0000 @@ -124,6 +124,22 @@ static bool drmNodeIsDRM(int maj, int min); static char *drmGetMinorNameForFD(int fd, int type); +static unsigned log2_int(unsigned x) +{ + unsigned l; + + if (x < 2) { + return 0; + } + for (l = 2; ; l++) { + if ((unsigned)(1 << l) > x) { + return l - 1; + } + } + return 0; +} + + drm_public void drmSetServerInfo(drmServerInfoPtr info) { drm_server_info = info; @@ -696,7 +712,7 @@ int retcode; sprintf(proc_name, "/proc/dri/%d/name", i); - if ((fd = open(proc_name, 0, 0)) >= 0) { + if ((fd = open(proc_name, O_RDONLY, 0)) >= 0) { retcode = read(fd, buf, sizeof(buf)-1); close(fd); if (retcode) { @@ -1335,7 +1351,12 @@ retval = drmMalloc(sizeof(*retval)); retval->count = info.count; - retval->list = drmMalloc(info.count * sizeof(*retval->list)); + if (!(retval->list = drmMalloc(info.count * sizeof(*retval->list)))) { + drmFree(retval); + drmFree(info.list); + return NULL; + } + for (i = 0; i < info.count; i++) { retval->list[i].count = info.list[i].count; retval->list[i].size = info.list[i].size; @@ -2822,7 +2843,7 @@ snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device/drm", maj, min); return stat(path, &sbuf) == 0; -#elif __FreeBSD__ +#elif defined(__FreeBSD__) char name[SPECNAMELEN]; if (!devname_r(makedev(maj, min), S_IFCHR, name, sizeof(name))) @@ -2935,7 +2956,7 @@ closedir(sysdir); return NULL; -#elif __FreeBSD__ +#elif defined(__FreeBSD__) struct stat sbuf; char dname[SPECNAMELEN]; const char *mname; @@ -3255,7 +3276,7 @@ info->func = pinfo.func; return 0; -#elif __FreeBSD__ +#elif defined(__FreeBSD__) return get_sysctl_pci_bus_info(maj, min, info); #else #warning "Missing implementation of drmParsePciBusInfo" @@ -3424,7 +3445,7 @@ device->subdevice_id = pinfo.subdevice_id; return 0; -#elif __FreeBSD__ +#elif defined(__FreeBSD__) drmPciBusInfo info; struct pci_conf_io pc; struct pci_match_conf patterns[1]; @@ -4001,7 +4022,7 @@ for (j = i + 1; j < count; j++) { if (drmDevicesEqual(local_devices[i], local_devices[j])) { local_devices[i]->available_nodes |= local_devices[j]->available_nodes; - node_type = log2(local_devices[j]->available_nodes); + node_type = log2_int(local_devices[j]->available_nodes); memcpy(local_devices[i]->nodes[node_type], local_devices[j]->nodes[node_type], drmGetMaxNodeName()); drmFreeDevice(&local_devices[j]); @@ -4256,6 +4277,10 @@ } closedir(sysdir); + + if (devices != NULL) + return MIN2(device_count, max_devices); + return device_count; } @@ -4302,7 +4327,7 @@ free(value); return strdup(path); -#elif __FreeBSD__ +#elif defined(__FreeBSD__) return drmGetDeviceNameFromFd(fd); #else struct stat sbuf; diff -Nru libdrm-2.4.102/xf86drm.h libdrm-2.4.105/xf86drm.h --- libdrm-2.4.102/xf86drm.h 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/xf86drm.h 2021-04-07 14:09:24.183843000 +0000 @@ -813,6 +813,24 @@ extern char *drmGetDeviceNameFromFd2(int fd); extern int drmGetNodeTypeFromFd(int fd); +/* Convert between GEM handles and DMA-BUF file descriptors. + * + * Warning: since GEM handles are not reference-counted and are unique per + * DRM file description, the caller is expected to perform its own reference + * counting. drmPrimeFDToHandle is guaranteed to return the same handle for + * different FDs if they reference the same underlying buffer object. This + * could even be a buffer object originally created on the same DRM FD. + * + * When sharing a DRM FD with an API such as EGL or GBM, the caller must not + * use drmPrimeHandleToFD nor drmPrimeFDToHandle. A single user-space + * reference-counting implementation is necessary to avoid double-closing GEM + * handles. + * + * Two processes can't share the same DRM FD and both use it to create or + * import GEM handles, even when using a single user-space reference-counting + * implementation like GBM, because GBM doesn't share its state between + * processes. + */ extern int drmPrimeHandleToFD(int fd, uint32_t handle, uint32_t flags, int *prime_fd); extern int drmPrimeFDToHandle(int fd, int prime_fd, uint32_t *handle); diff -Nru libdrm-2.4.102/xf86drmMode.c libdrm-2.4.105/xf86drmMode.c --- libdrm-2.4.102/xf86drmMode.c 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/xf86drmMode.c 2021-04-07 14:09:24.183843000 +0000 @@ -33,11 +33,6 @@ * */ -/* - * TODO the types we are after are defined in different headers on different - * platforms find which headers to include to get uint32_t - */ - #include #include #include @@ -151,6 +146,16 @@ * ModeSetting functions. */ +drm_public int drmIsKMS(int fd) +{ + struct drm_mode_card_res res = {0}; + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res) != 0) + return 0; + + return res.count_crtcs > 0 && res.count_connectors > 0 && res.count_encoders > 0; +} + drm_public drmModeResPtr drmModeGetResources(int fd) { struct drm_mode_card_res res, counts; @@ -284,8 +289,10 @@ memcpy(f.handles, bo_handles, 4 * sizeof(bo_handles[0])); memcpy(f.pitches, pitches, 4 * sizeof(pitches[0])); memcpy(f.offsets, offsets, 4 * sizeof(offsets[0])); - if (modifier) + if (modifier) { + f.flags |= DRM_MODE_FB_MODIFIERS; memcpy(f.modifier, modifier, 4 * sizeof(modifier[0])); + } if ((ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_ADDFB2, &f))) return ret; diff -Nru libdrm-2.4.102/xf86drmMode.h libdrm-2.4.105/xf86drmMode.h --- libdrm-2.4.102/xf86drmMode.h 2020-05-26 20:37:16.000000000 +0000 +++ libdrm-2.4.105/xf86drmMode.h 2021-04-07 14:09:24.183843000 +0000 @@ -41,15 +41,13 @@ #endif #include +#include #include #include /* * This is the interface for modesetting for drm. * - * In order to use this interface you must include either or another - * header defining uint32_t, int32_t and uint16_t. - * * It aims to provide a randr1.2 compatible interface for modesettings in the * kernel, the interface is also meant to be used by libraries like EGL. * @@ -62,121 +60,6 @@ */ /* - * If we pickup an old version of drm.h which doesn't include drm_mode.h - * we should redefine defines. This is so that builds doesn't breaks with - * new libdrm on old kernels. - */ -#ifndef _DRM_MODE_H - -#define DRM_DISPLAY_INFO_LEN 32 -#define DRM_CONNECTOR_NAME_LEN 32 -#define DRM_DISPLAY_MODE_LEN 32 -#define DRM_PROP_NAME_LEN 32 - -#define DRM_MODE_TYPE_BUILTIN (1<<0) -#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) -#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) -#define DRM_MODE_TYPE_PREFERRED (1<<3) -#define DRM_MODE_TYPE_DEFAULT (1<<4) -#define DRM_MODE_TYPE_USERDEF (1<<5) -#define DRM_MODE_TYPE_DRIVER (1<<6) - -/* Video mode flags */ -/* bit compatible with the xorg definitions. */ -#define DRM_MODE_FLAG_PHSYNC (1<<0) -#define DRM_MODE_FLAG_NHSYNC (1<<1) -#define DRM_MODE_FLAG_PVSYNC (1<<2) -#define DRM_MODE_FLAG_NVSYNC (1<<3) -#define DRM_MODE_FLAG_INTERLACE (1<<4) -#define DRM_MODE_FLAG_DBLSCAN (1<<5) -#define DRM_MODE_FLAG_CSYNC (1<<6) -#define DRM_MODE_FLAG_PCSYNC (1<<7) -#define DRM_MODE_FLAG_NCSYNC (1<<8) -#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ -#define DRM_MODE_FLAG_BCAST (1<<10) -#define DRM_MODE_FLAG_PIXMUX (1<<11) -#define DRM_MODE_FLAG_DBLCLK (1<<12) -#define DRM_MODE_FLAG_CLKDIV2 (1<<13) -#define DRM_MODE_FLAG_3D_MASK (0x1f<<14) -#define DRM_MODE_FLAG_3D_NONE (0<<14) -#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14) -#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14) -#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14) -#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14) -#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14) -#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14) -#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) -#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) - -/* DPMS flags */ -/* bit compatible with the xorg definitions. */ -#define DRM_MODE_DPMS_ON 0 -#define DRM_MODE_DPMS_STANDBY 1 -#define DRM_MODE_DPMS_SUSPEND 2 -#define DRM_MODE_DPMS_OFF 3 - -/* Scaling mode options */ -#define DRM_MODE_SCALE_NON_GPU 0 -#define DRM_MODE_SCALE_FULLSCREEN 1 -#define DRM_MODE_SCALE_NO_SCALE 2 -#define DRM_MODE_SCALE_ASPECT 3 - -/* Dithering mode options */ -#define DRM_MODE_DITHERING_OFF 0 -#define DRM_MODE_DITHERING_ON 1 - -#define DRM_MODE_ENCODER_NONE 0 -#define DRM_MODE_ENCODER_DAC 1 -#define DRM_MODE_ENCODER_TMDS 2 -#define DRM_MODE_ENCODER_LVDS 3 -#define DRM_MODE_ENCODER_TVDAC 4 -#define DRM_MODE_ENCODER_VIRTUAL 5 -#define DRM_MODE_ENCODER_DSI 6 -#define DRM_MODE_ENCODER_DPMST 7 -#define DRM_MODE_ENCODER_DPI 8 - -#define DRM_MODE_SUBCONNECTOR_Automatic 0 -#define DRM_MODE_SUBCONNECTOR_Unknown 0 -#define DRM_MODE_SUBCONNECTOR_DVID 3 -#define DRM_MODE_SUBCONNECTOR_DVIA 4 -#define DRM_MODE_SUBCONNECTOR_Composite 5 -#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 -#define DRM_MODE_SUBCONNECTOR_Component 8 -#define DRM_MODE_SUBCONNECTOR_SCART 9 - -#define DRM_MODE_CONNECTOR_Unknown 0 -#define DRM_MODE_CONNECTOR_VGA 1 -#define DRM_MODE_CONNECTOR_DVII 2 -#define DRM_MODE_CONNECTOR_DVID 3 -#define DRM_MODE_CONNECTOR_DVIA 4 -#define DRM_MODE_CONNECTOR_Composite 5 -#define DRM_MODE_CONNECTOR_SVIDEO 6 -#define DRM_MODE_CONNECTOR_LVDS 7 -#define DRM_MODE_CONNECTOR_Component 8 -#define DRM_MODE_CONNECTOR_9PinDIN 9 -#define DRM_MODE_CONNECTOR_DisplayPort 10 -#define DRM_MODE_CONNECTOR_HDMIA 11 -#define DRM_MODE_CONNECTOR_HDMIB 12 -#define DRM_MODE_CONNECTOR_TV 13 -#define DRM_MODE_CONNECTOR_eDP 14 -#define DRM_MODE_CONNECTOR_VIRTUAL 15 -#define DRM_MODE_CONNECTOR_DSI 16 -#define DRM_MODE_CONNECTOR_DPI 17 -#define DRM_MODE_CONNECTOR_WRITEBACK 18 - -#define DRM_MODE_PROP_PENDING (1<<0) -#define DRM_MODE_PROP_RANGE (1<<1) -#define DRM_MODE_PROP_IMMUTABLE (1<<2) -#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ -#define DRM_MODE_PROP_BLOB (1<<4) - -#define DRM_MODE_CURSOR_BO (1<<0) -#define DRM_MODE_CURSOR_MOVE (1<<1) - -#endif /* _DRM_MODE_H */ - - -/* * Feature defines * * Just because these are defined doesn't mean that the kernel @@ -268,6 +151,11 @@ return property->flags & type; } +static inline uint32_t drmModeGetPropertyType(const drmModePropertyRes *prop) +{ + return prop->flags & (DRM_MODE_PROP_LEGACY_TYPE | DRM_MODE_PROP_EXTENDED_TYPE); +} + typedef struct _drmModeCrtc { uint32_t crtc_id; uint32_t buffer_id; /**< FB id to connect to 0 = disconnect */ @@ -289,6 +177,18 @@ uint32_t possible_clones; } drmModeEncoder, *drmModeEncoderPtr; +/** + * Describes the connector status. + * + * DRM_MODE_CONNECTED means that the connector has a sink plugged in. + * DRM_MODE_DISCONNECTED means the contrary. DRM_MODE_UNKNOWNCONNECTION is used + * when it could be either. + * + * User-space should first try to enable DRM_MODE_CONNECTED connectors and + * ignore other connectors. If there are no DRM_MODE_CONNECTED connectors, + * user-space should then try to probe and enable DRM_MODE_UNKNOWNCONNECTION + * connectors. + */ typedef enum { DRM_MODE_CONNECTED = 1, DRM_MODE_DISCONNECTED = 2, @@ -365,6 +265,13 @@ extern void drmModeFreePlaneResources(drmModePlaneResPtr ptr); /** + * Check whether the DRM node supports Kernel Mode-Setting. + * + * Returns 1 if suitable for KMS, 0 otherwise. + */ +extern int drmIsKMS(int fd); + +/** * Retrieves all of the resources associated with a card. */ extern drmModeResPtr drmModeGetResources(int fd); @@ -548,14 +455,14 @@ typedef struct drmModeLesseeList { uint32_t count; - uint32_t lessees[0]; + uint32_t lessees[]; } drmModeLesseeListRes, *drmModeLesseeListPtr; extern drmModeLesseeListPtr drmModeListLessees(int fd); typedef struct drmModeObjectList { uint32_t count; - uint32_t objects[0]; + uint32_t objects[]; } drmModeObjectListRes, *drmModeObjectListPtr; extern drmModeObjectListPtr drmModeGetLease(int fd);