diff -Nru libdrm-2.4.105/amdgpu/amdgpu.h libdrm-2.4.107/amdgpu/amdgpu.h --- libdrm-2.4.105/amdgpu/amdgpu.h 2021-04-07 14:09:24.163843400 +0000 +++ libdrm-2.4.107/amdgpu/amdgpu.h 2021-07-02 12:49:05.425771700 +0000 @@ -1280,6 +1280,7 @@ */ #define AMDGPU_VA_RANGE_32_BIT 0x1 #define AMDGPU_VA_RANGE_HIGH 0x2 +#define AMDGPU_VA_RANGE_REPLAYABLE 0x4 /** * Allocate virtual address range diff -Nru libdrm-2.4.105/amdgpu/amdgpu_vamgr.c libdrm-2.4.107/amdgpu/amdgpu_vamgr.c --- libdrm-2.4.105/amdgpu/amdgpu_vamgr.c 2021-04-07 14:09:24.163843400 +0000 +++ libdrm-2.4.107/amdgpu/amdgpu_vamgr.c 2021-07-02 12:49:05.425771700 +0000 @@ -69,65 +69,99 @@ pthread_mutex_destroy(&mgr->bo_va_mutex); } -static drm_private uint64_t +static drm_private int +amdgpu_vamgr_subtract_hole(struct amdgpu_bo_va_hole *hole, uint64_t start_va, + uint64_t end_va) +{ + if (start_va > hole->offset && end_va - hole->offset < hole->size) { + struct amdgpu_bo_va_hole *n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); + if (!n) + return -ENOMEM; + + n->size = start_va - hole->offset; + n->offset = hole->offset; + list_add(&n->list, &hole->list); + + hole->size -= (end_va - hole->offset); + hole->offset = end_va; + } else if (start_va > hole->offset) { + hole->size = start_va - hole->offset; + } else if (end_va - hole->offset < hole->size) { + hole->size -= (end_va - hole->offset); + hole->offset = end_va; + } else { + list_del(&hole->list); + free(hole); + } + + return 0; +} + +static drm_private int amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, - uint64_t alignment, uint64_t base_required) + uint64_t alignment, uint64_t base_required, + bool search_from_top, uint64_t *va_out) { struct amdgpu_bo_va_hole *hole, *n; - uint64_t offset = 0, waste = 0; + uint64_t offset = 0; + int ret; alignment = MAX2(alignment, mgr->va_alignment); size = ALIGN(size, mgr->va_alignment); if (base_required % alignment) - return AMDGPU_INVALID_VA_ADDRESS; + return -EINVAL; pthread_mutex_lock(&mgr->bo_va_mutex); - LIST_FOR_EACH_ENTRY_SAFE_REV(hole, n, &mgr->va_holes, list) { - if (base_required) { - if (hole->offset > base_required || - (hole->offset + hole->size) < (base_required + size)) - continue; - waste = base_required - hole->offset; - offset = base_required; - } else { - offset = hole->offset; - waste = offset % alignment; - waste = waste ? alignment - waste : 0; - offset += waste; - if (offset >= (hole->offset + hole->size)) { - continue; + if (!search_from_top) { + LIST_FOR_EACH_ENTRY_SAFE_REV(hole, n, &mgr->va_holes, list) { + if (base_required) { + if (hole->offset > base_required || + (hole->offset + hole->size) < (base_required + size)) + continue; + offset = base_required; + } else { + uint64_t waste = hole->offset % alignment; + waste = waste ? alignment - waste : 0; + offset = hole->offset + waste; + if (offset >= (hole->offset + hole->size) || + size > (hole->offset + hole->size) - offset) { + continue; + } } - } - if (!waste && hole->size == size) { - offset = hole->offset; - list_del(&hole->list); - free(hole); + ret = amdgpu_vamgr_subtract_hole(hole, offset, offset + size); pthread_mutex_unlock(&mgr->bo_va_mutex); - return offset; + *va_out = offset; + return ret; } - if ((hole->size - waste) > size) { - if (waste) { - n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); - n->size = waste; - n->offset = hole->offset; - list_add(&n->list, &hole->list); + } else { + LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) { + if (base_required) { + if (hole->offset > base_required || + (hole->offset + hole->size) < (base_required + size)) + continue; + offset = base_required; + } else { + if (size > hole->size) + continue; + + offset = hole->offset + hole->size - size; + offset -= offset % alignment; + if (offset < hole->offset) { + continue; + } } - hole->size -= (size + waste); - hole->offset += size + waste; - pthread_mutex_unlock(&mgr->bo_va_mutex); - return offset; - } - if ((hole->size - waste) == size) { - hole->size = waste; + + ret = amdgpu_vamgr_subtract_hole(hole, offset, offset + size); pthread_mutex_unlock(&mgr->bo_va_mutex); - return offset; + *va_out = offset; + return ret; } } pthread_mutex_unlock(&mgr->bo_va_mutex); - return AMDGPU_INVALID_VA_ADDRESS; + return -ENOMEM; } static drm_private void @@ -196,6 +230,8 @@ uint64_t flags) { struct amdgpu_bo_va_mgr *vamgr; + bool search_from_top = !!(flags & AMDGPU_VA_RANGE_REPLAYABLE); + int ret; /* Clear the flag when the high VA manager is not initialized */ if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max) @@ -216,21 +252,22 @@ va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); size = ALIGN(size, vamgr->va_alignment); - *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size, - va_base_alignment, va_base_required); + ret = amdgpu_vamgr_find_va(vamgr, size, + va_base_alignment, va_base_required, + search_from_top, va_base_allocated); - if (!(flags & AMDGPU_VA_RANGE_32_BIT) && - (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) { + if (!(flags & AMDGPU_VA_RANGE_32_BIT) && ret) { /* fallback to 32bit address */ if (flags & AMDGPU_VA_RANGE_HIGH) vamgr = &dev->vamgr_high_32; else vamgr = &dev->vamgr_32; - *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size, - va_base_alignment, va_base_required); + ret = amdgpu_vamgr_find_va(vamgr, size, + va_base_alignment, va_base_required, + search_from_top, va_base_allocated); } - if (*va_base_allocated != AMDGPU_INVALID_VA_ADDRESS) { + if (!ret) { struct amdgpu_va* va; va = calloc(1, sizeof(struct amdgpu_va)); if(!va){ @@ -243,11 +280,9 @@ va->range = va_range_type; va->vamgr = vamgr; *va_range_handle = va; - } else { - return -EINVAL; } - return 0; + return ret; } drm_public int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) diff -Nru libdrm-2.4.105/core-symbols.txt libdrm-2.4.107/core-symbols.txt --- libdrm-2.4.105/core-symbols.txt 2021-04-07 14:09:24.163843400 +0000 +++ libdrm-2.4.107/core-symbols.txt 2021-07-02 12:49:05.425771700 +0000 @@ -196,3 +196,5 @@ drmUnmapBufs drmUpdateDrawableInfo drmWaitVBlank +drmGetFormatModifierName +drmGetFormatModifierVendor diff -Nru libdrm-2.4.105/data/amdgpu.ids libdrm-2.4.107/data/amdgpu.ids --- libdrm-2.4.105/data/amdgpu.ids 2021-04-07 14:09:24.163843400 +0000 +++ libdrm-2.4.107/data/amdgpu.ids 2021-07-02 12:49:05.425771700 +0000 @@ -135,7 +135,9 @@ 67C2, 01, AMD Radeon (TM) Pro V7350x2 67C2, 02, AMD Radeon (TM) Pro V7300X 67C4, 00, AMD Radeon (TM) Pro WX 7100 Graphics +67C4, 80, AMD Radeon (TM) E9560/E9565 Graphics 67C7, 00, AMD Radeon (TM) Pro WX 5100 Graphics +67C7, 80, AMD Radeon (TM) Pro E9390 Graphics 67C0, 00, AMD Radeon (TM) Pro WX 7100 Graphics 67D0, 01, AMD Radeon (TM) Pro V7350x2 67D0, 02, AMD Radeon (TM) Pro V7300X @@ -271,9 +273,15 @@ 7340, CF, Radeon RX 5300 7341, 00, AMD Radeon Pro W5500 7347, 00, AMD Radeon Pro W5500M +73A3, 00, AMD Radeon PRO W6800 +73AF, C0, AMD Radeon RX 6900 XT 73BF, C0, AMD Radeon RX 6900 XT 73BF, C1, AMD Radeon RX 6800 XT 73BF, C3, AMD Radeon RX 6800 +73DF, C1, AMD Radeon RX 6700 XT +73DF, C5, AMD Radeon RX 6700 XT +73E1, 00, AMD Radeon PRO W6600M +73E3, 00, AMD Radeon PRO W6600 9874, C4, AMD Radeon R7 Graphics 9874, C5, AMD Radeon R6 Graphics 9874, C6, AMD Radeon R6 Graphics diff -Nru libdrm-2.4.105/debian/changelog libdrm-2.4.107/debian/changelog --- libdrm-2.4.105/debian/changelog 2021-08-19 08:52:23.000000000 +0000 +++ libdrm-2.4.107/debian/changelog 2021-11-03 07:15:14.000000000 +0000 @@ -1,15 +1,67 @@ -libdrm (2.4.105-3~20.04.2) focal; urgency=medium +libdrm (2.4.107-8ubuntu1~20.04.1) focal; urgency=medium - * intel-Add-support-for-ADLP.patch: Add support for ADL-P. (LP: - #1940504) + * Backport to focal. (LP: #1949553) - -- Timo Aaltonen Thu, 19 Aug 2021 11:52:23 +0300 + -- Timo Aaltonen Wed, 03 Nov 2021 09:15:14 +0200 -libdrm (2.4.105-3~20.04.1) focal; urgency=medium +libdrm (2.4.107-8ubuntu1) impish; urgency=medium - * Backport to focal. (LP: #1923880, #1925320) + * Revert adding static libs, fix flutter. - -- Timo Aaltonen Wed, 19 May 2021 11:15:08 +0300 + -- Timo Aaltonen Tue, 05 Oct 2021 09:12:31 +0300 + +libdrm (2.4.107-8) unstable; urgency=medium + + * rules: Forcibly disable valgrind. + + -- Timo Aaltonen Mon, 27 Sep 2021 20:10:39 +0300 + +libdrm (2.4.107-7) unstable; urgency=medium + + * Drop valgrind support, it's not ready for multi-arch. (Closes: + #994955) + + -- Timo Aaltonen Mon, 27 Sep 2021 14:36:51 +0300 + +libdrm (2.4.107-6) unstable; urgency=medium + + * control: Fix valgrind dependency archs for libdrm-dev. + + -- Timo Aaltonen Thu, 23 Sep 2021 14:09:08 +0300 + +libdrm (2.4.107-5) unstable; urgency=medium + + * control: Add valgrind to libdrm-dev Depends. (Closes: #994873) + + -- Timo Aaltonen Thu, 23 Sep 2021 05:26:53 +0300 + +libdrm (2.4.107-4) unstable; urgency=medium + + * control: Add libpciaccess-dev to -dev Depends, required by + libdrm_intel.pc. + + -- Timo Aaltonen Wed, 22 Sep 2021 11:51:51 +0300 + +libdrm (2.4.107-3) unstable; urgency=medium + + * Include static libs in -dev again. (LP: #1944107) + + -- Timo Aaltonen Tue, 21 Sep 2021 16:52:54 +0300 + +libdrm (2.4.107-2) unstable; urgency=medium + + * Upload to unstable. + + -- Timo Aaltonen Fri, 20 Aug 2021 12:22:03 +0300 + +libdrm (2.4.107-1) experimental; urgency=medium + + * New upstream release. + * revert-set-fb-modifiers-flag.diff: Dropped, upstream. + * control: Add python3-setuptools to build-depends. + * symbols: Updated. + + -- Timo Aaltonen Wed, 04 Aug 2021 13:25:07 +0300 libdrm (2.4.105-3) experimental; urgency=medium diff -Nru libdrm-2.4.105/debian/control libdrm-2.4.107/debian/control --- libdrm-2.4.105/debian/control 2021-08-19 08:52:23.000000000 +0000 +++ libdrm-2.4.107/debian/control 2021-11-03 07:15:14.000000000 +0000 @@ -9,11 +9,12 @@ xsltproc, libx11-dev, pkg-config, + python3-setuptools, xutils-dev (>= 1:7.6+2), libudev-dev [linux-any], libpciaccess-dev, python3-docutils, - valgrind [amd64 armhf i386 mips mipsel powerpc s390x], +# valgrind [amd64 armhf i386 mips mipsel powerpc s390x], Standards-Version: 4.5.0 Section: libs Vcs-Git: https://salsa.debian.org/xorg-team/lib/libdrm @@ -34,6 +35,8 @@ libdrm-exynos1 (= ${binary:Version}) [any-arm], libdrm-tegra0 (= ${binary:Version}) [any-arm arm64], libdrm-etnaviv1 (= ${binary:Version}) [armhf arm64], + libpciaccess-dev, +# valgrind [amd64 armhf i386 mips mipsel powerpc s390x], ${misc:Depends}, Multi-Arch: same Description: Userspace interface to kernel DRM services -- development files diff -Nru libdrm-2.4.105/debian/libdrm2.symbols libdrm-2.4.107/debian/libdrm2.symbols --- libdrm-2.4.105/debian/libdrm2.symbols 2021-08-19 08:52:23.000000000 +0000 +++ libdrm-2.4.107/debian/libdrm2.symbols 2021-11-03 07:15:14.000000000 +0000 @@ -63,6 +63,8 @@ drmGetDevices2@Base 2.4.75 drmGetDevices@Base 2.4.65 drmGetEntry@Base 2.3.1 + drmGetFormatModifierName@Base 2.4.107 + drmGetFormatModifierVendor@Base 2.4.107 drmGetHashTable@Base 2.3.1 drmGetInterruptFromBusID@Base 2.3.1 drmGetLibVersion@Base 2.3.1 diff -Nru libdrm-2.4.105/debian/patches/intel-Add-support-for-ADLP.patch libdrm-2.4.107/debian/patches/intel-Add-support-for-ADLP.patch --- libdrm-2.4.105/debian/patches/intel-Add-support-for-ADLP.patch 2021-08-19 08:52:23.000000000 +0000 +++ libdrm-2.4.107/debian/patches/intel-Add-support-for-ADLP.patch 1970-01-01 00:00:00.000000000 +0000 @@ -1,63 +0,0 @@ -From 4c8365183ec52e9309ecae45c725aa315562854d Mon Sep 17 00:00:00 2001 -From: Tejas Upadhyay -Date: Mon, 17 May 2021 11:05:29 +0530 -Subject: [PATCH] intel: Add support for ADLP - -Add ADLP platform support and PCIIDs - -Reviewed-by: Lionel Landwerlin -Reviewed-by: Uma Shankar -Signed-off-by: Pankaj Bharadiya -Signed-off-by: Caz Yokoyama -Signed-off-by: Anusha Srivatsa -Signed-off-by: Tejas Upadhyay ---- - intel/i915_pciids.h | 21 +++++++++++++++++++++ - intel/intel_chipset.c | 1 + - 2 files changed, 22 insertions(+) - -diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h -index ebd0dd1c..2448be8c 100644 ---- a/intel/i915_pciids.h -+++ b/intel/i915_pciids.h -@@ -645,4 +645,25 @@ - INTEL_VGA_DEVICE(0x4692, info), \ - INTEL_VGA_DEVICE(0x4693, info) - -+/* ADL-P */ -+#define INTEL_ADLP_IDS(info) \ -+ INTEL_VGA_DEVICE(0x46A0, info), \ -+ INTEL_VGA_DEVICE(0x46A1, info), \ -+ INTEL_VGA_DEVICE(0x46A2, info), \ -+ INTEL_VGA_DEVICE(0x46A3, info), \ -+ INTEL_VGA_DEVICE(0x46A6, info), \ -+ INTEL_VGA_DEVICE(0x46A8, info), \ -+ INTEL_VGA_DEVICE(0x46AA, info), \ -+ INTEL_VGA_DEVICE(0x462A, info), \ -+ INTEL_VGA_DEVICE(0x4626, info), \ -+ INTEL_VGA_DEVICE(0x4628, info), \ -+ INTEL_VGA_DEVICE(0x46B0, info), \ -+ INTEL_VGA_DEVICE(0x46B1, info), \ -+ INTEL_VGA_DEVICE(0x46B2, info), \ -+ INTEL_VGA_DEVICE(0x46B3, info), \ -+ INTEL_VGA_DEVICE(0x46C0, info), \ -+ INTEL_VGA_DEVICE(0x46C1, info), \ -+ INTEL_VGA_DEVICE(0x46C2, info), \ -+ INTEL_VGA_DEVICE(0x46C3, info) -+ - #endif /* _I915_PCIIDS_H */ -diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c -index fda3de1a..f0da6d81 100644 ---- a/intel/intel_chipset.c -+++ b/intel/intel_chipset.c -@@ -35,6 +35,7 @@ static const struct pci_device { - uint16_t gen; - } pciids[] = { - /* Keep ids sorted by gen; latest gen first */ -+ INTEL_ADLP_IDS(12), - INTEL_ADLS_IDS(12), - INTEL_RKL_IDS(12), - INTEL_DG1_IDS(12), --- -2.30.2 - diff -Nru libdrm-2.4.105/debian/patches/revert-set-fb-modifiers-flag.diff libdrm-2.4.107/debian/patches/revert-set-fb-modifiers-flag.diff --- libdrm-2.4.105/debian/patches/revert-set-fb-modifiers-flag.diff 2021-08-19 08:52:23.000000000 +0000 +++ libdrm-2.4.107/debian/patches/revert-set-fb-modifiers-flag.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,29 +0,0 @@ -commit 40f73d0b0b3936ccadc693edc25aad70c1225766 -Author: Bas Nieuwenhuizen -Date: Wed Apr 21 21:31:06 2021 +0200 - - Revert "xf86drmMode: set FB_MODIFIERS flag when modifiers are supplied" - - This reverts commit b362850689d1b0048b7f4641cc236128b5a43773. - - This breaks when the kernel driver does not support modifiers and the - application properly zeroes the modifiers. - - Acked-by: Simon Ser - -diff --git a/xf86drmMode.c b/xf86drmMode.c -index dc177241..c3920b91 100644 ---- a/xf86drmMode.c -+++ b/xf86drmMode.c -@@ -289,10 +289,8 @@ drm_public int drmModeAddFB2WithModifiers(int fd, uint32_t width, - memcpy(f.handles, bo_handles, 4 * sizeof(bo_handles[0])); - memcpy(f.pitches, pitches, 4 * sizeof(pitches[0])); - memcpy(f.offsets, offsets, 4 * sizeof(offsets[0])); -- if (modifier) { -- f.flags |= DRM_MODE_FB_MODIFIERS; -+ if (modifier) - memcpy(f.modifier, modifier, 4 * sizeof(modifier[0])); -- } - - if ((ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_ADDFB2, &f))) - return ret; diff -Nru libdrm-2.4.105/debian/patches/series libdrm-2.4.107/debian/patches/series --- libdrm-2.4.105/debian/patches/series 2021-08-19 08:52:23.000000000 +0000 +++ libdrm-2.4.107/debian/patches/series 2021-11-03 07:15:14.000000000 +0000 @@ -1,4 +1,2 @@ 01_default_perms.diff -revert-set-fb-modifiers-flag.diff Revert-meson-use-library-instead-of-shared_library.patch -intel-Add-support-for-ADLP.patch diff -Nru libdrm-2.4.105/debian/rules libdrm-2.4.107/debian/rules --- libdrm-2.4.105/debian/rules 2021-07-02 13:02:50.000000000 +0000 +++ libdrm-2.4.107/debian/rules 2021-11-03 07:15:14.000000000 +0000 @@ -14,6 +14,7 @@ -Damdgpu=true \ -Dlibkms=false \ -Dinstall-test-programs=true \ + -Dvalgrind=false \ $() # Linux vs. the rest: diff -Nru libdrm-2.4.105/gen_table_fourcc.py libdrm-2.4.107/gen_table_fourcc.py --- libdrm-2.4.105/gen_table_fourcc.py 1970-01-01 00:00:00.000000000 +0000 +++ libdrm-2.4.107/gen_table_fourcc.py 2021-07-02 12:49:05.429105000 +0000 @@ -0,0 +1,84 @@ +#!/usr/bin/env python3 + +# Copyright 2021 Collabora, Ltd. +# +# Permission is hereby granted, free of charge, to any person obtaining +# a copy of this software and associated documentation files (the +# "Software"), to deal in the Software without restriction, including +# without limitation the rights to use, copy, modify, merge, publish, +# distribute, sublicense, and/or sell copies of the Software, and to +# permit persons to whom the Software is furnished to do so, subject to +# the following conditions: +# +# The above copyright notice and this permission notice (including the +# next paragraph) shall be included in all copies or substantial +# portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +# Helper script that reads drm_fourcc.h and writes a static table with the +# simpler format token modifiers + +import sys +import re + +filename = sys.argv[1] +towrite = sys.argv[2] + +fm_re = { + 'intel': r'^#define I915_FORMAT_MOD_(\w+)', + 'others': r'^#define DRM_FORMAT_MOD_((?:ARM|SAMSUNG|QCOM|VIVANTE|NVIDIA|BROADCOM|ALLWINNER)\w+)\s', + 'vendors': r'^#define DRM_FORMAT_MOD_VENDOR_(\w+)' +} + +def print_fm_intel(f, f_mod): + f.write(' {{ DRM_MODIFIER_INTEL({}, {}) }},\n'.format(f_mod, f_mod)) + +# generic write func +def print_fm(f, vendor, mod, f_name): + f.write(' {{ DRM_MODIFIER({}, {}, {}) }},\n'.format(vendor, mod, f_name)) + +with open(filename, "r") as f: + data = f.read() + for k, v in fm_re.items(): + fm_re[k] = re.findall(v, data, flags=re.M) + +with open(towrite, "w") as f: + f.write('''\ +/* AUTOMATICALLY GENERATED by gen_table_fourcc.py. You should modify + that script instead of adding here entries manually! */ +static const struct drmFormatModifierInfo drm_format_modifier_table[] = { +''') + f.write(' { DRM_MODIFIER_INVALID(NONE, INVALID_MODIFIER) },\n') + f.write(' { DRM_MODIFIER_LINEAR(NONE, LINEAR) },\n') + + for entry in fm_re['intel']: + print_fm_intel(f, entry) + + for entry in fm_re['others']: + (vendor, mod) = entry.split('_', 1) + if vendor == 'ARM' and (mod == 'TYPE_AFBC' or mod == 'TYPE_MISC'): + continue + print_fm(f, vendor, mod, mod) + + f.write('''\ +}; +''') + + f.write('''\ +static const struct drmFormatModifierVendorInfo drm_format_modifier_vendor_table[] = { +''') + + for entry in fm_re['vendors']: + f.write(" {{ DRM_FORMAT_MOD_VENDOR_{}, \"{}\" }},\n".format(entry, entry)) + + f.write('''\ +}; +''') diff -Nru libdrm-2.4.105/intel/i915_pciids.h libdrm-2.4.107/intel/i915_pciids.h --- libdrm-2.4.105/intel/i915_pciids.h 2021-04-07 14:09:24.167843300 +0000 +++ libdrm-2.4.107/intel/i915_pciids.h 2021-07-02 12:49:05.435771700 +0000 @@ -645,4 +645,25 @@ INTEL_VGA_DEVICE(0x4692, info), \ INTEL_VGA_DEVICE(0x4693, info) +/* ADL-P */ +#define INTEL_ADLP_IDS(info) \ + INTEL_VGA_DEVICE(0x46A0, info), \ + INTEL_VGA_DEVICE(0x46A1, info), \ + INTEL_VGA_DEVICE(0x46A2, info), \ + INTEL_VGA_DEVICE(0x46A3, info), \ + INTEL_VGA_DEVICE(0x46A6, info), \ + INTEL_VGA_DEVICE(0x46A8, info), \ + INTEL_VGA_DEVICE(0x46AA, info), \ + INTEL_VGA_DEVICE(0x462A, info), \ + INTEL_VGA_DEVICE(0x4626, info), \ + INTEL_VGA_DEVICE(0x4628, info), \ + INTEL_VGA_DEVICE(0x46B0, info), \ + INTEL_VGA_DEVICE(0x46B1, info), \ + INTEL_VGA_DEVICE(0x46B2, info), \ + INTEL_VGA_DEVICE(0x46B3, info), \ + INTEL_VGA_DEVICE(0x46C0, info), \ + INTEL_VGA_DEVICE(0x46C1, info), \ + INTEL_VGA_DEVICE(0x46C2, info), \ + INTEL_VGA_DEVICE(0x46C3, info) + #endif /* _I915_PCIIDS_H */ diff -Nru libdrm-2.4.105/intel/intel_chipset.c libdrm-2.4.107/intel/intel_chipset.c --- libdrm-2.4.105/intel/intel_chipset.c 2021-04-07 14:09:24.171843300 +0000 +++ libdrm-2.4.107/intel/intel_chipset.c 2021-07-02 12:49:05.435771700 +0000 @@ -35,6 +35,7 @@ uint16_t gen; } pciids[] = { /* Keep ids sorted by gen; latest gen first */ + INTEL_ADLP_IDS(12), INTEL_ADLS_IDS(12), INTEL_RKL_IDS(12), INTEL_DG1_IDS(12), diff -Nru libdrm-2.4.105/libkms/vmwgfx.c libdrm-2.4.107/libkms/vmwgfx.c --- libdrm-2.4.105/libkms/vmwgfx.c 2021-04-07 14:09:24.175843200 +0000 +++ libdrm-2.4.107/libkms/vmwgfx.c 2021-07-02 12:49:05.442438400 +0000 @@ -25,6 +25,9 @@ * **************************************************************************/ +#ifdef __FreeBSD__ +#define _WANT_KERNEL_ERRNO +#endif #include #include diff -Nru libdrm-2.4.105/meson.build libdrm-2.4.107/meson.build --- libdrm-2.4.105/meson.build 2021-04-07 14:09:24.175843200 +0000 +++ libdrm-2.4.107/meson.build 2021-07-02 12:49:05.442438400 +0000 @@ -21,9 +21,9 @@ project( 'libdrm', ['c'], - version : '2.4.105', + version : '2.4.107', license : 'MIT', - meson_version : '>= 0.43', + meson_version : '>= 0.46', default_options : ['buildtype=debugoptimized', 'c_std=gnu99'], ) @@ -51,6 +51,11 @@ intel_atomics = false lib_atomics = false +python3 = import('python').find_installation() +format_mod_static_table = custom_target('format_mod_static_table', + output : 'generated_static_table_fourcc.h', input: 'include/drm/drm_fourcc.h', + command : [python3, files('gen_table_fourcc.py'), '@INPUT@', '@OUTPUT@']) + dep_atomic_ops = dependency('atomic_ops', required : false) if cc.links(''' int atomic_add(int *i) { return __sync_add_and_fetch (i, 1); } @@ -300,7 +305,7 @@ 'xf86drm.c', 'xf86drmHash.c', 'xf86drmRandom.c', 'xf86drmSL.c', 'xf86drmMode.c' ), - config_file, + config_file, format_mod_static_table ], c_args : libdrm_c_args, dependencies : [dep_valgrind, dep_rt, dep_m], diff -Nru libdrm-2.4.105/nouveau/nouveau.c libdrm-2.4.107/nouveau/nouveau.c --- libdrm-2.4.105/nouveau/nouveau.c 2021-04-07 14:09:24.175843200 +0000 +++ libdrm-2.4.107/nouveau/nouveau.c 2021-07-02 12:49:05.442438400 +0000 @@ -46,19 +46,35 @@ #include "nvif/ioctl.h" #include "nvif/unpack.h" -#ifdef DEBUG +drm_private FILE *nouveau_out = NULL; drm_private uint32_t nouveau_debug = 0; static void -debug_init(char *args) +debug_init(void) { - if (args) { - int n = strtol(args, NULL, 0); + static bool once = false; + char *debug, *out; + + if (once) + return; + once = true; + + debug = getenv("NOUVEAU_LIBDRM_DEBUG"); + if (debug) { + int n = strtol(debug, NULL, 0); if (n >= 0) nouveau_debug = n; + + } + + nouveau_out = stderr; + out = getenv("NOUVEAU_LIBDRM_OUT"); + if (out) { + FILE *fout = fopen(out, "w"); + if (fout) + nouveau_out = fout; } } -#endif static int nouveau_object_ioctl(struct nouveau_object *obj, void *data, uint32_t size) @@ -327,9 +343,7 @@ struct nouveau_drm *drm; drmVersionPtr ver; -#ifdef DEBUG - debug_init(getenv("NOUVEAU_LIBDRM_DEBUG")); -#endif + debug_init(); if (!(drm = calloc(1, sizeof(*drm)))) return -ENOMEM; diff -Nru libdrm-2.4.105/nouveau/private.h libdrm-2.4.107/nouveau/private.h --- libdrm-2.4.105/nouveau/private.h 2021-04-07 14:09:24.175843200 +0000 +++ libdrm-2.4.107/nouveau/private.h 2021-07-02 12:49:05.445771700 +0000 @@ -1,6 +1,8 @@ #ifndef __NOUVEAU_LIBDRM_PRIVATE_H__ #define __NOUVEAU_LIBDRM_PRIVATE_H__ +#include + #include #include #include @@ -9,18 +11,19 @@ #include "nouveau.h" -#ifdef DEBUG +/* + * 0x00000001 dump all pushbuffers + * 0x00000002 submit pushbuffers synchronously + * 0x80000000 if compiled with SIMULATE return -EINVAL for all pb submissions + */ drm_private extern uint32_t nouveau_debug; +drm_private extern FILE *nouveau_out; #define dbg_on(lvl) (nouveau_debug & (1 << lvl)) #define dbg(lvl, fmt, args...) do { \ if (dbg_on((lvl))) \ - fprintf(stderr, "nouveau: "fmt, ##args); \ + fprintf(nouveau_out, "nouveau: "fmt, ##args); \ } while(0) -#else -#define dbg_on(lvl) (0) -#define dbg(lvl, fmt, args...) -#endif -#define err(fmt, args...) fprintf(stderr, "nouveau: "fmt, ##args) +#define err(fmt, args...) fprintf(nouveau_out, "nouveau: "fmt, ##args) struct nouveau_client_kref { struct drm_nouveau_gem_pushbuf_bo *kref; diff -Nru libdrm-2.4.105/nouveau/pushbuf.c libdrm-2.4.107/nouveau/pushbuf.c --- libdrm-2.4.105/nouveau/pushbuf.c 2021-04-07 14:09:24.175843200 +0000 +++ libdrm-2.4.107/nouveau/pushbuf.c 2021-07-02 12:49:05.445771700 +0000 @@ -292,11 +292,14 @@ kref = krec->buffer + kpsh->bo_index; bo = (void *)(unsigned long)kref->user_priv; bgn = (uint32_t *)((char *)bo->map + kpsh->offset); - end = bgn + (kpsh->length /4); + end = bgn + ((kpsh->length & 0x7fffff) /4); - err("ch%d: psh %08x %010llx %010llx\n", chid, kpsh->bo_index, + err("ch%d: psh %s%08x %010llx %010llx\n", chid, + bo->map ? "" : "(unmapped) ", kpsh->bo_index, (unsigned long long)kpsh->offset, (unsigned long long)(kpsh->offset + kpsh->length)); + if (!bo->map) + continue; while (bgn < end) err("\t0x%08x\n", *bgn++); } @@ -336,6 +339,8 @@ req.suffix0 = nvpb->suffix0; req.suffix1 = nvpb->suffix1; req.vram_available = 0; /* for valgrind */ + if (dbg_on(1)) + req.vram_available |= NOUVEAU_GEM_PUSHBUF_SYNC; req.gart_available = 0; if (dbg_on(0)) diff -Nru libdrm-2.4.105/README.rst libdrm-2.4.107/README.rst --- libdrm-2.4.105/README.rst 2021-04-07 14:09:24.159843400 +0000 +++ libdrm-2.4.107/README.rst 2021-07-02 12:49:05.422438400 +0000 @@ -13,6 +13,24 @@ libdrm is a low-level library, typically used by graphics drivers such as the Mesa drivers, the X drivers, libva and similar projects. +Syncing with the Linux kernel headers +------------------------------------- + +The library should be regularly updated to match the recent changes in the +`include/uapi/drm/`. + +libdrm maintains a human-readable version for the token format modifier, with +the simpler ones being extracted automatically from `drm_fourcc.h` header file +with the help of a python script. This might not always possible, as some of +the vendors require decoding/extracting them programmatically. For that +reason one can enhance the current vendor functions to include/provide the +newly added token formats, or, in case there's no such decoding +function, to add one that performs the tasks of extracting them. + +For simpler format modifier tokens there's a script (gen_table_fourcc.py) that +creates a static table, by going over `drm_fourcc.h` header file. The script +could be further modified if it can't handle new (simpler) token format +modifiers instead of the generated static table. Compiling --------- diff -Nru libdrm-2.4.105/tests/amdgpu/amdgpu_test.c libdrm-2.4.107/tests/amdgpu/amdgpu_test.c --- libdrm-2.4.105/tests/amdgpu/amdgpu_test.c 2021-04-07 14:09:24.175843200 +0000 +++ libdrm-2.4.107/tests/amdgpu/amdgpu_test.c 2021-07-02 12:49:05.449105300 +0000 @@ -37,6 +37,18 @@ #include #include #include +#ifdef __linux__ +#include +#elif __FreeBSD__ +/* SPECNAMELEN in FreeBSD is defined here: */ +#include +#endif +#ifdef MAJOR_IN_MKDEV +#include +#endif +#ifdef MAJOR_IN_SYSMACROS +#include +#endif #include "drm.h" #include "xf86drmMode.h" @@ -59,6 +71,7 @@ #define RAS_TESTS_STR "RAS Tests" #define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests" #define SECURITY_TESTS_STR "Security Tests" +#define HOTUNPLUG_TESTS_STR "Hotunplug Tests" /** * Open handles for amdgpu devices @@ -137,6 +150,12 @@ .pCleanupFunc = suite_security_tests_clean, .pTests = security_tests, }, + { + .pName = HOTUNPLUG_TESTS_STR, + .pInitFunc = suite_hotunplug_tests_init, + .pCleanupFunc = suite_hotunplug_tests_clean, + .pTests = hotunplug_tests, + }, CU_SUITE_INFO_NULL, }; @@ -198,6 +217,10 @@ .pName = SECURITY_TESTS_STR, .pActive = suite_security_tests_enable, }, + { + .pName = HOTUNPLUG_TESTS_STR, + .pActive = suite_hotunplug_tests_enable, + }, }; @@ -339,12 +362,13 @@ /* Close AMD devices. */ -static void amdgpu_close_devices() +void amdgpu_close_devices() { int i; for (i = 0; i < MAX_CARDS_SUPPORTED; i++) - if (drm_amdgpu[i] >=0) + if (drm_amdgpu[i] >=0) { close(drm_amdgpu[i]); + } } /* Print AMD devices information */ @@ -430,7 +454,8 @@ { amdgpu_device_handle device_handle; uint32_t major_version, minor_version, family_id; - int i; + drmDevicePtr devices[MAX_CARDS_SUPPORTED]; + int i, drm_count; int size = sizeof(suites_active_stat) / sizeof(suites_active_stat[0]); if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, @@ -442,6 +467,8 @@ if (amdgpu_device_deinitialize(device_handle)) return; + drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED); + /* Set active status for suites based on their policies */ for (i = 0; i < size; ++i) if (amdgpu_set_suite_active(suites_active_stat[i].pName, @@ -496,6 +523,9 @@ "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + if (amdgpu_set_test_active(BASIC_TESTS_STR, "bo eviction Test", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + /* This test was ran on GFX8 and GFX9 only */ if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV) if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency Test", CU_FALSE)) @@ -518,6 +548,84 @@ //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) if (amdgpu_set_test_active(BASIC_TESTS_STR, "GPU reset Test", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + + /* You need at least 2 devices for this */ + if (drm_count < 2) + if (amdgpu_set_test_active(HOTUNPLUG_TESTS_STR, "Unplug with exported fence", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); +} + +int test_device_index; + +int amdgpu_open_device_on_test_index(int render_node) +{ + int i; + + if (amdgpu_open_devices(open_render_node) <= 0) { + perror("Cannot open AMDGPU device"); + return -1; + } + + if (test_device_index >= 0) { + /* Most tests run on device of drm_amdgpu[0]. + * Swap the chosen device to drm_amdgpu[0]. + */ + i = drm_amdgpu[0]; + drm_amdgpu[0] = drm_amdgpu[test_device_index]; + drm_amdgpu[test_device_index] = i; + } + + return 0; + + +} + + +static bool amdgpu_node_is_drm(int maj, int min) +{ +#ifdef __linux__ + char path[64]; + struct stat sbuf; + + snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device/drm", + maj, min); + return stat(path, &sbuf) == 0; +#elif defined(__FreeBSD__) + char name[SPECNAMELEN]; + + if (!devname_r(makedev(maj, min), S_IFCHR, name, sizeof(name))) + return 0; + /* Handle drm/ and dri/ as both are present in different FreeBSD version + * FreeBSD on amd64/i386/powerpc external kernel modules create node in + * in /dev/drm/ and links in /dev/dri while a WIP in kernel driver creates + * only device nodes in /dev/dri/ */ + return (!strncmp(name, "drm/", 4) || !strncmp(name, "dri/", 4)); +#else + return maj == DRM_MAJOR; +#endif +} + +char *amdgpu_get_device_from_fd(int fd) +{ +#ifdef __linux__ + struct stat sbuf; + char path[PATH_MAX + 1]; + unsigned int maj, min; + + if (fstat(fd, &sbuf)) + return NULL; + + maj = major(sbuf.st_rdev); + min = minor(sbuf.st_rdev); + + if (!amdgpu_node_is_drm(maj, min) || !S_ISCHR(sbuf.st_mode)) + return NULL; + + snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device", maj, min); + return strdup(path); +#else + return NULL; +#endif } /* The main() function for setting up and running the tests. @@ -535,7 +643,6 @@ int display_devices = 0;/* By default not to display devices' info */ CU_pSuite pSuite = NULL; CU_pTest pTest = NULL; - int test_device_index; int display_list = 0; int force_run = 0; diff -Nru libdrm-2.4.105/tests/amdgpu/amdgpu_test.h libdrm-2.4.107/tests/amdgpu/amdgpu_test.h --- libdrm-2.4.105/tests/amdgpu/amdgpu_test.h 2021-04-07 14:09:24.175843200 +0000 +++ libdrm-2.4.107/tests/amdgpu/amdgpu_test.h 2021-07-02 12:49:05.449105300 +0000 @@ -273,6 +273,29 @@ unsigned ip_type, bool secure); + + +/** + * Initialize hotunplug test suite + */ +int suite_hotunplug_tests_init(); + +/** + * Deinitialize hotunplug test suite + */ +int suite_hotunplug_tests_clean(); + +/** + * Decide if the suite is enabled by default or not. + */ +CU_BOOL suite_hotunplug_tests_enable(void); + +/** + * Tests in uvd enc test suite + */ +extern CU_TestInfo hotunplug_tests[]; + + /** * Helper functions */ @@ -449,13 +472,18 @@ return r; } -static inline bool asic_is_arcturus(uint32_t asic_id) + +static inline bool asic_is_gfx_pipe_removed(uint32_t family_id, uint32_t chip_id, uint32_t chip_rev) { - switch(asic_id) { - /* Arcturus asic DID */ - case 0x738C: - case 0x7388: - case 0x738E: + + if (family_id != AMDGPU_FAMILY_AI) + return false; + + switch (chip_id - chip_rev) { + /* Arcturus */ + case 0x32: + /* Aldebaran */ + case 0x3c: return true; default: return false; @@ -471,4 +499,8 @@ struct amdgpu_cs_request *ibs_request, bool secure); +void amdgpu_close_devices(); +int amdgpu_open_device_on_test_index(int render_node); +char *amdgpu_get_device_from_fd(int fd); + #endif /* #ifdef _AMDGPU_TEST_H_ */ diff -Nru libdrm-2.4.105/tests/amdgpu/basic_tests.c libdrm-2.4.107/tests/amdgpu/basic_tests.c --- libdrm-2.4.105/tests/amdgpu/basic_tests.c 2021-04-07 14:09:24.175843200 +0000 +++ libdrm-2.4.107/tests/amdgpu/basic_tests.c 2021-07-02 12:49:05.449105300 +0000 @@ -46,6 +46,8 @@ static uint32_t major_version; static uint32_t minor_version; static uint32_t family_id; +static uint32_t chip_id; +static uint32_t chip_rev; static void amdgpu_query_info_test(void); static void amdgpu_command_submission_gfx(void); @@ -341,9 +343,10 @@ }; static const uint32_t bufferclear_cs_shader_gfx9[] = { - 0xD1FD0000, 0x04010C08, 0x7E020204, 0x7E040205, - 0x7E060206, 0x7E080207, 0xE01C2000, 0x80000100, - 0xBF810000 + 0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08, + 0x7e020280, 0x7e040204, 0x7e060205, 0x7e080206, + 0x7e0a0207, 0xe01c2000, 0x80000200, 0xbf8c0000, + 0xbf810000 }; static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = { @@ -357,8 +360,9 @@ static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5; static const uint32_t buffercopy_cs_shader_gfx9[] = { - 0xD1FD0000, 0x04010C08, 0xE00C2000, 0x80000100, - 0xBF8C0F70, 0xE01C2000, 0x80010100, 0xBF810000 + 0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08, + 0x7e020280, 0xe00c2000, 0x80000200, 0xbf8c0f70, + 0xe01c2000, 0x80010200, 0xbf810000 }; static const uint32_t preamblecache_gfx9[] = { @@ -617,19 +621,21 @@ CU_BOOL suite_basic_tests_enable(void) { - uint32_t asic_id; if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, &device_handle)) return CU_FALSE; - asic_id = device_handle->info.asic_id; + + family_id = device_handle->info.family_id; + chip_id = device_handle->info.chip_external_rev; + chip_rev = device_handle->info.chip_rev; if (amdgpu_device_deinitialize(device_handle)) return CU_FALSE; - /* disable gfx engine basic test cases for Arturus due to no CPG */ - if (asic_is_arcturus(asic_id)) { + /* disable gfx engine basic test cases for some asics have no CPG */ + if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) { if (amdgpu_set_test_active("Basic Tests", "Command submission Test (GFX)", CU_FALSE)) @@ -923,15 +929,6 @@ 0, &vram_info); CU_ASSERT_EQUAL(r, 0); - r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, - 0, >t_info); - CU_ASSERT_EQUAL(r, 0); - - if (vram_info.max_allocation > gtt_info.heap_size/3) { - vram_info.max_allocation = gtt_info.heap_size/3; - gtt_info.max_allocation = vram_info.max_allocation; - } - r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[0]); CU_ASSERT_EQUAL(r, 0); @@ -939,6 +936,10 @@ AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[1]); CU_ASSERT_EQUAL(r, 0); + r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, + 0, >t_info); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096, AMDGPU_GEM_DOMAIN_GTT, 0, >t_max[0]); CU_ASSERT_EQUAL(r, 0); @@ -1071,6 +1072,14 @@ amdgpu_bo_list_handle bo_list[2]; amdgpu_va_handle va_handle[2]; int r, i; + struct amdgpu_gpu_info gpu_info = {0}; + unsigned gc_ip_type; + + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + + gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ? + AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX; if (family_id == AMDGPU_FAMILY_SI) { sdma_nop = SDMA_PACKET_SI(SDMA_NOP_SI, 0, 0, 0, 0); @@ -1113,14 +1122,14 @@ r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_DMA, 0, 0, sem); CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); + r = amdgpu_cs_wait_semaphore(context_handle[0], gc_ip_type, 0, 0, sem); CU_ASSERT_EQUAL(r, 0); ptr = ib_result_cpu[1]; ptr[0] = gfx_nop; ib_info[1].ib_mc_address = ib_result_mc_address[1]; ib_info[1].size = 1; - ibs_request[1].ip_type = AMDGPU_HW_IP_GFX; + ibs_request[1].ip_type = gc_ip_type; ibs_request[1].number_of_ibs = 1; ibs_request[1].ibs = &ib_info[1]; ibs_request[1].resources = bo_list[1]; @@ -1130,7 +1139,7 @@ CU_ASSERT_EQUAL(r, 0); fence_status.context = context_handle[0]; - fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_type = gc_ip_type; fence_status.ip_instance = 0; fence_status.fence = ibs_request[1].seq_no; r = amdgpu_cs_query_fence_status(&fence_status, @@ -1144,24 +1153,24 @@ ib_info[0].ib_mc_address = ib_result_mc_address[0]; ib_info[0].size = 1; - ibs_request[0].ip_type = AMDGPU_HW_IP_GFX; + ibs_request[0].ip_type = gc_ip_type; ibs_request[0].number_of_ibs = 1; ibs_request[0].ibs = &ib_info[0]; ibs_request[0].resources = bo_list[0]; ibs_request[0].fence_info.handle = NULL; r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1); CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); + r = amdgpu_cs_signal_semaphore(context_handle[0], gc_ip_type, 0, 0, sem); CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem); + r = amdgpu_cs_wait_semaphore(context_handle[1], gc_ip_type, 0, 0, sem); CU_ASSERT_EQUAL(r, 0); ptr = ib_result_cpu[1]; ptr[0] = gfx_nop; ib_info[1].ib_mc_address = ib_result_mc_address[1]; ib_info[1].size = 1; - ibs_request[1].ip_type = AMDGPU_HW_IP_GFX; + ibs_request[1].ip_type = gc_ip_type; ibs_request[1].number_of_ibs = 1; ibs_request[1].ibs = &ib_info[1]; ibs_request[1].resources = bo_list[1]; @@ -1171,7 +1180,7 @@ CU_ASSERT_EQUAL(r, 0); fence_status.context = context_handle[1]; - fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_type = gc_ip_type; fence_status.ip_instance = 0; fence_status.fence = ibs_request[1].seq_no; r = amdgpu_cs_query_fence_status(&fence_status, diff -Nru libdrm-2.4.105/tests/amdgpu/cs_tests.c libdrm-2.4.107/tests/amdgpu/cs_tests.c --- libdrm-2.4.105/tests/amdgpu/cs_tests.c 2021-04-07 14:09:24.179843000 +0000 +++ libdrm-2.4.107/tests/amdgpu/cs_tests.c 2021-07-02 12:49:05.449105300 +0000 @@ -64,21 +64,20 @@ CU_BOOL suite_cs_tests_enable(void) { - uint32_t asic_id; - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, &device_handle)) return CU_FALSE; family_id = device_handle->info.family_id; - asic_id = device_handle->info.asic_id; + chip_id = device_handle->info.chip_external_rev; + chip_rev = device_handle->info.chip_rev; if (amdgpu_device_deinitialize(device_handle)) return CU_FALSE; if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI || - asic_is_arcturus(asic_id)) { + asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) { printf("\n\nThe ASIC NOT support UVD, suite disabled\n"); return CU_FALSE; } diff -Nru libdrm-2.4.105/tests/amdgpu/deadlock_tests.c libdrm-2.4.107/tests/amdgpu/deadlock_tests.c --- libdrm-2.4.105/tests/amdgpu/deadlock_tests.c 2021-04-07 14:09:24.179843000 +0000 +++ libdrm-2.4.107/tests/amdgpu/deadlock_tests.c 2021-07-02 12:49:05.449105300 +0000 @@ -106,6 +106,10 @@ static pthread_t stress_thread; static uint32_t *ptr; +static uint32_t family_id; +static uint32_t chip_rev; +static uint32_t chip_id; + int use_uc_mtype = 0; static void amdgpu_deadlock_helper(unsigned ip_type); @@ -124,25 +128,27 @@ CU_BOOL suite_deadlock_tests_enable(void) { CU_BOOL enable = CU_TRUE; - uint32_t asic_id; if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, &device_handle)) return CU_FALSE; + family_id = device_handle->info.family_id; + chip_id = device_handle->info.chip_external_rev; + chip_rev = device_handle->info.chip_rev; + /* * Only enable for ASICs supporting GPU reset and for which it's enabled * by default (currently GFX8/9 dGPUS) */ - if (device_handle->info.family_id != AMDGPU_FAMILY_VI && - device_handle->info.family_id != AMDGPU_FAMILY_AI && - device_handle->info.family_id != AMDGPU_FAMILY_CI) { + if (family_id != AMDGPU_FAMILY_VI && + family_id != AMDGPU_FAMILY_AI && + family_id != AMDGPU_FAMILY_CI) { printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n"); enable = CU_FALSE; } - asic_id = device_handle->info.asic_id; - if (asic_is_arcturus(asic_id)) { + if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) { if (amdgpu_set_test_active("Deadlock Tests", "gfx ring block test (set amdgpu.lockup_timeout=50)", CU_FALSE)) diff -Nru libdrm-2.4.105/tests/amdgpu/hotunplug_tests.c libdrm-2.4.107/tests/amdgpu/hotunplug_tests.c --- libdrm-2.4.105/tests/amdgpu/hotunplug_tests.c 1970-01-01 00:00:00.000000000 +0000 +++ libdrm-2.4.107/tests/amdgpu/hotunplug_tests.c 2021-07-02 12:49:05.449105300 +0000 @@ -0,0 +1,445 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * +*/ + +#include +#include +#include +#include +#include +#if HAVE_ALLOCA_H +# include +#endif + +#include "CUnit/Basic.h" + +#include "amdgpu_test.h" +#include "amdgpu_drm.h" +#include "amdgpu_internal.h" +#include "xf86drm.h" +#include + +#define GFX_COMPUTE_NOP 0xffff1000 + +static amdgpu_device_handle device_handle; +static uint32_t major_version; +static uint32_t minor_version; +static char *sysfs_remove = NULL; +static bool do_cs; + +CU_BOOL suite_hotunplug_tests_enable(void) +{ + CU_BOOL enable = CU_TRUE; + drmDevicePtr device; + + if (drmGetDevice2(drm_amdgpu[0], DRM_DEVICE_GET_PCI_REVISION, &device)) { + printf("\n\nGPU Failed to get DRM device PCI info!\n"); + return CU_FALSE; + } + + if (device->bustype != DRM_BUS_PCI) { + printf("\n\nGPU device is not on PCI bus!\n"); + amdgpu_device_deinitialize(device_handle); + return CU_FALSE; + } + + /* Disable until the hot-unplug support in kernel gets into drm-next */ + if (major_version < 0xff) + enable = false; + + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle)) + return CU_FALSE; + + /* TODO Once DRM version for unplug feature ready compare here agains it*/ + + if (amdgpu_device_deinitialize(device_handle)) + return CU_FALSE; + + return enable; +} + +int suite_hotunplug_tests_init(void) +{ + /* We need to open/close device at each test manually */ + amdgpu_close_devices(); + + return CUE_SUCCESS; +} + +int suite_hotunplug_tests_clean(void) +{ + + + return CUE_SUCCESS; +} + +static int amdgpu_hotunplug_trigger(const char *pathname) +{ + int fd, len; + + fd = open(pathname, O_WRONLY); + if (fd < 0) + return -errno; + + len = write(fd, "1", 1); + close(fd); + + return len; +} + +static int amdgpu_hotunplug_setup_test() +{ + int r; + char *tmp_str; + + if (amdgpu_open_device_on_test_index(open_render_node) < 0) { + printf("\n\n Failed to reopen device file!\n"); + return CUE_SINIT_FAILED; + + + + } + + r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle); + + if (r) { + if ((r == -EACCES) && (errno == EACCES)) + printf("\n\nError:%s. " + "Hint:Try to run this test program as root.", + strerror(errno)); + return CUE_SINIT_FAILED; + } + + tmp_str = amdgpu_get_device_from_fd(drm_amdgpu[0]); + if (!tmp_str){ + printf("\n\n Device path not found!\n"); + return CUE_SINIT_FAILED; + } + + sysfs_remove = realloc(tmp_str, strlen(tmp_str) * 2); + strcat(sysfs_remove, "/remove"); + + return 0; +} + +static int amdgpu_hotunplug_teardown_test() +{ + if (amdgpu_device_deinitialize(device_handle)) + return CUE_SCLEAN_FAILED; + + amdgpu_close_devices(); + + if (sysfs_remove) + free(sysfs_remove); + + return 0; +} + +static inline int amdgpu_hotunplug_remove() +{ + return amdgpu_hotunplug_trigger(sysfs_remove); +} + +static inline int amdgpu_hotunplug_rescan() +{ + return amdgpu_hotunplug_trigger("/sys/bus/pci/rescan"); +} + +static int amdgpu_cs_sync(amdgpu_context_handle context, + unsigned int ip_type, + int ring, + unsigned int seqno) +{ + struct amdgpu_cs_fence fence = { + .context = context, + .ip_type = ip_type, + .ring = ring, + .fence = seqno, + }; + uint32_t expired; + + return amdgpu_cs_query_fence_status(&fence, + AMDGPU_TIMEOUT_INFINITE, + 0, &expired); +} + +static void *amdgpu_nop_cs() +{ + amdgpu_bo_handle ib_result_handle; + void *ib_result_cpu; + uint64_t ib_result_mc_address; + uint32_t *ptr; + int i, r; + amdgpu_bo_list_handle bo_list; + amdgpu_va_handle va_handle; + amdgpu_context_handle context; + struct amdgpu_cs_request ibs_request; + struct amdgpu_cs_ib_info ib_info; + + r = amdgpu_cs_ctx_create(device_handle, &context); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &ib_result_handle, &ib_result_cpu, + &ib_result_mc_address, &va_handle); + CU_ASSERT_EQUAL(r, 0); + + ptr = ib_result_cpu; + for (i = 0; i < 16; ++i) + ptr[i] = GFX_COMPUTE_NOP; + + r = amdgpu_bo_list_create(device_handle, 1, &ib_result_handle, NULL, &bo_list); + CU_ASSERT_EQUAL(r, 0); + + memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); + ib_info.ib_mc_address = ib_result_mc_address; + ib_info.size = 16; + + memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); + ibs_request.ip_type = AMDGPU_HW_IP_GFX; + ibs_request.ring = 0; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.resources = bo_list; + + while (do_cs) + amdgpu_cs_submit(context, 0, &ibs_request, 1); + + amdgpu_cs_sync(context, AMDGPU_HW_IP_GFX, 0, ibs_request.seq_no); + amdgpu_bo_list_destroy(bo_list); + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, + ib_result_mc_address, 4096); + + amdgpu_cs_ctx_free(context); + + return (void *)0; +} + +static pthread_t* amdgpu_create_cs_thread() +{ + int r; + pthread_t *thread = malloc(sizeof(*thread)); + if (!thread) + return NULL; + + do_cs = true; + + r = pthread_create(thread, NULL, amdgpu_nop_cs, NULL); + CU_ASSERT_EQUAL(r, 0); + + /* Give thread enough time to start*/ + usleep(100000); + return thread; +} + +static void amdgpu_destroy_cs_thread(pthread_t *thread) +{ + void *status; + + do_cs = false; + + pthread_join(*thread, &status); + CU_ASSERT_EQUAL(status, 0); + + free(thread); +} + + +static void amdgpu_hotunplug_test(bool with_cs) +{ + int r; + pthread_t *thread = NULL; + + r = amdgpu_hotunplug_setup_test(); + CU_ASSERT_EQUAL(r , 0); + + if (with_cs) { + thread = amdgpu_create_cs_thread(); + CU_ASSERT_NOT_EQUAL(thread, NULL); + } + + r = amdgpu_hotunplug_remove(); + CU_ASSERT_EQUAL(r > 0, 1); + + if (with_cs) + amdgpu_destroy_cs_thread(thread); + + r = amdgpu_hotunplug_teardown_test(); + CU_ASSERT_EQUAL(r , 0); + + r = amdgpu_hotunplug_rescan(); + CU_ASSERT_EQUAL(r > 0, 1); +} + +static void amdgpu_hotunplug_simple(void) +{ + amdgpu_hotunplug_test(false); +} + +static void amdgpu_hotunplug_with_cs(void) +{ + amdgpu_hotunplug_test(true); +} + +static void amdgpu_hotunplug_with_exported_bo(void) +{ + int r; + uint32_t dma_buf_fd; + unsigned int *ptr; + amdgpu_bo_handle bo_handle; + + struct amdgpu_bo_alloc_request request = { + .alloc_size = 4096, + .phys_alignment = 4096, + .preferred_heap = AMDGPU_GEM_DOMAIN_GTT, + .flags = 0, + }; + + r = amdgpu_hotunplug_setup_test(); + CU_ASSERT_EQUAL(r , 0); + + amdgpu_bo_alloc(device_handle, &request, &bo_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_export(bo_handle, amdgpu_bo_handle_type_dma_buf_fd, &dma_buf_fd); + CU_ASSERT_EQUAL(r, 0); + + ptr = mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, dma_buf_fd, 0); + CU_ASSERT_NOT_EQUAL(ptr, MAP_FAILED); + + r = amdgpu_hotunplug_remove(); + CU_ASSERT_EQUAL(r > 0, 1); + + amdgpu_bo_free(bo_handle); + + r = amdgpu_hotunplug_teardown_test(); + CU_ASSERT_EQUAL(r , 0); + + *ptr = 0xdeafbeef; + + munmap(ptr, 4096); + close (dma_buf_fd); + + r = amdgpu_hotunplug_rescan(); + CU_ASSERT_EQUAL(r > 0, 1); +} + +static void amdgpu_hotunplug_with_exported_fence(void) +{ + amdgpu_bo_handle ib_result_handle; + void *ib_result_cpu; + uint64_t ib_result_mc_address; + uint32_t *ptr, sync_obj_handle, sync_obj_handle2; + int i, r; + amdgpu_bo_list_handle bo_list; + amdgpu_va_handle va_handle; + uint32_t major2, minor2; + amdgpu_device_handle device2; + amdgpu_context_handle context; + struct amdgpu_cs_request ibs_request; + struct amdgpu_cs_ib_info ib_info; + struct amdgpu_cs_fence fence_status = {0}; + int shared_fd; + + r = amdgpu_hotunplug_setup_test(); + CU_ASSERT_EQUAL(r , 0); + + r = amdgpu_device_initialize(drm_amdgpu[1], &major2, &minor2, &device2); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_create(device_handle, &context); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &ib_result_handle, &ib_result_cpu, + &ib_result_mc_address, &va_handle); + CU_ASSERT_EQUAL(r, 0); + + ptr = ib_result_cpu; + for (i = 0; i < 16; ++i) + ptr[i] = GFX_COMPUTE_NOP; + + r = amdgpu_bo_list_create(device_handle, 1, &ib_result_handle, NULL, &bo_list); + CU_ASSERT_EQUAL(r, 0); + + memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); + ib_info.ib_mc_address = ib_result_mc_address; + ib_info.size = 16; + + memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); + ibs_request.ip_type = AMDGPU_HW_IP_GFX; + ibs_request.ring = 0; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.resources = bo_list; + + CU_ASSERT_EQUAL(amdgpu_cs_submit(context, 0, &ibs_request, 1), 0); + + fence_status.context = context; + fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_instance = 0; + fence_status.fence = ibs_request.seq_no; + + CU_ASSERT_EQUAL(amdgpu_cs_fence_to_handle(device_handle, &fence_status, + AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ, + &sync_obj_handle), + 0); + + CU_ASSERT_EQUAL(amdgpu_cs_export_syncobj(device_handle, sync_obj_handle, &shared_fd), 0); + + CU_ASSERT_EQUAL(amdgpu_cs_import_syncobj(device2, shared_fd, &sync_obj_handle2), 0); + + CU_ASSERT_EQUAL(amdgpu_cs_destroy_syncobj(device_handle, sync_obj_handle), 0); + + CU_ASSERT_EQUAL(amdgpu_bo_list_destroy(bo_list), 0); + CU_ASSERT_EQUAL(amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, + ib_result_mc_address, 4096), 0); + CU_ASSERT_EQUAL(amdgpu_cs_ctx_free(context), 0); + + r = amdgpu_hotunplug_remove(); + CU_ASSERT_EQUAL(r > 0, 1); + + CU_ASSERT_EQUAL(amdgpu_cs_syncobj_wait(device2, &sync_obj_handle2, 1, 100000000, 0, NULL), 0); + + CU_ASSERT_EQUAL(amdgpu_cs_destroy_syncobj(device2, sync_obj_handle2), 0); + + amdgpu_device_deinitialize(device2); + + r = amdgpu_hotunplug_teardown_test(); + CU_ASSERT_EQUAL(r , 0); + + r = amdgpu_hotunplug_rescan(); + CU_ASSERT_EQUAL(r > 0, 1); +} + + +CU_TestInfo hotunplug_tests[] = { + { "Unplug card and rescan the bus to plug it back", amdgpu_hotunplug_simple }, + { "Same as first test but with command submission", amdgpu_hotunplug_with_cs }, + { "Unplug with exported bo", amdgpu_hotunplug_with_exported_bo }, + { "Unplug with exported fence", amdgpu_hotunplug_with_exported_fence }, + CU_TEST_INFO_NULL, +}; diff -Nru libdrm-2.4.105/tests/amdgpu/meson.build libdrm-2.4.107/tests/amdgpu/meson.build --- libdrm-2.4.105/tests/amdgpu/meson.build 2021-04-07 14:09:24.179843000 +0000 +++ libdrm-2.4.107/tests/amdgpu/meson.build 2021-07-02 12:49:05.449105300 +0000 @@ -25,6 +25,7 @@ 'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c', 'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c', 'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c', 'security_tests.c', + 'hotunplug_tests.c' ), dependencies : [dep_cunit, dep_threads, dep_atomic_ops], include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')], diff -Nru libdrm-2.4.105/tests/amdgpu/security_tests.c libdrm-2.4.107/tests/amdgpu/security_tests.c --- libdrm-2.4.105/tests/amdgpu/security_tests.c 2021-04-07 14:09:24.179843000 +0000 +++ libdrm-2.4.107/tests/amdgpu/security_tests.c 2021-07-02 12:49:05.452438600 +0000 @@ -432,7 +432,8 @@ &minor_version, &device_handle)) return CU_FALSE; - if (device_handle->info.family_id != AMDGPU_FAMILY_RV) { + + if (!(device_handle->dev_info.ids_flags & AMDGPU_IDS_FLAGS_TMZ)) { printf("\n\nDon't support TMZ (trust memory zone), security suite disabled\n"); enable = CU_FALSE; } diff -Nru libdrm-2.4.105/tests/amdgpu/syncobj_tests.c libdrm-2.4.107/tests/amdgpu/syncobj_tests.c --- libdrm-2.4.105/tests/amdgpu/syncobj_tests.c 2021-04-07 14:09:24.179843000 +0000 +++ libdrm-2.4.107/tests/amdgpu/syncobj_tests.c 2021-07-02 12:49:05.452438600 +0000 @@ -33,6 +33,10 @@ static uint32_t major_version; static uint32_t minor_version; +static uint32_t family_id; +static uint32_t chip_id; +static uint32_t chip_rev; + static void amdgpu_syncobj_timeline_test(void); CU_BOOL suite_syncobj_timeline_tests_enable(void) @@ -99,7 +103,19 @@ uint32_t expired; int i, r; uint64_t seq_no; - uint32_t *ptr; + static uint32_t *ptr; + struct amdgpu_gpu_info gpu_info = {0}; + unsigned gc_ip_type; + + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + + family_id = device_handle->info.family_id; + chip_id = device_handle->info.chip_external_rev; + chip_rev = device_handle->info.chip_rev; + + gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ? + AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX; r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); @@ -125,11 +141,11 @@ chunk_data.ib_data._pad = 0; chunk_data.ib_data.va_start = ib_result_mc_address; chunk_data.ib_data.ib_bytes = 16 * 4; - chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : + chunk_data.ib_data.ip_type = wait_or_signal ? gc_ip_type : AMDGPU_HW_IP_DMA; chunk_data.ib_data.ip_instance = 0; chunk_data.ib_data.ring = 0; - chunk_data.ib_data.flags = 0; + chunk_data.ib_data.flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC; chunks[1].chunk_id = wait_or_signal ? AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT : @@ -151,7 +167,7 @@ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); fence_status.context = context_handle; - fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX: + fence_status.ip_type = wait_or_signal ? gc_ip_type : AMDGPU_HW_IP_DMA; fence_status.ip_instance = 0; fence_status.ring = 0; diff -Nru libdrm-2.4.105/tests/amdgpu/vce_tests.c libdrm-2.4.107/tests/amdgpu/vce_tests.c --- libdrm-2.4.105/tests/amdgpu/vce_tests.c 2021-04-07 14:09:24.179843000 +0000 +++ libdrm-2.4.107/tests/amdgpu/vce_tests.c 2021-07-02 12:49:05.452438600 +0000 @@ -116,7 +116,7 @@ return CU_FALSE; if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI || - asic_is_arcturus(asic_id)) { + asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) { printf("\n\nThe ASIC NOT support VCE, suite disabled\n"); return CU_FALSE; } diff -Nru libdrm-2.4.105/tests/amdgpu/vcn_tests.c libdrm-2.4.107/tests/amdgpu/vcn_tests.c --- libdrm-2.4.105/tests/amdgpu/vcn_tests.c 2021-04-07 14:09:24.179843000 +0000 +++ libdrm-2.4.107/tests/amdgpu/vcn_tests.c 2021-07-02 12:49:05.452438600 +0000 @@ -114,7 +114,7 @@ if (r != 0 || !info.available_rings || (family_id < AMDGPU_FAMILY_RV && (family_id == AMDGPU_FAMILY_AI && - chip_id != (chip_rev + 0x32)))) { /* Arcturus */ + (chip_id - chip_rev) < 0x32))) { /* Arcturus */ printf("\n\nThe ASIC NOT support VCN, suite disabled\n"); return CU_FALSE; } diff -Nru libdrm-2.4.105/tests/amdgpu/vm_tests.c libdrm-2.4.107/tests/amdgpu/vm_tests.c --- libdrm-2.4.105/tests/amdgpu/vm_tests.c 2021-04-07 14:09:24.179843000 +0000 +++ libdrm-2.4.107/tests/amdgpu/vm_tests.c 2021-07-02 12:49:05.452438600 +0000 @@ -30,6 +30,9 @@ static amdgpu_device_handle device_handle; static uint32_t major_version; static uint32_t minor_version; +static uint32_t family_id; +static uint32_t chip_id; +static uint32_t chip_rev; static void amdgpu_vmid_reserve_test(void); static void amdgpu_vm_unaligned_map(void); @@ -110,7 +113,11 @@ r = amdgpu_query_gpu_info(device_handle, &gpu_info); CU_ASSERT_EQUAL(r, 0); - gc_ip_type = (asic_is_arcturus(gpu_info.asic_id)) ? + family_id = device_handle->info.family_id; + chip_id = device_handle->info.chip_external_rev; + chip_rev = device_handle->info.chip_rev; + + gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ? AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX; r = amdgpu_cs_ctx_create(device_handle, &context_handle); diff -Nru libdrm-2.4.105/tests/modetest/modetest.c libdrm-2.4.107/tests/modetest/modetest.c --- libdrm-2.4.105/tests/modetest/modetest.c 2021-04-07 14:09:24.183843000 +0000 +++ libdrm-2.4.107/tests/modetest/modetest.c 2021-07-02 12:49:05.455772000 +0000 @@ -265,52 +265,37 @@ static const char *modifier_to_string(uint64_t modifier) { - switch (modifier) { - case DRM_FORMAT_MOD_INVALID: - return "INVALID"; - case DRM_FORMAT_MOD_LINEAR: - return "LINEAR"; - case I915_FORMAT_MOD_X_TILED: - return "X_TILED"; - case I915_FORMAT_MOD_Y_TILED: - return "Y_TILED"; - case I915_FORMAT_MOD_Yf_TILED: - return "Yf_TILED"; - case I915_FORMAT_MOD_Y_TILED_CCS: - return "Y_TILED_CCS"; - case I915_FORMAT_MOD_Yf_TILED_CCS: - return "Yf_TILED_CCS"; - case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE: - return "SAMSUNG_64_32_TILE"; - case DRM_FORMAT_MOD_VIVANTE_TILED: - return "VIVANTE_TILED"; - case DRM_FORMAT_MOD_VIVANTE_SUPER_TILED: - return "VIVANTE_SUPER_TILED"; - case DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED: - return "VIVANTE_SPLIT_TILED"; - case DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED: - return "VIVANTE_SPLIT_SUPER_TILED"; - case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED: - return "NVIDIA_TEGRA_TILED"; - case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0): - return "NVIDIA_16BX2_BLOCK(0)"; - case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1): - return "NVIDIA_16BX2_BLOCK(1)"; - case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2): - return "NVIDIA_16BX2_BLOCK(2)"; - case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3): - return "NVIDIA_16BX2_BLOCK(3)"; - case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4): - return "NVIDIA_16BX2_BLOCK(4)"; - case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5): - return "NVIDIA_16BX2_BLOCK(5)"; - case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: - return "MOD_BROADCOM_VC4_T_TILED"; - case DRM_FORMAT_MOD_QCOM_COMPRESSED: - return "QCOM_COMPRESSED"; - default: - return "(UNKNOWN MODIFIER)"; + static char mod_string[4096]; + + char *modifier_name = drmGetFormatModifierName(modifier); + char *vendor_name = drmGetFormatModifierVendor(modifier); + memset(mod_string, 0x00, sizeof(mod_string)); + + if (!modifier_name) { + if (vendor_name) + snprintf(mod_string, sizeof(mod_string), "%s_%s", + vendor_name, "UNKNOWN_MODIFIER"); + else + snprintf(mod_string, sizeof(mod_string), "%s_%s", + "UNKNOWN_VENDOR", "UNKNOWN_MODIFIER"); + /* safe, as free is no-op for NULL */ + free(vendor_name); + return mod_string; + } + + if (modifier == DRM_FORMAT_MOD_LINEAR) { + snprintf(mod_string, sizeof(mod_string), "%s", modifier_name); + free(modifier_name); + free(vendor_name); + return mod_string; } + + snprintf(mod_string, sizeof(mod_string), "%s_%s", + vendor_name, modifier_name); + + free(modifier_name); + free(vendor_name); + return mod_string; } static void dump_in_formats(struct device *dev, uint32_t blob_id) diff -Nru libdrm-2.4.105/xf86drm.c libdrm-2.4.107/xf86drm.c --- libdrm-2.4.105/xf86drm.c 2021-04-07 14:09:24.183843000 +0000 +++ libdrm-2.4.107/xf86drm.c 2021-07-02 12:49:05.459105300 +0000 @@ -61,6 +61,7 @@ #include #endif #include +#include #if defined(__FreeBSD__) #include @@ -76,6 +77,7 @@ #include "xf86drm.h" #include "libdrm_macros.h" +#include "drm_fourcc.h" #include "util_math.h" @@ -124,6 +126,362 @@ static bool drmNodeIsDRM(int maj, int min); static char *drmGetMinorNameForFD(int fd, int type); +#define DRM_MODIFIER(v, f, f_name) \ + .modifier = DRM_FORMAT_MOD_##v ## _ ##f, \ + .modifier_name = #f_name + +#define DRM_MODIFIER_INVALID(v, f_name) \ + .modifier = DRM_FORMAT_MOD_INVALID, .modifier_name = #f_name + +#define DRM_MODIFIER_LINEAR(v, f_name) \ + .modifier = DRM_FORMAT_MOD_LINEAR, .modifier_name = #f_name + +/* Intel is abit special as the format doesn't follow other vendors naming + * scheme */ +#define DRM_MODIFIER_INTEL(f, f_name) \ + .modifier = I915_FORMAT_MOD_##f, .modifier_name = #f_name + +struct drmFormatModifierInfo { + uint64_t modifier; + const char *modifier_name; +}; + +struct drmFormatModifierVendorInfo { + uint8_t vendor; + const char *vendor_name; +}; + +#include "generated_static_table_fourcc.h" + +struct drmVendorInfo { + uint8_t vendor; + char *(*vendor_cb)(uint64_t modifier); +}; + +struct drmFormatVendorModifierInfo { + uint64_t modifier; + const char *modifier_name; +}; + +static char * +drmGetFormatModifierNameFromArm(uint64_t modifier); + +static char * +drmGetFormatModifierNameFromNvidia(uint64_t modifier); + +static char * +drmGetFormatModifierNameFromAmd(uint64_t modifier); + +static char * +drmGetFormatModifierNameFromAmlogic(uint64_t modifier); + +static const struct drmVendorInfo modifier_format_vendor_table[] = { + { DRM_FORMAT_MOD_VENDOR_ARM, drmGetFormatModifierNameFromArm }, + { DRM_FORMAT_MOD_VENDOR_NVIDIA, drmGetFormatModifierNameFromNvidia }, + { DRM_FORMAT_MOD_VENDOR_AMD, drmGetFormatModifierNameFromAmd }, + { DRM_FORMAT_MOD_VENDOR_AMLOGIC, drmGetFormatModifierNameFromAmlogic }, +}; + +#ifndef AFBC_FORMAT_MOD_MODE_VALUE_MASK +#define AFBC_FORMAT_MOD_MODE_VALUE_MASK 0x000fffffffffffffULL +#endif + +static const struct drmFormatVendorModifierInfo arm_mode_value_table[] = { + { AFBC_FORMAT_MOD_YTR, "YTR" }, + { AFBC_FORMAT_MOD_SPLIT, "SPLIT" }, + { AFBC_FORMAT_MOD_SPARSE, "SPARSE" }, + { AFBC_FORMAT_MOD_CBR, "CBR" }, + { AFBC_FORMAT_MOD_TILED, "TILED" }, + { AFBC_FORMAT_MOD_SC, "SC" }, + { AFBC_FORMAT_MOD_DB, "DB" }, + { AFBC_FORMAT_MOD_BCH, "BCH" }, + { AFBC_FORMAT_MOD_USM, "USM" }, +}; + +static bool is_x_t_amd_gfx9_tile(uint64_t tile) +{ + switch (tile) { + case AMD_FMT_MOD_TILE_GFX9_64K_S_X: + case AMD_FMT_MOD_TILE_GFX9_64K_D_X: + case AMD_FMT_MOD_TILE_GFX9_64K_R_X: + return true; + } + + return false; +} + +static char * +drmGetFormatModifierNameFromArm(uint64_t modifier) +{ + uint64_t type = (modifier >> 52) & 0xf; + uint64_t mode_value = modifier & AFBC_FORMAT_MOD_MODE_VALUE_MASK; + uint64_t block_size = mode_value & AFBC_FORMAT_MOD_BLOCK_SIZE_MASK; + + FILE *fp; + char *modifier_name = NULL; + size_t size = 0; + unsigned int i; + + const char *block = NULL; + const char *mode = NULL; + bool did_print_mode = false; + + /* misc type is already handled by the static table */ + if (type != DRM_FORMAT_MOD_ARM_TYPE_AFBC) + return NULL; + + fp = open_memstream(&modifier_name, &size); + if (!fp) + return NULL; + + /* add block, can only have a (single) block */ + switch (block_size) { + case AFBC_FORMAT_MOD_BLOCK_SIZE_16x16: + block = "16x16"; + break; + case AFBC_FORMAT_MOD_BLOCK_SIZE_32x8: + block = "32x8"; + break; + case AFBC_FORMAT_MOD_BLOCK_SIZE_64x4: + block = "64x4"; + break; + case AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4: + block = "32x8_64x4"; + break; + } + + if (!block) { + fclose(fp); + free(modifier_name); + return NULL; + } + + fprintf(fp, "BLOCK_SIZE=%s,", block); + + /* add mode */ + for (i = 0; i < ARRAY_SIZE(arm_mode_value_table); i++) { + if (arm_mode_value_table[i].modifier & mode_value) { + mode = arm_mode_value_table[i].modifier_name; + if (!did_print_mode) { + fprintf(fp, "MODE=%s", mode); + did_print_mode = true; + } else { + fprintf(fp, "|%s", mode); + } + } + } + + fclose(fp); + return modifier_name; +} + +static char * +drmGetFormatModifierNameFromNvidia(uint64_t modifier) +{ + uint64_t height, kind, gen, sector, compression; + + height = modifier & 0xf; + kind = (modifier >> 12) & 0xff; + + gen = (modifier >> 20) & 0x3; + sector = (modifier >> 22) & 0x1; + compression = (modifier >> 23) & 0x7; + + /* just in case there could other simpler modifiers, not yet added, avoid + * testing against TEGRA_TILE */ + if ((modifier & 0x10) == 0x10) { + char *mod_nvidia; + asprintf(&mod_nvidia, "BLOCK_LINEAR_2D,HEIGHT=%"PRIu64",KIND=%"PRIu64"," + "GEN=%"PRIu64",SECTOR=%"PRIu64",COMPRESSION=%"PRIu64"", height, + kind, gen, sector, compression); + return mod_nvidia; + } + + return NULL; +} + +static void +drmGetFormatModifierNameFromAmdDcc(uint64_t modifier, FILE *fp) +{ + uint64_t dcc_max_compressed_block = + AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier); + uint64_t dcc_retile = AMD_FMT_MOD_GET(DCC_RETILE, modifier); + + const char *dcc_max_compressed_block_str = NULL; + + fprintf(fp, ",DCC"); + + if (dcc_retile) + fprintf(fp, ",DCC_RETILE"); + + if (!dcc_retile && AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier)) + fprintf(fp, ",DCC_PIPE_ALIGN"); + + if (AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier)) + fprintf(fp, ",DCC_INDEPENDENT_64B"); + + if (AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier)) + fprintf(fp, ",DCC_INDEPENDENT_128B"); + + switch (dcc_max_compressed_block) { + case AMD_FMT_MOD_DCC_BLOCK_64B: + dcc_max_compressed_block_str = "64B"; + break; + case AMD_FMT_MOD_DCC_BLOCK_128B: + dcc_max_compressed_block_str = "128B"; + break; + case AMD_FMT_MOD_DCC_BLOCK_256B: + dcc_max_compressed_block_str = "256B"; + break; + } + + if (dcc_max_compressed_block_str) + fprintf(fp, ",DCC_MAX_COMPRESSED_BLOCK=%s", + dcc_max_compressed_block_str); + + if (AMD_FMT_MOD_GET(DCC_CONSTANT_ENCODE, modifier)) + fprintf(fp, ",DCC_CONSTANT_ENCODE"); +} + +static void +drmGetFormatModifierNameFromAmdTile(uint64_t modifier, FILE *fp) +{ + uint64_t pipe_xor_bits, bank_xor_bits, packers, rb; + uint64_t pipe, pipe_align, dcc, dcc_retile, tile_version; + + pipe_align = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); + pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); + dcc = AMD_FMT_MOD_GET(DCC, modifier); + dcc_retile = AMD_FMT_MOD_GET(DCC_RETILE, modifier); + tile_version = AMD_FMT_MOD_GET(TILE_VERSION, modifier); + + fprintf(fp, ",PIPE_XOR_BITS=%"PRIu64, pipe_xor_bits); + + if (tile_version == AMD_FMT_MOD_TILE_VER_GFX9) { + bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier); + fprintf(fp, ",BANK_XOR_BITS=%"PRIu64, bank_xor_bits); + } + + if (tile_version == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) { + packers = AMD_FMT_MOD_GET(PACKERS, modifier); + fprintf(fp, ",PACKERS=%"PRIu64, packers); + } + + if (dcc && tile_version == AMD_FMT_MOD_TILE_VER_GFX9) { + rb = AMD_FMT_MOD_GET(RB, modifier); + fprintf(fp, ",RB=%"PRIu64, rb); + } + + if (dcc && tile_version == AMD_FMT_MOD_TILE_VER_GFX9 && + (dcc_retile || pipe_align)) { + pipe = AMD_FMT_MOD_GET(PIPE, modifier); + fprintf(fp, ",PIPE_%"PRIu64, pipe); + } +} + +static char * +drmGetFormatModifierNameFromAmd(uint64_t modifier) +{ + uint64_t tile, tile_version, dcc; + FILE *fp; + char *mod_amd = NULL; + size_t size = 0; + + const char *str_tile = NULL; + const char *str_tile_version = NULL; + + tile = AMD_FMT_MOD_GET(TILE, modifier); + tile_version = AMD_FMT_MOD_GET(TILE_VERSION, modifier); + dcc = AMD_FMT_MOD_GET(DCC, modifier); + + fp = open_memstream(&mod_amd, &size); + if (!fp) + return NULL; + + /* add tile */ + switch (tile_version) { + case AMD_FMT_MOD_TILE_VER_GFX9: + str_tile_version = "GFX9"; + break; + case AMD_FMT_MOD_TILE_VER_GFX10: + str_tile_version = "GFX10"; + break; + case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: + str_tile_version = "GFX10_RBPLUS"; + break; + } + + if (str_tile_version) { + fprintf(fp, "%s", str_tile_version); + } else { + fclose(fp); + free(mod_amd); + return NULL; + } + + /* add tile str */ + switch (tile) { + case AMD_FMT_MOD_TILE_GFX9_64K_S: + str_tile = "GFX9_64K_S"; + break; + case AMD_FMT_MOD_TILE_GFX9_64K_D: + str_tile = "GFX9_64K_D"; + break; + case AMD_FMT_MOD_TILE_GFX9_64K_S_X: + str_tile = "GFX9_64K_S_X"; + break; + case AMD_FMT_MOD_TILE_GFX9_64K_D_X: + str_tile = "GFX9_64K_D_X"; + break; + case AMD_FMT_MOD_TILE_GFX9_64K_R_X: + str_tile = "GFX9_64K_R_X"; + break; + } + + if (str_tile) + fprintf(fp, ",%s", str_tile); + + if (dcc) + drmGetFormatModifierNameFromAmdDcc(modifier, fp); + + if (tile_version >= AMD_FMT_MOD_TILE_VER_GFX9 && is_x_t_amd_gfx9_tile(tile)) + drmGetFormatModifierNameFromAmdTile(modifier, fp); + + fclose(fp); + return mod_amd; +} + +static char * +drmGetFormatModifierNameFromAmlogic(uint64_t modifier) +{ + uint64_t layout = modifier & 0xff; + uint64_t options = (modifier >> 8) & 0xff; + char *mod_amlogic = NULL; + + const char *layout_str; + const char *opts_str; + + switch (layout) { + case AMLOGIC_FBC_LAYOUT_BASIC: + layout_str = "BASIC"; + break; + case AMLOGIC_FBC_LAYOUT_SCATTER: + layout_str = "SCATTER"; + break; + default: + layout_str = "INVALID_LAYOUT"; + break; + } + + if (options & AMLOGIC_FBC_OPTION_MEM_SAVING) + opts_str = "MEM_SAVING"; + else + opts_str = "0"; + + asprintf(&mod_amlogic, "FBC,LAYOUT=%s,OPTIONS=%s", layout_str, opts_str); + return mod_amlogic; +} + static unsigned log2_int(unsigned x) { unsigned l; @@ -4585,3 +4943,66 @@ return ret; } + +static char * +drmGetFormatModifierFromSimpleTokens(uint64_t modifier) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(drm_format_modifier_table); i++) { + if (drm_format_modifier_table[i].modifier == modifier) + return strdup(drm_format_modifier_table[i].modifier_name); + } + + return NULL; +} + +/** Retrieves a human-readable representation of a vendor (as a string) from + * the format token modifier + * + * \param modifier the format modifier token + * \return a char pointer to the human-readable form of the vendor. Caller is + * responsible for freeing it. + */ +drm_public char * +drmGetFormatModifierVendor(uint64_t modifier) +{ + unsigned int i; + uint8_t vendor = fourcc_mod_get_vendor(modifier); + + for (i = 0; i < ARRAY_SIZE(drm_format_modifier_vendor_table); i++) { + if (drm_format_modifier_vendor_table[i].vendor == vendor) + return strdup(drm_format_modifier_vendor_table[i].vendor_name); + } + + return NULL; +} + +/** Retrieves a human-readable representation string from a format token + * modifier + * + * If the dedicated function was not able to extract a valid name or searching + * the format modifier was not in the table, this function would return NULL. + * + * \param modifier the token format + * \return a malloc'ed string representation of the modifier. Caller is + * responsible for freeing the string returned. + * + */ +drm_public char * +drmGetFormatModifierName(uint64_t modifier) +{ + uint8_t vendorid = fourcc_mod_get_vendor(modifier); + char *modifier_found = NULL; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(modifier_format_vendor_table); i++) { + if (modifier_format_vendor_table[i].vendor == vendorid) + modifier_found = modifier_format_vendor_table[i].vendor_cb(modifier); + } + + if (!modifier_found) + return drmGetFormatModifierFromSimpleTokens(modifier); + + return modifier_found; +} diff -Nru libdrm-2.4.105/xf86drm.h libdrm-2.4.107/xf86drm.h --- libdrm-2.4.105/xf86drm.h 2021-04-07 14:09:24.183843000 +0000 +++ libdrm-2.4.107/xf86drm.h 2021-07-02 12:49:05.459105300 +0000 @@ -944,6 +944,17 @@ uint32_t src_handle, uint64_t src_point, uint32_t flags); +extern char * +drmGetFormatModifierVendor(uint64_t modifier); + +extern char * +drmGetFormatModifierName(uint64_t modifier); + +#ifndef fourcc_mod_get_vendor +#define fourcc_mod_get_vendor(modifier) \ + (((modifier) >> 56) & 0xff) +#endif + #if defined(__cplusplus) } #endif diff -Nru libdrm-2.4.105/xf86drmMode.c libdrm-2.4.107/xf86drmMode.c --- libdrm-2.4.105/xf86drmMode.c 2021-04-07 14:09:24.183843000 +0000 +++ libdrm-2.4.107/xf86drmMode.c 2021-07-02 12:49:05.459105300 +0000 @@ -38,6 +38,9 @@ #include #include #if HAVE_SYS_SYSCTL_H +#ifdef __FreeBSD__ +#include +#endif #include #endif #include @@ -289,10 +292,8 @@ memcpy(f.handles, bo_handles, 4 * sizeof(bo_handles[0])); memcpy(f.pitches, pitches, 4 * sizeof(pitches[0])); memcpy(f.offsets, offsets, 4 * sizeof(offsets[0])); - if (modifier) { - f.flags |= DRM_MODE_FB_MODIFIERS; + if (modifier) memcpy(f.modifier, modifier, 4 * sizeof(modifier[0])); - } if ((ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_ADDFB2, &f))) return ret;