diff -u lshw-02.17/debian/changelog lshw-02.17/debian/changelog
--- lshw-02.17/debian/changelog
+++ lshw-02.17/debian/changelog
@@ -1,3 +1,10 @@
+lshw (02.17-1.1ubuntu3.5) xenial; urgency=medium
+
+  * AArch64: cpuinfo: Remove redundant cpu caps loop (LP: #1582181)
+    (Merged into EZix upstream commit [20cda772])
+
+ -- Ike Panhc <ike.pan@canonical.com>  Wed, 21 Mar 2018 13:12:21 +0800
+
 lshw (02.17-1.1ubuntu3.4) xenial; urgency=medium
 
   * d/p/fix-segfault-in-privileged-containers.patch:
diff -u lshw-02.17/debian/patches/series lshw-02.17/debian/patches/series
--- lshw-02.17/debian/patches/series
+++ lshw-02.17/debian/patches/series
@@ -22,0 +23 @@
+AArch64-cpuinfo-Remove-redundant-cpu-caps-loop.patch
only in patch2:
unchanged:
--- lshw-02.17.orig/debian/patches/AArch64-cpuinfo-Remove-redundant-cpu-caps-loop.patch
+++ lshw-02.17/debian/patches/AArch64-cpuinfo-Remove-redundant-cpu-caps-loop.patch
@@ -0,0 +1,90 @@
+From: Alexandru Avadanii <Alexandru.Avadanii@enea.com>
+Date: Sun, 15 May 2016 22:16:03 +0200
+Subject: [PATCH] AArch64: cpuinfo: Remove redundant cpu caps loop.
+
+CPU capabilities should be added only to the current CPU core,
+and not recursively to all previous CPU cores.
+
+For a 48 core node, this parsing added up to 30 seconds (8 lines
+per core in /proc/cpuinfo resulted in 384 lines to parse).
+
+After this change, parsing for the above system takes less than
+1 second.
+
+Signed-off-by: Alexandru Avadanii <Alexandru.Avadanii@enea.com>
+---
+ src/core/cpuinfo.cc | 57 ++++++++++++++++++++++++++---------------------------
+ 1 file changed, 28 insertions(+), 29 deletions(-)
+
+diff --git a/src/core/cpuinfo.cc b/src/core/cpuinfo.cc
+index 5c7a6b1..1a3ea9d 100644
+--- a/src/core/cpuinfo.cc
++++ b/src/core/cpuinfo.cc
+@@ -74,37 +74,36 @@ static void cpuinfo_aarch64(hwNode & node,
+ 
+   if (id == "Features")
+     {
+-      while (value.length() > 0)
+-        {
+-          size_t pos = value.find(' ');
+-          string capability = (pos==string::npos)?value:value.substr(0, pos);
+-          aarch64_features.push_back(capability);
+-          if (pos == string::npos)
+-            value = "";
+-          else
+-            value = hw::strip(value.substr(pos));
+-        }
+-      for(int i=0; i<=currentcpu; i++)
++      hwNode *cpu = getcpu(node, currentcpu);
++      if (cpu)
+         {
+-          hwNode *cpu = getcpu(node, i);
+-          if (cpu)
++          cpu->addHint("logo", string("aarch64"));
++          if (node.getDescription() == "")
++            node.setDescription(aarch64_processor_name);
++          cpu->claim(true);
++
++          while (value.length() > 0)
++            {
++              size_t pos = value.find(' ');
++              string capability = (pos==string::npos)?value:value.substr(0, pos);
++              aarch64_features.push_back(capability);
++              if (pos == string::npos)
++                value = "";
++              else
++                value = hw::strip(value.substr(pos));
++            }
++
++          for(int i=0; i < aarch64_features.size(); i++)
+             {
+-              cpu->addHint("logo", string("aarch64"));
+-              if (node.getDescription() == "")
+-                node.setDescription(aarch64_processor_name);
+-              cpu->claim(true);
+-              for(int i=0; i < aarch64_features.size(); i++)
+-                {
+-                  cpu->addCapability(aarch64_features[i]);
+-                  cpu->describeCapability("fp", "Floating point instructions");
+-                  cpu->describeCapability("asimd", "Advanced SIMD");
+-                  cpu->describeCapability("evtstrm", "Event stream");
+-                  cpu->describeCapability("aes", "AES instructions");
+-                  cpu->describeCapability("pmull", "PMULL instruction");
+-                  cpu->describeCapability("sha1", "SHA1 instructions");
+-                  cpu->describeCapability("sha2", "SHA2 instructions");
+-                  cpu->describeCapability("crc32", "CRC extension");
+-                }
++              cpu->addCapability(aarch64_features[i]);
++              cpu->describeCapability("fp", "Floating point instructions");
++              cpu->describeCapability("asimd", "Advanced SIMD");
++              cpu->describeCapability("evtstrm", "Event stream");
++              cpu->describeCapability("aes", "AES instructions");
++              cpu->describeCapability("pmull", "PMULL instruction");
++              cpu->describeCapability("sha1", "SHA1 instructions");
++              cpu->describeCapability("sha2", "SHA2 instructions");
++              cpu->describeCapability("crc32", "CRC extension");
+             }
+         }
+     }
+-- 
+1.9.1