diff -u mesa-lts-quantal-9.0.3/debian/changelog mesa-lts-quantal-9.0.3/debian/changelog --- mesa-lts-quantal-9.0.3/debian/changelog +++ mesa-lts-quantal-9.0.3/debian/changelog @@ -1,3 +1,53 @@ +mesa-lts-quantal (9.0.3-0ubuntu0.4~precise1) precise-proposed; urgency=low + + * Added patches to fix a GPU hang with GT3. (LP: #1197316) + + -- Timo Aaltonen Wed, 03 Jul 2013 13:09:33 +0300 + +mesa (9.0.3-0ubuntu0.4) quantal-proposed; urgency=low + + * Added patches to fix a GPU hang with GT3 (LP: #1197316) + - add-chipset-limits-for-the-haswell-gt3-variant.diff + - turn-brw-urb-vs-size-and-gs-size-into-local-variables.diff + - update-urb-partitioning-code-for-haswell-gt3-variant.diff + - use-a-variable-for-the-push-constant-size-in-kb.diff + + -- Timo Aaltonen Wed, 03 Jul 2013 11:03:21 +0300 + +mesa-lts-quantal (9.0.3-0ubuntu0.3~precise1) precise-proposed; urgency=low + + * Added patches to add/fix Haswell pci-id's (LP: #1175533) + + -- Maarten Lankhorst Mon, 24 Jun 2013 14:10:41 +0200 + +mesa (9.0.3-0ubuntu0.3) quantal-proposed; urgency=low + + * Added patches to add/fix Haswell pci-id's (LP: #1175533) + - fix-hsw-crw-ids.diff + - add-vlv-ids.diff + - fix-hsw-gt3-names.diff + - fix-missing-gt3-id.diff + - add-more-reserved-hsw-ids.diff + + -- Maarten Lankhorst Mon, 24 Jun 2013 13:45:19 +0200 + +mesa (9.0.3-0ubuntu0.2) quantal-security; urgency=low + + * SECURITY UPDATE: denial of service and possible code execution via + out-of-bands access + - debian/patches/CVE-2013-1872.patch: check for out-of-bounds reads in + src/mesa/drivers/dri/i965/brw_fs.cpp, + src/mesa/drivers/dri/i965/brw_fs.h, + src/mesa/drivers/dri/i965/brw_fs_visitor.cpp. + - CVE-2013-1872 + * SECURITY UPDATE: denial of service and possible code execution via + integer overflows + - debian/patches/CVE-2013-1993.patch: check lengths in + src/glx/XF86dri.c. + - CVE-2013-1993 + + -- Marc Deslauriers Tue, 18 Jun 2013 14:05:02 -0400 + mesa-lts-quantal (9.0.3-0ubuntu0.1~precise3) precise-security; urgency=low * SECURITY UPDATE: denial of service and possible code execution via diff -u mesa-lts-quantal-9.0.3/debian/patches/series mesa-lts-quantal-9.0.3/debian/patches/series --- mesa-lts-quantal-9.0.3/debian/patches/series +++ mesa-lts-quantal-9.0.3/debian/patches/series @@ -19,0 +20,12 @@ + +# Add missing haswell pci ids +fix-hsw-crw-ids.diff +add-vlv-ids.diff +fix-hsw-gt3-names.diff +fix-missing-gt3-id.diff +add-more-reserved-hsw-ids.diff + +turn-brw-urb-vs-size-and-gs-size-into-local-variables.diff +use-a-variable-for-the-push-constant-size-in-kb.diff +update-urb-partitioning-code-for-haswell-gt3-variant.diff +add-chipset-limits-for-the-haswell-gt3-variant.diff only in patch2: unchanged: --- mesa-lts-quantal-9.0.3.orig/debian/patches/turn-brw-urb-vs-size-and-gs-size-into-local-variables.diff +++ mesa-lts-quantal-9.0.3/debian/patches/turn-brw-urb-vs-size-and-gs-size-into-local-variables.diff @@ -0,0 +1,110 @@ +commit 210f2794f5c4fedc7400d810af43b46d8e2dff84 +Author: Kenneth Graunke +Date: Tue Apr 2 21:11:50 2013 -0700 + + i965: Turn brw->urb.vs_size and gs_size into local variables. + + These variables are only used within a single function, so we may as + well make them local variables. + + Signed-off-by: Kenneth Graunke + Reviewed-by: Paul Berry + (cherry picked from commit 8cdb2d32ecd636a6d68840a68504c1fe1b14426b) + +diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h +index d718c15..910b73b 100644 +--- a/src/mesa/drivers/dri/i965/brw_context.h ++++ b/src/mesa/drivers/dri/i965/brw_context.h +@@ -844,15 +844,6 @@ struct brw_context + GLuint nr_sf_entries; + GLuint nr_cs_entries; + +- /* gen6: +- * The length of each URB entry owned by the VS (or GS), as +- * a number of 1024-bit (128-byte) rows. Should be >= 1. +- * +- * gen7: Same meaning, but in 512-bit (64-byte) rows. +- */ +- GLuint vs_size; +- GLuint gs_size; +- + GLuint vs_start; + GLuint gs_start; + GLuint clip_start; +diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c +index 2d69cbe..aa985de 100644 +--- a/src/mesa/drivers/dri/i965/gen6_urb.c ++++ b/src/mesa/drivers/dri/i965/gen6_urb.c +@@ -54,7 +54,7 @@ gen6_upload_urb( struct brw_context *brw ) + int total_urb_size = brw->urb.size * 1024; /* in bytes */ + + /* CACHE_NEW_VS_PROG */ +- brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1); ++ unsigned vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1); + + /* We use the same VUE layout for VS outputs and GS outputs (as it's what + * the SF and Clipper expect), so we can simply make the GS URB entry size +@@ -62,14 +62,14 @@ gen6_upload_urb( struct brw_context *brw ) + * where we have few vertex attributes and a lot of varyings, since the VS + * size is determined by the larger of the two. For now, it's safe. + */ +- brw->urb.gs_size = brw->urb.vs_size; ++ unsigned gs_size = vs_size; + + /* Calculate how many entries fit in each stage's section of the URB */ + if (brw->gs.prog_active) { +- nr_vs_entries = (total_urb_size/2) / (brw->urb.vs_size * 128); +- nr_gs_entries = (total_urb_size/2) / (brw->urb.gs_size * 128); ++ nr_vs_entries = (total_urb_size/2) / (vs_size * 128); ++ nr_gs_entries = (total_urb_size/2) / (gs_size * 128); + } else { +- nr_vs_entries = total_urb_size / (brw->urb.vs_size * 128); ++ nr_vs_entries = total_urb_size / (vs_size * 128); + nr_gs_entries = 0; + } + +@@ -87,14 +87,14 @@ gen6_upload_urb( struct brw_context *brw ) + assert(brw->urb.nr_vs_entries >= 24); + assert(brw->urb.nr_vs_entries % 4 == 0); + assert(brw->urb.nr_gs_entries % 4 == 0); +- assert(brw->urb.vs_size < 5); +- assert(brw->urb.gs_size < 5); ++ assert(vs_size < 5); ++ assert(gs_size < 5); + + BEGIN_BATCH(3); + OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2)); +- OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) | ++ OUT_BATCH(((vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) | + ((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT)); +- OUT_BATCH(((brw->urb.gs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) | ++ OUT_BATCH(((gs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) | + ((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT)); + ADVANCE_BATCH(); + +diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c +index 481497b..dafe1ad 100644 +--- a/src/mesa/drivers/dri/i965/gen7_urb.c ++++ b/src/mesa/drivers/dri/i965/gen7_urb.c +@@ -82,9 +82,9 @@ gen7_upload_urb(struct brw_context *brw) + int handle_region_size = (brw->urb.size - 16) * 1024; /* bytes */ + + /* CACHE_NEW_VS_PROG */ +- brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1); ++ unsigned vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1); + +- int nr_vs_entries = handle_region_size / (brw->urb.vs_size * 64); ++ int nr_vs_entries = handle_region_size / (vs_size * 64); + if (nr_vs_entries > brw->urb.max_vs_entries) + nr_vs_entries = brw->urb.max_vs_entries; + +@@ -100,8 +100,7 @@ gen7_upload_urb(struct brw_context *brw) + assert(!brw->gs.prog_active); + + gen7_emit_vs_workaround_flush(intel); +- gen7_emit_urb_state(brw, brw->urb.nr_vs_entries, brw->urb.vs_size, +- brw->urb.vs_start); ++ gen7_emit_urb_state(brw, brw->urb.nr_vs_entries, vs_size, brw->urb.vs_start); + } + + void only in patch2: unchanged: --- mesa-lts-quantal-9.0.3.orig/debian/patches/add-chipset-limits-for-the-haswell-gt3-variant.diff +++ mesa-lts-quantal-9.0.3/debian/patches/add-chipset-limits-for-the-haswell-gt3-variant.diff @@ -0,0 +1,29 @@ +commit ed7fa63bbd375aaf6f1ed179ecd7b74f3a752c64 +Author: Kenneth Graunke +Date: Wed Mar 7 09:58:15 2012 -0800 + + i965: Add chipset limits for the Haswell GT3 variant. + + NOTE: This is a candidate for stable branches. + + Signed-off-by: Kenneth Graunke + Signed-off-by: Eugeni Dodonov + (cherry picked from commit d0b82b1add5d1d1419d4390a3f7c584b6ee7d92c) + +diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c +index 19497e9..0b69b53 100644 +--- a/src/mesa/drivers/dri/i965/brw_context.c ++++ b/src/mesa/drivers/dri/i965/brw_context.c +@@ -293,6 +293,12 @@ brwCreateContext(int api, + brw->urb.size = 256; + brw->urb.max_vs_entries = 1664; + brw->urb.max_gs_entries = 640; ++ } else if (intel->gt == 3) { ++ brw->max_wm_threads = 408; ++ brw->max_vs_threads = 280; ++ brw->urb.size = 512; ++ brw->urb.max_vs_entries = 1664; ++ brw->urb.max_gs_entries = 640; + } + } else if (intel->gen == 7) { + if (intel->gt == 1) { only in patch2: unchanged: --- mesa-lts-quantal-9.0.3.orig/debian/patches/update-urb-partitioning-code-for-haswell-gt3-variant.diff +++ mesa-lts-quantal-9.0.3/debian/patches/update-urb-partitioning-code-for-haswell-gt3-variant.diff @@ -0,0 +1,78 @@ +commit acff9c2bbf6cf4d9aa270cf7ea04b40f29eb60ec +Author: Kenneth Graunke +Date: Sat Sep 24 00:12:58 2011 -0700 + + i965: Update URB partitioning code for Haswell's GT3 variant. + + Haswell's GT3 variant offers 32kB of URB space for push constants, while + GT1 and GT2 match Ivybridge, providing 16kB. Update the code to reserve + the full 32kB on GT3. + + v2: Specify push constant size correctly. I thought GT3 reinterpreted + the value as multiples of 2kB, but it doesn't. You simply have to + program an even number. + + NOTE: This is a candidate for stable branches. + + Signed-off-by: Kenneth Graunke + (cherry picked from commit eca2251f42f0234584d94268c29bddede3ff6451) + +diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c +index 5ac3885..e92e211 100644 +--- a/src/mesa/drivers/dri/i965/gen7_urb.c ++++ b/src/mesa/drivers/dri/i965/gen7_urb.c +@@ -39,29 +39,37 @@ + * +-------------------------------------------------------------+ + * + * Notably, push constants must be stored at the beginning of the URB +- * space, while entries can be stored anywhere. Ivybridge has a maximum +- * constant buffer size of 16kB. ++ * space, while entries can be stored anywhere. Ivybridge and Haswell ++ * GT1/GT2 have a maximum constant buffer size of 16kB, while Haswell GT3 ++ * doubles this (32kB). + * + * Currently we split the constant buffer space evenly between VS and FS. + * This is probably not ideal, but simple. + * +- * Ivybridge GT1 has 128kB of URB space. +- * Ivybridge GT2 has 256kB of URB space. ++ * Ivybridge GT1 and Haswell GT1 have 128kB of URB space. ++ * Ivybridge GT2 and Haswell GT2 have 256kB of URB space. ++ * Haswell GT3 has 512kB of URB space. + * +- * See "Volume 2a: 3D Pipeline," section 1.8. ++ * See "Volume 2a: 3D Pipeline," section 1.8, "Volume 1b: Configurations", ++ * and the documentation for 3DSTATE_PUSH_CONSTANT_ALLOC_xS. + */ + void + gen7_allocate_push_constants(struct brw_context *brw) + { + struct intel_context *intel = &brw->intel; ++ ++ unsigned size = 8; ++ if (intel->is_haswell && intel->gt == 3) ++ size = 16; ++ + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2)); +- OUT_BATCH(8); ++ OUT_BATCH(size); + ADVANCE_BATCH(); + + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2)); +- OUT_BATCH(8 | 8 << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); ++ OUT_BATCH(size | size << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); + ADVANCE_BATCH(); + } + +@@ -78,7 +86,8 @@ static void + gen7_upload_urb(struct brw_context *brw) + { + struct intel_context *intel = &brw->intel; +- const int push_size_kB = 16; ++ const int push_size_kB = intel->is_haswell && intel->gt == 3 ? 32 : 16; ++ + /* Total space for entries is URB size - 16kB for push constants */ + int handle_region_size = (brw->urb.size - push_size_kB) * 1024; /* bytes */ + only in patch2: unchanged: --- mesa-lts-quantal-9.0.3.orig/debian/patches/fix-missing-gt3-id.diff +++ mesa-lts-quantal-9.0.3/debian/patches/fix-missing-gt3-id.diff @@ -0,0 +1,26 @@ +commit 888fc7a89197972aac614fc19d1c82ed1adbb3f2 +Author: Rodrigo Vivi +Date: Mon May 13 17:53:38 2013 -0300 + + i965: Add missing Haswell GT3 Desktop to IS_HSW_GT3 check. + + NOTE: This is a candidate for stable branches. + + Signed-off-by: Rodrigo Vivi + Reviewed-by: Kenneth Graunke + +diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h +index df025ac..ee735bb 100644 +--- a/src/mesa/drivers/dri/intel/intel_chipset.h ++++ b/src/mesa/drivers/dri/intel/intel_chipset.h +@@ -230,8 +230,8 @@ + devid == PCI_CHIP_HASWELL_CRW_GT2 || \ + devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \ + devid == PCI_CHIP_HASWELL_CRW_S_GT2) +- +-#define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_M_GT3 || \ ++#define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_GT3 || \ ++ devid == PCI_CHIP_HASWELL_M_GT3 || \ + devid == PCI_CHIP_HASWELL_S_GT3 || \ + devid == PCI_CHIP_HASWELL_SDV_GT3 || \ + devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \ only in patch2: unchanged: --- mesa-lts-quantal-9.0.3.orig/debian/patches/add-vlv-ids.diff +++ mesa-lts-quantal-9.0.3/debian/patches/add-vlv-ids.diff @@ -0,0 +1,97 @@ +commit e7965598b7cc1123847e5c87ab16745145e849e2 +Author: Kenneth Graunke +Date: Wed Oct 3 14:26:29 2012 -0700 + + i965: Enable the Bay Trail platform. + + This patch adds PCI IDs for Bay Trail (sometimes called Valley View). + As far as the 3D driver is concerned, it's very similar to Ivybridge, + so the existing code should work just fine. + + Signed-off-by: Kenneth Graunke + +diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h +index 1e388f8..9a2da61 100644 +--- a/include/pci_ids/i965_pci_ids.h ++++ b/include/pci_ids/i965_pci_ids.h +@@ -62,3 +62,8 @@ CHIPSET(0x0D26, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) + CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1) + CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2) + CHIPSET(0x0D2A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0F31, BAYTRAIL_M_1, byt) ++CHIPSET(0x0F32, BAYTRAIL_M_2, byt) ++CHIPSET(0x0F33, BAYTRAIL_M_3, byt) ++CHIPSET(0x0157, BAYTRAIL_M_4, byt) ++CHIPSET(0x0155, BAYTRAIL_D, byt) +diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h +index 885f6c2..04753dd 100644 +--- a/src/mesa/drivers/dri/intel/intel_chipset.h ++++ b/src/mesa/drivers/dri/intel/intel_chipset.h +@@ -87,6 +87,12 @@ + #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */ + #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a + ++#define PCI_CHIP_BAYTRAIL_M_1 0x0F31 ++#define PCI_CHIP_BAYTRAIL_M_2 0x0F32 ++#define PCI_CHIP_BAYTRAIL_M_3 0x0F33 ++#define PCI_CHIP_BAYTRAIL_M_4 0x0157 ++#define PCI_CHIP_BAYTRAIL_D 0x0155 ++ + #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ + #define PCI_CHIP_HASWELL_GT2 0x0412 + #define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 +@@ -190,7 +196,14 @@ + + #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || IS_IVB_GT2(devid)) + ++#define IS_BAYTRAIL(devid) (devid == PCI_CHIP_BAYTRAIL_M_1 || \ ++ devid == PCI_CHIP_BAYTRAIL_M_2 || \ ++ devid == PCI_CHIP_BAYTRAIL_M_3 || \ ++ devid == PCI_CHIP_BAYTRAIL_M_4 || \ ++ devid == PCI_CHIP_BAYTRAIL_D) ++ + #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ ++ IS_BAYTRAIL(devid) || \ + IS_HASWELL(devid)) + + #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ +diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c +index ba7d4b6..0a1dd75 100644 +--- a/src/mesa/drivers/dri/intel/intel_context.c ++++ b/src/mesa/drivers/dri/intel/intel_context.c +@@ -186,6 +186,13 @@ intelGetString(struct gl_context * ctx, GLenum name) + case PCI_CHIP_IVYBRIDGE_S_GT2: + chipset = "Intel(R) Ivybridge Server"; + break; ++ case PCI_CHIP_BAYTRAIL_M_1: ++ case PCI_CHIP_BAYTRAIL_M_2: ++ case PCI_CHIP_BAYTRAIL_M_3: ++ case PCI_CHIP_BAYTRAIL_M_4: ++ case PCI_CHIP_BAYTRAIL_D: ++ chipset = "Intel(R) Bay Trail"; ++ break; + case PCI_CHIP_HASWELL_GT1: + case PCI_CHIP_HASWELL_GT2: + case PCI_CHIP_HASWELL_GT2_PLUS: +@@ -682,6 +689,9 @@ intelInitContext(struct intel_context *intel, + + if (IS_HASWELL(devID)) { + intel->is_haswell = true; ++ } else if (IS_BAYTRAIL(devID)) { ++ intel->is_baytrail = true; ++ intel->gt = 1; + } else if (IS_G4X(devID)) { + intel->is_g4x = true; + } else if (IS_945(devID)) { +diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h +index 4591ab7..c0f07ff 100644 +--- a/src/mesa/drivers/dri/intel/intel_context.h ++++ b/src/mesa/drivers/dri/intel/intel_context.h +@@ -236,6 +236,7 @@ struct intel_context + int gt; + bool needs_ff_sync; + bool is_haswell; ++ bool is_baytrail; + bool is_g4x; + bool is_945; + bool has_separate_stencil; only in patch2: unchanged: --- mesa-lts-quantal-9.0.3.orig/debian/patches/add-more-reserved-hsw-ids.diff +++ mesa-lts-quantal-9.0.3/debian/patches/add-more-reserved-hsw-ids.diff @@ -0,0 +1,231 @@ +commit ce67fb4715e0c2fab01de33da475ef4705622020 +Author: Rodrigo Vivi +Date: Mon May 13 17:53:39 2013 -0300 + + i965: Adding more reserved PCI IDs for Haswell. + + At DDX commit Chris mentioned the tendency we have of finding out more + PCI IDs only when users report. So Let's add all new reserved Haswell IDs. + + NOTE: This is a candidate for stable branches. + + Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701 + Signed-off-by: Rodrigo Vivi + Acked-by: Kenneth Graunke + +diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h +index 3e9765c..808eb4e 100644 +--- a/include/pci_ids/i965_pci_ids.h ++++ b/include/pci_ids/i965_pci_ids.h +@@ -35,6 +35,12 @@ CHIPSET(0x0426, HASWELL_M_GT3, hsw_gt3) + CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1) + CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2) + CHIPSET(0x042A, HASWELL_S_GT3, hsw_gt3) ++CHIPSET(0x040B, HASWELL_B_GT1, hsw_gt1) ++CHIPSET(0x041B, HASWELL_B_GT2, hsw_gt2) ++CHIPSET(0x042B, HASWELL_B_GT3, hsw_gt3) ++CHIPSET(0x040E, HASWELL_E_GT1, hsw_gt1) ++CHIPSET(0x041E, HASWELL_E_GT2, hsw_gt2) ++CHIPSET(0x042E, HASWELL_E_GT3, hsw_gt3) + CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1) + CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2) + CHIPSET(0x0C22, HASWELL_SDV_GT3, hsw_gt3) +@@ -44,6 +50,12 @@ CHIPSET(0x0C26, HASWELL_SDV_M_GT3, hsw_gt3) + CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1) + CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2) + CHIPSET(0x0C2A, HASWELL_SDV_S_GT3, hsw_gt3) ++CHIPSET(0x0C0B, HASWELL_SDV_B_GT1, hsw_gt1) ++CHIPSET(0x0C1B, HASWELL_SDV_B_GT2, hsw_gt2) ++CHIPSET(0x0C2B, HASWELL_SDV_B_GT3, hsw_gt3) ++CHIPSET(0x0C0E, HASWELL_SDV_E_GT1, hsw_gt1) ++CHIPSET(0x0C1E, HASWELL_SDV_E_GT2, hsw_gt2) ++CHIPSET(0x0C2E, HASWELL_SDV_E_GT3, hsw_gt3) + CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1) + CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2) + CHIPSET(0x0A22, HASWELL_ULT_GT3, hsw_gt3) +@@ -53,6 +65,12 @@ CHIPSET(0x0A26, HASWELL_ULT_M_GT3, hsw_gt3) + CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1) + CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2) + CHIPSET(0x0A2A, HASWELL_ULT_S_GT3, hsw_gt3) ++CHIPSET(0x0A0B, HASWELL_ULT_B_GT1, hsw_gt1) ++CHIPSET(0x0A1B, HASWELL_ULT_B_GT2, hsw_gt2) ++CHIPSET(0x0A2B, HASWELL_ULT_B_GT3, hsw_gt3) ++CHIPSET(0x0A0E, HASWELL_ULT_E_GT1, hsw_gt1) ++CHIPSET(0x0A1E, HASWELL_ULT_E_GT2, hsw_gt2) ++CHIPSET(0x0A2E, HASWELL_ULT_E_GT3, hsw_gt3) + CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1) + CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2) + CHIPSET(0x0D22, HASWELL_CRW_GT3, hsw_gt3) +@@ -62,6 +80,12 @@ CHIPSET(0x0D26, HASWELL_CRW_M_GT3, hsw_gt3) + CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1) + CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2) + CHIPSET(0x0D2A, HASWELL_CRW_S_GT3, hsw_gt3) ++CHIPSET(0x0D0B, HASWELL_CRW_B_GT1, hsw_gt1) ++CHIPSET(0x0D1B, HASWELL_CRW_B_GT2, hsw_gt2) ++CHIPSET(0x0D2B, HASWELL_CRW_B_GT3, hsw_gt3) ++CHIPSET(0x0D0E, HASWELL_CRW_E_GT1, hsw_gt1) ++CHIPSET(0x0D1E, HASWELL_CRW_E_GT2, hsw_gt2) ++CHIPSET(0x0D2E, HASWELL_CRW_E_GT3, hsw_gt3) + CHIPSET(0x0F31, BAYTRAIL_M_1, byt) + CHIPSET(0x0F32, BAYTRAIL_M_2, byt) + CHIPSET(0x0F33, BAYTRAIL_M_3, byt) +diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h +index ee735bb..1e98cf4 100644 +--- a/src/mesa/drivers/dri/intel/intel_chipset.h ++++ b/src/mesa/drivers/dri/intel/intel_chipset.h +@@ -102,6 +102,12 @@ + #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ + #define PCI_CHIP_HASWELL_S_GT2 0x041A + #define PCI_CHIP_HASWELL_S_GT3 0x042A ++#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */ ++#define PCI_CHIP_HASWELL_B_GT2 0x041B ++#define PCI_CHIP_HASWELL_B_GT3 0x042B ++#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */ ++#define PCI_CHIP_HASWELL_E_GT2 0x041E ++#define PCI_CHIP_HASWELL_E_GT3 0x042E + #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ + #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 + #define PCI_CHIP_HASWELL_SDV_GT3 0x0C22 +@@ -111,6 +117,12 @@ + #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ + #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A + #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A ++#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */ ++#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B ++#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B ++#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */ ++#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E ++#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E + #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ + #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 + #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 +@@ -120,6 +132,12 @@ + #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ + #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A + #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A ++#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */ ++#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B ++#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B ++#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */ ++#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E ++#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E + #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ + #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 + #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 +@@ -129,6 +147,12 @@ + #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ + #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A + #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A ++#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */ ++#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B ++#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B ++#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */ ++#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E ++#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E + + #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ + devid == PCI_CHIP_I915_GM || \ +@@ -209,39 +233,63 @@ + #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ + devid == PCI_CHIP_HASWELL_M_GT1 || \ + devid == PCI_CHIP_HASWELL_S_GT1 || \ ++ devid == PCI_CHIP_HASWELL_B_GT1 || \ ++ devid == PCI_CHIP_HASWELL_E_GT1 || \ + devid == PCI_CHIP_HASWELL_SDV_GT1 || \ + devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \ + devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \ ++ devid == PCI_CHIP_HASWELL_SDV_B_GT1 || \ ++ devid == PCI_CHIP_HASWELL_SDV_E_GT1 || \ + devid == PCI_CHIP_HASWELL_ULT_GT1 || \ + devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \ + devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \ ++ devid == PCI_CHIP_HASWELL_ULT_B_GT1 || \ ++ devid == PCI_CHIP_HASWELL_ULT_E_GT1 || \ + devid == PCI_CHIP_HASWELL_CRW_GT1 || \ + devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \ +- devid == PCI_CHIP_HASWELL_CRW_S_GT1) ++ devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \ ++ devid == PCI_CHIP_HASWELL_CRW_B_GT1 || \ ++ devid == PCI_CHIP_HASWELL_CRW_E_GT1) + #define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \ + devid == PCI_CHIP_HASWELL_M_GT2 || \ + devid == PCI_CHIP_HASWELL_S_GT2 || \ ++ devid == PCI_CHIP_HASWELL_B_GT2 || \ ++ devid == PCI_CHIP_HASWELL_E_GT2 || \ + devid == PCI_CHIP_HASWELL_SDV_GT2 || \ + devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \ + devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \ ++ devid == PCI_CHIP_HASWELL_SDV_B_GT2 || \ ++ devid == PCI_CHIP_HASWELL_SDV_E_GT2 || \ + devid == PCI_CHIP_HASWELL_ULT_GT2 || \ + devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \ + devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \ ++ devid == PCI_CHIP_HASWELL_ULT_B_GT2 || \ ++ devid == PCI_CHIP_HASWELL_ULT_E_GT2 || \ + devid == PCI_CHIP_HASWELL_CRW_GT2 || \ + devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \ +- devid == PCI_CHIP_HASWELL_CRW_S_GT2) ++ devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \ ++ devid == PCI_CHIP_HASWELL_CRW_B_GT2 || \ ++ devid == PCI_CHIP_HASWELL_CRW_E_GT2) + #define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_GT3 || \ + devid == PCI_CHIP_HASWELL_M_GT3 || \ + devid == PCI_CHIP_HASWELL_S_GT3 || \ ++ devid == PCI_CHIP_HASWELL_B_GT3 || \ ++ devid == PCI_CHIP_HASWELL_E_GT3 || \ + devid == PCI_CHIP_HASWELL_SDV_GT3 || \ + devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \ + devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \ ++ devid == PCI_CHIP_HASWELL_SDV_B_GT3 || \ ++ devid == PCI_CHIP_HASWELL_SDV_E_GT3 || \ + devid == PCI_CHIP_HASWELL_ULT_GT3 || \ + devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \ + devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \ ++ devid == PCI_CHIP_HASWELL_ULT_B_GT3 || \ ++ devid == PCI_CHIP_HASWELL_ULT_E_GT3 || \ + devid == PCI_CHIP_HASWELL_CRW_GT3 || \ + devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \ +- devid == PCI_CHIP_HASWELL_CRW_S_GT3) ++ devid == PCI_CHIP_HASWELL_CRW_S_GT3 || \ ++ devid == PCI_CHIP_HASWELL_CRW_B_GT3 || \ ++ devid == PCI_CHIP_HASWELL_CRW_E_GT3) + + #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ + IS_HSW_GT2(devid) || \ +diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c +index 88cc247..ab7f80b 100644 +--- a/src/mesa/drivers/dri/intel/intel_context.c ++++ b/src/mesa/drivers/dri/intel/intel_context.c +@@ -235,6 +235,32 @@ intelGetString(struct gl_context * ctx, GLenum name) + case PCI_CHIP_HASWELL_CRW_S_GT3: + chipset = "Intel(R) Haswell Server"; + break; ++ case PCI_CHIP_HASWELL_B_GT1: ++ case PCI_CHIP_HASWELL_B_GT2: ++ case PCI_CHIP_HASWELL_B_GT3: ++ case PCI_CHIP_HASWELL_SDV_B_GT1: ++ case PCI_CHIP_HASWELL_SDV_B_GT2: ++ case PCI_CHIP_HASWELL_SDV_B_GT3: ++ case PCI_CHIP_HASWELL_ULT_B_GT1: ++ case PCI_CHIP_HASWELL_ULT_B_GT2: ++ case PCI_CHIP_HASWELL_ULT_B_GT3: ++ case PCI_CHIP_HASWELL_CRW_B_GT1: ++ case PCI_CHIP_HASWELL_CRW_B_GT2: ++ case PCI_CHIP_HASWELL_CRW_B_GT3: ++ case PCI_CHIP_HASWELL_E_GT1: ++ case PCI_CHIP_HASWELL_E_GT2: ++ case PCI_CHIP_HASWELL_E_GT3: ++ case PCI_CHIP_HASWELL_SDV_E_GT1: ++ case PCI_CHIP_HASWELL_SDV_E_GT2: ++ case PCI_CHIP_HASWELL_SDV_E_GT3: ++ case PCI_CHIP_HASWELL_ULT_E_GT1: ++ case PCI_CHIP_HASWELL_ULT_E_GT2: ++ case PCI_CHIP_HASWELL_ULT_E_GT3: ++ case PCI_CHIP_HASWELL_CRW_E_GT1: ++ case PCI_CHIP_HASWELL_CRW_E_GT2: ++ case PCI_CHIP_HASWELL_CRW_E_GT3: ++ chipset = "Intel(R) Haswell"; ++ break; + default: + chipset = "Unknown Intel Chipset"; + break; only in patch2: unchanged: --- mesa-lts-quantal-9.0.3.orig/debian/patches/use-a-variable-for-the-push-constant-size-in-kb.diff +++ mesa-lts-quantal-9.0.3/debian/patches/use-a-variable-for-the-push-constant-size-in-kb.diff @@ -0,0 +1,38 @@ +commit d4311138e47224acea21f5ecde74a9ea2aee994f +Author: Kenneth Graunke +Date: Tue Apr 2 21:11:51 2013 -0700 + + i965: Use a variable for the push constant size in kB. + + This clarifies that the offset of 2 is actually 16 kB / 8kB units. + It also keys both computations off of a single variable, which should + make it easier to change in the future. + + Signed-off-by: Kenneth Graunke + Reviewed-by: Paul Berry + (cherry picked from commit 967514ce680f7bf785ab544c6174786dd20425de) + +diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c +index dafe1ad..5ac3885 100644 +--- a/src/mesa/drivers/dri/i965/gen7_urb.c ++++ b/src/mesa/drivers/dri/i965/gen7_urb.c +@@ -78,8 +78,9 @@ static void + gen7_upload_urb(struct brw_context *brw) + { + struct intel_context *intel = &brw->intel; ++ const int push_size_kB = 16; + /* Total space for entries is URB size - 16kB for push constants */ +- int handle_region_size = (brw->urb.size - 16) * 1024; /* bytes */ ++ int handle_region_size = (brw->urb.size - push_size_kB) * 1024; /* bytes */ + + /* CACHE_NEW_VS_PROG */ + unsigned vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1); +@@ -92,7 +93,7 @@ gen7_upload_urb(struct brw_context *brw) + brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 8); + + /* URB Starting Addresses are specified in multiples of 8kB. */ +- brw->urb.vs_start = 2; /* skip over push constants */ ++ brw->urb.vs_start = push_size_kB / 8; /* skip over push constants */ + + assert(brw->urb.nr_vs_entries % 8 == 0); + assert(brw->urb.nr_gs_entries % 8 == 0); only in patch2: unchanged: --- mesa-lts-quantal-9.0.3.orig/debian/patches/fix-hsw-crw-ids.diff +++ mesa-lts-quantal-9.0.3/debian/patches/fix-hsw-crw-ids.diff @@ -0,0 +1,68 @@ +commit b88f74d63dca9db0f1b1cb9ce4d85f706c7a7fab +Author: Kenneth Graunke +Date: Fri Mar 1 15:23:53 2013 -0800 + + i965: Fix Crystal Well PCI IDs. + + The second digit was off by one, which meant we accidentally treated + GTn as GT(n-1). This also meant no support for GT1 at all. + + NOTE: This is a candidate for stable branches. + + Signed-off-by: Kenneth Graunke + +diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h +index 09dca5b..1e388f8 100644 +--- a/include/pci_ids/i965_pci_ids.h ++++ b/include/pci_ids/i965_pci_ids.h +@@ -53,12 +53,12 @@ CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2) + CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1) + CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2) + CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2) +-CHIPSET(0x0D12, HASWELL_CRW_GT1, hsw_gt1) +-CHIPSET(0x0D22, HASWELL_CRW_GT2, hsw_gt2) +-CHIPSET(0x0D32, HASWELL_CRW_GT2_PLUS, hsw_gt2) +-CHIPSET(0x0D16, HASWELL_CRW_M_GT1, hsw_gt1) +-CHIPSET(0x0D26, HASWELL_CRW_M_GT2, hsw_gt2) +-CHIPSET(0x0D36, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) +-CHIPSET(0x0D1A, HASWELL_CRW_S_GT1, hsw_gt1) +-CHIPSET(0x0D2A, HASWELL_CRW_S_GT2, hsw_gt2) +-CHIPSET(0x0D3A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1) ++CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2) ++CHIPSET(0x0D22, HASWELL_CRW_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0D06, HASWELL_CRW_M_GT1, hsw_gt1) ++CHIPSET(0x0D16, HASWELL_CRW_M_GT2, hsw_gt2) ++CHIPSET(0x0D26, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1) ++CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2) ++CHIPSET(0x0D2A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) +diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h +index 9c00ba8..885f6c2 100644 +--- a/src/mesa/drivers/dri/intel/intel_chipset.h ++++ b/src/mesa/drivers/dri/intel/intel_chipset.h +@@ -114,15 +114,15 @@ + #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ + #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A + #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A +-#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */ +-#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22 +-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 +-#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ +-#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 +-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 +-#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ +-#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A +-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A ++#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ ++#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 ++#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22 ++#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ ++#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 ++#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 ++#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ ++#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A ++#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A + + #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ + devid == PCI_CHIP_I915_GM || \ only in patch2: unchanged: --- mesa-lts-quantal-9.0.3.orig/debian/patches/fix-hsw-gt3-names.diff +++ mesa-lts-quantal-9.0.3/debian/patches/fix-hsw-gt3-names.diff @@ -0,0 +1,238 @@ +commit f1d2b373177dbbb582cefb0d6c88994073fab652 +Author: Paulo Zanoni +Date: Fri Aug 10 12:06:37 2012 -0300 + + i965: make GT3 machines work as GT3 instead of GT2 + + We were not allowed to say the "GT3" name, but we really needed to + have the PCI IDs because too many people had such machines, so we had + to make the GT3 machines work as GT2. + + Let's just say that GT2_PLUS was a short for GT2_PLUS_1 :) + + NOTE: This is a candidate for stable branches. + + Signed-off-by: Paulo Zanoni + Signed-off-by: Kenneth Graunke + +diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h +index 9a2da61..3e9765c 100644 +--- a/include/pci_ids/i965_pci_ids.h ++++ b/include/pci_ids/i965_pci_ids.h +@@ -28,40 +28,40 @@ CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1) + CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2) + CHIPSET(0x0402, HASWELL_GT1, hsw_gt1) + CHIPSET(0x0412, HASWELL_GT2, hsw_gt2) +-CHIPSET(0x0422, HASWELL_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0422, HASWELL_GT3, hsw_gt3) + CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1) + CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2) +-CHIPSET(0x0426, HASWELL_M_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0426, HASWELL_M_GT3, hsw_gt3) + CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1) + CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2) +-CHIPSET(0x042A, HASWELL_S_GT2_PLUS, hsw_gt2) ++CHIPSET(0x042A, HASWELL_S_GT3, hsw_gt3) + CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1) + CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2) +-CHIPSET(0x0C22, HASWELL_SDV_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0C22, HASWELL_SDV_GT3, hsw_gt3) + CHIPSET(0x0C06, HASWELL_SDV_M_GT1, hsw_gt1) + CHIPSET(0x0C16, HASWELL_SDV_M_GT2, hsw_gt2) +-CHIPSET(0x0C26, HASWELL_SDV_M_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0C26, HASWELL_SDV_M_GT3, hsw_gt3) + CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1) + CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2) +-CHIPSET(0x0C2A, HASWELL_SDV_S_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0C2A, HASWELL_SDV_S_GT3, hsw_gt3) + CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1) + CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2) +-CHIPSET(0x0A22, HASWELL_ULT_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0A22, HASWELL_ULT_GT3, hsw_gt3) + CHIPSET(0x0A06, HASWELL_ULT_M_GT1, hsw_gt1) + CHIPSET(0x0A16, HASWELL_ULT_M_GT2, hsw_gt2) +-CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0A26, HASWELL_ULT_M_GT3, hsw_gt3) + CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1) + CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2) +-CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0A2A, HASWELL_ULT_S_GT3, hsw_gt3) + CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1) + CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2) +-CHIPSET(0x0D22, HASWELL_CRW_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0D22, HASWELL_CRW_GT3, hsw_gt3) + CHIPSET(0x0D06, HASWELL_CRW_M_GT1, hsw_gt1) + CHIPSET(0x0D16, HASWELL_CRW_M_GT2, hsw_gt2) +-CHIPSET(0x0D26, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0D26, HASWELL_CRW_M_GT3, hsw_gt3) + CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1) + CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2) +-CHIPSET(0x0D2A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) ++CHIPSET(0x0D2A, HASWELL_CRW_S_GT3, hsw_gt3) + CHIPSET(0x0F31, BAYTRAIL_M_1, byt) + CHIPSET(0x0F32, BAYTRAIL_M_2, byt) + CHIPSET(0x0F33, BAYTRAIL_M_3, byt) +diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h +index 04753dd..df025ac 100644 +--- a/src/mesa/drivers/dri/intel/intel_chipset.h ++++ b/src/mesa/drivers/dri/intel/intel_chipset.h +@@ -95,40 +95,40 @@ + + #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ + #define PCI_CHIP_HASWELL_GT2 0x0412 +-#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 ++#define PCI_CHIP_HASWELL_GT3 0x0422 + #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ + #define PCI_CHIP_HASWELL_M_GT2 0x0416 +-#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 ++#define PCI_CHIP_HASWELL_M_GT3 0x0426 + #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ + #define PCI_CHIP_HASWELL_S_GT2 0x041A +-#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A ++#define PCI_CHIP_HASWELL_S_GT3 0x042A + #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ + #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 +-#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22 ++#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22 + #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ + #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 +-#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 ++#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26 + #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ + #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A +-#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A ++#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A + #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ + #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 +-#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22 ++#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 + #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ + #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 +-#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 ++#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 + #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ + #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A +-#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A ++#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A + #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ + #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 +-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22 ++#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 + #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ + #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 +-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 ++#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 + #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ + #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A +-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A ++#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A + + #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ + devid == PCI_CHIP_I915_GM || \ +@@ -229,21 +229,23 @@ + devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \ + devid == PCI_CHIP_HASWELL_CRW_GT2 || \ + devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \ +- devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \ +- devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \ +- devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \ +- devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \ +- devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \ +- devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \ +- devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \ +- devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \ +- devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \ +- devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \ +- devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \ +- devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS) ++ devid == PCI_CHIP_HASWELL_CRW_S_GT2) ++ ++#define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_M_GT3 || \ ++ devid == PCI_CHIP_HASWELL_S_GT3 || \ ++ devid == PCI_CHIP_HASWELL_SDV_GT3 || \ ++ devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \ ++ devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \ ++ devid == PCI_CHIP_HASWELL_ULT_GT3 || \ ++ devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \ ++ devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \ ++ devid == PCI_CHIP_HASWELL_CRW_GT3 || \ ++ devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \ ++ devid == PCI_CHIP_HASWELL_CRW_S_GT3) + + #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ +- IS_HSW_GT2(devid)) ++ IS_HSW_GT2(devid) || \ ++ IS_HSW_GT3(devid)) + + #define IS_965(devid) (IS_GEN4(devid) || \ + IS_G4X(devid) || \ +diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c +index 0a1dd75..88cc247 100644 +--- a/src/mesa/drivers/dri/intel/intel_context.c ++++ b/src/mesa/drivers/dri/intel/intel_context.c +@@ -195,44 +195,44 @@ intelGetString(struct gl_context * ctx, GLenum name) + break; + case PCI_CHIP_HASWELL_GT1: + case PCI_CHIP_HASWELL_GT2: +- case PCI_CHIP_HASWELL_GT2_PLUS: ++ case PCI_CHIP_HASWELL_GT3: + case PCI_CHIP_HASWELL_SDV_GT1: + case PCI_CHIP_HASWELL_SDV_GT2: +- case PCI_CHIP_HASWELL_SDV_GT2_PLUS: ++ case PCI_CHIP_HASWELL_SDV_GT3: + case PCI_CHIP_HASWELL_ULT_GT1: + case PCI_CHIP_HASWELL_ULT_GT2: +- case PCI_CHIP_HASWELL_ULT_GT2_PLUS: ++ case PCI_CHIP_HASWELL_ULT_GT3: + case PCI_CHIP_HASWELL_CRW_GT1: + case PCI_CHIP_HASWELL_CRW_GT2: +- case PCI_CHIP_HASWELL_CRW_GT2_PLUS: ++ case PCI_CHIP_HASWELL_CRW_GT3: + chipset = "Intel(R) Haswell Desktop"; + break; + case PCI_CHIP_HASWELL_M_GT1: + case PCI_CHIP_HASWELL_M_GT2: +- case PCI_CHIP_HASWELL_M_GT2_PLUS: ++ case PCI_CHIP_HASWELL_M_GT3: + case PCI_CHIP_HASWELL_SDV_M_GT1: + case PCI_CHIP_HASWELL_SDV_M_GT2: +- case PCI_CHIP_HASWELL_SDV_M_GT2_PLUS: ++ case PCI_CHIP_HASWELL_SDV_M_GT3: + case PCI_CHIP_HASWELL_ULT_M_GT1: + case PCI_CHIP_HASWELL_ULT_M_GT2: +- case PCI_CHIP_HASWELL_ULT_M_GT2_PLUS: ++ case PCI_CHIP_HASWELL_ULT_M_GT3: + case PCI_CHIP_HASWELL_CRW_M_GT1: + case PCI_CHIP_HASWELL_CRW_M_GT2: +- case PCI_CHIP_HASWELL_CRW_M_GT2_PLUS: ++ case PCI_CHIP_HASWELL_CRW_M_GT3: + chipset = "Intel(R) Haswell Mobile"; + break; + case PCI_CHIP_HASWELL_S_GT1: + case PCI_CHIP_HASWELL_S_GT2: +- case PCI_CHIP_HASWELL_S_GT2_PLUS: ++ case PCI_CHIP_HASWELL_S_GT3: + case PCI_CHIP_HASWELL_SDV_S_GT1: + case PCI_CHIP_HASWELL_SDV_S_GT2: +- case PCI_CHIP_HASWELL_SDV_S_GT2_PLUS: ++ case PCI_CHIP_HASWELL_SDV_S_GT3: + case PCI_CHIP_HASWELL_ULT_S_GT1: + case PCI_CHIP_HASWELL_ULT_S_GT2: +- case PCI_CHIP_HASWELL_ULT_S_GT2_PLUS: ++ case PCI_CHIP_HASWELL_ULT_S_GT3: + case PCI_CHIP_HASWELL_CRW_S_GT1: + case PCI_CHIP_HASWELL_CRW_S_GT2: +- case PCI_CHIP_HASWELL_CRW_S_GT2_PLUS: ++ case PCI_CHIP_HASWELL_CRW_S_GT3: + chipset = "Intel(R) Haswell Server"; + break; + default: +@@ -684,6 +684,8 @@ intelInitContext(struct intel_context *intel, + intel->gt = 1; + else if (IS_SNB_GT2(devID) || IS_IVB_GT2(devID) || IS_HSW_GT2(devID)) + intel->gt = 2; ++ else if (IS_HSW_GT3(devID)) ++ intel->gt = 3; + else + intel->gt = 0; +