diff -Nru qemu-5.0/debian/changelog qemu-5.0/debian/changelog --- qemu-5.0/debian/changelog 2021-03-26 09:36:31.000000000 +0000 +++ qemu-5.0/debian/changelog 2021-04-07 09:58:29.000000000 +0000 @@ -1,3 +1,13 @@ +qemu (1:5.0-5ubuntu9.8) groovy; urgency=medium + + * d/p/u/lp-1921754*: add EPYC-Rome-v2 as v1 missed IBRS and thereby fails + on some HW/Guest combinations e.g. Windows 10 on Threadripper chips + (LP: #1921754) + * d/p/u/lp-1921880*: add EPYC-Milan features and named cpu type support + (LP: #1921880) + + -- Christian Ehrhardt Wed, 07 Apr 2021 11:58:29 +0200 + qemu (1:5.0-5ubuntu9.7) groovy; urgency=medium * d/p/u/lp-1921468-*: fix issues handling boot menu index on s390x diff -Nru qemu-5.0/debian/patches/series qemu-5.0/debian/patches/series --- qemu-5.0/debian/patches/series 2021-03-26 09:36:31.000000000 +0000 +++ qemu-5.0/debian/patches/series 2021-04-07 09:58:29.000000000 +0000 @@ -122,3 +122,7 @@ ubuntu/lp-1887535-configure-replace-enable-disable-git-update-with-wit.patch ubuntu/lp-1921665-1-block-Require-aligned-image-size-to-avoid-assert.patch ubuntu/lp-1921665-2-file-posix-Allow-byte-aligned-O_DIRECT-with-NFS.patch +ubuntu/lp-1921880-target-i386-add-fast-short-REP-MOV-support.patch +ubuntu/lp-1921880-x86-cpu-Populate-SVM-CPUID-feature-bits.patch +ubuntu/lp-1921880-i386-Add-the-support-for-AMD-EPYC-3rd-generation-pro.patch +ubuntu/lp-1921754-Add-missing-cpu-feature-bits-in-EPYC-Rome-model.patch diff -Nru qemu-5.0/debian/patches/ubuntu/lp-1921754-Add-missing-cpu-feature-bits-in-EPYC-Rome-model.patch qemu-5.0/debian/patches/ubuntu/lp-1921754-Add-missing-cpu-feature-bits-in-EPYC-Rome-model.patch --- qemu-5.0/debian/patches/ubuntu/lp-1921754-Add-missing-cpu-feature-bits-in-EPYC-Rome-model.patch 1970-01-01 00:00:00.000000000 +0000 +++ qemu-5.0/debian/patches/ubuntu/lp-1921754-Add-missing-cpu-feature-bits-in-EPYC-Rome-model.patch 2021-04-07 09:58:29.000000000 +0000 @@ -0,0 +1,45 @@ +Found the following cpu feature bits missing from EPYC-Rome model. +ibrs : Indirect Branch Restricted Speculation +ssbd : Speculative Store Bypass Disable + +These new features will be added in EPYC-Rome-v2. The -cpu help output +after the change. + +x86 EPYC-Rome (alias configured by machine type) +x86 EPYC-Rome-v1 AMD EPYC-Rome Processor +x86 EPYC-Rome-v2 AMD EPYC-Rome Processor + +Reported-by: Pankaj Gupta +Signed-off-by: Babu Moger +Signed-off-by: Pankaj Gupta + +Backport-Note: 0c1538cb1 was applied in 5.0 and not yet reverted (in 5.2) +Origin: backport, https://git.qemu.org/?p=qemu.git;a=commit;h=cdeaed2778 +Bug-Ubuntu: https://bugs.launchpad.net/bugs/1921754 +Last-Update: 2021-04-07 + +--- + target/i386/cpu.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -4117,6 +4117,18 @@ static X86CPUDefinition builtin_x86_defs + .model_id = "AMD EPYC-Rome Processor", + .cache_info = &epyc_rome_cache_info, + .use_epyc_apic_id_encoding = 1, ++ .versions = (X86CPUVersionDefinition[]) { ++ { .version = 1 }, ++ { ++ .version = 2, ++ .props = (PropValue[]) { ++ { "ibrs", "on" }, ++ { "amd-ssbd", "on" }, ++ { /* end of list */ } ++ } ++ }, ++ { /* end of list */ } ++ } + }, + { + .name = "EPYC-Milan", diff -Nru qemu-5.0/debian/patches/ubuntu/lp-1921880-i386-Add-the-support-for-AMD-EPYC-3rd-generation-pro.patch qemu-5.0/debian/patches/ubuntu/lp-1921880-i386-Add-the-support-for-AMD-EPYC-3rd-generation-pro.patch --- qemu-5.0/debian/patches/ubuntu/lp-1921880-i386-Add-the-support-for-AMD-EPYC-3rd-generation-pro.patch 1970-01-01 00:00:00.000000000 +0000 +++ qemu-5.0/debian/patches/ubuntu/lp-1921880-i386-Add-the-support-for-AMD-EPYC-3rd-generation-pro.patch 2021-04-07 09:58:29.000000000 +0000 @@ -0,0 +1,198 @@ +From 623972ceae091b31331ae4a1dc94fe5cbb891937 Mon Sep 17 00:00:00 2001 +From: Babu Moger +Date: Tue, 9 Feb 2021 15:04:05 -0600 +Subject: [PATCH] i386: Add the support for AMD EPYC 3rd generation processors + +Adds the support for AMD 3rd generation processors. The model +display for the new processor will be EPYC-Milan. + +Adds the following new feature bits on top of the feature bits from +the first and second generation EPYC models. + +pcid : Process context identifiers support +ibrs : Indirect Branch Restricted Speculation +ssbd : Speculative Store Bypass Disable +erms : Enhanced REP MOVSB/STOSB support +fsrm : Fast Short REP MOVSB support +invpcid : Invalidate processor context ID +pku : Protection keys support +svme-addr-chk : SVM instructions address check for #GP handling + +Depends on the following kernel commits: +14c2bf81fcd2 ("KVM: SVM: Fix #GP handling for doubly-nested virtualization") +3b9c723ed7cf ("KVM: SVM: Add support for SVM instruction address check change") +4aa2691dcbd3 ("8ce1c461188799d863398dd2865d KVM: x86: Factor out x86 instruction emulation with decoding") +4407a797e941 ("KVM: SVM: Enable INVPCID feature on AMD") +9715092f8d7e ("KVM: X86: Move handling of INVPCID types to x86") +3f3393b3ce38 ("KVM: X86: Rename and move the function vmx_handle_memory_failure to x86.c") +830bd71f2c06 ("KVM: SVM: Remove set_cr_intercept, clr_cr_intercept and is_cr_intercept") +4c44e8d6c193 ("KVM: SVM: Add new intercept word in vmcb_control_area") +c62e2e94b9d4 ("KVM: SVM: Modify 64 bit intercept field to two 32 bit vectors") +9780d51dc2af ("KVM: SVM: Modify intercept_exceptions to generic intercepts") +30abaa88382c ("KVM: SVM: Change intercept_dr to generic intercepts") +03bfeeb988a9 ("KVM: SVM: Change intercept_cr to generic intercepts") +c45ad7229d13 ("KVM: SVM: Introduce vmcb_(set_intercept/clr_intercept/_is_intercept)") +a90c1ed9f11d ("(pcid) KVM: nSVM: Remove unused field") +fa44b82eb831 ("KVM: x86: Move MPK feature detection to common code") +38f3e775e9c2 ("x86/Kconfig: Update config and kernel doc for MPK feature on AMD") +37486135d3a7 ("KVM: x86: Fix pkru save/restore when guest CR4.PKE=0, move it to x86.c") + +Signed-off-by: Babu Moger +Message-Id: <161290460478.11352.8933244555799318236.stgit@bmoger-ubuntu> +Signed-off-by: Eduardo Habkost + +Backport-Note: 0c1538cb1 was applied in 5.0 and not yet reverted (in 5.2) +Origin: backport, https://git.qemu.org/?p=qemu.git;a=commit;h=623972ce +Bug-Ubuntu: https://bugs.launchpad.net/bugs/1921880 +Last-Update: 2021-04-07 + +--- + target/i386/cpu.c | 107 +++++++++++++++++++++++++++++++++++++++++++++- + target/i386/cpu.h | 4 ++ + 2 files changed, 110 insertions(+), 1 deletion(-) + +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -1040,7 +1040,7 @@ static FeatureWordInfo feature_word_info + "clzero", NULL, "xsaveerptr", NULL, + NULL, NULL, NULL, NULL, + NULL, "wbnoinvd", NULL, NULL, +- "ibpb", NULL, NULL, "amd-stibp", ++ "ibpb", NULL, "ibrs", "amd-stibp", + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, +@@ -1771,6 +1771,56 @@ static CPUCaches epyc_rome_cache_info = + }, + }; + ++static CPUCaches epyc_milan_cache_info = { ++ .l1d_cache = &(CPUCacheInfo) { ++ .type = DATA_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l1i_cache = &(CPUCacheInfo) { ++ .type = INSTRUCTION_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l2_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 2, ++ .size = 512 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 1024, ++ .lines_per_tag = 1, ++ }, ++ .l3_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 3, ++ .size = 32 * MiB, ++ .line_size = 64, ++ .associativity = 16, ++ .partitions = 1, ++ .sets = 32768, ++ .lines_per_tag = 1, ++ .self_init = true, ++ .inclusive = true, ++ .complex_indexing = true, ++ }, ++}; ++ + /* The following VMX features are not supported by KVM and are left out in the + * CPU definitions: + * +@@ -4068,6 +4118,61 @@ static X86CPUDefinition builtin_x86_defs + .cache_info = &epyc_rome_cache_info, + .use_epyc_apic_id_encoding = 1, + }, ++ { ++ .name = "EPYC-Milan", ++ .level = 0xd, ++ .vendor = CPUID_VENDOR_AMD, ++ .family = 25, ++ .model = 1, ++ .stepping = 1, ++ .features[FEAT_1_EDX] = ++ CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | ++ CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | ++ CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | ++ CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | ++ CPUID_VME | CPUID_FP87, ++ .features[FEAT_1_ECX] = ++ CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | ++ CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | ++ CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | ++ CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | ++ CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | ++ CPUID_EXT_PCID, ++ .features[FEAT_8000_0001_EDX] = ++ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | ++ CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | ++ CPUID_EXT2_SYSCALL, ++ .features[FEAT_8000_0001_ECX] = ++ CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | ++ CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | ++ CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | ++ CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, ++ .features[FEAT_8000_0008_EBX] = ++ CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | ++ CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | ++ CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | ++ CPUID_8000_0008_EBX_AMD_SSBD, ++ .features[FEAT_7_0_EBX] = ++ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | ++ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | ++ CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | ++ CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | ++ CPUID_7_0_EBX_INVPCID, ++ .features[FEAT_7_0_ECX] = ++ CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, ++ .features[FEAT_7_0_EDX] = ++ CPUID_7_0_EDX_FSRM, ++ .features[FEAT_XSAVE] = ++ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | ++ CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, ++ .features[FEAT_6_EAX] = ++ CPUID_6_EAX_ARAT, ++ .features[FEAT_SVM] = ++ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, ++ .xlevel = 0x8000001E, ++ .model_id = "AMD EPYC-Milan Processor", ++ .cache_info = &epyc_milan_cache_info, ++ }, + }; + + /* KVM-specific features that are automatically added/removed +--- a/target/i386/cpu.h ++++ b/target/i386/cpu.h +@@ -798,8 +798,12 @@ typedef uint64_t FeatureWordArray[FEATUR + #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) + /* Indirect Branch Prediction Barrier */ + #define CPUID_8000_0008_EBX_IBPB (1U << 12) ++/* Indirect Branch Restricted Speculation */ ++#define CPUID_8000_0008_EBX_IBRS (1U << 14) + /* Single Thread Indirect Branch Predictors */ + #define CPUID_8000_0008_EBX_STIBP (1U << 15) ++/* Speculative Store Bypass Disable */ ++#define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) + + #define CPUID_XSAVE_XSAVEOPT (1U << 0) + #define CPUID_XSAVE_XSAVEC (1U << 1) diff -Nru qemu-5.0/debian/patches/ubuntu/lp-1921880-target-i386-add-fast-short-REP-MOV-support.patch qemu-5.0/debian/patches/ubuntu/lp-1921880-target-i386-add-fast-short-REP-MOV-support.patch --- qemu-5.0/debian/patches/ubuntu/lp-1921880-target-i386-add-fast-short-REP-MOV-support.patch 1970-01-01 00:00:00.000000000 +0000 +++ qemu-5.0/debian/patches/ubuntu/lp-1921880-target-i386-add-fast-short-REP-MOV-support.patch 2021-04-07 09:58:29.000000000 +0000 @@ -0,0 +1,48 @@ +From 5cb287d2bd578dfe4897458793b4fce35bc4f744 Mon Sep 17 00:00:00 2001 +From: Chenyi Qiang +Date: Tue, 14 Jul 2020 16:41:46 +0800 +Subject: [PATCH] target/i386: add fast short REP MOV support + +For CPUs support fast short REP MOV[CPUID.(EAX=7,ECX=0):EDX(bit4)], e.g +Icelake and Tigerlake, expose it to the guest VM. + +Reviewed-by: Eduardo Habkost +Signed-off-by: Chenyi Qiang +Message-Id: <20200714084148.26690-2-chenyi.qiang@intel.com> +Signed-off-by: Eduardo Habkost + +Backport-Note: +Some noise due to missing the less used/requested + - 353f98c9 avx512-vp2intersect + - b3c7344e tsx-ldtrk +Origin: backport, https://git.qemu.org/?p=qemu.git;a=commit;h=5cb287d2 +Bug-Ubuntu: https://bugs.launchpad.net/bugs/1921880 +Last-Update: 2021-04-07 + +--- + target/i386/cpu.c | 2 +- + target/i386/cpu.h | 2 ++ + 2 files changed, 3 insertions(+), 1 deletion(-) + +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -1077,7 +1077,7 @@ static FeatureWordInfo feature_word_info + .type = CPUID_FEATURE_WORD, + .feat_names = { + NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", +- NULL, NULL, NULL, NULL, ++ "fsrm", NULL, NULL, NULL, + NULL, NULL, "md-clear", NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL /* pconfig */, NULL, +--- a/target/i386/cpu.h ++++ b/target/i386/cpu.h +@@ -769,6 +769,8 @@ typedef uint64_t FeatureWordArray[FEATUR + #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) + /* AVX512 Multiply Accumulation Single Precision */ + #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) ++/* Fast Short Rep Mov */ ++#define CPUID_7_0_EDX_FSRM (1U << 4) + /* Speculation Control */ + #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) + /* Single Thread Indirect Branch Predictors */ diff -Nru qemu-5.0/debian/patches/ubuntu/lp-1921880-x86-cpu-Populate-SVM-CPUID-feature-bits.patch qemu-5.0/debian/patches/ubuntu/lp-1921880-x86-cpu-Populate-SVM-CPUID-feature-bits.patch --- qemu-5.0/debian/patches/ubuntu/lp-1921880-x86-cpu-Populate-SVM-CPUID-feature-bits.patch 1970-01-01 00:00:00.000000000 +0000 +++ qemu-5.0/debian/patches/ubuntu/lp-1921880-x86-cpu-Populate-SVM-CPUID-feature-bits.patch 2021-04-07 09:58:29.000000000 +0000 @@ -0,0 +1,83 @@ +From 5447089c2b3b084b51670af36fc86ee3979e04be Mon Sep 17 00:00:00 2001 +From: Wei Huang +Date: Tue, 26 Jan 2021 14:24:56 -0600 +Subject: [PATCH] x86/cpu: Populate SVM CPUID feature bits + +Newer AMD CPUs will add CPUID_0x8000000A_EDX[28] bit, which indicates +that SVM instructions (VMRUN/VMSAVE/VMLOAD) will trigger #VMEXIT before +CPU checking their EAX against reserved memory regions. This change will +allow the hypervisor to avoid intercepting #GP and emulating SVM +instructions. KVM turns on this CPUID bit for nested VMs. In order to +support it, let us populate this bit, along with other SVM feature bits, +in FEAT_SVM. + +Signed-off-by: Wei Huang +Message-Id: <20210126202456.589932-1-wei.huang2@amd.com> +Signed-off-by: Paolo Bonzini + +Origin: upstream, https://git.qemu.org/?p=qemu.git;a=commit;h=5447089c +Bug-Ubuntu: https://bugs.launchpad.net/bugs/1921880 +Last-Update: 2021-04-07 + +--- + target/i386/cpu.c | 6 +++--- + target/i386/cpu.h | 24 ++++++++++++++---------- + 2 files changed, 17 insertions(+), 13 deletions(-) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index e775e9abb5..ff25ad6f6c 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -926,11 +926,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { + "npt", "lbrv", "svm-lock", "nrip-save", + "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", + NULL, NULL, "pause-filter", NULL, +- "pfthreshold", NULL, NULL, NULL, +- NULL, NULL, NULL, NULL, +- NULL, NULL, NULL, NULL, ++ "pfthreshold", "avic", NULL, "v-vmsave-vmload", ++ "vgif", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, ++ "svme-addr-chk", NULL, NULL, NULL, + }, + .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, + .tcg_features = TCG_SVM_FEATURES, +diff --git a/target/i386/cpu.h b/target/i386/cpu.h +index d23a5b340a..b39ec505de 100644 +--- a/target/i386/cpu.h ++++ b/target/i386/cpu.h +@@ -670,16 +670,20 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; + #define CPUID_EXT3_PERFCORE (1U << 23) + #define CPUID_EXT3_PERFNB (1U << 24) + +-#define CPUID_SVM_NPT (1U << 0) +-#define CPUID_SVM_LBRV (1U << 1) +-#define CPUID_SVM_SVMLOCK (1U << 2) +-#define CPUID_SVM_NRIPSAVE (1U << 3) +-#define CPUID_SVM_TSCSCALE (1U << 4) +-#define CPUID_SVM_VMCBCLEAN (1U << 5) +-#define CPUID_SVM_FLUSHASID (1U << 6) +-#define CPUID_SVM_DECODEASSIST (1U << 7) +-#define CPUID_SVM_PAUSEFILTER (1U << 10) +-#define CPUID_SVM_PFTHRESHOLD (1U << 12) ++#define CPUID_SVM_NPT (1U << 0) ++#define CPUID_SVM_LBRV (1U << 1) ++#define CPUID_SVM_SVMLOCK (1U << 2) ++#define CPUID_SVM_NRIPSAVE (1U << 3) ++#define CPUID_SVM_TSCSCALE (1U << 4) ++#define CPUID_SVM_VMCBCLEAN (1U << 5) ++#define CPUID_SVM_FLUSHASID (1U << 6) ++#define CPUID_SVM_DECODEASSIST (1U << 7) ++#define CPUID_SVM_PAUSEFILTER (1U << 10) ++#define CPUID_SVM_PFTHRESHOLD (1U << 12) ++#define CPUID_SVM_AVIC (1U << 13) ++#define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) ++#define CPUID_SVM_VGIF (1U << 16) ++#define CPUID_SVM_SVME_ADDR_CHK (1U << 28) + + /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ + #define CPUID_7_0_EBX_FSGSBASE (1U << 0) +-- +2.31.1 +