diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/bin/bugzilla_mesa.sh mesa-10.6.3+git20150809+10.6.736f6e16/bin/bugzilla_mesa.sh --- mesa-10.6.3~git20150727+10.6.ccef8901/bin/bugzilla_mesa.sh 2014-04-20 07:52:19.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/bin/bugzilla_mesa.sh 2015-08-09 06:15:27.000000000 +0000 @@ -15,17 +15,14 @@ # $ DRYRUN=yes bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3 | wc -l -# regex pattern: trim before url -trim_before='s/.*\(http\)/\1/' +# regex pattern: trim before bug number +trim_before='s/.*show_bug.cgi?id=\([0-9]*\).*/\1/' -# regex pattern: trim after url -trim_after='s/\(show_bug.cgi?id=[0-9]*\).*/\1/' - -# regex pattern: always use https -use_https='s/http:/https:/' +# regex pattern: reconstruct the url +use_after='s,^,https://bugs.freedesktop.org/show_bug.cgi?id=,' # extract fdo urls from commit log -urls=$(git log $* | grep 'bugs.freedesktop.org/show_bug' | sed -e $trim_before -e $trim_after -e $use_https | sort | uniq) +urls=$(git log $* | grep 'bugs.freedesktop.org/show_bug' | sed -e $trim_before | sort -n -u | sed -e $use_after) # if DRYRUN is set to "yes", simply print the URLs and don't fetch the # details from fdo bugzilla. diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/ChangeLog mesa-10.6.3+git20150809+10.6.736f6e16/ChangeLog --- mesa-10.6.3~git20150727+10.6.ccef8901/ChangeLog 2015-07-27 05:58:10.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/ChangeLog 2015-08-09 06:16:24.000000000 +0000 @@ -1,9 +1,552 @@ -commit 8f2d65f7e730b48d1d045bcb5fc2f5e6e03c8915 +commit 0131677d488783887a5c74fb27b29e1110dffc4b Author: Rico Tzschichholz -Date: Mon Jul 27 07:57:14 2015 +0200 +Date: Sun Aug 9 08:15:27 2015 +0200 Add debian tree from origin/ubuntu+1 +commit 736f6e16d9989f01cc55dcba15ba978ba90b7748 +Author: Francisco Jerez +Date: Wed Aug 5 16:29:30 2015 +0300 + + i965/fs: Fix fs_inst::regs_read() for sources in the ATTR file. + + Otherwise it would crash on Gen8 with scalar VS. The issue can easily + be reproduced with the following patch, but I don't see any reason why + it wouldn't be possible to end up with an ATTR argument here even + without it. + + CC: mesa-stable@lists.freedesktop.org + Reviewed-by: Connor Abbott + Reviewed-by: Jason Ekstrand + (cherry picked from commit 42a18ca76057621ae7d8812b29ea2245d6ff282d) + +commit f13ba8a5ab537e6dcdcc8b0c1a814012202d2497 +Author: Eduardo Lima Mitev +Date: Wed Jul 29 16:01:28 2015 +0200 + + mesa: Fix error returned by glCopyTexImage2D() upon an invalid internal format + + Page 161 of the OpenGL-ES 3.1 (PDF) spec, and page 207 of the OpenGL 4.5 (PDF), + both on section '8.6. ALTERNATE TEXTURE IMAGE SPECIFICATION COMMANDS', states: + + "An INVALID_ENUM error is generated if an invalid value is specified for + internalformat". + + It is currently returning INVALID_OPERATION error because + _mesa_get_read_renderbuffer_for_format() is called before the internalformat + argument has been validated. To fix this, we move this call down the validation + process, after _mesa_base_tex_format() has been called. _mesa_base_tex_format() + effectively serves as a validator for the internal format. + + Fixes 1 dEQP test: + * dEQP-GLES3.functional.negative_api.texture.copyteximage2d_invalid_format + + Fixes 1 piglit test: + * spec@oes_compressed_etc1_rgb8_texture@basic + + Reviewed-by: Ian Romanick + Cc: 10.6 + (cherry picked from commit 4b07e9a033ddb6733eba206b5bd47a2373756f7d) + +commit 791cf8a025ac0d610596cdfab17fc84b49df2288 +Author: Eduardo Lima Mitev +Date: Wed Jul 29 16:01:26 2015 +0200 + + mesa: Validate target before resolving tex obj in glTex(ture)SubImageXD + + Currently, glTexSubImageXD attempt to resolve the texture object + (by calling _mesa_get_current_tex_object()) before validating the given + target. However, that method explicitly states that target must have been + validated before calling it, so it never returns a user error. + + The target validation occurs later when texsubimage_error_check() is called. + + This patch reorganizes target validation, taking it out from the error check + function and into a point before the texture object is resolved. + + Reviewed-by: Ian Romanick + Cc: 10.6 + (cherry picked from commit 5d64cae8427b090c42d6d38da7fb474b3ddd4eb0) + [Emil Velikov: s/_mesa_enum_to_string/_mesa_lookup_enum_by_nr/] + Signed-off-by: Emil Velikov + + Conflicts: + src/mesa/main/teximage.c + +commit 58b2e95c1f09aafdfe5434f433ed7dc7a628e7a8 +Author: Eduardo Lima Mitev +Date: Wed Jul 29 16:01:23 2015 +0200 + + mesa: Fix errors values returned by glShaderBinary() + + Page 68, section 7.2 'Shader Binaries" of the of the OpenGL ES 3.1, + and page 88 of the OpenGL 4.5 specs state: + + "An INVALID_VALUE error is generated if count or length is negative. + An INVALID_ENUM error is generated if binaryformat is not a supported + format returned in SHADER_BINARY_FORMATS." + + Currently, an INVALID_OPERATION error is returned for all cases. + + Fixes 1 dEQP test: + * dEQP-GLES3.functional.negative_api.shader.shader_binary + + Reviewed-by: Ian Romanick + Cc: 10.6 + (cherry picked from commit b38a50f1e3edae6079c91f73a8d9c63a2dbf512a) + +commit 1f6798a70a6d7e6db636decc6af752f9a7714906 +Author: Frank Binns +Date: Fri Jul 31 09:11:45 2015 +0100 + + egl: Add eglQuerySurface surface type check for EGL_LARGEST_PBUFFER attrib + + Calling eglQuerySurface on a window or pixmap with the EGL_LARGEST_PBUFFER + attribute resulted in the contents of the 'value' parameter being modified. + This is the wrong behaviour according to the EGL spec, which states: + + "Querying EGL_LARGEST_PBUFFER for a pbuffer surface returns the + same attribute value specified when the surface was created with + eglCreatePbufferSurface. For a window or pixmap surface, the + contents of value are not modified." + + Avoid this from happening by checking that the surface type is EGL_PBUFFER_BIT + before modifying the contents of the parameter. + + Cc: + Signed-off-by: Frank Binns + Reviewed-by: Emil Velikov + Reviewed-by: Eric Anholt + (cherry picked from commit b2c5986ea1c8e66c4e0a05bcacbcf28c27f5b183) + +commit 84ef345dffec02d790db13fd6257e2c08eb0d56a +Author: Frank Binns +Date: Fri Jul 31 09:11:46 2015 +0100 + + egl/dri: Add error info needed for EGL_EXT_image_dma_buf_import extension + + Update the DRI image interface error codes to reflect the needs of the + EGL_EXT_image_dma_buf_import extension. This means updating the existing error + code documentation and adding a new __DRI_IMAGE_ERROR_BAD_ACCESS error code + so that drivers can correctly reject unsupported pitches and offsets. Hook + the new error code up in EGL to return EGL_BAD_ACCESS. + + Cc: + Signed-off-by: Frank Binns + Reviewed-by: Emil Velikov + Reviewed-by: Eric Anholt + (cherry picked from commit cfc3200a35647026a0b5cf188f378ce33802044b) + +commit 7722a24cab4b8880d45fb723205e2eedfada2055 +Author: Marek Olšák +Date: Sun Aug 2 15:18:36 2015 +0200 + + r600g: fix the CB_SHADER_MASK setup + + This fixes the single-sample fast clear hang. + + Cc: 10.6 + Tested-by: Dieter Nützel + Reviewed-by: Dave Airlie + (cherry picked from commit d4ad4c20617f45f71152e292ee39f020ef352bfd) + +commit 880a0ce2e973d5ed9ee28c3f48fc5332128f9652 +Author: Marek Olšák +Date: Sat Jul 25 00:53:16 2015 +0200 + + radeonsi: completely rework updating descriptors without CP DMA + + For 10.6: This fixes graphical corruption occuring on most Southern Islands + Radeon GPUs. This will allow closing a lot of bugs in the bugzilla. + + The patch has a better explanation. Just a summary here: + - The CPU always uploads a whole descriptor array to previously-unused memory. + - CP DMA isn't used. + - No caches need to be flushed. + - All descriptors are always up-to-date in memory even after a hang, because + CP DMA doesn't serve as a middle man to update them. + + This should bring: + - better hang recovery (descriptors are always up-to-date) + - better GPU performance (no KCACHE and TC flushes) + - worse CPU performance for partial updates (only whole arrays are uploaded) + - less used IB space (no CP_DMA and WRITE_DATA packets) + - simpler code + - corruption issues are fixed on SI cards + + Reviewed-by: Michel Dänzer + (cherry picked from commit b0528118dfb1af00e7d08cdb637191b80c14c2ba) + +commit 842a3af20b6d5dc12e2025be8005531d5da6285c +Author: Marek Olšák +Date: Mon Sep 15 23:34:28 2014 +0200 + + radeonsi: rework how shader pointers to descriptors are set + + For 10.6: This is a prerequisite for the next fix. The below comment is from + the original commit. + + This is mainly needed for tessellation where a VS can be bound as VS, ES, + or LS, and TES (tess. evaluationshader) can be bound as VS or ES or neither. + Therefore we need the ability to move pointers to descriptors between + shaders arbitrarily. + + The idea is that the context has a mapping from PIPE_SHADER_x to + SPI_SHADER_USER_DATA_x. After a shader is enabled or disabled, + si_shader_change_notify should be called to update this mapping accordingly. + + There is a dirty flag for each shader pointer, but only one emit function + for all pointers in the whole context, whose code and logic is separated + from descriptors. + + Reviewed-by: Michel Dänzer + (cherry picked from commit 3ce91c727f2a00a05f414351266b0b45d677611e) + +commit bc29f8f6b7b4a9bf575e401bd08bebe87d7dc863 +Author: Igor Gnatenko +Date: Tue Jul 7 13:05:04 2015 +0300 + + opencl: use versioned .so in mesa.icd + + We must have versioned library in mesa.icd, because ICD loader would + fail if the mesa-devel package wasn't installed. + + Cc: "10.6" + Reported-by: Fabian Deutsch + Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73512 + Signed-off-by: Igor Gnatenko + Reviewed-by: Emil Velikov + Acked-by: Michel Dänzer + (cherry picked from commit 4d7e0fa8c731776ad5d630f37b36c535f1907371) + +commit f2f62059dc5c9b548127c31bc7875c6836716944 +Author: Emil Velikov +Date: Mon Jul 13 20:01:39 2015 +0100 + + bugzilla_mesa.sh: sort the bugs list by number + + v2: Use change sed/sort based on Ilia's suggestion. + + Signed-off-by: Emil Velikov + (cherry picked from commit c505064b2cea14c9da115a26e9326b9c0c7dca3b) + +commit 2a72e18abbe9286d16e388eb1a004147f0b6e54b +Author: Samuel Pitoiset +Date: Mon Jul 6 23:34:23 2015 +0200 + + nv50: avoid segfault with enabled but unbound vertex attrib + + Before validating vertex arrays we need to check if a VBO is present. + Checking if vb->buffer is not NULL fixes the issue. + + Fixes the following piglit test: + gl-3.1-vao-broken-attrib + + Signed-off-by: Samuel Pitoiset + Reviewed-by: Ilia Mirkin + (cherry picked from commit adc816a1e41812e6489a5bc388f80de65504be5b) + +commit b70176d96b1b5033d4bc1414fd63758ebd144787 +Author: Emil Velikov +Date: Wed Jul 29 15:44:32 2015 +0100 + + winsys/radeon: don't leak the fd when it is 0 + + Earlier commit added an extra dup(fd) to fix a ZaphodHeads issue. + Although it did not consider the (very unlikely) case where we might end + up with the valid fd == 0. + + Fixes: 28dda47ae4d(winsys/radeon: Use dup fd as key in drm-winsys hash + table to fix ZaphodHeads.) + + Cc: 10.6 + Signed-off-by: Emil Velikov + Reviewed-by: Alex Deucher + Reviewed-by: Mario Kleiner + (cherry picked from commit 1307be519b8785249ee863a22115930299ff642a) + +commit d8116f8ec531980d287e5fcb1091acfe2fcffb8d +Author: Emil Velikov +Date: Fri Jul 10 11:01:55 2015 +0100 + + egl/wayland: libdrm is a hard requirement, treat it as such + + Prompt at configure time if it's missing otherwise we'll fail later on + in the build. Remove ambiguous HAVE_LIBDRM guard. + + Cc: 10.6 + Signed-off-by: Emil Velikov + (cherry picked from commit fa109d02dda118f756903b663879375c06353ae7) + +commit 8f8c842338b11185e8432e4b44e31a85abcbf9c6 +Author: Ben Widawsky +Date: Wed Jul 29 12:35:24 2015 -0700 + + i965/skl: Add production thread counts and URB size + + This patch adjusts the SKL values to the best known values we have. + + v2: Remove HS/DS/CS fields. Adding this makes most sense to add to the + GEN9_FEATURES macro, however, doing that would require updating BXT values, and + Jordan requested I not do that. Conveniently, this request makes a lot of sense + wrt to stable backport as HS, and DS do not even exist there. + + Cc: mesa-stable@lists.freedesktop.org + Signed-off-by: Ben Widawsky + Reviewed-by: Jordan Justen + (cherry picked from commit 7eaacc1678195738fab3bb98870828611cae066d) + [Emil Velikov: .supports_simd16_3src is missing in 10.6] + Signed-off-by: Emil Velikov + + Conflicts: + src/mesa/drivers/dri/i965/brw_device_info.c + +commit eddea78fb36039e03478e11780c8a32c06c1c435 +Author: Kenneth Graunke +Date: Wed Jul 22 20:08:23 2015 -0700 + + glsl: Fix a bug where LHS swizzles of swizzles were too small. + + A simple shader such as + + vec4 color; + color.xy.x = 1.0; + + would cause ir_assignment::set_lhs() to generate bogus IR: + + (swiz xy (swiz x (constant float (1.0)))) + + We were setting the number of components of each new RHS swizzle based + on the highest channel used in the LHS swizzle. So, .xy.y would + generate (swiz xy (swiz xx ...)), while .xy.x would break. + + Our existing Piglit test happened to use .xzy.z, which worked, since + 'z' is the third component, resulting in an xxx swizzle. + + This patch sets the number of swizzle components based on the size of + the LHS swizzle's inner value, so we always have the correct number + at each step. + + Fixes new Piglit tests glsl-vs-swizzle-swizzle-lhs-[23]. + Fixes ir_validate assertions in in Metro 2033 Redux. + + v2: Move num_components updating completely out of update_rhs_swizzle + (suggested by Timothy Arceri). Simplify. + + Cc: mesa-stable@lists.freedesktop.org + Signed-off-by: Kenneth Graunke + Reviewed-by: Timothy Arceri + (cherry picked from commit e235ca159f5f6de2bd29616fdda5c02dc69b0d7f) + +commit 080c4713bcd4c0c3643b3fb3ede1aa09f891aecf +Author: Marek Olšák +Date: Fri Jul 24 19:47:06 2015 +0200 + + st/mesa: don't ignore texture buffer state changes + + Fixes piglit: + spec@arb_texture_buffer_range@ranges-2 + + Cc: mesa-stable@lists.freedesktop.org + Reviewed-by: Brian Paul + (cherry picked from commit e39ece0d7856d0532a0f011cd5cb17bc85ee82e2) + [Emil Velikov: resolve tess related conflicts.] + Signed-off-by: Emil Velikov + + Conflicts: + src/mesa/state_tracker/st_atom_texture.c + src/mesa/state_tracker/st_context.c + src/mesa/state_tracker/st_context.h + +commit ba10c9ff5088b99591c13cad0b70929b49e6319c +Author: Ilia Mirkin +Date: Sat Jul 11 12:47:03 2015 -0400 + + nvc0: fix geometry program revalidation of clipping params + + Signed-off-by: Ilia Mirkin + Reviewed-by: Samuel Pitoiset + Cc: mesa-stable@lists.freedesktop.org + (cherry picked from commit a818faa6ddcfa6cd90a24b70c49ec76573954111) + +commit f167d9b46cd41e8c750bdfd65a05c04545546236 +Author: Anuj Phogat +Date: Tue May 12 05:46:04 2015 -0700 + + meta: Fix reading luminance texture as rgba in _mesa_meta_pbo_GetTexSubImage() + + After recent addition of pbo testing in piglit test getteximage-luminance, + it fails on i965. This patch makes a sub test pass. + + This patch adds a clear color operation to meta pbo path, which I think is + better than falling back to software path. + + V2: Fix color mask for GL_LUMINANCE_ALPHA + + Cc: + Signed-off-by: Anuj Phogat + Reviewed-by: Iago Toral Quiroga + (cherry picked from commit aa40546b2de4cd572af02d31fd5c7d4045505ea2) + +commit def2d2e018abbab381ea329a8472bded18b45659 +Author: Anuj Phogat +Date: Thu Jun 11 16:48:26 2015 -0700 + + mesa: Add a helper function _mesa_need_luminance_to_rgb_conversion() + + Cc: + Signed-off-by: Anuj Phogat + Reviewed-by: Iago Toral Quiroga + (cherry picked from commit c59c0f8a42652603da7f89e3270897cb685fe76b) + +commit 831bf63e6b55c4f1f610a2fb988906550157172a +Author: Anuj Phogat +Date: Wed May 6 05:43:08 2015 -0700 + + meta: Don't do fragment color clamping in _mesa_meta_pbo_GetTexSubImage + + _mesa_meta_pbo_GetTexSubImage() uses _mesa_meta_BlitFrameBuffer(), + which will do fragment clamping if enabled. But fragment clamping + doesn't affect ReadPixels and GetTexImage. + + Without this patch, piglit test arb_color_buffer_float-clear fails, + when forced to use the meta pbo path. + + v2: Apply this fix to both glReadPixels and glGetTexImage. + + Cc: + Signed-off-by: Anuj Phogat + Reviewed-by: Iago Toral Quiroga + (cherry picked from commit ca4e17e03e9aeaa04fe6bb04bfe2d6f97991005b) + +commit 6321bf72be877fe3efc81bd9e3c6d645d6b6ed9a +Author: Anuj Phogat +Date: Wed May 20 10:22:45 2015 -0700 + + meta: Abort meta pbo path if readpixels need signed-unsigned conversion + + Meta pbo path for ReadPixels rely on BlitFramebuffer which doesn't support + signed to unsigned integer conversions and vice versa. + + Without this patch, piglit test fbo_integer_readpixels_sint_uint fails, when + forced to use the meta pbo path. + + v2: Make need_signed_unsigned_int_conversion() a static function. (Iago) + Bump up the comment and the commit message. (Jason) + + Signed-off-by: Anuj Phogat + Cc: + Reviewed-by: Jason Ekstrand + Reviewed-by: Iago Toral + (cherry picked from commit 0d207905e675b778739236072e7a4dfba7cd7959) + +commit acaac69ccd3d8d70044aab98dbadc5b177510eb5 +Author: Anuj Phogat +Date: Wed May 20 10:21:39 2015 -0700 + + meta: Fix transfer operations check in meta pbo path for readpixels + + Currently used ctx->_ImageTransferState check is not sufficient + because it doesn't include the read color clamping enabled with + GL_CLAMP_READ_COLOR. So, use the helper function + _mesa_get_readpixels_transfer_ops(). + + Also, transfer operations don't affect glGetTexImage(). So, do + the check only for glReadPixles. + + Without this patch, arb_color_buffer_float-readpixels test fails, when + forced to use meta pbo path. + + V2: Add a comment and bump up the commit message. + + Signed-off-by: Anuj Phogat + Cc: + Reviewed-by: Iago Toral Quiroga + (cherry picked from commit 1252d53c19ec005c17ca666cecb7db072d77e5ce) + +commit fbc464803a777bea4f9b7b11eeba192122adf8cb +Author: Anuj Phogat +Date: Tue May 19 17:44:52 2015 -0700 + + mesa: Turn get_readpixels_transfer_ops() in to a global function + + This utility function is utilized in a later patch. + + Cc: + Signed-off-by: Anuj Phogat + Reviewed-by: Iago Toral Quiroga + (cherry picked from commit 7974e23be9ff7586e5250cff321b6ec7749ecc44) + +commit 56e4cc67fec63d86d76f5b4de55678890cf06648 +Author: Samuel Iglesias Gonsalvez +Date: Thu Jul 23 10:38:36 2015 +0200 + + glsl/glcpp: fix SIGSEGV when checking error condition for macro redefinition + + Commit a6e9cd14c does not take into account than node_{a,b}->next could be NULL + in some circumstances, such as in a shader containing this code: + + #define A 1 /* comment */ + #define A 1 /* comment */ + + This patch fixes the segmentation fault for cases like that. + + Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91290 + Signed-off-by: Samuel Iglesias Gonsalvez + Reviewed-by: Anuj Phogat + Cc: mesa-stable@lists.freedesktop.org + (cherry picked from commit 30f97b5e52b324d501c56df8902d294fb755a5b7) + +commit a31dfd91b500735c44bb89e194f02b718299bf2e +Author: Marek Olšák +Date: Fri Jul 10 23:35:55 2015 +0200 + + radeonsi: upload shader rodata after updating scratch relocations + + Cc: 10.5 10.6 + Reviewed-by: Tom Stellard + Reviewed-by: Michel Dänzer + (cherry picked from commit 50a957c5de842b18e10c361f7b0310aa46bb483f) + Signed-off-by: Emil Velikov + + Conflicts: + src/gallium/drivers/radeonsi/si_shader.c + src/gallium/drivers/radeonsi/si_shader.h + +commit 504903b827604f1a630a335d14231f88c2cf36be +Author: Marek Olšák +Date: Thu Jul 16 17:14:07 2015 +0200 + + st/mesa: don't call st_validate_state in BlitFramebuffer + + None of the draw states are used here. + This fixes a crash in piglit: ext_framebuffer_blit/blit-early + + Calling st_manager_validate_framebuffers is the minimum requirement here. + + Cc: mesa-stable@lists.freedesktop.org + (cherry picked from commit d082c5324914212f76e45be497229c7a0681f706) + +commit c33ca1696a0a967091937805fa198ffc3317a03f +Author: Emil Velikov +Date: Thu Jul 9 21:19:15 2015 +0100 + + configure.ac: do not set HAVE_DRI(23) when libdrm is missing + + These conditionals are used to guard both dri modules and loader(s). + + Currently if we try to build the gallium swrast dri module (without glx) + on a system that's missing libdrm the build will fail. + + v2: Make sure we assign prior to checking the have_libdrm variable. + + Cc: 10.6 + Signed-off-by: Emil Velikov + (cherry picked from commit 16f6d432de07dcb537dafd0c9f3ef7614891ed6b) + + Conflicts: + configure.ac + commit ccef8901de421eae5dcc8affa14218d46cc06593 Author: Emil Velikov Date: Sun Jul 26 15:18:24 2015 +0100 diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/configure.ac mesa-10.6.3+git20150809+10.6.736f6e16/configure.ac --- mesa-10.6.3~git20150727+10.6.ccef8901/configure.ac 2015-07-27 05:57:14.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/configure.ac 2015-08-09 06:15:27.000000000 +0000 @@ -63,6 +63,8 @@ dnl Set internal versions OSMESA_VERSION=8 AC_SUBST([OSMESA_VERSION]) +OPENCL_VERSION=1 +AC_SUBST([OPENCL_VERSION]) dnl Versions for external dependencies LIBDRM_REQUIRED=2.4.38 @@ -909,6 +911,13 @@ AM_CONDITIONAL(HAVE_DRI_GLX, test "x$enable_glx" = xyes -a \ "x$enable_dri" = xyes) +# Check for libdrm +PKG_CHECK_MODULES([LIBDRM], [libdrm >= $LIBDRM_REQUIRED], + [have_libdrm=yes], [have_libdrm=no]) +if test "x$have_libdrm" = xyes; then + DEFINES="$DEFINES -DHAVE_LIBDRM" +fi + # Select which platform-dependent DRI code gets built case "$host_os" in darwin*) @@ -921,8 +930,8 @@ AM_CONDITIONAL(HAVE_DRICOMMON, test "x$enable_dri" = xyes ) AM_CONDITIONAL(HAVE_DRISW, test "x$enable_dri" = xyes ) -AM_CONDITIONAL(HAVE_DRI2, test "x$enable_dri" = xyes -a "x$dri_platform" = xdrm ) -AM_CONDITIONAL(HAVE_DRI3, test "x$enable_dri3" = xyes -a "x$dri_platform" = xdrm ) +AM_CONDITIONAL(HAVE_DRI2, test "x$enable_dri" = xyes -a "x$dri_platform" = xdrm -a "x$have_libdrm" = xyes ) +AM_CONDITIONAL(HAVE_DRI3, test "x$enable_dri3" = xyes -a "x$dri_platform" = xdrm -a "x$have_libdrm" = xyes ) AM_CONDITIONAL(HAVE_APPLEDRI, test "x$enable_dri" = xyes -a "x$dri_platform" = xapple ) AC_ARG_ENABLE([shared-glapi], @@ -978,13 +987,6 @@ AC_SUBST([MESA_LLVM]) -# Check for libdrm -PKG_CHECK_MODULES([LIBDRM], [libdrm >= $LIBDRM_REQUIRED], - [have_libdrm=yes], [have_libdrm=no]) -if test "x$have_libdrm" = xyes; then - DEFINES="$DEFINES -DHAVE_LIBDRM" -fi - case "$host_os" in linux*) need_pci_id=yes ;; @@ -1627,6 +1629,9 @@ for plat in $egl_platforms; do case "$plat" in wayland) + test "x$have_libdrm" != xyes && + AC_MSG_ERROR([EGL platform wayland requires libdrm >= $LIBDRM_REQUIRED]) + PKG_CHECK_MODULES([WAYLAND], [wayland-client >= $WAYLAND_REQUIRED wayland-server >= $WAYLAND_REQUIRED]) if test "x$WAYLAND_SCANNER" = x; then @@ -2238,6 +2243,7 @@ src/gallium/targets/libgl-xlib/Makefile src/gallium/targets/omx/Makefile src/gallium/targets/opencl/Makefile + src/gallium/targets/opencl/mesa.icd src/gallium/targets/osmesa/Makefile src/gallium/targets/osmesa/osmesa.pc src/gallium/targets/pipe-loader/Makefile diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/debian/changelog mesa-10.6.3+git20150809+10.6.736f6e16/debian/changelog --- mesa-10.6.3~git20150727+10.6.ccef8901/debian/changelog 2015-08-09 06:28:18.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/debian/changelog 2015-08-09 06:28:19.000000000 +0000 @@ -1,7 +1,7 @@ -mesa (10.6.3~git20150727+10.6.ccef8901-0ubuntu0ricotz~trusty) trusty; urgency=medium +mesa (10.6.3+git20150809+10.6.736f6e16-0ubuntu0ricotz~trusty) trusty; urgency=medium - * Checkout from git 20150727 (10.6 branch) up to commit - ccef8901de421eae5dcc8affa14218d46cc06593 + * Checkout from git 20150809 (10.6 branch) up to commit + 736f6e16d9989f01cc55dcba15ba978ba90b7748 * Only added debian/ tree from origin/ubuntu+1 * hook: Disable MIR support. * hook: Relax symbols check. @@ -10,9 +10,9 @@ (upstream) * hook: update symbols. - -- Rico Tzschichholz Mon, 27 Jul 2015 07:58:11 +0200 + -- Rico Tzschichholz Sun, 09 Aug 2015 08:16:25 +0200 -mesa (10.6.1-0ubuntu1) UNRELEASED; urgency=medium +mesa (10.6.3-0ubuntu1) UNRELEASED; urgency=medium * Merge from debian-experimental git. * Drop skl-*, i965-* patches, upstream. @@ -20,14 +20,25 @@ -- Timo Aaltonen Thu, 18 Jun 2015 15:31:27 +0300 -mesa (10.6.1-1) UNRELEASED; urgency=medium +mesa (10.6.3-1) unstable; urgency=medium * New upstream release. * libegl1-mesa.symbols: Updated. * not-installed: Dropped wmesa.h which is gone. * libgles{1,2}-mesa.symbols: Updated. + * libegl1-mesa.symbols: Drop a spurious comment. + * source/local-options: Updated extend-diff-ignore. + * mesa-common-dev.docs: Updated. + * Delete i965-do_blit...patch, upstream. - -- Timo Aaltonen Mon, 27 Apr 2015 10:43:45 +0300 + -- Timo Aaltonen Tue, 28 Jul 2015 11:12:44 +0300 + +mesa (10.5.9-2) unstable; urgency=medium + + * i965-do_blit_drawpixels-decode-array-formats.patch: Fix a regression + since 10.5.5, allow using blit fastpath again. + + -- Timo Aaltonen Fri, 10 Jul 2015 13:01:40 +0300 mesa (10.5.9-1ubuntu1) wily; urgency=medium diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/debian/libegl1-mesa.symbols mesa-10.6.3+git20150809+10.6.736f6e16/debian/libegl1-mesa.symbols --- mesa-10.6.3~git20150727+10.6.ccef8901/debian/libegl1-mesa.symbols 2015-08-09 06:28:18.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/debian/libegl1-mesa.symbols 2015-08-09 06:28:19.000000000 +0000 @@ -1,7 +1,4 @@ libEGL.so.1 libegl1-mesa #MINVER# | libegl1-x11 -# These are all internal symbols between libEGL and the -# drivers. Handle the dependency explicitly in the driver -# package. eglBindAPI@Base 7.8.1 eglBindTexImage@Base 7.8.1 eglChooseConfig@Base 7.8.1 diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/debian/mesa-common-dev.docs mesa-10.6.3+git20150809+10.6.736f6e16/debian/mesa-common-dev.docs --- mesa-10.6.3~git20150727+10.6.ccef8901/debian/mesa-common-dev.docs 2015-08-09 06:28:18.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/debian/mesa-common-dev.docs 2015-08-09 06:28:19.000000000 +0000 @@ -1,8 +1,4 @@ -docs/bugs.html -docs/debugging.html -docs/envvars.html -docs/faq.html -docs/osmesa.html -docs/RELNOTES-* -docs/relnotes* -docs/*.spec +docs/*.html +docs/relnotes/* +docs/specs/*.spec +docs/specs/OLD/*.spec diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/include/GL/internal/dri_interface.h mesa-10.6.3+git20150809+10.6.736f6e16/include/GL/internal/dri_interface.h --- mesa-10.6.3~git20150727+10.6.ccef8901/include/GL/internal/dri_interface.h 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/include/GL/internal/dri_interface.h 2015-08-09 06:15:27.000000000 +0000 @@ -1180,7 +1180,8 @@ }; /** - * \name Reasons that __DRIimageExtensionRec::createImageFromTexture might fail + * \name Reasons that __DRIimageExtensionRec::createImageFromTexture or + * __DRIimageExtensionRec::createImageFromDmaBufs might fail */ /*@{*/ /** Success! */ @@ -1189,11 +1190,14 @@ /** Memory allocation failure */ #define __DRI_IMAGE_ERROR_BAD_ALLOC 1 -/** Client requested an invalid attribute for a texture object */ +/** Client requested an invalid attribute */ #define __DRI_IMAGE_ERROR_BAD_MATCH 2 /** Client requested an invalid texture object */ #define __DRI_IMAGE_ERROR_BAD_PARAMETER 3 + +/** Client requested an invalid pitch and/or offset */ +#define __DRI_IMAGE_ERROR_BAD_ACCESS 4 /*@}*/ /** diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/.lastcommit mesa-10.6.3+git20150809+10.6.736f6e16/.lastcommit --- mesa-10.6.3~git20150727+10.6.ccef8901/.lastcommit 2015-07-27 05:57:14.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/.lastcommit 2015-08-09 06:15:27.000000000 +0000 @@ -1 +1 @@ -commit ccef8901de421eae5dcc8affa14218d46cc06593 +commit 736f6e16d9989f01cc55dcba15ba978ba90b7748 diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/egl/drivers/dri2/egl_dri2.c mesa-10.6.3+git20150809+10.6.736f6e16/src/egl/drivers/dri2/egl_dri2.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/egl/drivers/dri2/egl_dri2.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/egl/drivers/dri2/egl_dri2.c 2015-08-09 06:15:27.000000000 +0000 @@ -1510,6 +1510,10 @@ egl_error = EGL_BAD_PARAMETER; break; + case __DRI_IMAGE_ERROR_BAD_ACCESS: + egl_error = EGL_BAD_ACCESS; + break; + default: assert(0); egl_error = EGL_BAD_MATCH; @@ -2123,13 +2127,11 @@ wl_drm_callbacks.authenticate = (int(*)(void *, uint32_t)) dri2_dpy->vtbl->authenticate; -#ifdef HAVE_LIBDRM if (drmGetCap(dri2_dpy->fd, DRM_CAP_PRIME, &cap) == 0 && cap == (DRM_PRIME_CAP_IMPORT | DRM_PRIME_CAP_EXPORT) && dri2_dpy->image->base.version >= 7 && dri2_dpy->image->createImageFromFds != NULL) flags |= WAYLAND_DRM_PRIME; -#endif dri2_dpy->wl_server_drm = wayland_drm_init(wl_dpy, dri2_dpy->device_name, diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/egl/main/eglsurface.c mesa-10.6.3+git20150809+10.6.736f6e16/src/egl/main/eglsurface.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/egl/main/eglsurface.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/egl/main/eglsurface.c 2015-08-09 06:15:27.000000000 +0000 @@ -309,7 +309,8 @@ *value = surface->Config->ConfigID; break; case EGL_LARGEST_PBUFFER: - *value = surface->LargestPbuffer; + if (surface->Type == EGL_PBUFFER_BIT) + *value = surface->LargestPbuffer; break; case EGL_TEXTURE_FORMAT: /* texture attributes: only for pbuffers, no error otherwise */ diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/nouveau/nv50/nv50_vbo.c mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/nouveau/nv50/nv50_vbo.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/nouveau/nv50/nv50_vbo.c 2015-07-16 07:06:16.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/nouveau/nv50/nv50_vbo.c 2015-08-09 06:15:27.000000000 +0000 @@ -382,6 +382,11 @@ if (nv50->vbo_user & (1 << b)) { address = addrs[b] + ve->pipe.src_offset; limit = addrs[b] + limits[b]; + } else + if (!vb->buffer) { + BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); + PUSH_DATA (push, 0); + continue; } else { struct nv04_resource *buf = nv04_resource(vb->buffer); if (!(refd & (1 << b))) { diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c 2015-07-27 05:57:14.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c 2015-08-09 06:15:27.000000000 +0000 @@ -339,7 +339,7 @@ nvc0_vertprog_validate(nvc0); else if (likely(vp == nvc0->gmtyprog)) - nvc0_vertprog_validate(nvc0); + nvc0_gmtyprog_validate(nvc0); else nvc0_tevlprog_validate(nvc0); } diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/r600/evergreen_state.c mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/r600/evergreen_state.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/r600/evergreen_state.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/r600/evergreen_state.c 2015-08-09 06:15:27.000000000 +0000 @@ -1732,10 +1732,10 @@ r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */ - /* Always enable the first colorbuffer in CB_SHADER_MASK. This - * will assure that the alpha-test will work even if there is - * no colorbuffer bound. */ - radeon_emit(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */ + /* This must match the used export instructions exactly. + * Other values may lead to undefined behavior and hangs. + */ + radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */ } static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom) diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/r600/r600_shader.c mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/r600/r600_shader.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/r600/r600_shader.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/r600/r600_shader.c 2015-08-09 06:15:27.000000000 +0000 @@ -2482,6 +2482,7 @@ output[j].array_base = 0; output[j].op = CF_OP_EXPORT; j++; + shader->nr_ps_color_exports++; } noutput = j; diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_descriptors.c mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_descriptors.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_descriptors.c 2015-02-25 15:01:21.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_descriptors.c 2015-08-09 06:15:27.000000000 +0000 @@ -24,14 +24,23 @@ * Marek Olšák */ -/* Resource binding slots and sampler states (each described with 8 or 4 dwords) - * live in memory on SI. +/* Resource binding slots and sampler states (each described with 8 or + * 4 dwords) are stored in lists in memory which is accessed by shaders + * using scalar load instructions. * - * This file is responsible for managing lists of resources and sampler states - * in memory and binding them, which means updating those structures in memory. + * This file is responsible for managing such lists. It keeps a copy of all + * descriptors in CPU memory and re-uploads a whole list if some slots have + * been changed. * - * There is also code for updating shader pointers to resources and sampler - * states. CP DMA functions are here too. + * This code is also reponsible for updating shader pointers to those lists. + * + * Note that CP DMA can't be used for updating the lists, because a GPU hang + * could leave the list in a mid-IB state and the next IB would get wrong + * descriptors and the whole context would be unusable at that point. + * (Note: The register shadowing can't be used due to the same reason) + * + * Also, uploading descriptors to newly allocated memory doesn't require + * a KCACHE flush. */ #include "radeon/r600_cs.h" @@ -42,7 +51,6 @@ #include "util/u_memory.h" #include "util/u_upload_mgr.h" -#define SI_NUM_CONTEXTS 16 /* NULL image and buffer descriptor. * @@ -139,209 +147,62 @@ } } -static void si_init_descriptors(struct si_context *sctx, - struct si_descriptors *desc, - unsigned shader_userdata_reg, +static void si_init_descriptors(struct si_descriptors *desc, + unsigned shader_userdata_index, unsigned element_dw_size, - unsigned num_elements, - void (*emit_func)(struct si_context *ctx, struct r600_atom *state)) + unsigned num_elements) { + int i; + assert(num_elements <= sizeof(desc->enabled_mask)*8); - assert(num_elements <= sizeof(desc->dirty_mask)*8); - desc->atom.emit = (void*)emit_func; - desc->shader_userdata_reg = shader_userdata_reg; + desc->list = CALLOC(num_elements, element_dw_size * 4); desc->element_dw_size = element_dw_size; desc->num_elements = num_elements; - desc->context_size = num_elements * element_dw_size * 4; - - desc->buffer = (struct r600_resource*) - pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM, - PIPE_USAGE_DEFAULT, - SI_NUM_CONTEXTS * desc->context_size); + desc->list_dirty = true; /* upload the list before the next draw */ + desc->shader_userdata_offset = shader_userdata_index * 4; - r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer, - RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA); - - /* We don't check for CS space here, because this should be called - * only once at context initialization. */ - si_emit_cp_dma_clear_buffer(sctx, desc->buffer->gpu_address, - desc->buffer->b.b.width0, 0, - R600_CP_DMA_SYNC | CIK_CP_DMA_USE_L2); + /* Initialize the array to NULL descriptors if the element size is 8. */ + if (element_dw_size == 8) + for (i = 0; i < num_elements; i++) + memcpy(desc->list + i*element_dw_size, null_descriptor, + sizeof(null_descriptor)); } static void si_release_descriptors(struct si_descriptors *desc) { pipe_resource_reference((struct pipe_resource**)&desc->buffer, NULL); + FREE(desc->list); } -static void si_update_descriptors(struct si_context *sctx, +static bool si_upload_descriptors(struct si_context *sctx, struct si_descriptors *desc) { - if (desc->dirty_mask) { - desc->atom.num_dw = - 7 + /* copy */ - (4 + desc->element_dw_size) * util_bitcount64(desc->dirty_mask) + /* update */ - 4; /* pointer update */ - - if (desc->shader_userdata_reg >= R_00B130_SPI_SHADER_USER_DATA_VS_0 && - desc->shader_userdata_reg < R_00B230_SPI_SHADER_USER_DATA_GS_0) - desc->atom.num_dw += 4; /* second pointer update */ - - desc->atom.dirty = true; - - /* TODO: Investigate if these flushes can be removed after - * adding CE support. */ - - /* The descriptors are read with the K cache. */ - sctx->b.flags |= SI_CONTEXT_INV_KCACHE; - - /* Since SI uses uncached CP DMA to update descriptors, - * we have to flush TC L2, which is used to fetch constants - * along with KCACHE. */ - if (sctx->b.chip_class == SI) - sctx->b.flags |= SI_CONTEXT_INV_TC_L2; - } else { - desc->atom.dirty = false; - } -} + unsigned list_size = desc->num_elements * desc->element_dw_size * 4; + void *ptr; -static void si_emit_shader_pointer(struct si_context *sctx, - struct r600_atom *atom) -{ - struct si_descriptors *desc = (struct si_descriptors*)atom; - struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; - uint64_t va = desc->buffer->gpu_address + - desc->current_context_id * desc->context_size + - desc->buffer_offset; + if (!desc->list_dirty) + return true; - radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0)); - radeon_emit(cs, (desc->shader_userdata_reg - SI_SH_REG_OFFSET) >> 2); - radeon_emit(cs, va); - radeon_emit(cs, va >> 32); + u_upload_alloc(sctx->b.uploader, 0, list_size, + &desc->buffer_offset, + (struct pipe_resource**)&desc->buffer, &ptr); + if (!desc->buffer) + return false; /* skip the draw call */ - if (desc->shader_userdata_reg >= R_00B130_SPI_SHADER_USER_DATA_VS_0 && - desc->shader_userdata_reg < R_00B230_SPI_SHADER_USER_DATA_GS_0) { - radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0)); - radeon_emit(cs, (desc->shader_userdata_reg + - (R_00B330_SPI_SHADER_USER_DATA_ES_0 - - R_00B130_SPI_SHADER_USER_DATA_VS_0) - - SI_SH_REG_OFFSET) >> 2); - radeon_emit(cs, va); - radeon_emit(cs, va >> 32); - } -} - -static void si_emit_descriptors(struct si_context *sctx, - struct si_descriptors *desc, - uint32_t **descriptors) -{ - struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; - uint64_t va_base; - int packet_start = 0; - int packet_size = 0; - int last_index = desc->num_elements; /* point to a non-existing element */ - uint64_t dirty_mask = desc->dirty_mask; - unsigned new_context_id = (desc->current_context_id + 1) % SI_NUM_CONTEXTS; - - assert(dirty_mask); - - va_base = desc->buffer->gpu_address; - - /* Copy the descriptors to a new context slot. */ - si_emit_cp_dma_copy_buffer(sctx, - va_base + new_context_id * desc->context_size, - va_base + desc->current_context_id * desc->context_size, - desc->context_size, R600_CP_DMA_SYNC | CIK_CP_DMA_USE_L2); - - va_base += new_context_id * desc->context_size; - - /* Update the descriptors. - * Updates of consecutive descriptors are merged to one WRITE_DATA packet. - * - * XXX When unbinding lots of resources, consider clearing the memory - * with CP DMA instead of emitting zeros. - */ - while (dirty_mask) { - int i = u_bit_scan64(&dirty_mask); - - assert(i < desc->num_elements); - - if (last_index+1 == i && packet_size) { - /* Append new data at the end of the last packet. */ - packet_size += desc->element_dw_size; - cs->buf[packet_start] = PKT3(PKT3_WRITE_DATA, packet_size, 0); - } else { - /* Start a new packet. */ - uint64_t va = va_base + i * desc->element_dw_size * 4; - - packet_start = cs->cdw; - packet_size = 2 + desc->element_dw_size; + util_memcpy_cpu_to_le32(ptr, desc->list, list_size); - radeon_emit(cs, PKT3(PKT3_WRITE_DATA, packet_size, 0)); - radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(sctx->b.chip_class == SI ? - PKT3_WRITE_DATA_DST_SEL_MEM_SYNC : - PKT3_WRITE_DATA_DST_SEL_TC_L2) | - PKT3_WRITE_DATA_WR_CONFIRM | - PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME)); - radeon_emit(cs, va & 0xFFFFFFFFUL); - radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL); - } - - radeon_emit_array(cs, descriptors[i], desc->element_dw_size); - - last_index = i; - } - - desc->dirty_mask = 0; - desc->current_context_id = new_context_id; - - /* Now update the shader userdata pointer. */ - si_emit_shader_pointer(sctx, &desc->atom); -} + r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer, + RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); -static unsigned si_get_shader_user_data_base(unsigned shader) -{ - switch (shader) { - case PIPE_SHADER_VERTEX: - return R_00B130_SPI_SHADER_USER_DATA_VS_0; - case PIPE_SHADER_GEOMETRY: - return R_00B230_SPI_SHADER_USER_DATA_GS_0; - case PIPE_SHADER_FRAGMENT: - return R_00B030_SPI_SHADER_USER_DATA_PS_0; - default: - assert(0); - return 0; - } + desc->list_dirty = false; + desc->pointer_dirty = true; + sctx->shader_userdata.atom.dirty = true; + return true; } /* SAMPLER VIEWS */ -static void si_emit_sampler_views(struct si_context *sctx, struct r600_atom *atom) -{ - struct si_sampler_views *views = (struct si_sampler_views*)atom; - - si_emit_descriptors(sctx, &views->desc, views->desc_data); -} - -static void si_init_sampler_views(struct si_context *sctx, - struct si_sampler_views *views, - unsigned shader) -{ - int i; - - si_init_descriptors(sctx, &views->desc, - si_get_shader_user_data_base(shader) + - SI_SGPR_RESOURCE * 4, - 8, SI_NUM_SAMPLER_VIEWS, si_emit_sampler_views); - - for (i = 0; i < views->desc.num_elements; i++) { - views->desc_data[i] = null_descriptor; - views->desc.dirty_mask |= 1llu << i; - } - si_update_descriptors(sctx, &views->desc); -} - static void si_release_sampler_views(struct si_sampler_views *views) { int i; @@ -382,10 +243,10 @@ si_get_resource_ro_priority(rview->resource)); } + if (!views->desc.buffer) + return; r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, views->desc.buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA); - - si_emit_shader_pointer(sctx, &views->desc.atom); } static void si_set_sampler_view(struct si_context *sctx, unsigned shader, @@ -406,17 +267,16 @@ rview->resource, RADEON_USAGE_READ, si_get_resource_ro_priority(rview->resource)); - pipe_sampler_view_reference(&views->views[slot], view); - views->desc_data[slot] = view_desc; + memcpy(views->desc.list + slot*8, view_desc, 8*4); views->desc.enabled_mask |= 1llu << slot; } else { pipe_sampler_view_reference(&views->views[slot], NULL); - views->desc_data[slot] = null_descriptor; + memcpy(views->desc.list + slot*8, null_descriptor, 8*4); views->desc.enabled_mask &= ~(1llu << slot); } - views->desc.dirty_mask |= 1llu << slot; + views->desc.list_dirty = true; } static void si_set_sampler_views(struct pipe_context *ctx, @@ -475,25 +335,17 @@ NULL, NULL); } } - - si_update_descriptors(sctx, &samplers->views.desc); } /* SAMPLER STATES */ -static void si_emit_sampler_states(struct si_context *sctx, struct r600_atom *atom) -{ - struct si_sampler_states *states = (struct si_sampler_states*)atom; - - si_emit_descriptors(sctx, &states->desc, states->desc_data); -} - static void si_sampler_states_begin_new_cs(struct si_context *sctx, struct si_sampler_states *states) { + if (!states->desc.buffer) + return; r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, states->desc.buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA); - si_emit_shader_pointer(sctx, &states->desc.atom); } void si_set_sampler_descriptors(struct si_context *sctx, unsigned shader, @@ -513,66 +365,39 @@ for (i = 0; i < count; i++) { unsigned slot = start + i; - if (!sstates[i]) { - samplers->desc.dirty_mask &= ~(1llu << slot); + if (!sstates[i]) continue; - } - samplers->desc_data[slot] = sstates[i]->val; - samplers->desc.dirty_mask |= 1llu << slot; + memcpy(samplers->desc.list + slot*4, sstates[i]->val, 4*4); + samplers->desc.list_dirty = true; } - - si_update_descriptors(sctx, &samplers->desc); } /* BUFFER RESOURCES */ -static void si_emit_buffer_resources(struct si_context *sctx, struct r600_atom *atom) -{ - struct si_buffer_resources *buffers = (struct si_buffer_resources*)atom; - - si_emit_descriptors(sctx, &buffers->desc, buffers->desc_data); -} - -static void si_init_buffer_resources(struct si_context *sctx, - struct si_buffer_resources *buffers, - unsigned num_buffers, unsigned shader, +static void si_init_buffer_resources(struct si_buffer_resources *buffers, + unsigned num_buffers, unsigned shader_userdata_index, enum radeon_bo_usage shader_usage, enum radeon_bo_priority priority) { - int i; - - buffers->num_buffers = num_buffers; buffers->shader_usage = shader_usage; buffers->priority = priority; buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*)); - buffers->desc_storage = CALLOC(num_buffers, sizeof(uint32_t) * 4); - - /* si_emit_descriptors only accepts an array of arrays. - * This adds such an array. */ - buffers->desc_data = CALLOC(num_buffers, sizeof(uint32_t*)); - for (i = 0; i < num_buffers; i++) { - buffers->desc_data[i] = &buffers->desc_storage[i*4]; - } - si_init_descriptors(sctx, &buffers->desc, - si_get_shader_user_data_base(shader) + - shader_userdata_index*4, 4, num_buffers, - si_emit_buffer_resources); + si_init_descriptors(&buffers->desc, shader_userdata_index, 4, + num_buffers); } static void si_release_buffer_resources(struct si_buffer_resources *buffers) { int i; - for (i = 0; i < buffers->num_buffers; i++) { + for (i = 0; i < buffers->desc.num_elements; i++) { pipe_resource_reference(&buffers->buffers[i], NULL); } FREE(buffers->buffers); - FREE(buffers->desc_storage); - FREE(buffers->desc_data); si_release_descriptors(&buffers->desc); } @@ -590,11 +415,11 @@ buffers->shader_usage, buffers->priority); } + if (!buffers->desc.buffer) + return; r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, buffers->desc.buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA); - - si_emit_shader_pointer(sctx, &buffers->desc.atom); } /* VERTEX BUFFERS */ @@ -617,14 +442,15 @@ (struct r600_resource*)sctx->vertex_buffer[vb].buffer, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO); } + + if (!desc->buffer) + return; r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); - - si_emit_shader_pointer(sctx, &desc->atom); } -void si_update_vertex_buffers(struct si_context *sctx) +static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx) { struct si_descriptors *desc = &sctx->vertex_buffers; bool bound[SI_NUM_VERTEX_BUFFERS] = {}; @@ -632,8 +458,10 @@ uint64_t va; uint32_t *ptr; + if (!sctx->vertex_buffers_dirty) + return true; if (!count || !sctx->vertex_elements) - return; + return true; /* Vertex buffer descriptors are the only ones which are uploaded * directly through a staging buffer and don't go through @@ -641,13 +469,14 @@ */ u_upload_alloc(sctx->b.uploader, 0, count * 16, &desc->buffer_offset, (struct pipe_resource**)&desc->buffer, (void**)&ptr); + if (!desc->buffer) + return false; r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); assert(count <= SI_NUM_VERTEX_BUFFERS); - assert(desc->current_context_id == 0); for (i = 0; i < count; i++) { struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i]; @@ -693,13 +522,14 @@ } } - desc->atom.num_dw = 8; /* update 2 shader pointers (VS+ES) */ - desc->atom.dirty = true; - /* Don't flush the const cache. It would have a very negative effect * on performance (confirmed by testing). New descriptors are always * uploaded to a fresh new buffer, so I don't think flushing the const * cache is needed. */ + desc->pointer_dirty = true; + sctx->shader_userdata.atom.dirty = true; + sctx->vertex_buffers_dirty = false; + return true; } @@ -724,7 +554,7 @@ if (shader >= SI_NUM_SHADERS) return; - assert(slot < buffers->num_buffers); + assert(slot < buffers->desc.num_elements); pipe_resource_reference(&buffers->buffers[slot], NULL); /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy @@ -751,7 +581,7 @@ } /* Set the descriptor. */ - uint32_t *desc = buffers->desc_data[slot]; + uint32_t *desc = buffers->desc.list + slot*4; desc[0] = va; desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(0); @@ -770,12 +600,11 @@ buffers->desc.enabled_mask |= 1llu << slot; } else { /* Clear the descriptor. */ - memset(buffers->desc_data[slot], 0, sizeof(uint32_t) * 4); + memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4); buffers->desc.enabled_mask &= ~(1llu << slot); } - buffers->desc.dirty_mask |= 1llu << slot; - si_update_descriptors(sctx, &buffers->desc); + buffers->desc.list_dirty = true; } /* RING BUFFERS */ @@ -795,7 +624,7 @@ /* The stride field in the resource descriptor has 14 bits */ assert(stride < (1 << 14)); - assert(slot < buffers->num_buffers); + assert(slot < buffers->desc.num_elements); pipe_resource_reference(&buffers->buffers[slot], NULL); if (buffer) { @@ -840,7 +669,7 @@ } /* Set the descriptor. */ - uint32_t *desc = buffers->desc_data[slot]; + uint32_t *desc = buffers->desc.list + slot*4; desc[0] = va; desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride) | @@ -863,12 +692,11 @@ buffers->desc.enabled_mask |= 1llu << slot; } else { /* Clear the descriptor. */ - memset(buffers->desc_data[slot], 0, sizeof(uint32_t) * 4); + memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4); buffers->desc.enabled_mask &= ~(1llu << slot); } - buffers->desc.dirty_mask |= 1llu << slot; - si_update_descriptors(sctx, &buffers->desc); + buffers->desc.list_dirty = true; } /* STREAMOUT BUFFERS */ @@ -930,7 +758,7 @@ uint64_t va = r600_resource(buffer)->gpu_address; /* Set the descriptor. */ - uint32_t *desc = buffers->desc_data[bufidx]; + uint32_t *desc = buffers->desc.list + bufidx*4; desc[0] = va; desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32); desc[2] = 0xffffffff; @@ -948,24 +776,22 @@ buffers->desc.enabled_mask |= 1llu << bufidx; } else { /* Clear the descriptor and unset the resource. */ - memset(buffers->desc_data[bufidx], 0, + memset(buffers->desc.list + bufidx*4, 0, sizeof(uint32_t) * 4); pipe_resource_reference(&buffers->buffers[bufidx], NULL); buffers->desc.enabled_mask &= ~(1llu << bufidx); } - buffers->desc.dirty_mask |= 1llu << bufidx; } for (; i < old_num_targets; i++) { bufidx = SI_SO_BUF_OFFSET + i; /* Clear the descriptor and unset the resource. */ - memset(buffers->desc_data[bufidx], 0, sizeof(uint32_t) * 4); + memset(buffers->desc.list + bufidx*4, 0, sizeof(uint32_t) * 4); pipe_resource_reference(&buffers->buffers[bufidx], NULL); buffers->desc.enabled_mask &= ~(1llu << bufidx); - buffers->desc.dirty_mask |= 1llu << bufidx; } - si_update_descriptors(sctx, &buffers->desc); + buffers->desc.list_dirty = true; } static void si_desc_reset_buffer_offset(struct pipe_context *ctx, @@ -1034,22 +860,19 @@ /* Read/Write buffers. */ for (shader = 0; shader < SI_NUM_SHADERS; shader++) { struct si_buffer_resources *buffers = &sctx->rw_buffers[shader]; - bool found = false; uint64_t mask = buffers->desc.enabled_mask; while (mask) { i = u_bit_scan64(&mask); if (buffers->buffers[i] == buf) { - si_desc_reset_buffer_offset(ctx, buffers->desc_data[i], + si_desc_reset_buffer_offset(ctx, buffers->desc.list + i*4, old_va, buf); + buffers->desc.list_dirty = true; r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, rbuffer, buffers->shader_usage, buffers->priority); - buffers->desc.dirty_mask |= 1llu << i; - found = true; - if (i >= SI_SO_BUF_OFFSET && shader == PIPE_SHADER_VERTEX) { /* Update the streamout state. */ if (sctx->b.streamout.begin_emitted) { @@ -1061,34 +884,25 @@ } } } - if (found) { - si_update_descriptors(sctx, &buffers->desc); - } } /* Constant buffers. */ for (shader = 0; shader < SI_NUM_SHADERS; shader++) { struct si_buffer_resources *buffers = &sctx->const_buffers[shader]; - bool found = false; uint64_t mask = buffers->desc.enabled_mask; while (mask) { unsigned i = u_bit_scan64(&mask); if (buffers->buffers[i] == buf) { - si_desc_reset_buffer_offset(ctx, buffers->desc_data[i], + si_desc_reset_buffer_offset(ctx, buffers->desc.list + i*4, old_va, buf); + buffers->desc.list_dirty = true; r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, rbuffer, buffers->shader_usage, buffers->priority); - - buffers->desc.dirty_mask |= 1llu << i; - found = true; } } - if (found) { - si_update_descriptors(sctx, &buffers->desc); - } } /* Texture buffers - update virtual addresses in sampler view descriptors. */ @@ -1100,23 +914,20 @@ /* Texture buffers - update bindings. */ for (shader = 0; shader < SI_NUM_SHADERS; shader++) { struct si_sampler_views *views = &sctx->samplers[shader].views; - bool found = false; uint64_t mask = views->desc.enabled_mask; while (mask) { unsigned i = u_bit_scan64(&mask); if (views->views[i]->texture == buf) { + si_desc_reset_buffer_offset(ctx, views->desc.list + i*8+4, + old_va, buf); + views->desc.list_dirty = true; + r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO); - - views->desc.dirty_mask |= 1llu << i; - found = true; } } - if (found) { - si_update_descriptors(sctx, &views->desc); - } } } @@ -1277,39 +1088,133 @@ r600_resource(dst)->TC_L2_dirty = true; } -/* INIT/DEINIT */ +/* SHADER USER DATA */ + +static void si_mark_shader_pointers_dirty(struct si_context *sctx, + unsigned shader) +{ + sctx->const_buffers[shader].desc.pointer_dirty = true; + sctx->rw_buffers[shader].desc.pointer_dirty = true; + sctx->samplers[shader].views.desc.pointer_dirty = true; + sctx->samplers[shader].states.desc.pointer_dirty = true; + + if (shader == PIPE_SHADER_VERTEX) + sctx->vertex_buffers.pointer_dirty = true; + + sctx->shader_userdata.atom.dirty = true; +} + +static void si_shader_userdata_begin_new_cs(struct si_context *sctx) +{ + int i; + + for (i = 0; i < SI_NUM_SHADERS; i++) { + si_mark_shader_pointers_dirty(sctx, i); + } +} + +/* Set a base register address for user data constants in the given shader. + * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*. + */ +static void si_set_user_data_base(struct si_context *sctx, + unsigned shader, uint32_t new_base) +{ + uint32_t *base = &sctx->shader_userdata.sh_base[shader]; + + if (*base != new_base) { + *base = new_base; + + if (new_base) + si_mark_shader_pointers_dirty(sctx, shader); + } +} + +/* This must be called when these shaders are changed from non-NULL to NULL + * and vice versa: + * - geometry shader + * - tessellation control shader + * - tessellation evaluation shader + */ +void si_shader_change_notify(struct si_context *sctx) +{ + /* VS can be bound as VS or ES. */ + if (sctx->gs_shader) + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, + R_00B330_SPI_SHADER_USER_DATA_ES_0); + else + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, + R_00B130_SPI_SHADER_USER_DATA_VS_0); +} + +static void si_emit_shader_pointer(struct si_context *sctx, + struct si_descriptors *desc, + unsigned sh_base, bool keep_dirty) +{ + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; + uint64_t va; + + if (!desc->pointer_dirty || !desc->buffer) + return; + + va = desc->buffer->gpu_address + + desc->buffer_offset; + + radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0)); + radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2); + radeon_emit(cs, va); + radeon_emit(cs, va >> 32); + + desc->pointer_dirty = keep_dirty; +} + +static void si_emit_shader_userdata(struct si_context *sctx, + struct r600_atom *atom) +{ + unsigned i; + uint32_t *sh_base = sctx->shader_userdata.sh_base; + + /* The VS copy shader needs these for clipping, streamout, and rings. */ + if (sctx->gs_shader) { + unsigned base = R_00B130_SPI_SHADER_USER_DATA_VS_0; + unsigned i = PIPE_SHADER_VERTEX; + + si_emit_shader_pointer(sctx, &sctx->const_buffers[i].desc, base, true); + si_emit_shader_pointer(sctx, &sctx->rw_buffers[i].desc, base, true); + } + + for (i = 0; i < SI_NUM_SHADERS; i++) { + unsigned base = sh_base[i]; + + si_emit_shader_pointer(sctx, &sctx->const_buffers[i].desc, base, false); + si_emit_shader_pointer(sctx, &sctx->rw_buffers[i].desc, base, false); + si_emit_shader_pointer(sctx, &sctx->samplers[i].views.desc, base, false); + si_emit_shader_pointer(sctx, &sctx->samplers[i].states.desc, base, false); + } + si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false); +} + +/* INIT/DEINIT/UPLOAD */ void si_init_all_descriptors(struct si_context *sctx) { int i; for (i = 0; i < SI_NUM_SHADERS; i++) { - si_init_buffer_resources(sctx, &sctx->const_buffers[i], - SI_NUM_CONST_BUFFERS, i, SI_SGPR_CONST, + si_init_buffer_resources(&sctx->const_buffers[i], + SI_NUM_CONST_BUFFERS, SI_SGPR_CONST, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO); - si_init_buffer_resources(sctx, &sctx->rw_buffers[i], - i == PIPE_SHADER_VERTEX ? - SI_NUM_RW_BUFFERS : SI_NUM_RING_BUFFERS, - i, SI_SGPR_RW_BUFFERS, + si_init_buffer_resources(&sctx->rw_buffers[i], + SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS, RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW); - si_init_sampler_views(sctx, &sctx->samplers[i].views, i); + si_init_descriptors(&sctx->samplers[i].views.desc, + SI_SGPR_RESOURCE, 8, SI_NUM_SAMPLER_VIEWS); + si_init_descriptors(&sctx->samplers[i].states.desc, + SI_SGPR_SAMPLER, 4, SI_NUM_SAMPLER_STATES); + } - si_init_descriptors(sctx, &sctx->samplers[i].states.desc, - si_get_shader_user_data_base(i) + SI_SGPR_SAMPLER * 4, - 4, SI_NUM_SAMPLER_STATES, si_emit_sampler_states); - - sctx->atoms.s.const_buffers[i] = &sctx->const_buffers[i].desc.atom; - sctx->atoms.s.rw_buffers[i] = &sctx->rw_buffers[i].desc.atom; - sctx->atoms.s.sampler_views[i] = &sctx->samplers[i].views.desc.atom; - sctx->atoms.s.sampler_states[i] = &sctx->samplers[i].states.desc.atom; - } - - si_init_descriptors(sctx, &sctx->vertex_buffers, - si_get_shader_user_data_base(PIPE_SHADER_VERTEX) + - SI_SGPR_VERTEX_BUFFER*4, 4, SI_NUM_VERTEX_BUFFERS, - si_emit_shader_pointer); - sctx->atoms.s.vertex_buffers = &sctx->vertex_buffers.atom; + si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFER, + 4, SI_NUM_VERTEX_BUFFERS); /* Set pipe_context functions. */ sctx->b.b.set_constant_buffer = si_set_constant_buffer; @@ -1317,6 +1222,32 @@ sctx->b.b.set_stream_output_targets = si_set_streamout_targets; sctx->b.clear_buffer = si_clear_buffer; sctx->b.invalidate_buffer = si_invalidate_buffer; + + /* Shader user data. */ + sctx->atoms.s.shader_userdata = &sctx->shader_userdata.atom; + sctx->shader_userdata.atom.emit = (void*)si_emit_shader_userdata; + + /* Upper bound, 4 pointers per shader, +1 for vertex buffers, +2 for the VS copy shader. */ + sctx->shader_userdata.atom.num_dw = (SI_NUM_SHADERS * 4 + 1 + 2) * 4; + + /* Set default and immutable mappings. */ + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0); + si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0); + si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0); +} + +bool si_upload_shader_descriptors(struct si_context *sctx) +{ + int i; + + for (i = 0; i < SI_NUM_SHADERS; i++) { + if (!si_upload_descriptors(sctx, &sctx->const_buffers[i].desc) || + !si_upload_descriptors(sctx, &sctx->rw_buffers[i].desc) || + !si_upload_descriptors(sctx, &sctx->samplers[i].views.desc) || + !si_upload_descriptors(sctx, &sctx->samplers[i].states.desc)) + return false; + } + return si_upload_vertex_buffer_descriptors(sctx); } void si_release_all_descriptors(struct si_context *sctx) @@ -1343,4 +1274,5 @@ si_sampler_states_begin_new_cs(sctx, &sctx->samplers[i].states); } si_vertex_buffers_begin_new_cs(sctx); + si_shader_userdata_begin_new_cs(sctx); } diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_pipe.h mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_pipe.h --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_pipe.h 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_pipe.h 2015-08-09 06:15:27.000000000 +0000 @@ -125,8 +125,6 @@ #define SI_NUM_ATOMS(sctx) (sizeof((sctx)->atoms)/sizeof((sctx)->atoms.array[0])) -#define SI_NUM_SHADERS (PIPE_SHADER_GEOMETRY+1) - struct si_context { struct r600_common_context b; struct blitter_context *blitter; @@ -141,13 +139,6 @@ union { struct { /* The order matters. */ - struct r600_atom *vertex_buffers; - struct r600_atom *const_buffers[SI_NUM_SHADERS]; - struct r600_atom *rw_buffers[SI_NUM_SHADERS]; - struct r600_atom *sampler_views[SI_NUM_SHADERS]; - struct r600_atom *sampler_states[SI_NUM_SHADERS]; - /* Caches must be flushed after resource descriptors are - * updated in memory. */ struct r600_atom *cache_flush; struct r600_atom *streamout_begin; struct r600_atom *streamout_enable; /* must be after streamout_begin */ @@ -156,6 +147,7 @@ struct r600_atom *db_render_state; struct r600_atom *msaa_config; struct r600_atom *clip_regs; + struct r600_atom *shader_userdata; } s; struct r600_atom *array[0]; } atoms; @@ -169,6 +161,7 @@ struct si_shader_selector *gs_shader; struct si_shader_selector *vs_shader; struct si_cs_shader_state cs_shader_state; + struct si_shader_data shader_userdata; /* shader information */ unsigned sprite_coord_enable; bool flatshade; diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_shader.c mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_shader.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_shader.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_shader.c 2015-08-09 06:15:27.000000000 +0000 @@ -2647,18 +2647,43 @@ } } +int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader) +{ + const struct radeon_shader_binary *binary = &shader->binary; + unsigned code_size = binary->code_size + binary->rodata_size; + unsigned char *ptr; + + r600_resource_reference(&shader->bo, NULL); + shader->bo = si_resource_create_custom(&sscreen->b.b, + PIPE_USAGE_IMMUTABLE, + code_size); + if (!shader->bo) + return -ENOMEM; + + ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, + PIPE_TRANSFER_READ_WRITE); + util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size); + if (binary->rodata_size > 0) { + ptr += binary->code_size; + util_memcpy_cpu_to_le32(ptr, binary->rodata, + binary->rodata_size); + } + + sscreen->b.ws->buffer_unmap(shader->bo->cs_buf); + return 0; +} + int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader, const struct radeon_shader_binary *binary) { unsigned i; - unsigned code_size; - unsigned char *ptr; bool dump = r600_can_dump_shader(&sscreen->b, shader->selector ? shader->selector->tokens : NULL); si_shader_binary_read_config(sscreen, shader, 0); + si_shader_binary_upload(sscreen, shader); if (dump) { if (!binary->disassembled) { @@ -2676,26 +2701,6 @@ shader->num_sgprs, shader->num_vgprs, binary->code_size, shader->lds_size, shader->scratch_bytes_per_wave); } - - /* copy new shader */ - code_size = binary->code_size + binary->rodata_size; - r600_resource_reference(&shader->bo, NULL); - shader->bo = si_resource_create_custom(&sscreen->b.b, PIPE_USAGE_IMMUTABLE, - code_size); - if (shader->bo == NULL) { - return -ENOMEM; - } - - - ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_READ_WRITE); - util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size); - if (binary->rodata_size > 0) { - ptr += binary->code_size; - util_memcpy_cpu_to_le32(ptr, binary->rodata, binary->rodata_size); - } - - sscreen->b.ws->buffer_unmap(shader->bo->cs_buf); - return 0; } diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_shader.h mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_shader.h --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_shader.h 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_shader.h 2015-08-09 06:15:27.000000000 +0000 @@ -189,6 +189,7 @@ LLVMTargetMachineRef tm, LLVMModuleRef mod); void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader); unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index); +int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader); int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader, const struct radeon_shader_binary *binary); void si_shader_apply_scratch_relocs(struct si_context *sctx, diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_state_draw.c mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_state_draw.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_state_draw.c 2015-07-27 05:57:14.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_state_draw.c 2015-08-09 06:15:27.000000000 +0000 @@ -249,8 +249,7 @@ const struct pipe_index_buffer *ib) { struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; - unsigned sh_base_reg = (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : - R_00B130_SPI_SHADER_USER_DATA_VS_0); + unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX]; if (info->count_from_stream_output) { struct r600_so_target *t = @@ -540,11 +539,8 @@ sctx->current_rast_prim = info->mode; si_update_shaders(sctx); - - if (sctx->vertex_buffers_dirty) { - si_update_vertex_buffers(sctx); - sctx->vertex_buffers_dirty = false; - } + if (!si_upload_shader_descriptors(sctx)) + return; if (info->indexed) { /* Initialize the index buffer struct. */ diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_state.h mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_state.h --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_state.h 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_state.h 2015-08-09 06:15:27.000000000 +0000 @@ -30,6 +30,8 @@ #include "si_pm4.h" #include "radeon/r600_pipe_common.h" +#define SI_NUM_SHADERS (PIPE_SHADER_GEOMETRY+1) + struct si_screen; struct si_shader; @@ -111,6 +113,11 @@ struct si_pm4_state *array[0]; }; +struct si_shader_data { + struct r600_atom atom; + uint32_t sh_base[SI_NUM_SHADERS]; +}; + #define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */ #define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS #define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1) @@ -144,59 +151,48 @@ #define SI_NUM_VERTEX_BUFFERS 16 -/* This represents resource descriptors in memory, such as buffer resources, +/* This represents descriptors in memory, such as buffer resources, * image resources, and sampler states. */ struct si_descriptors { - struct r600_atom atom; - - /* The size of one resource descriptor. */ + /* The list of descriptors in malloc'd memory. */ + uint32_t *list; + /* The size of one descriptor. */ unsigned element_dw_size; - /* The maximum number of resource descriptors. */ + /* The maximum number of descriptors. */ unsigned num_elements; + /* Whether the list has been changed and should be re-uploaded. */ + bool list_dirty; - /* The buffer where resource descriptors are stored. */ + /* The buffer where the descriptors have been uploaded. */ struct r600_resource *buffer; unsigned buffer_offset; - /* The i-th bit is set if that element is dirty (changed but not emitted). */ - uint64_t dirty_mask; /* The i-th bit is set if that element is enabled (non-NULL resource). */ uint64_t enabled_mask; - /* We can't update descriptors directly because the GPU might be - * reading them at the same time, so we have to update them - * in a copy-on-write manner. Each such copy is called a context, - * which is just another array descriptors in the same buffer. */ - unsigned current_context_id; - /* The size of a context, should be equal to 4*element_dw_size*num_elements. */ - unsigned context_size; - - /* The shader userdata register where the 64-bit pointer to the descriptor + /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor * array will be stored. */ - unsigned shader_userdata_reg; + unsigned shader_userdata_offset; + /* Whether the pointer should be re-emitted. */ + bool pointer_dirty; }; struct si_sampler_views { struct si_descriptors desc; struct pipe_sampler_view *views[SI_NUM_SAMPLER_VIEWS]; - uint32_t *desc_data[SI_NUM_SAMPLER_VIEWS]; }; struct si_sampler_states { struct si_descriptors desc; - uint32_t *desc_data[SI_NUM_SAMPLER_STATES]; void *saved_states[2]; /* saved for u_blitter */ }; struct si_buffer_resources { struct si_descriptors desc; - unsigned num_buffers; enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */ enum radeon_bo_priority priority; struct pipe_resource **buffers; /* this has num_buffers elements */ - uint32_t *desc_storage; /* this has num_buffers*4 elements */ - uint32_t **desc_data; /* an array of pointers pointing to desc_storage */ }; #define si_pm4_block_idx(member) \ @@ -232,13 +228,13 @@ /* si_descriptors.c */ void si_set_sampler_descriptors(struct si_context *sctx, unsigned shader, unsigned start, unsigned count, void **states); -void si_update_vertex_buffers(struct si_context *sctx); void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot, struct pipe_resource *buffer, unsigned stride, unsigned num_records, bool add_tid, bool swizzle, unsigned element_size, unsigned index_stride); void si_init_all_descriptors(struct si_context *sctx); +bool si_upload_shader_descriptors(struct si_context *sctx); void si_release_all_descriptors(struct si_context *sctx); void si_all_descriptors_begin_new_cs(struct si_context *sctx); void si_copy_buffer(struct si_context *sctx, @@ -246,6 +242,7 @@ uint64_t dst_offset, uint64_t src_offset, unsigned size, bool is_framebuffer); void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer, const uint8_t *ptr, unsigned size, uint32_t *const_offset); +void si_shader_change_notify(struct si_context *sctx); /* si_state.c */ struct si_shader_selector; diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_state_shaders.c mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_state_shaders.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/drivers/radeonsi/si_state_shaders.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/drivers/radeonsi/si_state_shaders.c 2015-08-09 06:15:27.000000000 +0000 @@ -535,6 +535,7 @@ { struct si_context *sctx = (struct si_context *)ctx; struct si_shader_selector *sel = state; + bool enable_changed = !!sctx->gs_shader != !!sel; if (sctx->gs_shader == sel) return; @@ -542,6 +543,9 @@ sctx->gs_shader = sel; sctx->clip_regs.dirty = true; sctx->last_rast_prim = -1; /* reset this so that it gets updated */ + + if (enable_changed) + si_shader_change_notify(sctx); } static void si_make_dummy_ps(struct si_context *sctx) @@ -743,7 +747,6 @@ { struct si_shader *shader; uint64_t scratch_va = sctx->scratch_buffer->gpu_address; - unsigned char *ptr; if (!sel) return 0; @@ -764,12 +767,7 @@ si_shader_apply_scratch_relocs(sctx, shader, scratch_va); /* Replace the shader bo with a new bo that has the relocs applied. */ - r600_resource_reference(&shader->bo, NULL); - shader->bo = si_resource_create_custom(&sctx->screen->b.b, PIPE_USAGE_IMMUTABLE, - shader->binary.code_size); - ptr = sctx->screen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_WRITE); - util_memcpy_cpu_to_le32(ptr, shader->binary.code, shader->binary.code_size); - sctx->screen->b.ws->buffer_unmap(shader->bo->cs_buf); + si_shader_binary_upload(sctx->screen, shader); /* Update the shader state to use the new shader bo. */ si_shader_init_pm4_state(shader); diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/targets/opencl/Makefile.am mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/targets/opencl/Makefile.am --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/targets/opencl/Makefile.am 2015-02-25 15:01:21.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/targets/opencl/Makefile.am 2015-08-09 06:15:27.000000000 +0000 @@ -7,7 +7,7 @@ lib@OPENCL_LIBNAME@_la_LDFLAGS = \ $(LLVM_LDFLAGS) \ -no-undefined \ - -version-number 1:0 \ + -version-number @OPENCL_VERSION@:0 \ $(GC_SECTIONS) \ $(LD_NO_UNDEFINED) diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/targets/opencl/mesa.icd mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/targets/opencl/mesa.icd --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/targets/opencl/mesa.icd 2014-04-20 07:52:19.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/targets/opencl/mesa.icd 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -libMesaOpenCL.so diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/targets/opencl/mesa.icd.in mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/targets/opencl/mesa.icd.in --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/targets/opencl/mesa.icd.in 1970-01-01 00:00:00.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/targets/opencl/mesa.icd.in 2015-08-09 06:15:27.000000000 +0000 @@ -0,0 +1 @@ +lib@OPENCL_LIBNAME@.so.@OPENCL_VERSION@ diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 2015-07-27 05:57:14.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 2015-08-09 06:15:27.000000000 +0000 @@ -489,7 +489,7 @@ radeon_surface_manager_free(ws->surf_man); } - if (ws->fd) + if (ws->fd >= 0) close(ws->fd); FREE(rws); @@ -778,7 +778,7 @@ ws->kman->destroy(ws->kman); if (ws->surf_man) radeon_surface_manager_free(ws->surf_man); - if (ws->fd) + if (ws->fd >= 0) close(ws->fd); FREE(ws); diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/glsl/glcpp/glcpp-parse.y mesa-10.6.3+git20150809+10.6.736f6e16/src/glsl/glcpp/glcpp-parse.y --- mesa-10.6.3~git20150727+10.6.ccef8901/src/glsl/glcpp/glcpp-parse.y 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/glsl/glcpp/glcpp-parse.y 2015-08-09 06:15:27.000000000 +0000 @@ -1074,9 +1074,9 @@ */ if (node_a->token->type == SPACE && node_b->token->type == SPACE) { - while (node_a->token->type == SPACE) + while (node_a && node_a->token->type == SPACE) node_a = node_a->next; - while (node_b->token->type == SPACE) + while (node_b && node_b->token->type == SPACE) node_b = node_b->next; continue; } diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/glsl/ir.cpp mesa-10.6.3+git20150809+10.6.736f6e16/src/glsl/ir.cpp --- mesa-10.6.3~git20150727+10.6.ccef8901/src/glsl/ir.cpp 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/glsl/ir.cpp 2015-08-09 06:15:27.000000000 +0000 @@ -63,8 +63,6 @@ case 3: m.w = from; break; default: assert(!"Should not get here."); } - - m.num_components = MAX2(m.num_components, (to + 1)); } void @@ -95,6 +93,7 @@ write_mask |= (((this->write_mask >> i) & 1) << c); update_rhs_swizzle(rhs_swiz, i, c); + rhs_swiz.num_components = swiz->val->type->vector_elements; } this->write_mask = write_mask; @@ -114,6 +113,7 @@ if (write_mask & (1 << i)) update_rhs_swizzle(rhs_swiz, i, rhs_chan++); } + rhs_swiz.num_components = rhs_chan; this->rhs = new(mem_ctx) ir_swizzle(this->rhs, rhs_swiz); } diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/drivers/common/meta_tex_subimage.c mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/drivers/common/meta_tex_subimage.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/drivers/common/meta_tex_subimage.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/drivers/common/meta_tex_subimage.c 2015-08-09 06:15:27.000000000 +0000 @@ -25,8 +25,10 @@ * Jason Ekstrand */ +#include "blend.h" #include "bufferobj.h" #include "buffers.h" +#include "clear.h" #include "fbobject.h" #include "glformats.h" #include "glheader.h" @@ -247,6 +249,24 @@ return success; } +static bool +need_signed_unsigned_int_conversion(mesa_format rbFormat, + GLenum format, GLenum type) +{ + const GLenum srcType = _mesa_get_format_datatype(rbFormat); + const bool is_dst_format_integer = _mesa_is_enum_format_integer(format); + return (srcType == GL_INT && + is_dst_format_integer && + (type == GL_UNSIGNED_INT || + type == GL_UNSIGNED_SHORT || + type == GL_UNSIGNED_BYTE)) || + (srcType == GL_UNSIGNED_INT && + is_dst_format_integer && + (type == GL_INT || + type == GL_SHORT || + type == GL_BYTE)); +} + bool _mesa_meta_pbo_GetTexSubImage(struct gl_context *ctx, GLuint dims, struct gl_texture_image *tex_image, @@ -259,8 +279,9 @@ int full_height, image_height; struct gl_texture_image *pbo_tex_image; struct gl_renderbuffer *rb = NULL; - GLenum status; - bool success = false; + GLenum status, src_base_format; + bool success = false, clear_channels_to_zero = false; + float save_clear_color[4]; int z; if (!_mesa_is_bufferobj(packing->BufferObj)) @@ -272,14 +293,27 @@ format == GL_COLOR_INDEX) return false; - if (ctx->_ImageTransferState) - return false; - - + /* Don't use meta path for readpixels in below conditions. */ if (!tex_image) { rb = ctx->ReadBuffer->_ColorReadBuffer; + + /* _mesa_get_readpixels_transfer_ops() includes the cases of read + * color clamping along with the ctx->_ImageTransferState. + */ + if (_mesa_get_readpixels_transfer_ops(ctx, rb->Format, format, + type, GL_FALSE)) + return false; + if (_mesa_need_rgb_to_luminance_conversion(rb->Format, format)) return false; + + /* This function rely on BlitFramebuffer to fill in the pixel data for + * ReadPixels. But, BlitFrameBuffer doesn't support signed to unsigned + * or unsigned to signed integer conversions. OpenGL spec expects an + * invalid operation in that case. + */ + if (need_signed_unsigned_int_conversion(rb->Format, format, type)) + return false; } /* For arrays, use a tall (height * depth) 2D texture but taking into @@ -299,6 +333,10 @@ _mesa_meta_begin(ctx, ~(MESA_META_PIXEL_TRANSFER | MESA_META_PIXEL_STORE)); + /* GL_CLAMP_FRAGMENT_COLOR doesn't affect ReadPixels and GettexImage */ + if (ctx->Extensions.ARB_color_buffer_float) + _mesa_ClampColor(GL_CLAMP_FRAGMENT_COLOR, GL_FALSE); + _mesa_GenFramebuffers(2, fbos); if (tex_image && tex_image->TexObject->Target == GL_TEXTURE_1D_ARRAY) { @@ -344,6 +382,27 @@ GL_COLOR_BUFFER_BIT, GL_NEAREST)) goto fail; + src_base_format = tex_image ? + tex_image->_BaseFormat : + ctx->ReadBuffer->_ColorReadBuffer->_BaseFormat; + + /* Depending on the base formats involved we might need to rebase some + * values. For example if we download from a Luminance format to RGBA + * format, we want G=0 and B=0. + */ + clear_channels_to_zero = + _mesa_need_luminance_to_rgb_conversion(src_base_format, + pbo_tex_image->_BaseFormat); + + if (clear_channels_to_zero) { + memcpy(save_clear_color, ctx->Color.ClearColor.f, 4 * sizeof(float)); + /* Clear the Green, Blue channels. */ + _mesa_ColorMask(GL_FALSE, GL_TRUE, GL_TRUE, + src_base_format != GL_LUMINANCE_ALPHA); + _mesa_ClearColor(0.0, 0.0, 0.0, 1.0); + _mesa_Clear(GL_COLOR_BUFFER_BIT); + } + for (z = 1; z < depth; z++) { _mesa_meta_bind_fbo_image(GL_READ_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, tex_image, zoffset + z); @@ -356,6 +415,15 @@ 0, z * image_height, width, z * image_height + height, GL_COLOR_BUFFER_BIT, GL_NEAREST); + if (clear_channels_to_zero) + _mesa_Clear(GL_COLOR_BUFFER_BIT); + } + + /* Unmask the color channels and restore the saved clear color values. */ + if (clear_channels_to_zero) { + _mesa_ColorMask(GL_TRUE, GL_TRUE, GL_TRUE, GL_TRUE); + _mesa_ClearColor(save_clear_color[0], save_clear_color[1], + save_clear_color[2], save_clear_color[3]); } success = true; diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/drivers/dri/i965/brw_device_info.c mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/drivers/dri/i965/brw_device_info.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/drivers/dri/i965/brw_device_info.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/drivers/dri/i965/brw_device_info.c 2015-08-09 06:15:27.000000000 +0000 @@ -304,13 +304,13 @@ .must_use_separate_stencil = true, \ .has_llc = true, \ .has_pln = true, \ - .max_vs_threads = 280, \ - .max_gs_threads = 256, \ - .max_wm_threads = 408, \ + .max_vs_threads = 336, \ + .max_gs_threads = 336, \ + .max_wm_threads = 64 * 6, \ .urb = { \ - .size = 128, \ + .size = 192, \ .min_vs_entries = 64, \ - .max_vs_entries = 1664, \ + .max_vs_entries = 1856, \ .max_gs_entries = 640, \ } diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/drivers/dri/i965/brw_fs.cpp mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/drivers/dri/i965/brw_fs.cpp --- mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/drivers/dri/i965/brw_fs.cpp 2015-07-27 05:57:14.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/drivers/dri/i965/brw_fs.cpp 2015-08-09 06:15:27.000000000 +0000 @@ -973,6 +973,7 @@ case IMM: return 1; case GRF: + case ATTR: case HW_REG: if (src[arg].stride == 0) { return 1; diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/main/readpix.c mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/main/readpix.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/main/readpix.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/main/readpix.c 2015-08-09 06:15:27.000000000 +0000 @@ -60,13 +60,33 @@ format == GL_LUMINANCE_ALPHA_INTEGER_EXT); } +/** + * Return true if the conversion L,I to RGB conversion is needed. + */ +GLboolean +_mesa_need_luminance_to_rgb_conversion(GLenum srcBaseFormat, + GLenum dstBaseFormat) +{ + return (srcBaseFormat == GL_LUMINANCE || + srcBaseFormat == GL_LUMINANCE_ALPHA || + srcBaseFormat == GL_INTENSITY) && + (dstBaseFormat == GL_GREEN || + dstBaseFormat == GL_BLUE || + dstBaseFormat == GL_RG || + dstBaseFormat == GL_RGB || + dstBaseFormat == GL_BGR || + dstBaseFormat == GL_RGBA || + dstBaseFormat == GL_BGRA); +} /** * Return transfer op flags for this ReadPixels operation. */ -static GLbitfield -get_readpixels_transfer_ops(const struct gl_context *ctx, mesa_format texFormat, - GLenum format, GLenum type, GLboolean uses_blit) +GLbitfield +_mesa_get_readpixels_transfer_ops(const struct gl_context *ctx, + mesa_format texFormat, + GLenum format, GLenum type, + GLboolean uses_blit) { GLbitfield transferOps = ctx->_ImageTransferState; @@ -169,8 +189,8 @@ } /* And finally, see if there are any transfer ops. */ - return get_readpixels_transfer_ops(ctx, rb->Format, format, type, - uses_blit) != 0; + return _mesa_get_readpixels_transfer_ops(ctx, rb->Format, format, type, + uses_blit) != 0; } return GL_FALSE; } @@ -436,8 +456,8 @@ if (!rb) return; - transferOps = get_readpixels_transfer_ops(ctx, rb->Format, format, type, - GL_FALSE); + transferOps = _mesa_get_readpixels_transfer_ops(ctx, rb->Format, format, + type, GL_FALSE); /* Describe the dst format */ dst_is_integer = _mesa_is_enum_format_integer(format); dst_stride = _mesa_image_row_stride(packing, width, format, type); diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/main/readpix.h mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/main/readpix.h --- mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/main/readpix.h 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/main/readpix.h 2015-08-09 06:15:27.000000000 +0000 @@ -40,6 +40,16 @@ extern GLboolean _mesa_need_rgb_to_luminance_conversion(mesa_format texFormat, GLenum format); +extern GLboolean +_mesa_need_luminance_to_rgb_conversion(GLenum srcBaseFormat, + GLenum dstBaseFormat); + +extern GLbitfield +_mesa_get_readpixels_transfer_ops(const struct gl_context *ctx, + mesa_format texFormat, + GLenum format, GLenum type, + GLboolean uses_blit); + extern void _mesa_readpixels(struct gl_context *ctx, GLint x, GLint y, GLsizei width, GLsizei height, diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/main/shaderapi.c mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/main/shaderapi.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/main/shaderapi.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/main/shaderapi.c 2015-08-09 06:15:27.000000000 +0000 @@ -1692,12 +1692,23 @@ const void* binary, GLint length) { GET_CURRENT_CONTEXT(ctx); - (void) n; (void) shaders; (void) binaryformat; (void) binary; - (void) length; - _mesa_error(ctx, GL_INVALID_OPERATION, "glShaderBinary"); + + /* Page 68, section 7.2 'Shader Binaries" of the of the OpenGL ES 3.1, and + * page 88 of the OpenGL 4.5 specs state: + * + * "An INVALID_VALUE error is generated if count or length is negative. + * An INVALID_ENUM error is generated if binaryformat is not a supported + * format returned in SHADER_BINARY_FORMATS." + */ + if (n < 0 || length < 0) { + _mesa_error(ctx, GL_INVALID_VALUE, "glShaderBinary(count or length < 0)"); + return; + } + + _mesa_error(ctx, GL_INVALID_ENUM, "glShaderBinary(format)"); } diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/main/teximage.c mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/main/teximage.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/main/teximage.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/main/teximage.c 2015-08-09 06:15:27.000000000 +0000 @@ -2479,13 +2479,6 @@ return GL_TRUE; } - /* check target (proxies not allowed) */ - if (!legal_texsubimage_target(ctx, dimensions, target, dsa)) { - _mesa_error(ctx, GL_INVALID_ENUM, "%s(target=%s)", - callerName, _mesa_lookup_enum_by_nr(target)); - return GL_TRUE; - } - /* level check */ if (level < 0 || level >= _mesa_max_texture_levels(ctx, target)) { _mesa_error(ctx, GL_INVALID_VALUE, "%s(level=%d)", callerName, level); @@ -2629,13 +2622,6 @@ return GL_TRUE; } - rb = _mesa_get_read_renderbuffer_for_format(ctx, internalFormat); - if (rb == NULL) { - _mesa_error(ctx, GL_INVALID_OPERATION, - "glCopyTexImage%dD(read buffer)", dimensions); - return GL_TRUE; - } - /* OpenGL ES 1.x and OpenGL ES 2.0 impose additional restrictions on the * internalFormat. */ @@ -2648,7 +2634,7 @@ case GL_LUMINANCE_ALPHA: break; default: - _mesa_error(ctx, GL_INVALID_VALUE, + _mesa_error(ctx, GL_INVALID_ENUM, "glCopyTexImage%dD(internalFormat=%s)", dimensions, _mesa_lookup_enum_by_nr(internalFormat)); return GL_TRUE; @@ -2657,12 +2643,19 @@ baseFormat = _mesa_base_tex_format(ctx, internalFormat); if (baseFormat < 0) { - _mesa_error(ctx, GL_INVALID_OPERATION, + _mesa_error(ctx, GL_INVALID_ENUM, "glCopyTexImage%dD(internalFormat=%s)", dimensions, _mesa_lookup_enum_by_nr(internalFormat)); return GL_TRUE; } + rb = _mesa_get_read_renderbuffer_for_format(ctx, internalFormat); + if (rb == NULL) { + _mesa_error(ctx, GL_INVALID_OPERATION, + "glCopyTexImage%dD(read buffer)", dimensions); + return GL_TRUE; + } + rb_internal_format = rb->InternalFormat; rb_base_format = _mesa_base_tex_format(ctx, rb->InternalFormat); if (_mesa_is_color_format(internalFormat)) { @@ -3515,14 +3508,6 @@ { FLUSH_VERTICES(ctx, 0); - /* check target (proxies not allowed) */ - if (!legal_texsubimage_target(ctx, dims, target, dsa)) { - _mesa_error(ctx, GL_INVALID_ENUM, "glTex%sSubImage%uD(target=%s)", - dsa ? "ture" : "", - dims, _mesa_lookup_enum_by_nr(target)); - return; - } - if (ctx->NewState & _NEW_PIXEL) _mesa_update_state(ctx); @@ -3572,6 +3557,13 @@ struct gl_texture_object *texObj; struct gl_texture_image *texImage; + /* check target (proxies not allowed) */ + if (!legal_texsubimage_target(ctx, dims, target, false)) { + _mesa_error(ctx, GL_INVALID_ENUM, "glTexSubImage%uD(target=%s)", + dims, _mesa_lookup_enum_by_nr(target)); + return; + } + texObj = _mesa_get_current_tex_object(ctx, target); if (!texObj) return; @@ -3632,6 +3624,13 @@ return; } + /* check target (proxies not allowed) */ + if (!legal_texsubimage_target(ctx, dims, texObj->Target, true)) { + _mesa_error(ctx, GL_INVALID_ENUM, "%s(target=%s)", + callerName, _mesa_lookup_enum_by_nr(texObj->Target)); + return; + } + if (texsubimage_error_check(ctx, dims, texObj, texObj->Target, level, xoffset, yoffset, zoffset, width, height, depth, format, type, diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/state_tracker/st_atom_texture.c mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/state_tracker/st_atom_texture.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/state_tracker/st_atom_texture.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/state_tracker/st_atom_texture.c 2015-08-09 06:15:27.000000000 +0000 @@ -478,7 +478,7 @@ "st_update_texture", /* name */ { /* dirty */ _NEW_TEXTURE, /* mesa */ - ST_NEW_FRAGMENT_PROGRAM, /* st */ + ST_NEW_FRAGMENT_PROGRAM | ST_NEW_SAMPLER_VIEWS, /* st */ }, update_fragment_textures /* update */ }; @@ -488,7 +488,7 @@ "st_update_vertex_texture", /* name */ { /* dirty */ _NEW_TEXTURE, /* mesa */ - ST_NEW_VERTEX_PROGRAM, /* st */ + ST_NEW_VERTEX_PROGRAM | ST_NEW_SAMPLER_VIEWS, /* st */ }, update_vertex_textures /* update */ }; @@ -498,7 +498,7 @@ "st_update_geometry_texture", /* name */ { /* dirty */ _NEW_TEXTURE, /* mesa */ - ST_NEW_GEOMETRY_PROGRAM, /* st */ + ST_NEW_GEOMETRY_PROGRAM | ST_NEW_SAMPLER_VIEWS, /* st */ }, update_geometry_textures /* update */ }; diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/state_tracker/st_cb_blit.c mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/state_tracker/st_cb_blit.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/state_tracker/st_cb_blit.c 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/state_tracker/st_cb_blit.c 2015-08-09 06:15:27.000000000 +0000 @@ -39,7 +39,7 @@ #include "st_cb_bitmap.h" #include "st_cb_blit.h" #include "st_cb_fbo.h" -#include "st_atom.h" +#include "st_manager.h" #include "util/u_format.h" @@ -92,7 +92,7 @@ } clip; struct pipe_blit_info blit; - st_validate_state(st); + st_manager_validate_framebuffers(st); /* Make sure bitmap rendering has landed in the framebuffers */ st_flush_bitmap_cache(st); diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/state_tracker/st_context.c mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/state_tracker/st_context.c --- mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/state_tracker/st_context.c 2015-07-27 05:57:14.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/state_tracker/st_context.c 2015-08-09 06:15:27.000000000 +0000 @@ -313,6 +313,7 @@ f->NewArray = ST_NEW_VERTEX_ARRAYS; f->NewRasterizerDiscard = ST_NEW_RASTERIZER; f->NewUniformBuffer = ST_NEW_UNIFORM_BUFFER; + f->NewTextureBuffer = ST_NEW_SAMPLER_VIEWS; } struct st_context *st_create_context(gl_api api, struct pipe_context *pipe, diff -Nru mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/state_tracker/st_context.h mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/state_tracker/st_context.h --- mesa-10.6.3~git20150727+10.6.ccef8901/src/mesa/state_tracker/st_context.h 2015-07-25 09:20:43.000000000 +0000 +++ mesa-10.6.3+git20150809+10.6.736f6e16/src/mesa/state_tracker/st_context.h 2015-08-09 06:15:27.000000000 +0000 @@ -58,6 +58,8 @@ #define ST_NEW_VERTEX_ARRAYS (1 << 6) #define ST_NEW_RASTERIZER (1 << 7) #define ST_NEW_UNIFORM_BUFFER (1 << 8) +/* gap for TESSCTRL/TESSEVAL that's in master only */ +#define ST_NEW_SAMPLER_VIEWS (1 << 11) struct st_state_flags {