Linaro GCC 4.6-2011.10

Milestone information

Project:
Linaro GCC
Series:
4.6
Version:
4.6-2011.10
Released:
2011-10-13  
Registrant:
Michael Hope
Release registered:
2011-10-13
Active:
Yes. Drivers can target bugs and blueprints to this milestone.  

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Assignees:
1 Andrew Stubbs, 3 Ira Rosen, 1 Michael Hope, 1 Revital Eres, 3 Richard Sandiford
Blueprints:
7 Implemented
Bugs:
2 Fix Released

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Release notes 

Linaro GCC 4.6 2011.10 is the eighth release in the 4.6 series. Based
off the latest GCC 4.6.1+svn179483, it contains a range of vectoriser
performance improvements and general bug fixes.

Interesting changes include:
 * Updates to 4.6.1+svn179483
 * Vectorises more straight-line code with data dependencies
 * Now picks the best vector width when vectorising straight line code
 * Better handles handling auto increment addresses in SMS
 * Changes the default vector width from double word to quad word
 * Better handling extracting the top or bottom half of a quad word vector
 * Now supports the NEON absolute difference instruction

Fixes:
 * LP: #689887 ICE in get_arm_condition_code
 * LP: #809761 oss4 version 4.2-build2004-1ubuntu1 failed to build on armel

The source tarballs are available from:
 https://launchpad.net/gcc-linaro/+milestone/4.6-2011.10

Downloads are available from the Linaro GCC page on Launchpad:
 https://launchpad.net/gcc-linaro

More information on the features and issues are available from the
release page:
 https://launchpad.net/gcc-linaro/4.6/4.6-2011.10

Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain

Bugs: https://bugs.launchpad.net/gcc-linaro/

Questions? https://ask.linaro.org/

Interested in commercial support? inquire at support@linaro.org

Changelog 

View the full changelog

2011-10-04 Andrew Stubbs <email address hidden>

 Merge from FSF GCC 4.6.1 (svn branches/gcc-4_6-branch 179483).

2011-10-06 Ira Rosen <email address hidden>

 gcc/testsuite/
 * gcc.dg/vect/bb-slp-26.c: Simplify to make the basic block
 vectorizable.

 Backport from mainline:

 2011-09-25 Ira Rosen <email address hidden>

 gcc/
 * tree-vect-slp.c (vect_slp_analyze_bb_1): Split out core part
 of vect_analyze_bb here.
 (vect_analyze_bb): Loop over vector sizes calling vect_analyze_bb_1.

 gcc/testsuite/
 * lib/target-supports.exp (check_effective_target_vect64): New.
 * gcc.dg/vect/bb-slp-11.c: Expect the error message twice in case
 of multiple vector sizes.
 * gcc.dg/vect/bb-slp-26.c: New.

2011-10-06 Ira Rosen <email address hidden>

 Backport from mainline:

 2011-09-25 Ira Rosen <email address hidden>

 gcc/
 * tree-data-ref.c (dr_analyze_innermost): Add new argument.
 Allow not simple iv if analyzing basic block.
 (create_data_ref): Update call to dr_analyze_innermost.
 (stmt_with_adjacent_zero_store_dr_p, ref_base_address): Likewise.
 * tree-loop-distribution.c (generate_memset_zero): Likewise.
 * tree-predcom.c (find_looparound_phi): Likewise.
 * tree-data-ref.h (dr_analyze_innermost): Add new argument.

 gcc/testsuite/
 * gcc.dg/vect/bb-slp-24.c: New.

 2011-09-15 Ira Rosen <email address hidden>

 gcc/
 * tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Allow
 read-after-read dependencies in basic block SLP.

 gcc/testsuite/
 * gcc.dg/vect/bb-slp-25.c: New.

 2011-04-21 Richard Sandiford <email address hidden>

 gcc/
 * tree-vect-data-refs.c (vect_drs_dependent_in_basic_block): Use
 operand_equal_p to compare DR_BASE_ADDRESSes.
 (vect_check_interleaving): Likewise.

 gcc/testsuite/
 * gcc.dg/vect/vect-119.c: New test.

2011-10-03 Richard Sandiford <email address hidden>

 gcc/
 Backport from mainline:

 2011-09-22 Richard Sandiford <email address hidden>

 * config/arm/predicates.md (expandable_comparison_operator): New
 predicate, extracted from...
 (arm_comparison_operator): ...here.
 * config/arm/arm.md (cbranchsi4, cbranchsf4, cbranchdf4, cbranchdi4)
 (cstoresi4, cstoresf4, cstoredf4, cstoredi4, movsicc, movsfcc)
 (movdfcc): Use expandable_comparison_operator.

 gcc/testsuite/
 Backport from mainline:

 2011-09-22 Richard Sandiford <email address hidden>

 * gcc.target/arm/cmp-1.c: New test.
 * gcc.target/arm/cmp-2.c: Likewise.

2011-10-03 Richard Sandiford <email address hidden>

 gcc/
 Backport from mainline:

 2011-09-07 Richard Sandiford <email address hidden>

 PR target/49030
 * config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
 * config/arm/arm.c (maybe_get_arm_condition_code): New function,
 reusing the old code from get_arm_condition_code. Return ARM_NV
 for invalid comparison codes.
 (get_arm_condition_code): Redefine in terms of
 maybe_get_arm_condition_code.
 * config/arm/predicates.md (arm_comparison_operator): Use
 maybe_get_arm_condition_code.

 gcc/testsuite/
 Backport from mainline:

 2011-09-07 Richard Sandiford <email address hidden>

 PR target/49030
 * gcc.dg/torture/pr49030.c: New test.

2011-10-03 Michael Hope <email address hidden>

 Backport from mainline:

 2011-09-13 Sevak Sargsyan <email address hidden>

 gcc/
 * config/arm/neon.md (neon_vabd<mode>_2, neon_vabd<mode>_3): New
 define_insn patterns for combine.

 gcc/testsuite/
 * gcc.target/arm/neon-combine-sub-abs-into-vabd.c: New test.

2011-10-01 Revital Eres <email address hidden>

 gcc/
 Backport from mainline -r179380 and -r179381

 * ddg.c (autoinc_var_is_used_p): New function.
 (create_ddg_dep_from_intra_loop_link,
 add_cross_iteration_register_deps): Call it.
 * ddg.h (autoinc_var_is_used_p): Declare.
 * modulo-sched.c (sms_schedule): Handle instructions with REG_INC.
 (generate_reg_moves): Call autoinc_var_is_used_p. Skip
 instructions that do not set a register and verify no regmoves
 are created for !single_set instructions.

 gcc/testsuite/

 * gcc.dg/sms-10.c: New file

2011-09-28 Richard Sandiford <email address hidden>

 gcc/
 Backport from mainline:

 2011-09-28 Richard Sandiford <email address hidden>

 * config/arm/neon.md (neon_move_lo_quad_<mode>): Delete.
 (neon_move_hi_quad_<mode>): Likewise.
 (move_hi_quad_<mode>, move_lo_quad_<mode>): Use subreg moves.

2011-09-28 Richard Sandiford <email address hidden>

 gcc/
 Backport from mainline:

 2011-09-27 Richard Sandiford <email address hidden>

 * config/arm/neon.md (neon_vget_highv16qi, neon_vget_highv8hi)
 (neon_vget_highv4si, neon_vget_highv4sf, neon_vget_highv2di)
 (neon_vget_lowv16qi, neon_vget_lowv8hi, neon_vget_lowv4si)
 (neon_vget_lowv4sf, neon_vget_lowv2di): Turn into define_expands
 that produce subreg moves. Define using VQX iterators.

2011-09-28 Richard Sandiford <email address hidden>

 gcc/
 Backport from mainline:

 2011-09-14 Richard Sandiford <email address hidden>

 * simplify-rtx.c (simplify_subreg): Check that the inner mode is
 a scalar integer before applying integer-only optimisations to
 inner arithmetic.

2011-09-25 Ira Rosen <email address hidden>

 gcc/testsuite/
 * lib/target-supports.exp (check_effective_target_vect_multiple_sizes):
 Replace check_effective_target_arm_neon with
 check_effective_target_arm_neon_ok.

 Backport from mainline:

 2011-09-06 Ira Rosen <email address hidden>

 gcc/
 * config/arm/arm.c (arm_preferred_simd_mode): Check
 TARGET_NEON_VECTORIZE_DOUBLE instead of
 TARGET_NEON_VECTORIZE_QUAD.
 (arm_autovectorize_vector_sizes): Likewise.
 * config/arm/arm.opt (mvectorize-with-neon-quad): Make inverse
 mask of mvectorize-with-neon-double. Add RejectNegative.
 (mvectorize-with-neon-double): New.

 gcc/testsuite/
 * lib/target-supports.exp (check_effective_target_vect_multiple_sizes):
 New procedure.
 (add_options_for_quad_vectors): Replace with ...
 (add_options_for_double_vectors): ... this.
 * gfortran.dg/vect/pr19049.f90: Expect more printings on targets that
 support multiple vector sizes since the vectorizer attempts to
 vectorize with both vector sizes.
 * gcc.dg/vect/no-vfa-vect-79.c,
 gcc.dg/vect/no-vfa-vect-102a.c, gcc.dg/vect/vect-outer-1a.c,
 gcc.dg/vect/vect-outer-1b.c, gcc.dg/vect/vect-outer-2b.c,
 gcc.dg/vect/vect-outer-3a.c, gcc.dg/vect/no-vfa-vect-37.c,
 gcc.dg/vect/vect-outer-3b.c, gcc.dg/vect/no-vfa-vect-101.c,
 gcc.dg/vect/no-vfa-vect-102.c, gcc.dg/vect/vect-reduc-dot-s8b.c,
 gcc.dg/vect/vect-outer-1.c, gcc.dg/vect/vect-104.c: Likewise.
 * gcc.dg/vect/vect-42.c: Run with 64 bit vectors if applicable.
 * gcc.dg/vect/vect-multitypes-6.c, gcc.dg/vect/vect-52.c,
 gcc.dg/vect/vect-54.c, gcc.dg/vect/vect-46.c, gcc.dg/vect/vect-48.c,
 gcc.dg/vect/vect-96.c, gcc.dg/vect/vect-multitypes-3.c,
 gcc.dg/vect/vect-40.c: Likewise.
 * gcc.dg/vect/vect-outer-5.c: Remove quad-vectors option as
 redundant.
 * gcc.dg/vect/vect-109.c, gcc.dg/vect/vect-peel-1.c,
 gcc.dg/vect/vect-peel-2.c, gcc.dg/vect/slp-25.c,
 gcc.dg/vect/vect-multitypes-1.c, gcc.dg/vect/slp-3.c,
 gcc.dg/vect/no-vfa-pr29145.c, gcc.dg/vect/vect-multitypes-4.c:
 Likewise.
 * gcc.dg/vect/vect-peel-4.c: Make ia global.

2011-09-22 Revital Eres <email address hidden>

 Backport from trunk -r178804:
 * modulo-sched.c (remove_node_from_ps): Return void
 instead of bool.
 (optimize_sc): Adjust call to remove_node_from_ps.
 (sms_schedule): Add print info.

7 blueprints and 2 bugs targeted

Blueprint Priority Assignee Delivery
Improve SLP data analysis 4 High Ira Rosen  11 Implemented
Linaro GCC the product (some work for this milestone) 4 High Andrew Stubbs  11 Implemented
Improve extraction of double vectors from quad vectors 3 Medium Richard Sandiford  11 Implemented
Make SLP try different vector widths 3 Medium Ira Rosen  11 Implemented
SMS: support auto-inc 3 Medium Revital Eres  11 Implemented
Widen default vector size 3 Medium Ira Rosen  11 Implemented
Add backend support for NEON's VABD 2 Low Michael Hope  11 Implemented
Bug report Importance Assignee Status
689887 #689887 armel ICE gcc 4.5 4 Medium Richard Sandiford  10 Fix Released
809761 #809761 oss4 version 4.2-build2004-1ubuntu1 failed to build on armel 4 Medium Richard Sandiford  10 Fix Released
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