diff -u binutils-2.26.1/debian/changelog binutils-2.26.1/debian/changelog --- binutils-2.26.1/debian/changelog +++ binutils-2.26.1/debian/changelog @@ -1,3 +1,29 @@ +binutils (2.26.1-1ubuntu1~16.04.6) xenial; urgency=medium + + * pr19353.diff: Fix internal error when applying TLSDESC relocations with no TLS + segment. (LP: #1722162) + + -- Timo Aaltonen Wed, 08 Nov 2017 18:06:03 +0200 + +binutils (2.26.1-1ubuntu1~16.04.5) xenial-proposed; urgency=medium + + * SRU: LP: #1696686. + * Fix PR ld/20608: Relocation truncated to fit: R_ARM_THM_JUMP24 for + relocation to PLT entry. + + -- Matthias Klose Mon, 21 Aug 2017 16:24:14 +0200 + +binutils (2.26.1-1ubuntu1~16.04.4) xenial-proposed; urgency=medium + + * SRU + * POWER backports (LP: #1655181) + - Don't treat .opd section specially when ELFv2. + - Fix PowerPC64 ELFv1 undefined weak functions. + - Modify POWER9 support to match final ISA 3.0 documentation. + * Fix PR gold/18989. Implement --push-state/--pop-state. LP: #1623418. + + -- Matthias Klose Fri, 10 Feb 2017 02:30:30 +0100 + binutils (2.26.1-1ubuntu1~16.04.3) xenial-security; urgency=medium [ Matthias Klose ] diff -u binutils-2.26.1/debian/patches/series binutils-2.26.1/debian/patches/series --- binutils-2.26.1/debian/patches/series +++ binutils-2.26.1/debian/patches/series @@ -32,0 +33,12 @@ + +# patches taken from the 2.26 branch +power9-isa-3.0.diff + +# patches taken from the 2.27 branch +power9-001.diff +power9-004.diff + +# patches taken from the trunk +pr18989.diff +pr20608.diff +pr19353.diff only in patch2: unchanged: --- binutils-2.26.1.orig/debian/patches/power9-001.diff +++ binutils-2.26.1/debian/patches/power9-001.diff @@ -0,0 +1,61 @@ +PowerPC64 ELFv1 undefined weak functions + +Undefined weak functions, like __gmon_start__, were not being made +dynamic or emitting plt call code. While the behaviour of undefined +weak symbols is not defined in the ELF standard, the intention on +powerpc64 was to make it possible to link without a definition of such +symbols and at run time behave the same as if a definition was found +at link time in a shared library. + +2016-08-11 Alan Modra + + * elf64-ppc.c (ppc64_elf_adjust_dynamic_symbol): Don't exit with + non_got_ref true in any case where we could have generated dynbss + copies but decide not to do so. + + +diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c +index d7af888..cd9fda9 100644 +--- a/bfd/elf64-ppc.c ++++ b/bfd/elf64-ppc.c +@@ -7223,29 +7223,20 @@ ppc64_elf_adjust_dynamic_symbol (struct bfd_link_info *info, + return TRUE; + + /* Don't generate a copy reloc for symbols defined in the executable. */ +- if (!h->def_dynamic || !h->ref_regular || h->def_regular) +- return TRUE; ++ if (!h->def_dynamic || !h->ref_regular || h->def_regular + +- /* If -z nocopyreloc was given, don't generate them either. */ +- if (info->nocopyreloc) +- { +- h->non_got_ref = 0; +- return TRUE; +- } ++ /* If -z nocopyreloc was given, don't generate them either. */ ++ || info->nocopyreloc + +- /* If we didn't find any dynamic relocs in read-only sections, then +- we'll be keeping the dynamic relocs and avoiding the copy reloc. */ +- if (ELIMINATE_COPY_RELOCS && !readonly_dynrelocs (h)) +- { +- h->non_got_ref = 0; +- return TRUE; +- } ++ /* If we didn't find any dynamic relocs in read-only sections, then ++ we'll be keeping the dynamic relocs and avoiding the copy reloc. */ ++ || (ELIMINATE_COPY_RELOCS && !readonly_dynrelocs (h)) + +- /* Protected variables do not work with .dynbss. The copy in +- .dynbss won't be used by the shared library with the protected +- definition for the variable. Text relocations are preferable +- to an incorrect program. */ +- if (h->protected_def) ++ /* Protected variables do not work with .dynbss. The copy in ++ .dynbss won't be used by the shared library with the protected ++ definition for the variable. Text relocations are preferable ++ to an incorrect program. */ ++ || h->protected_def) + { + h->non_got_ref = 0; + return TRUE; only in patch2: unchanged: --- binutils-2.26.1.orig/debian/patches/power9-004.diff +++ binutils-2.26.1/debian/patches/power9-004.diff @@ -0,0 +1,76 @@ +2016-09-01 Alan Modra + + * elf64-ppc.c (synthetic_opd): New static var. + (compare_symbols): Don't treat symbols in .opd specially for ELFv2. + (ppc64_elf_get_synthetic_symtab): Likewise. Comment. + + +diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c +index 461bd5e..d236732 100644 +--- a/bfd/elf64-ppc.c ++++ b/bfd/elf64-ppc.c +@@ -3085,6 +3085,7 @@ get_opd_info (asection * sec) + + /* Parameters for the qsort hook. */ + static bfd_boolean synthetic_relocatable; ++static asection *synthetic_opd; + + /* qsort comparison function for ppc64_elf_get_synthetic_symtab. */ + +@@ -3101,12 +3102,15 @@ compare_symbols (const void *ap, const void *bp) + return 1; + + /* then .opd symbols. */ +- if (strcmp (a->section->name, ".opd") == 0 +- && strcmp (b->section->name, ".opd") != 0) +- return -1; +- if (strcmp (a->section->name, ".opd") != 0 +- && strcmp (b->section->name, ".opd") == 0) +- return 1; ++ if (synthetic_opd != NULL) ++ { ++ if (strcmp (a->section->name, ".opd") == 0 ++ && strcmp (b->section->name, ".opd") != 0) ++ return -1; ++ if (strcmp (a->section->name, ".opd") != 0 ++ && strcmp (b->section->name, ".opd") == 0) ++ return 1; ++ } + + /* then other code symbols. */ + if ((a->section->flags & (SEC_CODE | SEC_ALLOC | SEC_THREAD_LOCAL)) +@@ -3265,6 +3269,7 @@ ppc64_elf_get_synthetic_symtab (bfd *abfd, + memcpy (syms, static_syms, (symcount + 1) * sizeof (*syms)); + + synthetic_relocatable = relocatable; ++ synthetic_opd = opd; + qsort (syms, symcount, sizeof (*syms), compare_symbols); + + if (!relocatable && symcount > 1) +@@ -3281,7 +3286,11 @@ ppc64_elf_get_synthetic_symtab (bfd *abfd, + } + + i = 0; +- if (strcmp (syms[i]->section->name, ".opd") == 0) ++ /* Note that here and in compare_symbols we can't compare opd and ++ sym->section directly. With separate debug info files, the ++ symbols will be extracted from the debug file while abfd passed ++ to this function is the real binary. */ ++ if (opd != NULL && strcmp (syms[i]->section->name, ".opd") == 0) + ++i; + codesecsym = i; + +@@ -3297,9 +3306,10 @@ ppc64_elf_get_synthetic_symtab (bfd *abfd, + break; + secsymend = i; + +- for (; i < symcount; ++i) +- if (strcmp (syms[i]->section->name, ".opd") != 0) +- break; ++ if (opd != NULL) ++ for (; i < symcount; ++i) ++ if (strcmp (syms[i]->section->name, ".opd") != 0) ++ break; + opdsymend = i; + + for (; i < symcount; ++i) only in patch2: unchanged: --- binutils-2.26.1.orig/debian/patches/power9-isa-3.0.diff +++ binutils-2.26.1/debian/patches/power9-isa-3.0.diff @@ -0,0 +1,344 @@ +diff --git a/gas/ChangeLog b/gas/ChangeLog +index 66bc9a3..2f783e5 100644 +--- a/gas/ChangeLog ++++ b/gas/ChangeLog +@@ -1,3 +1,14 @@ ++2016-09-16 Peter Bergner ++ ++ Apply from master. ++ 2016-09-14 Peter Bergner ++ ++ * testsuite/gas/ppc/power9.d New tests. ++ : Remove tests. ++ : Update tests. ++ * testsuite/gas/ppc/power9.s: Likewise. ++ + 2016-06-29 Tristan Gingold + + * configure: Regenerate. +diff --git a/gas/testsuite/gas/ppc/power9.d b/gas/testsuite/gas/ppc/power9.d +index 5004e11..4da740d 100644 +--- a/gas/testsuite/gas/ppc/power9.d ++++ b/gas/testsuite/gas/ppc/power9.d +@@ -278,14 +278,6 @@ Disassembly of section \.text: + .*: (7f a8 49 80|80 49 a8 7f) cmprb cr7,1,r8,r9 + .*: (7d e0 01 00|00 01 e0 7d) setb r15,cr0 + .*: (7d fc 01 00|00 01 fc 7d) setb r15,cr7 +-.*: (7e 00 01 01|01 01 00 7e) setbool r16,lt +-.*: (7e 01 01 01|01 01 01 7e) setbool r16,gt +-.*: (7e 02 01 01|01 01 02 7e) setbool r16,eq +-.*: (7e 03 01 01|01 01 03 7e) setbool r16,so +-.*: (7e 1c 01 01|01 01 1c 7e) setbool r16,4\*cr7\+lt +-.*: (7e 1d 01 01|01 01 1d 7e) setbool r16,4\*cr7\+gt +-.*: (7e 1e 01 01|01 01 1e 7e) setbool r16,4\*cr7\+eq +-.*: (7e 1f 01 01|01 01 1f 7e) setbool r16,4\*cr7\+so + .*: (7f 40 52 1a|1a 52 40 7f) lxvl vs26,0,r10 + .*: (7f 14 52 1b|1b 52 14 7f) lxvl vs56,r20,r10 + .*: (7f 60 5b 1a|1a 5b 60 7f) stxvl vs27,0,r11 +@@ -329,6 +321,7 @@ Disassembly of section \.text: + .*: (4c e0 80 04|04 80 e0 4c) addpcis r7,-32768 + .*: (4c e0 80 04|04 80 e0 4c) addpcis r7,-32768 + .*: (7c 00 02 a4|a4 02 00 7c) slbsync ++.*: (7d 40 06 a4|a4 06 40 7d) slbiag r10 + .*: (7d 40 5b a4|a4 5b 40 7d) slbieg r10,r11 + .*: (7c 60 27 26|26 27 60 7c) slbmfee r3,r4 + .*: (7c 60 27 26|26 27 60 7c) slbmfee r3,r4 +@@ -342,14 +335,9 @@ Disassembly of section \.text: + .*: (7c 00 1a 24|24 1a 00 7c) tlbiel r3 + .*: (7c 00 1a 24|24 1a 00 7c) tlbiel r3 + .*: (7c 8f 1a 24|24 1a 8f 7c) tlbiel r3,r4,3,1,1 +-.*: (7c 0c 6e 0c|0c 6e 0c 7c) copy r12,r13 +-.*: (7c 2c 6e 0c|0c 6e 2c 7c) copy_first r12,r13 +-.*: (7c 2c 6e 0c|0c 6e 2c 7c) copy_first r12,r13 +-.*: (7c 0a 5f 0c|0c 5f 0a 7c) paste r10,r11 +-.*: (7c 0a 5f 0c|0c 5f 0a 7c) paste r10,r11 +-.*: (7c 2a 5f 0d|0d 5f 2a 7c) paste_last r10,r11 +-.*: (7c 2a 5f 0d|0d 5f 2a 7c) paste_last r10,r11 +-.*: (7c 00 06 8c|8c 06 00 7c) cp_abort ++.*: (7c 2c 6e 0c|0c 6e 2c 7c) copy r12,r13 ++.*: (7c 2a 5f 0d|0d 5f 2a 7c) paste\. r10,r11 ++.*: (7c 00 06 8c|8c 06 00 7c) cpabort + .*: (7c 00 04 ac|ac 04 00 7c) hwsync + .*: (7c 00 04 ac|ac 04 00 7c) hwsync + .*: (7c 00 04 ac|ac 04 00 7c) hwsync +@@ -357,8 +345,6 @@ Disassembly of section \.text: + .*: (7c 20 04 ac|ac 04 20 7c) lwsync + .*: (7c 40 04 ac|ac 04 40 7c) ptesync + .*: (7c 40 04 ac|ac 04 40 7c) ptesync +-.*: (7c 07 04 ac|ac 04 07 7c) sync 0,7 +-.*: (7c 28 04 ac|ac 04 28 7c) sync 1,8 + .*: (7e 80 04 cc|cc 04 80 7e) ldat r20,0,0 + .*: (7e 8a e4 cc|cc e4 8a 7e) ldat r20,r10,28 + .*: (7e a0 04 8c|8c 04 a0 7e) lwat r21,0,0 +@@ -371,8 +357,6 @@ Disassembly of section \.text: + .*: (7c 00 f6 e4|e4 f6 00 7c) rmieg r30 + .*: (7d 40 7a 6a|6a 7a 40 7d) ldmx r10,0,r15 + .*: (7d 43 7a 6a|6a 7a 43 7d) ldmx r10,r3,r15 +-.*: (7d 60 83 6a|6a 83 60 7d) lwzmx r11,0,r16 +-.*: (7d 63 83 6a|6a 83 63 7d) lwzmx r11,r3,r16 + .*: (4c 00 02 e4|e4 02 00 4c) stop + .*: (7c 00 00 3c|3c 00 00 7c) wait + .*: (7c 00 00 3c|3c 00 00 7c) wait +@@ -395,9 +379,6 @@ Disassembly of section \.text: + .*: (7d 6c 69 54|54 69 6c 7d) addex r11,r12,r13,0 + .*: (7d 6c 6b 54|54 6b 6c 7d) addex r11,r12,r13,1 + .*: (7d 6c 6d 54|54 6d 6c 7d) addex r11,r12,r13,2 +-.*: (7e b6 b9 55|55 b9 b6 7e) addex\. r21,r22,r23,0 +-.*: (7e b6 bb 55|55 bb b6 7e) addex\. r21,r22,r23,1 +-.*: (7e b6 bd 55|55 bd b6 7e) addex\. r21,r22,r23,2 + .*: (ff 20 04 8e|8e 04 20 ff) mffs f25 + .*: (ff 20 04 8f|8f 04 20 ff) mffs\. f25 + .*: (ff 41 04 8e|8e 04 41 ff) mffsce f26 +@@ -408,12 +389,4 @@ Disassembly of section \.text: + .*: (ff d7 04 8e|8e 04 d7 ff) mffscrni f30,0 + .*: (ff d7 1c 8e|8e 1c d7 ff) mffscrni f30,3 + .*: (ff f8 04 8e|8e 04 f8 ff) mffsl f31 +-.*: (7e 8a 01 76|76 01 8a 7e) brd r10,r20 +-.*: (7e ab 01 b6|b6 01 ab 7e) brh r11,r21 +-.*: (7e cc 01 36|36 01 cc 7e) brw r12,r22 +-.*: (11 6a 63 77|77 63 6a 11) nandxor r10,r11,r12,r13 +-.*: (12 b4 b5 f6|f6 b5 b4 12) xor3 r20,r21,r22,r23 +-.*: (11 6a 60 34|34 60 6a 11) rldixor r10,r11,0,r12 +-.*: (11 6a 66 f4|f4 66 6a 11) rldixor r10,r11,27,r12 +-.*: (11 6a 67 f5|f5 67 6a 11) rldixor r10,r11,63,r12 + #pass +diff --git a/gas/testsuite/gas/ppc/power9.s b/gas/testsuite/gas/ppc/power9.s +index 851c146..5fcf4a7 100644 +--- a/gas/testsuite/gas/ppc/power9.s ++++ b/gas/testsuite/gas/ppc/power9.s +@@ -269,14 +269,6 @@ power9: + cmprb 7,1,8,9 + setb 15,0 + setb 15,7 +- setbool 16,0 +- setbool 16,1 +- setbool 16,2 +- setbool 16,3 +- setbool 16,28 +- setbool 16,29 +- setbool 16,30 +- setbool 16,31 + lxvl 26,0,10 + lxvl 56,20,10 + stxvl 27,0,11 +@@ -320,6 +312,7 @@ power9: + addpcis 7,-0x8000 + subpcis 7,0x8000 + slbsync ++ slbiag 10 + slbieg 10,11 + slbmfee 3,4 + slbmfee 3,4,0 +@@ -333,23 +326,16 @@ power9: + tlbiel 3 + tlbiel 3,0,0,0,0 + tlbiel 3,4,3,1,1 +- copy 12,13,0 +- copy_first 12,13 +- copy 12,13,1 +- paste 10,11,0 +- paste 10,11 +- paste. 10,11,1 +- paste_last 10,11 +- cp_abort ++ copy 12,13 ++ paste. 10,11 ++ cpabort + hwsync + sync +- sync 0,0x0 ++ sync 0 + lwsync +- sync 1,0x0 ++ sync 1 + ptesync +- sync 2,0x0 +- sync 0,0x7 +- sync 1,0x8 ++ sync 2 + ldat 20,0,0x0 + ldat 20,10,0x1c + lwat 21,0,0x0 +@@ -362,8 +348,6 @@ power9: + rmieg 30 + ldmx 10,0,15 + ldmx 10,3,15 +- lwzmx 11,0,16 +- lwzmx 11,3,16 + stop + wait + wait 0 +@@ -386,9 +370,6 @@ power9: + addex 11,12,13,0 + addex 11,12,13,1 + addex 11,12,13,2 +- addex. 21,22,23,0 +- addex. 21,22,23,1 +- addex. 21,22,23,2 + mffs 25 + mffs. 25 + mffsce 26 +@@ -399,11 +380,3 @@ power9: + mffscrni 30,0 + mffscrni 30,3 + mffsl 31 +- brd 10,20 +- brh 11,21 +- brw 12,22 +- nandxor 10,11,12,13 +- xor3 20,21,22,23 +- rldixor 10,11,0,12 +- rldixor 10,11,27,12 +- rldixor 10,11,63,12 +diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog +index a26cec1..d384e52 100644 +--- a/opcodes/ChangeLog ++++ b/opcodes/ChangeLog +@@ -1,3 +1,22 @@ ++2016-09-16 Peter Bergner ++ ++ Apply from master. ++ 2016-09-14 Peter Bergner ++ ++ * ppc-opc.c (powerpc_opcodes) : New mnemonic. ++ : Delete mnemonics. ++ : Rename mnemonic from ... ++ : ...to this. ++ : Change to a X form instruction. ++ : Change to 1 operand form. ++ : Delete mnemonic. ++ : Rename mnemonic from ... ++ : ...to this. ++ : Delete mnemonics. ++ : Rename mnemonic from ... ++ : ...to this. ++ + 2016-06-29 Tristan Gingold + + * configure: Regenerate. +diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c +index 21932f8..1e4cb6f 100644 +--- a/opcodes/ppc-opc.c ++++ b/opcodes/ppc-opc.c +@@ -3154,7 +3154,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"machhwu.", XO (4, 12,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, + {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, + {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, +-{"rldixor", VXASH(4,26), VXASH_MASK, POWER9, PPCNONE, {RA, RS, SH6, RB}}, + {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, + {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, + {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +@@ -3201,8 +3200,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, + {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, + {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}}, +-{"xor3", VXA(4, 54), VXA_MASK, POWER9, PPCNONE, {RA, RS, RB, RC}}, +-{"nandxor", VXA(4, 55), VXA_MASK, POWER9, PPCNONE, {RA, RS, RB, RC}}, + {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, VC}}, + {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}}, + {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}}, +@@ -4936,8 +4933,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { + + {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}}, + +-{"setb", VX(31,256), VXVB_MASK|(3<<16), POWER9, PPCNONE, {RT, BFA}}, +-{"setbool", VX(31,257), VXVB_MASK, POWER9, PPCNONE, {RT, BA}}, ++{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, PPCNONE, {RT, BFA}}, + + {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}}, + +@@ -4987,8 +4983,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { + + {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}}, + +-{"brw", X(31,155), XRB_MASK, POWER9, PPCNONE, {RA, RS}}, +- + {"stdepx", X(31,157), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}}, + + {"stwepx", X(31,159), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}}, +@@ -5001,7 +4995,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + + {"addex", ZRC(31,170,0), Z2_MASK, POWER9, PPCNONE, {RT, RA, RB, CY}}, +-{"addex.", ZRC(31,170,1), Z2_MASK, POWER9, PPCNONE, {RT, RA, RB, CY}}, + + {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, PPCNONE, {RB}}, + {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, +@@ -5026,8 +5019,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { + + {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}}, + +-{"brd", X(31,187), XRB_MASK, POWER9, PPCNONE, {RA, RS}}, +- + {"cmprb", X(31,192), XCMP_MASK, POWER9, PPCNONE, {BF, L, RA, RB}}, + + {"icblq.", XRC(31,198,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}}, +@@ -5066,8 +5057,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + {"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +-{"brh", X(31,219), XRB_MASK, POWER9, PPCNONE, {RA, RS}}, +- + {"stbepx", X(31,223), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}}, + + {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, PPCNONE, {BF, RA, RB}}, +@@ -5534,8 +5523,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { + + {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}}, + +-{"lwzmx", X(31,437), X_MASK, POWER9, PPCNONE, {RT, RA0, RB}}, +- + {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, + + {"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}}, +@@ -5899,8 +5886,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}}, + {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, + {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}}, +-{"sync", X(31,598), XSYNCLE_MASK,POWER9|E6500, PPCNONE, {LS, ESYNC}}, +-{"sync", X(31,598), XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476|POWER9, {LS}}, ++{"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}}, ++{"sync", X(31,598), XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476,{LS}}, + {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}}, + {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, + {"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}}, +@@ -6065,8 +6052,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { + + {"lvsm", X(31,773), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, + +-{"copy_first", XOPL(31,774,1), XRT_MASK, POWER9, PPCNONE, {RA0, RB}}, +-{"copy", X(31,774), XLRT_MASK, POWER9, PPCNONE, {RA0, RB, L}}, ++{"copy", XOPL(31,774,1), XRT_MASK, POWER9, PPCNONE, {RA0, RB}}, + + {"stvepxl", X(31,775), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, + {"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, +@@ -6136,7 +6122,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { + + {"lvtlxl", X(31,837), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, + +-{"cp_abort", X(31,838), XRTRARB_MASK,POWER9, PPCNONE, {0}}, ++{"cpabort", X(31,838), XRTRARB_MASK,POWER9, PPCNONE, {0}}, + + {"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + {"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +@@ -6148,6 +6134,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { + + {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, PPCNONE, {RA0, RB}}, + ++{"slbiag", X(31,850), XRARB_MASK, POWER9, PPCNONE, {RS}}, + {"slbmfev", X(31,851), XRLA_MASK, POWER9, PPCNONE, {RT, RB, A_L}}, + {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, + +@@ -6183,9 +6170,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"extswsli", XS(31,445,0), XS_MASK, POWER9, PPCNONE, {RA, RS, SH6}}, + {"extswsli.", XS(31,445,1), XS_MASK, POWER9, PPCNONE, {RA, RS, SH6}}, + +-{"paste", XRC(31,902,0), XLRT_MASK, POWER9, PPCNONE, {RA0, RB, L0}}, +-{"paste_last", XRCL(31,902,1,1),XRT_MASK, POWER9, PPCNONE, {RA0, RB}}, +-{"paste.", XRC(31,902,1), XLRT_MASK, POWER9, PPCNONE, {RA0, RB, L1}}, ++{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, PPCNONE, {RA0, RB}}, + + {"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, + {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, only in patch2: unchanged: --- binutils-2.26.1.orig/debian/patches/pr18989.diff +++ binutils-2.26.1/debian/patches/pr18989.diff @@ -0,0 +1,134 @@ +# DP: Fix PR gold/18989. Implement --push-state/--pop-state. + +Index: b/gold/options.cc +=================================================================== +--- a/gold/options.cc ++++ b/gold/options.cc +@@ -687,6 +687,20 @@ General_options::string_to_object_format + } + } + ++const char* ++General_options::object_format_to_string(General_options::Object_format fmt) ++{ ++ switch (fmt) ++ { ++ case General_options::OBJECT_FORMAT_ELF: ++ return "elf"; ++ case General_options::OBJECT_FORMAT_BINARY: ++ return "binary"; ++ default: ++ gold_unreachable(); ++ } ++} ++ + void + General_options::parse_fix_v4bx(const char*, const char*, + Command_line*) +@@ -713,6 +727,39 @@ General_options::parse_EL(const char*, c + this->endianness_ = ENDIANNESS_LITTLE; + } + ++void ++General_options::copy_from_posdep_options( ++ const Position_dependent_options& posdep) ++{ ++ this->set_as_needed(posdep.as_needed()); ++ this->set_Bdynamic(posdep.Bdynamic()); ++ this->set_format( ++ General_options::object_format_to_string(posdep.format_enum())); ++ this->set_whole_archive(posdep.whole_archive()); ++ this->set_incremental_disposition(posdep.incremental_disposition()); ++} ++ ++void ++General_options::parse_push_state(const char*, const char*, Command_line*) ++{ ++ Position_dependent_options* posdep = new Position_dependent_options(*this); ++ this->options_stack_.push_back(posdep); ++} ++ ++void ++General_options::parse_pop_state(const char*, const char*, Command_line*) ++{ ++ if (this->options_stack_.empty()) ++ { ++ gold::gold_error(_("unbalanced --push-state/--pop-state")); ++ return; ++ } ++ Position_dependent_options* posdep = this->options_stack_.back(); ++ this->options_stack_.pop_back(); ++ this->copy_from_posdep_options(*posdep); ++ delete posdep; ++} ++ + } // End namespace gold. + + namespace +Index: b/gold/options.h +=================================================================== +--- a/gold/options.h ++++ b/gold/options.h +@@ -1028,6 +1028,11 @@ class General_options + N_("Print symbols defined and used for each input"), + N_("FILENAME")); + ++ DEFINE_special(push_state, options::TWO_DASHES, '\0', ++ N_("Save the state of flags related to input files"), NULL); ++ DEFINE_special(pop_state, options::TWO_DASHES, '\0', ++ N_("Restore the state of flags related to input files"), NULL); ++ + DEFINE_bool(Qy, options::EXACTLY_ONE_DASH, '\0', false, + N_("Ignored for SVR4 compatibility"), NULL); + +@@ -1403,6 +1408,10 @@ class General_options + static Object_format + string_to_object_format(const char* arg); + ++ // Convert an Object_format to string. ++ static const char* ++ object_format_to_string(Object_format); ++ + // Note: these functions are not very fast. + Object_format format_enum() const; + Object_format oformat_enum() const; +@@ -1496,6 +1505,10 @@ class General_options + incremental_disposition() const + { return this->incremental_disposition_; } + ++ void ++ set_incremental_disposition(Incremental_disposition disp) ++ { this->incremental_disposition_ = disp; } ++ + // The disposition to use for startup files (those that precede the + // first --incremental-changed, etc. option). + Incremental_disposition +@@ -1627,6 +1640,9 @@ class General_options + void + add_plugin_option(const char* opt); + ++ void ++ copy_from_posdep_options(const Position_dependent_options&); ++ + // Whether we printed version information. + bool printed_version_; + // Whether to mark the stack as executable. +@@ -1670,6 +1686,8 @@ class General_options + Endianness endianness_; + // What local symbols to discard. + Discard_locals discard_locals_; ++ // Stack of saved options for --push-state/--pop-state. ++ std::vector options_stack_; + }; + + // The position-dependent options. We use this to store the state of +@@ -1700,7 +1718,8 @@ class Position_dependent_options + = Position_dependent_options::default_options_) + { copy_from_options(options); } + +- void copy_from_options(const General_options& options) ++ void ++ copy_from_options(const General_options& options) + { + this->set_as_needed(options.as_needed()); + this->set_Bdynamic(options.Bdynamic()); only in patch2: unchanged: --- binutils-2.26.1.orig/debian/patches/pr19353.diff +++ binutils-2.26.1/debian/patches/pr19353.diff @@ -0,0 +1,168 @@ +From d21f123b0ead1806416cf0dafae12bec4cca8920 Mon Sep 17 00:00:00 2001 +From: Cary Coutant +Date: Mon, 11 Jan 2016 23:57:44 -0800 +Subject: [PATCH 1/1] Fix internal error when applying TLSDESC relocations with + no TLS segment. + +gold/ + PR gold/19353 + * aarch64.cc (Target_aarch64::relocate_tls): Don't insist that + we have a TLS segment for GD-to-IE optimization. + * i386.cc (Target_i386::tls_gd_to_ie): Remove tls_segment parameter. + Adjust all calls. + (Target_i386::tls_desc_gd_to_ie): Likewise. + (Target_i386::relocate_tls): Don't insist that we have a TLS segment + for TLSDESC GD-to-IE optimizations. + * x86_64.cc (Target_x86_64::tls_gd_to_ie): Remove tls_segment parameter. + Adjust all calls. + (Target_x86_64::tls_desc_gd_to_ie): Likewise. + (Target_x86_64::relocate_tls): Don't insist that we have a TLS segment + for TLSDESC GD-to-IE optimizations. +--- + gold/ChangeLog | 16 ++++++++++++++++ + gold/aarch64.cc | 6 ------ + gold/i386.cc | 14 ++------------ + gold/x86_64.cc | 14 ++------------ + 4 files changed, 20 insertions(+), 30 deletions(-) + +diff --git a/gold/aarch64.cc b/gold/aarch64.cc +index 20f2f4f..5ad061b 100644 +--- a/gold/aarch64.cc ++++ b/gold/aarch64.cc +@@ -7422,12 +7422,6 @@ Target_aarch64::Relocate::relocate_tls( + } + if (tlsopt == tls::TLSOPT_TO_IE) + { +- if (tls_segment == NULL) +- { +- gold_assert(parameters->errors()->error_count() > 0 +- || issue_undefined_symbol_error(gsym)); +- return aarch64_reloc_funcs::STATUS_BAD_RELOC; +- } + return tls_desc_gd_to_ie(relinfo, target, rela, r_type, + view, psymval, got_entry_address, + address); +diff --git a/gold/i386.cc b/gold/i386.cc +index 82886d4..a7168a8 100644 +--- a/gold/i386.cc ++++ b/gold/i386.cc +@@ -668,7 +668,6 @@ class Target_i386 : public Sized_target<32, false> + // Do a TLS General-Dynamic to Initial-Exec transition. + inline void + tls_gd_to_ie(const Relocate_info<32, false>*, size_t relnum, +- Output_segment* tls_segment, + const elfcpp::Rel<32, false>&, unsigned int r_type, + elfcpp::Elf_types<32>::Elf_Addr value, + unsigned char* view, +@@ -687,7 +686,6 @@ class Target_i386 : public Sized_target<32, false> + // transition. + inline void + tls_desc_gd_to_ie(const Relocate_info<32, false>*, size_t relnum, +- Output_segment* tls_segment, + const elfcpp::Rel<32, false>&, unsigned int r_type, + elfcpp::Elf_types<32>::Elf_Addr value, + unsigned char* view, +@@ -3054,7 +3052,7 @@ Target_i386::Relocate::relocate_tls(const Relocate_info<32, false>* relinfo, + } + if (optimized_type == tls::TLSOPT_TO_IE) + { +- this->tls_gd_to_ie(relinfo, relnum, tls_segment, rel, r_type, ++ this->tls_gd_to_ie(relinfo, relnum, rel, r_type, + got_offset, view, view_size); + break; + } +@@ -3116,13 +3114,7 @@ Target_i386::Relocate::relocate_tls(const Relocate_info<32, false>* relinfo, + } + if (optimized_type == tls::TLSOPT_TO_IE) + { +- if (tls_segment == NULL) +- { +- gold_assert(parameters->errors()->error_count() > 0 +- || issue_undefined_symbol_error(gsym)); +- return; +- } +- this->tls_desc_gd_to_ie(relinfo, relnum, tls_segment, rel, r_type, ++ this->tls_desc_gd_to_ie(relinfo, relnum, rel, r_type, + got_offset, view, view_size); + break; + } +@@ -3354,7 +3346,6 @@ Target_i386::Relocate::tls_gd_to_le(const Relocate_info<32, false>* relinfo, + inline void + Target_i386::Relocate::tls_gd_to_ie(const Relocate_info<32, false>* relinfo, + size_t relnum, +- Output_segment*, + const elfcpp::Rel<32, false>& rel, + unsigned int, + elfcpp::Elf_types<32>::Elf_Addr value, +@@ -3449,7 +3440,6 @@ inline void + Target_i386::Relocate::tls_desc_gd_to_ie( + const Relocate_info<32, false>* relinfo, + size_t relnum, +- Output_segment*, + const elfcpp::Rel<32, false>& rel, + unsigned int r_type, + elfcpp::Elf_types<32>::Elf_Addr value, +diff --git a/gold/x86_64.cc b/gold/x86_64.cc +index 3cfc064..4ad5afc 100644 +--- a/gold/x86_64.cc ++++ b/gold/x86_64.cc +@@ -816,7 +816,6 @@ class Target_x86_64 : public Sized_target + // Do a TLS General-Dynamic to Initial-Exec transition. + inline void + tls_gd_to_ie(const Relocate_info*, size_t relnum, +- Output_segment* tls_segment, + const elfcpp::Rela&, unsigned int r_type, + typename elfcpp::Elf_types::Elf_Addr value, + unsigned char* view, +@@ -835,7 +834,6 @@ class Target_x86_64 : public Sized_target + // Do a TLSDESC-style General-Dynamic to Initial-Exec transition. + inline void + tls_desc_gd_to_ie(const Relocate_info*, size_t relnum, +- Output_segment* tls_segment, + const elfcpp::Rela&, unsigned int r_type, + typename elfcpp::Elf_types::Elf_Addr value, + unsigned char* view, +@@ -3733,7 +3731,7 @@ Target_x86_64::Relocate::relocate_tls( + if (optimized_type == tls::TLSOPT_TO_IE) + { + value = target->got_plt_section()->address() + got_offset; +- this->tls_gd_to_ie(relinfo, relnum, tls_segment, rela, r_type, ++ this->tls_gd_to_ie(relinfo, relnum, rela, r_type, + value, view, address, view_size); + break; + } +@@ -3800,14 +3798,8 @@ Target_x86_64::Relocate::relocate_tls( + } + if (optimized_type == tls::TLSOPT_TO_IE) + { +- if (tls_segment == NULL) +- { +- gold_assert(parameters->errors()->error_count() > 0 +- || issue_undefined_symbol_error(gsym)); +- return; +- } + value = target->got_plt_section()->address() + got_offset; +- this->tls_desc_gd_to_ie(relinfo, relnum, tls_segment, ++ this->tls_desc_gd_to_ie(relinfo, relnum, + rela, r_type, value, view, address, + view_size); + break; +@@ -3973,7 +3965,6 @@ inline void + Target_x86_64::Relocate::tls_gd_to_ie( + const Relocate_info* relinfo, + size_t relnum, +- Output_segment*, + const elfcpp::Rela& rela, + unsigned int, + typename elfcpp::Elf_types::Elf_Addr value, +@@ -4085,7 +4076,6 @@ inline void + Target_x86_64::Relocate::tls_desc_gd_to_ie( + const Relocate_info* relinfo, + size_t relnum, +- Output_segment*, + const elfcpp::Rela& rela, + unsigned int r_type, + typename elfcpp::Elf_types::Elf_Addr value, +-- +2.9.3 + only in patch2: unchanged: --- binutils-2.26.1.orig/debian/patches/pr20608.diff +++ binutils-2.26.1/debian/patches/pr20608.diff @@ -0,0 +1,346 @@ +From fc7afe8c75ccd6b34d8381384268d7cbe02cf1ed Mon Sep 17 00:00:00 2001 +From: Christophe Lyon +Date: Wed, 28 Sep 2016 01:37:52 +0200 +Subject: [PATCH] [ARM] PR ld/20608 Relocation truncated to fit: + R_ARM_THM_JUMP24 for relocation to PLT entry + +2016-09-28 Christophe Lyon + + PR ld/20608 + bfd/ + * elf32-arm.c (arm_type_of_stub): Handle the case when the pre-PLT + Thumb-ARM stub is too far. + + ld + * testsuite/ld-arm/arm-elf.exp: Handle new testcase. + * testsuite/ld-arm/farcall-mixed-app2.d: New file. + * testsuite/ld-arm/farcall-mixed-app2.r: Likewise. + * testsuite/ld-arm/farcall-mixed-app2.s: Likewise. + * testsuite/ld-arm/farcall-mixed-app2.sym: Likewise. +--- + bfd/elf32-arm.c | 47 ++++++++++++-- + ld/testsuite/ld-arm/arm-elf.exp | 6 ++ + ld/testsuite/ld-arm/farcall-mixed-app2.d | 99 ++++++++++++++++++++++++++++++ + ld/testsuite/ld-arm/farcall-mixed-app2.r | 10 +++ + ld/testsuite/ld-arm/farcall-mixed-app2.s | 76 +++++++++++++++++++++++ + ld/testsuite/ld-arm/farcall-mixed-app2.sym | 15 +++++ + 8 files changed, 267 insertions(+), 6 deletions(-) + create mode 100644 ld/testsuite/ld-arm/farcall-mixed-app2.d + create mode 100644 ld/testsuite/ld-arm/farcall-mixed-app2.r + create mode 100644 ld/testsuite/ld-arm/farcall-mixed-app2.s + create mode 100644 ld/testsuite/ld-arm/farcall-mixed-app2.sym + +diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c +index 3d4a458..700bec3 100644 +--- a/bfd/elf32-arm.c ++++ b/bfd/elf32-arm.c +@@ -3877,17 +3877,43 @@ arm_type_of_stub (struct bfd_link_info *info, + /* Note when dealing with PLT entries: the main PLT stub is in + ARM mode, so if the branch is in Thumb mode, another + Thumb->ARM stub will be inserted later just before the ARM +- PLT stub. We don't take this extra distance into account +- here, because if a long branch stub is needed, we'll add a +- Thumb->Arm one and branch directly to the ARM PLT entry +- because it avoids spreading offset corrections in several +- places. */ ++ PLT stub. If a long branch stub is needed, we'll add a ++ Thumb->Arm one and branch directly to the ARM PLT entry. ++ Here, we have to check if a pre-PLT Thumb->ARM stub ++ is needed and if it will be close enough. */ + + destination = (splt->output_section->vma + + splt->output_offset + + root_plt->offset); + st_type = STT_FUNC; +- branch_type = ST_BRANCH_TO_ARM; ++ ++ /* Thumb branch/call to PLT: it can become a branch to ARM ++ or to Thumb. We must perform the same checks and ++ corrections as in elf32_arm_final_link_relocate. */ ++ if ((r_type == R_ARM_THM_CALL) ++ || (r_type == R_ARM_THM_JUMP24)) ++ { ++ if (globals->use_blx ++ && r_type == R_ARM_THM_CALL ++ && !thumb_only) ++ { ++ /* If the Thumb BLX instruction is available, convert ++ the BL to a BLX instruction to call the ARM-mode ++ PLT entry. */ ++ branch_type = ST_BRANCH_TO_ARM; ++ } ++ else ++ { ++ if (!thumb_only) ++ /* Target the Thumb stub before the ARM PLT entry. */ ++ destination -= PLT_THUMB_STUB_SIZE; ++ branch_type = ST_BRANCH_TO_THUMB; ++ } ++ } ++ else ++ { ++ branch_type = ST_BRANCH_TO_ARM; ++ } + } + } + /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */ +@@ -3923,6 +3949,15 @@ arm_type_of_stub (struct bfd_link_info *info, + || (r_type == R_ARM_THM_JUMP19)) + && !use_plt)) + { ++ /* If we need to insert a Thumb-Thumb long branch stub to a ++ PLT, use one that branches directly to the ARM PLT ++ stub. If we pretended we'd use the pre-PLT Thumb->ARM ++ stub, undo this now. */ ++ if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only) { ++ branch_type = ST_BRANCH_TO_ARM; ++ branch_offset += PLT_THUMB_STUB_SIZE; ++ } ++ + if (branch_type == ST_BRANCH_TO_THUMB) + { + /* Thumb to thumb. */ +diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp +index a5d4c87..50a2f26 100644 +--- a/ld/testsuite/ld-arm/arm-elf.exp ++++ b/ld/testsuite/ld-arm/arm-elf.exp +@@ -556,6 +556,12 @@ set armeabitests_nonacl { + {readelf -Ds farcall-mixed-app.sym}} + "farcall-mixed-app-v5"} + ++ {"Mixed ARM/Thumb2 dynamic application with farcalls" "tmpdir/mixed-lib.so -T arm-dyn.ld --section-start .mid_thumb=0x10081c0 --section-start .far_arm=0x2100000 --section-start .far_thumb=0x2200000" "" "" ++ {farcall-mixed-app2.s} ++ {{objdump -fdw farcall-mixed-app2.d} {objdump -Rw farcall-mixed-app2.r} ++ {readelf -Ds farcall-mixed-app2.sym}} ++ "farcall-mixed-app2"} ++ + {"Mixed ARM/Thumb shared library with long branches (v4t)" "-shared -T arm-lib.ld" "" "-march=armv4t" + {farcall-mixed-lib1.s farcall-mixed-lib2.s} + {{objdump -fdw farcall-mixed-lib-v4t.d}} +diff --git a/ld/testsuite/ld-arm/farcall-mixed-app2.d b/ld/testsuite/ld-arm/farcall-mixed-app2.d +new file mode 100644 +index 0000000..54338d0 +--- /dev/null ++++ b/ld/testsuite/ld-arm/farcall-mixed-app2.d +@@ -0,0 +1,99 @@ ++ ++tmpdir/farcall-mixed-app2: file format elf32-(little|big)arm ++architecture: arm.*, flags 0x00000112: ++EXEC_P, HAS_SYMS, D_PAGED ++start address 0x.* ++ ++Disassembly of section .plt: ++ ++.* : ++ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) ++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* ++ .*: e08fe00e add lr, pc, lr ++ .*: e5bef008 ldr pc, \[lr, #8\]! ++ .*: .* ++.* : ++ .*: 4778 bx pc ++ .*: 46c0 nop ; \(mov r8, r8\) ++ .*: e28fc6.* add ip, pc, #.* ++ .*: e28cca.* add ip, ip, #.* ; 0x.* ++ .*: e5bcf.* ldr pc, \[ip, #.*\]!.* ++.* : ++ .*: e28fc6.* add ip, pc, #.* ++ .*: e28cca.* add ip, ip, #.* ; 0x.* ++ .*: e5bcf.* ldr pc, \[ip, #.*\]!.* ++ ++Disassembly of section .text: ++ ++.* <_start>: ++ .*: e1a0c00d mov ip, sp ++ .*: e92dd800 push {fp, ip, lr, pc} ++ .*: eb000008 bl .* <__app_func_veneer> ++ .*: ebfffff6 bl .* ++ .*: ebfffff2 bl .* ++ .*: e89d6800 ldm sp, {fp, sp, lr} ++ .*: e12fff1e bx lr ++ .*: e1a00000 nop ; \(mov r0, r0\) ++ ++.* : ++ .*: b500 push {lr} ++ .*: f7ff efde blx 81e0 ++ .*: bd00 pop {pc} ++ .*: 4770 bx lr ++ .*: 46c0 nop ; \(mov r8, r8\) ++#... ++ ++.* <__app_func_veneer>: ++ .*: e51ff004 ldr pc, \[pc, #-4\] ; 8234 <__app_func_veneer\+0x4> ++ .*: 02100000 .word 0x02100000 ++ ++Disassembly of section .mid_thumb: ++ ++.* : ++#... ++ .*: f400 9000 b.w .* ++ .*: f000 b800 b.w .* <__lib_func2_from_thumb> ++ ++.* <__lib_func2_from_thumb>: ++ .*: 4778 bx pc ++ .*: 46c0 nop ; \(mov r8, r8\) ++ .*: e51ff004 ldr pc, \[pc, #-4\] ; 10081e8 <__lib_func2_from_thumb\+0x8> ++ .*: 000081e0 .word 0x000081e0 ++ .*: 00000000 .word 0x00000000 ++ ++Disassembly of section .far_arm: ++ ++.* : ++ .*: e1a0c00d mov ip, sp ++ .*: e92dd800 push {fp, ip, lr, pc} ++ .*: eb000006 bl .* <__lib_func1_veneer> ++ .*: eb000007 bl .* <__lib_func2_veneer> ++ .*: e89d6800 ldm sp, {fp, sp, lr} ++ .*: e12fff1e bx lr ++ .*: e1a00000 nop ; \(mov r0, r0\) ++ .*: e1a00000 nop ; \(mov r0, r0\) ++ ++.* : ++ .*: e12fff1e bx lr ++#... ++ ++.* <__lib_func1_veneer>: ++ .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func1_veneer\+0x4> ++ .*: 000081ec .word 0x000081ec ++.* <__lib_func2_veneer>: ++ .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func2_veneer\+0x4> ++ .*: 000081e0 .word 0x000081e0 ++ ++Disassembly of section .far_thumb: ++ ++.* : ++ .*: b500 push {lr} ++ .*: f000 e806 blx .* <__lib_func2_from_thumb> ++ .*: bd00 pop {pc} ++ .*: 4770 bx lr ++ .*: 46c0 nop ; \(mov r8, r8\) ++#... ++ ++.* <__lib_func2_from_thumb>: ++ .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200014 <__lib_func2_from_thumb\+0x4> ++ .*: 000081e0 .word 0x000081e0 +diff --git a/ld/testsuite/ld-arm/farcall-mixed-app2.r b/ld/testsuite/ld-arm/farcall-mixed-app2.r +new file mode 100644 +index 0000000..910a361 +--- /dev/null ++++ b/ld/testsuite/ld-arm/farcall-mixed-app2.r +@@ -0,0 +1,10 @@ ++ ++tmpdir/farcall-mixed-app.*: file format elf32-(little|big)arm ++ ++DYNAMIC RELOCATION RECORDS ++OFFSET TYPE VALUE ++.* R_ARM_COPY data_obj ++.* R_ARM_JUMP_SLOT lib_func2 ++.* R_ARM_JUMP_SLOT lib_func1 ++ ++ +diff --git a/ld/testsuite/ld-arm/farcall-mixed-app2.s b/ld/testsuite/ld-arm/farcall-mixed-app2.s +new file mode 100644 +index 0000000..ee315e9 +--- /dev/null ++++ b/ld/testsuite/ld-arm/farcall-mixed-app2.s +@@ -0,0 +1,76 @@ ++ .text ++ .p2align 4 ++ .globl _start ++_start: ++ mov ip, sp ++ stmdb sp!, {r11, ip, lr, pc} ++ bl app_func ++ bl lib_func1 ++ bl lib_func2 ++ ldmia sp, {r11, sp, lr} ++ bx lr ++ ++ .p2align 4 ++ .globl app_tfunc_close ++ .type app_tfunc_close,%function ++ .thumb_func ++ .code 16 ++app_tfunc_close: ++ push {lr} ++ bl lib_func2 ++ pop {pc} ++ bx lr ++ ++@ We will place the section .mid_thumb at 0xFFFEF8. ++@ Just far enough for XXXX ++ .section .mid_thumb, "xa" ++ ++ .p2align 4 ++ .globl mid_tfunc ++ .type mid_tfunc,%function ++ .thumb_func ++ .code 16 ++mid_tfunc: ++ .syntax unified ++ .space 24 ++ b.w lib_func2 ++ b.w lib_func2 ++ ++@ We will place the section .far_arm at 0x2100000. ++ .section .far_arm, "xa" ++ ++ .arm ++ .p2align 4 ++ .globl app_func ++ .type app_func,%function ++app_func: ++ mov ip, sp ++ stmdb sp!, {r11, ip, lr, pc} ++ bl lib_func1 ++ bl lib_func2 ++ ldmia sp, {r11, sp, lr} ++ bx lr ++ ++ .arm ++ .p2align 4 ++ .globl app_func2 ++ .type app_func2,%function ++app_func2: ++ bx lr ++ ++@ We will place the section .far_thumb at 0x2200000. ++ .section .far_thumb, "xa" ++ ++ .p2align 4 ++ .globl app_tfunc ++ .type app_tfunc,%function ++ .thumb_func ++ .code 16 ++app_tfunc: ++ push {lr} ++ bl lib_func2 ++ pop {pc} ++ bx lr ++ ++ .data ++ .long data_obj +diff --git a/ld/testsuite/ld-arm/farcall-mixed-app2.sym b/ld/testsuite/ld-arm/farcall-mixed-app2.sym +new file mode 100644 +index 0000000..1d3bd1d +--- /dev/null ++++ b/ld/testsuite/ld-arm/farcall-mixed-app2.sym +@@ -0,0 +1,15 @@ ++ ++Symbol table for image: ++ +Num +Buc: +Value +Size +Type +Bind +Vis +Ndx +Name ++ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +11 _edata ++ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 __bss_start__ ++ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 _end ++ +.. +..: ........ +4 +OBJECT +GLOBAL +DEFAULT +12 data_obj ++ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 __bss_end__ ++ +.. +..: 0*[^0]*.* +0 +FUNC +GLOBAL +DEFAULT +UND lib_func1 ++ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +11 __data_start ++ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 __end__ ++ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 __bss_start ++ +.. +..: .......0 +0 +FUNC +GLOBAL +DEFAULT +15 app_func2 ++ +.. +..: 0*[^0]*.* +0 +FUNC +GLOBAL +DEFAULT +UND lib_func2 ++ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 _bss_end__ +-- +2.9.3 +