diff -Nru cpputest-3.7.2/debian/changelog cpputest-3.7.2+dfsg/debian/changelog --- cpputest-3.7.2/debian/changelog 2015-05-11 08:02:35.000000000 +0000 +++ cpputest-3.7.2+dfsg/debian/changelog 2016-05-09 20:22:44.000000000 +0000 @@ -1,3 +1,12 @@ +cpputest (3.7.2+dfsg-1) unstable; urgency=medium + + * Repackage upstream tarball to drop platforms* directories containing + some non-free files. Closes: #823711 + * Update Standards-Version to 3.9.8. + * Update Vcs-Git and Vcs-Browser to use https URLs. + + -- Raphaël Hertzog Mon, 09 May 2016 22:15:27 +0200 + cpputest (3.7.2-1) unstable; urgency=medium * New upstream release that drops the test that fails on arm64, powerpc, diff -Nru cpputest-3.7.2/debian/control cpputest-3.7.2+dfsg/debian/control --- cpputest-3.7.2/debian/control 2015-05-11 08:02:35.000000000 +0000 +++ cpputest-3.7.2+dfsg/debian/control 2016-05-09 20:22:44.000000000 +0000 @@ -3,9 +3,9 @@ Priority: optional Maintainer: Raphaël Hertzog Homepage: http://cpputest.github.io/ -Vcs-Git: git://anonscm.debian.org/collab-maint/cpputest.git -Vcs-Browser: http://anonscm.debian.org/cgit/collab-maint/cpputest.git -Standards-Version: 3.9.6 +Vcs-Git: https://anonscm.debian.org/git/collab-maint/cpputest.git +Vcs-Browser: https://anonscm.debian.org/cgit/collab-maint/cpputest.git +Standards-Version: 3.9.8 Build-Depends: debhelper (>= 9.20120608~), dh-autoreconf Package: cpputest diff -Nru cpputest-3.7.2/debian/copyright cpputest-3.7.2+dfsg/debian/copyright --- cpputest-3.7.2/debian/copyright 2015-05-11 08:02:35.000000000 +0000 +++ cpputest-3.7.2+dfsg/debian/copyright 2016-05-09 20:22:44.000000000 +0000 @@ -1,6 +1,10 @@ Format: http://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Source: http://sourceforge.net/projects/cpputest/files/ Upstream-Name: CppUTest +Files-Excluded: + platforms_startup + platforms_examples + platforms Files: * Copyright: 2007-2011, Michael Feathers, James Grenning and Bas Vodde diff -Nru cpputest-3.7.2/debian/watch cpputest-3.7.2+dfsg/debian/watch --- cpputest-3.7.2/debian/watch 2015-05-11 08:02:35.000000000 +0000 +++ cpputest-3.7.2+dfsg/debian/watch 2016-05-09 20:22:44.000000000 +0000 @@ -1,4 +1,4 @@ version=3 -opts=downloadurlmangle=s/$/?raw=true/ \ +opts=downloadurlmangle=s/$/?raw=true/,repacksuffix=+dfsg,dversionmangle=s/\+dfsg// \ https://github.com/cpputest/cpputest.github.io/tree/master/releases \ .*/releases/[Cc]pp[Uu][Tt]est-v?(\d[\d.]*)\.tar\.gz diff -Nru cpputest-3.7.2/platforms/armcc/Makefile cpputest-3.7.2+dfsg/platforms/armcc/Makefile --- cpputest-3.7.2/platforms/armcc/Makefile 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/armcc/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,195 +0,0 @@ -# We don't need to clean up when we're making these targets -NODEPS := clean debug - -# CPU architecture. Passing to armcc.exe. For list: armcc --cpu list -ifndef CPU - CPU = ARM7TDMI -endif - -# ARM/THUMB mode. Passing to armcc.exe. May be 'thumb' or 'arm' -ifndef CPU_MODE - CPU_MODE = thumb -endif - -# Path to cygwin binary -CYGWIN_DIR :=C:/CYGWIN/bin - -# Path to ARMCC of Keil MDK-ARM, with libraries, includes and executables -KEIL_DIR :=D:/Keil/ARM/ARMCC - -MKDIR :=$(CYGWIN_DIR)/mkdir -RM :=$(CYGWIN_DIR)/rm -CC :=@$(KEIL_DIR)/bin/armcc.exe -AR :=@$(KEIL_DIR)/bin/armar.exe - - -# source CppUTest files -CPPUTEST_HOME := ../.. -COMPONENT_NAME := CppUTest - -INCLUDE_DIRS :=\ - $(CPPUTEST_HOME)/include \ - $(CPPUTEST_HOME)/include/Platforms/armcc \ - -# armcc system include path -SYS_INCLUDE_DIRS:=$(KEIL_DIR)/include - -SRC_DIRS :=\ - $(CPPUTEST_HOME)/src/$(COMPONENT_NAME)\ - $(CPPUTEST_HOME)/src/Platforms/armcc\ - -TARGET_PLATFORM :=armcc_$(CPU)_$(CPU_MODE) -CPPUTEST_USE_MEM_LEAK_DETECTION := N -CPPUTEST_USE_STD_CPP_LIB := N -CPPUTEST_USE_VPATH := Y -CPPUTEST_USE_STD_C_LIB := Y -CPPUTEST_ENABLE_DEBUG := Y - - -# Default dir for temporary files (d, o) -# Default dir for the outout library -CPPUTEST_OBJS_DIR = objs -CPPUTEST_LIB_DIR = $(CPPUTEST_HOME)/lib/$(TARGET_PLATFORM) - -TARGET_LIB = \ - $(CPPUTEST_LIB_DIR)/lib$(COMPONENT_NAME).a - - -#Helper Functions -get_src_from_dir = $(wildcard $1/*.cpp) $(wildcard $1/*.cc) $(wildcard $1/*.c) -get_dirs_from_dirspec = $(wildcard $1) -get_src_from_dir_list = $(foreach dir, $1, $(call get_src_from_dir,$(dir))) -__src_to = $(subst .c,$1, $(subst .cc,$1, $(subst .cpp,$1,$(if $(CPPUTEST_USE_VPATH),$(notdir $2),$2)))) -src_to = $(addprefix $(CPPUTEST_OBJS_DIR)/,$(call __src_to,$1,$2)) -src_to_o = $(call src_to,.o,$1) -src_to_d = $(call src_to,.d,$1) -src_to_gcda = $(call src_to,.gcda,$1) -src_to_gcno = $(call src_to,.gcno,$1) -time = $(shell date +%s) -delta_t = $(eval minus, $1, $2) -debug_print_list = $(foreach word,$1,echo " $(word)";) echo; - -#Derived -SRC = $(call get_src_from_dir_list, $(SRC_DIRS)) -OBJ = $(call src_to_o,$(SRC)) - -STUFF_TO_CLEAN = $(OBJ) - -ALL_SRC = $(SRC) - -CPUFLAGS =--cpu=$(CPU) -ifeq ($(CPU_MODE), thumb) - CPUFLAGS +=--apcs=/interwork -endif -DEPFLAGS =$(CPUFLAGS) -M $(INCLUDES) --depend_format=unix_escaped --depend_single_line --no_depend_system_headers -OPTFLAGS =-O1 -CCFLAGS =$(CPUFLAGS) $(OPTFLAGS) -c $(INCLUDES)\ - --$(CPU_MODE)\ - --exceptions\ - -D__CLK_TCK=1000\ - - -# If we're using VPATH -ifeq ($(CPPUTEST_USE_VPATH), Y) -# gather all the source directories and add them - VPATH += $(sort $(dir $(ALL_SRC))) -# Add the component name to the objs dir path, to differentiate between same-name objects - CPPUTEST_OBJS_DIR := $(addsuffix /$(COMPONENT_NAME),$(CPPUTEST_OBJS_DIR)) -endif - -INCLUDES_DIRS_EXPANDED = $(call get_dirs_from_dirspec, $(INCLUDE_DIRS)) -INCLUDES += $(foreach dir, $(INCLUDES_DIRS_EXPANDED), -I$(dir)) - -DEP_FILES = $(call src_to_d, $(ALL_SRC)) -STUFF_TO_CLEAN += $(DEP_FILES) - - -# Without the C library, we'll need to disable the C++ library and ... -ifeq ($(CPPUTEST_USE_STD_C_LIB), N) - CPPUTEST_USE_STD_CPP_LIB = N - CPPUTEST_USE_MEM_LEAK_DETECTION = N - CCFLAGS += -DCPPUTEST_STD_C_LIB_DISABLED -else - INCLUDE_DIRS +=$(SYS_INCLUDE_DIRS) -endif - -ifeq ($(CPPUTEST_USE_MEM_LEAK_DETECTION), N) - CCFLAGS += -DCPPUTEST_MEM_LEAK_DETECTION_DISABLED -endif - -ifeq ($(CPPUTEST_ENABLE_DEBUG), Y) - CCFLAGS += -g - ARFLAGS := --debug_symbols -endif - -ifeq ($(CPPUTEST_USE_STD_CPP_LIB), N) - CCFLAGS += -DCPPUTEST_STD_CPP_LIB_DISABLED -endif - - -OBJS_DIRS :=$(sort $(dir $(STUFF_TO_CLEAN))) - -$(OBJS_DIRS) $(CPPUTEST_LIB_DIR): - @echo Updating directory $@ - $(MKDIR) -p $@ - - -#This is the rule for creating the dependency files -$(CPPUTEST_OBJS_DIR)/%.d: %.c Makefile | $(OBJS_DIRS) - @echo Compiling C file $< for dependency. Out file $@. - $(CC) $(DEPFLAGS) $< --depend=$@ --depend_target='$(patsubst %.d,%.o,$@)' - -$(CPPUTEST_OBJS_DIR)/%.d: %.cpp Makefile | $(OBJS_DIRS) - @echo Compiling C++ file $< for dependency. Out file $@. - $(CC) $(DEPFLAGS) $< --depend=$@ --depend_target='$(patsubst %.d,%.o,$@)' - -#This rule does the compilation C++ files -$(CPPUTEST_OBJS_DIR)/%.o: %.cpp $(CPPUTEST_OBJS_DIR)/%.d Makefile - @echo Compiling C++ file $<. Out file $@ - $(CC) $(CCFLAGS) $< -o $@ - -#This rule does the compilation C files -$(CPPUTEST_OBJS_DIR)/%.o: %.c $(CPPUTEST_OBJS_DIR)/%.d Makefile - @echo Compiling C file $<. Out file $@ - $(CC) $(CCFLAGS) $< -o $@ - - -$(TARGET_LIB): $(OBJ) | $(CPPUTEST_LIB_DIR) - @echo Archiving to $@ - $(AR) $(ARFLAGS) --create $@ $^ - - -.PHONY: all - -all: $(TARGET_LIB) - @echo Done! - - -.PHONY: debug -debug: - @echo - @echo "Target Source files:" - @$(call debug_print_list,$(SRC)) - @echo "Target Object files:" - @$(call debug_print_list,$(OBJ)) - @echo "All Input Dependency files:" - @$(call debug_print_list,$(DEP_FILES)) - @echo Stuff to clean: - @$(call debug_print_list,$(STUFF_TO_CLEAN)) - @echo Includes: - @$(call debug_print_list,$(INCLUDES)) - @echo Directories to create: - @$(call debug_print_list,$(OBJS_DIRS)) - @echo Directories of CppUTest object files: - @$(call debug_print_list,$(CPPUTEST_OBJS_DIR)) - @echo Flags: - @$(call debug_print_list,$(CCFLAGS)) - - -#Don't create dependencies when we're cleaning, for instance -ifeq (0, $(words $(findstring $(MAKECMDGOALS), $(NODEPS)))) - -include $(DEP_FILES) -endif - -clean: - @$(RM) -rf $(STUFF_TO_CLEAN) diff -Nru cpputest-3.7.2/platforms/armcc/README cpputest-3.7.2+dfsg/platforms/armcc/README --- cpputest-3.7.2/platforms/armcc/README 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/armcc/README 1970-01-01 00:00:00.000000000 +0000 @@ -1,69 +0,0 @@ -Makefile to build CppUTest library to run in hardware using ARM C/C++ compiler. - -Also it is possible to build CppUTestExt library using -"make all COMPONENT_NAME=CppUTestExt". - -All libraries is placed in lib directory of CppUTest home. - -Thumb mode is using. For ARM mode, you need to remove compiler key -"--apcs=/interwork" and change $(CPU_MODE) to arm. - -You need installed CYGWIN with make.exe, rm.exe, mkdir.exe and installed - Keil MDK-ARM. - -For compiling CppUTest library using ARMCC, please adjust Makefile: -1. # Path to cygwin binary - CYGWIN_DIR :=C:/CYGWIN/bin -2. # Path to ARMCC of Keil MDK-ARM, with libraries, includes and executables - KEIL_DIR :=D:/Keil/ARM/ARMCC -3. # source CppUTest files - CPPUTEST_HOME := ../.. -4. other options explained in $(CPPUTEST_HOME)/build/MakefileWorker.mk - CPPUTEST_USE_MEM_LEAK_DETECTION := Y - CPPUTEST_USE_STD_CPP_LIB := N - CPPUTEST_USE_VPATH := Y - CPPUTEST_USE_STD_C_LIB := Y - CPPUTEST_ENABLE_DEBUG := Y - -You may add additional options "CPU=xx" and "CPU_MODE=yy" -CPU is an option that passed to armcc.exe. It selects CPU. List of CPU is - available by executing 'armcc.exe --cpu list'. - Default CPU architecture is ARM7TDMI. - For armcc v5.02 build 28, CPU is one of the next: - ARM7EJ-S - ARM7TM - ARM7TDM - ARM7TDMI - ARM710T - ARM720T - ARM740T - ARM7TM-S - ARM7TDMI-S - ARM9TDMI - ARM920T - ARM922T - ARM940T - ARM9E-S - ARM9EJ-S - ARM926EJ-S - ARM946E-S - ARM966E-S - ARM968E-S - Cortex-M0 - Cortex-M0plus - SC000 - Cortex-M1 - Cortex-M1.os_extension - Cortex-M1.no_os_extension - Cortex-M3 - Cortex-M3-rev0 - SC300 - Cortex-M4 - Cortex-M4.fp - Cortex-R4 - Cortex-R4F - -CPU_MODE is one of 'arm', 'thumb'. - Default is thumb. - -Tested with Keil MDK-ARM Pro v4.60 diff -Nru cpputest-3.7.2/platforms/armcc/TODO cpputest-3.7.2+dfsg/platforms/armcc/TODO --- cpputest-3.7.2/platforms/armcc/TODO 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/armcc/TODO 1970-01-01 00:00:00.000000000 +0000 @@ -1,6 +0,0 @@ -I am not familiar with automake. - -There is need to change build libCppUTest.a for target platform from - makefile in current directory to automake in CppUTest root directory. - And keep in mind that I want to add gcc way, and the others may want to add - some instructions for different compilers and chips. diff -Nru cpputest-3.7.2/platforms/CCStudio/CppUTestExtRunAllTests1.pjt cpputest-3.7.2+dfsg/platforms/CCStudio/CppUTestExtRunAllTests1.pjt --- cpputest-3.7.2/platforms/CCStudio/CppUTestExtRunAllTests1.pjt 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/CCStudio/CppUTestExtRunAllTests1.pjt 1970-01-01 00:00:00.000000000 +0000 @@ -1,65 +0,0 @@ -; Code Composer Project File, Version 2.0 (do not modify or remove this line) - -[Project Settings] -ProjectDir="C:\data\00_Dev\05_CppUTest\cpputest\platforms\CCStudio\" -ProjectType=Executable -CPUFamily=TMS320C28XX -Tool="Compiler" -Tool="CustomBuilder" -Tool="DspBiosBuilder" -Tool="Linker" -Config="Debug" - -[Source Files] -Source="..\..\src\CppUTest\CommandLineArguments.cpp" -Source="..\..\src\CppUTest\CommandLineTestRunner.cpp" -Source="..\..\src\CppUTest\JUnitTestOutput.cpp" -Source="..\..\src\CppUTest\MemoryLeakDetector.cpp" -Source="..\..\src\CppUTest\MemoryLeakWarningPlugin.cpp" -Source="..\..\src\CppUTest\SimpleMutex.cpp" -Source="..\..\src\CppUTest\SimpleString.cpp" -Source="..\..\src\CppUTest\TestFailure.cpp" -Source="..\..\src\CppUTest\TestFilter.cpp" -Source="..\..\src\CppUTest\TestHarness_c.cpp" -Source="..\..\src\CppUTest\TestMemoryAllocator.cpp" -Source="..\..\src\CppUTest\TestOutput.cpp" -Source="..\..\src\CppUTest\TestPlugin.cpp" -Source="..\..\src\CppUTest\TestRegistry.cpp" -Source="..\..\src\CppUTest\TestResult.cpp" -Source="..\..\src\CppUTest\Utest.cpp" -Source="..\..\src\CppUTestExt\CodeMemoryReportFormatter.cpp" -Source="..\..\src\CppUTestExt\MemoryReportAllocator.cpp" -Source="..\..\src\CppUTestExt\MemoryReporterPlugin.cpp" -Source="..\..\src\CppUTestExt\MemoryReportFormatter.cpp" -Source="..\..\src\CppUTestExt\MockActualCall.cpp" -Source="..\..\src\CppUTestExt\MockExpectedCall.cpp" -Source="..\..\src\CppUTestExt\MockExpectedCallsList.cpp" -Source="..\..\src\CppUTestExt\MockFailure.cpp" -Source="..\..\src\CppUTestExt\MockNamedValue.cpp" -Source="..\..\src\CppUTestExt\MockSupport.cpp" -Source="..\..\src\CppUTestExt\MockSupport_c.cpp" -Source="..\..\src\CppUTestExt\MockSupportPlugin.cpp" -Source="..\..\src\CppUTestExt\OrderedTest.cpp" -Source="..\..\src\Platforms\C2000\UtestPlatform.cpp" -Source="..\..\tests\CppUTestExt\CodeMemoryReportFormatterTest.cpp" -Source="..\..\tests\CppUTestExt\GMockTest.cpp" -Source="..\..\tests\CppUTestExt\GTest1Test.cpp" -Source="..\..\tests\CppUTestExt\GTest2ConvertorTest.cpp" -Source="..\..\tests\CppUTestExt\MemoryReportAllocatorTest.cpp" -Source="..\..\tests\CppUTestExt\MemoryReporterPluginTest.cpp" -Source="..\..\tests\CppUTestExt\MemoryReportFormatterTest.cpp" -Source="..\..\tests\CppUTestExt\MockActualCallTest.cpp" -Source="..\..\tests\CppUTestExt\MockCheatSheetTest.cpp" -Source="..\..\tests\CppUTestExt\MockExpectedCallTest.cpp" -Source="..\..\tests\CppUTestExt\MockExpectedFunctionsListTest.cpp" -Source="..\..\tests\CppUTestExt\MockFailureTest.cpp" -Source="C:\CCStudio_v3.3\C2000\cgtools\lib\src\farmem_cpp.cpp" -Source="tests\CppUTestExt\AllTestsForTarget.cpp" -Source="sim28335.cmd" - -["Compiler" Settings: "Debug"] -Options=-g -rtti -pdsw225 -pden -pds1 -fr"$(Proj_dir)\Debug" -i"$(Proj_dir)\..\..\include" -i"$(Proj_dir)\..\..\include\CppUTestExt\CppUTestGMock" -i"$(Proj_dir)\..\..\tests" -d"_DEBUG" -d"LARGE_MODEL" -d"CPPUTEST_STD_CPP_LIB_DISABLED" -d"CPPUTEST_USE_MEM_LEAK_DETECTION" -d"CPPUTEST_USE_MALLOC_MACROS" -ml -v28 --preinclude="$(Proj_dir)\..\..\include\Platforms\c2000\stdint.h" - -["Linker" Settings: "Debug"] -Options=-a -c -farheap0x20000 -f0x0 -heap0x2000 -m".\Debug\CppUTestExtRunAllTests.map" -o".\Debug\CppUTestExtRunAllTests1.out" -stack0x4000 --disable_auto_rts -w -l"rts2800_ml.lib" - diff -Nru cpputest-3.7.2/platforms/CCStudio/CppUTestExtRunAllTests2.pjt cpputest-3.7.2+dfsg/platforms/CCStudio/CppUTestExtRunAllTests2.pjt --- cpputest-3.7.2/platforms/CCStudio/CppUTestExtRunAllTests2.pjt 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/CCStudio/CppUTestExtRunAllTests2.pjt 1970-01-01 00:00:00.000000000 +0000 @@ -1,59 +0,0 @@ -; Code Composer Project File, Version 2.0 (do not modify or remove this line) - -[Project Settings] -ProjectDir="C:\data\00_Dev\05_CppUTest\cpputest\platforms\CCStudio\" -ProjectType=Executable -CPUFamily=TMS320C28XX -Tool="Compiler" -Tool="CustomBuilder" -Tool="DspBiosBuilder" -Tool="Linker" -Config="Debug" - -[Source Files] -Source="..\..\src\CppUTest\CommandLineArguments.cpp" -Source="..\..\src\CppUTest\CommandLineTestRunner.cpp" -Source="..\..\src\CppUTest\JUnitTestOutput.cpp" -Source="..\..\src\CppUTest\MemoryLeakDetector.cpp" -Source="..\..\src\CppUTest\MemoryLeakWarningPlugin.cpp" -Source="..\..\src\CppUTest\SimpleMutex.cpp" -Source="..\..\src\CppUTest\SimpleString.cpp" -Source="..\..\src\CppUTest\TestFailure.cpp" -Source="..\..\src\CppUTest\TestFilter.cpp" -Source="..\..\src\CppUTest\TestHarness_c.cpp" -Source="..\..\src\CppUTest\TestMemoryAllocator.cpp" -Source="..\..\src\CppUTest\TestOutput.cpp" -Source="..\..\src\CppUTest\TestPlugin.cpp" -Source="..\..\src\CppUTest\TestRegistry.cpp" -Source="..\..\src\CppUTest\TestResult.cpp" -Source="..\..\src\CppUTest\Utest.cpp" -Source="..\..\src\CppUTestExt\CodeMemoryReportFormatter.cpp" -Source="..\..\src\CppUTestExt\MemoryReportAllocator.cpp" -Source="..\..\src\CppUTestExt\MemoryReporterPlugin.cpp" -Source="..\..\src\CppUTestExt\MemoryReportFormatter.cpp" -Source="..\..\src\CppUTestExt\MockActualCall.cpp" -Source="..\..\src\CppUTestExt\MockExpectedCall.cpp" -Source="..\..\src\CppUTestExt\MockExpectedCallsList.cpp" -Source="..\..\src\CppUTestExt\MockFailure.cpp" -Source="..\..\src\CppUTestExt\MockNamedValue.cpp" -Source="..\..\src\CppUTestExt\MockSupport.cpp" -Source="..\..\src\CppUTestExt\MockSupport_c.cpp" -Source="..\..\src\CppUTestExt\MockSupportPlugin.cpp" -Source="..\..\src\CppUTestExt\OrderedTest.cpp" -Source="..\..\src\Platforms\C2000\UtestPlatform.cpp" -Source="..\..\tests\CppUTestExt\MockFailureTest.cpp" -Source="..\..\tests\CppUTestExt\MockPluginTest.cpp" -Source="..\..\tests\CppUTestExt\MockSupport_cTest.cpp" -Source="..\..\tests\CppUTestExt\MockSupport_cTestCFile.c" -Source="..\..\tests\CppUTestExt\MockSupportTest.cpp" -Source="..\..\tests\CppUTestExt\OrderedTestTest.cpp" -Source="C:\CCStudio_v3.3\C2000\cgtools\lib\src\farmem_cpp.cpp" -Source="tests\CppUTestExt\AllTestsForTarget.cpp" -Source="sim28335.cmd" - -["Compiler" Settings: "Debug"] -Options=-g -rtti -pdsw225 -pden -pds1 -fr"$(Proj_dir)\Debug" -i"$(Proj_dir)\..\..\include" -i"$(Proj_dir)\..\..\include\CppUTestExt\CppUTestGMock" -i"$(Proj_dir)\..\..\tests" -d"_DEBUG" -d"LARGE_MODEL" -d"CPPUTEST_STD_CPP_LIB_DISABLED" -d"CPPUTEST_USE_MEM_LEAK_DETECTION" -d"CPPUTEST_USE_MALLOC_MACROS" -ml -v28 --preinclude="$(Proj_dir)\..\..\include\Platforms\c2000\stdint.h" - -["Linker" Settings: "Debug"] -Options=-a -c -farheap0x20000 -f0x0 -heap0x2000 -m".\Debug\CppUTestExtRunAllTests.map" -o".\Debug\CppUTestExtRunAllTests2.out" -stack0x4000 --disable_auto_rts -w -l"rts2800_ml.lib" - diff -Nru cpputest-3.7.2/platforms/CCStudio/CppUTest.pjt cpputest-3.7.2+dfsg/platforms/CCStudio/CppUTest.pjt --- cpputest-3.7.2/platforms/CCStudio/CppUTest.pjt 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/CCStudio/CppUTest.pjt 1970-01-01 00:00:00.000000000 +0000 @@ -1,50 +0,0 @@ -; Code Composer Project File, Version 2.0 (do not modify or remove this line) - -[Project Settings] -ProjectDir="C:\data\00_Dev\05_CppUTest\cpputest\platforms\CCStudio\" -ProjectType=Library -CPUFamily=TMS320C28XX -Tool="Archiver" -Tool="Compiler" -Tool="CustomBuilder" -Tool="DspBiosBuilder" -Config="Debug" - -[Source Files] -Source="..\..\src\CppUTest\CommandLineArguments.cpp" -Source="..\..\src\CppUTest\CommandLineTestRunner.cpp" -Source="..\..\src\CppUTest\JUnitTestOutput.cpp" -Source="..\..\src\CppUTest\MemoryLeakDetector.cpp" -Source="..\..\src\CppUTest\MemoryLeakWarningPlugin.cpp" -Source="..\..\src\CppUTest\SimpleMutex.cpp" -Source="..\..\src\CppUTest\SimpleString.cpp" -Source="..\..\src\CppUTest\TestFailure.cpp" -Source="..\..\src\CppUTest\TestFilter.cpp" -Source="..\..\src\CppUTest\TestHarness_c.cpp" -Source="..\..\src\CppUTest\TestMemoryAllocator.cpp" -Source="..\..\src\CppUTest\TestOutput.cpp" -Source="..\..\src\CppUTest\TestPlugin.cpp" -Source="..\..\src\CppUTest\TestRegistry.cpp" -Source="..\..\src\CppUTest\TestResult.cpp" -Source="..\..\src\CppUTest\Utest.cpp" -Source="..\..\src\CppUTestExt\CodeMemoryReportFormatter.cpp" -Source="..\..\src\CppUTestExt\MemoryReportAllocator.cpp" -Source="..\..\src\CppUTestExt\MemoryReporterPlugin.cpp" -Source="..\..\src\CppUTestExt\MemoryReportFormatter.cpp" -Source="..\..\src\CppUTestExt\MockActualCall.cpp" -Source="..\..\src\CppUTestExt\MockExpectedCall.cpp" -Source="..\..\src\CppUTestExt\MockExpectedCallsList.cpp" -Source="..\..\src\CppUTestExt\MockFailure.cpp" -Source="..\..\src\CppUTestExt\MockNamedValue.cpp" -Source="..\..\src\CppUTestExt\MockSupport.cpp" -Source="..\..\src\CppUTestExt\MockSupport_c.cpp" -Source="..\..\src\CppUTestExt\MockSupportPlugin.cpp" -Source="..\..\src\CppUTestExt\OrderedTest.cpp" -Source="..\..\src\Platforms\C2000\UtestPlatform.cpp" - -["Archiver" Settings: "Debug"] -Options=-r -o"..\..\lib\c2000\CppUTestd.lib" - -["Compiler" Settings: "Debug"] -Options=-g -rtti -pdsw225 -pden -pds1 -fr"$(Proj_dir)\Debug" -i"$(Proj_dir)\..\..\include" -d"_DEBUG" -d"LARGE_MODEL" -d"CPPUTEST_STD_CPP_LIB_DISABLED" -d"CPPUTEST_USE_MEM_LEAK_DETECTION" -ml -v28 - diff -Nru cpputest-3.7.2/platforms/CCStudio/CppUTestRunAllTests1.pjt cpputest-3.7.2+dfsg/platforms/CCStudio/CppUTestRunAllTests1.pjt --- cpputest-3.7.2/platforms/CCStudio/CppUTestRunAllTests1.pjt 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/CCStudio/CppUTestRunAllTests1.pjt 1970-01-01 00:00:00.000000000 +0000 @@ -1,54 +0,0 @@ -; Code Composer Project File, Version 2.0 (do not modify or remove this line) - -[Project Settings] -ProjectDir="C:\data\00_Dev\05_CppUTest\cpputest\platforms\CCStudio\" -ProjectType=Executable -CPUFamily=TMS320C28XX -Tool="Compiler" -Tool="CustomBuilder" -Tool="DspBiosBuilder" -Tool="Linker" -Config="Debug" - -[Source Files] -Source="..\..\src\CppUTest\CommandLineArguments.cpp" -Source="..\..\src\CppUTest\CommandLineTestRunner.cpp" -Source="..\..\src\CppUTest\JUnitTestOutput.cpp" -Source="..\..\src\CppUTest\MemoryLeakDetector.cpp" -Source="..\..\src\CppUTest\MemoryLeakWarningPlugin.cpp" -Source="..\..\src\CppUTest\SimpleMutex.cpp" -Source="..\..\src\CppUTest\SimpleString.cpp" -Source="..\..\src\CppUTest\TestFailure.cpp" -Source="..\..\src\CppUTest\TestFilter.cpp" -Source="..\..\src\CppUTest\TestHarness_c.cpp" -Source="..\..\src\CppUTest\TestMemoryAllocator.cpp" -Source="..\..\src\CppUTest\TestOutput.cpp" -Source="..\..\src\CppUTest\TestPlugin.cpp" -Source="..\..\src\CppUTest\TestRegistry.cpp" -Source="..\..\src\CppUTest\TestResult.cpp" -Source="..\..\src\CppUTest\Utest.cpp" -Source="..\..\src\Platforms\C2000\UtestPlatform.cpp" -Source="..\..\tests\AllocationInCFile.c" -Source="..\..\tests\AllocationInCppFile.cpp" -Source="..\..\tests\AllocLetTestFree.c" -Source="..\..\tests\AllocLetTestFreeTest.cpp" -Source="..\..\tests\CheatSheetTest.cpp" -Source="..\..\tests\CommandLineArgumentsTest.cpp" -Source="..\..\tests\CommandLineTestRunnerTest.cpp" -Source="..\..\tests\JUnitOutputTest.cpp" -Source="..\..\tests\MemoryLeakDetectorTest.cpp" -Source="..\..\tests\MemoryLeakOperatorOverloadsTest.cpp" -Source="..\..\tests\MemoryLeakWarningTest.cpp" -Source="..\..\tests\PluginTest.cpp" -Source="..\..\tests\PreprocessorTest.cpp" -Source="..\..\tests\SetPluginTest.cpp" -Source="C:\CCStudio_v3.3\C2000\cgtools\lib\src\farmem_cpp.cpp" -Source="tests\CppUTest\AllTestsForTarget.cpp" -Source="sim28335.cmd" - -["Compiler" Settings: "Debug"] -Options=-g -rtti -pdsw225 -pden -pds1 -fr"$(Proj_dir)\Debug" -i"$(Proj_dir)\..\..\include" -i"$(Proj_dir)\..\..\tests" -d"_DEBUG" -d"LARGE_MODEL" -d"CPPUTEST_STD_CPP_LIB_DISABLED" -d"CPPUTEST_USE_MEM_LEAK_DETECTION" -ml -v28 --preinclude="$(Proj_dir)\..\..\include\Platforms\c2000\stdint.h" - -["Linker" Settings: "Debug"] -Options=-a -c -farheap0x020000 -f0x0 -heap0x2000 -m".\Debug\CppUTestRunAllTests1.map" -o".\Debug\CppUTestRunAllTests1.out" -stack0x4000 --disable_auto_rts -w -l"rts2800_ml.lib" - diff -Nru cpputest-3.7.2/platforms/CCStudio/CppUTestRunAllTests2.pjt cpputest-3.7.2+dfsg/platforms/CCStudio/CppUTestRunAllTests2.pjt --- cpputest-3.7.2/platforms/CCStudio/CppUTestRunAllTests2.pjt 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/CCStudio/CppUTestRunAllTests2.pjt 1970-01-01 00:00:00.000000000 +0000 @@ -1,53 +0,0 @@ -; Code Composer Project File, Version 2.0 (do not modify or remove this line) - -[Project Settings] -ProjectDir="C:\data\00_Dev\05_CppUTest\cpputest\platforms\CCStudio\" -ProjectType=Executable -CPUFamily=TMS320C28XX -Tool="Compiler" -Tool="CustomBuilder" -Tool="DspBiosBuilder" -Tool="Linker" -Config="Debug" - -[Source Files] -Source="..\..\src\CppUTest\CommandLineArguments.cpp" -Source="..\..\src\CppUTest\CommandLineTestRunner.cpp" -Source="..\..\src\CppUTest\JUnitTestOutput.cpp" -Source="..\..\src\CppUTest\MemoryLeakDetector.cpp" -Source="..\..\src\CppUTest\MemoryLeakWarningPlugin.cpp" -Source="..\..\src\CppUTest\SimpleMutex.cpp" -Source="..\..\src\CppUTest\SimpleString.cpp" -Source="..\..\src\CppUTest\TestFailure.cpp" -Source="..\..\src\CppUTest\TestFilter.cpp" -Source="..\..\src\CppUTest\TestHarness_c.cpp" -Source="..\..\src\CppUTest\TestMemoryAllocator.cpp" -Source="..\..\src\CppUTest\TestOutput.cpp" -Source="..\..\src\CppUTest\TestPlugin.cpp" -Source="..\..\src\CppUTest\TestRegistry.cpp" -Source="..\..\src\CppUTest\TestResult.cpp" -Source="..\..\src\CppUTest\Utest.cpp" -Source="..\..\src\Platforms\C2000\UtestPlatform.cpp" -Source="..\..\tests\SimpleStringTest.cpp" -Source="..\..\tests\TestFailureNaNTest.cpp" -Source="..\..\tests\TestFailureTest.cpp" -Source="..\..\tests\TestFilterTest.cpp" -Source="..\..\tests\TestHarness_cTest.cpp" -Source="..\..\tests\TestHarness_cTestCFile.c" -Source="..\..\tests\TestInstallerTest.cpp" -Source="..\..\tests\TestMemoryAllocatorTest.cpp" -Source="..\..\tests\TestOutputTest.cpp" -Source="..\..\tests\TestRegistryTest.cpp" -Source="..\..\tests\TestResultTest.cpp" -Source="..\..\tests\TestUTestMacro.cpp" -Source="..\..\tests\UtestTest.cpp" -Source="C:\CCStudio_v3.3\C2000\cgtools\lib\src\farmem_cpp.cpp" -Source="tests\CppUTest\AllTestsForTarget.cpp" -Source="sim28335.cmd" - -["Compiler" Settings: "Debug"] -Options=-g -rtti -pdsw225 -pden -pds1 -fr"$(Proj_dir)\Debug" -i"$(Proj_dir)\..\..\include" -i"$(Proj_dir)\..\..\tests" -d"_DEBUG" -d"LARGE_MODEL" -d"CPPUTEST_STD_CPP_LIB_DISABLED" -d"CPPUTEST_USE_MEM_LEAK_DETECTION" -ml -v28 --preinclude="$(Proj_dir)\..\..\include\Platforms\c2000\stdint.h" - -["Linker" Settings: "Debug"] -Options=-a -c -farheap0x020000 -f0x0 -heap0x2000 -m".\Debug\CppUTestRunAllTests2.map" -o".\Debug\CppUTestRunAllTests2.out" -stack0x4000 --disable_auto_rts -w -l"rts2800_ml.lib" - Binary files /tmp/tmpb9zS_i/zecyhXFOU6/cpputest-3.7.2/platforms/CCStudio/CppUTest.wks and /tmp/tmpb9zS_i/pm1EURXLF1/cpputest-3.7.2+dfsg/platforms/CCStudio/CppUTest.wks differ diff -Nru cpputest-3.7.2/platforms/CCStudio/sim28335.cmd cpputest-3.7.2+dfsg/platforms/CCStudio/sim28335.cmd --- cpputest-3.7.2/platforms/CCStudio/sim28335.cmd 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/CCStudio/sim28335.cmd 1970-01-01 00:00:00.000000000 +0000 @@ -1,43 +0,0 @@ -/************************************************************/ -/* Linker command file for simulator only */ -/************************************************************/ - -/* Contains only the bare necessities for running a unit test - * in the TI CCS 3.3 Simulator - */ - -MEMORY -{ -PAGE 0 : /* Program Memory */ - - /* Flash as one big segment */ - FLASH : origin = 0x300000, length = 0x040000 - -PAGE 1 : /* Data Memory */ - - /* Internal SARAM */ - RAM_0 : origin = 0x000000, length = 0x002000 - /* 0x2000 to 0x3FFF: Not defined */ - STACK : origin = 0x004000, length = 0x004000 /* stack needs own segment in low RAM */ - RAM_1 : origin = 0x008000, length = 0x008000 - - /* External memory */ - EMEM : origin = 0x100000, length = 0x030000 -} - -SECTIONS -{ - /* segment allocation */ - .cinit : > FLASH, PAGE = 0 /* initialized internal RAM-data */ - .pinit : > FLASH, PAGE = 0 /* initialized constructors */ - .stack : > STACK, PAGE = 1 - .text : > FLASH, PAGE = 0 - .bss : > RAM_0, PAGE = 1 - .ebss : > RAM_1, FILL = 0x0020, PAGE = 1 /* uninitialized external RAM-data */ - .econst : > FLASH, PAGE = 0 - .esysmem : > EMEM, PAGE = 1 /* not used if no malloc calls in code */ - .cio : > RAM_0, PAGE = 1 - - /* keep the linker from complaining */ - .reset : > FLASH, PAGE = 0, TYPE = DSECT /* not used */ -} diff -Nru cpputest-3.7.2/platforms/CCStudio/sim28335.gel cpputest-3.7.2+dfsg/platforms/CCStudio/sim28335.gel --- cpputest-3.7.2/platforms/CCStudio/sim28335.gel 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/CCStudio/sim28335.gel 1970-01-01 00:00:00.000000000 +0000 @@ -1,247 +0,0 @@ -/********************************************************************/ -/* f28335.gel */ -/* Version 4.00.2 */ -/* */ -/* This GEL file is to be used with the TMS320F28335 DSP. */ -/* Changes may be required to support specific hardware designs. */ -/* */ -/* Code Composer Studio supports six reserved GEL functions that */ -/* automatically get executed if they are defined. They are: */ -/* */ -/* StartUp() - Executed whenever CCS is invoked */ -/* OnReset() - Executed after Debug->Reset CPU */ -/* OnRestart() - Executed after Debug->Restart */ -/* OnPreFileLoaded() - Executed before File->Load Program */ -/* OnFileLoaded() - Executed after File->Load Program */ -/* OnTargetConnect() - Executed after Debug->Connect */ -/* */ -/********************************************************************/ - -StartUp() -{ - /* The next line automatically loads the .gel file that comes */ - /* with the DSP2833x Peripheral Header Files download. To use, */ - /* uncomment, and copy the peripheral header .gel file to */ - /* same directory as device .gel file. */ - // GEL_LoadGel("$(GEL_file_dir)\\DSP2833x_Peripheral.gel"); -} - -OnReset(int nErrorCode) -{ - C28x_Mode(); - XINTF_Enable(); -} - -OnRestart(int nErrorCode) -{ -/* CCS will call OnRestart() when you do a Debug->Restart and */ -/* after you load a new file. Between running interrupt based */ -/* programs, this function will clear interrupts and help keep */ -/* the processor from going off into invalid memory. */ - C28x_Mode(); - IER = 0; - IFR = 0; -} - -OnPreFileLoaded() -{ - C28x_Mode(); - XINTF_Enable(); - GEL_Reset(); -} - -OnFileLoaded(int nErrorCode, int bSymbolsOnly) -{ -} - -OnTargetConnect() -{ - C28335_Memory_Map(); /* Initialize the CCS memory map */ - - /* Check to see if CCS has been started-up with the DSP already */ - /* running in real-time mode. The user can add whatever */ - /* custom initialization stuff they want to each case. */ - - if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */ - { - // Note: This case never executes with the simulator - } - else /* Do stop-mode target initialization */ - { - // Note: This case always executes with the simulator - } -} - - -/********************************************************************/ -/* F28335 Memory Map */ -/* */ -/* Note: M0M1MAP and VMAP signals tied high on F28335 core */ -/* */ -/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */ -/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */ -/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */ -/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */ -/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */ -/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */ -/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */ -/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */ -/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */ -/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */ -/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */ -/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */ -/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */ -/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */ -/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */ -/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */ -/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data */ -/* 0x300000 - 0x33ffff Flash (Prog and Data) */ -/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */ -/* 0x380090 - 0x380090 PARTID value (Prog and Data) */ -/* 0x380400 - 0x3807ff OTP (Prog and Data) */ -/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */ -/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */ -/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */ -/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */ -/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */ -/********************************************************************/ -menuitem "Initialize Memory Map"; - -hotmenu Memory_Map_Off() -{ - GEL_MapReset(); - GEL_MapOff(); -} - -hotmenu C28335_Memory_Map() -{ - GEL_MapReset(); - GEL_MapOn(); - - /* Program memory map */ - GEL_MapAdd(0x000,0,0x400,1,1); /* M0 SARAM */ - GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */ - GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */ - GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */ - GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */ - GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */ - GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */ - GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */ - GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */ - GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */ - GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */ - GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */ - GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */ - GEL_MapAdd(0x300000,0,0x40000,1,1); /* FLASH */ - GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/ - GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */ - GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */ - GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */ - GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */ - GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */ - GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */ - GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */ - - /* Data memory map */ - GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */ - GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */ - GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */ - GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */ - GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */ - GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */ - GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */ - GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */ - GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */ - GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */ - GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */ - GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */ - GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */ - GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */ - GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */ - GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */ - GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */ - GEL_MapAdd(0x300000,1,0x40000,1,0); /* FLASH */ - GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */ - GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/ - GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */ - GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */ - GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */ - GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */ - GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */ - GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */ -} - -/********************************************************************/ -menuitem "Addressing Modes"; - -hotmenu C28x_Mode() -{ - ST1 = ST1 & (~0x0100); /* AMODE = 0 */ - ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ -} - -hotmenu C24x_Mode() -{ - ST1 = ST1 | 0x0100; /* AMODE = 1 */ - ST1 = ST1 | 0x0200; /* OBJMODE = 1 */ -} - -hotmenu C27x_Mode() -{ - ST1 = ST1 & (~0x0100); /* AMODE = 0 */ - ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */ -} - -/********************************************************************/ -/* Enable the XINTF and configure GPIOs for XINTF function */ -/********************************************************************/ -int TxtOutCtl=0; -menuitem "XINTF Enable" -hotmenu XINTF_Enable() -{ - - if (TxtOutCtl==0) - { - GEL_TextOut("\nNOTES:\nTo configure the XINTF automatically on reset:\n uncomment the XINTF_Enable call in the OnReset function of the GEL file."); - GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use."); - TxtOutCtl=1; - } - - /* enable XINTF clock (XTIMCLK) */ - - *0x7020 = 0x3700; - /* GPBMUX1: XA0-XA7, XA16, XZCS0, */ - /* XZCS7, XREADY, XRNW, XWE0 */ - /* GPAMUX2: XA17-XA19, XZCS6 */ - /* GPCMUX2: XA8-XA15 */ - /* GPCMUX1: XD0-XD15 */ - *(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */ - *(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */ - *(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */ - *(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */ - - /* Uncomment for x32 data bus */ - /* GPBMUX2: XD16-XD31 */ -// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */ - - /* Zone timing. - /* Each zone can be configured seperately */ - /* Uncomment the x16 or the x32 timing */ - /* depending on the data bus width for */ - /* the zone */ - - /* x16 Timing */ - *(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */ - *(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */ - *(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */ - - /* x32 Timing: -// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */ -// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */ -// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */ - - -} - -/********************************************************************/ -/*** End of file ***/ diff -Nru cpputest-3.7.2/platforms/CCStudio/sim2833x.cfg cpputest-3.7.2+dfsg/platforms/CCStudio/sim2833x.cfg --- cpputest-3.7.2/platforms/CCStudio/sim2833x.cfg 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/CCStudio/sim2833x.cfg 1970-01-01 00:00:00.000000000 +0000 @@ -1,411 +0,0 @@ -/////////////////////////////////////////////////////////// -// Initialize default F2833x memory map as defined by // -// the MEMRSn signal. For F2833x, M0M1MAP=1 and VMAP=1. // -/////////////////////////////////////////////////////////// -module F2833x_memory; - -/////////////////////////////////////////////////////////// -// M0 SARAM, shared prog and data space // -/////////////////////////////////////////////////////////// -memory M0_prog_mem; - first 0x000000; - last 0x0003FF; - space prog; - waitstates 0; - type saram; - shared M0_data_mem; -end M0_prog_mem; - -memory M0_data_mem; - first 0x000000; - last 0x0003FF; - space data; - waitstates 0; - type saram; -end M0_data_mem; - -/////////////////////////////////////////////////////////// -// M1 SARAM, shared prog and data space // -/////////////////////////////////////////////////////////// -memory M1_prog_mem; - first 0x000400; - last 0x0007FF; - space prog; - waitstates 0; - type saram; - shared M1_data_mem; -end M1_prog_mem; - -memory M1_data_mem; - first 0x000400; - last 0x0007FF; - space data; - waitstates 0; - type saram; -end M1_data_mem; - -/////////////////////////////////////////////////////////// -// PF0A, data space only // -/////////////////////////////////////////////////////////// -memory PF0A_data_mem; - first 0x000800; - last 0x000CFF; - space data; - waitstates 1; - type saram; -end PF0A_data_mem; - -/////////////////////////////////////////////////////////// -// PIE Vector Table // -/////////////////////////////////////////////////////////// -memory PIE_vectors; - first 0x000D00; - last 0x000DFF; - space data; - waitstates 0; - type saram; -end PIE_vectors; - -/////////////////////////////////////////////////////////// -// PF0B, data space only // -/////////////////////////////////////////////////////////// -memory PF0B_data_mem; - first 0x000E00; - last 0x001FFF; - space data; - waitstates 1; - type saram; -end PF0B_data_mem; - -/////////////////////////////////////////////////////////// -// PF3, data space only // -/////////////////////////////////////////////////////////// -memory PF3_data_mem; - first 0x005000; - last 0x005FFF; - space data; - waitstates 2; - type saram; -end PF3_data_mem; - -////////////////////////////////////////////////////////// -// VBUS32 data space (PF1) // -// 0x6000 - 0x6FFF // -////////////////////////////////////////////////////////// -memory vbus32_data_mem; - read_waitstates 2; - write_waitstates 0; - type vbus32; -end vbus32_data_mem; - -////////////////////////////////////////////////////////// -// VBUS16 data space (PF2) // -// 0x7000 - 0x7FFF // -////////////////////////////////////////////////////////// -memory vbus16_data_mem; - read_waitstates 2; - write_waitstates 0; - type vbus16; -end vbus16_data_mem; - -////////////////////////////////////////////////////////// -// XINTF ZONE 0, shared prog and data space // -////////////////////////////////////////////////////////// -memory XINTF0_prog_mem; - first 0x004000; - last 0x004FFF; - space prog; - waitstates 7; - type saram; - shared XINTF0_data_mem; -end XINTF0_prog_mem; - -memory XINTF0_data_mem; - first 0x004000; - last 0x004FFF; - space data; - waitstates 7; - type saram; -end XINTF0_data_mem; - -////////////////////////////////////////////////////////// -// L0 SARAM, shared prog and data space // -////////////////////////////////////////////////////////// -memory L0_prog_mem; - first 0x008000; - last 0x008FFF; - space prog; - waitstates 0; - type saram; - shared L0_data_mem; -end L0_prog_mem; - -memory L0_data_mem; - first 0x008000; - last 0x008FFF; - space data; - waitstates 0; - type saram; -end L0_data_mem; - -////////////////////////////////////////////////////////// -// L1 SARAM, shared prog and data space // -////////////////////////////////////////////////////////// -memory L1_prog_mem; - first 0x009000; - last 0x009FFF; - space prog; - waitstates 0; - type saram; - shared L1_data_mem; -end L1_prog_mem; - -memory L1_data_mem; - first 0x009000; - last 0x009FFF; - space data; - waitstates 0; - type saram; -end L1_data_mem; - -////////////////////////////////////////////////////////// -// L2 SARAM, shared prog and data space // -////////////////////////////////////////////////////////// -memory L2_prog_mem; - first 0x00A000; - last 0x00AFFF; - space prog; - waitstates 0; - type saram; - shared L2_data_mem; -end L2_prog_mem; - -memory L2_data_mem; - first 0x00A000; - last 0x00AFFF; - space data; - waitstates 0; - type saram; -end L2_data_mem; - -////////////////////////////////////////////////////////// -// L3 SARAM, shared prog and data space // -////////////////////////////////////////////////////////// -memory L3_prog_mem; - first 0x00B000; - last 0x00BFFF; - space prog; - waitstates 0; - type saram; - shared L3_data_mem; -end L3_prog_mem; - -memory L3_data_mem; - first 0x00B000; - last 0x00BFFF; - space data; - waitstates 0; - type saram; -end L3_data_mem; - -////////////////////////////////////////////////////////// -// L4 SARAM, shared prog and data space // -////////////////////////////////////////////////////////// -memory L4_prog_mem; - first 0x00C000; - last 0x00CFFF; - space prog; - waitstates 0; - type saram; - shared L4_data_mem; -end L4_prog_mem; - -memory L4_data_mem; - first 0x00C000; - last 0x00CFFF; - space data; - waitstates 0; - type saram; -end L4_data_mem; - -////////////////////////////////////////////////////////// -// L5 SARAM, shared prog and data space // -////////////////////////////////////////////////////////// -memory L5_prog_mem; - first 0x00D000; - last 0x00DFFF; - space prog; - waitstates 0; - type saram; - shared L5_data_mem; -end L5_prog_mem; - -memory L5_data_mem; - first 0x00D000; - last 0x00DFFF; - space data; - waitstates 0; - type saram; -end L5_data_mem; - -////////////////////////////////////////////////////////// -// L6 SARAM, shared prog and data space // -////////////////////////////////////////////////////////// -memory L6_prog_mem; - first 0x00E000; - last 0x00EFFF; - space prog; - waitstates 1; - type saram; - shared L6_data_mem; -end L6_prog_mem; - -memory L6_data_mem; - first 0x00E000; - last 0x00EFFF; - space data; - waitstates 1; - type saram; -end L6_data_mem; - -////////////////////////////////////////////////////////// -// L7 SARAM, shared prog and data space // -////////////////////////////////////////////////////////// -memory L7_prog_mem; - first 0x00F000; - last 0x00FFFF; - space prog; - waitstates 1; - type saram; - shared L7_data_mem; -end L7_prog_mem; - -memory L7_data_mem; - first 0x00F000; - last 0x00FFFF; - space data; - waitstates 1; - type saram; -end L7_data_mem; - -////////////////////////////////////////////////////////// -// XINTF ZONE 6, shared prog and data space // -////////////////////////////////////////////////////////// -memory XINTF6_prog_mem; - first 0x100000; - last 0x1FFFFF; - space prog; - waitstates 7; - type saram; - shared XINTF6_data_mem; -end XINTF6_prog_mem; - -memory XINTF6_data_mem; - first 0x100000; - last 0x1FFFFF; - space data; - waitstates 7; - type saram; -end XINTF6_data_mem; - -////////////////////////////////////////////////////////// -// XINTF ZONE 7, shared prog and data space // -////////////////////////////////////////////////////////// -memory XINTF7_prog_mem; - first 0x200000; - last 0x2FFFFF; - space prog; - waitstates 7; - type saram; - shared XINTF7_data_mem; -end XINTF7_prog_mem; - -memory XINTF7_data_mem; - first 0x200000; - last 0x2FFFFF; - space data; - waitstates 7; - type saram; -end XINTF7_data_mem; - -////////////////////////////////////////////////////////// -// FLASH, shared prog and data space // -////////////////////////////////////////////////////////// -memory FLASH_prog_mem; - first 0x300000; - last 0x33FFF7; - space prog; - waitstates 5; - type flash; - shared FLASH_data_mem; -end FLASH_prog_mem; - -memory FLASH_data_mem; - first 0x300000; - last 0x33FFF7; - space data; - waitstates 5; - type flash; -end FLASH_data_mem; - -////////////////////////////////////////////////////////// -// PASSWORDS, shared prog and data space // -////////////////////////////////////////////////////////// -memory PASSWORDS_prog_mem; - first 0x33FFF8; - last 0x33FFFF; - space prog; - waitstates 16; - type flash; - shared PASSWORDS_data_mem; -end PASSWORDS_prog_mem; - -memory PASSWORDS_data_mem; - first 0x33FFF8; - last 0x33FFFF; - space data; - waitstates 16; - type flash; -end PASSWORDS_data_mem; - -////////////////////////////////////////////////////////// -// OTP, shared prog and data space // -////////////////////////////////////////////////////////// -memory OTP_prog_mem; - first 0x380400; - last 0x3807FF; - space prog; - waitstates 8; - type flash; - shared OTP_data_mem; -end OTP_prog_mem; - -memory OTP_data_mem; - first 0x380400; - last 0x3807FF; - space data; - waitstates 8; - type flash; -end OTP_data_mem; - -////////////////////////////////////////////////////////// -// BOOT ROM, shared prog and data space // -////////////////////////////////////////////////////////// -memory BOOT_prog_mem; - first 0x3FE000; - last 0x3FFFFF; - space prog; - waitstates 1; - type rom; - shared BOOT_data_mem; -end BOOT_prog_mem; - -memory BOOT_data_mem; - first 0x3FE000; - last 0x3FFFFF; - space data; - waitstates 1; - type rom; -end BOOT_data_mem; - -end F2833x_memory; diff -Nru cpputest-3.7.2/platforms/CCStudio/tests/CppUTest/AllTestsForTarget.cpp cpputest-3.7.2+dfsg/platforms/CCStudio/tests/CppUTest/AllTestsForTarget.cpp --- cpputest-3.7.2/platforms/CCStudio/tests/CppUTest/AllTestsForTarget.cpp 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/CCStudio/tests/CppUTest/AllTestsForTarget.cpp 1970-01-01 00:00:00.000000000 +0000 @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2013, Michael Feathers, James Grenning, Bas Vodde - * and Arnd Strube - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE EARLIER MENTIONED AUTHORS ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "CppUTest/CommandLineTestRunner.h" - -int main(int ac, char** av) -{ - /* Specify commandline arguments here as needed */ - char* argv[] = - { - (char*) 0, - (char*) "-v", -// (char*) "-gSimpleStringBuffer", -// (char*) "-ojunit", - }; - - ac = sizeof(argv) / sizeof(char*); - - /* These checks are here to make sure assertions outside test runs don't crash */ - CHECK(true); - LONGS_EQUAL(1, 1); - - return CommandLineTestRunner::RunAllTests(ac, argv); -} - diff -Nru cpputest-3.7.2/platforms/CCStudio/tests/CppUTestExt/AllTestsForTarget.cpp cpputest-3.7.2+dfsg/platforms/CCStudio/tests/CppUTestExt/AllTestsForTarget.cpp --- cpputest-3.7.2/platforms/CCStudio/tests/CppUTestExt/AllTestsForTarget.cpp 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/CCStudio/tests/CppUTestExt/AllTestsForTarget.cpp 1970-01-01 00:00:00.000000000 +0000 @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2013, Michael Feathers, James Grenning, Bas Vodde - * and Arnd Strube - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE EARLIER MENTIONED AUTHORS ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "CppUTest/CommandLineTestRunner.h" -#include "CppUTest/TestRegistry.h" -#include "CppUTestExt/MemoryReporterPlugin.h" -#include "CppUTestExt/MockSupportPlugin.h" - -int main(int ac, char** av) -{ - /* Specify commandline arguments here as needed */ - char* argv[] = - { - (char*) 0, - (char*) "-v", -// (char*) "-gSimpleStringBuffer", -// (char*) "-ojunit", - }; - - ac = sizeof(argv) / sizeof(char*); - - MemoryReporterPlugin plugin; - MockSupportPlugin mockPlugin; - TestRegistry::getCurrentRegistry()->installPlugin(&plugin); - TestRegistry::getCurrentRegistry()->installPlugin(&mockPlugin); - return CommandLineTestRunner::RunAllTests(ac, argv); -} - diff -Nru cpputest-3.7.2/platforms/Eclipse-Cygwin/CppUTestExtTests.launch cpputest-3.7.2+dfsg/platforms/Eclipse-Cygwin/CppUTestExtTests.launch --- cpputest-3.7.2/platforms/Eclipse-Cygwin/CppUTestExtTests.launch 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/Eclipse-Cygwin/CppUTestExtTests.launch 1970-01-01 00:00:00.000000000 +0000 @@ -1,22 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - diff -Nru cpputest-3.7.2/platforms/Eclipse-Cygwin/CppUTestTests.launch cpputest-3.7.2+dfsg/platforms/Eclipse-Cygwin/CppUTestTests.launch --- cpputest-3.7.2/platforms/Eclipse-Cygwin/CppUTestTests.launch 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/Eclipse-Cygwin/CppUTestTests.launch 1970-01-01 00:00:00.000000000 +0000 @@ -1,22 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - diff -Nru cpputest-3.7.2/platforms/Eclipse-Cygwin/.cproject cpputest-3.7.2+dfsg/platforms/Eclipse-Cygwin/.cproject --- cpputest-3.7.2/platforms/Eclipse-Cygwin/.cproject 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/Eclipse-Cygwin/.cproject 1970-01-01 00:00:00.000000000 +0000 @@ -1,234 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - make - extensions - true - true - true - - - make - - examples - true - true - true - - - make - - cleanExamples - true - true - true - - - - - - diff -Nru cpputest-3.7.2/platforms/Eclipse-Cygwin/.project cpputest-3.7.2+dfsg/platforms/Eclipse-Cygwin/.project --- cpputest-3.7.2/platforms/Eclipse-Cygwin/.project 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/Eclipse-Cygwin/.project 1970-01-01 00:00:00.000000000 +0000 @@ -1,2428 +0,0 @@ - - - CppUTest - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - .gitattributes - 1 - PARENT-2-ECLIPSE_HOME/00_Dev/05_CppUTest/cpputest/.gitattributes - - - .gitignore - 1 - PARENT-2-ECLIPSE_HOME/00_Dev/05_CppUTest/cpputest/.gitignore - - - .travis.yml - 1 - PARENT-2-ECLIPSE_HOME/00_Dev/05_CppUTest/cpputest/.travis.yml - - - .travis_github_deployer.yml - 1 - PARENT-2-ECLIPSE_HOME/00_Dev/05_CppUTest/cpputest/.travis_github_deployer.yml - - - AUTHORS - 1 - PARENT-2-ECLIPSE_HOME/00_Dev/05_CppUTest/cpputest/AUTHORS - - - CMakeLists.txt - 1 - PARENT-2-ECLIPSE_HOME/00_Dev/05_CppUTest/cpputest/CMakeLists.txt - - - COPYING - 1 - PARENT-2-ECLIPSE_HOME/00_Dev/05_CppUTest/cpputest/COPYING - - - ChangeLog - 1 - PARENT-2-ECLIPSE_HOME/00_Dev/05_CppUTest/cpputest/ChangeLog - - - CppUTest.dsw - 1 - PARENT-2-ECLIPSE_HOME/00_Dev/05_CppUTest/cpputest/CppUTest.dsw - - - CppUTest.vcproj - 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- - scripts/templates/ProjectTemplate/include/util/ProjectBuildTime.h - 1 - PARENT-2-ECLIPSE_HOME/00_Dev/05_CppUTest/cpputest/scripts/templates/ProjectTemplate/include/util/ProjectBuildTime.h - - - scripts/templates/ProjectTemplate/src/util/ProjectBuildTime.cpp - 1 - PARENT-2-ECLIPSE_HOME/00_Dev/05_CppUTest/cpputest/scripts/templates/ProjectTemplate/src/util/ProjectBuildTime.cpp - - - scripts/templates/ProjectTemplate/tests/util/ProjectBuildTimeTest.cpp - 1 - PARENT-2-ECLIPSE_HOME/00_Dev/05_CppUTest/cpputest/scripts/templates/ProjectTemplate/tests/util/ProjectBuildTimeTest.cpp - - - diff -Nru cpputest-3.7.2/platforms/Eclipse-Cygwin/README.md cpputest-3.7.2+dfsg/platforms/Eclipse-Cygwin/README.md --- cpputest-3.7.2/platforms/Eclipse-Cygwin/README.md 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms/Eclipse-Cygwin/README.md 1970-01-01 00:00:00.000000000 +0000 @@ -1,65 +0,0 @@ -##Using the Eclipse-Cygwin Project - -This project is for use on the Windows platform. These are the steps required for using it. (If you only wish to compile the CppUTest libraries, it is recommended that you use the method described at http://cpputest.github.io, rather than setting up Eclipse). - -###Preparation -####1. Install Cygwin -You need to have Cygwin installed, with at least the Gnu C\C++ compiler, make, autotools and libtool. Please follow the instructions at http://cpputest.github.io to build CppUTest from the Cygwin bash prompt. - -####2. Set your PATH -Next, you need to add the path to your Cygwin binaries to your Windows system path, e.g. -```dos -C:\\Cygwin\bin -``` - -####3. Install Eclipse CDT -Use your existing Eclipse CDT (Juno, Kepler, ...) or unpack the release to your system drive. You may use the 32 bit version as it will work on all systems. Unless you have a specific reason, you do not require the 64 bit version. You may need to install or update your Java JRE and add it to your system path. The JRE needs to match, e.g. 32 bit Eclipse requires the 32 bit JRE. - -####4. Install the C/C++Unit plugin -Open Eclipse. -Accept the default workspace for now (you may want to set a more appropriate workspace location later on). Then install the "C/C++ Unit Test" plugin: - "Help"->"Install New Software"-> work with "Kepler - http://download.eclipse.org/releases/kepler". - You will find the plugin under: -``` - [ ] Programming Languages - [x] C/C++ Unit Testing Support. -``` -While you are at it, you might also want to install: -``` - [ ] Linux Tools - [x] Gcov Integration -``` - -####5. Add the CppUTest plugin -Clone the [CppUTest Eclipse Test Runner](https://github.com/tcmak/CppUTestEclipseJunoTestRunner) and add it to Eclipse following the instructions there. - -###Import this project into Eclipse -In Eclipse you can't simply "open" a project - you have to first import it into the workspace: - * File->Import...->General->Existing Projects into workspace - * [Next >]->Select root directory: `/Platforms/Eclipse-Cygwin` - * Make sure that `[ ] Copy projects into workspace` is **NOT** ticked. - * Click Finish. - -###Compile and run tests -Before you can compile CppUTest in Eclipse, you must configure it using Automake. Instructions can be found at http://cpputest.github.io/. Once you have done this, select a configuration (Libraries, Check, CppUTestTests or CppUTestExtTests) via Project->BuildConfiguration->Set Active>. The 'Check' configuration will build the libraries along with all tests and run the tests. - -###Working with the C/C++ Unit plugin -Make sure your unit test executable has been built and exists, e.g. cpputest_build/CppUTestTests.exe. - -The first time you run tests using the plugin, you need to select them via -Run->Run Configurations...->C/C++Unit->CppUTestTest. -Click [Run]. (If Run is greyed out, you need to build the configuration CppUTestTests first) -Once you have run the tests at least once, you should be able to select them by clicking the down triangle next to the green "Run" icon, where it should be listed right at the top. On subsequent runs, the executable will be built automatically, if necessary. - -Note that launch configurations have been included with this project; in your own projects, you will need to create these yourself. - -This is an example of what a successful test run would look like: -![Successful Test Run](https://raw.githubusercontent.com/cpputest/cpputest.github.io/master/images/eclipse-testrunner-01.png) -You can select and rerun individual tests in the upper pane, and error messages for failed tests will appear in the lower pane. -###Troubleshooting -####Problem: I am getting no test results... -...but you know your tests should have run, and you did not receive any error message. -#####Possible Reason: -This can happen if the Cygwin-generated binary can't find the Cygwin DLLs. (If you were to run your test executable at the Windows cmd prompt, you would see a Windows error message box to that effect). Since no error message is displayed in the console via stderr, this leaves the test runner ignorant of what happenend -#####Solution: -You need to add /Cygwin/bin to your system PATH variable. Then you must restart Eclipse. Binary files /tmp/tmpb9zS_i/zecyhXFOU6/cpputest-3.7.2/platforms/IAR-STR912.zip and /tmp/tmpb9zS_i/pm1EURXLF1/cpputest-3.7.2+dfsg/platforms/IAR-STR912.zip differ diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/AT91SAM7A3.jflash cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/AT91SAM7A3.jflash --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/AT91SAM7A3.jflash 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/AT91SAM7A3.jflash 1970-01-01 00:00:00.000000000 +0000 @@ -1,247 +0,0 @@ - AppVersion = 47803 -[GENERAL] - ConnectMode = 0 - CurrentFile = "obj/tst.mot" - DataFileSAddr = 0x00000000 - GUIMode = 0 - HostName = "" - TargetIF = 0 - USBPort = 0 - USBSerialNo = 0x00000000 -[JTAG] - IRLen = 0 - MultipleTargets = 0 - NumDevices = 0 - Speed0 = 30 - Speed1 = 400 - TAP_Number = 0 - UseAdaptive0 = 0 - UseAdaptive1 = 0 - UseMaxSpeed0 = 0 - UseMaxSpeed1 = 1 -[CPU] - CheckCoreID = 1 - ChipName = "Atmel AT91SAM7A3" - ClockSpeed = 0x003D0900 - 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InitStep15_Comment = "" - InitStep15_Value0 = 0x00000000 - InitStep15_Value1 = 0x00000001 - InitStep16_Action = "Write 32bit" - InitStep16_Comment = "Unlock 3 region" - InitStep16_Value0 = 0xFFFFFF64 - InitStep16_Value1 = 0x5A003004 - InitStep17_Action = "Delay" - InitStep17_Comment = "" - InitStep17_Value0 = 0x00000000 - InitStep17_Value1 = 0x00000001 - InitStep18_Action = "Write 32bit" - InitStep18_Comment = "Unlock 4 region" - InitStep18_Value0 = 0xFFFFFF64 - InitStep18_Value1 = 0x5A004004 - InitStep19_Action = "Delay" - InitStep19_Comment = "" - InitStep19_Value0 = 0x00000000 - InitStep19_Value1 = 0x00000001 - InitStep1_Action = "Reset" - InitStep1_Comment = "" - InitStep1_Value0 = 0x00000000 - InitStep1_Value1 = 0x00000000 - InitStep20_Action = "Write 32bit" - InitStep20_Comment = "Unlock 5 region" - InitStep20_Value0 = 0xFFFFFF64 - InitStep20_Value1 = 0x5A005004 - InitStep21_Action = "Delay" - InitStep21_Comment = "" - InitStep21_Value0 = 0x00000000 - InitStep21_Value1 = 0x00000001 - InitStep22_Action = "Write 32bit" - InitStep22_Comment = "Unlock 6 region" - InitStep22_Value0 = 0xFFFFFF64 - InitStep22_Value1 = 0x5A006004 - InitStep23_Action = "Delay" - InitStep23_Comment = "" - InitStep23_Value0 = 0x00000000 - InitStep23_Value1 = 0x00000001 - InitStep24_Action = "Write 32bit" - InitStep24_Comment = "Unlock 7 region" - InitStep24_Value0 = 0xFFFFFF64 - InitStep24_Value1 = 0x5A007004 - InitStep25_Action = "Delay" - InitStep25_Comment = "" - InitStep25_Value0 = 0x00000000 - InitStep25_Value1 = 0x00000001 - InitStep26_Action = "Write 32bit" - InitStep26_Comment = "Unlock 8 region" - InitStep26_Value0 = 0xFFFFFF64 - InitStep26_Value1 = 0x5A008004 - InitStep27_Action = "Delay" - InitStep27_Comment = "" - InitStep27_Value0 = 0x00000000 - InitStep27_Value1 = 0x00000001 - InitStep28_Action = "Write 32bit" - InitStep28_Comment = "Unlock 9 region" - InitStep28_Value0 = 0xFFFFFF64 - InitStep28_Value1 = 0x5A009004 - InitStep29_Action = "Delay" - InitStep29_Comment = "" - InitStep29_Value0 = 0x00000000 - InitStep29_Value1 = 0x00000001 - InitStep2_Action = "Delay" - InitStep2_Comment = "" - InitStep2_Value0 = 0x00000000 - InitStep2_Value1 = 0x00000002 - InitStep30_Action = "Write 32bit" - InitStep30_Comment = "Unlock 10 region" - InitStep30_Value0 = 0xFFFFFF64 - InitStep30_Value1 = 0x5A00A004 - InitStep31_Action = "Delay" - InitStep31_Comment = "" - InitStep31_Value0 = 0x00000000 - InitStep31_Value1 = 0x00000001 - InitStep32_Action = "Write 32bit" - InitStep32_Comment = "Unlock 11 region" - InitStep32_Value0 = 0xFFFFFF64 - InitStep32_Value1 = 0x5A00B004 - InitStep33_Action = "Delay" - InitStep33_Comment = "" - InitStep33_Value0 = 0x00000000 - InitStep33_Value1 = 0x00000001 - InitStep34_Action = "Write 32bit" - InitStep34_Comment = "Unlock 12 region" - InitStep34_Value0 = 0xFFFFFF64 - InitStep34_Value1 = 0x5A00C004 - InitStep35_Action = "Delay" - InitStep35_Comment = "" - InitStep35_Value0 = 0x00000000 - InitStep35_Value1 = 0x00000001 - InitStep36_Action = "Write 32bit" - InitStep36_Comment = "Unlock 13 region" - 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InitStep5_Comment = "" - InitStep5_Value0 = 0x00000000 - InitStep5_Value1 = 0x00000002 - InitStep6_Action = "Write 32bit" - InitStep6_Comment = "Set PLL and divider" - InitStep6_Value0 = 0xFFFFFC2C - InitStep6_Value1 = 0x00C79E04 - InitStep7_Action = "Write 32bit" - InitStep7_Comment = "4MHz" - InitStep7_Value0 = 0xFFFFFC30 - InitStep7_Value1 = 0x00000001 - InitStep8_Action = "Delay" - InitStep8_Comment = "" - InitStep8_Value0 = 0x00000000 - InitStep8_Value1 = 0x00000002 - InitStep9_Action = "Write 32bit" - InitStep9_Comment = "Set WS = 2 (for write), FCN = 6 for 4 MHz" - InitStep9_Value0 = 0xFFFFFF60 - InitStep9_Value1 = 0x00060000 - NumExitSteps = 0 - NumInitSteps = 42 - RAMAddr = 0x00200000 - RAMSize = 0x00004000 - ScriptFile = "" - UseAutoSpeed = 0x00000001 - UseRAM = 1 - UseScriptFile = 0 -[FLASH] - aSectorSel[1024] = 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 - AutoDetect = 0 - BankName = "" - BankSelMode = 0 - BaseAddr = 0x00100000 - CheckId = 0 - CustomRAMCode = "" - DeviceName = "AT91SAM7A3 internal" - EndBank = 1023 - NumBanks = 1 - OrgNumBits = 32 - OrgNumChips = 1 - StartBank = 0 - UseCustomRAMCode = 0 -[PRODUCTION] - AutoPerformsErase = 1 - AutoPerformsHardLock = 0 - AutoPerformsHardUnlock = 0 - AutoPerformsProgram = 1 - AutoPerformsSecure = 0 - AutoPerformsSoftLock = 0 - AutoPerformsSoftUnlock = 1 - AutoPerformsStartApp = 1 - AutoPerformsUnsecure = 0 - AutoPerformsVerify = 1 - EnableProductionMode = 0 - EnableTargetPower = 1 - EraseType = 1 - ProductionDelay = 0x000001F4 - ProductionThreshold = 0x00000BB8 - ProgramSN = 0 - SerialFile = "" - SNAddr = 0x00000000 - SNInc = 0x00000001 - SNLen = 0x00000008 - SNListFile = "" - SNValue = 0x00000001 - TargetPowerDelay = 0x00000014 - VerifyType = 2 diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/AT91SAM7A3.launch cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/AT91SAM7A3.launch --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/AT91SAM7A3.launch 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/AT91SAM7A3.launch 1970-01-01 00:00:00.000000000 +0000 @@ -1,58 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/.cproject cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/.cproject --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/.cproject 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/.cproject 1970-01-01 00:00:00.000000000 +0000 @@ -1,74 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/HEAP.txt cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/HEAP.txt --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/HEAP.txt 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/HEAP.txt 1970-01-01 00:00:00.000000000 +0000 @@ -1,4 +0,0 @@ -Heap usage for initialization of std::cout is about 1496 bytes. -Additional heap usage for std::cout << (double) is about 644 bytes. - -All heap usage for CRT + cpp + sample tests is about 10624 bytes. \ No newline at end of file diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/jlink_gdb.cmd cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/jlink_gdb.cmd --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/jlink_gdb.cmd 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/jlink_gdb.cmd 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -start "JLink GDB Server" "C:\Program Files (x86)\SEGGER\JLink_V490b\JLinkGDBServerCL.exe" -device AT91SAM7A3 diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/LICENSE cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/LICENSE --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/LICENSE 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/LICENSE 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -No any additional license is used except standard Keil MDK-ARM license. - -If you use Keil MDK-ARM or ARM C/C++ then you agreed with terms of -Keil MDK-ARM license. - diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/Makefile cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/Makefile --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/Makefile 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,321 +0,0 @@ -.SILENT: - -#We don't need to clean up when we're making these targets -NODEPS = clean - -# CPU architecture. Passing to armcc.exe. For list: armcc --cpu list -ifndef CPU - CPU = ARM7TDMI -endif - -# ARM/THUMB mode. Passing to armcc.exe. May be 'thumb' or 'arm' -ifndef CPU_MODE - CPU_MODE = thumb -endif - -TARGET_PLATFORM =armcc_$(CPU)_$(CPU_MODE) - -# Need to use only relative path! Path with logical letters does not working. -CPPUTEST_HOME = ../../.. - -COMPONENT_NAME = app - -CPPUTEST_OBJS_DIR = objs - -# directory for appication library -CPPUTEST_LIB_DIR = lib - -CPPUTEST_USE_MEM_LEAK_DETECTION = N -CPPUTEST_USE_STD_CPP_LIB = Y -CPPUTEST_USE_VPATH = Y -CPPUTEST_USE_STD_C_LIB = Y -CPPUTEST_ENABLE_DEBUG = Y -CPPUTEST_USE_EXTENSIONS = N - -SRC_DIRS = \ - -SRC_FILES = $(CPPUTEST_HOME)/examples/ApplicationLib/CircularBuffer.cpp \ - $(CPPUTEST_HOME)/examples/ApplicationLib/Printer.cpp - -TEST_SRC_DIRS = \ - tests \ - -TEST_FILES = $(CPPUTEST_HOME)/examples/AllTests/CircularBufferTest.cpp - - -# directory with CppUTest and startup libraries -CPPUTEST_LIB_LINK_DIR = $(CPPUTEST_HOME)/lib/$(TARGET_PLATFORM) - -INCLUDE_DIRS = \ - $(CPPUTEST_HOME)/include \ - $(SRC_DIRS) \ - $(CPPUTEST_HOME)/examples/ApplicationLib \ - -# name of extension of output file. Default Keil MDK-ARM extension is .axf which is elf format -# .axf will be .elf for eclipse debug -OUTFILE_EXT = elf - -# output filename, mapfile (.map), hexfile (.mot) -OUTNAME = $(COMPONENT_NAME) -OUTFILE = $(OUTNAME).$(OUTFILE_EXT) -HEXFILE = $(OUTNAME).mot -MAPFILE = $(OUTNAME).map - -# CYGWIN path -CYGWIN =C:/CYGWIN/bin -MKDIR =$(CYGWIN)/mkdir -RM =$(CYGWIN)/rm -TOUCH =$(CYGWIN)/touch -ECHO =$(CYGWIN)/echo - -KEIL_DIR=D:/Keil/ARM/ARMCC -CC=$(KEIL_DIR)/bin/armcc.exe -AS=$(KEIL_DIR)/bin/armasm.exe -AR=$(KEIL_DIR)/bin/armar.exe -LD=$(KEIL_DIR)/bin/armlink.exe -FROMELF=$(KEIL_DIR)/bin/fromelf.exe -# armcc system include path -SYS_INCLUDE_DIRS =$(KEIL_DIR)/include - -JFLASH ="C:/Program Files (x86)/SEGGER/JLink_V490b/JFlash.exe" -JFLASHPRJ =AT91SAM7A3.jflash -LDSCRIPT = ROM.sct - -CPUFLAGS =--cpu=$(CPU) -ifeq ($(CPU_MODE), thumb) - CPUFLAGS +=--apcs=/interwork -endif -DEPFLAGS =-M \ - $(INCLUDES) \ - --depend_format=unix_escaped \ - --depend_single_line \ - --no_depend_system_headers - -OPTFLAGS =-O3 - -CPPUTEST_CPPFLAGS =$(CPUFLAGS) \ - $(OPTFLAGS) \ - -c \ - -g \ - $(INCLUDES) \ - --$(CPU_MODE) \ - --exceptions \ - -D__CLK_TCK=1000 \ - -CPPUTEST_LDFLAGS =$(CPUFLAGS) \ - --strict \ - --entry=Reset_Handler \ - --summary_stderr \ - --map \ - --callgraph \ - --info=summarysizes \ - --info=sizes \ - --info=totals \ - --info=veneers\ - --load_addr_map_info \ - --library_type=standardlib \ - --remove \ - --debug \ - -ARFLAGS = --debug_symbols - - -# new and delete for memory leak detection on by default -ifndef CPPUTEST_USE_MEM_LEAK_DETECTION - CPPUTEST_USE_MEM_LEAK_DETECTION = Y -endif - -# Use the standard C library -ifndef CPPUTEST_USE_STD_C_LIB - CPPUTEST_USE_STD_C_LIB = Y -endif - -# Use the standard C++ library -ifndef CPPUTEST_USE_STD_CPP_LIB - CPPUTEST_USE_STD_CPP_LIB = Y -endif - -# No extentions is default -ifndef CPPUTEST_USE_EXTENSIONS - CPPUTEST_USE_EXTENSIONS = N -endif - -# No VPATH is default -ifndef CPPUTEST_USE_VPATH - CPPUTEST_USE_VPATH = N -endif -# Make empty, instead of 'N', for usage in $(if ) conditionals -ifneq ($(CPPUTEST_USE_VPATH), Y) - CPPUTEST_USE_VPATH = -endif - -# Without the C library, we'll need to disable the C++ library and ... -ifeq ($(CPPUTEST_USE_STD_C_LIB), N) - CPPUTEST_USE_STD_CPP_LIB = N - CPPUTEST_USE_MEM_LEAK_DETECTION = N - CPPUTEST_CPPFLAGS += -DCPPUTEST_STD_C_LIB_DISABLED - CPPUTEST_LDFLAGS +=--no_scanlib -else - INCLUDE_DIRS +=$(SYS_INCLUDE_DIRS) -endif - - -ifeq ($(CPPUTEST_USE_MEM_LEAK_DETECTION), N) - CPPUTEST_CPPFLAGS += -DCPPUTEST_MEM_LEAK_DETECTION_DISABLED -else - ifndef CPPUTEST_MEMLEAK_DETECTOR_NEW_MACRO_FILE - CPPUTEST_MEMLEAK_DETECTOR_NEW_MACRO_FILE = -include $(CPPUTEST_HOME)/include/CppUTest/MemoryLeakDetectorNewMacros.h - endif - ifndef CPPUTEST_MEMLEAK_DETECTOR_MALLOC_MACRO_FILE - CPPUTEST_MEMLEAK_DETECTOR_MALLOC_MACRO_FILE = -include $(CPPUTEST_HOME)/include/CppUTest/MemoryLeakDetectorMallocMacros.h - endif -endif - - -ifeq ($(CPPUTEST_USE_STD_CPP_LIB), N) - CPPUTEST_CPPFLAGS += -DCPPUTEST_STD_CPP_LIB_DISABLED -endif - -# Link with CppUTest lib -CPPUTEST_LIB = $(CPPUTEST_LIB_LINK_DIR)/libCppUTest.a - -# Link with startup lib -CPPUTEST_LIB += $(CPPUTEST_LIB_LINK_DIR)/libStartup_AT91SAM7A3.a - -# Link with CppUTestExt lib -ifeq ($(CPPUTEST_USE_EXTENSIONS), Y) -CPPUTEST_LIB += $(CPPUTEST_LIB_LINK_DIR)/libCppUTestExt.a -endif - -TARGET_LIB = \ - $(CPPUTEST_LIB_DIR)/lib$(COMPONENT_NAME).a - -ifndef TEST_TARGET - ifndef TARGET_PLATFORM - TEST_TARGET = $(COMPONENT_NAME)_tests - else - TEST_TARGET = $(COMPONENT_NAME)_$(TARGET_PLATFORM)_tests - endif -endif - -#Helper Functions -get_src_from_dir = $(wildcard $1/*.cpp) $(wildcard $1/*.cc) $(wildcard $1/*.c) $(wildcard $1/*.asm) -get_src_from_dir_list = $(foreach dir, $1, $(call get_src_from_dir,$(dir))) -__src_to = $(subst .c,$1, $(subst .cc,$1, $(subst .cpp,$1, $(if $(CPPUTEST_USE_VPATH),$(notdir $2),$2)))) -src_to = $(addprefix $3/,$(call __src_to,$1,$2)) -src_to_o = $(call src_to,.o,$1,$2) -src_to_d = $(call src_to,.d,$1,$2) -time = $(shell date +%s) -delta_t = $(eval minus, $1, $2) -debug_print_list = $(foreach word,$1,echo " $(word)";) echo - -# исходники программных модулей -SRC = $(call get_src_from_dir_list, $(SRC_DIRS)) $(SRC_FILES) -OBJ = $(call src_to_o,$(SRC),$(CPPUTEST_OBJS_DIR)) -# исходники тестов -TEST_SRC = $(call get_src_from_dir_list, $(TEST_SRC_DIRS)) $(TEST_FILES) -TEST_OBJ = $(call src_to_o,$(TEST_SRC),$(CPPUTEST_OBJS_DIR)) - -# If we're using VPATH -ALL_SRC = $(SRC) $(TEST_SRC) -ifeq ($(CPPUTEST_USE_VPATH), Y) -# gather all the source directories and add them - VPATH += $(sort $(dir $(ALL_SRC))) -# Add the component name to the objs dir path, to differentiate between same-name objects - CPPUTEST_OBJS_DIR := $(addsuffix /$(COMPONENT_NAME),$(CPPUTEST_OBJS_DIR)) -endif - -# for building application library -INCLUDES += $(foreach dir, $(INCLUDE_DIRS), -I$(dir)) -DEP_FILES = $(call src_to_d, $(SRC), $(CPPUTEST_OBJS_DIR)) -DEP_TEST_FILES = $(call src_to_d, $(TEST_SRC), $(CPPUTEST_OBJS_DIR)) -STUFF_TO_CLEAN = $(OBJ) $(TEST_OBJ) $(DEP_FILES) $(DEP_TEST_FILES) $(TARGET_LIB) - -#Don't create CRT dependencies when we're cleaning, for instance -ifeq (0, $(words $(findstring $(MAKECMDGOALS), $(NODEPS)))) - -include $(DEP_FILES) -endif - -STUFF_TO_CLEAN += $(OUTFILE) $(MAPFILE) - - -all: $(CPPUTEST_OBJS_DIR)/$(OUTFILE) - echo Done! - -$(TARGET_LIB): $(OBJ) | $(CPPUTEST_LIB_DIR) - echo Building application library $@ - $(AR) $(ARFLAGS) --create $@ $^ - -$(CPPUTEST_OBJS_DIR)/$(OUTFILE): $(TEST_OBJ) $(CPPUTEST_LIB) $(TARGET_LIB) | ROM.sct Makefile - echo Linking! - $(LD) $(CPPUTEST_LDFLAGS) $^ --scatter $(LDSCRIPT) --list $(MAPFILE) -o $@ - - -.PHONY: prog -prog: $(CPPUTEST_OBJS_DIR)/$(HEXFILE) - $(JFLASH) -openprj$(JFLASHPRJ) -open$< -auto -exit - -$(CPPUTEST_OBJS_DIR)/$(HEXFILE): $(CPPUTEST_OBJS_DIR)/$(OUTFILE) - echo Converting to Motorola S19 - $(FROMELF) --m32 --output=$@ $< - -debug: - echo - echo "Target Source files:" - $(call debug_print_list,$(SRC)) - echo "Target Object files:" - $(call debug_print_list,$(OBJ)) - echo "All Input Dependency files:" - $(call debug_print_list,$(DEP_FILES)) - echo Stuff to clean: - $(call debug_print_list,$(STUFF_TO_CLEAN)) - echo Includes: - $(call debug_print_list,$(INCLUDES)) - echo Directories to create: - $(call debug_print_list,$(OBJS_DIRS)) - echo Directories of CppUTest object files: - $(call debug_print_list,$(OBJS_DIR)) - -#Don't create dependencies when we're cleaning, for instance -ifeq (0, $(words $(findstring $(MAKECMDGOALS), $(NODEPS)))) - -include $(DEP_FILES) -endif - -OBJS_DIRS =$(sort $(dir $(STUFF_TO_CLEAN))) - -$(LIB_DIR) $(OBJS_DIRS): - echo Updating directory $@ - $(MKDIR) -p $@ - -#This is the rule for creating the dependency files -$(CPPUTEST_OBJS_DIR)/%.d: %.c Makefile | $(OBJS_DIRS) - echo Compiling C file $< for dependency. Out file $@. - $(CC) $(DEPFLAGS) $< --depend=$@ --depend_target='$(patsubst %.d,%.o,$@)' - -$(CPPUTEST_OBJS_DIR)/%.d: %.cpp Makefile | $(OBJS_DIRS) - echo Compiling C++ file $< for dependency. Out file $@. - $(CC) $(DEPFLAGS) $< --depend=$@ --depend_target='$(patsubst %.d,%.o,$@)' - -$(CPPUTEST_OBJS_DIR)/%.d: %.cc Makefile | $(OBJS_DIRS) - echo Compiling CC++ file $< for dependency. Out file $@. - $(CC) $(DEPFLAGS) $< --depend=$@ --depend_target='$(patsubst %.d,%.o,$@)' - -#This rule does the compilation C++ files -$(CPPUTEST_OBJS_DIR)/%.o: %.cpp $(CPPUTEST_OBJS_DIR)/%.d - echo Compiling C++ file $<. Out file $@ - $(CC) $(CPPUTEST_CPPFLAGS) $< -o $@ - -#This rule does the compilation CC++ files -$(CPPUTEST_OBJS_DIR)/%.o: %.cc $(CPPUTEST_OBJS_DIR)/%.d - echo Compiling CC++ file $<. Out file $@ - $(CC) $(CPPUTEST_CPPFLAGS) $< -o $@ - -#This rule does the compilation C files -$(CPPUTEST_OBJS_DIR)/%.o: %.c $(CPPUTEST_OBJS_DIR)/%.d - echo Compiling C file $<. Out file $@ - $(CC) $(CPPUTEST_CPPFLAGS) $< -o $@ - -clean: - $(RM) -f $(STUFF_TO_CLEAN) - - diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/.project cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/.project --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/.project 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/.project 1970-01-01 00:00:00.000000000 +0000 @@ -1,26 +0,0 @@ - - - CppUTest AT91SAM7A3 sample project - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - org.eclipse.cdt.core.ccnature - - diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/RAM.txt cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/RAM.txt --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/RAM.txt 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/RAM.txt 1970-01-01 00:00:00.000000000 +0000 @@ -1,7 +0,0 @@ -bss memory usage for std::cout is about 12248 bytes - -Library cpp_ts(ios.o) needs two big regions of 7472 and 4104 bytes and other - small regions. - -More than 8k needed for statically created arrays with size - SetPointerPlugin::MAX_SET diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/README cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/README --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/README 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/README 1970-01-01 00:00:00.000000000 +0000 @@ -1,55 +0,0 @@ -Sample project to test CppUTest for Keil MDK-ARM toolchain and AT91SAM7A3 chip. - -Requirements: -1. CYGWIN (rm.exe, mkdir.exe, make.exe) - -2. Keil MDK-ARM - -3. JLink Flash (for programming chip) - -4. serial connection to DBGU interface - -5. 4 MHz quartz. If else, need to be adjusted in - $(CPPUTEST_HOME)/platforms_startup/armcc/AT91SAM7A3/SAM7A3.asm - (for setup PLL and change core clock from IRC to PLL) - and - $(CPPUTEST_HOME)/platforms_startup/armcc/AT91SAM7A3/Retarget.c - (for _clock_init() function working correctly) - -6. eclipse + gdb server from JLink + arm-none-eabi-gdb from GNU ARM Tools Embedded - For debug only. - -First, you need to compile CppUTest and target startup library: - make -C ../../../platforms/armcc - make -C ../../../platforms_startup/armcc/AT91SAM7A3 - -Second, you need to write tests. As example, I use - $(CPPUTEST_HOME)/examples/AllTests/CircularBufferTest.cpp. - All test from $(CPPUTEST_HOME)/examples/AllTests/ needs to many - RAM (chip does not have such). - -Third, you need to make executable: - make all - -Fourth, you need to program executable on target chip: - make prog - -Project use semihosting, so you may use standard printf() or std::cout << "Hello!" - -If problems with heap or low memory, adjust heap size in - $(CPPUTEST_HOME)/platforms_startup/armcc/AT91SAM7A3/SAM7A3.asm - and rebuild startup library. - -Startup library uses standard Keil MDK-ARM license. - -Eclipse project is tested in eclipse Kepler, eclipse Luna. -You need to adjust some environment variables in "C/C++ Build" tab in -properties window for project. -"CPPUTEST_HOME" is a path to root of CppUTest -"KEIL_DIR" is a path to ARM C/C++ compiler -"PATH" there is need to add path to make.exe -Eclipse project use plugin "GDB Hardware Debugger" to debug, so for debug -you may install "GDB Hardware Debugger" and gdb client (from -GNU ARM Tools Embedded) or create your own debug configuration -(for exampe, use eclipse plugin from Keil MDK-ARM installation; no need to -install other plugins and toolchains). diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/ROM.sct cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/ROM.sct --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/ROM.sct 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/ROM.sct 1970-01-01 00:00:00.000000000 +0000 @@ -1,34 +0,0 @@ -#! armcc -E -; code upper need to use #define - -;------------------------------------------------------------------------------------- -; Keil scatter loading file -; For AT91SAM7A3 -;------------------------------------------------------------------------------------- - -#define FLASH_START (0x00100000) -#define FLASH_END (0x00140000) -#define FLASH_SIZE (FLASH_END-FLASH_START) - -; Internal SRAM -#define RAM_START 0x00200000 -#define RAM_END 0x00208000 -#define RAM_SIZE (RAM_END-RAM_START) - -; Load region for main program -LR1 FLASH_START FLASH_SIZE { - ER2 FLASH_START { - *.o(.reset, +First) - *.o(InRoot$$Sections) - *.o(+RO) - } - ER5 RAM_START RAM_SIZE { - *.o(+RW +ZI) - *.o(STACK) - } -} - - - -/*----------------------------------------------------------------------------*/ - diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/STACK.txt cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/STACK.txt --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/STACK.txt 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/STACK.txt 1970-01-01 00:00:00.000000000 +0000 @@ -1,14 +0,0 @@ -See objs/app/app.htm for details about stack sizes for functions and call tree. - -Stack usage for std::cout << (double) is about 1336 bytes - -Stack usage for CppUTest is at least 4368 bytes with call chain: -main -> - CommandLineTestRunner::RunAllTests(int, char**) -> - CommandLineTestRunner::RunAllTests(int, const char**) -> - MemoryLeakWarningPlugin::MemoryLeakWarningPlugin(const SimpleString&, MemoryLeakDetector*) -> - MemoryLeakWarningPlugin::getGlobalDetector() -> - MemoryLeakDetector::MemoryLeakDetector(MemoryLeakFailure*) -> - MemoryLeakDetectorTable::MemoryLeakDetectorTable() -> - __aeabi_vec_ctor_nocookie_nodtor -Maximum stack consumption for constructor MemoryLeakDetector::MemoryLeakDetector(MemoryLeakFailure*) diff -Nru cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/tests/main.cpp cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/tests/main.cpp --- cpputest-3.7.2/platforms_examples/armcc/AT91SAM7A3/tests/main.cpp 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/AT91SAM7A3/tests/main.cpp 1970-01-01 00:00:00.000000000 +0000 @@ -1,27 +0,0 @@ -//- ------------------------------------------------------------------ -//- Copyright (c) James W. Grenning -- All Rights Reserved -//- For use by owners of Test-Driven Development for Embedded C, -//- and attendees of Renaissance Software Consulting, Co. training -//- classes. -//- -//- Available at http://pragprog.com/titles/jgade/ -//- ISBN 1-934356-62-X, ISBN13 978-1-934356-62-3 -//- -//- Authorized users may use this source code in your own -//- projects, however the source code may not be used to -//- create training material, courses, books, articles, and -//- the like. We make no guarantees that this source code is -//- fit for any purpose. -//- -//- www.renaissancesoftware.net james@renaissancesoftware.net -//- ------------------------------------------------------------------ - -#include "CppUTest/CommandLineTestRunner.h" - -int main(int ac, char** av) -{ - int result = RUN_ALL_TESTS(ac, av); - - return result; -} - diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1768/cpputest_example_Default.launch cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/cpputest_example_Default.launch --- cpputest-3.7.2/platforms_examples/armcc/LPC1768/cpputest_example_Default.launch 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/cpputest_example_Default.launch 1970-01-01 00:00:00.000000000 +0000 @@ -1,52 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1768/.cproject cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/.cproject --- cpputest-3.7.2/platforms_examples/armcc/LPC1768/.cproject 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/.cproject 1970-01-01 00:00:00.000000000 +0000 @@ -1,83 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1768/jlink_gdb.cmd cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/jlink_gdb.cmd --- cpputest-3.7.2/platforms_examples/armcc/LPC1768/jlink_gdb.cmd 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/jlink_gdb.cmd 1970-01-01 00:00:00.000000000 +0000 @@ -1 +0,0 @@ -start "JLink GDB Server" "C:\Program Files (x86)\SEGGER\JLinkARM_V486a\JLinkGDBServerCL.exe" -device LPC1768 -if SWD diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1768/LPC1768.jflash cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/LPC1768.jflash --- cpputest-3.7.2/platforms_examples/armcc/LPC1768/LPC1768.jflash 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/LPC1768.jflash 1970-01-01 00:00:00.000000000 +0000 @@ -1,83 +0,0 @@ - AppVersion = 46202 -[GENERAL] - ConnectMode = 0 - CurrentFile = "objs/app/app.mot" - DataFileSAddr = 0x00000000 - GUIMode = 0 - HostName = "" - TargetIF = 1 - USBPort = 0 - USBSerialNo = 0x00000000 -[JTAG] - IRLen = 0 - MultipleTargets = 0 - NumDevices = 0 - Speed0 = 5 - Speed1 = 4000 - TAP_Number = 0 - UseAdaptive0 = 0 - UseAdaptive1 = 0 - UseMaxSpeed0 = 1 - UseMaxSpeed1 = 1 -[CPU] - CheckCoreID = 1 - ChipName = "NXP LPC1768" - ClockSpeed = 0x05F5E100 - Core = 0x030000FF - CoreID = 0x4BA00477 - CoreIDMask = 0xFFFFFFFF - DeviceFamily = 0x00000003 - EndianMode = 0 - HasInternalFlash = 1 - InitStep0_Action = "Reset" - InitStep0_Comment = "Reset and halt target" - InitStep0_Value0 = 0x00000000 - InitStep0_Value1 = 0x00000000 - NumExitSteps = 0 - NumInitSteps = 1 - RAMAddr = 0x10000000 - RAMSize = 0x00008000 - ScriptFile = "" - UseAutoSpeed = 0x00000001 - UseRAM = 1 - UseScriptFile = 0 -[FLASH] - aSectorSel[30] = 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 - AutoDetect = 0 - BankName = "" - BankSelMode = 0 - BaseAddr = 0x00000000 - CheckId = 0 - CustomRAMCode = "" - DeviceName = "LPC1768 internal" - EndBank = 29 - NumBanks = 1 - OrgNumBits = 32 - OrgNumChips = 1 - StartBank = 0 - UseCustomRAMCode = 0 -[PRODUCTION] - AutoPerformsErase = 1 - AutoPerformsHardLock = 0 - AutoPerformsHardUnlock = 0 - AutoPerformsProgram = 1 - AutoPerformsSecure = 0 - AutoPerformsSoftLock = 0 - AutoPerformsSoftUnlock = 1 - AutoPerformsStartApp = 1 - AutoPerformsUnsecure = 0 - AutoPerformsVerify = 1 - EnableProductionMode = 0 - EnableTargetPower = 0 - EraseType = 2 - ProductionDelay = 0x000001F4 - ProductionThreshold = 0x00000BB8 - ProgramSN = 0 - SerialFile = "" - SNAddr = 0x00000000 - SNInc = 0x00000001 - SNLen = 0x00000008 - SNListFile = "" - SNValue = 0x00000001 - TargetPowerDelay = 0x00000014 - VerifyType = 1 diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1768/.project cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/.project --- cpputest-3.7.2/platforms_examples/armcc/LPC1768/.project 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/.project 1970-01-01 00:00:00.000000000 +0000 @@ -1,26 +0,0 @@ - - - cpputest_example - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1768/README cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/README --- cpputest-3.7.2/platforms_examples/armcc/LPC1768/README 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/README 1970-01-01 00:00:00.000000000 +0000 @@ -1,40 +0,0 @@ -Sample project to test CppUTest for Keil MDK-ARM toolchain and LPC1768 chip. - -Requirements: -1. CYGWIN (rm.exe, mkdir.exe, make.exe) - -2. Keil MDK-ARM - -3. JLink Flash (for programming chip) or FlashMagic - -4. serial connection to UART0 or UART1 interface - -5. 12 or 24 MHz quartz. If else, need to be adjusted in - $(CPPUTEST_HOME)/platforms_startup/armcc/LPC1768/system_LPC17xx.c - (for _clock_init() function working correctly and to set up 100 MHz core - clock). - Please check system_LPC17xx.c for correct quartz selection in function - SystemInit(), and rebuild startup library for any change. - Default is 12 MHz quartz. - -6. eclipse + gdb server from JLink + arm-none-eabi-gdb from GNU ARM Tools Embedded - For debug only. - -First, you need to compile CppUTest and target startup library: - make -C ../../../platforms/armcc CPU=Cortex-M3 all - make -C ../../../platforms_startup/armcc/LPC1768 all - -Second, you need to write tests. As example, I use - $(CPPUTEST_HOME)/examples/AllTests/CircularBufferTest.cpp. - -Third, you need to make executable: - make all - -Fourth, you need to program executable on target chip: - make prog - -Project use semihosting, so you may use standard printf() or std::cout << "Hello!" - -If problems with heap or low memory, adjust heap size in - $(CPPUTEST_HOME)/platforms_startup/armcc/LPC1768/startup_LPC17xx.asm - and rebuild startup library. diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1768/ROM.sct cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/ROM.sct --- cpputest-3.7.2/platforms_examples/armcc/LPC1768/ROM.sct 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/ROM.sct 1970-01-01 00:00:00.000000000 +0000 @@ -1,42 +0,0 @@ -#! armcc -E -; code upper need to use #define - -;------------------------------------------------------------------------------------- -; Keil scatter loading file -; For LPC1768 -;------------------------------------------------------------------------------------- - -#define FLASH_START (0x00000000) -#define FLASH_END (0x00080000) -#define FLASH_SIZE (FLASH_END-FLASH_START) - -; Internal SRAM -#define RAM1_START 0x10000000 -#define RAM1_END 0x10008000 -#define RAM1_SIZE (RAM1_END-RAM1_START) - -; Internal SRAM for peripherial DMA -#define RAM2_START 0x2007C000 -#define RAM2_END 0x20084000 -#define RAM2_SIZE (RAM2_END-RAM2_START) - -; Load region for main program -LR1 FLASH_START FLASH_SIZE { - ER1 FLASH_START { - *.o(RESET, +First) - *.o(InRoot$$Sections) - *.o(+RO) - } - ER2 RAM1_START RAM1_SIZE { - *.o(+RW +ZI) - } - ER3 RAM2_START RAM2_SIZE { - *.o(HEAP) - *.o(STACK) - } -} - - - -/*----------------------------------------------------------------------------*/ - diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1768/tests/main.cpp cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/tests/main.cpp --- cpputest-3.7.2/platforms_examples/armcc/LPC1768/tests/main.cpp 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1768/tests/main.cpp 1970-01-01 00:00:00.000000000 +0000 @@ -1,37 +0,0 @@ -//- ------------------------------------------------------------------ -//- Copyright (c) James W. Grenning -- All Rights Reserved -//- For use by owners of Test-Driven Development for Embedded C, -//- and attendees of Renaissance Software Consulting, Co. training -//- classes. -//- -//- Available at http://pragprog.com/titles/jgade/ -//- ISBN 1-934356-62-X, ISBN13 978-1-934356-62-3 -//- -//- Authorized users may use this source code in your own -//- projects, however the source code may not be used to -//- create training material, courses, books, articles, and -//- the like. We make no guarantees that this source code is -//- fit for any purpose. -//- -//- www.renaissancesoftware.net james@renaissancesoftware.net -//- ------------------------------------------------------------------ - -#include "CppUTest/CommandLineTestRunner.h" -#include -#include - -extern "C" void _clock_init(void); -extern std::uint32_t SystemCoreClock; -extern const std::uint32_t SystemCoreClock12; - -int main(int ac, char** av) -{ - SystemCoreClock = SystemCoreClock12; /* if 12 MHz quartz is used; need to LPC_TIM3 measure */ - _clock_init(); /* secondary call for new SystemCoreClock freq; previous call worked with unknown value */ - - std::cout << "Hello, World!\n"; - int result = RUN_ALL_TESTS(ac, av); - - return result; -} - diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1833/FLASH.sct cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1833/FLASH.sct --- cpputest-3.7.2/platforms_examples/armcc/LPC1833/FLASH.sct 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1833/FLASH.sct 1970-01-01 00:00:00.000000000 +0000 @@ -1,52 +0,0 @@ -#! armcc -E -; code upper need to use #define - -;------------------------------------------------------------------------------------- -; Keil scatter loading file -; For LPC1833 -;------------------------------------------------------------------------------------- - -; Internal SRAM0 -#define SRAM0_START 0x10000000 -#define SRAM0_END 0x10008000 -#define SRAM0_SIZE (SRAM0_END-SRAM0_START) - -; Internal SRAM1 -#define SRAM1_START 0x10080000 -#define SRAM1_END 0x1008A000 -#define SRAM1_SIZE (SRAM1_END-SRAM1_START) - -; Internal SRAM2 -#define SRAM2_START 0x20000000 -#define SRAM2_END 0x20010000 -#define SRAM2_SIZE (SRAM2_END-SRAM2_START) - -; SDRAM -#define SDRAM_START 0x28000000 - -; Internal FLASHA -#define FLASHA_START 0x1A000000 -#define FLASHA_END 0x1A040000 -#define FLASHA_SIZE (FLASHA_END-FLASHA_START) - -; Internal FLASHB -#define FLASHB_START 0x1B000000 -#define FLASHB_END 0x1B040000 -#define FLASHB_SIZE (FLASHB_END-FLASHB_START) - -LR1 FLASHA_START FLASHA_SIZE { - ER1 FLASHA_START FLASHA_SIZE { - *(RESET, +FIRST) - *(InRoot$$Sections) - *.o (+RO) - } - ER2 SRAM0_START SRAM0_SIZE { - *.o (+RW +ZI) - } - - ER4 (SRAM1_START) SRAM1_SIZE { - *(HEAP) - *(STACK) - } -} - diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1833/LPC1833.jflash cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1833/LPC1833.jflash --- cpputest-3.7.2/platforms_examples/armcc/LPC1833/LPC1833.jflash 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1833/LPC1833.jflash 1970-01-01 00:00:00.000000000 +0000 @@ -1,83 +0,0 @@ - AppVersion = 46202 -[GENERAL] - ConnectMode = 0 - CurrentFile = "objs\can_eth.hex" - DataFileSAddr = 0x00000000 - GUIMode = 0 - HostName = "" - TargetIF = 0 - USBPort = 0 - USBSerialNo = 0x00000000 -[JTAG] - IRLen = 0 - MultipleTargets = 0 - NumDevices = 0 - Speed0 = 5 - Speed1 = 4000 - TAP_Number = 0 - UseAdaptive0 = 0 - UseAdaptive1 = 0 - UseMaxSpeed0 = 1 - UseMaxSpeed1 = 1 -[CPU] - CheckCoreID = 1 - ChipName = "NXP LPC1833" - ClockSpeed = 0x016E3600 - Core = 0x030000FF - CoreID = 0x4BA00477 - CoreIDMask = 0x0F000FFF - DeviceFamily = 0x00000003 - EndianMode = 0 - HasInternalFlash = 1 - InitStep0_Action = "Reset" - InitStep0_Comment = "Reset and halt target" - InitStep0_Value0 = 0x00000000 - InitStep0_Value1 = 0x00000000 - NumExitSteps = 0 - NumInitSteps = 1 - RAMAddr = 0x10080000 - RAMSize = 0x00008000 - ScriptFile = "" - UseAutoSpeed = 0x00000001 - UseRAM = 1 - UseScriptFile = 0 -[FLASH] - aSectorSel[22] = 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 - AutoDetect = 0 - BankName = "" - BankSelMode = 0 - BaseAddr = 0x1A000000 - CheckId = 0 - CustomRAMCode = "" - DeviceName = "LPC1833 internal" - EndBank = 21 - NumBanks = 1 - OrgNumBits = 32 - OrgNumChips = 1 - StartBank = 0 - UseCustomRAMCode = 0 -[PRODUCTION] - AutoPerformsErase = 1 - AutoPerformsHardLock = 0 - AutoPerformsHardUnlock = 0 - AutoPerformsProgram = 1 - AutoPerformsSecure = 0 - AutoPerformsSoftLock = 0 - AutoPerformsSoftUnlock = 1 - AutoPerformsStartApp = 1 - AutoPerformsUnsecure = 0 - AutoPerformsVerify = 1 - EnableProductionMode = 0 - EnableTargetPower = 0 - EraseType = 1 - ProductionDelay = 0x000001F4 - ProductionThreshold = 0x00000BB8 - ProgramSN = 0 - SerialFile = "" - SNAddr = 0x00000000 - SNInc = 0x00000001 - SNLen = 0x00000008 - SNListFile = "" - SNValue = 0x00000001 - TargetPowerDelay = 0x00000014 - VerifyType = 1 diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1833/src/dummy.c cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1833/src/dummy.c --- cpputest-3.7.2/platforms_examples/armcc/LPC1833/src/dummy.c 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1833/src/dummy.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,3 +0,0 @@ -/* this file is requred to build application library, armar.exe can't build - * libraries without at least one object input file. -*/ diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1833/tests/main.cpp cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1833/tests/main.cpp --- cpputest-3.7.2/platforms_examples/armcc/LPC1833/tests/main.cpp 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1833/tests/main.cpp 1970-01-01 00:00:00.000000000 +0000 @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2007, Michael Feathers, James Grenning and Bas Vodde - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE EARLIER MENTIONED AUTHORS ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "CppUTest/CommandLineTestRunner.h" - -int main(int ac, const char** av) -{ - /* These checks are here to make sure assertions outside test runs don't crash */ - CHECK(true); - LONGS_EQUAL(1, 1); - - return CommandLineTestRunner::RunAllTests(ac, av); -} - diff -Nru cpputest-3.7.2/platforms_examples/armcc/LPC1833/tests/test1.cpp cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1833/tests/test1.cpp --- cpputest-3.7.2/platforms_examples/armcc/LPC1833/tests/test1.cpp 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/armcc/LPC1833/tests/test1.cpp 1970-01-01 00:00:00.000000000 +0000 @@ -1,10 +0,0 @@ -#include "CppUTest/TestHarness.h" - -TEST_GROUP(start) -{ -}; - -TEST(start, first) -{ - FAIL("Start here!"); -} diff -Nru cpputest-3.7.2/platforms_examples/README cpputest-3.7.2+dfsg/platforms_examples/README --- cpputest-3.7.2/platforms_examples/README 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_examples/README 1970-01-01 00:00:00.000000000 +0000 @@ -1,9 +0,0 @@ -Directory to place test examples for different toolchains/chips combinations. - -Source files from this directory is compiled to executable using CppUTest, - CppUTestExt and startup libraries from lib directory in CppUTest home. - -There is a sample eclipse project in armcc/AT91SAM7A3 folder. It may be used -to see at possibility way of cross development with CppUTest running in -target platform. It is based on Makefile. -Makefile need some Cygwin utility, so you need to install cygwin. diff -Nru cpputest-3.7.2/platforms_startup/armcc/AT91SAM7A3/AT91SAM7A3.h cpputest-3.7.2+dfsg/platforms_startup/armcc/AT91SAM7A3/AT91SAM7A3.h --- cpputest-3.7.2/platforms_startup/armcc/AT91SAM7A3/AT91SAM7A3.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/AT91SAM7A3/AT91SAM7A3.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,2992 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7A3.h -// Object : AT91SAM7A3 definitions -// Generated : AT91 SW Application Group 09/13/2005 (09:48:02) -// -// CVS Reference : /AT91SAM7A3.pl/1.28/Tue Sep 13 07:43:39 2005// -// CVS Reference : /SYS_SAM7A3.pl/1.7/Thu Feb 3 17:24:14 2005// -// CVS Reference : /MC_SAM7A3.pl/1.2/Fri May 20 14:22:29 2005// -// CVS Reference : /PMC_SAM7A3.pl/1.2/Tue Feb 8 14:00:18 2005// -// CVS Reference : /RSTC_SAM7A3.pl/1.2/Wed Jul 13 15:25:16 2005// -// CVS Reference : /SHDWC_SAM7A3.pl/1.1/Thu Feb 3 17:23:24 2005// -// CVS Reference : /UDP_SAM7A3.pl/1.1/Tue May 10 12:39:23 2005// -// CVS Reference : /PWM_SAM7A3.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 06:38:23 2004// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// -// CVS Reference : /MCI_6101A.pl/1.1/Tue Jul 13 06:33:59 2004// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:46:08 2005// -// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 13:30:33 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7A3_H -#define AT91SAM7A3_H - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[1]; // - AT91_REG SHDWC_SHCR; // Shut Down Control Register - AT91_REG SHDWC_SHMR; // Shut Down Mode Register - AT91_REG SHDWC_SHSR; // Shut Down Status Register - AT91_REG Reserved27[1]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved28[1]; // - AT91_REG SYS_GPBR0; // General Purpose Register 0 - AT91_REG SYS_GPBR1; // General Purpose Register 1 - AT91_REG Reserved29[106]; // - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved30[1]; // - AT91_REG MC_PUIA[16]; // MC Protection Unit Area - AT91_REG MC_PUP; // MC Protection Unit Peripherals - AT91_REG MC_PUER; // MC Protection Unit Enable Register - AT91_REG Reserved31[2]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_SYS, *AT91PS_SYS; - -// -------- GPBR : (SYS Offset: 0xd50) GPBR General Purpose Register -------- -// -------- GPBR : (SYS Offset: 0xd54) GPBR General Purpose Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_GENERAL ((unsigned int) 0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Length - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Shut Down Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SHDWC { - AT91_REG SHDWC_SHCR; // Shut Down Control Register - AT91_REG SHDWC_SHMR; // Shut Down Mode Register - AT91_REG SHDWC_SHSR; // Shut Down Status Register -} AT91S_SHDWC, *AT91PS_SHDWC; - -// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- -#define AT91C_SHDWC_SHDW ((unsigned int) 0x1 << 0) // (SHDWC) Processor Reset -#define AT91C_SHDWC_KEY ((unsigned int) 0xFF << 24) // (SHDWC) Shut down KEY Password -// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- -#define AT91C_SHDWC_WKMODE0 ((unsigned int) 0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection -#define AT91C_SHDWC_WKMODE0_NONE ((unsigned int) 0x0) // (SHDWC) None. No detection is performed on the wake up input. -#define AT91C_SHDWC_WKMODE0_HIGH ((unsigned int) 0x1) // (SHDWC) High Level. -#define AT91C_SHDWC_WKMODE0_LOW ((unsigned int) 0x2) // (SHDWC) Low Level. -#define AT91C_SHDWC_WKMODE0_ANYLEVEL ((unsigned int) 0x3) // (SHDWC) Any level change. -#define AT91C_SHDWC_CPTWK0 ((unsigned int) 0xF << 4) // (SHDWC) Counter On Wake Up 0 -#define AT91C_SHDWC_WKMODE1 ((unsigned int) 0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection -#define AT91C_SHDWC_WKMODE1_NONE ((unsigned int) 0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input. -#define AT91C_SHDWC_WKMODE1_HIGH ((unsigned int) 0x1 << 8) // (SHDWC) High Level. -#define AT91C_SHDWC_WKMODE1_LOW ((unsigned int) 0x2 << 8) // (SHDWC) Low Level. -#define AT91C_SHDWC_WKMODE1_ANYLEVEL ((unsigned int) 0x3 << 8) // (SHDWC) Any level change. -#define AT91C_SHDWC_CPTWK1 ((unsigned int) 0xF << 12) // (SHDWC) Counter On Wake Up 1 -#define AT91C_SHDWC_RTTWKEN ((unsigned int) 0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable -// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- -#define AT91C_SHDWC_WAKEUP0 ((unsigned int) 0x1 << 0) // (SHDWC) Wake Up 0 Status -#define AT91C_SHDWC_WAKEUP1 ((unsigned int) 0x1 << 1) // (SHDWC) Wake Up 1 Status -#define AT91C_SHDWC_FWKUP ((unsigned int) 0x1 << 2) // (SHDWC) Force Wake Up Status -#define AT91C_SHDWC_RTTWK ((unsigned int) 0x1 << 16) // (SHDWC) Real Time Timer wake Up - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[1]; // - AT91_REG MC_PUIA[16]; // MC Protection Unit Area - AT91_REG MC_PUP; // MC Protection Unit Peripherals - AT91_REG MC_PUER; // MC Protection Unit Enable Register - AT91_REG Reserved1[2]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_MPU ((unsigned int) 0x1 << 2) // (MC) Memory protection Unit Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- -#define AT91C_MC_PROT ((unsigned int) 0x3 << 0) // (MC) Protection -#define AT91C_MC_PROT_PNAUNA ((unsigned int) 0x0) // (MC) Privilege: No Access, User: No Access -#define AT91C_MC_PROT_PRWUNA ((unsigned int) 0x1) // (MC) Privilege: Read/Write, User: No Access -#define AT91C_MC_PROT_PRWURO ((unsigned int) 0x2) // (MC) Privilege: Read/Write, User: Read Only -#define AT91C_MC_PROT_PRWURW ((unsigned int) 0x3) // (MC) Privilege: Read/Write, User: Read/Write -#define AT91C_MC_SIZE ((unsigned int) 0xF << 4) // (MC) Internal Area Size -#define AT91C_MC_SIZE_1KB ((unsigned int) 0x0 << 4) // (MC) Area size 1KByte -#define AT91C_MC_SIZE_2KB ((unsigned int) 0x1 << 4) // (MC) Area size 2KByte -#define AT91C_MC_SIZE_4KB ((unsigned int) 0x2 << 4) // (MC) Area size 4KByte -#define AT91C_MC_SIZE_8KB ((unsigned int) 0x3 << 4) // (MC) Area size 8KByte -#define AT91C_MC_SIZE_16KB ((unsigned int) 0x4 << 4) // (MC) Area size 16KByte -#define AT91C_MC_SIZE_32KB ((unsigned int) 0x5 << 4) // (MC) Area size 32KByte -#define AT91C_MC_SIZE_64KB ((unsigned int) 0x6 << 4) // (MC) Area size 64KByte -#define AT91C_MC_SIZE_128KB ((unsigned int) 0x7 << 4) // (MC) Area size 128KByte -#define AT91C_MC_SIZE_256KB ((unsigned int) 0x8 << 4) // (MC) Area size 256KByte -#define AT91C_MC_SIZE_512KB ((unsigned int) 0x9 << 4) // (MC) Area size 512KByte -#define AT91C_MC_SIZE_1MB ((unsigned int) 0xA << 4) // (MC) Area size 1MByte -#define AT91C_MC_SIZE_2MB ((unsigned int) 0xB << 4) // (MC) Area size 2MByte -#define AT91C_MC_SIZE_4MB ((unsigned int) 0xC << 4) // (MC) Area size 4MByte -#define AT91C_MC_SIZE_8MB ((unsigned int) 0xD << 4) // (MC) Area size 8MByte -#define AT91C_MC_SIZE_16MB ((unsigned int) 0xE << 4) // (MC) Area size 16MByte -#define AT91C_MC_SIZE_64MB ((unsigned int) 0xF << 4) // (MC) Area size 64MByte -#define AT91C_MC_BA ((unsigned int) 0x3FFFF << 10) // (MC) Internal Area Base Address -// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- -// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- -#define AT91C_MC_PUEB ((unsigned int) 0x1 << 0) // (MC) Protection Unit enable Bit -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_EOP ((unsigned int) 0x1 << 0) // (MC) End Of Programming Flag -#define AT91C_MC_EOL ((unsigned int) 0x1 << 1) // (MC) End Of Lock/Unlock Flag -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error Flag -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error Flag -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Multimedia Card Interface -// ***************************************************************************** -typedef struct _AT91S_MCI { - AT91_REG MCI_CR; // MCI Control Register - AT91_REG MCI_MR; // MCI Mode Register - AT91_REG MCI_DTOR; // MCI Data Timeout Register - AT91_REG MCI_SDCR; // MCI SD Card Register - AT91_REG MCI_ARGR; // MCI Argument Register - AT91_REG MCI_CMDR; // MCI Command Register - AT91_REG Reserved0[2]; // - AT91_REG MCI_RSPR[4]; // MCI Response Register - AT91_REG MCI_RDR; // MCI Receive Data Register - AT91_REG MCI_TDR; // MCI Transmit Data Register - AT91_REG Reserved1[2]; // - AT91_REG MCI_SR; // MCI Status Register - AT91_REG MCI_IER; // MCI Interrupt Enable Register - AT91_REG MCI_IDR; // MCI Interrupt Disable Register - AT91_REG MCI_IMR; // MCI Interrupt Mask Register - AT91_REG Reserved2[44]; // - AT91_REG MCI_RPR; // Receive Pointer Register - AT91_REG MCI_RCR; // Receive Counter Register - AT91_REG MCI_TPR; // Transmit Pointer Register - AT91_REG MCI_TCR; // Transmit Counter Register - AT91_REG MCI_RNPR; // Receive Next Pointer Register - AT91_REG MCI_RNCR; // Receive Next Counter Register - AT91_REG MCI_TNPR; // Transmit Next Pointer Register - AT91_REG MCI_TNCR; // Transmit Next Counter Register - AT91_REG MCI_PTCR; // PDC Transfer Control Register - AT91_REG MCI_PTSR; // PDC Transfer Status Register -} AT91S_MCI, *AT91PS_MCI; - -// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- -#define AT91C_MCI_MCIEN ((unsigned int) 0x1 << 0) // (MCI) Multimedia Interface Enable -#define AT91C_MCI_MCIDIS ((unsigned int) 0x1 << 1) // (MCI) Multimedia Interface Disable -#define AT91C_MCI_PWSEN ((unsigned int) 0x1 << 2) // (MCI) Power Save Mode Enable -#define AT91C_MCI_PWSDIS ((unsigned int) 0x1 << 3) // (MCI) Power Save Mode Disable -#define AT91C_MCI_SWRST ((unsigned int) 0x1 << 7) // (MCI) MCI Software reset -// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- -#define AT91C_MCI_CLKDIV ((unsigned int) 0xFF << 0) // (MCI) Clock Divider -#define AT91C_MCI_PWSDIV ((unsigned int) 0x7 << 8) // (MCI) Power Saving Divider -#define AT91C_MCI_PDCPADV ((unsigned int) 0x1 << 14) // (MCI) PDC Padding Value -#define AT91C_MCI_PDCMODE ((unsigned int) 0x1 << 15) // (MCI) PDC Oriented Mode -#define AT91C_MCI_BLKLEN ((unsigned int) 0xFFF << 18) // (MCI) Data Block Length -// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- -#define AT91C_MCI_DTOCYC ((unsigned int) 0xF << 0) // (MCI) Data Timeout Cycle Number -#define AT91C_MCI_DTOMUL ((unsigned int) 0x7 << 4) // (MCI) Data Timeout Multiplier -#define AT91C_MCI_DTOMUL_1 ((unsigned int) 0x0 << 4) // (MCI) DTOCYC x 1 -#define AT91C_MCI_DTOMUL_16 ((unsigned int) 0x1 << 4) // (MCI) DTOCYC x 16 -#define AT91C_MCI_DTOMUL_128 ((unsigned int) 0x2 << 4) // (MCI) DTOCYC x 128 -#define AT91C_MCI_DTOMUL_256 ((unsigned int) 0x3 << 4) // (MCI) DTOCYC x 256 -#define AT91C_MCI_DTOMUL_1024 ((unsigned int) 0x4 << 4) // (MCI) DTOCYC x 1024 -#define AT91C_MCI_DTOMUL_4096 ((unsigned int) 0x5 << 4) // (MCI) DTOCYC x 4096 -#define AT91C_MCI_DTOMUL_65536 ((unsigned int) 0x6 << 4) // (MCI) DTOCYC x 65536 -#define AT91C_MCI_DTOMUL_1048576 ((unsigned int) 0x7 << 4) // (MCI) DTOCYC x 1048576 -// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- -#define AT91C_MCI_SCDSEL ((unsigned int) 0xF << 0) // (MCI) SD Card Selector -#define AT91C_MCI_SCDBUS ((unsigned int) 0x1 << 7) // (MCI) SD Card Bus Width -// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- -#define AT91C_MCI_CMDNB ((unsigned int) 0x3F << 0) // (MCI) Command Number -#define AT91C_MCI_RSPTYP ((unsigned int) 0x3 << 6) // (MCI) Response Type -#define AT91C_MCI_RSPTYP_NO ((unsigned int) 0x0 << 6) // (MCI) No response -#define AT91C_MCI_RSPTYP_48 ((unsigned int) 0x1 << 6) // (MCI) 48-bit response -#define AT91C_MCI_RSPTYP_136 ((unsigned int) 0x2 << 6) // (MCI) 136-bit response -#define AT91C_MCI_SPCMD ((unsigned int) 0x7 << 8) // (MCI) Special CMD -#define AT91C_MCI_SPCMD_NONE ((unsigned int) 0x0 << 8) // (MCI) Not a special CMD -#define AT91C_MCI_SPCMD_INIT ((unsigned int) 0x1 << 8) // (MCI) Initialization CMD -#define AT91C_MCI_SPCMD_SYNC ((unsigned int) 0x2 << 8) // (MCI) Synchronized CMD -#define AT91C_MCI_SPCMD_IT_CMD ((unsigned int) 0x4 << 8) // (MCI) Interrupt command -#define AT91C_MCI_SPCMD_IT_REP ((unsigned int) 0x5 << 8) // (MCI) Interrupt response -#define AT91C_MCI_OPDCMD ((unsigned int) 0x1 << 11) // (MCI) Open Drain Command -#define AT91C_MCI_MAXLAT ((unsigned int) 0x1 << 12) // (MCI) Maximum Latency for Command to respond -#define AT91C_MCI_TRCMD ((unsigned int) 0x3 << 16) // (MCI) Transfer CMD -#define AT91C_MCI_TRCMD_NO ((unsigned int) 0x0 << 16) // (MCI) No transfer -#define AT91C_MCI_TRCMD_START ((unsigned int) 0x1 << 16) // (MCI) Start transfer -#define AT91C_MCI_TRCMD_STOP ((unsigned int) 0x2 << 16) // (MCI) Stop transfer -#define AT91C_MCI_TRDIR ((unsigned int) 0x1 << 18) // (MCI) Transfer Direction -#define AT91C_MCI_TRTYP ((unsigned int) 0x3 << 19) // (MCI) Transfer Type -#define AT91C_MCI_TRTYP_BLOCK ((unsigned int) 0x0 << 19) // (MCI) Block Transfer type -#define AT91C_MCI_TRTYP_MULTIPLE ((unsigned int) 0x1 << 19) // (MCI) Multiple Block transfer type -#define AT91C_MCI_TRTYP_STREAM ((unsigned int) 0x2 << 19) // (MCI) Stream transfer type -// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- -#define AT91C_MCI_CMDRDY ((unsigned int) 0x1 << 0) // (MCI) Command Ready flag -#define AT91C_MCI_RXRDY ((unsigned int) 0x1 << 1) // (MCI) RX Ready flag -#define AT91C_MCI_TXRDY ((unsigned int) 0x1 << 2) // (MCI) TX Ready flag -#define AT91C_MCI_BLKE ((unsigned int) 0x1 << 3) // (MCI) Data Block Transfer Ended flag -#define AT91C_MCI_DTIP ((unsigned int) 0x1 << 4) // (MCI) Data Transfer in Progress flag -#define AT91C_MCI_NOTBUSY ((unsigned int) 0x1 << 5) // (MCI) Data Line Not Busy flag -#define AT91C_MCI_ENDRX ((unsigned int) 0x1 << 6) // (MCI) End of RX Buffer flag -#define AT91C_MCI_ENDTX ((unsigned int) 0x1 << 7) // (MCI) End of TX Buffer flag -#define AT91C_MCI_RXBUFF ((unsigned int) 0x1 << 14) // (MCI) RX Buffer Full flag -#define AT91C_MCI_TXBUFE ((unsigned int) 0x1 << 15) // (MCI) TX Buffer Empty flag -#define AT91C_MCI_RINDE ((unsigned int) 0x1 << 16) // (MCI) Response Index Error flag -#define AT91C_MCI_RDIRE ((unsigned int) 0x1 << 17) // (MCI) Response Direction Error flag -#define AT91C_MCI_RCRCE ((unsigned int) 0x1 << 18) // (MCI) Response CRC Error flag -#define AT91C_MCI_RENDE ((unsigned int) 0x1 << 19) // (MCI) Response End Bit Error flag -#define AT91C_MCI_RTOE ((unsigned int) 0x1 << 20) // (MCI) Response Time-out Error flag -#define AT91C_MCI_DCRCE ((unsigned int) 0x1 << 21) // (MCI) data CRC Error flag -#define AT91C_MCI_DTOE ((unsigned int) 0x1 << 22) // (MCI) Data timeout Error flag -#define AT91C_MCI_OVRE ((unsigned int) 0x1 << 30) // (MCI) Overrun flag -#define AT91C_MCI_UNRE ((unsigned int) 0x1 << 31) // (MCI) Underrun flag -// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- -// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- -// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[8]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4 -#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5 -#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6 -#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7A3 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -#define AT91C_SYS_GPBR1 ((AT91_REG *) 0xFFFFFD54) // (SYS) General Purpose Register 1 -#define AT91C_SYS_GPBR0 ((AT91_REG *) 0xFFFFFD50) // (SYS) General Purpose Register 0 -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -// ========== Register definition for SHDWC peripheral ========== -#define AT91C_SHDWC_SHMR ((AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register -#define AT91C_SHDWC_SHSR ((AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register -#define AT91C_SHDWC_SHCR ((AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_PUER ((AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -#define AT91C_MC_PUP ((AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals -#define AT91C_MC_PUIA ((AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for CAN0_MB0 peripheral ========== -#define AT91C_CAN0_MB0_MDH ((AT91_REG *) 0xFFF80218) // (CAN0_MB0) MailBox Data High Register -#define AT91C_CAN0_MB0_MSR ((AT91_REG *) 0xFFF80210) // (CAN0_MB0) MailBox Status Register -#define AT91C_CAN0_MB0_MID ((AT91_REG *) 0xFFF80208) // (CAN0_MB0) MailBox ID Register -#define AT91C_CAN0_MB0_MMR ((AT91_REG *) 0xFFF80200) // (CAN0_MB0) MailBox Mode Register -#define AT91C_CAN0_MB0_MCR ((AT91_REG *) 0xFFF8021C) // (CAN0_MB0) MailBox Control Register -#define AT91C_CAN0_MB0_MDL ((AT91_REG *) 0xFFF80214) // (CAN0_MB0) MailBox Data Low Register -#define AT91C_CAN0_MB0_MFID ((AT91_REG *) 0xFFF8020C) // (CAN0_MB0) MailBox Family ID Register -#define AT91C_CAN0_MB0_MAM ((AT91_REG *) 0xFFF80204) // (CAN0_MB0) MailBox Acceptance Mask Register -// ========== Register definition for CAN0_MB1 peripheral ========== -#define AT91C_CAN0_MB1_MDH ((AT91_REG *) 0xFFF80238) // (CAN0_MB1) MailBox Data High Register -#define AT91C_CAN0_MB1_MSR ((AT91_REG *) 0xFFF80230) // (CAN0_MB1) MailBox Status Register -#define AT91C_CAN0_MB1_MID ((AT91_REG *) 0xFFF80228) // (CAN0_MB1) MailBox ID Register -#define AT91C_CAN0_MB1_MMR ((AT91_REG *) 0xFFF80220) // (CAN0_MB1) MailBox Mode Register -#define AT91C_CAN0_MB1_MCR ((AT91_REG *) 0xFFF8023C) // (CAN0_MB1) MailBox Control Register -#define AT91C_CAN0_MB1_MDL ((AT91_REG *) 0xFFF80234) // (CAN0_MB1) MailBox Data Low Register -#define AT91C_CAN0_MB1_MFID ((AT91_REG *) 0xFFF8022C) // (CAN0_MB1) MailBox Family ID Register -#define AT91C_CAN0_MB1_MAM ((AT91_REG *) 0xFFF80224) // (CAN0_MB1) MailBox Acceptance Mask Register -// ========== Register definition for CAN0_MB2 peripheral ========== -#define AT91C_CAN0_MB2_MDH ((AT91_REG *) 0xFFF80258) // (CAN0_MB2) MailBox Data High Register -#define AT91C_CAN0_MB2_MSR ((AT91_REG *) 0xFFF80250) // (CAN0_MB2) MailBox Status Register -#define AT91C_CAN0_MB2_MID ((AT91_REG *) 0xFFF80248) // (CAN0_MB2) MailBox ID Register -#define AT91C_CAN0_MB2_MMR ((AT91_REG *) 0xFFF80240) // (CAN0_MB2) MailBox Mode Register -#define AT91C_CAN0_MB2_MCR ((AT91_REG *) 0xFFF8025C) // (CAN0_MB2) MailBox Control Register -#define AT91C_CAN0_MB2_MDL ((AT91_REG *) 0xFFF80254) // (CAN0_MB2) MailBox Data Low Register -#define AT91C_CAN0_MB2_MFID ((AT91_REG *) 0xFFF8024C) // (CAN0_MB2) MailBox Family ID Register -#define AT91C_CAN0_MB2_MAM ((AT91_REG *) 0xFFF80244) // (CAN0_MB2) MailBox Acceptance Mask Register -// ========== Register definition for CAN0_MB3 peripheral ========== -#define AT91C_CAN0_MB3_MDH ((AT91_REG *) 0xFFF80278) // (CAN0_MB3) MailBox Data High Register -#define AT91C_CAN0_MB3_MSR ((AT91_REG *) 0xFFF80270) // (CAN0_MB3) MailBox Status Register -#define AT91C_CAN0_MB3_MID ((AT91_REG *) 0xFFF80268) // (CAN0_MB3) MailBox ID Register -#define AT91C_CAN0_MB3_MMR ((AT91_REG *) 0xFFF80260) // (CAN0_MB3) MailBox Mode Register -#define AT91C_CAN0_MB3_MCR ((AT91_REG *) 0xFFF8027C) // (CAN0_MB3) MailBox Control Register -#define AT91C_CAN0_MB3_MDL ((AT91_REG *) 0xFFF80274) // (CAN0_MB3) MailBox Data Low Register -#define AT91C_CAN0_MB3_MFID ((AT91_REG *) 0xFFF8026C) // (CAN0_MB3) MailBox Family ID Register -#define AT91C_CAN0_MB3_MAM ((AT91_REG *) 0xFFF80264) // (CAN0_MB3) MailBox Acceptance Mask Register -// ========== Register definition for CAN0_MB4 peripheral ========== -#define AT91C_CAN0_MB4_MDH ((AT91_REG *) 0xFFF80298) // (CAN0_MB4) MailBox Data High Register -#define AT91C_CAN0_MB4_MSR ((AT91_REG *) 0xFFF80290) // (CAN0_MB4) MailBox Status Register -#define AT91C_CAN0_MB4_MID ((AT91_REG *) 0xFFF80288) // (CAN0_MB4) MailBox ID Register -#define AT91C_CAN0_MB4_MMR ((AT91_REG *) 0xFFF80280) // (CAN0_MB4) MailBox Mode Register -#define AT91C_CAN0_MB4_MCR ((AT91_REG *) 0xFFF8029C) // (CAN0_MB4) MailBox Control Register -#define AT91C_CAN0_MB4_MDL ((AT91_REG *) 0xFFF80294) // (CAN0_MB4) MailBox Data Low Register -#define AT91C_CAN0_MB4_MFID ((AT91_REG *) 0xFFF8028C) // (CAN0_MB4) MailBox Family ID Register -#define AT91C_CAN0_MB4_MAM ((AT91_REG *) 0xFFF80284) // (CAN0_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN0_MB5 peripheral ========== -#define AT91C_CAN0_MB5_MSR ((AT91_REG *) 0xFFF802B0) // (CAN0_MB5) MailBox Status Register -#define AT91C_CAN0_MB5_MID ((AT91_REG *) 0xFFF802A8) // (CAN0_MB5) MailBox ID Register -#define AT91C_CAN0_MB5_MMR ((AT91_REG *) 0xFFF802A0) // (CAN0_MB5) MailBox Mode Register -#define AT91C_CAN0_MB5_MCR ((AT91_REG *) 0xFFF802BC) // (CAN0_MB5) MailBox Control Register -#define AT91C_CAN0_MB5_MDL ((AT91_REG *) 0xFFF802B4) // (CAN0_MB5) MailBox Data Low Register -#define AT91C_CAN0_MB5_MFID ((AT91_REG *) 0xFFF802AC) // (CAN0_MB5) MailBox Family ID Register -#define AT91C_CAN0_MB5_MAM ((AT91_REG *) 0xFFF802A4) // (CAN0_MB5) MailBox Acceptance Mask Register -#define AT91C_CAN0_MB5_MDH ((AT91_REG *) 0xFFF802B8) // (CAN0_MB5) MailBox Data High Register -// ========== Register definition for CAN0_MB6 peripheral ========== -#define AT91C_CAN0_MB6_MCR ((AT91_REG *) 0xFFF802DC) // (CAN0_MB6) MailBox Control Register -#define AT91C_CAN0_MB6_MDL ((AT91_REG *) 0xFFF802D4) // (CAN0_MB6) MailBox Data Low Register -#define AT91C_CAN0_MB6_MFID ((AT91_REG *) 0xFFF802CC) // (CAN0_MB6) MailBox Family ID Register -#define AT91C_CAN0_MB6_MAM ((AT91_REG *) 0xFFF802C4) // (CAN0_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN0_MB6_MDH ((AT91_REG *) 0xFFF802D8) // (CAN0_MB6) MailBox Data High Register -#define AT91C_CAN0_MB6_MSR ((AT91_REG *) 0xFFF802D0) // (CAN0_MB6) MailBox Status Register -#define AT91C_CAN0_MB6_MID ((AT91_REG *) 0xFFF802C8) // (CAN0_MB6) MailBox ID Register -#define AT91C_CAN0_MB6_MMR ((AT91_REG *) 0xFFF802C0) // (CAN0_MB6) MailBox Mode Register -// ========== Register definition for CAN0_MB7 peripheral ========== -#define AT91C_CAN0_MB7_MCR ((AT91_REG *) 0xFFF802FC) // (CAN0_MB7) MailBox Control Register -#define AT91C_CAN0_MB7_MDL ((AT91_REG *) 0xFFF802F4) // (CAN0_MB7) MailBox Data Low Register -#define AT91C_CAN0_MB7_MFID ((AT91_REG *) 0xFFF802EC) // (CAN0_MB7) MailBox Family ID Register -#define AT91C_CAN0_MB7_MAM ((AT91_REG *) 0xFFF802E4) // (CAN0_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN0_MB7_MDH ((AT91_REG *) 0xFFF802F8) // (CAN0_MB7) MailBox Data High Register -#define AT91C_CAN0_MB7_MSR ((AT91_REG *) 0xFFF802F0) // (CAN0_MB7) MailBox Status Register -#define AT91C_CAN0_MB7_MID ((AT91_REG *) 0xFFF802E8) // (CAN0_MB7) MailBox ID Register -#define AT91C_CAN0_MB7_MMR ((AT91_REG *) 0xFFF802E0) // (CAN0_MB7) MailBox Mode Register -// ========== Register definition for CAN0_MB8 peripheral ========== -#define AT91C_CAN0_MB8_MCR ((AT91_REG *) 0xFFF8031C) // (CAN0_MB8) MailBox Control Register -#define AT91C_CAN0_MB8_MDL ((AT91_REG *) 0xFFF80314) // (CAN0_MB8) MailBox Data Low Register -#define AT91C_CAN0_MB8_MFID ((AT91_REG *) 0xFFF8030C) // (CAN0_MB8) MailBox Family ID Register -#define AT91C_CAN0_MB8_MAM ((AT91_REG *) 0xFFF80304) // (CAN0_MB8) MailBox Acceptance Mask Register -#define AT91C_CAN0_MB8_MDH ((AT91_REG *) 0xFFF80318) // (CAN0_MB8) MailBox Data High Register -#define AT91C_CAN0_MB8_MMR ((AT91_REG *) 0xFFF80300) // (CAN0_MB8) MailBox Mode Register -#define AT91C_CAN0_MB8_MID ((AT91_REG *) 0xFFF80308) // (CAN0_MB8) MailBox ID Register -#define AT91C_CAN0_MB8_MSR ((AT91_REG *) 0xFFF80310) // (CAN0_MB8) MailBox Status Register -// ========== Register definition for CAN0_MB9 peripheral ========== -#define AT91C_CAN0_MB9_MCR ((AT91_REG *) 0xFFF8033C) // (CAN0_MB9) MailBox Control Register -#define AT91C_CAN0_MB9_MDL ((AT91_REG *) 0xFFF80334) // (CAN0_MB9) MailBox Data Low Register -#define AT91C_CAN0_MB9_MFID ((AT91_REG *) 0xFFF8032C) // (CAN0_MB9) MailBox Family ID Register -#define AT91C_CAN0_MB9_MAM ((AT91_REG *) 0xFFF80324) // (CAN0_MB9) MailBox Acceptance Mask Register -#define AT91C_CAN0_MB9_MDH ((AT91_REG *) 0xFFF80338) // (CAN0_MB9) MailBox Data High Register -#define AT91C_CAN0_MB9_MSR ((AT91_REG *) 0xFFF80330) // (CAN0_MB9) MailBox Status Register -#define AT91C_CAN0_MB9_MID ((AT91_REG *) 0xFFF80328) // (CAN0_MB9) MailBox ID Register -#define AT91C_CAN0_MB9_MMR ((AT91_REG *) 0xFFF80320) // (CAN0_MB9) MailBox Mode Register -// ========== Register definition for CAN0_MB10 peripheral ========== -#define AT91C_CAN0_MB10_MCR ((AT91_REG *) 0xFFF8035C) // (CAN0_MB10) MailBox Control Register -#define AT91C_CAN0_MB10_MDL ((AT91_REG *) 0xFFF80354) // (CAN0_MB10) MailBox Data Low Register -#define AT91C_CAN0_MB10_MFID ((AT91_REG *) 0xFFF8034C) // (CAN0_MB10) MailBox Family ID Register -#define AT91C_CAN0_MB10_MAM ((AT91_REG *) 0xFFF80344) // (CAN0_MB10) MailBox Acceptance Mask Register -#define AT91C_CAN0_MB10_MDH ((AT91_REG *) 0xFFF80358) // (CAN0_MB10) MailBox Data High Register -#define AT91C_CAN0_MB10_MSR ((AT91_REG *) 0xFFF80350) // (CAN0_MB10) MailBox Status Register -#define AT91C_CAN0_MB10_MID ((AT91_REG *) 0xFFF80348) // (CAN0_MB10) MailBox ID Register -#define AT91C_CAN0_MB10_MMR ((AT91_REG *) 0xFFF80340) // (CAN0_MB10) MailBox Mode Register -// ========== Register definition for CAN0_MB11 peripheral ========== -#define AT91C_CAN0_MB11_MCR ((AT91_REG *) 0xFFF8037C) // (CAN0_MB11) MailBox Control Register -#define AT91C_CAN0_MB11_MDL ((AT91_REG *) 0xFFF80374) // (CAN0_MB11) MailBox Data Low Register -#define AT91C_CAN0_MB11_MFID ((AT91_REG *) 0xFFF8036C) // (CAN0_MB11) MailBox Family ID Register -#define AT91C_CAN0_MB11_MAM ((AT91_REG *) 0xFFF80364) // (CAN0_MB11) MailBox Acceptance Mask Register -#define AT91C_CAN0_MB11_MDH ((AT91_REG *) 0xFFF80378) // (CAN0_MB11) MailBox Data High Register -#define AT91C_CAN0_MB11_MSR ((AT91_REG *) 0xFFF80370) // (CAN0_MB11) MailBox Status Register -#define AT91C_CAN0_MB11_MMR ((AT91_REG *) 0xFFF80360) // (CAN0_MB11) MailBox Mode Register -#define AT91C_CAN0_MB11_MID ((AT91_REG *) 0xFFF80368) // (CAN0_MB11) MailBox ID Register -// ========== Register definition for CAN0_MB12 peripheral ========== -#define AT91C_CAN0_MB12_MCR ((AT91_REG *) 0xFFF8039C) // (CAN0_MB12) MailBox Control Register -#define AT91C_CAN0_MB12_MDL ((AT91_REG *) 0xFFF80394) // (CAN0_MB12) MailBox Data Low Register -#define AT91C_CAN0_MB12_MFID ((AT91_REG *) 0xFFF8038C) // (CAN0_MB12) MailBox Family ID Register -#define AT91C_CAN0_MB12_MAM ((AT91_REG *) 0xFFF80384) // (CAN0_MB12) MailBox Acceptance Mask Register -#define AT91C_CAN0_MB12_MDH ((AT91_REG *) 0xFFF80398) // (CAN0_MB12) MailBox Data High Register -#define AT91C_CAN0_MB12_MSR ((AT91_REG *) 0xFFF80390) // (CAN0_MB12) MailBox Status Register -#define AT91C_CAN0_MB12_MID ((AT91_REG *) 0xFFF80388) // (CAN0_MB12) MailBox ID Register -#define AT91C_CAN0_MB12_MMR ((AT91_REG *) 0xFFF80380) // (CAN0_MB12) MailBox Mode Register -// ========== Register definition for CAN0_MB13 peripheral ========== -#define AT91C_CAN0_MB13_MCR ((AT91_REG *) 0xFFF803BC) // (CAN0_MB13) MailBox Control Register -#define AT91C_CAN0_MB13_MDL ((AT91_REG *) 0xFFF803B4) // (CAN0_MB13) MailBox Data Low Register -#define AT91C_CAN0_MB13_MFID ((AT91_REG *) 0xFFF803AC) // (CAN0_MB13) MailBox Family ID Register -#define AT91C_CAN0_MB13_MAM ((AT91_REG *) 0xFFF803A4) // (CAN0_MB13) MailBox Acceptance Mask Register -#define AT91C_CAN0_MB13_MDH ((AT91_REG *) 0xFFF803B8) // (CAN0_MB13) MailBox Data High Register -#define AT91C_CAN0_MB13_MSR ((AT91_REG *) 0xFFF803B0) // (CAN0_MB13) MailBox Status Register -#define AT91C_CAN0_MB13_MID ((AT91_REG *) 0xFFF803A8) // (CAN0_MB13) MailBox ID Register -#define AT91C_CAN0_MB13_MMR ((AT91_REG *) 0xFFF803A0) // (CAN0_MB13) MailBox Mode Register -// ========== Register definition for CAN0_MB14 peripheral ========== -#define AT91C_CAN0_MB14_MCR ((AT91_REG *) 0xFFF803DC) // (CAN0_MB14) MailBox Control Register -#define AT91C_CAN0_MB14_MDL ((AT91_REG *) 0xFFF803D4) // (CAN0_MB14) MailBox Data Low Register -#define AT91C_CAN0_MB14_MFID ((AT91_REG *) 0xFFF803CC) // (CAN0_MB14) MailBox Family ID Register -#define AT91C_CAN0_MB14_MAM ((AT91_REG *) 0xFFF803C4) // (CAN0_MB14) MailBox Acceptance Mask Register -#define AT91C_CAN0_MB14_MDH ((AT91_REG *) 0xFFF803D8) // (CAN0_MB14) MailBox Data High Register -#define AT91C_CAN0_MB14_MSR ((AT91_REG *) 0xFFF803D0) // (CAN0_MB14) MailBox Status Register -#define AT91C_CAN0_MB14_MID ((AT91_REG *) 0xFFF803C8) // (CAN0_MB14) MailBox ID Register -#define AT91C_CAN0_MB14_MMR ((AT91_REG *) 0xFFF803C0) // (CAN0_MB14) MailBox Mode Register -// ========== Register definition for CAN0_MB15 peripheral ========== -#define AT91C_CAN0_MB15_MMR ((AT91_REG *) 0xFFF803E0) // (CAN0_MB15) MailBox Mode Register -#define AT91C_CAN0_MB15_MDH ((AT91_REG *) 0xFFF803F8) // (CAN0_MB15) MailBox Data High Register -#define AT91C_CAN0_MB15_MSR ((AT91_REG *) 0xFFF803F0) // (CAN0_MB15) MailBox Status Register -#define AT91C_CAN0_MB15_MID ((AT91_REG *) 0xFFF803E8) // (CAN0_MB15) MailBox ID Register -#define AT91C_CAN0_MB15_MCR ((AT91_REG *) 0xFFF803FC) // (CAN0_MB15) MailBox Control Register -#define AT91C_CAN0_MB15_MDL ((AT91_REG *) 0xFFF803F4) // (CAN0_MB15) MailBox Data Low Register -#define AT91C_CAN0_MB15_MFID ((AT91_REG *) 0xFFF803EC) // (CAN0_MB15) MailBox Family ID Register -#define AT91C_CAN0_MB15_MAM ((AT91_REG *) 0xFFF803E4) // (CAN0_MB15) MailBox Acceptance Mask Register -// ========== Register definition for CAN0 peripheral ========== -#define AT91C_CAN0_TCR ((AT91_REG *) 0xFFF80024) // (CAN0) Transfer Command Register -#define AT91C_CAN0_TIMESTP ((AT91_REG *) 0xFFF8001C) // (CAN0) Time Stamp Register -#define AT91C_CAN0_BR ((AT91_REG *) 0xFFF80014) // (CAN0) Baudrate Register -#define AT91C_CAN0_ACR ((AT91_REG *) 0xFFF80028) // (CAN0) Abort Command Register -#define AT91C_CAN0_VR ((AT91_REG *) 0xFFF800FC) // (CAN0) Version Register -#define AT91C_CAN0_IER ((AT91_REG *) 0xFFF80004) // (CAN0) Interrupt Enable Register -#define AT91C_CAN0_IMR ((AT91_REG *) 0xFFF8000C) // (CAN0) Interrupt Mask Register -#define AT91C_CAN0_MR ((AT91_REG *) 0xFFF80000) // (CAN0) Mode Register -#define AT91C_CAN0_IDR ((AT91_REG *) 0xFFF80008) // (CAN0) Interrupt Disable Register -#define AT91C_CAN0_SR ((AT91_REG *) 0xFFF80010) // (CAN0) Status Register -#define AT91C_CAN0_TIM ((AT91_REG *) 0xFFF80018) // (CAN0) Timer Register -#define AT91C_CAN0_ECR ((AT91_REG *) 0xFFF80020) // (CAN0) Error Counter Register -// ========== Register definition for CAN1_MB0 peripheral ========== -#define AT91C_CAN1_MB0_MDH ((AT91_REG *) 0xFFF84218) // (CAN1_MB0) MailBox Data High Register -#define AT91C_CAN1_MB0_MSR ((AT91_REG *) 0xFFF84210) // (CAN1_MB0) MailBox Status Register -#define AT91C_CAN1_MB0_MID ((AT91_REG *) 0xFFF84208) // (CAN1_MB0) MailBox ID Register -#define AT91C_CAN1_MB0_MMR ((AT91_REG *) 0xFFF84200) // (CAN1_MB0) MailBox Mode Register -#define AT91C_CAN1_MB0_MCR ((AT91_REG *) 0xFFF8421C) // (CAN1_MB0) MailBox Control Register -#define AT91C_CAN1_MB0_MDL ((AT91_REG *) 0xFFF84214) // (CAN1_MB0) MailBox Data Low Register -#define AT91C_CAN1_MB0_MFID ((AT91_REG *) 0xFFF8420C) // (CAN1_MB0) MailBox Family ID Register -#define AT91C_CAN1_MB0_MAM ((AT91_REG *) 0xFFF84204) // (CAN1_MB0) MailBox Acceptance Mask Register -// ========== Register definition for CAN1_MB1 peripheral ========== -#define AT91C_CAN1_MB1_MDH ((AT91_REG *) 0xFFF84238) // (CAN1_MB1) MailBox Data High Register -#define AT91C_CAN1_MB1_MSR ((AT91_REG *) 0xFFF84230) // (CAN1_MB1) MailBox Status Register -#define AT91C_CAN1_MB1_MID ((AT91_REG *) 0xFFF84228) // (CAN1_MB1) MailBox ID Register -#define AT91C_CAN1_MB1_MMR ((AT91_REG *) 0xFFF84220) // (CAN1_MB1) MailBox Mode Register -#define AT91C_CAN1_MB1_MCR ((AT91_REG *) 0xFFF8423C) // (CAN1_MB1) MailBox Control Register -#define AT91C_CAN1_MB1_MDL ((AT91_REG *) 0xFFF84234) // (CAN1_MB1) MailBox Data Low Register -#define AT91C_CAN1_MB1_MFID ((AT91_REG *) 0xFFF8422C) // (CAN1_MB1) MailBox Family ID Register -#define AT91C_CAN1_MB1_MAM ((AT91_REG *) 0xFFF84224) // (CAN1_MB1) MailBox Acceptance Mask Register -// ========== Register definition for CAN1_MB2 peripheral ========== -#define AT91C_CAN1_MB2_MDH ((AT91_REG *) 0xFFF84258) // (CAN1_MB2) MailBox Data High Register -#define AT91C_CAN1_MB2_MSR ((AT91_REG *) 0xFFF84250) // (CAN1_MB2) MailBox Status Register -#define AT91C_CAN1_MB2_MID ((AT91_REG *) 0xFFF84248) // (CAN1_MB2) MailBox ID Register -#define AT91C_CAN1_MB2_MMR ((AT91_REG *) 0xFFF84240) // (CAN1_MB2) MailBox Mode Register -#define AT91C_CAN1_MB2_MCR ((AT91_REG *) 0xFFF8425C) // (CAN1_MB2) MailBox Control Register -#define AT91C_CAN1_MB2_MDL ((AT91_REG *) 0xFFF84254) // (CAN1_MB2) MailBox Data Low Register -#define AT91C_CAN1_MB2_MFID ((AT91_REG *) 0xFFF8424C) // (CAN1_MB2) MailBox Family ID Register -#define AT91C_CAN1_MB2_MAM ((AT91_REG *) 0xFFF84244) // (CAN1_MB2) MailBox Acceptance Mask Register -// ========== Register definition for CAN1_MB3 peripheral ========== -#define AT91C_CAN1_MB3_MCR ((AT91_REG *) 0xFFF8427C) // (CAN1_MB3) MailBox Control Register -#define AT91C_CAN1_MB3_MFID ((AT91_REG *) 0xFFF8426C) // (CAN1_MB3) MailBox Family ID Register -#define AT91C_CAN1_MB3_MAM ((AT91_REG *) 0xFFF84264) // (CAN1_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN1_MB3_MMR ((AT91_REG *) 0xFFF84260) // (CAN1_MB3) MailBox Mode Register -#define AT91C_CAN1_MB3_MDH ((AT91_REG *) 0xFFF84278) // (CAN1_MB3) MailBox Data High Register -#define AT91C_CAN1_MB3_MSR ((AT91_REG *) 0xFFF84270) // (CAN1_MB3) MailBox Status Register -#define AT91C_CAN1_MB3_MID ((AT91_REG *) 0xFFF84268) // (CAN1_MB3) MailBox ID Register -#define AT91C_CAN1_MB3_MDL ((AT91_REG *) 0xFFF84274) // (CAN1_MB3) MailBox Data Low Register -// ========== Register definition for CAN1_MB4 peripheral ========== -#define AT91C_CAN1_MB4_MCR ((AT91_REG *) 0xFFF8429C) // (CAN1_MB4) MailBox Control Register -#define AT91C_CAN1_MB4_MDL ((AT91_REG *) 0xFFF84294) // (CAN1_MB4) MailBox Data Low Register -#define AT91C_CAN1_MB4_MFID ((AT91_REG *) 0xFFF8428C) // (CAN1_MB4) MailBox Family ID Register -#define AT91C_CAN1_MB4_MAM ((AT91_REG *) 0xFFF84284) // (CAN1_MB4) MailBox Acceptance Mask Register -#define AT91C_CAN1_MB4_MDH ((AT91_REG *) 0xFFF84298) // (CAN1_MB4) MailBox Data High Register -#define AT91C_CAN1_MB4_MSR ((AT91_REG *) 0xFFF84290) // (CAN1_MB4) MailBox Status Register -#define AT91C_CAN1_MB4_MID ((AT91_REG *) 0xFFF84288) // (CAN1_MB4) MailBox ID Register -#define AT91C_CAN1_MB4_MMR ((AT91_REG *) 0xFFF84280) // (CAN1_MB4) MailBox Mode Register -// ========== Register definition for CAN1_MB5 peripheral ========== -#define AT91C_CAN1_MB5_MCR ((AT91_REG *) 0xFFF842BC) // (CAN1_MB5) MailBox Control Register -#define AT91C_CAN1_MB5_MDL ((AT91_REG *) 0xFFF842B4) // (CAN1_MB5) MailBox Data Low Register -#define AT91C_CAN1_MB5_MFID ((AT91_REG *) 0xFFF842AC) // (CAN1_MB5) MailBox Family ID Register -#define AT91C_CAN1_MB5_MAM ((AT91_REG *) 0xFFF842A4) // (CAN1_MB5) MailBox Acceptance Mask Register -#define AT91C_CAN1_MB5_MDH ((AT91_REG *) 0xFFF842B8) // (CAN1_MB5) MailBox Data High Register -#define AT91C_CAN1_MB5_MSR ((AT91_REG *) 0xFFF842B0) // (CAN1_MB5) MailBox Status Register -#define AT91C_CAN1_MB5_MID ((AT91_REG *) 0xFFF842A8) // (CAN1_MB5) MailBox ID Register -#define AT91C_CAN1_MB5_MMR ((AT91_REG *) 0xFFF842A0) // (CAN1_MB5) MailBox Mode Register -// ========== Register definition for CAN1_MB6 peripheral ========== -#define AT91C_CAN1_MB6_MDH ((AT91_REG *) 0xFFF842D8) // (CAN1_MB6) MailBox Data High Register -#define AT91C_CAN1_MB6_MSR ((AT91_REG *) 0xFFF842D0) // (CAN1_MB6) MailBox Status Register -#define AT91C_CAN1_MB6_MID ((AT91_REG *) 0xFFF842C8) // (CAN1_MB6) MailBox ID Register -#define AT91C_CAN1_MB6_MMR ((AT91_REG *) 0xFFF842C0) // (CAN1_MB6) MailBox Mode Register -#define AT91C_CAN1_MB6_MAM ((AT91_REG *) 0xFFF842C4) // (CAN1_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN1_MB6_MCR ((AT91_REG *) 0xFFF842DC) // (CAN1_MB6) MailBox Control Register -#define AT91C_CAN1_MB6_MDL ((AT91_REG *) 0xFFF842D4) // (CAN1_MB6) MailBox Data Low Register -#define AT91C_CAN1_MB6_MFID ((AT91_REG *) 0xFFF842CC) // (CAN1_MB6) MailBox Family ID Register -// ========== Register definition for CAN1_MB7 peripheral ========== -#define AT91C_CAN1_MB7_MDH ((AT91_REG *) 0xFFF842F8) // (CAN1_MB7) MailBox Data High Register -#define AT91C_CAN1_MB7_MSR ((AT91_REG *) 0xFFF842F0) // (CAN1_MB7) MailBox Status Register -#define AT91C_CAN1_MB7_MID ((AT91_REG *) 0xFFF842E8) // (CAN1_MB7) MailBox ID Register -#define AT91C_CAN1_MB7_MMR ((AT91_REG *) 0xFFF842E0) // (CAN1_MB7) MailBox Mode Register -#define AT91C_CAN1_MB7_MCR ((AT91_REG *) 0xFFF842FC) // (CAN1_MB7) MailBox Control Register -#define AT91C_CAN1_MB7_MDL ((AT91_REG *) 0xFFF842F4) // (CAN1_MB7) MailBox Data Low Register -#define AT91C_CAN1_MB7_MFID ((AT91_REG *) 0xFFF842EC) // (CAN1_MB7) MailBox Family ID Register -#define AT91C_CAN1_MB7_MAM ((AT91_REG *) 0xFFF842E4) // (CAN1_MB7) MailBox Acceptance Mask Register -// ========== Register definition for CAN1_MB8 peripheral ========== -#define AT91C_CAN1_MB8_MDH ((AT91_REG *) 0xFFF84318) // (CAN1_MB8) MailBox Data High Register -#define AT91C_CAN1_MB8_MSR ((AT91_REG *) 0xFFF84310) // (CAN1_MB8) MailBox Status Register -#define AT91C_CAN1_MB8_MID ((AT91_REG *) 0xFFF84308) // (CAN1_MB8) MailBox ID Register -#define AT91C_CAN1_MB8_MMR ((AT91_REG *) 0xFFF84300) // (CAN1_MB8) MailBox Mode Register -#define AT91C_CAN1_MB8_MCR ((AT91_REG *) 0xFFF8431C) // (CAN1_MB8) MailBox Control Register -#define AT91C_CAN1_MB8_MDL ((AT91_REG *) 0xFFF84314) // (CAN1_MB8) MailBox Data Low Register -#define AT91C_CAN1_MB8_MFID ((AT91_REG *) 0xFFF8430C) // (CAN1_MB8) MailBox Family ID Register -#define AT91C_CAN1_MB8_MAM ((AT91_REG *) 0xFFF84304) // (CAN1_MB8) MailBox Acceptance Mask Register -// ========== Register definition for CAN1_MB9 peripheral ========== -#define AT91C_CAN1_MB9_MID ((AT91_REG *) 0xFFF84328) // (CAN1_MB9) MailBox ID Register -#define AT91C_CAN1_MB9_MDH ((AT91_REG *) 0xFFF84338) // (CAN1_MB9) MailBox Data High Register -#define AT91C_CAN1_MB9_MSR ((AT91_REG *) 0xFFF84330) // (CAN1_MB9) MailBox Status Register -#define AT91C_CAN1_MB9_MMR ((AT91_REG *) 0xFFF84320) // (CAN1_MB9) MailBox Mode Register -#define AT91C_CAN1_MB9_MCR ((AT91_REG *) 0xFFF8433C) // (CAN1_MB9) MailBox Control Register -#define AT91C_CAN1_MB9_MDL ((AT91_REG *) 0xFFF84334) // (CAN1_MB9) MailBox Data Low Register -#define AT91C_CAN1_MB9_MFID ((AT91_REG *) 0xFFF8432C) // (CAN1_MB9) MailBox Family ID Register -#define AT91C_CAN1_MB9_MAM ((AT91_REG *) 0xFFF84324) // (CAN1_MB9) MailBox Acceptance Mask Register -// ========== Register definition for CAN1_MB10 peripheral ========== -#define AT91C_CAN1_MB10_MDH ((AT91_REG *) 0xFFF84358) // (CAN1_MB10) MailBox Data High Register -#define AT91C_CAN1_MB10_MSR ((AT91_REG *) 0xFFF84350) // (CAN1_MB10) MailBox Status Register -#define AT91C_CAN1_MB10_MID ((AT91_REG *) 0xFFF84348) // (CAN1_MB10) MailBox ID Register -#define AT91C_CAN1_MB10_MMR ((AT91_REG *) 0xFFF84340) // (CAN1_MB10) MailBox Mode Register -#define AT91C_CAN1_MB10_MCR ((AT91_REG *) 0xFFF8435C) // (CAN1_MB10) MailBox Control Register -#define AT91C_CAN1_MB10_MDL ((AT91_REG *) 0xFFF84354) // (CAN1_MB10) MailBox Data Low Register -#define AT91C_CAN1_MB10_MFID ((AT91_REG *) 0xFFF8434C) // (CAN1_MB10) MailBox Family ID Register -#define AT91C_CAN1_MB10_MAM ((AT91_REG *) 0xFFF84344) // (CAN1_MB10) MailBox Acceptance Mask Register -// ========== Register definition for CAN1_MB11 peripheral ========== -#define AT91C_CAN1_MB11_MDH ((AT91_REG *) 0xFFF84378) // (CAN1_MB11) MailBox Data High Register -#define AT91C_CAN1_MB11_MSR ((AT91_REG *) 0xFFF84370) // (CAN1_MB11) MailBox Status Register -#define AT91C_CAN1_MB11_MID ((AT91_REG *) 0xFFF84368) // (CAN1_MB11) MailBox ID Register -#define AT91C_CAN1_MB11_MMR ((AT91_REG *) 0xFFF84360) // (CAN1_MB11) MailBox Mode Register -#define AT91C_CAN1_MB11_MCR ((AT91_REG *) 0xFFF8437C) // (CAN1_MB11) MailBox Control Register -#define AT91C_CAN1_MB11_MDL ((AT91_REG *) 0xFFF84374) // (CAN1_MB11) MailBox Data Low Register -#define AT91C_CAN1_MB11_MFID ((AT91_REG *) 0xFFF8436C) // (CAN1_MB11) MailBox Family ID Register -#define AT91C_CAN1_MB11_MAM ((AT91_REG *) 0xFFF84364) // (CAN1_MB11) MailBox Acceptance Mask Register -// ========== Register definition for CAN1_MB12 peripheral ========== -#define AT91C_CAN1_MB12_MDH ((AT91_REG *) 0xFFF84398) // (CAN1_MB12) MailBox Data High Register -#define AT91C_CAN1_MB12_MSR ((AT91_REG *) 0xFFF84390) // (CAN1_MB12) MailBox Status Register -#define AT91C_CAN1_MB12_MID ((AT91_REG *) 0xFFF84388) // (CAN1_MB12) MailBox ID Register -#define AT91C_CAN1_MB12_MMR ((AT91_REG *) 0xFFF84380) // (CAN1_MB12) MailBox Mode Register -#define AT91C_CAN1_MB12_MCR ((AT91_REG *) 0xFFF8439C) // (CAN1_MB12) MailBox Control Register -#define AT91C_CAN1_MB12_MDL ((AT91_REG *) 0xFFF84394) // (CAN1_MB12) MailBox Data Low Register -#define AT91C_CAN1_MB12_MFID ((AT91_REG *) 0xFFF8438C) // (CAN1_MB12) MailBox Family ID Register -#define AT91C_CAN1_MB12_MAM ((AT91_REG *) 0xFFF84384) // (CAN1_MB12) MailBox Acceptance Mask Register -// ========== Register definition for CAN1_MB13 peripheral ========== -#define AT91C_CAN1_MB13_MDH ((AT91_REG *) 0xFFF843B8) // (CAN1_MB13) MailBox Data High Register -#define AT91C_CAN1_MB13_MSR ((AT91_REG *) 0xFFF843B0) // (CAN1_MB13) MailBox Status Register -#define AT91C_CAN1_MB13_MID ((AT91_REG *) 0xFFF843A8) // (CAN1_MB13) MailBox ID Register -#define AT91C_CAN1_MB13_MMR ((AT91_REG *) 0xFFF843A0) // (CAN1_MB13) MailBox Mode Register -#define AT91C_CAN1_MB13_MCR ((AT91_REG *) 0xFFF843BC) // (CAN1_MB13) MailBox Control Register -#define AT91C_CAN1_MB13_MDL ((AT91_REG *) 0xFFF843B4) // (CAN1_MB13) MailBox Data Low Register -#define AT91C_CAN1_MB13_MFID ((AT91_REG *) 0xFFF843AC) // (CAN1_MB13) MailBox Family ID Register -#define AT91C_CAN1_MB13_MAM ((AT91_REG *) 0xFFF843A4) // (CAN1_MB13) MailBox Acceptance Mask Register -// ========== Register definition for CAN1_MB14 peripheral ========== -#define AT91C_CAN1_MB14_MDH ((AT91_REG *) 0xFFF843D8) // (CAN1_MB14) MailBox Data High Register -#define AT91C_CAN1_MB14_MSR ((AT91_REG *) 0xFFF843D0) // (CAN1_MB14) MailBox Status Register -#define AT91C_CAN1_MB14_MID ((AT91_REG *) 0xFFF843C8) // (CAN1_MB14) MailBox ID Register -#define AT91C_CAN1_MB14_MMR ((AT91_REG *) 0xFFF843C0) // (CAN1_MB14) MailBox Mode Register -#define AT91C_CAN1_MB14_MCR ((AT91_REG *) 0xFFF843DC) // (CAN1_MB14) MailBox Control Register -#define AT91C_CAN1_MB14_MDL ((AT91_REG *) 0xFFF843D4) // (CAN1_MB14) MailBox Data Low Register -#define AT91C_CAN1_MB14_MFID ((AT91_REG *) 0xFFF843CC) // (CAN1_MB14) MailBox Family ID Register -#define AT91C_CAN1_MB14_MAM ((AT91_REG *) 0xFFF843C4) // (CAN1_MB14) MailBox Acceptance Mask Register -// ========== Register definition for CAN1_MB15 peripheral ========== -#define AT91C_CAN1_MB15_MDH ((AT91_REG *) 0xFFF843F8) // (CAN1_MB15) MailBox Data High Register -#define AT91C_CAN1_MB15_MSR ((AT91_REG *) 0xFFF843F0) // (CAN1_MB15) MailBox Status Register -#define AT91C_CAN1_MB15_MID ((AT91_REG *) 0xFFF843E8) // (CAN1_MB15) MailBox ID Register -#define AT91C_CAN1_MB15_MMR ((AT91_REG *) 0xFFF843E0) // (CAN1_MB15) MailBox Mode Register -#define AT91C_CAN1_MB15_MCR ((AT91_REG *) 0xFFF843FC) // (CAN1_MB15) MailBox Control Register -#define AT91C_CAN1_MB15_MDL ((AT91_REG *) 0xFFF843F4) // (CAN1_MB15) MailBox Data Low Register -#define AT91C_CAN1_MB15_MFID ((AT91_REG *) 0xFFF843EC) // (CAN1_MB15) MailBox Family ID Register -#define AT91C_CAN1_MB15_MAM ((AT91_REG *) 0xFFF843E4) // (CAN1_MB15) MailBox Acceptance Mask Register -// ========== Register definition for CAN1 peripheral ========== -#define AT91C_CAN1_MR ((AT91_REG *) 0xFFF84000) // (CAN1) Mode Register -#define AT91C_CAN1_VR ((AT91_REG *) 0xFFF840FC) // (CAN1) Version Register -#define AT91C_CAN1_TIMESTP ((AT91_REG *) 0xFFF8401C) // (CAN1) Time Stamp Register -#define AT91C_CAN1_BR ((AT91_REG *) 0xFFF84014) // (CAN1) Baudrate Register -#define AT91C_CAN1_IMR ((AT91_REG *) 0xFFF8400C) // (CAN1) Interrupt Mask Register -#define AT91C_CAN1_IER ((AT91_REG *) 0xFFF84004) // (CAN1) Interrupt Enable Register -#define AT91C_CAN1_ACR ((AT91_REG *) 0xFFF84028) // (CAN1) Abort Command Register -#define AT91C_CAN1_ECR ((AT91_REG *) 0xFFF84020) // (CAN1) Error Counter Register -#define AT91C_CAN1_TIM ((AT91_REG *) 0xFFF84018) // (CAN1) Timer Register -#define AT91C_CAN1_SR ((AT91_REG *) 0xFFF84010) // (CAN1) Status Register -#define AT91C_CAN1_TCR ((AT91_REG *) 0xFFF84024) // (CAN1) Transfer Command Register -#define AT91C_CAN1_IDR ((AT91_REG *) 0xFFF84008) // (CAN1) Interrupt Disable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TCB0 peripheral ========== -#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register -#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register -// ========== Register definition for TC3 peripheral ========== -#define AT91C_TC3_IMR ((AT91_REG *) 0xFFFA402C) // (TC3) Interrupt Mask Register -#define AT91C_TC3_CV ((AT91_REG *) 0xFFFA4010) // (TC3) Counter Value -#define AT91C_TC3_CCR ((AT91_REG *) 0xFFFA4000) // (TC3) Channel Control Register -#define AT91C_TC3_IER ((AT91_REG *) 0xFFFA4024) // (TC3) Interrupt Enable Register -#define AT91C_TC3_CMR ((AT91_REG *) 0xFFFA4004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC3_RA ((AT91_REG *) 0xFFFA4014) // (TC3) Register A -#define AT91C_TC3_RC ((AT91_REG *) 0xFFFA401C) // (TC3) Register C -#define AT91C_TC3_IDR ((AT91_REG *) 0xFFFA4028) // (TC3) Interrupt Disable Register -#define AT91C_TC3_RB ((AT91_REG *) 0xFFFA4018) // (TC3) Register B -#define AT91C_TC3_SR ((AT91_REG *) 0xFFFA4020) // (TC3) Status Register -// ========== Register definition for TC4 peripheral ========== -#define AT91C_TC4_IMR ((AT91_REG *) 0xFFFA406C) // (TC4) Interrupt Mask Register -#define AT91C_TC4_IER ((AT91_REG *) 0xFFFA4064) // (TC4) Interrupt Enable Register -#define AT91C_TC4_RC ((AT91_REG *) 0xFFFA405C) // (TC4) Register C -#define AT91C_TC4_RA ((AT91_REG *) 0xFFFA4054) // (TC4) Register A -#define AT91C_TC4_CMR ((AT91_REG *) 0xFFFA4044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC4_IDR ((AT91_REG *) 0xFFFA4068) // (TC4) Interrupt Disable Register -#define AT91C_TC4_SR ((AT91_REG *) 0xFFFA4060) // (TC4) Status Register -#define AT91C_TC4_RB ((AT91_REG *) 0xFFFA4058) // (TC4) Register B -#define AT91C_TC4_CV ((AT91_REG *) 0xFFFA4050) // (TC4) Counter Value -#define AT91C_TC4_CCR ((AT91_REG *) 0xFFFA4040) // (TC4) Channel Control Register -// ========== Register definition for TC5 peripheral ========== -#define AT91C_TC5_CMR ((AT91_REG *) 0xFFFA4084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC5_IDR ((AT91_REG *) 0xFFFA40A8) // (TC5) Interrupt Disable Register -#define AT91C_TC5_SR ((AT91_REG *) 0xFFFA40A0) // (TC5) Status Register -#define AT91C_TC5_RB ((AT91_REG *) 0xFFFA4098) // (TC5) Register B -#define AT91C_TC5_CV ((AT91_REG *) 0xFFFA4090) // (TC5) Counter Value -#define AT91C_TC5_CCR ((AT91_REG *) 0xFFFA4080) // (TC5) Channel Control Register -#define AT91C_TC5_IMR ((AT91_REG *) 0xFFFA40AC) // (TC5) Interrupt Mask Register -#define AT91C_TC5_IER ((AT91_REG *) 0xFFFA40A4) // (TC5) Interrupt Enable Register -#define AT91C_TC5_RC ((AT91_REG *) 0xFFFA409C) // (TC5) Register C -#define AT91C_TC5_RA ((AT91_REG *) 0xFFFA4094) // (TC5) Register A -// ========== Register definition for TCB1 peripheral ========== -#define AT91C_TCB1_BCR ((AT91_REG *) 0xFFFA40C0) // (TCB1) TC Block Control Register -#define AT91C_TCB1_BMR ((AT91_REG *) 0xFFFA40C4) // (TCB1) TC Block Mode Register -// ========== Register definition for TC6 peripheral ========== -#define AT91C_TC6_IDR ((AT91_REG *) 0xFFFA8028) // (TC6) Interrupt Disable Register -#define AT91C_TC6_SR ((AT91_REG *) 0xFFFA8020) // (TC6) Status Register -#define AT91C_TC6_RB ((AT91_REG *) 0xFFFA8018) // (TC6) Register B -#define AT91C_TC6_CV ((AT91_REG *) 0xFFFA8010) // (TC6) Counter Value -#define AT91C_TC6_CCR ((AT91_REG *) 0xFFFA8000) // (TC6) Channel Control Register -#define AT91C_TC6_IMR ((AT91_REG *) 0xFFFA802C) // (TC6) Interrupt Mask Register -#define AT91C_TC6_IER ((AT91_REG *) 0xFFFA8024) // (TC6) Interrupt Enable Register -#define AT91C_TC6_RC ((AT91_REG *) 0xFFFA801C) // (TC6) Register C -#define AT91C_TC6_RA ((AT91_REG *) 0xFFFA8014) // (TC6) Register A -#define AT91C_TC6_CMR ((AT91_REG *) 0xFFFA8004) // (TC6) Channel Mode Register (Capture Mode / Waveform Mode) -// ========== Register definition for TC7 peripheral ========== -#define AT91C_TC7_IDR ((AT91_REG *) 0xFFFA8068) // (TC7) Interrupt Disable Register -#define AT91C_TC7_SR ((AT91_REG *) 0xFFFA8060) // (TC7) Status Register -#define AT91C_TC7_RB ((AT91_REG *) 0xFFFA8058) // (TC7) Register B -#define AT91C_TC7_CV ((AT91_REG *) 0xFFFA8050) // (TC7) Counter Value -#define AT91C_TC7_CCR ((AT91_REG *) 0xFFFA8040) // (TC7) Channel Control Register -#define AT91C_TC7_IMR ((AT91_REG *) 0xFFFA806C) // (TC7) Interrupt Mask Register -#define AT91C_TC7_IER ((AT91_REG *) 0xFFFA8064) // (TC7) Interrupt Enable Register -#define AT91C_TC7_RC ((AT91_REG *) 0xFFFA805C) // (TC7) Register C -#define AT91C_TC7_RA ((AT91_REG *) 0xFFFA8054) // (TC7) Register A -#define AT91C_TC7_CMR ((AT91_REG *) 0xFFFA8044) // (TC7) Channel Mode Register (Capture Mode / Waveform Mode) -// ========== Register definition for TC8 peripheral ========== -#define AT91C_TC8_CV ((AT91_REG *) 0xFFFA8090) // (TC8) Counter Value -#define AT91C_TC8_CCR ((AT91_REG *) 0xFFFA8080) // (TC8) Channel Control Register -#define AT91C_TC8_IMR ((AT91_REG *) 0xFFFA80AC) // (TC8) Interrupt Mask Register -#define AT91C_TC8_IER ((AT91_REG *) 0xFFFA80A4) // (TC8) Interrupt Enable Register -#define AT91C_TC8_RC ((AT91_REG *) 0xFFFA809C) // (TC8) Register C -#define AT91C_TC8_RA ((AT91_REG *) 0xFFFA8094) // (TC8) Register A -#define AT91C_TC8_CMR ((AT91_REG *) 0xFFFA8084) // (TC8) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC8_IDR ((AT91_REG *) 0xFFFA80A8) // (TC8) Interrupt Disable Register -#define AT91C_TC8_SR ((AT91_REG *) 0xFFFA80A0) // (TC8) Status Register -#define AT91C_TC8_RB ((AT91_REG *) 0xFFFA8098) // (TC8) Register B -// ========== Register definition for TCB2 peripheral ========== -#define AT91C_TCB2_BMR ((AT91_REG *) 0xFFFA80C4) // (TCB2) TC Block Mode Register -#define AT91C_TCB2_BCR ((AT91_REG *) 0xFFFA80C0) // (TCB2) TC Block Control Register -// ========== Register definition for PDC_MCI peripheral ========== -#define AT91C_MCI_RCR ((AT91_REG *) 0xFFFAC104) // (PDC_MCI) Receive Counter Register -#define AT91C_MCI_PTCR ((AT91_REG *) 0xFFFAC120) // (PDC_MCI) PDC Transfer Control Register -#define AT91C_MCI_TNPR ((AT91_REG *) 0xFFFAC118) // (PDC_MCI) Transmit Next Pointer Register -#define AT91C_MCI_RNPR ((AT91_REG *) 0xFFFAC110) // (PDC_MCI) Receive Next Pointer Register -#define AT91C_MCI_TPR ((AT91_REG *) 0xFFFAC108) // (PDC_MCI) Transmit Pointer Register -#define AT91C_MCI_RPR ((AT91_REG *) 0xFFFAC100) // (PDC_MCI) Receive Pointer Register -#define AT91C_MCI_PTSR ((AT91_REG *) 0xFFFAC124) // (PDC_MCI) PDC Transfer Status Register -#define AT91C_MCI_TNCR ((AT91_REG *) 0xFFFAC11C) // (PDC_MCI) Transmit Next Counter Register -#define AT91C_MCI_RNCR ((AT91_REG *) 0xFFFAC114) // (PDC_MCI) Receive Next Counter Register -#define AT91C_MCI_TCR ((AT91_REG *) 0xFFFAC10C) // (PDC_MCI) Transmit Counter Register -// ========== Register definition for MCI peripheral ========== -#define AT91C_MCI_IER ((AT91_REG *) 0xFFFAC044) // (MCI) MCI Interrupt Enable Register -#define AT91C_MCI_TDR ((AT91_REG *) 0xFFFAC034) // (MCI) MCI Transmit Data Register -#define AT91C_MCI_IDR ((AT91_REG *) 0xFFFAC048) // (MCI) MCI Interrupt Disable Register -#define AT91C_MCI_SR ((AT91_REG *) 0xFFFAC040) // (MCI) MCI Status Register -#define AT91C_MCI_DTOR ((AT91_REG *) 0xFFFAC008) // (MCI) MCI Data Timeout Register -#define AT91C_MCI_CR ((AT91_REG *) 0xFFFAC000) // (MCI) MCI Control Register -#define AT91C_MCI_IMR ((AT91_REG *) 0xFFFAC04C) // (MCI) MCI Interrupt Mask Register -#define AT91C_MCI_MR ((AT91_REG *) 0xFFFAC004) // (MCI) MCI Mode Register -#define AT91C_MCI_SDCR ((AT91_REG *) 0xFFFAC00C) // (MCI) MCI SD Card Register -#define AT91C_MCI_CMDR ((AT91_REG *) 0xFFFAC014) // (MCI) MCI Command Register -#define AT91C_MCI_ARGR ((AT91_REG *) 0xFFFAC010) // (MCI) MCI Argument Register -#define AT91C_MCI_RSPR ((AT91_REG *) 0xFFFAC020) // (MCI) MCI Response Register -#define AT91C_MCI_RDR ((AT91_REG *) 0xFFFAC030) // (MCI) MCI Receive Data Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US2 peripheral ========== -#define AT91C_US2_PTSR ((AT91_REG *) 0xFFFC8124) // (PDC_US2) PDC Transfer Status Register -#define AT91C_US2_TNCR ((AT91_REG *) 0xFFFC811C) // (PDC_US2) Transmit Next Counter Register -#define AT91C_US2_RNCR ((AT91_REG *) 0xFFFC8114) // (PDC_US2) Receive Next Counter Register -#define AT91C_US2_TCR ((AT91_REG *) 0xFFFC810C) // (PDC_US2) Transmit Counter Register -#define AT91C_US2_PTCR ((AT91_REG *) 0xFFFC8120) // (PDC_US2) PDC Transfer Control Register -#define AT91C_US2_RCR ((AT91_REG *) 0xFFFC8104) // (PDC_US2) Receive Counter Register -#define AT91C_US2_TNPR ((AT91_REG *) 0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register -#define AT91C_US2_RPR ((AT91_REG *) 0xFFFC8100) // (PDC_US2) Receive Pointer Register -#define AT91C_US2_TPR ((AT91_REG *) 0xFFFC8108) // (PDC_US2) Transmit Pointer Register -#define AT91C_US2_RNPR ((AT91_REG *) 0xFFFC8110) // (PDC_US2) Receive Next Pointer Register -// ========== Register definition for US2 peripheral ========== -#define AT91C_US2_FIDI ((AT91_REG *) 0xFFFC8040) // (US2) FI_DI_Ratio Register -#define AT91C_US2_TTGR ((AT91_REG *) 0xFFFC8028) // (US2) Transmitter Time-guard Register -#define AT91C_US2_BRGR ((AT91_REG *) 0xFFFC8020) // (US2) Baud Rate Generator Register -#define AT91C_US2_RHR ((AT91_REG *) 0xFFFC8018) // (US2) Receiver Holding Register -#define AT91C_US2_IMR ((AT91_REG *) 0xFFFC8010) // (US2) Interrupt Mask Register -#define AT91C_US2_IER ((AT91_REG *) 0xFFFC8008) // (US2) Interrupt Enable Register -#define AT91C_US2_CR ((AT91_REG *) 0xFFFC8000) // (US2) Control Register -#define AT91C_US2_IF ((AT91_REG *) 0xFFFC804C) // (US2) IRDA_FILTER Register -#define AT91C_US2_NER ((AT91_REG *) 0xFFFC8044) // (US2) Nb Errors Register -#define AT91C_US2_RTOR ((AT91_REG *) 0xFFFC8024) // (US2) Receiver Time-out Register -#define AT91C_US2_THR ((AT91_REG *) 0xFFFC801C) // (US2) Transmitter Holding Register -#define AT91C_US2_CSR ((AT91_REG *) 0xFFFC8014) // (US2) Channel Status Register -#define AT91C_US2_IDR ((AT91_REG *) 0xFFFC800C) // (US2) Interrupt Disable Register -#define AT91C_US2_MR ((AT91_REG *) 0xFFFC8004) // (US2) Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH4 peripheral ========== -#define AT91C_PWMC_CH4_CUPDR ((AT91_REG *) 0xFFFCC290) // (PWMC_CH4) Channel Update Register -#define AT91C_PWMC_CH4_CPRDR ((AT91_REG *) 0xFFFCC288) // (PWMC_CH4) Channel Period Register -#define AT91C_PWMC_CH4_CMR ((AT91_REG *) 0xFFFCC280) // (PWMC_CH4) Channel Mode Register -#define AT91C_PWMC_CH4_Reserved ((AT91_REG *) 0xFFFCC294) // (PWMC_CH4) Reserved -#define AT91C_PWMC_CH4_CCNTR ((AT91_REG *) 0xFFFCC28C) // (PWMC_CH4) Channel Counter Register -#define AT91C_PWMC_CH4_CDTYR ((AT91_REG *) 0xFFFCC284) // (PWMC_CH4) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH5 peripheral ========== -#define AT91C_PWMC_CH5_CUPDR ((AT91_REG *) 0xFFFCC2B0) // (PWMC_CH5) Channel Update Register -#define AT91C_PWMC_CH5_CPRDR ((AT91_REG *) 0xFFFCC2A8) // (PWMC_CH5) Channel Period Register -#define AT91C_PWMC_CH5_CMR ((AT91_REG *) 0xFFFCC2A0) // (PWMC_CH5) Channel Mode Register -#define AT91C_PWMC_CH5_Reserved ((AT91_REG *) 0xFFFCC2B4) // (PWMC_CH5) Reserved -#define AT91C_PWMC_CH5_CCNTR ((AT91_REG *) 0xFFFCC2AC) // (PWMC_CH5) Channel Counter Register -#define AT91C_PWMC_CH5_CDTYR ((AT91_REG *) 0xFFFCC2A4) // (PWMC_CH5) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH6 peripheral ========== -#define AT91C_PWMC_CH6_Reserved ((AT91_REG *) 0xFFFCC2D4) // (PWMC_CH6) Reserved -#define AT91C_PWMC_CH6_CCNTR ((AT91_REG *) 0xFFFCC2CC) // (PWMC_CH6) Channel Counter Register -#define AT91C_PWMC_CH6_CDTYR ((AT91_REG *) 0xFFFCC2C4) // (PWMC_CH6) Channel Duty Cycle Register -#define AT91C_PWMC_CH6_CUPDR ((AT91_REG *) 0xFFFCC2D0) // (PWMC_CH6) Channel Update Register -#define AT91C_PWMC_CH6_CPRDR ((AT91_REG *) 0xFFFCC2C8) // (PWMC_CH6) Channel Period Register -#define AT91C_PWMC_CH6_CMR ((AT91_REG *) 0xFFFCC2C0) // (PWMC_CH6) Channel Mode Register -// ========== Register definition for PWMC_CH7 peripheral ========== -#define AT91C_PWMC_CH7_Reserved ((AT91_REG *) 0xFFFCC2F4) // (PWMC_CH7) Reserved -#define AT91C_PWMC_CH7_CCNTR ((AT91_REG *) 0xFFFCC2EC) // (PWMC_CH7) Channel Counter Register -#define AT91C_PWMC_CH7_CDTYR ((AT91_REG *) 0xFFFCC2E4) // (PWMC_CH7) Channel Duty Cycle Register -#define AT91C_PWMC_CH7_CUPDR ((AT91_REG *) 0xFFFCC2F0) // (PWMC_CH7) Channel Update Register -#define AT91C_PWMC_CH7_CPRDR ((AT91_REG *) 0xFFFCC2E8) // (PWMC_CH7) Channel Period Register -#define AT91C_PWMC_CH7_CMR ((AT91_REG *) 0xFFFCC2E0) // (PWMC_CH7) Channel Mode Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -// ========== Register definition for PDC_SSC0 peripheral ========== -#define AT91C_SSC0_PTCR ((AT91_REG *) 0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register -#define AT91C_SSC0_TNPR ((AT91_REG *) 0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register -#define AT91C_SSC0_RNPR ((AT91_REG *) 0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register -#define AT91C_SSC0_TPR ((AT91_REG *) 0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register -#define AT91C_SSC0_RPR ((AT91_REG *) 0xFFFD0100) // (PDC_SSC0) Receive Pointer Register -#define AT91C_SSC0_PTSR ((AT91_REG *) 0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register -#define AT91C_SSC0_TNCR ((AT91_REG *) 0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register -#define AT91C_SSC0_RNCR ((AT91_REG *) 0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register -#define AT91C_SSC0_TCR ((AT91_REG *) 0xFFFD010C) // (PDC_SSC0) Transmit Counter Register -#define AT91C_SSC0_RCR ((AT91_REG *) 0xFFFD0104) // (PDC_SSC0) Receive Counter Register -// ========== Register definition for SSC0 peripheral ========== -#define AT91C_SSC0_IMR ((AT91_REG *) 0xFFFD004C) // (SSC0) Interrupt Mask Register -#define AT91C_SSC0_IER ((AT91_REG *) 0xFFFD0044) // (SSC0) Interrupt Enable Register -#define AT91C_SSC0_TSHR ((AT91_REG *) 0xFFFD0034) // (SSC0) Transmit Sync Holding Register -#define AT91C_SSC0_THR ((AT91_REG *) 0xFFFD0024) // (SSC0) Transmit Holding Register -#define AT91C_SSC0_TFMR ((AT91_REG *) 0xFFFD001C) // (SSC0) Transmit Frame Mode Register -#define AT91C_SSC0_RFMR ((AT91_REG *) 0xFFFD0014) // (SSC0) Receive Frame Mode Register -#define AT91C_SSC0_CMR ((AT91_REG *) 0xFFFD0004) // (SSC0) Clock Mode Register -#define AT91C_SSC0_IDR ((AT91_REG *) 0xFFFD0048) // (SSC0) Interrupt Disable Register -#define AT91C_SSC0_SR ((AT91_REG *) 0xFFFD0040) // (SSC0) Status Register -#define AT91C_SSC0_RSHR ((AT91_REG *) 0xFFFD0030) // (SSC0) Receive Sync Holding Register -#define AT91C_SSC0_RHR ((AT91_REG *) 0xFFFD0020) // (SSC0) Receive Holding Register -#define AT91C_SSC0_TCMR ((AT91_REG *) 0xFFFD0018) // (SSC0) Transmit Clock Mode Register -#define AT91C_SSC0_RCMR ((AT91_REG *) 0xFFFD0010) // (SSC0) Receive Clock ModeRegister -#define AT91C_SSC0_CR ((AT91_REG *) 0xFFFD0000) // (SSC0) Control Register -// ========== Register definition for PDC_SSC1 peripheral ========== -#define AT91C_SSC1_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register -#define AT91C_SSC1_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register -#define AT91C_SSC1_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register -#define AT91C_SSC1_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register -#define AT91C_SSC1_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC1) Receive Pointer Register -#define AT91C_SSC1_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register -#define AT91C_SSC1_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register -#define AT91C_SSC1_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register -#define AT91C_SSC1_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC1) Transmit Counter Register -#define AT91C_SSC1_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC1) Receive Counter Register -// ========== Register definition for SSC1 peripheral ========== -#define AT91C_SSC1_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC1) Receive Frame Mode Register -#define AT91C_SSC1_CMR ((AT91_REG *) 0xFFFD4004) // (SSC1) Clock Mode Register -#define AT91C_SSC1_IDR ((AT91_REG *) 0xFFFD4048) // (SSC1) Interrupt Disable Register -#define AT91C_SSC1_SR ((AT91_REG *) 0xFFFD4040) // (SSC1) Status Register -#define AT91C_SSC1_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC1) Receive Sync Holding Register -#define AT91C_SSC1_RHR ((AT91_REG *) 0xFFFD4020) // (SSC1) Receive Holding Register -#define AT91C_SSC1_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC1) Transmit Clock Mode Register -#define AT91C_SSC1_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC1) Receive Clock ModeRegister -#define AT91C_SSC1_CR ((AT91_REG *) 0xFFFD4000) // (SSC1) Control Register -#define AT91C_SSC1_IMR ((AT91_REG *) 0xFFFD404C) // (SSC1) Interrupt Mask Register -#define AT91C_SSC1_IER ((AT91_REG *) 0xFFFD4044) // (SSC1) Interrupt Enable Register -#define AT91C_SSC1_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC1) Transmit Sync Holding Register -#define AT91C_SSC1_THR ((AT91_REG *) 0xFFFD4024) // (SSC1) Transmit Holding Register -#define AT91C_SSC1_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC1) Transmit Frame Mode Register -// ========== Register definition for PDC_ADC0 peripheral ========== -#define AT91C_ADC0_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC0) PDC Transfer Control Register -#define AT91C_ADC0_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC0) Transmit Next Pointer Register -#define AT91C_ADC0_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC0) Receive Next Pointer Register -#define AT91C_ADC0_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC0) Transmit Pointer Register -#define AT91C_ADC0_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC0) Receive Pointer Register -#define AT91C_ADC0_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC0) PDC Transfer Status Register -#define AT91C_ADC0_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC0) Transmit Next Counter Register -#define AT91C_ADC0_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC0) Receive Next Counter Register -#define AT91C_ADC0_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC0) Transmit Counter Register -#define AT91C_ADC0_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC0) Receive Counter Register -// ========== Register definition for ADC0 peripheral ========== -#define AT91C_ADC0_IMR ((AT91_REG *) 0xFFFD802C) // (ADC0) ADC Interrupt Mask Register -#define AT91C_ADC0_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC0) ADC Channel Data Register 4 -#define AT91C_ADC0_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC0) ADC Channel Data Register 2 -#define AT91C_ADC0_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC0) ADC Channel Data Register 0 -#define AT91C_ADC0_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC0) ADC Channel Data Register 7 -#define AT91C_ADC0_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC0) ADC Channel Data Register 1 -#define AT91C_ADC0_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC0) ADC Channel Data Register 3 -#define AT91C_ADC0_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC0) ADC Channel Data Register 5 -#define AT91C_ADC0_MR ((AT91_REG *) 0xFFFD8004) // (ADC0) ADC Mode Register -#define AT91C_ADC0_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC0) ADC Channel Data Register 6 -#define AT91C_ADC0_CR ((AT91_REG *) 0xFFFD8000) // (ADC0) ADC Control Register -#define AT91C_ADC0_CHER ((AT91_REG *) 0xFFFD8010) // (ADC0) ADC Channel Enable Register -#define AT91C_ADC0_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC0) ADC Channel Status Register -#define AT91C_ADC0_IER ((AT91_REG *) 0xFFFD8024) // (ADC0) ADC Interrupt Enable Register -#define AT91C_ADC0_SR ((AT91_REG *) 0xFFFD801C) // (ADC0) ADC Status Register -#define AT91C_ADC0_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC0) ADC Channel Disable Register -#define AT91C_ADC0_IDR ((AT91_REG *) 0xFFFD8028) // (ADC0) ADC Interrupt Disable Register -#define AT91C_ADC0_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC0) ADC Last Converted Data Register -// ========== Register definition for PDC_ADC1 peripheral ========== -#define AT91C_ADC1_RPR ((AT91_REG *) 0xFFFDC100) // (PDC_ADC1) Receive Pointer Register -#define AT91C_ADC1_RCR ((AT91_REG *) 0xFFFDC104) // (PDC_ADC1) Receive Counter Register -#define AT91C_ADC1_PTSR ((AT91_REG *) 0xFFFDC124) // (PDC_ADC1) PDC Transfer Status Register -#define AT91C_ADC1_TNCR ((AT91_REG *) 0xFFFDC11C) // (PDC_ADC1) Transmit Next Counter Register -#define AT91C_ADC1_RNCR ((AT91_REG *) 0xFFFDC114) // (PDC_ADC1) Receive Next Counter Register -#define AT91C_ADC1_TCR ((AT91_REG *) 0xFFFDC10C) // (PDC_ADC1) Transmit Counter Register -#define AT91C_ADC1_PTCR ((AT91_REG *) 0xFFFDC120) // (PDC_ADC1) PDC Transfer Control Register -#define AT91C_ADC1_TNPR ((AT91_REG *) 0xFFFDC118) // (PDC_ADC1) Transmit Next Pointer Register -#define AT91C_ADC1_RNPR ((AT91_REG *) 0xFFFDC110) // (PDC_ADC1) Receive Next Pointer Register -#define AT91C_ADC1_TPR ((AT91_REG *) 0xFFFDC108) // (PDC_ADC1) Transmit Pointer Register -// ========== Register definition for ADC1 peripheral ========== -#define AT91C_ADC1_CDR1 ((AT91_REG *) 0xFFFDC034) // (ADC1) ADC Channel Data Register 1 -#define AT91C_ADC1_IMR ((AT91_REG *) 0xFFFDC02C) // (ADC1) ADC Interrupt Mask Register -#define AT91C_ADC1_IER ((AT91_REG *) 0xFFFDC024) // (ADC1) ADC Interrupt Enable Register -#define AT91C_ADC1_SR ((AT91_REG *) 0xFFFDC01C) // (ADC1) ADC Status Register -#define AT91C_ADC1_CDR2 ((AT91_REG *) 0xFFFDC038) // (ADC1) ADC Channel Data Register 2 -#define AT91C_ADC1_CDR0 ((AT91_REG *) 0xFFFDC030) // (ADC1) ADC Channel Data Register 0 -#define AT91C_ADC1_CDR3 ((AT91_REG *) 0xFFFDC03C) // (ADC1) ADC Channel Data Register 3 -#define AT91C_ADC1_CDR6 ((AT91_REG *) 0xFFFDC048) // (ADC1) ADC Channel Data Register 6 -#define AT91C_ADC1_CDR4 ((AT91_REG *) 0xFFFDC040) // (ADC1) ADC Channel Data Register 4 -#define AT91C_ADC1_CR ((AT91_REG *) 0xFFFDC000) // (ADC1) ADC Control Register -#define AT91C_ADC1_CDR7 ((AT91_REG *) 0xFFFDC04C) // (ADC1) ADC Channel Data Register 7 -#define AT91C_ADC1_CDR5 ((AT91_REG *) 0xFFFDC044) // (ADC1) ADC Channel Data Register 5 -#define AT91C_ADC1_CHDR ((AT91_REG *) 0xFFFDC014) // (ADC1) ADC Channel Disable Register -#define AT91C_ADC1_MR ((AT91_REG *) 0xFFFDC004) // (ADC1) ADC Mode Register -#define AT91C_ADC1_IDR ((AT91_REG *) 0xFFFDC028) // (ADC1) ADC Interrupt Disable Register -#define AT91C_ADC1_LCDR ((AT91_REG *) 0xFFFDC020) // (ADC1) ADC Last Converted Data Register -#define AT91C_ADC1_CHSR ((AT91_REG *) 0xFFFDC018) // (ADC1) ADC Channel Status Register -#define AT91C_ADC1_CHER ((AT91_REG *) 0xFFFDC010) // (ADC1) ADC Channel Enable Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7A3 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_TWD ((unsigned int) AT91C_PIO_PA0) // TWI Two-wire Serial Data -#define AT91C_PA0_ADTRG0 ((unsigned int) AT91C_PIO_PA0) // ADC0 External Trigger -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TWCK ((unsigned int) AT91C_PIO_PA1) // TWI Two-wire Serial Clock -#define AT91C_PA1_ADTRG1 ((unsigned int) AT91C_PIO_PA1) // ADC1 External Trigger -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TXD2 ((unsigned int) AT91C_PIO_PA10) // USART 2 Transmit Data -#define AT91C_PA10_SPI1_SPCK ((unsigned int) AT91C_PIO_PA10) // SPI1 Serial Clock -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_SPI0_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI0 Peripheral Chip Select 0 -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA12) // SPI0 Peripheral Chip Select 1 -#define AT91C_PA12_MCDA1 ((unsigned int) AT91C_PIO_PA12) // Multimedia Card A Data 1 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA13) // SPI0 Peripheral Chip Select 2 -#define AT91C_PA13_MCDA2 ((unsigned int) AT91C_PIO_PA13) // Multimedia Card A Data 2 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA14) // SPI0 Peripheral Chip Select 3 -#define AT91C_PA14_MCDA3 ((unsigned int) AT91C_PIO_PA14) // Multimedia Card A Data 3 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_SPI0_MISO ((unsigned int) AT91C_PIO_PA15) // SPI0 Master In Slave -#define AT91C_PA15_MCDA0 ((unsigned int) AT91C_PIO_PA15) // Multimedia Card A Data 0 -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_SPI0_MOSI ((unsigned int) AT91C_PIO_PA16) // SPI0 Master Out Slave -#define AT91C_PA16_MCCDA ((unsigned int) AT91C_PIO_PA16) // Multimedia Card A Command -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_SPI0_SPCK ((unsigned int) AT91C_PIO_PA17) // SPI0 Serial Clock -#define AT91C_PA17_MCCK ((unsigned int) AT91C_PIO_PA17) // Multimedia Card Clock -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_PWM0 ((unsigned int) AT91C_PIO_PA18) // PWMC Channel 0 -#define AT91C_PA18_PCK0 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_PWM1 ((unsigned int) AT91C_PIO_PA19) // PWMC Channel 1 -#define AT91C_PA19_PCK1 ((unsigned int) AT91C_PIO_PA19) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_RXD0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Receive Data -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_PWM2 ((unsigned int) AT91C_PIO_PA20) // PWMC Channel 2 -#define AT91C_PA20_PCK2 ((unsigned int) AT91C_PIO_PA20) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_PWM3 ((unsigned int) AT91C_PIO_PA21) // PWMC Channel 3 -#define AT91C_PA21_PCK3 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_PWM4 ((unsigned int) AT91C_PIO_PA22) // PWMC Channel 4 -#define AT91C_PA22_IRQ0 ((unsigned int) AT91C_PIO_PA22) // Interrupt input 0 -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_PWM5 ((unsigned int) AT91C_PIO_PA23) // PWMC Channel 5 -#define AT91C_PA23_IRQ1 ((unsigned int) AT91C_PIO_PA23) // Interrupt input 1 -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_PWM6 ((unsigned int) AT91C_PIO_PA24) // PWMC Channel 6 -#define AT91C_PA24_TCLK4 ((unsigned int) AT91C_PIO_PA24) // Timer Counter 4 external Clock Input -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_PWM7 ((unsigned int) AT91C_PIO_PA25) // PWMC Channel 7 -#define AT91C_PA25_TCLK5 ((unsigned int) AT91C_PIO_PA25) // Timer Counter 5 external Clock Input -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_CANRX0 ((unsigned int) AT91C_PIO_PA26) // CAN Receive 0 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_CANTX0 ((unsigned int) AT91C_PIO_PA27) // CAN Transmit 0 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_CANRX1 ((unsigned int) AT91C_PIO_PA28) // CAN Receive 1 -#define AT91C_PA28_TCLK3 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 3 external Clock Input -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_CANTX1 ((unsigned int) AT91C_PIO_PA29) // CAN Transmit 1 -#define AT91C_PA29_TCLK6 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 6 external clock input -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TXD0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Transmit Data -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) // DBGU Debug Receive Data -#define AT91C_PA30_TCLK7 ((unsigned int) AT91C_PIO_PA30) // Timer Counter 7 external clock input -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) // DBGU Debug Transmit Data -#define AT91C_PA31_TCLK8 ((unsigned int) AT91C_PIO_PA31) // Timer Counter 8 external clock input -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_SCK0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Serial Clock -#define AT91C_PA4_SPI1_NPCS0 ((unsigned int) AT91C_PIO_PA4) // SPI1 Peripheral Chip Select 0 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RTS0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Ready To Send -#define AT91C_PA5_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA5) // SPI1 Peripheral Chip Select 1 -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_CTS0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Clear To Send -#define AT91C_PA6_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA6) // SPI1 Peripheral Chip Select 2 -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RXD1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Receive Data -#define AT91C_PA7_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA7) // SPI1 Peripheral Chip Select 3 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_TXD1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Transmit Data -#define AT91C_PA8_SPI1_MISO ((unsigned int) AT91C_PIO_PA8) // SPI1 Master In Slave -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_RXD2 ((unsigned int) AT91C_PIO_PA9) // USART 2 Receive Data -#define AT91C_PA9_SPI1_MOSI ((unsigned int) AT91C_PIO_PA9) // SPI1 Master Out Slave -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_IRQ2 ((unsigned int) AT91C_PIO_PB0) // Interrupt input 2 -#define AT91C_PB0_PWM5 ((unsigned int) AT91C_PIO_PB0) // PWMC Channel 5 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_IRQ3 ((unsigned int) AT91C_PIO_PB1) // Interrupt input 3 -#define AT91C_PB1_PWM6 ((unsigned int) AT91C_PIO_PB1) // PWMC Channel 6 -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_TCLK1 ((unsigned int) AT91C_PIO_PB10) // Timer Counter 1 external clock input -#define AT91C_PB10_RK1 ((unsigned int) AT91C_PIO_PB10) // SSC Receive Clock 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_TCLK2 ((unsigned int) AT91C_PIO_PB11) // Timer Counter 2 external clock input -#define AT91C_PB11_RF1 ((unsigned int) AT91C_PIO_PB11) // SSC Receive Frame Sync 1 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_TIOA0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB12_TD1 ((unsigned int) AT91C_PIO_PB12) // SSC Transmit Data 1 -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_TIOB0 ((unsigned int) AT91C_PIO_PB13) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB13_RD1 ((unsigned int) AT91C_PIO_PB13) // SSC Receive Data 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_TIOA1 ((unsigned int) AT91C_PIO_PB14) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB14_PWM0 ((unsigned int) AT91C_PIO_PB14) // PWMC Channel 0 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_TIOB1 ((unsigned int) AT91C_PIO_PB15) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB15_PWM1 ((unsigned int) AT91C_PIO_PB15) // PWMC Channel 1 -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_TIOA2 ((unsigned int) AT91C_PIO_PB16) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB16_PWM2 ((unsigned int) AT91C_PIO_PB16) // PWMC Channel 2 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_TIOB2 ((unsigned int) AT91C_PIO_PB17) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB17_PWM3 ((unsigned int) AT91C_PIO_PB17) // PWMC Channel 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_TIOA3 ((unsigned int) AT91C_PIO_PB18) // Timer Counter 3 Multipurpose Timer I/O Pin A -#define AT91C_PB18_PWM4 ((unsigned int) AT91C_PIO_PB18) // PWMC Channel 4 -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_TIOB3 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 3 Multipurpose Timer I/O Pin B -#define AT91C_PB19_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PB19) // SPI1 Peripheral Chip Select 1 -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_TF0 ((unsigned int) AT91C_PIO_PB2) // SSC Transmit Frame Sync 0 -#define AT91C_PB2_PWM7 ((unsigned int) AT91C_PIO_PB2) // PWMC Channel 7 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_TIOA4 ((unsigned int) AT91C_PIO_PB20) // Timer Counter 4 Multipurpose Timer I/O Pin A -#define AT91C_PB20_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PB20) // SPI1 Peripheral Chip Select 2 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_TIOB4 ((unsigned int) AT91C_PIO_PB21) // Timer Counter 4 Multipurpose Timer I/O Pin B -#define AT91C_PB21_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PB21) // SPI1 Peripheral Chip Select 3 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_TIOA5 ((unsigned int) AT91C_PIO_PB22) // Timer Counter 5 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOB5 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 5 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOA6 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 6 Multipurpose Timer I/O Pin A -#define AT91C_PB24_RTS1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Ready To Send -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOB6 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 6 Multipurpose Timer I/O Pin B -#define AT91C_PB25_CTS1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Clear To Send -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOA7 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 7 Multipurpose Timer I/O Pin A -#define AT91C_PB26_SCK1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Serial Clock -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOB7 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 7 Multipurpose Timer I/O Pin B -#define AT91C_PB27_RTS2 ((unsigned int) AT91C_PIO_PB27) // USART 2 Ready To Send -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOA8 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 8 Multipurpose Timer I/O Pin A -#define AT91C_PB28_CTS2 ((unsigned int) AT91C_PIO_PB28) // USART 2 Clear To Send -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_TIOB8 ((unsigned int) AT91C_PIO_PB29) // Timer Counter 8 Multipurpose Timer I/O Pin B -#define AT91C_PB29_SCK2 ((unsigned int) AT91C_PIO_PB29) // USART 2 Serial Clock -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_TK0 ((unsigned int) AT91C_PIO_PB3) // SSC Transmit Clock 0 -#define AT91C_PB3_PCK0 ((unsigned int) AT91C_PIO_PB3) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_TD0 ((unsigned int) AT91C_PIO_PB4) // SSC Transmit data -#define AT91C_PB4_PCK1 ((unsigned int) AT91C_PIO_PB4) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_RD0 ((unsigned int) AT91C_PIO_PB5) // SSC Receive Data -#define AT91C_PB5_PCK2 ((unsigned int) AT91C_PIO_PB5) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_RK0 ((unsigned int) AT91C_PIO_PB6) // SSC Receive Clock -#define AT91C_PB6_PCK3 ((unsigned int) AT91C_PIO_PB6) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_RF0 ((unsigned int) AT91C_PIO_PB7) // SSC Receive Frame Sync 0 -#define AT91C_PB7_CANTX1 ((unsigned int) AT91C_PIO_PB7) // CAN Transmit 1 -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_FIQ ((unsigned int) AT91C_PIO_PB8) // AIC Fast Interrupt Input -#define AT91C_PB8_TF1 ((unsigned int) AT91C_PIO_PB8) // SSC Transmit Frame Sync 1 -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_TCLK0 ((unsigned int) AT91C_PIO_PB9) // Timer Counter 0 external clock input -#define AT91C_PB9_TK1 ((unsigned int) AT91C_PIO_PB9) // SSC Transmit Clock 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7A3 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_CAN0 ((unsigned int) 4) // Control Area Network Controller 0 -#define AT91C_ID_CAN1 ((unsigned int) 5) // Control Area Network Controller 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_US2 ((unsigned int) 8) // USART 2 -#define AT91C_ID_MCI ((unsigned int) 9) // Multimedia Card Interface -#define AT91C_ID_TWI ((unsigned int) 10) // Two-Wire Interface -#define AT91C_ID_SPI0 ((unsigned int) 11) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 12) // Serial Peripheral Interface 1 -#define AT91C_ID_SSC0 ((unsigned int) 13) // Serial Synchronous Controller 0 -#define AT91C_ID_SSC1 ((unsigned int) 14) // Serial Synchronous Controller 1 -#define AT91C_ID_TC0 ((unsigned int) 15) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 16) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 17) // Timer Counter 2 -#define AT91C_ID_TC3 ((unsigned int) 18) // Timer Counter 3 -#define AT91C_ID_TC4 ((unsigned int) 19) // Timer Counter 4 -#define AT91C_ID_TC5 ((unsigned int) 20) // Timer Counter 5 -#define AT91C_ID_TC6 ((unsigned int) 21) // Timer Counter 6 -#define AT91C_ID_TC7 ((unsigned int) 22) // Timer Counter 7 -#define AT91C_ID_TC8 ((unsigned int) 23) // Timer Counter 8 -#define AT91C_ID_ADC0 ((unsigned int) 24) // Analog To Digital Converter 0 -#define AT91C_ID_ADC1 ((unsigned int) 25) // Analog To Digital Converter 1 -#define AT91C_ID_PWMC ((unsigned int) 26) // Pulse Width Modulation Controller -#define AT91C_ID_UDP ((unsigned int) 27) // USB Device Port -#define AT91C_ID_IRQ0 ((unsigned int) 28) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 29) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ID_IRQ2 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ2) -#define AT91C_ID_IRQ3 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ3) -#define AT91C_ALL_INT ((unsigned int) 0xFFFFFFFF) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7A3 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_SHDWC ((AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_CAN0_MB0 ((AT91PS_CAN_MB) 0xFFF80200) // (CAN0_MB0) Base Address -#define AT91C_BASE_CAN0_MB1 ((AT91PS_CAN_MB) 0xFFF80220) // (CAN0_MB1) Base Address -#define AT91C_BASE_CAN0_MB2 ((AT91PS_CAN_MB) 0xFFF80240) // (CAN0_MB2) Base Address -#define AT91C_BASE_CAN0_MB3 ((AT91PS_CAN_MB) 0xFFF80260) // (CAN0_MB3) Base Address -#define AT91C_BASE_CAN0_MB4 ((AT91PS_CAN_MB) 0xFFF80280) // (CAN0_MB4) Base Address -#define AT91C_BASE_CAN0_MB5 ((AT91PS_CAN_MB) 0xFFF802A0) // (CAN0_MB5) Base Address -#define AT91C_BASE_CAN0_MB6 ((AT91PS_CAN_MB) 0xFFF802C0) // (CAN0_MB6) Base Address -#define AT91C_BASE_CAN0_MB7 ((AT91PS_CAN_MB) 0xFFF802E0) // (CAN0_MB7) Base Address -#define AT91C_BASE_CAN0_MB8 ((AT91PS_CAN_MB) 0xFFF80300) // (CAN0_MB8) Base Address -#define AT91C_BASE_CAN0_MB9 ((AT91PS_CAN_MB) 0xFFF80320) // (CAN0_MB9) Base Address -#define AT91C_BASE_CAN0_MB10 ((AT91PS_CAN_MB) 0xFFF80340) // (CAN0_MB10) Base Address -#define AT91C_BASE_CAN0_MB11 ((AT91PS_CAN_MB) 0xFFF80360) // (CAN0_MB11) Base Address -#define AT91C_BASE_CAN0_MB12 ((AT91PS_CAN_MB) 0xFFF80380) // (CAN0_MB12) Base Address -#define AT91C_BASE_CAN0_MB13 ((AT91PS_CAN_MB) 0xFFF803A0) // (CAN0_MB13) Base Address -#define AT91C_BASE_CAN0_MB14 ((AT91PS_CAN_MB) 0xFFF803C0) // (CAN0_MB14) Base Address -#define AT91C_BASE_CAN0_MB15 ((AT91PS_CAN_MB) 0xFFF803E0) // (CAN0_MB15) Base Address -#define AT91C_BASE_CAN0 ((AT91PS_CAN) 0xFFF80000) // (CAN0) Base Address -#define AT91C_BASE_CAN1_MB0 ((AT91PS_CAN_MB) 0xFFF84200) // (CAN1_MB0) Base Address -#define AT91C_BASE_CAN1_MB1 ((AT91PS_CAN_MB) 0xFFF84220) // (CAN1_MB1) Base Address -#define AT91C_BASE_CAN1_MB2 ((AT91PS_CAN_MB) 0xFFF84240) // (CAN1_MB2) Base Address -#define AT91C_BASE_CAN1_MB3 ((AT91PS_CAN_MB) 0xFFF84260) // (CAN1_MB3) Base Address -#define AT91C_BASE_CAN1_MB4 ((AT91PS_CAN_MB) 0xFFF84280) // (CAN1_MB4) Base Address -#define AT91C_BASE_CAN1_MB5 ((AT91PS_CAN_MB) 0xFFF842A0) // (CAN1_MB5) Base Address -#define AT91C_BASE_CAN1_MB6 ((AT91PS_CAN_MB) 0xFFF842C0) // (CAN1_MB6) Base Address -#define AT91C_BASE_CAN1_MB7 ((AT91PS_CAN_MB) 0xFFF842E0) // (CAN1_MB7) Base Address -#define AT91C_BASE_CAN1_MB8 ((AT91PS_CAN_MB) 0xFFF84300) // (CAN1_MB8) Base Address -#define AT91C_BASE_CAN1_MB9 ((AT91PS_CAN_MB) 0xFFF84320) // (CAN1_MB9) Base Address -#define AT91C_BASE_CAN1_MB10 ((AT91PS_CAN_MB) 0xFFF84340) // (CAN1_MB10) Base Address -#define AT91C_BASE_CAN1_MB11 ((AT91PS_CAN_MB) 0xFFF84360) // (CAN1_MB11) Base Address -#define AT91C_BASE_CAN1_MB12 ((AT91PS_CAN_MB) 0xFFF84380) // (CAN1_MB12) Base Address -#define AT91C_BASE_CAN1_MB13 ((AT91PS_CAN_MB) 0xFFF843A0) // (CAN1_MB13) Base Address -#define AT91C_BASE_CAN1_MB14 ((AT91PS_CAN_MB) 0xFFF843C0) // (CAN1_MB14) Base Address -#define AT91C_BASE_CAN1_MB15 ((AT91PS_CAN_MB) 0xFFF843E0) // (CAN1_MB15) Base Address -#define AT91C_BASE_CAN1 ((AT91PS_CAN) 0xFFF84000) // (CAN1) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address -#define AT91C_BASE_TC3 ((AT91PS_TC) 0xFFFA4000) // (TC3) Base Address -#define AT91C_BASE_TC4 ((AT91PS_TC) 0xFFFA4040) // (TC4) Base Address -#define AT91C_BASE_TC5 ((AT91PS_TC) 0xFFFA4080) // (TC5) Base Address -#define AT91C_BASE_TCB1 ((AT91PS_TCB) 0xFFFA4000) // (TCB1) Base Address -#define AT91C_BASE_TC6 ((AT91PS_TC) 0xFFFA8000) // (TC6) Base Address -#define AT91C_BASE_TC7 ((AT91PS_TC) 0xFFFA8040) // (TC7) Base Address -#define AT91C_BASE_TC8 ((AT91PS_TC) 0xFFFA8080) // (TC8) Base Address -#define AT91C_BASE_TCB2 ((AT91PS_TCB) 0xFFFA8000) // (TCB2) Base Address -#define AT91C_BASE_PDC_MCI ((AT91PS_PDC) 0xFFFAC100) // (PDC_MCI) Base Address -#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFAC000) // (MCI) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US2 ((AT91PS_PDC) 0xFFFC8100) // (PDC_US2) Base Address -#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) // (US2) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH4 ((AT91PS_PWMC_CH) 0xFFFCC280) // (PWMC_CH4) Base Address -#define AT91C_BASE_PWMC_CH5 ((AT91PS_PWMC_CH) 0xFFFCC2A0) // (PWMC_CH5) Base Address -#define AT91C_BASE_PWMC_CH6 ((AT91PS_PWMC_CH) 0xFFFCC2C0) // (PWMC_CH6) Base Address -#define AT91C_BASE_PWMC_CH7 ((AT91PS_PWMC_CH) 0xFFFCC2E0) // (PWMC_CH7) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_PDC_SSC0 ((AT91PS_PDC) 0xFFFD0100) // (PDC_SSC0) Base Address -#define AT91C_BASE_SSC0 ((AT91PS_SSC) 0xFFFD0000) // (SSC0) Base Address -#define AT91C_BASE_PDC_SSC1 ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC1) Base Address -#define AT91C_BASE_SSC1 ((AT91PS_SSC) 0xFFFD4000) // (SSC1) Base Address -#define AT91C_BASE_PDC_ADC0 ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC0) Base Address -#define AT91C_BASE_ADC0 ((AT91PS_ADC) 0xFFFD8000) // (ADC0) Base Address -#define AT91C_BASE_PDC_ADC1 ((AT91PS_PDC) 0xFFFDC100) // (PDC_ADC1) Base Address -#define AT91C_BASE_ADC1 ((AT91PS_ADC) 0xFFFDC000) // (ADC1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7A3 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbytes) -// IFLASH -#define AT91C_IFLASH ((char *) 0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal FLASH size in byte (256 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE ((unsigned int) 256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE ((unsigned int) 16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES ((unsigned int) 1024) // Internal FLASH Number of Pages: 1024 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS ((unsigned int) 16) // Internal FLASH Number of Lock Bits: 16 bytes - -#endif diff -Nru cpputest-3.7.2/platforms_startup/armcc/AT91SAM7A3/lib_AT91SAM7A3.h cpputest-3.7.2+dfsg/platforms_startup/armcc/AT91SAM7A3/lib_AT91SAM7A3.h --- cpputest-3.7.2/platforms_startup/armcc/AT91SAM7A3/lib_AT91SAM7A3.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/AT91SAM7A3/lib_AT91SAM7A3.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,5054 +0,0 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7A3.h -//* Object : AT91SAM7A3 inlined functions -//* Generated : AT91 SW Application Group 09/13/2005 (09:48:02) -//* -//* CVS Reference : /lib_MC_SAM.h/1.3/Wed Apr 28 09:02:35 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 12:29:40 2002// -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_shdwc_6122A.h/1.1/Wed Oct 6 13:06:00 2004// -//* CVS Reference : /lib_spi2.h/1.2/Tue Aug 23 15:43:14 2005// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Wed Dec 3 10:23:10 2003// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Thu Nov 4 14:01:11 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// -//* CVS Reference : /lib_pmc_SAM.h/1.9/Tue Aug 30 13:03:40 2005// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 09:39:19 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 09:39:38 2004// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 13:37:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:53 2002// -//* CVS Reference : /lib_mci.h/1.7/Thu May 27 08:47:43 2004// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 09:38:30 2004// -//* CVS Reference : /lib_udp.h/1.5/Mon Aug 29 08:17:54 2005// -//* CVS Reference : /lib_aic_6075b.h/1.2/Mon Jul 18 11:06:01 2005// -//* CVS Reference : /lib_can_AT91.h/1.5/Tue Aug 23 15:42:51 2005// -//* ---------------------------------------------------------------------------- - -#ifndef lib_AT91SAM7A3_H -#define lib_AT91SAM7A3_H - -#include "AT91SAM7A3.h" -/* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) () ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask ; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; - else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number -{ - pAic->AIC_ISCR = (0x1 << irq_id) ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_ISR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_IPR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); - - pAic->AIC_SPU = (unsigned int) SpuriousHandler; - pAic->AIC_DCR = protectMode; -} -/* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = (unsigned int) address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = (unsigned int) address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = (unsigned int) address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} -/* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled -{ - pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled -{ - pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller -{ - return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable - -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable or disable pullup on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_PullupEnable -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_PullupEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect Pullup - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_PullupDisable -//* \brief Disable pullup on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_PullupDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupDisable) // \arg enable pullup on PIO -{ - // Not connect Pullup - pPio->PIO_PPUDR = pullupDisable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive - -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter - -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInput(pPio) & flag); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled -{ - pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled -{ - pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled -{ - pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled -{ - pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled -{ - pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled -{ - pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection -{ - pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection -{ - pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled -{ - pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled -{ - pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkEnableReg -//* \brief Configure the System Clock Enable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkEnableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCER register - pPMC->PMC_SCER = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkDisableReg -//* \brief Configure the System Clock Disable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkDisableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCDR register - pPMC->PMC_SCDR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetSysClkStatusReg -//* \brief Return the System Clock Status Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( - AT91PS_PMC pPMC // pointer to a CAN controller - ) -{ - return pPMC->PMC_SCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Disable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetPeriphClock -//* \brief Get peripheral clock status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetPeriphClock ( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_PCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscillatorReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) -{ - pCKGR->CKGR_MOR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MOR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_EnableMainOscillator -//* \brief Enable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_EnableMainOscillator( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_DisableMainOscillator -//* \brief Disable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_DisableMainOscillator ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscStartUpTime -//* \brief Cfg MOR Register according to the main osc startup time -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscStartUpTime ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int startup_time, // \arg main osc startup time in microsecond (us) - unsigned int slowClock) // \arg slowClock in Hz -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; - pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClockFreqReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MCFR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgMCKReg -//* \brief Cfg Master Clock Register -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgMCKReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - pPMC->PMC_MCKR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMCKReg -//* \brief Return Master Clock Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetMCKReg( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_MCKR; -} - -//*------------------------------------------------------------------------------ -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz which correponds to processor clock for ARM7 -//*------------------------------------------------------------------------------ -__inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); - unsigned int pllDivider, pllMultiplier; - - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLR; - pllDivider = (reg & AT91C_CKGR_DIV); - pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 - unsigned int mode) -{ - pPMC->PMC_PCKR[pck] = mode; - pPMC->PMC_SCER = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 -{ - pPMC->PMC_SCDR = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnableIt -//* \brief Enable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pPMC->PMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisableIt -//* \brief Disable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pPMC->PMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetStatus -//* \brief Return PMC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetInterruptMaskStatus -//* \brief Return PMC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsInterruptMasked -//* \brief Test if PMC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsInterruptMasked( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsStatusSet -//* \brief Test if PMC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsStatusSet( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetStatus(pPMC) & flag); -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_CKGR_CfgPLLReg -// \brief Cfg the PLL Register -// ---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgPLLReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) -{ - pCKGR->CKGR_PLLR = mode; -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_CKGR_GetPLLReg -// \brief Get the PLL Register -// ---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetPLLReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_PLLR; -} - - -/* ***************************************************************************** - SOFTWARE API FOR RSTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSoftReset -//* \brief Start Software Reset -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSoftReset( - AT91PS_RSTC pRSTC, - unsigned int reset) -{ - pRSTC->RSTC_RCR = (0xA5000000 | reset); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSetMode -//* \brief Set Reset Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSetMode( - AT91PS_RSTC pRSTC, - unsigned int mode) -{ - pRSTC->RSTC_RMR = (0xA5000000 | mode); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetMode -//* \brief Get Reset Mode -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetMode( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetStatus -//* \brief Get Reset Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetStatus( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RSR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTIsSoftRstActive -//* \brief Return !=0 if software reset is still not completed -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTIsSoftRstActive( - AT91PS_RSTC pRSTC) -{ - return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); -} -/* ***************************************************************************** - SOFTWARE API FOR SHDWC - ***************************************************************************** */ -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91F_SHDWNSetMode() -//* Object : Set the Shutdown mode register -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_SHDWNSetMode( - AT91PS_SHDWC pSHDWC, - unsigned int mode) -{ - pSHDWC->SHDWC_SHMR = mode; - return(pSHDWC->SHDWC_SHMR); -} - -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91F_SHDWNGetMode() -//* Object : Get the Shutdown mode register -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_SHDWNGetMode( - AT91PS_SHDWC pSHDWC) -{ - return(pSHDWC->SHDWC_SHMR); -} - -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91F_SHDWNEnable() -//* Object : Enable Shutdown -//*-------------------------------------------------------------------------------------- -__inline void AT91F_SHDWNEnable( - AT91PS_SHDWC pSHDWC) -{ - pSHDWC->SHDWC_SHCR = 0xA5000001; -} - -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91F_SHDWNGetStatus() -//* Object : Get Shutdown Status -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_SHDWNGetStatus( - AT91PS_SHDWC pSHDWC) -{ - return(pSHDWC->SHDWC_SHSR); -} - -/* ***************************************************************************** - SOFTWARE API FOR RTTC - ***************************************************************************** */ -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_SetRTT_TimeBase() -//* \brief Set the RTT prescaler according to the TimeBase in ms -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetTimeBase( - AT91PS_RTTC pRTTC, - unsigned int ms) -{ - if (ms > 2000) - return 1; // AT91C_TIME_OUT_OF_RANGE - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); - return 0; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTSetPrescaler() -//* \brief Set the new prescaler value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetPrescaler( - AT91PS_RTTC pRTTC, - unsigned int rtpres) -{ - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); - return (pRTTC->RTTC_RTMR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTRestart() -//* \brief Restart the RTT prescaler -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTRestart( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; -} - - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmINT() -//* \brief Enable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearAlarmINT() -//* \brief Disable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetRttIncINT() -//* \brief Enable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearRttIncINT() -//* \brief Disable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmValue() -//* \brief Set RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmValue( - AT91PS_RTTC pRTTC, unsigned int alarm) -{ - pRTTC->RTTC_RTAR = alarm; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_GetAlarmValue() -//* \brief Get RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetAlarmValue( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTAR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTGetStatus() -//* \brief Read the RTT status -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetStatus( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTSR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ReadValue() -//* \brief Read the RTT value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTReadValue( - AT91PS_RTTC pRTTC) -{ - register volatile unsigned int val1,val2; - do - { - val1 = pRTTC->RTTC_RTVR; - val2 = pRTTC->RTTC_RTVR; - } - while(val1 != val2); - return(val1); -} -/* ***************************************************************************** - SOFTWARE API FOR PITC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITInit -//* \brief System timer init : period in �second, system clock freq in MHz -//*---------------------------------------------------------------------------- -__inline void AT91F_PITInit( - AT91PS_PITC pPITC, - unsigned int period, - unsigned int pit_frequency) -{ - pPITC->PITC_PIMR = period ? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 - pPITC->PITC_PIMR |= AT91C_PITC_PITEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITSetPIV -//* \brief Set the PIT Periodic Interval Value -//*---------------------------------------------------------------------------- -__inline void AT91F_PITSetPIV( - AT91PS_PITC pPITC, - unsigned int piv) -{ - pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITEnableInt -//* \brief Enable PIT periodic interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PITEnableInt( - AT91PS_PITC pPITC) -{ - pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITDisableInt -//* \brief Disable PIT periodic interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PITDisableInt( - AT91PS_PITC pPITC) -{ - pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetMode -//* \brief Read PIT mode register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetMode( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetStatus -//* \brief Read PIT status register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetStatus( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PISR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIIR -//* \brief Read PIT CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetPIIR( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIIR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIVR -//* \brief Read System timer CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetPIVR( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIVR); -} -/* ***************************************************************************** - SOFTWARE API FOR WDTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSetMode -//* \brief Set Watchdog Mode Register -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTSetMode( - AT91PS_WDTC pWDTC, - unsigned int Mode) -{ - pWDTC->WDTC_WDMR = Mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTRestart -//* \brief Restart Watchdog -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTRestart( - AT91PS_WDTC pWDTC) -{ - pWDTC->WDTC_WDCR = 0xA5000001; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSGettatus -//* \brief Get Watchdog Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_WDTSGettatus( - AT91PS_WDTC pWDTC) -{ - return(pWDTC->WDTC_WDSR & 0x3); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTGetPeriod -//* \brief Translate ms into Watchdog Compatible value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) -{ - if ((ms < 4) || (ms > 16000)) - return 0; - return((ms << 8) / 1000); -} -/* ***************************************************************************** - SOFTWARE API FOR MC - ***************************************************************************** */ - -#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_Remap -//* \brief Make Remap -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_Remap (void) // -{ - AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; - - pMC->MC_RCR = AT91C_MC_RCB; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_CfgModeReg -//* \brief Configure the EFC Mode Register of the MC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_CfgModeReg ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int mode) // mode register -{ - // Write to the FMR register - pMC->MC_FMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetModeReg -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetModeReg( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_ComputeFMCN -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_ComputeFMCN( - int master_clock) // master clock in Hz -{ - return (master_clock/1000000 +2); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_PerformCmd -//* \brief Perform EFC Command -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_PerformCmd ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int transfer_cmd) -{ - pMC->MC_FCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetStatus -//* \brief Return MC EFC Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetStatus( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptMasked -//* \brief Test if EFC MC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetModeReg(pMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptSet -//* \brief Test if EFC MC Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptSet( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetStatus(pMC) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR CAN - ***************************************************************************** */ -#define STANDARD_FORMAT 0 -#define EXTENDED_FORMAT 1 - -//*---------------------------------------------------------------------------- -//* \fn AT91F_InitMailboxRegisters() -//* \brief Configure the corresponding mailbox -//*---------------------------------------------------------------------------- -__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, - int mode_reg, - int acceptance_mask_reg, - int id_reg, - int data_low_reg, - int data_high_reg, - int control_reg) -{ - CAN_Mailbox->CAN_MB_MCR = 0x0; - CAN_Mailbox->CAN_MB_MMR = mode_reg; - CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; - CAN_Mailbox->CAN_MB_MID = id_reg; - CAN_Mailbox->CAN_MB_MDL = data_low_reg; - CAN_Mailbox->CAN_MB_MDH = data_high_reg; - CAN_Mailbox->CAN_MB_MCR = control_reg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EnableCAN() -//* \brief -//*---------------------------------------------------------------------------- -__inline void AT91F_EnableCAN( - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - pCAN->CAN_MR |= AT91C_CAN_CANEN; - - // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver - while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DisableCAN() -//* \brief -//*---------------------------------------------------------------------------- -__inline void AT91F_DisableCAN( - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - pCAN->CAN_MR &= ~AT91C_CAN_CANEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_EnableIt -//* \brief Enable CAN interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_EnableIt ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pCAN->CAN_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_DisableIt -//* \brief Disable CAN interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_DisableIt ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pCAN->CAN_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetStatus -//* \brief Return CAN Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - return pCAN->CAN_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetInterruptMaskStatus -//* \brief Return CAN Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - return pCAN->CAN_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_IsInterruptMasked -//* \brief Test if CAN Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_IsInterruptMasked( - AT91PS_CAN pCAN, // \arg pointer to a CAN controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_IsStatusSet -//* \brief Test if CAN Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_IsStatusSet( - AT91PS_CAN pCAN, // \arg pointer to a CAN controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_CAN_GetStatus(pCAN) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgModeReg -//* \brief Configure the Mode Register of the CAN controller -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgModeReg ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pCAN->CAN_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetModeReg -//* \brief Return the Mode Register of the CAN controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetModeReg ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgBaudrateReg -//* \brief Configure the Baudrate of the CAN controller for the network -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgBaudrateReg ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int baudrate_cfg) -{ - //* Write to the BR register - pCAN->CAN_BR = baudrate_cfg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetBaudrate -//* \brief Return the Baudrate of the CAN controller for the network value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetBaudrate ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_BR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetInternalCounter -//* \brief Return CAN Timer Regsiter Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetInternalCounter ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_TIM; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetTimestamp -//* \brief Return CAN Timestamp Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetTimestamp ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_TIMESTP; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetErrorCounter -//* \brief Return CAN Error Counter Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetErrorCounter ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_ECR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_InitTransferRequest -//* \brief Request for a transfer on the corresponding mailboxes -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_InitTransferRequest ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int transfer_cmd) -{ - pCAN->CAN_TCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_InitAbortRequest -//* \brief Abort the corresponding mailboxes -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_InitAbortRequest ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int abort_cmd) -{ - pCAN->CAN_ACR = abort_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageModeReg -//* \brief Program the Message Mode Register -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageModeReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int mode) -{ - CAN_Mailbox->CAN_MB_MMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageModeReg -//* \brief Return the Message Mode Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageModeReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageIDReg -//* \brief Program the Message ID Register -//* \brief Version == 0 for Standard messsage, Version == 1 for Extended -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageIDReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int id, - unsigned char version) -{ - if(version==0) // IDvA Standard Format - CAN_Mailbox->CAN_MB_MID = id<<18; - else // IDvB Extended Format - CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageIDReg -//* \brief Return the Message ID Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageIDReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MID; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg -//* \brief Program the Message Acceptance Mask Register -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int mask) -{ - CAN_Mailbox->CAN_MB_MAM = mask; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg -//* \brief Return the Message Acceptance Mask Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MAM; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetFamilyID -//* \brief Return the Message ID Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetFamilyID ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MFID; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageCtrl -//* \brief Request and config for a transfer on the corresponding mailbox -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageCtrlReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int message_ctrl_cmd) -{ - CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageStatus -//* \brief Return CAN Mailbox Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageStatus ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageDataLow -//* \brief Program data low value -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageDataLow ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int data) -{ - CAN_Mailbox->CAN_MB_MDL = data; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageDataLow -//* \brief Return data low value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageDataLow ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MDL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageDataHigh -//* \brief Program data high value -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageDataHigh ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int data) -{ - CAN_Mailbox->CAN_MB_MDH = data; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageDataHigh -//* \brief Return data high value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageDataHigh ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MDH; -} - -/* ***************************************************************************** - SOFTWARE API FOR TC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptEnable -//* \brief Enable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptEnable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be enabled -{ - pTc->TC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptDisable -//* \brief Disable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptDisable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be disabled -{ - pTc->TC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_GetInterruptMaskStatus -//* \brief Return TC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status - AT91PS_TC pTc) // \arg pointer to a TC controller -{ - return pTc->TC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_IsInterruptMasked -//* \brief Test if TC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TC_IsInterruptMasked( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR MCI - ***************************************************************************** */ -//* Classic MCI Data Timeout Register Configuration with 1048576 MCK cycles between 2 data transfer -#define AT91C_MCI_DTOR_1MEGA_CYCLES (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL) - -//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot A -#define AT91C_MCI_MMC_SLOTA (AT91C_MCI_SCDSEL & 0x0) - -//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot B -#define AT91C_MCI_MMC_SLOTB (AT91C_MCI_SCDSEL & 0x1) - -//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot A -#define AT91C_MCI_SDCARD_4BITS_SLOTA ( (AT91C_MCI_SCDSEL & 0x0) | AT91C_MCI_SCDBUS ) - -//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot B -#define AT91C_MCI_SDCARD_4BITS_SLOTB ( (AT91C_MCI_SCDSEL & 0x1) | AT91C_MCI_SCDBUS ) - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Configure -//* \brief Configure the MCI -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_Configure ( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int DTOR_register, // \arg Data Timeout Register to be programmed - unsigned int MR_register, // \arg Mode Register to be programmed - unsigned int SDCR_register) // \arg SDCard Register to be programmed -{ - //* Disable the MCI - pMCI->MCI_CR = AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS; - - //* Disable all the interrupts - pMCI->MCI_IDR = 0xFFFFFFFF; - - //* Set the Data Timeout Register - pMCI->MCI_DTOR = DTOR_register; - - //* Set the Mode Register - pMCI->MCI_MR = MR_register; - - //* Set the SDCard Register - pMCI->MCI_SDCR = SDCR_register; - - //* Enable the MCI - pMCI->MCI_CR = AT91C_MCI_MCIEN | AT91C_MCI_PWSEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_EnableIt -//* \brief Enable MCI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_EnableIt ( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pMCI->MCI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_DisableIt -//* \brief Disable MCI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_DisableIt ( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pMCI->MCI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetStatus -//* \brief Return MCI Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MCI_GetStatus( // \return MCI Interrupt Status - AT91PS_MCI pMCI) // pointer to a MCI controller -{ - return pMCI->MCI_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetInterruptMaskStatus -//* \brief Return MCI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MCI_GetInterruptMaskStatus( // \return MCI Interrupt Mask Status - AT91PS_MCI pMCI) // pointer to a MCI controller -{ - return pMCI->MCI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_IsInterruptMasked -//* \brief Test if MCI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MCI_IsInterruptMasked( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MCI_GetInterruptMaskStatus(pMCI) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_IsStatusSet -//* \brief Test if MCI Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MCI_IsStatusSet( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MCI_GetStatus(pMCI) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Enable -//* \brief Enable the MCI Interface -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_Enable ( - AT91PS_MCI pMCI) // \arg pointer to a MCI controller -{ - //* Enable the MCI - pMCI->MCI_CR = AT91C_MCI_MCIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Disable -//* \brief Disable the MCI Interface -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_Disable ( - AT91PS_MCI pMCI) // \arg pointer to a MCI controller -{ - //* Disable the MCI - pMCI->MCI_CR = AT91C_MCI_MCIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SW_Reset -//* \brief Reset the MCI Interface -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_SW_Reset ( - AT91PS_MCI pMCI) // \arg pointer to a MCI controller -{ - //* Disable the MCI - pMCI->MCI_CR = AT91C_MCI_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_CfgModeReg -//* \brief Configure the Mode Register of the MCI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_CfgModeReg ( - AT91PS_MCI pMCI, // pointer to a MCI controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pMCI->MCI_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetModeReg -//* \brief Return the Mode Register of the MCI controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MCI_GetModeReg ( - AT91PS_MCI pMCI // pointer to a MCI controller - ) -{ - return pMCI->MCI_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_CfgFrequency -//* \brief Configure the frequency MCCK of the MCI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_CfgFrequency ( - AT91PS_MCI pMCI, // pointer to a MCI controller - unsigned int mck_clock, // in MHz - unsigned int mci_clock) // in MHz -{ - unsigned int prescal; - - prescal = mck_clock/(2*mci_clock) - 1; - - //* Write to the MR register - pMCI->MCI_MR &= ~AT91C_MCI_CLKDIV; - pMCI->MCI_MR |= (prescal & AT91C_MCI_CLKDIV); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_CfgDataTimeOutReg -//* \brief Configure the Data TimeOut Register of the MCI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_CfgDataTimeOutReg ( - AT91PS_MCI pMCI, // pointer to a MCI controller - unsigned int cfg) -{ - //* Write to the DTOR register - pMCI->MCI_DTOR = cfg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetDataTimeOutReg -//* \brief Return the Data TimeOut Register of the MCI controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MCI_GetDataTimeOutReg ( - AT91PS_MCI pMCI // pointer to a MCI controller - ) -{ - return pMCI->MCI_DTOR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_CfgSDCardReg -//* \brief Configure the SDCard Register of the MCI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_CfgSDCardReg ( - AT91PS_MCI pMCI, // pointer to a MCI controller - unsigned int cfg) -{ - //* Write to the SDCR register - pMCI->MCI_SDCR = cfg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetSDCardReg -//* \brief Return the SDCard Register of the MCI controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MCI_GetSDCardReg ( - AT91PS_MCI pMCI // pointer to a MCI controller - ) -{ - return pMCI->MCI_SDCR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_CfgARGReg -//* \brief Configure the Command ARGUMENT Register of the MCI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_CfgARGReg ( - AT91PS_MCI pMCI, // pointer to a MCI controller - unsigned int arg) -{ - //* Write to the ARG register - pMCI->MCI_ARGR = arg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetARGReg -//* \brief Return the Command ARGUMENT Register of the MCI controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MCI_GetARGReg ( - AT91PS_MCI pMCI // pointer to a MCI controller - ) -{ - return pMCI->MCI_ARGR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_CfgCMDReg -//* \brief Configure the COMMAND Register of the MCI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_CfgCMDReg ( - AT91PS_MCI pMCI, // pointer to a MCI controller - unsigned int cmd) -{ - //* Write to the ARG register - pMCI->MCI_CMDR = cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetRSP0Reg -//* \brief Return the RESPONSE Register 0 of the MCI controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MCI_GetRSP0Reg ( - AT91PS_MCI pMCI // pointer to a MCI controller - ) -{ - return pMCI->MCI_RSPR[0]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetRSP1Reg -//* \brief Return the RESPONSE Register 1 of the MCI controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MCI_GetRSP1Reg ( - AT91PS_MCI pMCI // pointer to a MCI controller - ) -{ - return pMCI->MCI_RSPR[0]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetRSP2Reg -//* \brief Return the RESPONSE Register 2 of the MCI controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MCI_GetRSP2Reg ( - AT91PS_MCI pMCI // pointer to a MCI controller - ) -{ - return pMCI->MCI_RSPR[0]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetRSP3Reg -//* \brief Return the RESPONSE Register 3 of the MCI controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MCI_GetRSP3Reg ( - AT91PS_MCI pMCI // pointer to a MCI controller - ) -{ - return pMCI->MCI_RSPR[0]; -} - -/* ***************************************************************************** - SOFTWARE API FOR UDP - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableIt -//* \brief Enable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUDP->UDP_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableIt -//* \brief Disable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pUDP->UDP_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetAddress -//* \brief Set UDP functional address -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetAddress ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char address) // \arg new UDP address -{ - pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetState -//* \brief Set UDP Device state -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetState ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg new UDP address -{ - pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetState -//* \brief return UDP Device state -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state - AT91PS_UDP pUDP) // \arg pointer to a UDP controller -{ - return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_ResetEp -//* \brief Reset UDP endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_ResetEp ( // \return the UDP device state - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg Endpoints to be reset -{ - pUDP->UDP_RSTEP = flag; - pUDP->UDP_RSTEP = 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStall -//* \brief Endpoint will STALL requests -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpStall( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpWrite -//* \brief Write value in the DPR -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpWrite( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned char value) // \arg value to be written in the DPR -{ - pUDP->UDP_FDR[endpoint] = value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpRead -//* \brief Return value from the DPR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpRead( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_FDR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpEndOfWr -//* \brief Notify the UDP that values in DPR are ready to be sent -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpEndOfWr( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpClear -//* \brief Clear flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpClear( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] &= ~(flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpSet -//* \brief Set flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpSet( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStatus -//* \brief Return the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpStatus( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_CSR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetInterruptMaskStatus -//* \brief Return UDP Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( - AT91PS_UDP pUdp) // \arg pointer to a UDP controller -{ - return pUdp->UDP_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_IsInterruptMasked -//* \brief Test if UDP Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_UDP_IsInterruptMasked( - AT91PS_UDP pUdp, // \arg pointer to a UDP controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_UDP_InterruptStatusRegister -// \brief Return the Interrupt Status Register -// ---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_InterruptStatusRegister( - AT91PS_UDP pUDP ) // \arg pointer to a UDP controller -{ - return pUDP->UDP_ISR; -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_UDP_InterruptClearRegister -// \brief Clear Interrupt Register -// ---------------------------------------------------------------------------- -__inline void AT91F_UDP_InterruptClearRegister ( - AT91PS_UDP pUDP, // \arg pointer to UDP controller - unsigned int flag) // \arg IT to be cleat -{ - pUDP->UDP_ICR = flag; -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_UDP_EnableTransceiver -// \brief Enable transceiver -// ---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableTransceiver( - AT91PS_UDP pUDP ) // \arg pointer to a UDP controller -{ - pUDP->UDP_TXVC &= ~AT91C_UDP_TXVDIS; -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_UDP_DisableTransceiver -// \brief Disable transceiver -// ---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableTransceiver( - AT91PS_UDP pUDP ) // \arg pointer to a UDP controller -{ - pUDP->UDP_TXVC = AT91C_UDP_TXVDIS; -} - -/* ***************************************************************************** - SOFTWARE API FOR TWI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_EnableIt -//* \brief Enable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_EnableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pTWI->TWI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_DisableIt -//* \brief Disable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_DisableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pTWI->TWI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_Configure -//* \brief Configure TWI in master mode -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller -{ - //* Disable interrupts - pTWI->TWI_IDR = (unsigned int) -1; - - //* Reset peripheral - pTWI->TWI_CR = AT91C_TWI_SWRST; - - //* Set Master mode - pTWI->TWI_CR = AT91C_TWI_MSEN; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_GetInterruptMaskStatus -//* \brief Return TWI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status - AT91PS_TWI pTwi) // \arg pointer to a TWI controller -{ - return pTwi->TWI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_IsInterruptMasked -//* \brief Test if TWI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TWI_IsInterruptMasked( - AT91PS_TWI pTwi, // \arg pointer to a TWI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR USART - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Calculate the baudrate -//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_EXT ) - -//* Standard Synchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ - AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* SCK used Label -#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) - -//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity -#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ - AT91C_US_CLKS_CLOCK +\ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_EVEN + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CKLO +\ - AT91C_US_OVER) - -//* Standard IRDA mode -#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Caluculate baud_value according to the main clock and the baud rate -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Baudrate ( - const unsigned int main_clock, // \arg peripheral clock - const unsigned int baud_rate) // \arg UART baudrate -{ - unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - return baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetBaudrate ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg UART baudrate -{ - //* Define the baud rate divisor register - pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetTimeguard -//* \brief Set USART timeguard -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetTimeguard ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int timeguard) // \arg timeguard value -{ - //* Write the Timeguard Register - pUSART->US_TTGR = timeguard ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableIt -//* \brief Enable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUSART->US_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableIt -//* \brief Disable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IER register - pUSART->US_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Configure -//* \brief Configure USART -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Configure ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int mode , // \arg mode Register to be programmed - unsigned int baudRate , // \arg baudrate to be programmed - unsigned int timeguard ) // \arg timeguard to be programmed -{ - //* Disable interrupts - pUSART->US_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; - - //* Define the baud rate divisor register - AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); - - //* Write the Timeguard Register - AT91F_US_SetTimeguard(pUSART, timeguard); - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Define the USART mode - pUSART->US_MR = mode ; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableRx -//* \brief Enable receiving characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableTx -//* \brief Enable sending characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetRx -//* \brief Reset Receiver and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset receiver - pUSART->US_CR = AT91C_US_RSTRX; - //* Re-Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetTx -//* \brief Reset Transmitter and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset transmitter - pUSART->US_CR = AT91C_US_RSTTX; - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableRx -//* \brief Disable Receiver -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable receiver - pUSART->US_CR = AT91C_US_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableTx -//* \brief Disable Transmitter -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable transmitter - pUSART->US_CR = AT91C_US_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Close -//* \brief Close USART: disable IT disable receiver and transmitter, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Close ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset the baud rate divisor register - pUSART->US_BRGR = 0 ; - - //* Reset the USART mode - pUSART->US_MR = 0 ; - - //* Reset the Timeguard Register - pUSART->US_TTGR = 0; - - //* Disable all interrupts - pUSART->US_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_TxReady -//* \brief Return 1 if a character can be written in US_THR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_TxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_TXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_RxReady -//* \brief Return 1 if a character can be read in US_RHR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_RxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_RXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Error -//* \brief Return the error flag -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Error ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & - (AT91C_US_OVRE | // Overrun error - AT91C_US_FRAME | // Framing error - AT91C_US_PARE)); // Parity error -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_US_PutChar ( - AT91PS_USART pUSART, - int character ) -{ - pUSART->US_THR = (character & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_US_GetChar ( - const AT91PS_USART pUSART) -{ - return((pUSART->US_RHR) & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_SendFrame( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_ReceiveFrame ( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetIrdaFilter -//* \brief Set the value of IrDa filter tregister -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetIrdaFilter ( - AT91PS_USART pUSART, - unsigned char value -) -{ - pUSART->US_IF = value; -} - -/* ***************************************************************************** - SOFTWARE API FOR PWMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetStatus -//* \brief Return PWM Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status - AT91PS_PWMC pPWM) // pointer to a PWM controller -{ - return pPWM->PWMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptEnable -//* \brief Enable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptEnable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be enabled -{ - pPwm->PWMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptDisable -//* \brief Disable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptDisable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be disabled -{ - pPwm->PWMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetInterruptMaskStatus -//* \brief Return PWM Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status - AT91PS_PWMC pPwm) // \arg pointer to a PWM controller -{ - return pPwm->PWMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsInterruptMasked -//* \brief Test if PWM Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsInterruptMasked( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsStatusSet -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsStatusSet( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_CfgChannel -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int mode, // \arg PWM mode - unsigned int period, // \arg PWM period - unsigned int duty) // \arg PWM duty cycle -{ - pPWM->PWMC_CH[channelId].PWMC_CMR = mode; - pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; - pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StartChannel -//* \brief Enable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StartChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_ENA = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StopChannel -//* \brief Disable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StopChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_DIS = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_UpdateChannel -//* \brief Update Period or Duty Cycle -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_UpdateChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int update) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; -} - -/* ***************************************************************************** - SOFTWARE API FOR SSC - ***************************************************************************** */ -//* Define the standard I2S mode configuration - -//* Configuration to set in the SSC Transmit Clock Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - AT91C_SSC_CKS_DIV +\ - AT91C_SSC_CKO_CONTINOUS +\ - AT91C_SSC_CKG_NONE +\ - AT91C_SSC_START_FALL_RF +\ - AT91C_SSC_STTOUT +\ - ((1<<16) & AT91C_SSC_STTDLY) +\ - ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) - - -//* Configuration to set in the SSC Transmit Frame Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - (nb_bit_by_slot-1) +\ - AT91C_SSC_MSBF +\ - (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ - (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ - AT91C_SSC_FSOS_NEGATIVE) - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_SetBaudrate ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg SSC baudrate -{ - unsigned int baud_value; - //* Define the baud rate divisor register - if (speed == 0) - baud_value = 0; - else - { - baud_value = (unsigned int) (mainClock * 10)/(2*speed); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - } - - pSSC->SSC_CMR = baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_Configure -//* \brief Configure SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_Configure ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int syst_clock, // \arg System Clock Frequency - unsigned int baud_rate, // \arg Expected Baud Rate Frequency - unsigned int clock_rx, // \arg Receiver Clock Parameters - unsigned int mode_rx, // \arg mode Register to be programmed - unsigned int clock_tx, // \arg Transmitter Clock Parameters - unsigned int mode_tx) // \arg mode Register to be programmed -{ - //* Disable interrupts - pSSC->SSC_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; - - //* Define the Clock Mode Register - AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); - - //* Write the Receive Clock Mode Register - pSSC->SSC_RCMR = clock_rx; - - //* Write the Transmit Clock Mode Register - pSSC->SSC_TCMR = clock_tx; - - //* Write the Receive Frame Mode Register - pSSC->SSC_RFMR = mode_rx; - - //* Write the Transmit Frame Mode Register - pSSC->SSC_TFMR = mode_tx; - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); - - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableRx -//* \brief Enable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable receiver - pSSC->SSC_CR = AT91C_SSC_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableRx -//* \brief Disable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable receiver - pSSC->SSC_CR = AT91C_SSC_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableTx -//* \brief Enable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable transmitter - pSSC->SSC_CR = AT91C_SSC_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableTx -//* \brief Disable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable transmitter - pSSC->SSC_CR = AT91C_SSC_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableIt -//* \brief Enable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pSSC->SSC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableIt -//* \brief Disable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pSSC->SSC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_ReceiveFrame ( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_SendFrame( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_GetInterruptMaskStatus -//* \brief Return SSC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status - AT91PS_SSC pSsc) // \arg pointer to a SSC controller -{ - return pSsc->SSC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_IsInterruptMasked -//* \brief Test if SSC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SSC_IsInterruptMasked( - AT91PS_SSC pSsc, // \arg pointer to a SSC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR ADC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableIt -//* \brief Enable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pADC->ADC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableIt -//* \brief Disable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pADC->ADC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetStatus -//* \brief Return ADC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetInterruptMaskStatus -//* \brief Return ADC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsInterruptMasked -//* \brief Test if ADC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsInterruptMasked( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsStatusSet -//* \brief Test if ADC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsStatusSet( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgModeReg -//* \brief Configure the Mode Register of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgModeReg ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pADC->ADC_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetModeReg -//* \brief Return the Mode Register of the ADC controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetModeReg ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgTimings -//* \brief Configure the different necessary timings of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgTimings ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mck_clock, // in MHz - unsigned int adc_clock, // in MHz - unsigned int startup_time, // in us - unsigned int sample_and_hold_time) // in ns -{ - unsigned int prescal,startup,shtim; - - prescal = mck_clock/(2*adc_clock) - 1; - startup = adc_clock*startup_time/8 - 1; - shtim = adc_clock*sample_and_hold_time/1000 - 1; - - //* Write to the MR register - pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHER register - pADC->ADC_CHER = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHDR register - pADC->ADC_CHDR = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetChannelStatus -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetChannelStatus ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CHSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_StartConversion -//* \brief Software request for a analog to digital conversion -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_StartConversion ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_SoftReset -//* \brief Software reset -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_SoftReset ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetLastConvertedData -//* \brief Return the Last Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetLastConvertedData ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_LCDR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH0 -//* \brief Return the Channel 0 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH1 -//* \brief Return the Channel 1 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR1; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH2 -//* \brief Return the Channel 2 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR2; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH3 -//* \brief Return the Channel 3 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR3; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH4 -//* \brief Return the Channel 4 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH5 -//* \brief Return the Channel 5 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR5; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH6 -//* \brief Return the Channel 6 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR6; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH7 -//* \brief Return the Channel 7 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR7; -} - -/* ***************************************************************************** - SOFTWARE API FOR SPI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgCs -//* \brief Configure SPI chip select register -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgCs ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int cs, // SPI cs number (0 to 3) - int val) // chip select register -{ - //* Write to the CSR register - *(pSPI->SPI_CSR + cs) = val; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_EnableIt -//* \brief Enable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_EnableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pSPI->SPI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_DisableIt -//* \brief Disable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_DisableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pSPI->SPI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Reset -//* \brief Reset the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Reset ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Enable -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Enable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Disable -//* \brief Disable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Disable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgMode -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgMode ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int mode) // mode register -{ - //* Write to the MR register - pSPI->SPI_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPCS -//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgPCS ( - AT91PS_SPI pSPI, // pointer to a SPI controller - char PCS_Device) // PCS of the Device -{ - //* Write to the MR register - pSPI->SPI_MR &= 0xFFF0FFFF; - pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_ReceiveFrame ( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_SendFrame( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Close -//* \brief Close SPI: disable IT disable transfert, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Close ( - AT91PS_SPI pSPI) // \arg pointer to a SPI controller -{ - //* Reset all the Chip Select register - pSPI->SPI_CSR[0] = 0 ; - pSPI->SPI_CSR[1] = 0 ; - pSPI->SPI_CSR[2] = 0 ; - pSPI->SPI_CSR[3] = 0 ; - - //* Reset the SPI mode - pSPI->SPI_MR = 0 ; - - //* Disable all interrupts - pSPI->SPI_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_PutChar ( - AT91PS_SPI pSPI, - unsigned int character, - unsigned int cs_number ) -{ - unsigned int value_for_cs; - value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number - pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_GetChar ( - const AT91PS_SPI pSPI) -{ - return((pSPI->SPI_RDR) & 0xFFFF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetInterruptMaskStatus -//* \brief Return SPI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status - AT91PS_SPI pSpi) // \arg pointer to a SPI controller -{ - return pSpi->SPI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_IsInterruptMasked -//* \brief Test if SPI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_IsInterruptMasked( - AT91PS_SPI pSpi, // \arg pointer to a SPI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_CfgPMC -//* \brief Enable Peripheral clock in PMC for MC -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPMC -//* \brief Enable Peripheral clock in PMC for DBGU -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPIO -//* \brief Configure PIO controllers to drive DBGU signals -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA31_DTXD ) | - ((unsigned int) AT91C_PA30_DRXD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH0_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA18_PWM0 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB14_PWM0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH1_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA19_PWM1 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB15_PWM1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH2_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA20_PWM2 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB16_PWM2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH3_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH3 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH3_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA21_PWM3 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB17_PWM3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH4_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH4 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH4_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA22_PWM4 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB18_PWM4 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH5_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH5 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH5_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA23_PWM5 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB0_PWM5 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH6_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH6 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH6_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA24_PWM6 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB1_PWM6 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH7_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH7 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH7_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA25_PWM7 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB2_PWM7 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SHDWC_CfgPMC -//* \brief Enable Peripheral clock in PMC for SHDWC -//*---------------------------------------------------------------------------- -__inline void AT91F_SHDWC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI0_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI0 -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI0_CfgPIO -//* \brief Configure PIO controllers to drive SPI0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA16_SPI0_MOSI) | - ((unsigned int) AT91C_PA11_SPI0_NPCS0) | - ((unsigned int) AT91C_PA12_SPI0_NPCS1) | - ((unsigned int) AT91C_PA15_SPI0_MISO) | - ((unsigned int) AT91C_PA13_SPI0_NPCS2) | - ((unsigned int) AT91C_PA17_SPI0_SPCK) | - ((unsigned int) AT91C_PA14_SPI0_NPCS3), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI1_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI1 -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI1_CfgPIO -//* \brief Configure PIO controllers to drive SPI1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA9_SPI1_MOSI) | - ((unsigned int) AT91C_PA4_SPI1_NPCS0) | - ((unsigned int) AT91C_PA8_SPI1_MISO) | - ((unsigned int) AT91C_PA5_SPI1_NPCS1) | - ((unsigned int) AT91C_PA10_SPI1_SPCK) | - ((unsigned int) AT91C_PA6_SPI1_NPCS2) | - ((unsigned int) AT91C_PA7_SPI1_NPCS3)); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB19_SPI1_NPCS1) | - ((unsigned int) AT91C_PB20_SPI1_NPCS2) | - ((unsigned int) AT91C_PB21_SPI1_NPCS3)); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC0 -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC0_CfgPIO -//* \brief Configure PIO controllers to drive SSC0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB7_RF0 ) | - ((unsigned int) AT91C_PB3_TK0 ) | - ((unsigned int) AT91C_PB6_RK0 ) | - ((unsigned int) AT91C_PB4_TD0 ) | - ((unsigned int) AT91C_PB5_RD0 ) | - ((unsigned int) AT91C_PB2_TF0 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC1 -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC1_CfgPIO -//* \brief Configure PIO controllers to drive SSC1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB9_TK1 ) | - ((unsigned int) AT91C_PB11_RF1 ) | - ((unsigned int) AT91C_PB10_RK1 ) | - ((unsigned int) AT91C_PB12_TD1 ) | - ((unsigned int) AT91C_PB13_RD1 ) | - ((unsigned int) AT91C_PB8_TF1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PWMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PWMC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC0 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPIO -//* \brief Configure PIO controllers to drive TC0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB12_TIOA0 ) | - ((unsigned int) AT91C_PB13_TIOB0 ) | - ((unsigned int) AT91C_PB9_TCLK0 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC1 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPIO -//* \brief Configure PIO controllers to drive TC1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB14_TIOA1 ) | - ((unsigned int) AT91C_PB15_TIOB1 ) | - ((unsigned int) AT91C_PB10_TCLK1 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC2 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPIO -//* \brief Configure PIO controllers to drive TC2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB16_TIOA2 ) | - ((unsigned int) AT91C_PB17_TIOB2 ) | - ((unsigned int) AT91C_PB11_TCLK2 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC3_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC3 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC3_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC3)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC3_CfgPIO -//* \brief Configure PIO controllers to drive TC3 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC3_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA28_TCLK3 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB18_TIOA3 ) | - ((unsigned int) AT91C_PB19_TIOB3 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC4_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC4 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC4_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC4)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC4_CfgPIO -//* \brief Configure PIO controllers to drive TC4 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC4_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA24_TCLK4 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB21_TIOB4 ) | - ((unsigned int) AT91C_PB20_TIOA4 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC5_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC5 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC5_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC5)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC5_CfgPIO -//* \brief Configure PIO controllers to drive TC5 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC5_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA25_TCLK5 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB23_TIOB5 ) | - ((unsigned int) AT91C_PB22_TIOA5 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC6_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC6 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC6_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC6)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC6_CfgPIO -//* \brief Configure PIO controllers to drive TC6 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC6_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA29_TCLK6 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB24_TIOA6 ) | - ((unsigned int) AT91C_PB25_TIOB6 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC7_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC7 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC7_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC7)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC7_CfgPIO -//* \brief Configure PIO controllers to drive TC7 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC7_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA30_TCLK7 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB26_TIOA7 ) | - ((unsigned int) AT91C_PB27_TIOB7 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC8_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC8 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC8_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC8)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC8_CfgPIO -//* \brief Configure PIO controllers to drive TC8 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC8_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA31_TCLK8 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB28_TIOA8 ) | - ((unsigned int) AT91C_PB29_TIOB8 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PITC -//*---------------------------------------------------------------------------- -__inline void AT91F_PITC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for ADC0 -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_ADC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC0_CfgPIO -//* \brief Configure PIO controllers to drive ADC0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA0_ADTRG0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for ADC1 -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_ADC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC1_CfgPIO -//* \brief Configure PIO controllers to drive ADC1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA1_ADTRG1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPIO -//* \brief Configure PIO controllers to drive PMC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA19_PCK1 ) | - ((unsigned int) AT91C_PA20_PCK2 ) | - ((unsigned int) AT91C_PA21_PCK3 ) | - ((unsigned int) AT91C_PA18_PCK0 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB4_PCK1 ) | - ((unsigned int) AT91C_PB5_PCK2 ) | - ((unsigned int) AT91C_PB6_PCK3 ) | - ((unsigned int) AT91C_PB3_PCK0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RSTC -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOA_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOA -//*---------------------------------------------------------------------------- -__inline void AT91F_PIOA_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOA)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOB_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOB -//*---------------------------------------------------------------------------- -__inline void AT91F_PIOB_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOB)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RTTC -//*---------------------------------------------------------------------------- -__inline void AT91F_RTTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPMC -//* \brief Enable Peripheral clock in PMC for TWI -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TWI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPIO -//* \brief Configure PIO controllers to drive TWI signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA0_TWD ) | - ((unsigned int) AT91C_PA1_TWCK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPMC -//* \brief Enable Peripheral clock in PMC for US0 -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPIO -//* \brief Configure PIO controllers to drive US0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA2_RXD0 ) | - ((unsigned int) AT91C_PA3_TXD0 ) | - ((unsigned int) AT91C_PA5_RTS0 ) | - ((unsigned int) AT91C_PA4_SCK0 ) | - ((unsigned int) AT91C_PA6_CTS0 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPMC -//* \brief Enable Peripheral clock in PMC for US1 -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPIO -//* \brief Configure PIO controllers to drive US1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA7_RXD1 ) | - ((unsigned int) AT91C_PA8_TXD1 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB26_SCK1 ) | - ((unsigned int) AT91C_PB24_RTS1 ) | - ((unsigned int) AT91C_PB25_CTS1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US2_CfgPMC -//* \brief Enable Peripheral clock in PMC for US2 -//*---------------------------------------------------------------------------- -__inline void AT91F_US2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US2_CfgPIO -//* \brief Configure PIO controllers to drive US2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA10_TXD2 ) | - ((unsigned int) AT91C_PA9_RXD2 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB28_CTS2 ) | - ((unsigned int) AT91C_PB29_SCK2 ) | - ((unsigned int) AT91C_PB27_RTS2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_CfgPMC -//* \brief Enable Peripheral clock in PMC for MCI -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_MCI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_CfgPIO -//* \brief Configure PIO controllers to drive MCI signals -//*---------------------------------------------------------------------------- -__inline void AT91F_MCI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA14_MCDA3 ) | - ((unsigned int) AT91C_PA16_MCCDA ) | - ((unsigned int) AT91C_PA15_MCDA0 ) | - ((unsigned int) AT91C_PA17_MCCK ) | - ((unsigned int) AT91C_PA12_MCDA1 ) | - ((unsigned int) AT91C_PA13_MCDA2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for WDTC -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UDP -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_UDP)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPMC -//* \brief Enable Peripheral clock in PMC for AIC -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_IRQ1) | - ((unsigned int) 1 << AT91C_ID_IRQ2) | - ((unsigned int) 1 << AT91C_ID_FIQ) | - ((unsigned int) 1 << AT91C_ID_IRQ3) | - ((unsigned int) 1 << AT91C_ID_IRQ0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPIO -//* \brief Configure PIO controllers to drive AIC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA22_IRQ0 ) | - ((unsigned int) AT91C_PA23_IRQ1 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB8_FIQ ) | - ((unsigned int) AT91C_PB0_IRQ2 ) | - ((unsigned int) AT91C_PB1_IRQ3 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN0_CfgPMC -//* \brief Enable Peripheral clock in PMC for CAN0 -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_CAN0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN0_CfgPIO -//* \brief Configure PIO controllers to drive CAN0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA27_CANTX0 ) | - ((unsigned int) AT91C_PA26_CANRX0 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN1_CfgPMC -//* \brief Enable Peripheral clock in PMC for CAN1 -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_CAN1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN1_CfgPIO -//* \brief Configure PIO controllers to drive CAN1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA29_CANTX1 ) | - ((unsigned int) AT91C_PA28_CANRX1 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB7_CANTX1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_SetBaudRate -//* \brief Set baud rate for DBGU -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_SetBaudRate( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int cd) // \arg dbgu CD -{ - pDbgu->DBGU_BRGR = cd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_Configure -//* \brief Configure DBGU -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_Configure ( - AT91PS_DBGU pDbgu, // \arg pointer to a USART controller - unsigned int bd, // \arg baudrate to be programmed - unsigned int mode) // \arg mode Register to be programmed -{ - // Disable interrupts - pDbgu->DBGU_IDR = (unsigned int) -1; - // Reset receiver and transmitter - pDbgu->DBGU_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS | AT91C_US_RSTSTA; - // Define the baud rate divisor register - AT91F_DBGU_SetBaudRate(pDbgu, bd); - // Define the DBGU mode - pDbgu->DBGU_MR = mode; -} - -__inline void AT91F_DBGU_EnableRx ( - AT91PS_DBGU pDbgu) // \arg pointer to a USART controller -{ - //* Enable receiver - pDbgu->DBGU_CR = AT91C_US_RXEN; -} - -__inline void AT91F_DBGU_EnableTx ( - AT91PS_DBGU pDbgu) // \arg pointer to a USART controller -{ - //* Enable transmitter - pDbgu->DBGU_CR = AT91C_US_TXEN; -} - -__inline void AT91F_DBGU_PutChar ( - AT91PS_DBGU pDbgu, - unsigned char character ) -{ - pDbgu->DBGU_THR = (character & 0xFF); -} - -__inline unsigned int AT91F_DBGU_IsENDTXInt ( - AT91PS_DBGU pDbgu ) // \arg pointer to a USART controller -{ - return (pDbgu->DBGU_CSR & AT91C_US_ENDTX); -} - -__inline unsigned int AT91F_DBGU_IsTXRDYInt ( - AT91PS_DBGU pDbgu ) // \arg pointer to a USART controller -{ - return (pDbgu->DBGU_CSR & AT91C_US_TXRDY); -} - -__inline unsigned int AT91F_DBGU_IsRXRDYInt( - AT91PS_DBGU pDbgu ) // \arg pointer to a USART controller -{ - return (pDbgu->DBGU_CSR & AT91C_US_RXRDY); -} - -__inline unsigned int AT91F_DBGU_IsOVREInt ( - AT91PS_DBGU pDbgu ) // \arg pointer to a USART controller -{ - return (pDbgu->DBGU_CSR & AT91C_US_OVRE); -} - -__inline unsigned int AT91F_DBGU_IsFRAMEInt ( - AT91PS_DBGU pDbgu ) // \arg pointer to a USART controller -{ - return (pDbgu->DBGU_CSR & AT91C_US_FRAME); -} - -__inline unsigned int AT91F_DBGU_IsPAREInt ( - AT91PS_DBGU pDbgu ) // \arg pointer to a USART controller -{ - return (pDbgu->DBGU_CSR & AT91C_US_PARE); -} - -__inline unsigned int AT91F_DBGU_IsTXEMPTYInt ( - AT91PS_DBGU pDbgu ) // \arg pointer to a USART controller -{ - return (pDbgu->DBGU_CSR & AT91C_US_TXEMPTY); -} - -__inline void AT91F_DBGU_ResetStatus ( - AT91PS_DBGU pDbgu ) // \arg pointer to a USART controller -{ - pDbgu->DBGU_CR = AT91C_US_RSTSTA; -} - -__inline unsigned char AT91F_DBGU_GetChar ( - AT91PS_DBGU pDbgu ) // \arg pointer to a USART controller -{ - return (AT91C_BASE_DBGU->DBGU_RHR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_Reset -//* \brief Reset PWM main registers -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_Reset( - AT91PS_PWMC pPWM) // pointer to a PWM controller -{ - pPWM->PWMC_MR = 0; //clock off -} - - -#endif // lib_AT91SAM7A3_H diff -Nru cpputest-3.7.2/platforms_startup/armcc/AT91SAM7A3/Makefile cpputest-3.7.2+dfsg/platforms_startup/armcc/AT91SAM7A3/Makefile --- cpputest-3.7.2/platforms_startup/armcc/AT91SAM7A3/Makefile 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/AT91SAM7A3/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,125 +0,0 @@ -# Makefile to create startup library for AT91SAM7A3 chip - -.SILENT: - -CPU = ARM7TDMI -CPU_MODE = thumb -TARGET_PLATFORM =armcc_$(CPU)_$(CPU_MODE) - -CPPUTEST_HOME = ../../.. - -# component name -COMPONENT_NAME = Startup_AT91SAM7A3 - -# directory to place artefacts -OBJS_DIR = objs - -# directory to place startup library -LIB_DIR = $(CPPUTEST_HOME)/lib/$(TARGET_PLATFORM) - -# directory with source files -SRC_DIRS = . - -# directory with header files -INCLUDE_DIRS = . - -# CYGWIN path -CYGWIN =C:/CYGWIN/bin -MKDIR =$(CYGWIN)/mkdir -RM =$(CYGWIN)/rm -TOUCH =$(CYGWIN)/touch - -KEIL_DIR=D:/Keil/ARM/ARMCC -CC=$(KEIL_DIR)/bin/armcc.exe -AS=$(KEIL_DIR)/bin/armasm.exe -AR=$(KEIL_DIR)/bin/armar.exe -# armcc system include path -SYS_INCLUDE_DIRS =$(KEIL_DIR)/include - -# adding Keil MDK-ARM system headers to build startup library -INCLUDE_DIRS +=$(SYS_INCLUDE_DIRS) - -CPUFLAGS =--cpu=$(CPU) -ifeq ($(CPU_MODE), thumb) - CPUFLAGS +=--apcs=/interwork -endif - -DEPFLAGS =-M \ - $(INCLUDES) \ - --depend_format=unix_escaped \ - --depend_single_line \ - --no_depend_system_headers - -OPTFLAGS =-O3 - -CPPUTEST_CPPFLAGS =$(CPUFLAGS) \ - $(OPTFLAGS) \ - -c \ - -g \ - $(INCLUDES) \ - --$(CPU_MODE) \ - -D__CLK_TCK=1000 \ - -ARFLAGS = --debug_symbols - - -TARGET_LIB = \ - $(LIB_DIR)/lib$(COMPONENT_NAME).a - -#Helper Functions -get_src_from_dir = $(wildcard $1/*.c) $(wildcard $1/*.asm) -get_src_from_dir_list = $(foreach dir, $1, $(call get_src_from_dir,$(dir))) -__src_to = $(subst .asm,$1, $(subst .c,$1,$2)) -src_to = $(addprefix $3/,$(call __src_to,$1,$2)) -src_to_o = $(call src_to,.o,$1,$2) -src_to_d = $(call src_to,.d,$1,$2) -time = $(shell date +%s) -delta_t = $(eval minus, $1, $2) -debug_print_list = $(foreach word,$1,echo " $(word)";) echo - -# for building CRT library -SRC = $(call get_src_from_dir_list, $(SRC_DIRS)) -OBJ = $(call src_to_o,$(SRC),$(OBJS_DIR)) -INCLUDES += $(foreach dir, $(INCLUDE_DIRS), -I$(dir)) -DEP_FILES = $(call src_to_d, $(SRC), $(OBJS_DIR)) -STUFF_TO_CLEAN = $(OBJ) $(DEP_FILES) - -#Don't create CRT dependencies when we're cleaning, for instance -ifeq (0, $(words $(findstring $(MAKECMDGOALS), $(NODEPS)))) - -include $(DEP_FILES) -endif - -all: $(TARGET_LIB) - echo Done! - -$(TARGET_LIB): $(OBJ) | $(LIB_DIR) - $(AR) $(ARFLAGS) --create $@ $^ - echo Build CRT library done! - -$(LIB_DIR) $(OBJS_DIR): - echo Updating directory $@ - $(MKDIR) -p $@ - -#This is the rule for creating the dependency files -$(OBJS_DIR)/%.d: %.c Makefile | $(OBJS_DIR) - echo Compiling C file $< for dependency. Out file $@. - $(CC) $(DEPFLAGS) $< --depend=$@ --depend_target='$(patsubst %.d,%.o,$@)' - -$(OBJS_DIR)/%.d: %.asm | $(OBJS_DIR) - echo Compiling ASM file $< for dependency. Out file $@. - $(TOUCH) $@ - -#This rule does the compilation C files -$(OBJS_DIR)/%.o: %.c $(OBJS_DIR)/%.d - echo Compiling C file $<. Out file $@ - $(CC) $(CPPUTEST_CPPFLAGS) $< -o $@ - -#This rule does the compilation ASM -$(OBJS_DIR)/%.o: %.asm $(OBJS_DIR)/%.d - echo Assembling file $<. Out file $@ - $(AS) $(CPUFLAGS) --diag-suppress 1786 $< -o $@ - - -clean: - @$(RM) -f $(STUFF_TO_CLEAN) - diff -Nru cpputest-3.7.2/platforms_startup/armcc/AT91SAM7A3/README cpputest-3.7.2+dfsg/platforms_startup/armcc/AT91SAM7A3/README --- cpputest-3.7.2/platforms_startup/armcc/AT91SAM7A3/README 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/AT91SAM7A3/README 1970-01-01 00:00:00.000000000 +0000 @@ -1,9 +0,0 @@ -Startup library for ARM C/C++ compiler and AT91SAM7A3 chip. -Semihosting is in use, so you may use standard printf() or std::cout << "Hello!" - -Requirements: -1. CYGWIN (rm.exe, mkdir.exe, make.exe, echo.exe) -2. Keil MDK-ARM - -Library libStartup_AT91SAM7A3.a is placed in ./lib/armcc_ARM7TDMI_thumb - directory of home CppUTest directory. diff -Nru cpputest-3.7.2/platforms_startup/armcc/AT91SAM7A3/Retarget.c cpputest-3.7.2+dfsg/platforms_startup/armcc/AT91SAM7A3/Retarget.c --- cpputest-3.7.2/platforms_startup/armcc/AT91SAM7A3/Retarget.c 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/AT91SAM7A3/Retarget.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,177 +0,0 @@ -/*---------------------------------------------------------------------------- - * Name: Retarget.c - * Purpose: 'Retarget' layer for target-dependent low level functions - * Note(s): - *---------------------------------------------------------------------------- - * This file is part of the uVision/ARM development tools. - * This software may only be used under the terms of a valid, current, - * end user licence from KEIL for a compatible version of KEIL software - * development tools. Nothing else gives you the right to use this software. - * - * This software is supplied "AS IS" without warranties of any kind. - * - * Copyright (c) 2011 Keil - An ARM Company. All rights reserved. - *----------------------------------------------------------------------------*/ - -#include -#include -#include -#include "lib_AT91SAM7A3.h" - -/* Standard IO device handles. */ -#define STDIN 0x8001 -#define STDOUT 0x8002 -#define STDERR 0x8003 - - -#pragma import(__use_no_semihosting_swi) - -const char __stdin_name[] = "STDIN"; -const char __stdout_name[] = "STDOUT"; -const char __stderr_name[] = "STDERR"; - -static int init_UART_done = 0; -static void UART_putc(unsigned char); -static void UART_init(void); - - -FILEHANDLE _sys_open(const char *name, int openmode) -{ - FILEHANDLE rc; - /* Register standard Input Output devices. */ - if (strcmp(name, "STDIN") == 0) rc = STDIN; - else if (strcmp(name, "STDOUT") == 0) rc = STDOUT; - else if (strcmp(name, "STDERR") == 0) rc = STDERR; - else rc = 1; - return (rc); -} - -int _sys_close(FILEHANDLE fh) -{ - return 0; -} - -int _sys_write(FILEHANDLE fh, const unsigned char *buf, - unsigned len, int mode) -{ - while (len) { - UART_putc(*buf); - buf++; - len--; - } - return len; -} - -int _sys_read(FILEHANDLE fh, unsigned char *buf, - unsigned len, int mode) -{ - return -1; /* not supported */ -} - -void _ttywrch(int ch) -{ - UART_putc(ch); -} - -int _sys_istty(FILEHANDLE fh) -{ - return 0; /* buffered output */ -} - -int _sys_seek(FILEHANDLE fh, long pos) -{ - return -1; /* not supported */ -} - -long _sys_flen(FILEHANDLE fh) -{ - return -1; /* not supported */ -} - -void _sys_exit(int return_code) { - while(1); -} - -char *_sys_command_string(char *cmd, int len) -{ - const char * const arg[] = { - "tst.axf", - "-v", - "-gSimpleStringBuffer", - "-ojunit"}; - int i, j; - char *rc = cmd; - if (len) { - /* Specify commandline arguments here as needed */ - len = sizeof(arg) / sizeof(char *); - for (i = 0; i < len; i++) { - j = strlen(arg[i])+1; - if (cmd - rc + j > len) { - rc = NULL; - break; - } - memcpy(cmd, arg[i], j); - cmd += j; - } - if (rc) rc = cmd; - } else rc = NULL; - return rc; -} - -void _clock_init(void) -{ - AT91F_PITInit(AT91C_BASE_PITC, 1000, 50); /* Period = 1000 Hz, CLK = 50 MHz */ -} - -clock_t clock(void) -{ - static clock_t rc = 0; - rc += AT91F_PITGetPIVR(AT91C_BASE_PITC) >> 20; - return rc; -} - -time_t time(time_t *timer) -{ - return 0; -} - - -static void UART_putc(unsigned char ch) -{ - if (init_UART_done == 0) { - UART_init(); - init_UART_done++; - } - while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXRDY) == 0) __nop(); - AT91C_BASE_DBGU->DBGU_THR = ch; -} - -static void UART_init(void) -{ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS; - AT91C_BASE_PIOA->PIO_PDR = (1<<30) | (1UL<<31); - AT91C_BASE_PIOA->PIO_ASR = (1<<30) | (1UL<<31); - AT91C_BASE_DBGU->DBGU_IDR = ~0; - AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS | AT91C_US_RSTSTA; - AT91C_BASE_DBGU->DBGU_BRGR = 27; /* 115200 if MCLK = 50 МГц */ - AT91C_BASE_DBGU->DBGU_MR = AT91C_US_PAR_NONE | AT91C_US_CHMODE_NORMAL; - AT91C_BASE_DBGU->DBGU_CR = AT91C_US_TXEN; - AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN; - AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTSTA; /* Reset status IRQ */ -} - -/* Replace of default Keil MDK-ARM function to create linked list of - * destructor addresses of global or statically created objects. List is - * placed in heap at startup. - * No exit() is planned to call (exit from main() never take place in - * embedded applications). So, it is no need to that list and it is possible - * to use less heap memory. - * New version of __aeabi_atexit does not create that list. See also - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka3951.html - * http://infocenter.arm.com/help/topic/com.arm.doc.ihi0041d/IHI0041D_cppabi.pdf - */ -int __aeabi_atexit(void* object, void (*destroyer)(void*), void* dso_handle) -{ - return 1; // 0: failed; non-0: OK -// return __cxa_atexit(destroyer, object, dso_handle); /* Keil MDK-ARM version */ -} diff -Nru cpputest-3.7.2/platforms_startup/armcc/AT91SAM7A3/SAM7A3.asm cpputest-3.7.2+dfsg/platforms_startup/armcc/AT91SAM7A3/SAM7A3.asm --- cpputest-3.7.2/platforms_startup/armcc/AT91SAM7A3/SAM7A3.asm 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/AT91SAM7A3/SAM7A3.asm 1970-01-01 00:00:00.000000000 +0000 @@ -1,434 +0,0 @@ -;/*****************************************************************************/ -;/* SAM7.S: Startup file for Atmel AT91SAM7 device series */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - - -;/* -; * The SAM7.S code is executed after CPU Reset. This file may be -; * translated with the following SET symbols. In uVision these SET -; * symbols are entered under Options - ASM - Define. -; * -; * REMAP: when set the startup code remaps exception vectors from -; * on-chip RAM to address 0. -; * -; * RAM_INTVEC: when set the startup code copies exception vectors -; * from on-chip Flash to on-chip RAM. -; */ - - -; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -; Internal Memory Base Addresses -FLASH_BASE EQU 0x00100000 -RAM_BASE EQU 0x00200000 - - -;// Stack Configuration (Stack Sizes in Bytes) -;// Undefined Mode <0x0-0xFFFFFFFF:8> -;// Supervisor Mode <0x0-0xFFFFFFFF:8> -;// Abort Mode <0x0-0xFFFFFFFF:8> -;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8> -;// Interrupt Mode <0x0-0xFFFFFFFF:8> -;// User/System Mode <0x0-0xFFFFFFFF:8> -;// - -UND_Stack_Size EQU 0x00000000 -SVC_Stack_Size EQU 0x00001000 -ABT_Stack_Size EQU 0x00000000 -FIQ_Stack_Size EQU 0x00000000 -IRQ_Stack_Size EQU 0x00000070 -USR_Stack_Size EQU 0x00000000 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size - -Stack_Top - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF> -;// - -Heap_Size EQU 0x0002800 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - -; Reset Controller (RSTC) definitions -RSTC_BASE EQU 0xFFFFFD00 ; RSTC Base Address -RSTC_MR EQU 0x08 ; RSTC_MR Offset - -;/* -;// Reset Controller (RSTC) -;// URSTEN: User Reset Enable -;// Enables NRST Pin to generate Reset -;// ERSTL: External Reset Length <0-15> -;// External Reset Time in 2^(ERSTL+1) Slow Clock Cycles -;// -;*/ -RSTC_SETUP EQU 1 -RSTC_MR_Val EQU 0xA5000401 - - -; Embedded Flash Controller (EFC) definitions -EFC_BASE EQU 0xFFFFFF00 ; EFC Base Address -EFC0_FMR EQU 0x60 ; EFC0_FMR Offset -EFC1_FMR EQU 0x70 ; EFC1_FMR Offset - -;// Embedded Flash Controller 0 (EFC0) -;// FMCN: Flash Microsecond Cycle Number <0-255> -;// Number of Master Clock Cycles in 1us -;// FWS: Flash Wait State -;// <0=> Read: 1 cycle / Write: 2 cycles -;// <1=> Read: 2 cycle / Write: 3 cycles -;// <2=> Read: 3 cycle / Write: 4 cycles -;// <3=> Read: 4 cycle / Write: 4 cycles -;// -EFC0_SETUP EQU 1 -EFC0_FMR_Val EQU 0x004B0100 - -;// Embedded Flash Controller 1 (EFC1) -;// FMCN: Flash Microsecond Cycle Number <0-255> -;// Number of Master Clock Cycles in 1us -;// FWS: Flash Wait State -;// <0=> Read: 1 cycle / Write: 2 cycles -;// <1=> Read: 2 cycle / Write: 3 cycles -;// <2=> Read: 3 cycle / Write: 4 cycles -;// <3=> Read: 4 cycle / Write: 4 cycles -;// -EFC1_SETUP EQU 0 -EFC1_FMR_Val EQU 0x00320100 - - -; Watchdog Timer (WDT) definitions -WDT_BASE EQU 0xFFFFFD40 ; WDT Base Address -WDT_MR EQU 0x04 ; WDT_MR Offset - -;// Watchdog Timer (WDT) -;// WDV: Watchdog Counter Value <0-4095> -;// WDD: Watchdog Delta Value <0-4095> -;// WDFIEN: Watchdog Fault Interrupt Enable -;// WDRSTEN: Watchdog Reset Enable -;// WDRPROC: Watchdog Reset Processor -;// WDDBGHLT: Watchdog Debug Halt -;// WDIDLEHLT: Watchdog Idle Halt -;// WDDIS: Watchdog Disable -;// -WDT_SETUP EQU 1 -WDT_MR_Val EQU 0x00008000 - - -; Power Mangement Controller (PMC) definitions -PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address -PMC_MOR EQU 0x20 ; PMC_MOR Offset -PMC_MCFR EQU 0x24 ; PMC_MCFR Offset -PMC_PLLR EQU 0x2C ; PMC_PLLR Offset -PMC_MCKR EQU 0x30 ; PMC_MCKR Offset -PMC_SR EQU 0x68 ; PMC_SR Offset -PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable -PMC_OSCBYPASS EQU (1<<1) ; Main Oscillator Bypass -PMC_OSCOUNT EQU (0xFF<<8) ; Main OScillator Start-up Time -PMC_DIV EQU (0xFF<<0) ; PLL Divider -PMC_PLLCOUNT EQU (0x3F<<8) ; PLL Lock Counter -PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range -PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier -PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider -PMC_CSS EQU (3<<0) ; Clock Source Selection -PMC_PRES EQU (7<<2) ; Prescaler Selection -PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable -PMC_LOCK EQU (1<<2) ; PLL Lock Status -PMC_MCKRDY EQU (1<<3) ; Master Clock Status - -;// Power Mangement Controller (PMC) -;// Main Oscillator -;// MOSCEN: Main Oscillator Enable -;// OSCBYPASS: Oscillator Bypass -;// OSCCOUNT: Main Oscillator Startup Time <0-255> -;// -;// Phase Locked Loop (PLL) -;// DIV: PLL Divider <0-255> -;// MUL: PLL Multiplier <0-2047> -;// PLL Output is multiplied by MUL+1 -;// OUT: PLL Clock Frequency Range -;// <0=> 80..160MHz <1=> Reserved -;// <2=> 150..220MHz <3=> Reserved -;// PLLCOUNT: PLL Lock Counter <0-63> -;// USBDIV: USB Clock Divider -;// <0=> None <1=> 2 <2=> 4 <3=> Reserved -;// -;// CSS: Clock Source Selection -;// <0=> Slow Clock -;// <1=> Main Clock -;// <2=> Reserved -;// <3=> PLL Clock -;// PRES: Prescaler -;// <0=> None -;// <1=> Clock / 2 <2=> Clock / 4 -;// <3=> Clock / 8 <4=> Clock / 16 -;// <5=> Clock / 32 <6=> Clock / 64 -;// <7=> Reserved -;// -PMC_SETUP EQU 1 -PMC_MOR_Val EQU 0x00000601 -PMC_PLLR_Val EQU 0x00C71E04 -PMC_MCKR_Val EQU 0x0000000B - - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address at which it expects to run. - - AREA |.reset|, CODE, READONLY - ARM - - -; Exception Vectors -; Mapped to Address 0. -; Absolute addressing mode must be used. -; Dummy Handlers are implemented as infinite loops which can be modified. - -Vectors LDR PC,Reset_Addr - LDR PC,Undef_Addr - LDR PC,SWI_Addr - LDR PC,PAbt_Addr - LDR PC,DAbt_Addr - NOP ; Reserved Vector -; LDR PC,IRQ_Addr - LDR PC,[PC,#-0xF20] ; Vector From AIC_IVR -; LDR PC,FIQ_Addr - LDR PC,[PC,#-0xF20] ; Vector From AIC_FVR - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SWI_Addr DCD SWI_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler - DCD 0 ; Reserved Address -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - -Undef_Handler B Undef_Handler -SWI_Handler B SWI_Handler ; Part of RTL -PAbt_Handler B PAbt_Handler -DAbt_Handler B DAbt_Handler -IRQ_Handler B IRQ_Handler -FIQ_Handler B FIQ_Handler - - -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - - -; Setup RSTC - IF RSTC_SETUP != 0 - LDR R0, =RSTC_BASE - LDR R1, =RSTC_MR_Val - STR R1, [R0, #RSTC_MR] - ENDIF - - -; Setup EFC0 - IF EFC0_SETUP != 0 - LDR R0, =EFC_BASE - LDR R1, =EFC0_FMR_Val - STR R1, [R0, #EFC0_FMR] - ENDIF - -; Setup EFC1 - IF EFC1_SETUP != 0 - LDR R0, =EFC_BASE - LDR R1, =EFC1_FMR_Val - STR R1, [R0, #EFC1_FMR] - ENDIF - - -; Setup WDT - IF WDT_SETUP != 0 - LDR R0, =WDT_BASE - LDR R1, =WDT_MR_Val - STR R1, [R0, #WDT_MR] - ENDIF - - -; Setup PMC - IF PMC_SETUP != 0 - LDR R0, =PMC_BASE - -; Setup Main Oscillator - LDR R1, =PMC_MOR_Val - STR R1, [R0, #PMC_MOR] - -; Wait until Main Oscillator is stablilized - IF (PMC_MOR_Val:AND:PMC_MOSCEN) != 0 -MOSCS_Loop LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MOSCS - BEQ MOSCS_Loop - ENDIF - -; Setup the PLL - IF (PMC_PLLR_Val:AND:PMC_MUL) != 0 - LDR R1, =PMC_PLLR_Val - STR R1, [R0, #PMC_PLLR] - -; Wait until PLL is stabilized -PLL_Loop LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_LOCK - BEQ PLL_Loop - ENDIF - -; Select Clock - IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected - LDR R1, =PMC_MCKR_Val - AND R1, #PMC_CSS - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy1 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy1 - LDR R1, =PMC_MCKR_Val - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy2 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy2 - ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected - LDR R1, =PMC_MCKR_Val - AND R1, #PMC_PRES - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy1 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy1 - LDR R1, =PMC_MCKR_Val - STR R1, [R0, #PMC_MCKR] -WAIT_Rdy2 LDR R2, [R0, #PMC_SR] - ANDS R2, R2, #PMC_MCKRDY - BEQ WAIT_Rdy2 - ENDIF ; Select Clock - ENDIF ; PMC_SETUP - - -; Copy Exception Vectors to Internal RAM - - IF :DEF:RAM_INTVEC - ADR R8, Vectors ; Source - LDR R9, =RAM_BASE ; Destination - LDMIA R8!, {R0-R7} ; Load Vectors - STMIA R9!, {R0-R7} ; Store Vectors - LDMIA R8!, {R0-R7} ; Load Handler Addresses - STMIA R9!, {R0-R7} ; Store Handler Addresses - ENDIF - - -; Remap on-chip RAM to address 0 - -MC_BASE EQU 0xFFFFFF00 ; MC Base Address -MC_RCR EQU 0x00 ; MC_RCR Offset - - IF :DEF:REMAP - LDR R0, =MC_BASE - MOV R1, #1 - STR R1, [R0, #MC_RCR] ; Remap - ENDIF - - -; Setup Stack for each mode - - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #SVC_Stack_Size - -; Enter User Mode and set its Stack Pointer -; MSR CPSR_c, #Mode_USR -; IF :DEF:__MICROLIB - -; EXPORT __initial_sp - -; ELSE - -; MOV SP, R0 -; SUB SL, SP, #USR_Stack_Size - -; ENDIF - - -; Enter the C code - - IMPORT __main - LDR R0, =__main - BX R0 - - - IF :DEF:__MICROLIB - - EXPORT __heap_base - EXPORT __heap_limit - - ELSE -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_setup_stackheap -__user_setup_stackheap - - LDR R0, = Heap_Mem - LDR R2, = (Heap_Mem + Heap_Size) - LDR SP, =(Stack_Mem + SVC_Stack_Size) - BX LR - ENDIF - - - END diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/core_cm3.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/core_cm3.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/core_cm3.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/core_cm3.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1227 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - - -/** \ingroup CMSIS_Core - \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup CMSIS_Core - \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks */ -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \ingroup CMSIS_Core - \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB - Type definitions for the Cortex-M System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \ingroup CMSIS_Core - \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/core_cmFunc.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/core_cmFunc.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/core_cmFunc.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/core_cmFunc.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,609 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V2.10 - * @date 26. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -static __INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -static __INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -static __INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/core_cmInstr.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/core_cmInstr.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/core_cmInstr.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/core_cmInstr.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,586 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \ingroup CMSIS_Core - \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_clkpwr.c cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_clkpwr.c --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_clkpwr.c 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_clkpwr.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,350 +0,0 @@ -/********************************************************************** -* $Id$ lpc17xx_clkpwr.c 2010-06-18 -*//** -* @file lpc17xx_clkpwr.c -* @brief Contains all functions support for Clock and Power Control -* firmware library on LPC17xx -* @version 3.0 -* @date 18. June. 2010 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2010, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup CLKPWR - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc17xx_clkpwr.h" - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup CLKPWR_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Set value of each Peripheral Clock Selection - * @param[in] ClkType Peripheral Clock Selection of each type, - * should be one of the following: - * - CLKPWR_PCLKSEL_WDT : WDT - - CLKPWR_PCLKSEL_TIMER0 : Timer 0 - - CLKPWR_PCLKSEL_TIMER1 : Timer 1 - - CLKPWR_PCLKSEL_UART0 : UART 0 - - CLKPWR_PCLKSEL_UART1 : UART 1 - - CLKPWR_PCLKSEL_PWM1 : PWM 1 - - CLKPWR_PCLKSEL_I2C0 : I2C 0 - - CLKPWR_PCLKSEL_SPI : SPI - - CLKPWR_PCLKSEL_SSP1 : SSP 1 - - CLKPWR_PCLKSEL_DAC : DAC - - CLKPWR_PCLKSEL_ADC : ADC - - CLKPWR_PCLKSEL_CAN1 : CAN 1 - - CLKPWR_PCLKSEL_CAN2 : CAN 2 - - CLKPWR_PCLKSEL_ACF : ACF - - CLKPWR_PCLKSEL_QEI : QEI - - CLKPWR_PCLKSEL_PCB : PCB - - CLKPWR_PCLKSEL_I2C1 : I2C 1 - - CLKPWR_PCLKSEL_SSP0 : SSP 0 - - CLKPWR_PCLKSEL_TIMER2 : Timer 2 - - CLKPWR_PCLKSEL_TIMER3 : Timer 3 - - CLKPWR_PCLKSEL_UART2 : UART 2 - - CLKPWR_PCLKSEL_UART3 : UART 3 - - CLKPWR_PCLKSEL_I2C2 : I2C 2 - - CLKPWR_PCLKSEL_I2S : I2S - - CLKPWR_PCLKSEL_RIT : RIT - - CLKPWR_PCLKSEL_SYSCON : SYSCON - - CLKPWR_PCLKSEL_MC : MC - - * @param[in] DivVal Value of divider, should be: - * - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4 - * - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1 - * - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2 - * - * @return none - **********************************************************************/ -void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal) -{ - uint32_t bitpos; - - bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32); - - /* PCLKSEL0 selected */ - if (ClkType < 32) - { - /* Clear two bit at bit position */ - LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos))); - - /* Set two selected bit */ - LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal)); - } - /* PCLKSEL1 selected */ - else - { - /* Clear two bit at bit position */ - LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos)); - - /* Set two selected bit */ - LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal)); - } -} - - -/*********************************************************************//** - * @brief Get current value of each Peripheral Clock Selection - * @param[in] ClkType Peripheral Clock Selection of each type, - * should be one of the following: - * - CLKPWR_PCLKSEL_WDT : WDT - - CLKPWR_PCLKSEL_TIMER0 : Timer 0 - - CLKPWR_PCLKSEL_TIMER1 : Timer 1 - - CLKPWR_PCLKSEL_UART0 : UART 0 - - CLKPWR_PCLKSEL_UART1 : UART 1 - - CLKPWR_PCLKSEL_PWM1 : PWM 1 - - CLKPWR_PCLKSEL_I2C0 : I2C 0 - - CLKPWR_PCLKSEL_SPI : SPI - - CLKPWR_PCLKSEL_SSP1 : SSP 1 - - CLKPWR_PCLKSEL_DAC : DAC - - CLKPWR_PCLKSEL_ADC : ADC - - CLKPWR_PCLKSEL_CAN1 : CAN 1 - - CLKPWR_PCLKSEL_CAN2 : CAN 2 - - CLKPWR_PCLKSEL_ACF : ACF - - CLKPWR_PCLKSEL_QEI : QEI - - CLKPWR_PCLKSEL_PCB : PCB - - CLKPWR_PCLKSEL_I2C1 : I2C 1 - - CLKPWR_PCLKSEL_SSP0 : SSP 0 - - CLKPWR_PCLKSEL_TIMER2 : Timer 2 - - CLKPWR_PCLKSEL_TIMER3 : Timer 3 - - CLKPWR_PCLKSEL_UART2 : UART 2 - - CLKPWR_PCLKSEL_UART3 : UART 3 - - CLKPWR_PCLKSEL_I2C2 : I2C 2 - - CLKPWR_PCLKSEL_I2S : I2S - - CLKPWR_PCLKSEL_RIT : RIT - - CLKPWR_PCLKSEL_SYSCON : SYSCON - - CLKPWR_PCLKSEL_MC : MC - - * @return Value of Selected Peripheral Clock Selection - **********************************************************************/ -uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType) -{ - uint32_t bitpos, retval; - - if (ClkType < 32) - { - bitpos = ClkType; - retval = LPC_SC->PCLKSEL0; - } - else - { - bitpos = ClkType - 32; - retval = LPC_SC->PCLKSEL1; - } - - retval = CLKPWR_PCLKSEL_GET(bitpos, retval); - return retval; -} - - - -/*********************************************************************//** - * @brief Get current value of each Peripheral Clock - * @param[in] ClkType Peripheral Clock Selection of each type, - * should be one of the following: - * - CLKPWR_PCLKSEL_WDT : WDT - - CLKPWR_PCLKSEL_TIMER0 : Timer 0 - - CLKPWR_PCLKSEL_TIMER1 : Timer 1 - - CLKPWR_PCLKSEL_UART0 : UART 0 - - CLKPWR_PCLKSEL_UART1 : UART 1 - - CLKPWR_PCLKSEL_PWM1 : PWM 1 - - CLKPWR_PCLKSEL_I2C0 : I2C 0 - - CLKPWR_PCLKSEL_SPI : SPI - - CLKPWR_PCLKSEL_SSP1 : SSP 1 - - CLKPWR_PCLKSEL_DAC : DAC - - CLKPWR_PCLKSEL_ADC : ADC - - CLKPWR_PCLKSEL_CAN1 : CAN 1 - - CLKPWR_PCLKSEL_CAN2 : CAN 2 - - CLKPWR_PCLKSEL_ACF : ACF - - CLKPWR_PCLKSEL_QEI : QEI - - CLKPWR_PCLKSEL_PCB : PCB - - CLKPWR_PCLKSEL_I2C1 : I2C 1 - - CLKPWR_PCLKSEL_SSP0 : SSP 0 - - CLKPWR_PCLKSEL_TIMER2 : Timer 2 - - CLKPWR_PCLKSEL_TIMER3 : Timer 3 - - CLKPWR_PCLKSEL_UART2 : UART 2 - - CLKPWR_PCLKSEL_UART3 : UART 3 - - CLKPWR_PCLKSEL_I2C2 : I2C 2 - - CLKPWR_PCLKSEL_I2S : I2S - - CLKPWR_PCLKSEL_RIT : RIT - - CLKPWR_PCLKSEL_SYSCON : SYSCON - - CLKPWR_PCLKSEL_MC : MC - - * @return Value of Selected Peripheral Clock - **********************************************************************/ -uint32_t CLKPWR_GetPCLK (uint32_t ClkType) -{ - uint32_t retval, div; - - retval = SystemCoreClock; - div = CLKPWR_GetPCLKSEL(ClkType); - - switch (div) - { - case 0: - div = 4; - break; - - case 1: - div = 1; - break; - - case 2: - div = 2; - break; - - case 3: - div = 8; - break; - } - retval /= div; - - return retval; -} - - - -/*********************************************************************//** - * @brief Configure power supply for each peripheral according to NewState - * @param[in] PPType Type of peripheral used to enable power, - * should be one of the following: - * - CLKPWR_PCONP_PCTIM0 : Timer 0 - - CLKPWR_PCONP_PCTIM1 : Timer 1 - - CLKPWR_PCONP_PCUART0 : UART 0 - - CLKPWR_PCONP_PCUART1 : UART 1 - - CLKPWR_PCONP_PCPWM1 : PWM 1 - - CLKPWR_PCONP_PCI2C0 : I2C 0 - - CLKPWR_PCONP_PCSPI : SPI - - CLKPWR_PCONP_PCRTC : RTC - - CLKPWR_PCONP_PCSSP1 : SSP 1 - - CLKPWR_PCONP_PCAD : ADC - - CLKPWR_PCONP_PCAN1 : CAN 1 - - CLKPWR_PCONP_PCAN2 : CAN 2 - - CLKPWR_PCONP_PCGPIO : GPIO - - CLKPWR_PCONP_PCRIT : RIT - - CLKPWR_PCONP_PCMC : MC - - CLKPWR_PCONP_PCQEI : QEI - - CLKPWR_PCONP_PCI2C1 : I2C 1 - - CLKPWR_PCONP_PCSSP0 : SSP 0 - - CLKPWR_PCONP_PCTIM2 : Timer 2 - - CLKPWR_PCONP_PCTIM3 : Timer 3 - - CLKPWR_PCONP_PCUART2 : UART 2 - - CLKPWR_PCONP_PCUART3 : UART 3 - - CLKPWR_PCONP_PCI2C2 : I2C 2 - - CLKPWR_PCONP_PCI2S : I2S - - CLKPWR_PCONP_PCGPDMA : GPDMA - - CLKPWR_PCONP_PCENET : Ethernet - - CLKPWR_PCONP_PCUSB : USB - * - * @param[in] NewState New state of Peripheral Power, should be: - * - ENABLE : Enable power for this peripheral - * - DISABLE : Disable power for this peripheral - * - * @return none - **********************************************************************/ -void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK; - } - else if (NewState == DISABLE) - { - LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK; - } -} - - -/*********************************************************************//** - * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None - **********************************************************************/ -void CLKPWR_Sleep(void) -{ - LPC_SC->PCON = 0x00; - /* Sleep Mode*/ - __WFI(); -} - - -/*********************************************************************//** - * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None - **********************************************************************/ -void CLKPWR_DeepSleep(void) -{ - /* Deep-Sleep Mode, set SLEEPDEEP bit */ - SCB->SCR = 0x4; - LPC_SC->PCON = 0x00; - /* Deep Sleep Mode*/ - __WFI(); -} - - -/*********************************************************************//** - * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None - **********************************************************************/ -void CLKPWR_PowerDown(void) -{ - /* Deep-Sleep Mode, set SLEEPDEEP bit */ - SCB->SCR = 0x4; - LPC_SC->PCON = 0x01; - /* Power Down Mode*/ - __WFI(); -} - - -/*********************************************************************//** - * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None - **********************************************************************/ -void CLKPWR_DeepPowerDown(void) -{ - /* Deep-Sleep Mode, set SLEEPDEEP bit */ - SCB->SCR = 0x4; - LPC_SC->PCON = 0x03; - /* Deep Power Down Mode*/ - __WFI(); -} - -/** - * @} - */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_clkpwr.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_clkpwr.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_clkpwr.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_clkpwr.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,406 +0,0 @@ -/********************************************************************** -* $Id$ lpc17xx_clkpwr.h 2010-05-21 -*//** -* @file lpc17xx_clkpwr.h -* @brief Contains all macro definitions and function prototypes -* support for Clock and Power Control firmware library on LPC17xx -* @version 2.0 -* @date 21. May. 2010 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2010, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup CLKPWR CLKPWR (Clock Power) - * @ingroup LPC1700CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef LPC17XX_CLKPWR_H_ -#define LPC17XX_CLKPWR_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC17xx.h" -#include "lpc_types.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros - * @{ - */ - -/********************************************************************** - * Peripheral Clock Selection Definitions - **********************************************************************/ -/** Peripheral clock divider bit position for WDT */ -#define CLKPWR_PCLKSEL_WDT ((uint32_t)(0)) -/** Peripheral clock divider bit position for TIMER0 */ -#define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2)) -/** Peripheral clock divider bit position for TIMER1 */ -#define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4)) -/** Peripheral clock divider bit position for UART0 */ -#define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6)) -/** Peripheral clock divider bit position for UART1 */ -#define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8)) -/** Peripheral clock divider bit position for PWM1 */ -#define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12)) -/** Peripheral clock divider bit position for I2C0 */ -#define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14)) -/** Peripheral clock divider bit position for SPI */ -#define CLKPWR_PCLKSEL_SPI ((uint32_t)(16)) -/** Peripheral clock divider bit position for SSP1 */ -#define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20)) -/** Peripheral clock divider bit position for DAC */ -#define CLKPWR_PCLKSEL_DAC ((uint32_t)(22)) -/** Peripheral clock divider bit position for ADC */ -#define CLKPWR_PCLKSEL_ADC ((uint32_t)(24)) -/** Peripheral clock divider bit position for CAN1 */ -#define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26)) -/** Peripheral clock divider bit position for CAN2 */ -#define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28)) -/** Peripheral clock divider bit position for ACF */ -#define CLKPWR_PCLKSEL_ACF ((uint32_t)(30)) -/** Peripheral clock divider bit position for QEI */ -#define CLKPWR_PCLKSEL_QEI ((uint32_t)(32)) -/** Peripheral clock divider bit position for PCB */ -#define CLKPWR_PCLKSEL_PCB ((uint32_t)(36)) -/** Peripheral clock divider bit position for I2C1 */ -#define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38)) -/** Peripheral clock divider bit position for SSP0 */ -#define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42)) -/** Peripheral clock divider bit position for TIMER2 */ -#define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44)) -/** Peripheral clock divider bit position for TIMER3 */ -#define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46)) -/** Peripheral clock divider bit position for UART2 */ -#define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48)) -/** Peripheral clock divider bit position for UART3 */ -#define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50)) -/** Peripheral clock divider bit position for I2C2 */ -#define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52)) -/** Peripheral clock divider bit position for I2S */ -#define CLKPWR_PCLKSEL_I2S ((uint32_t)(54)) -/** Peripheral clock divider bit position for RIT */ -#define CLKPWR_PCLKSEL_RIT ((uint32_t)(58)) -/** Peripheral clock divider bit position for SYSCON */ -#define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60)) -/** Peripheral clock divider bit position for MC */ -#define CLKPWR_PCLKSEL_MC ((uint32_t)(62)) - -/** Macro for Peripheral Clock Selection register bit values - * Note: When CCLK_DIV_8, Peripherals clock is selected to - * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering - * when 11selects PCLK_xyz = CCLK/6 */ -/* Peripheral clock divider is set to 4 from CCLK */ -#define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0)) -/** Peripheral clock divider is the same with CCLK */ -#define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1)) -/** Peripheral clock divider is set to 2 from CCLK */ -#define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2)) - - -/******************************************************************** -* Power Control for Peripherals Definitions -**********************************************************************/ -/** Timer/Counter 0 power/clock control bit */ -#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1)) -/* Timer/Counter 1 power/clock control bit */ -#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2)) -/** UART0 power/clock control bit */ -#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3)) -/** UART1 power/clock control bit */ -#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4)) -/** PWM1 power/clock control bit */ -#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6)) -/** The I2C0 interface power/clock control bit */ -#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7)) -/** The SPI interface power/clock control bit */ -#define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8)) -/** The RTC power/clock control bit */ -#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9)) -/** The SSP1 interface power/clock control bit */ -#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10)) -/** A/D converter 0 (ADC0) power/clock control bit */ -#define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12)) -/** CAN Controller 1 power/clock control bit */ -#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13)) -/** CAN Controller 2 power/clock control bit */ -#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14)) -/** GPIO power/clock control bit */ -#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15)) -/** Repetitive Interrupt Timer power/clock control bit */ -#define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16)) -/** Motor Control PWM */ -#define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17)) -/** Quadrature Encoder Interface power/clock control bit */ -#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18)) -/** The I2C1 interface power/clock control bit */ -#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19)) -/** The SSP0 interface power/clock control bit */ -#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21)) -/** Timer 2 power/clock control bit */ -#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22)) -/** Timer 3 power/clock control bit */ -#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23)) -/** UART 2 power/clock control bit */ -#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24)) -/** UART 3 power/clock control bit */ -#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25)) -/** I2C interface 2 power/clock control bit */ -#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26)) -/** I2S interface power/clock control bit*/ -#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27)) -/** GP DMA function power/clock control bit*/ -#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29)) -/** Ethernet block power/clock control bit*/ -#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30)) -/** USB interface power/clock control bit*/ -#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31)) - - -/** - * @} - */ -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros - * @{ - */ - -/* --------------------- BIT DEFINITIONS -------------------------------------- */ -/*********************************************************************//** - * Macro defines for Clock Source Select Register - **********************************************************************/ -/** Internal RC oscillator */ -#define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00)) -/** Main oscillator */ -#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01)) -/** RTC oscillator */ -#define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02)) -/** Clock source selection bit mask */ -#define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03)) - -/*********************************************************************//** - * Macro defines for Clock Output Configuration Register - **********************************************************************/ -/* Clock Output Configuration register definition */ -/** Selects the CPU clock as the CLKOUT source */ -#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00)) -/** Selects the main oscillator as the CLKOUT source */ -#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01)) -/** Selects the Internal RC oscillator as the CLKOUT source */ -#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02)) -/** Selects the USB clock as the CLKOUT source */ -#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03)) -/** Selects the RTC oscillator as the CLKOUT source */ -#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04)) -/** Integer value to divide the output clock by, minus one */ -#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4)) -/** CLKOUT enable control */ -#define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8)) -/** CLKOUT activity indication */ -#define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9)) -/** Clock source selection bit mask */ -#define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF)) - -/*********************************************************************//** - * Macro defines for PPL0 Control Register - **********************************************************************/ -/** PLL 0 control enable */ -#define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01)) -/** PLL 0 control connect */ -#define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02)) -/** PLL 0 control bit mask */ -#define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03)) - -/*********************************************************************//** - * Macro defines for PPL0 Configuration Register - **********************************************************************/ -/** PLL 0 Configuration MSEL field */ -#define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF)) -/** PLL 0 Configuration NSEL field */ -#define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000)) -/** PLL 0 Configuration bit mask */ -#define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF)) - - -/*********************************************************************//** - * Macro defines for PPL0 Status Register - **********************************************************************/ -/** PLL 0 MSEL value */ -#define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF)) -/** PLL NSEL get value */ -#define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF)) -/** PLL status enable bit */ -#define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24)) -/** PLL status Connect bit */ -#define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25)) -/** PLL status lock */ -#define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26)) - -/*********************************************************************//** - * Macro defines for PPL0 Feed Register - **********************************************************************/ -/** PLL0 Feed bit mask */ -#define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF) - -/*********************************************************************//** - * Macro defines for PLL1 Control Register - **********************************************************************/ -/** USB PLL control enable */ -#define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01)) -/** USB PLL control connect */ -#define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02)) -/** USB PLL control bit mask */ -#define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03)) - -/*********************************************************************//** - * Macro defines for PLL1 Configuration Register - **********************************************************************/ -/** USB PLL MSEL set value */ -#define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F)) -/** USB PLL PSEL set value */ -#define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5)) -/** USB PLL configuration bit mask */ -#define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F)) - -/*********************************************************************//** - * Macro defines for PLL1 Status Register - **********************************************************************/ -/** USB PLL MSEL get value */ -#define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F)) -/** USB PLL PSEL get value */ -#define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03)) -/** USB PLL status enable bit */ -#define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8)) -/** USB PLL status Connect bit */ -#define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9)) -/** USB PLL status lock */ -#define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10)) - -/*********************************************************************//** - * Macro defines for PLL1 Feed Register - **********************************************************************/ -/** PLL1 Feed bit mask */ -#define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF) - -/*********************************************************************//** - * Macro defines for CPU Clock Configuration Register - **********************************************************************/ -/** CPU Clock configuration bit mask */ -#define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF)) - -/*********************************************************************//** - * Macro defines for USB Clock Configuration Register - **********************************************************************/ -/** USB Clock Configuration bit mask */ -#define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F)) - -/*********************************************************************//** - * Macro defines for IRC Trim Register - **********************************************************************/ -/** IRC Trim bit mask */ -#define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F)) - -/*********************************************************************//** - * Macro defines for Peripheral Clock Selection Register 0 and 1 - **********************************************************************/ -/** Peripheral Clock Selection 0 mask bit */ -#define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF)) -/** Peripheral Clock Selection 1 mask bit */ -#define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3)) -/** Macro to set peripheral clock of each type - * p: position of two bits that hold divider of peripheral clock - * n: value of divider of peripheral clock to be set */ -#define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n) -/** Macro to mask peripheral clock of each type */ -#define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03) -/** Macro to get peripheral clock of each type */ -#define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03)) - -/*********************************************************************//** - * Macro defines for Power Mode Control Register - **********************************************************************/ -/** Power mode control bit 0 */ -#define CLKPWR_PCON_PM0 ((uint32_t)(1<<0)) -/** Power mode control bit 1 */ -#define CLKPWR_PCON_PM1 ((uint32_t)(1<<1)) -/** Brown-Out Reduced Power Mode */ -#define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2)) -/** Brown-Out Global Disable */ -#define CLKPWR_PCON_BOGD ((uint32_t)(1<<3)) -/** Brown Out Reset Disable */ -#define CLKPWR_PCON_BORD ((uint32_t)(1<<4)) -/** Sleep Mode entry flag */ -#define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8)) -/** Deep Sleep entry flag */ -#define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9)) -/** Power-down entry flag */ -#define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10)) -/** Deep Power-down entry flag */ -#define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11)) - -/*********************************************************************//** - * Macro defines for Power Control for Peripheral Register - **********************************************************************/ -/** Power Control for Peripherals bit mask */ -#define CLKPWR_PCONP_BITMASK 0xEFEFF7DE - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions - * @{ - */ - -void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal); -uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType); -uint32_t CLKPWR_GetPCLK (uint32_t ClkType); -void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState); -void CLKPWR_Sleep(void); -void CLKPWR_DeepSleep(void); -void CLKPWR_PowerDown(void); -void CLKPWR_DeepPowerDown(void); - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* LPC17XX_CLKPWR_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/LPC17xx.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/LPC17xx.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/LPC17xx.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/LPC17xx.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1083 +0,0 @@ -/**************************************************************************//** - * @file LPC17xx.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for - * NXP LPC17xx Device Series - * @version: V1.09 - * @date: 25. July. 2011 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __LPC17xx_H__ -#define __LPC17xx_H__ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -/** @addtogroup LPC17xx_System - * @{ - */ - -/** @brief IRQ interrupt source definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** LPC17xx Specific Interrupt Numbers *******************************************************/ - WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ - TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ - TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ - TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ - TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ - UART0_IRQn = 5, /*!< UART0 Interrupt */ - UART1_IRQn = 6, /*!< UART1 Interrupt */ - UART2_IRQn = 7, /*!< UART2 Interrupt */ - UART3_IRQn = 8, /*!< UART3 Interrupt */ - PWM1_IRQn = 9, /*!< PWM1 Interrupt */ - I2C0_IRQn = 10, /*!< I2C0 Interrupt */ - I2C1_IRQn = 11, /*!< I2C1 Interrupt */ - I2C2_IRQn = 12, /*!< I2C2 Interrupt */ - SPI_IRQn = 13, /*!< SPI Interrupt */ - SSP0_IRQn = 14, /*!< SSP0 Interrupt */ - SSP1_IRQn = 15, /*!< SSP1 Interrupt */ - PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ - RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ - EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ - EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ - EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ - EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ - ADC_IRQn = 22, /*!< A/D Converter Interrupt */ - BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ - USB_IRQn = 24, /*!< USB Interrupt */ - CAN_IRQn = 25, /*!< CAN Interrupt */ - DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ - I2S_IRQn = 27, /*!< I2S Interrupt */ - ENET_IRQn = 28, /*!< Ethernet Interrupt */ - RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ - MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ - QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ - PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ - USBActivity_IRQn = 33, /*!< USB Activity Interrupt */ - CANActivity_IRQn = 34 /*!< CAN Activity Interrupt */ -} IRQn_Type; - - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include "system_LPC17xx.h" /* System Header */ -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ - - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#elif defined ( __ICCARM__ ) -#pragma language=save -#pragma language=extended -#endif - -/*------------- System Control (SC) ------------------------------------------*/ -/** @brief System Control (SC) register structure definition */ -typedef struct -{ - __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ - uint32_t RESERVED0[31]; - __IO uint32_t PLL0CON; /* Clocking and Power Control */ - __IO uint32_t PLL0CFG; - __I uint32_t PLL0STAT; - __O uint32_t PLL0FEED; - uint32_t RESERVED1[4]; - __IO uint32_t PLL1CON; - __IO uint32_t PLL1CFG; - __I uint32_t PLL1STAT; - __O uint32_t PLL1FEED; - uint32_t RESERVED2[4]; - __IO uint32_t PCON; - __IO uint32_t PCONP; - uint32_t RESERVED3[15]; - __IO uint32_t CCLKCFG; - __IO uint32_t USBCLKCFG; - __IO uint32_t CLKSRCSEL; - __IO uint32_t CANSLEEPCLR; - __IO uint32_t CANWAKEFLAGS; - uint32_t RESERVED4[10]; - __IO uint32_t EXTINT; /* External Interrupts */ - uint32_t RESERVED5; - __IO uint32_t EXTMODE; - __IO uint32_t EXTPOLAR; - uint32_t RESERVED6[12]; - __IO uint32_t RSID; /* Reset */ - uint32_t RESERVED7[7]; - __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ - __IO uint32_t IRCTRIM; /* Clock Dividers */ - __IO uint32_t PCLKSEL0; - __IO uint32_t PCLKSEL1; - uint32_t RESERVED8[4]; - __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ - __IO uint32_t DMAREQSEL; - __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ - } LPC_SC_TypeDef; - -/*------------- Pin Connect Block (PINCON) -----------------------------------*/ -/** @brief Pin Connect Block (PINCON) register structure definition */ -typedef struct -{ - __IO uint32_t PINSEL0; - __IO uint32_t PINSEL1; - __IO uint32_t PINSEL2; - __IO uint32_t PINSEL3; - __IO uint32_t PINSEL4; - __IO uint32_t PINSEL5; - __IO uint32_t PINSEL6; - __IO uint32_t PINSEL7; - __IO uint32_t PINSEL8; - __IO uint32_t PINSEL9; - __IO uint32_t PINSEL10; - uint32_t RESERVED0[5]; - __IO uint32_t PINMODE0; - __IO uint32_t PINMODE1; - __IO uint32_t PINMODE2; - __IO uint32_t PINMODE3; - __IO uint32_t PINMODE4; - __IO uint32_t PINMODE5; - __IO uint32_t PINMODE6; - __IO uint32_t PINMODE7; - __IO uint32_t PINMODE8; - __IO uint32_t PINMODE9; - __IO uint32_t PINMODE_OD0; - __IO uint32_t PINMODE_OD1; - __IO uint32_t PINMODE_OD2; - __IO uint32_t PINMODE_OD3; - __IO uint32_t PINMODE_OD4; - __IO uint32_t I2CPADCFG; -} LPC_PINCON_TypeDef; - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -/** @brief General Purpose Input/Output (GPIO) register structure definition */ -typedef struct -{ - union { - __IO uint32_t FIODIR; - struct { - __IO uint16_t FIODIRL; - __IO uint16_t FIODIRH; - }; - struct { - __IO uint8_t FIODIR0; - __IO uint8_t FIODIR1; - __IO uint8_t FIODIR2; - __IO uint8_t FIODIR3; - }; - }; - uint32_t RESERVED0[3]; - union { - __IO uint32_t FIOMASK; - struct { - __IO uint16_t FIOMASKL; - __IO uint16_t FIOMASKH; - }; - struct { - __IO uint8_t FIOMASK0; - __IO uint8_t FIOMASK1; - __IO uint8_t FIOMASK2; - __IO uint8_t FIOMASK3; - }; - }; - union { - __IO uint32_t FIOPIN; - struct { - __IO uint16_t FIOPINL; - __IO uint16_t FIOPINH; - }; - struct { - __IO uint8_t FIOPIN0; - __IO uint8_t FIOPIN1; - __IO uint8_t FIOPIN2; - __IO uint8_t FIOPIN3; - }; - }; - union { - __IO uint32_t FIOSET; - struct { - __IO uint16_t FIOSETL; - __IO uint16_t FIOSETH; - }; - struct { - __IO uint8_t FIOSET0; - __IO uint8_t FIOSET1; - __IO uint8_t FIOSET2; - __IO uint8_t FIOSET3; - }; - }; - union { - __O uint32_t FIOCLR; - struct { - __O uint16_t FIOCLRL; - __O uint16_t FIOCLRH; - }; - struct { - __O uint8_t FIOCLR0; - __O uint8_t FIOCLR1; - __O uint8_t FIOCLR2; - __O uint8_t FIOCLR3; - }; - }; -} LPC_GPIO_TypeDef; - -/** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */ -typedef struct -{ - __I uint32_t IntStatus; - __I uint32_t IO0IntStatR; - __I uint32_t IO0IntStatF; - __O uint32_t IO0IntClr; - __IO uint32_t IO0IntEnR; - __IO uint32_t IO0IntEnF; - uint32_t RESERVED0[3]; - __I uint32_t IO2IntStatR; - __I uint32_t IO2IntStatF; - __O uint32_t IO2IntClr; - __IO uint32_t IO2IntEnR; - __IO uint32_t IO2IntEnF; -} LPC_GPIOINT_TypeDef; - -/*------------- Timer (TIM) --------------------------------------------------*/ -/** @brief Timer (TIM) register structure definition */ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - __I uint32_t CR1; - uint32_t RESERVED0[2]; - __IO uint32_t EMR; - uint32_t RESERVED1[12]; - __IO uint32_t CTCR; -} LPC_TIM_TypeDef; - -/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ -/** @brief Pulse-Width Modulation (PWM) register structure definition */ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - __I uint32_t CR1; - __I uint32_t CR2; - __I uint32_t CR3; - uint32_t RESERVED0; - __IO uint32_t MR4; - __IO uint32_t MR5; - __IO uint32_t MR6; - __IO uint32_t PCR; - __IO uint32_t LER; - uint32_t RESERVED1[7]; - __IO uint32_t CTCR; -} LPC_PWM_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -/** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */ -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __I uint8_t FIFOLVL; -} LPC_UART_TypeDef; - -/** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */ -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __I uint8_t FIFOLVL; -} LPC_UART0_TypeDef; - -/** @brief Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition */ -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[3]; - __IO uint8_t MCR; - uint8_t RESERVED2[3]; - __I uint8_t LSR; - uint8_t RESERVED3[3]; - __I uint8_t MSR; - uint8_t RESERVED4[3]; - __IO uint8_t SCR; - uint8_t RESERVED5[3]; - __IO uint32_t ACR; - uint32_t RESERVED6; - __IO uint32_t FDR; - uint32_t RESERVED7; - __IO uint8_t TER; - uint8_t RESERVED8[27]; - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3]; - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3]; - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3]; - __I uint8_t FIFOLVL; -} LPC_UART1_TypeDef; - -/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ -/** @brief Serial Peripheral Interface (SPI) register structure definition */ -typedef struct -{ - __IO uint32_t SPCR; - __I uint32_t SPSR; - __IO uint32_t SPDR; - __IO uint32_t SPCCR; - uint32_t RESERVED0[3]; - __IO uint32_t SPINT; -} LPC_SPI_TypeDef; - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -/** @brief Synchronous Serial Communication (SSP) register structure definition */ -typedef struct -{ - __IO uint32_t CR0; - __IO uint32_t CR1; - __IO uint32_t DR; - __I uint32_t SR; - __IO uint32_t CPSR; - __IO uint32_t IMSC; - __IO uint32_t RIS; - __IO uint32_t MIS; - __IO uint32_t ICR; - __IO uint32_t DMACR; -} LPC_SSP_TypeDef; - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -/** @brief Inter-Integrated Circuit (I2C) register structure definition */ -typedef struct -{ - __IO uint32_t I2CONSET; - __I uint32_t I2STAT; - __IO uint32_t I2DAT; - __IO uint32_t I2ADR0; - __IO uint32_t I2SCLH; - __IO uint32_t I2SCLL; - __O uint32_t I2CONCLR; - __IO uint32_t MMCTRL; - __IO uint32_t I2ADR1; - __IO uint32_t I2ADR2; - __IO uint32_t I2ADR3; - __I uint32_t I2DATA_BUFFER; - __IO uint32_t I2MASK0; - __IO uint32_t I2MASK1; - __IO uint32_t I2MASK2; - __IO uint32_t I2MASK3; -} LPC_I2C_TypeDef; - -/*------------- Inter IC Sound (I2S) -----------------------------------------*/ -/** @brief Inter IC Sound (I2S) register structure definition */ -typedef struct -{ - __IO uint32_t I2SDAO; - __IO uint32_t I2SDAI; - __O uint32_t I2STXFIFO; - __I uint32_t I2SRXFIFO; - __I uint32_t I2SSTATE; - __IO uint32_t I2SDMA1; - __IO uint32_t I2SDMA2; - __IO uint32_t I2SIRQ; - __IO uint32_t I2STXRATE; - __IO uint32_t I2SRXRATE; - __IO uint32_t I2STXBITRATE; - __IO uint32_t I2SRXBITRATE; - __IO uint32_t I2STXMODE; - __IO uint32_t I2SRXMODE; -} LPC_I2S_TypeDef; - -/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ -/** @brief Repetitive Interrupt Timer (RIT) register structure definition */ -typedef struct -{ - __IO uint32_t RICOMPVAL; - __IO uint32_t RIMASK; - __IO uint8_t RICTRL; - uint8_t RESERVED0[3]; - __IO uint32_t RICOUNTER; -} LPC_RIT_TypeDef; - -/*------------- Real-Time Clock (RTC) ----------------------------------------*/ -/** @brief Real-Time Clock (RTC) register structure definition */ -typedef struct -{ - __IO uint8_t ILR; - uint8_t RESERVED0[7]; - __IO uint8_t CCR; - uint8_t RESERVED1[3]; - __IO uint8_t CIIR; - uint8_t RESERVED2[3]; - __IO uint8_t AMR; - uint8_t RESERVED3[3]; - __I uint32_t CTIME0; - __I uint32_t CTIME1; - __I uint32_t CTIME2; - __IO uint8_t SEC; - uint8_t RESERVED4[3]; - __IO uint8_t MIN; - uint8_t RESERVED5[3]; - __IO uint8_t HOUR; - uint8_t RESERVED6[3]; - __IO uint8_t DOM; - uint8_t RESERVED7[3]; - __IO uint8_t DOW; - uint8_t RESERVED8[3]; - __IO uint16_t DOY; - uint16_t RESERVED9; - __IO uint8_t MONTH; - uint8_t RESERVED10[3]; - __IO uint16_t YEAR; - uint16_t RESERVED11; - __IO uint32_t CALIBRATION; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; - __IO uint8_t RTC_AUXEN; - uint8_t RESERVED12[3]; - __IO uint8_t RTC_AUX; - uint8_t RESERVED13[3]; - __IO uint8_t ALSEC; - uint8_t RESERVED14[3]; - __IO uint8_t ALMIN; - uint8_t RESERVED15[3]; - __IO uint8_t ALHOUR; - uint8_t RESERVED16[3]; - __IO uint8_t ALDOM; - uint8_t RESERVED17[3]; - __IO uint8_t ALDOW; - uint8_t RESERVED18[3]; - __IO uint16_t ALDOY; - uint16_t RESERVED19; - __IO uint8_t ALMON; - uint8_t RESERVED20[3]; - __IO uint16_t ALYEAR; - uint16_t RESERVED21; -} LPC_RTC_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -/** @brief Watchdog Timer (WDT) register structure definition */ -typedef struct -{ - __IO uint8_t WDMOD; - uint8_t RESERVED0[3]; - __IO uint32_t WDTC; - __O uint8_t WDFEED; - uint8_t RESERVED1[3]; - __I uint32_t WDTV; - __IO uint32_t WDCLKSEL; -} LPC_WDT_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -/** @brief Analog-to-Digital Converter (ADC) register structure definition */ -typedef struct -{ - __IO uint32_t ADCR; - __IO uint32_t ADGDR; - uint32_t RESERVED0; - __IO uint32_t ADINTEN; - __I uint32_t ADDR0; - __I uint32_t ADDR1; - __I uint32_t ADDR2; - __I uint32_t ADDR3; - __I uint32_t ADDR4; - __I uint32_t ADDR5; - __I uint32_t ADDR6; - __I uint32_t ADDR7; - __I uint32_t ADSTAT; - __IO uint32_t ADTRM; -} LPC_ADC_TypeDef; - -/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ -/** @brief Digital-to-Analog Converter (DAC) register structure definition */ -typedef struct -{ - __IO uint32_t DACR; - __IO uint32_t DACCTRL; - __IO uint16_t DACCNTVAL; -} LPC_DAC_TypeDef; - -/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ -/** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */ -typedef struct -{ - __I uint32_t MCCON; - __O uint32_t MCCON_SET; - __O uint32_t MCCON_CLR; - __I uint32_t MCCAPCON; - __O uint32_t MCCAPCON_SET; - __O uint32_t MCCAPCON_CLR; - __IO uint32_t MCTIM0; - __IO uint32_t MCTIM1; - __IO uint32_t MCTIM2; - __IO uint32_t MCPER0; - __IO uint32_t MCPER1; - __IO uint32_t MCPER2; - __IO uint32_t MCPW0; - __IO uint32_t MCPW1; - __IO uint32_t MCPW2; - __IO uint32_t MCDEADTIME; - __IO uint32_t MCCCP; - __IO uint32_t MCCR0; - __IO uint32_t MCCR1; - __IO uint32_t MCCR2; - __I uint32_t MCINTEN; - __O uint32_t MCINTEN_SET; - __O uint32_t MCINTEN_CLR; - __I uint32_t MCCNTCON; - __O uint32_t MCCNTCON_SET; - __O uint32_t MCCNTCON_CLR; - __I uint32_t MCINTFLAG; - __O uint32_t MCINTFLAG_SET; - __O uint32_t MCINTFLAG_CLR; - __O uint32_t MCCAP_CLR; -} LPC_MCPWM_TypeDef; - -/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ -/** @brief Quadrature Encoder Interface (QEI) register structure definition */ -typedef struct -{ - __O uint32_t QEICON; - __I uint32_t QEISTAT; - __IO uint32_t QEICONF; - __I uint32_t QEIPOS; - __IO uint32_t QEIMAXPOS; - __IO uint32_t CMPOS0; - __IO uint32_t CMPOS1; - __IO uint32_t CMPOS2; - __I uint32_t INXCNT; - __IO uint32_t INXCMP; - __IO uint32_t QEILOAD; - __I uint32_t QEITIME; - __I uint32_t QEIVEL; - __I uint32_t QEICAP; - __IO uint32_t VELCOMP; - __IO uint32_t FILTER; - uint32_t RESERVED0[998]; - __O uint32_t QEIIEC; - __O uint32_t QEIIES; - __I uint32_t QEIINTSTAT; - __I uint32_t QEIIE; - __O uint32_t QEICLR; - __O uint32_t QEISET; -} LPC_QEI_TypeDef; - -/*------------- Controller Area Network (CAN) --------------------------------*/ -/** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */ -typedef struct -{ - __IO uint32_t mask[512]; /* ID Masks */ -} LPC_CANAF_RAM_TypeDef; - -/** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */ -typedef struct /* Acceptance Filter Registers */ -{ - __IO uint32_t AFMR; - __IO uint32_t SFF_sa; - __IO uint32_t SFF_GRP_sa; - __IO uint32_t EFF_sa; - __IO uint32_t EFF_GRP_sa; - __IO uint32_t ENDofTable; - __I uint32_t LUTerrAd; - __I uint32_t LUTerr; - __IO uint32_t FCANIE; - __IO uint32_t FCANIC0; - __IO uint32_t FCANIC1; -} LPC_CANAF_TypeDef; - -/** @brief Controller Area Network Central (CANCR) register structure definition */ -typedef struct /* Central Registers */ -{ - __I uint32_t CANTxSR; - __I uint32_t CANRxSR; - __I uint32_t CANMSR; -} LPC_CANCR_TypeDef; - -/** @brief Controller Area Network Controller (CAN) register structure definition */ -typedef struct /* Controller Registers */ -{ - __IO uint32_t MOD; - __O uint32_t CMR; - __IO uint32_t GSR; - __I uint32_t ICR; - __IO uint32_t IER; - __IO uint32_t BTR; - __IO uint32_t EWL; - __I uint32_t SR; - __IO uint32_t RFS; - __IO uint32_t RID; - __IO uint32_t RDA; - __IO uint32_t RDB; - __IO uint32_t TFI1; - __IO uint32_t TID1; - __IO uint32_t TDA1; - __IO uint32_t TDB1; - __IO uint32_t TFI2; - __IO uint32_t TID2; - __IO uint32_t TDA2; - __IO uint32_t TDB2; - __IO uint32_t TFI3; - __IO uint32_t TID3; - __IO uint32_t TDA3; - __IO uint32_t TDB3; -} LPC_CAN_TypeDef; - -/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ -/** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */ -typedef struct /* Common Registers */ -{ - __I uint32_t DMACIntStat; - __I uint32_t DMACIntTCStat; - __O uint32_t DMACIntTCClear; - __I uint32_t DMACIntErrStat; - __O uint32_t DMACIntErrClr; - __I uint32_t DMACRawIntTCStat; - __I uint32_t DMACRawIntErrStat; - __I uint32_t DMACEnbldChns; - __IO uint32_t DMACSoftBReq; - __IO uint32_t DMACSoftSReq; - __IO uint32_t DMACSoftLBReq; - __IO uint32_t DMACSoftLSReq; - __IO uint32_t DMACConfig; - __IO uint32_t DMACSync; -} LPC_GPDMA_TypeDef; - -/** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */ -typedef struct /* Channel Registers */ -{ - __IO uint32_t DMACCSrcAddr; - __IO uint32_t DMACCDestAddr; - __IO uint32_t DMACCLLI; - __IO uint32_t DMACCControl; - __IO uint32_t DMACCConfig; -} LPC_GPDMACH_TypeDef; - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -/** @brief Universal Serial Bus (USB) register structure definition */ -typedef struct -{ - __I uint32_t HcRevision; /* USB Host Registers */ - __IO uint32_t HcControl; - __IO uint32_t HcCommandStatus; - __IO uint32_t HcInterruptStatus; - __IO uint32_t HcInterruptEnable; - __IO uint32_t HcInterruptDisable; - __IO uint32_t HcHCCA; - __I uint32_t HcPeriodCurrentED; - __IO uint32_t HcControlHeadED; - __IO uint32_t HcControlCurrentED; - __IO uint32_t HcBulkHeadED; - __IO uint32_t HcBulkCurrentED; - __I uint32_t HcDoneHead; - __IO uint32_t HcFmInterval; - __I uint32_t HcFmRemaining; - __I uint32_t HcFmNumber; - __IO uint32_t HcPeriodicStart; - __IO uint32_t HcLSTreshold; - __IO uint32_t HcRhDescriptorA; - __IO uint32_t HcRhDescriptorB; - __IO uint32_t HcRhStatus; - __IO uint32_t HcRhPortStatus1; - __IO uint32_t HcRhPortStatus2; - uint32_t RESERVED0[40]; - __I uint32_t Module_ID; - - __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ - __IO uint32_t OTGIntEn; - __O uint32_t OTGIntSet; - __O uint32_t OTGIntClr; - __IO uint32_t OTGStCtrl; - __IO uint32_t OTGTmr; - uint32_t RESERVED1[58]; - - __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t USBDevIntEn; - __O uint32_t USBDevIntClr; - __O uint32_t USBDevIntSet; - - __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ - __I uint32_t USBCmdData; - - __I uint32_t USBRxData; /* USB Device Transfer Registers */ - __O uint32_t USBTxData; - __I uint32_t USBRxPLen; - __O uint32_t USBTxPLen; - __IO uint32_t USBCtrl; - __O uint32_t USBDevIntPri; - - __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ - __IO uint32_t USBEpIntEn; - __O uint32_t USBEpIntClr; - __O uint32_t USBEpIntSet; - __O uint32_t USBEpIntPri; - - __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ - __O uint32_t USBEpInd; - __IO uint32_t USBMaxPSize; - - __I uint32_t USBDMARSt; /* USB Device DMA Registers */ - __O uint32_t USBDMARClr; - __O uint32_t USBDMARSet; - uint32_t RESERVED2[9]; - __IO uint32_t USBUDCAH; - __I uint32_t USBEpDMASt; - __O uint32_t USBEpDMAEn; - __O uint32_t USBEpDMADis; - __I uint32_t USBDMAIntSt; - __IO uint32_t USBDMAIntEn; - uint32_t RESERVED3[2]; - __I uint32_t USBEoTIntSt; - __O uint32_t USBEoTIntClr; - __O uint32_t USBEoTIntSet; - __I uint32_t USBNDDRIntSt; - __O uint32_t USBNDDRIntClr; - __O uint32_t USBNDDRIntSet; - __I uint32_t USBSysErrIntSt; - __O uint32_t USBSysErrIntClr; - __O uint32_t USBSysErrIntSet; - uint32_t RESERVED4[15]; - - union { - __I uint32_t I2C_RX; /* USB OTG I2C Registers */ - __O uint32_t I2C_TX; - }; - __I uint32_t I2C_STS; - __IO uint32_t I2C_CTL; - __IO uint32_t I2C_CLKHI; - __O uint32_t I2C_CLKLO; - uint32_t RESERVED5[824]; - - union { - __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ - __IO uint32_t OTGClkCtrl; - }; - union { - __I uint32_t USBClkSt; - __I uint32_t OTGClkSt; - }; -} LPC_USB_TypeDef; - -/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ -/** @brief Ethernet Media Access Controller (EMAC) register structure definition */ -typedef struct -{ - __IO uint32_t MAC1; /* MAC Registers */ - __IO uint32_t MAC2; - __IO uint32_t IPGT; - __IO uint32_t IPGR; - __IO uint32_t CLRT; - __IO uint32_t MAXF; - __IO uint32_t SUPP; - __IO uint32_t TEST; - __IO uint32_t MCFG; - __IO uint32_t MCMD; - __IO uint32_t MADR; - __O uint32_t MWTD; - __I uint32_t MRDD; - __I uint32_t MIND; - uint32_t RESERVED0[2]; - __IO uint32_t SA0; - __IO uint32_t SA1; - __IO uint32_t SA2; - uint32_t RESERVED1[45]; - __IO uint32_t Command; /* Control Registers */ - __I uint32_t Status; - __IO uint32_t RxDescriptor; - __IO uint32_t RxStatus; - __IO uint32_t RxDescriptorNumber; - __I uint32_t RxProduceIndex; - __IO uint32_t RxConsumeIndex; - __IO uint32_t TxDescriptor; - __IO uint32_t TxStatus; - __IO uint32_t TxDescriptorNumber; - __IO uint32_t TxProduceIndex; - __I uint32_t TxConsumeIndex; - uint32_t RESERVED2[10]; - __I uint32_t TSV0; - __I uint32_t TSV1; - __I uint32_t RSV; - uint32_t RESERVED3[3]; - __IO uint32_t FlowControlCounter; - __I uint32_t FlowControlStatus; - uint32_t RESERVED4[34]; - __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ - __IO uint32_t RxFilterWoLStatus; - __IO uint32_t RxFilterWoLClear; - uint32_t RESERVED5; - __IO uint32_t HashFilterL; - __IO uint32_t HashFilterH; - uint32_t RESERVED6[882]; - __I uint32_t IntStatus; /* Module Control Registers */ - __IO uint32_t IntEnable; - __O uint32_t IntClear; - __O uint32_t IntSet; - uint32_t RESERVED7; - __IO uint32_t PowerDown; - uint32_t RESERVED8; - __IO uint32_t Module_ID; -} LPC_EMAC_TypeDef; - - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#elif defined ( __ICCARM__ ) -#pragma language=restore -#endif - - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#ifdef __LPC17XX_REV00 -#define LPC_AHBRAM0_BASE (0x20000000UL) -#define LPC_AHBRAM1_BASE (0x20004000UL) -#else -#define LPC_AHBRAM0_BASE (0x2007C000UL) -#define LPC_AHBRAM1_BASE (0x20080000UL) -#endif -#define LPC_GPIO_BASE (0x2009C000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_APB1_BASE (0x40080000UL) -#define LPC_AHB_BASE (0x50000000UL) -#define LPC_CM3_BASE (0xE0000000UL) - -/* APB0 peripherals */ -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) -#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) -#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) -#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) -#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) -#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) -#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) - -/* APB1 peripherals */ -#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) -#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) -#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) -#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) -#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) -#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) -#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) -#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) -#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) -#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) -#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) -#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) - -/* AHB peripherals */ -#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) -#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) -#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) -#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) -#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) -#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) -#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) -#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) -#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) -#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) - -/* GPIOs */ -#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) -#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) -#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) -#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) -#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) -#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) -#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) -#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) -#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) -#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) -#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) -#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) -#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) -#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) -#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) -#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) -#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) -#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) -#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) -#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) -#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) -#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) -#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) -#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) -#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) -#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) -#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) -#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) -#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) -#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) -#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) -#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) -#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) -#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) -#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) -#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) -#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) -#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) -#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) -#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) -#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) -#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) -#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) - -/** - * @} - */ - -#endif // __LPC17xx_H__ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_libcfg_default.c cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_libcfg_default.c --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_libcfg_default.c 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_libcfg_default.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,76 +0,0 @@ -/********************************************************************** -* $Id$ lpc17xx_libcfg_default.c 2010-05-21 -*//** -* @file lpc17xx_libcfg_default.c -* @brief Library configuration source file (default), used to build -* library without examples -* @version 2.0 -* @date 21. May. 2010 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2010, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Library group ----------------------------------------------------------- */ -/** @addtogroup LIBCFG_DEFAULT - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc17xx_libcfg_default.h" - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup LIBCFG_DEFAULT_Public_Functions - * @{ - */ - -#ifndef __BUILD_WITH_EXAMPLE__ - -#ifdef DEBUG -/******************************************************************************* -* @brief Reports the name of the source file and the source line number -* where the CHECK_PARAM error has occurred. -* @param[in] file Pointer to the source file name -* @param[in] line assert_param error line source number -* @return None -*******************************************************************************/ -void check_failed(uint8_t *file, uint32_t line) -{ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\n", file, line) */ - - /* Infinite loop */ - while(1); -} -#endif /* DEBUG */ - -#endif /* __BUILD_WITH_EXAMPLE__ */ - -/** - * @} - */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_libcfg_default.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_libcfg_default.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_libcfg_default.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_libcfg_default.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,182 +0,0 @@ -/********************************************************************** -* $Id$ lpc17xx_libcfg_default.h 2010-05-21 -*//** -* @file lpc17xx_libcfg_default.h -* @brief Default Library configuration header file -* @version 2.0 -* @date 21. May. 2010 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2010, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Library Configuration group ----------------------------------------------------------- */ -/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT (Default Library Configuration) - * @ingroup LPC1700CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef LPC17XX_LIBCFG_DEFAULT_H_ -#define LPC17XX_LIBCFG_DEFAULT_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc_types.h" - - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros - * @{ - */ - -/************************** DEBUG MODE DEFINITIONS *********************************/ -/* Un-comment the line below to compile the library in DEBUG mode, this will expanse - the "CHECK_PARAM" macro in the FW library code */ - -#define DEBUG - - -/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/ -/* Comment the line below to disable the specific peripheral inclusion */ - -/* DEBUG_FRAMWORK ------------------------------ */ -#define _DBGFWK - -/* GPIO ------------------------------- */ -#define _GPIO - -/* EXTI ------------------------------- */ -#define _EXTI - -/* UART ------------------------------- */ -#define _UART -#define _UART0 -#define _UART1 -#define _UART2 -#define _UART3 - -/* SPI ------------------------------- */ -#define _SPI - -/* SYSTICK --------------------------- */ -#define _SYSTICK - -/* SSP ------------------------------- */ -#define _SSP -#define _SSP0 -#define _SSP1 - - -/* I2C ------------------------------- */ -#define _I2C -#define _I2C0 -#define _I2C1 -#define _I2C2 - -/* TIMER ------------------------------- */ -#define _TIM - -/* WDT ------------------------------- */ -#define _WDT - - -/* GPDMA ------------------------------- */ -#define _GPDMA - - -/* DAC ------------------------------- */ -#define _DAC - -/* DAC ------------------------------- */ -#define _ADC - - -/* PWM ------------------------------- */ -#define _PWM -#define _PWM1 - -/* RTC ------------------------------- */ -#define _RTC - -/* I2S ------------------------------- */ -#define _I2S - -/* USB device ------------------------------- */ -#define _USBDEV -#define _USB_DMA - -/* QEI ------------------------------- */ -#define _QEI - -/* MCPWM ------------------------------- */ -#define _MCPWM - -/* CAN--------------------------------*/ -#define _CAN - -/* RIT ------------------------------- */ -#define _RIT - -/* EMAC ------------------------------ */ -#define _EMAC - -/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/ - -#ifdef DEBUG -/******************************************************************************* -* @brief The CHECK_PARAM macro is used for function's parameters check. -* It is used only if the library is compiled in DEBUG mode. -* @param[in] expr - If expr is false, it calls check_failed() function -* which reports the name of the source file and the source -* line number of the call that failed. -* - If expr is true, it returns no value. -* @return None -*******************************************************************************/ -#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) -#else -#define CHECK_PARAM(expr) -#endif /* DEBUG */ - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions - * @{ - */ - -#ifdef DEBUG -void check_failed(uint8_t *file, uint32_t line); -#endif - -/** - * @} - */ - -#endif /* LPC17XX_LIBCFG_DEFAULT_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_pinsel.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_pinsel.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_pinsel.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_pinsel.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,203 +0,0 @@ -/********************************************************************** -* $Id$ lpc17xx_pinsel.h 2010-05-21 -*//** -* @file lpc17xx_pinsel.h -* @brief Contains all macro definitions and function prototypes -* support for Pin connect block firmware library on LPC17xx -* @version 2.0 -* @date 21. May. 2010 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2010, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup PINSEL PINSEL (Pin Selection) - * @ingroup LPC1700CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef LPC17XX_PINSEL_H_ -#define LPC17XX_PINSEL_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC17xx.h" -#include "lpc_types.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup PINSEL_Public_Macros PINSEL Public Macros - * @{ - */ - -/*********************************************************************//** - *!< Macros define for PORT Selection - ***********************************************************************/ -#define PINSEL_PORT_0 ((0)) /**< PORT 0*/ -#define PINSEL_PORT_1 ((1)) /**< PORT 1*/ -#define PINSEL_PORT_2 ((2)) /**< PORT 2*/ -#define PINSEL_PORT_3 ((3)) /**< PORT 3*/ -#define PINSEL_PORT_4 ((4)) /**< PORT 4*/ - -/*********************************************************************** - * Macros define for Pin Function selection - **********************************************************************/ -#define PINSEL_FUNC_0 ((0)) /**< default function*/ -#define PINSEL_FUNC_1 ((1)) /**< first alternate function*/ -#define PINSEL_FUNC_2 ((2)) /**< second alternate function*/ -#define PINSEL_FUNC_3 ((3)) /**< third or reserved alternate function*/ - -/*********************************************************************** - * Macros define for Pin Number of Port - **********************************************************************/ -#define PINSEL_PIN_0 ((0)) /**< Pin 0 */ -#define PINSEL_PIN_1 ((1)) /**< Pin 1 */ -#define PINSEL_PIN_2 ((2)) /**< Pin 2 */ -#define PINSEL_PIN_3 ((3)) /**< Pin 3 */ -#define PINSEL_PIN_4 ((4)) /**< Pin 4 */ -#define PINSEL_PIN_5 ((5)) /**< Pin 5 */ -#define PINSEL_PIN_6 ((6)) /**< Pin 6 */ -#define PINSEL_PIN_7 ((7)) /**< Pin 7 */ -#define PINSEL_PIN_8 ((8)) /**< Pin 8 */ -#define PINSEL_PIN_9 ((9)) /**< Pin 9 */ -#define PINSEL_PIN_10 ((10)) /**< Pin 10 */ -#define PINSEL_PIN_11 ((11)) /**< Pin 11 */ -#define PINSEL_PIN_12 ((12)) /**< Pin 12 */ -#define PINSEL_PIN_13 ((13)) /**< Pin 13 */ -#define PINSEL_PIN_14 ((14)) /**< Pin 14 */ -#define PINSEL_PIN_15 ((15)) /**< Pin 15 */ -#define PINSEL_PIN_16 ((16)) /**< Pin 16 */ -#define PINSEL_PIN_17 ((17)) /**< Pin 17 */ -#define PINSEL_PIN_18 ((18)) /**< Pin 18 */ -#define PINSEL_PIN_19 ((19)) /**< Pin 19 */ -#define PINSEL_PIN_20 ((20)) /**< Pin 20 */ -#define PINSEL_PIN_21 ((21)) /**< Pin 21 */ -#define PINSEL_PIN_22 ((22)) /**< Pin 22 */ -#define PINSEL_PIN_23 ((23)) /**< Pin 23 */ -#define PINSEL_PIN_24 ((24)) /**< Pin 24 */ -#define PINSEL_PIN_25 ((25)) /**< Pin 25 */ -#define PINSEL_PIN_26 ((26)) /**< Pin 26 */ -#define PINSEL_PIN_27 ((27)) /**< Pin 27 */ -#define PINSEL_PIN_28 ((28)) /**< Pin 28 */ -#define PINSEL_PIN_29 ((29)) /**< Pin 29 */ -#define PINSEL_PIN_30 ((30)) /**< Pin 30 */ -#define PINSEL_PIN_31 ((31)) /**< Pin 31 */ - -/*********************************************************************** - * Macros define for Pin mode - **********************************************************************/ -#define PINSEL_PINMODE_PULLUP ((0)) /**< Internal pull-up resistor*/ -#define PINSEL_PINMODE_TRISTATE ((2)) /**< Tri-state */ -#define PINSEL_PINMODE_PULLDOWN ((3)) /**< Internal pull-down resistor */ - -/*********************************************************************** - * Macros define for Pin mode (normal/open drain) - **********************************************************************/ -#define PINSEL_PINMODE_NORMAL ((0)) /**< Pin is in the normal (not open drain) mode.*/ -#define PINSEL_PINMODE_OPENDRAIN ((1)) /**< Pin is in the open drain mode */ - -/*********************************************************************** - * Macros define for I2C mode - ***********************************************************************/ -#define PINSEL_I2C_Normal_Mode ((0)) /**< The standard drive mode */ -#define PINSEL_I2C_Fast_Mode ((1)) /**< Fast Mode Plus drive mode */ - -/** - * @} - */ - -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup PINSEL_Private_Macros PINSEL Private Macros - * @{ - */ - -/* Pin selection define */ -/* I2C Pin Configuration register bit description */ -#define PINSEL_I2CPADCFG_SDADRV0 _BIT(0) /**< Drive mode control for the SDA0 pin, P0.27 */ -#define PINSEL_I2CPADCFG_SDAI2C0 _BIT(1) /**< I2C mode control for the SDA0 pin, P0.27 */ -#define PINSEL_I2CPADCFG_SCLDRV0 _BIT(2) /**< Drive mode control for the SCL0 pin, P0.28 */ -#define PINSEL_I2CPADCFG_SCLI2C0 _BIT(3) /**< I2C mode control for the SCL0 pin, P0.28 */ - -/** - * @} - */ - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup PINSEL_Public_Types PINSEL Public Types - * @{ - */ - -/** @brief Pin configuration structure */ -typedef struct -{ - uint8_t Portnum; /**< Port Number, should be PINSEL_PORT_x, - where x should be in range from 0 to 4 */ - uint8_t Pinnum; /**< Pin Number, should be PINSEL_PIN_x, - where x should be in range from 0 to 31 */ - uint8_t Funcnum; /**< Function Number, should be PINSEL_FUNC_x, - where x should be in range from 0 to 3 */ - uint8_t Pinmode; /**< Pin Mode, should be: - - PINSEL_PINMODE_PULLUP: Internal pull-up resistor - - PINSEL_PINMODE_TRISTATE: Tri-state - - PINSEL_PINMODE_PULLDOWN: Internal pull-down resistor */ - uint8_t OpenDrain; /**< OpenDrain mode, should be: - - PINSEL_PINMODE_NORMAL: Pin is in the normal (not open drain) mode - - PINSEL_PINMODE_OPENDRAIN: Pin is in the open drain mode */ -} PINSEL_CFG_Type; - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup PINSEL_Public_Functions PINSEL Public Functions - * @{ - */ - -void PINSEL_ConfigPin(PINSEL_CFG_Type *PinCfg); -void PINSEL_ConfigTraceFunc (FunctionalState NewState); -void PINSEL_SetI2C0Pins(uint8_t i2cPinMode, FunctionalState filterSlewRateEnable); - - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* LPC17XX_PINSEL_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ - diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_timer.c cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_timer.c --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_timer.c 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_timer.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,609 +0,0 @@ -/********************************************************************** -* $Id$ lpc17xx_timer.c 2011-03-10 -*//** -* @file lpc17xx_timer.c -* @brief Contains all functions support for Timer firmware library -* on LPC17xx -* @version 3.1 -* @date 10. March. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @addtogroup TIM - * @{ - */ - -/* Includes ------------------------------------------------------------------- */ -#include "lpc17xx_timer.h" -#include "lpc17xx_clkpwr.h" -#include "lpc17xx_pinsel.h" - -/* If this source file built with example, the LPC17xx FW library configuration - * file in each example directory ("lpc17xx_libcfg.h") must be included, - * otherwise the default FW library configuration file must be included instead - */ -#ifdef __BUILD_WITH_EXAMPLE__ -#include "lpc17xx_libcfg.h" -#else -#include "lpc17xx_libcfg_default.h" -#endif /* __BUILD_WITH_EXAMPLE__ */ - -#ifdef _TIM - -/* Private Functions ---------------------------------------------------------- */ - -static uint32_t getPClock (uint32_t timernum); -static uint32_t converUSecToVal (uint32_t timernum, uint32_t usec); -static uint32_t converPtrToTimeNum (LPC_TIM_TypeDef *TIMx); - - -/*********************************************************************//** - * @brief Get peripheral clock of each timer controller - * @param[in] timernum Timer number - * @return Peripheral clock of timer - **********************************************************************/ -static uint32_t getPClock (uint32_t timernum) -{ - uint32_t clkdlycnt; - switch (timernum) - { - case 0: - clkdlycnt = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_TIMER0); - break; - - case 1: - clkdlycnt = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_TIMER1); - break; - - case 2: - clkdlycnt = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_TIMER2); - break; - - case 3: - clkdlycnt = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_TIMER3); - break; - } - return clkdlycnt; -} - - -/*********************************************************************//** - * @brief Convert a time to a timer count value - * @param[in] timernum Timer number - * @param[in] usec Time in microseconds - * @return The number of required clock ticks to give the time delay - **********************************************************************/ -uint32_t converUSecToVal (uint32_t timernum, uint32_t usec) -{ - uint64_t clkdlycnt; - - // Get Pclock of timer - clkdlycnt = (uint64_t) getPClock(timernum); - - clkdlycnt = (clkdlycnt * usec) / 1000000; - return (uint32_t) clkdlycnt; -} - - -/*********************************************************************//** - * @brief Convert a timer register pointer to a timer number - * @param[in] TIMx Pointer to LPC_TIM_TypeDef, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @return The timer number (0 to 3) or 0xFFFF FFFF if register pointer is bad - **********************************************************************/ -uint32_t converPtrToTimeNum (LPC_TIM_TypeDef *TIMx) -{ - uint32_t tnum = 0xFFFFFFFF; - - if (TIMx == LPC_TIM0) - { - tnum = 0; - } - else if (TIMx == LPC_TIM1) - { - tnum = 1; - } - else if (TIMx == LPC_TIM2) - { - tnum = 2; - } - else if (TIMx == LPC_TIM3) - { - tnum = 3; - } - - return tnum; -} - -/* End of Private Functions ---------------------------------------------------- */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @addtogroup TIM_Public_Functions - * @{ - */ - -/*********************************************************************//** - * @brief Get Interrupt Status - * @param[in] TIMx Timer selection, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] IntFlag: interrupt type, should be: - * - TIM_MR0_INT: Interrupt for Match channel 0 - * - TIM_MR1_INT: Interrupt for Match channel 1 - * - TIM_MR2_INT: Interrupt for Match channel 2 - * - TIM_MR3_INT: Interrupt for Match channel 3 - * - TIM_CR0_INT: Interrupt for Capture channel 0 - * - TIM_CR1_INT: Interrupt for Capture channel 1 - * @return FlagStatus - * - SET : interrupt - * - RESET : no interrupt - **********************************************************************/ -FlagStatus TIM_GetIntStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag) -{ - uint8_t temp; - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag)); - temp = (TIMx->IR)& TIM_IR_CLR(IntFlag); - if (temp) - return SET; - - return RESET; - -} -/*********************************************************************//** - * @brief Get Capture Interrupt Status - * @param[in] TIMx Timer selection, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] IntFlag: interrupt type, should be: - * - TIM_MR0_INT: Interrupt for Match channel 0 - * - TIM_MR1_INT: Interrupt for Match channel 1 - * - TIM_MR2_INT: Interrupt for Match channel 2 - * - TIM_MR3_INT: Interrupt for Match channel 3 - * - TIM_CR0_INT: Interrupt for Capture channel 0 - * - TIM_CR1_INT: Interrupt for Capture channel 1 - * @return FlagStatus - * - SET : interrupt - * - RESET : no interrupt - **********************************************************************/ -FlagStatus TIM_GetIntCaptureStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag) -{ - uint8_t temp; - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag)); - temp = (TIMx->IR) & (1<<(4+IntFlag)); - if(temp) - return SET; - return RESET; -} -/*********************************************************************//** - * @brief Clear Interrupt pending - * @param[in] TIMx Timer selection, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] IntFlag: interrupt type, should be: - * - TIM_MR0_INT: Interrupt for Match channel 0 - * - TIM_MR1_INT: Interrupt for Match channel 1 - * - TIM_MR2_INT: Interrupt for Match channel 2 - * - TIM_MR3_INT: Interrupt for Match channel 3 - * - TIM_CR0_INT: Interrupt for Capture channel 0 - * - TIM_CR1_INT: Interrupt for Capture channel 1 - * @return None - **********************************************************************/ -void TIM_ClearIntPending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag)); - TIMx->IR = TIM_IR_CLR(IntFlag); -} - -/*********************************************************************//** - * @brief Clear Capture Interrupt pending - * @param[in] TIMx Timer selection, should be - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] IntFlag interrupt type, should be: - * - TIM_MR0_INT: Interrupt for Match channel 0 - * - TIM_MR1_INT: Interrupt for Match channel 1 - * - TIM_MR2_INT: Interrupt for Match channel 2 - * - TIM_MR3_INT: Interrupt for Match channel 3 - * - TIM_CR0_INT: Interrupt for Capture channel 0 - * - TIM_CR1_INT: Interrupt for Capture channel 1 - * @return None - **********************************************************************/ -void TIM_ClearIntCapturePending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag)); - TIMx->IR = (1<<(4+IntFlag)); -} - -/*********************************************************************//** - * @brief Configuration for Timer at initial time - * @param[in] TimerCounterMode timer counter mode, should be: - * - TIM_TIMER_MODE: Timer mode - * - TIM_COUNTER_RISING_MODE: Counter rising mode - * - TIM_COUNTER_FALLING_MODE: Counter falling mode - * - TIM_COUNTER_ANY_MODE:Counter on both edges - * @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type or - * TIM_COUNTERCFG_Type - * @return None - **********************************************************************/ -void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct) -{ - if (TimerCounterMode == TIM_TIMER_MODE ) - { - TIM_TIMERCFG_Type * pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct; - pTimeCfg->PrescaleOption = TIM_PRESCALE_USVAL; - pTimeCfg->PrescaleValue = 1; - } - else - { - TIM_COUNTERCFG_Type * pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct; - pCounterCfg->CountInputSelect = TIM_COUNTER_INCAP0; - } -} - -/*********************************************************************//** - * @brief Initial Timer/Counter device - * Set Clock frequency for Timer - * Set initial configuration for Timer - * @param[in] TIMx Timer selection, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] TimerCounterMode Timer counter mode, should be: - * - TIM_TIMER_MODE: Timer mode - * - TIM_COUNTER_RISING_MODE: Counter rising mode - * - TIM_COUNTER_FALLING_MODE: Counter falling mode - * - TIM_COUNTER_ANY_MODE:Counter on both edges - * @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type - * that contains the configuration information for the - * specified Timer peripheral. - * @return None - **********************************************************************/ -void TIM_Init(LPC_TIM_TypeDef *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct) -{ - TIM_TIMERCFG_Type *pTimeCfg; - TIM_COUNTERCFG_Type *pCounterCfg; - - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_MODE_OPT(TimerCounterMode)); - - //set power - - if (TIMx== LPC_TIM0) - { - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM0, ENABLE); - //PCLK_Timer0 = CCLK/4 - CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER0, CLKPWR_PCLKSEL_CCLK_DIV_4); - } - else if (TIMx== LPC_TIM1) - { - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM1, ENABLE); - //PCLK_Timer1 = CCLK/4 - CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER1, CLKPWR_PCLKSEL_CCLK_DIV_4); - - } - - else if (TIMx== LPC_TIM2) - { - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, ENABLE); - //PCLK_Timer2= CCLK/4 - CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER2, CLKPWR_PCLKSEL_CCLK_DIV_4); - } - else if (TIMx== LPC_TIM3) - { - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM3, ENABLE); - //PCLK_Timer3= CCLK/4 - CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER3, CLKPWR_PCLKSEL_CCLK_DIV_4); - - } - - TIMx->CCR &= ~TIM_CTCR_MODE_MASK; - TIMx->CCR |= TIM_TIMER_MODE; - - TIMx->TC =0; - TIMx->PC =0; - TIMx->PR =0; - TIMx->TCR |= (1<<1); //Reset Counter - TIMx->TCR &= ~(1<<1); //release reset - if (TimerCounterMode == TIM_TIMER_MODE ) - { - pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct; - if (pTimeCfg->PrescaleOption == TIM_PRESCALE_TICKVAL) - { - TIMx->PR = pTimeCfg->PrescaleValue -1 ; - } - else - { - TIMx->PR = converUSecToVal (converPtrToTimeNum(TIMx),pTimeCfg->PrescaleValue)-1; - } - } - else - { - - pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct; - TIMx->CCR &= ~TIM_CTCR_INPUT_MASK; - if (pCounterCfg->CountInputSelect == TIM_COUNTER_INCAP1) - TIMx->CCR |= _BIT(2); - } - - // Clear interrupt pending - TIMx->IR = 0xFFFFFFFF; - -} - -/*********************************************************************//** - * @brief Close Timer/Counter device - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @return None - **********************************************************************/ -void TIM_DeInit (LPC_TIM_TypeDef *TIMx) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - // Disable timer/counter - TIMx->TCR = 0x00; - - // Disable power - if (TIMx== LPC_TIM0) - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM0, DISABLE); - - else if (TIMx== LPC_TIM1) - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM1, DISABLE); - - else if (TIMx== LPC_TIM2) - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, DISABLE); - - else if (TIMx== LPC_TIM3) - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, DISABLE); - -} - -/*********************************************************************//** - * @brief Start/Stop Timer/Counter device - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] NewState - * - ENABLE : set timer enable - * - DISABLE : disable timer - * @return None - **********************************************************************/ -void TIM_Cmd(LPC_TIM_TypeDef *TIMx, FunctionalState NewState) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - if (NewState == ENABLE) - { - TIMx->TCR |= TIM_ENABLE; - } - else - { - TIMx->TCR &= ~TIM_ENABLE; - } -} - -/*********************************************************************//** - * @brief Reset Timer/Counter device, - * Make TC and PC are synchronously reset on the next - * positive edge of PCLK - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @return None - **********************************************************************/ -void TIM_ResetCounter(LPC_TIM_TypeDef *TIMx) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - TIMx->TCR |= TIM_RESET; - TIMx->TCR &= ~TIM_RESET; -} - -/*********************************************************************//** - * @brief Configuration for Match register - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] TIM_MatchConfigStruct Pointer to TIM_MATCHCFG_Type - * - MatchChannel : choose channel 0 or 1 - * - IntOnMatch : if SET, interrupt will be generated when MRxx match - * the value in TC - * - StopOnMatch : if SET, TC and PC will be stopped whenM Rxx match - * the value in TC - * - ResetOnMatch : if SET, Reset on MR0 when MRxx match - * the value in TC - * -ExtMatchOutputType: Select output for external match - * + 0: Do nothing for external output pin if match - * + 1: Force external output pin to low if match - * + 2: Force external output pin to high if match - * + 3: Toggle external output pin if match - * MatchValue: Set the value to be compared with TC value - * @return None - **********************************************************************/ -void TIM_ConfigMatch(LPC_TIM_TypeDef *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct) -{ - - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_EXTMATCH_OPT(TIM_MatchConfigStruct->ExtMatchOutputType)); - - switch(TIM_MatchConfigStruct->MatchChannel) - { - case 0: - TIMx->MR0 = TIM_MatchConfigStruct->MatchValue; - break; - case 1: - TIMx->MR1 = TIM_MatchConfigStruct->MatchValue; - break; - case 2: - TIMx->MR2 = TIM_MatchConfigStruct->MatchValue; - break; - case 3: - TIMx->MR3 = TIM_MatchConfigStruct->MatchValue; - break; - default: - //Error match value - //Error loop - while(1); - } - //interrupt on MRn - TIMx->MCR &=~TIM_MCR_CHANNEL_MASKBIT(TIM_MatchConfigStruct->MatchChannel); - - if (TIM_MatchConfigStruct->IntOnMatch) - TIMx->MCR |= TIM_INT_ON_MATCH(TIM_MatchConfigStruct->MatchChannel); - - //reset on MRn - if (TIM_MatchConfigStruct->ResetOnMatch) - TIMx->MCR |= TIM_RESET_ON_MATCH(TIM_MatchConfigStruct->MatchChannel); - - //stop on MRn - if (TIM_MatchConfigStruct->StopOnMatch) - TIMx->MCR |= TIM_STOP_ON_MATCH(TIM_MatchConfigStruct->MatchChannel); - - // match output type - - TIMx->EMR &= ~TIM_EM_MASK(TIM_MatchConfigStruct->MatchChannel); - TIMx->EMR |= TIM_EM_SET(TIM_MatchConfigStruct->MatchChannel,TIM_MatchConfigStruct->ExtMatchOutputType); -} -/*********************************************************************//** - * @brief Update Match value - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] MatchChannel Match channel, should be: 0..3 - * @param[in] MatchValue updated match value - * @return None - **********************************************************************/ -void TIM_UpdateMatchValue(LPC_TIM_TypeDef *TIMx,uint8_t MatchChannel, uint32_t MatchValue) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - switch(MatchChannel) - { - case 0: - TIMx->MR0 = MatchValue; - break; - case 1: - TIMx->MR1 = MatchValue; - break; - case 2: - TIMx->MR2 = MatchValue; - break; - case 3: - TIMx->MR3 = MatchValue; - break; - default: - //Error Loop - while(1); - } - -} -/*********************************************************************//** - * @brief Configuration for Capture register - * @param[in] TIMx Pointer to timer device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * - CaptureChannel: set the channel to capture data - * - RisingEdge : if SET, Capture at rising edge - * - FallingEdge : if SET, Capture at falling edge - * - IntOnCaption : if SET, Capture generate interrupt - * @param[in] TIM_CaptureConfigStruct Pointer to TIM_CAPTURECFG_Type - * @return None - **********************************************************************/ -void TIM_ConfigCapture(LPC_TIM_TypeDef *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct) -{ - - CHECK_PARAM(PARAM_TIMx(TIMx)); - TIMx->CCR &= ~TIM_CCR_CHANNEL_MASKBIT(TIM_CaptureConfigStruct->CaptureChannel); - - if (TIM_CaptureConfigStruct->RisingEdge) - TIMx->CCR |= TIM_CAP_RISING(TIM_CaptureConfigStruct->CaptureChannel); - - if (TIM_CaptureConfigStruct->FallingEdge) - TIMx->CCR |= TIM_CAP_FALLING(TIM_CaptureConfigStruct->CaptureChannel); - - if (TIM_CaptureConfigStruct->IntOnCaption) - TIMx->CCR |= TIM_INT_ON_CAP(TIM_CaptureConfigStruct->CaptureChannel); -} - -/*********************************************************************//** - * @brief Read value of capture register in timer/counter device - * @param[in] TIMx Pointer to timer/counter device, should be: - * - LPC_TIM0: TIMER0 peripheral - * - LPC_TIM1: TIMER1 peripheral - * - LPC_TIM2: TIMER2 peripheral - * - LPC_TIM3: TIMER3 peripheral - * @param[in] CaptureChannel: capture channel number, should be: - * - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn - * - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn - * @return Value of capture register - **********************************************************************/ -uint32_t TIM_GetCaptureValue(LPC_TIM_TypeDef *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel) -{ - CHECK_PARAM(PARAM_TIMx(TIMx)); - CHECK_PARAM(PARAM_TIM_COUNTER_INPUT_OPT(CaptureChannel)); - - if(CaptureChannel==0) - return TIMx->CR0; - else - return TIMx->CR1; -} - -/** - * @} - */ - -#endif /* _TIMER */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_timer.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_timer.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc17xx_timer.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc17xx_timer.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,348 +0,0 @@ -/********************************************************************** -* $Id$ lpc17xx_timer.h 2010-05-21 -*//** -* @file lpc17xx_timer.h -* @brief Contains all macro definitions and function prototypes -* support for Timer firmware library on LPC17xx -* @version 2.0 -* @date 21. May. 2010 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2010, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Peripheral group ----------------------------------------------------------- */ -/** @defgroup TIM TIM (Timer) - * @ingroup LPC1700CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef __LPC17XX_TIMER_H_ -#define __LPC17XX_TIMER_H_ - -/* Includes ------------------------------------------------------------------- */ -#include "LPC17xx.h" -#include "lpc_types.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Private Macros ------------------------------------------------------------- */ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ - -/* --------------------- BIT DEFINITIONS -------------------------------------- */ -/********************************************************************** -** Interrupt information -**********************************************************************/ -/** Macro to clean interrupt pending */ -#define TIM_IR_CLR(n) _BIT(n) - -/********************************************************************** -** Timer interrupt register definitions -**********************************************************************/ -/** Macro for getting a timer match interrupt bit */ -#define TIM_MATCH_INT(n) (_BIT(n & 0x0F)) -/** Macro for getting a capture event interrupt bit */ -#define TIM_CAP_INT(n) (_BIT(((n & 0x0F) + 4))) - -/********************************************************************** -* Timer control register definitions -**********************************************************************/ -/** Timer/counter enable bit */ -#define TIM_ENABLE ((uint32_t)(1<<0)) -/** Timer/counter reset bit */ -#define TIM_RESET ((uint32_t)(1<<1)) -/** Timer control bit mask */ -#define TIM_TCR_MASKBIT ((uint32_t)(3)) - -/********************************************************************** -* Timer match control register definitions -**********************************************************************/ -/** Bit location for interrupt on MRx match, n = 0 to 3 */ -#define TIM_INT_ON_MATCH(n) (_BIT((n * 3))) -/** Bit location for reset on MRx match, n = 0 to 3 */ -#define TIM_RESET_ON_MATCH(n) (_BIT(((n * 3) + 1))) -/** Bit location for stop on MRx match, n = 0 to 3 */ -#define TIM_STOP_ON_MATCH(n) (_BIT(((n * 3) + 2))) -/** Timer Match control bit mask */ -#define TIM_MCR_MASKBIT ((uint32_t)(0x0FFF)) -/** Timer Match control bit mask for specific channel*/ -#define TIM_MCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3))) - -/********************************************************************** -* Timer capture control register definitions -**********************************************************************/ -/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */ -#define TIM_CAP_RISING(n) (_BIT((n * 3))) -/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */ -#define TIM_CAP_FALLING(n) (_BIT(((n * 3) + 1))) -/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */ -#define TIM_INT_ON_CAP(n) (_BIT(((n * 3) + 2))) -/** Mask bit for rising and falling edge bit */ -#define TIM_EDGE_MASK(n) (_SBF((n * 3), 0x03)) -/** Timer capture control bit mask */ -#define TIM_CCR_MASKBIT ((uint32_t)(0x3F)) -/** Timer Capture control bit mask for specific channel*/ -#define TIM_CCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3))) - -/********************************************************************** -* Timer external match register definitions -**********************************************************************/ -/** Bit location for output state change of MAT.n when external match - happens, n = 0 to 3 */ -#define TIM_EM(n) _BIT(n) -/** Output state change of MAT.n when external match happens: no change */ -#define TIM_EM_NOTHING ((uint8_t)(0x0)) -/** Output state change of MAT.n when external match happens: low */ -#define TIM_EM_LOW ((uint8_t)(0x1)) -/** Output state change of MAT.n when external match happens: high */ -#define TIM_EM_HIGH ((uint8_t)(0x2)) -/** Output state change of MAT.n when external match happens: toggle */ -#define TIM_EM_TOGGLE ((uint8_t)(0x3)) -/** Macro for setting for the MAT.n change state bits */ -#define TIM_EM_SET(n,s) (_SBF(((n << 1) + 4), (s & 0x03))) -/** Mask for the MAT.n change state bits */ -#define TIM_EM_MASK(n) (_SBF(((n << 1) + 4), 0x03)) -/** Timer external match bit mask */ -#define TIM_EMR_MASKBIT 0x0FFF - -/********************************************************************** -* Timer Count Control Register definitions -**********************************************************************/ -/** Mask to get the Counter/timer mode bits */ -#define TIM_CTCR_MODE_MASK 0x3 -/** Mask to get the count input select bits */ -#define TIM_CTCR_INPUT_MASK 0xC -/** Timer Count control bit mask */ -#define TIM_CTCR_MASKBIT 0xF -#define TIM_COUNTER_MODE ((uint8_t)(1)) - - -/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ -/** Macro to determine if it is valid TIMER peripheral */ -#define PARAM_TIMx(n) ((((uint32_t *)n)==((uint32_t *)LPC_TIM0)) || (((uint32_t *)n)==((uint32_t *)LPC_TIM1)) \ -|| (((uint32_t *)n)==((uint32_t *)LPC_TIM2)) || (((uint32_t *)n)==((uint32_t *)LPC_TIM3))) - -/* Macro check interrupt type */ -#define PARAM_TIM_INT_TYPE(TYPE) ((TYPE ==TIM_MR0_INT)||(TYPE ==TIM_MR1_INT)\ -||(TYPE ==TIM_MR2_INT)||(TYPE ==TIM_MR3_INT)\ -||(TYPE ==TIM_CR0_INT)||(TYPE ==TIM_CR1_INT)) - -/* Macro check TIMER mode */ -#define PARAM_TIM_MODE_OPT(MODE) ((MODE == TIM_TIMER_MODE)||(MODE == TIM_COUNTER_RISING_MODE)\ -|| (MODE == TIM_COUNTER_RISING_MODE)||(MODE == TIM_COUNTER_RISING_MODE)) - -/* Macro check TIMER prescale value */ -#define PARAM_TIM_PRESCALE_OPT(OPT) ((OPT == TIM_PRESCALE_TICKVAL)||(OPT == TIM_PRESCALE_USVAL)) - -/* Macro check TIMER counter intput mode */ -#define PARAM_TIM_COUNTER_INPUT_OPT(OPT) ((OPT == TIM_COUNTER_INCAP0)||(OPT == TIM_COUNTER_INCAP1)) - -/* Macro check TIMER external match mode */ -#define PARAM_TIM_EXTMATCH_OPT(OPT) ((OPT == TIM_EXTMATCH_NOTHING)||(OPT == TIM_EXTMATCH_LOW)\ -||(OPT == TIM_EXTMATCH_HIGH)||(OPT == TIM_EXTMATCH_TOGGLE)) - -/* Macro check TIMER external match mode */ -#define PARAM_TIM_CAP_MODE_OPT(OPT) ((OPT == TIM_CAPTURE_NONE)||(OPT == TIM_CAPTURE_RISING) \ -||(OPT == TIM_CAPTURE_FALLING)||(OPT == TIM_CAPTURE_ANY)) - -/** - * @} - */ - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup TIM_Public_Types TIM Public Types - * @{ - */ - -/*********************************************************************** - * Timer device enumeration -**********************************************************************/ -/** @brief interrupt type */ -typedef enum -{ - TIM_MR0_INT =0, /*!< interrupt for Match channel 0*/ - TIM_MR1_INT =1, /*!< interrupt for Match channel 1*/ - TIM_MR2_INT =2, /*!< interrupt for Match channel 2*/ - TIM_MR3_INT =3, /*!< interrupt for Match channel 3*/ - TIM_CR0_INT =4, /*!< interrupt for Capture channel 0*/ - TIM_CR1_INT =5 /*!< interrupt for Capture channel 1*/ -}TIM_INT_TYPE; - -/** @brief Timer/counter operating mode */ -typedef enum -{ - TIM_TIMER_MODE = 0, /*!< Timer mode */ - TIM_COUNTER_RISING_MODE, /*!< Counter rising mode */ - TIM_COUNTER_FALLING_MODE, /*!< Counter falling mode */ - TIM_COUNTER_ANY_MODE /*!< Counter on both edges */ -} TIM_MODE_OPT; - -/** @brief Timer/Counter prescale option */ -typedef enum -{ - TIM_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */ - TIM_PRESCALE_USVAL /*!< Prescale in microsecond value */ -} TIM_PRESCALE_OPT; - -/** @brief Counter input option */ -typedef enum -{ - TIM_COUNTER_INCAP0 = 0, /*!< CAPn.0 input pin for TIMERn */ - TIM_COUNTER_INCAP1, /*!< CAPn.1 input pin for TIMERn */ -} TIM_COUNTER_INPUT_OPT; - -/** @brief Timer/Counter external match option */ -typedef enum -{ - TIM_EXTMATCH_NOTHING = 0, /*!< Do nothing for external output pin if match */ - TIM_EXTMATCH_LOW, /*!< Force external output pin to low if match */ - TIM_EXTMATCH_HIGH, /*!< Force external output pin to high if match */ - TIM_EXTMATCH_TOGGLE /*!< Toggle external output pin if match */ -}TIM_EXTMATCH_OPT; - -/** @brief Timer/counter capture mode options */ -typedef enum { - TIM_CAPTURE_NONE = 0, /*!< No Capture */ - TIM_CAPTURE_RISING, /*!< Rising capture mode */ - TIM_CAPTURE_FALLING, /*!< Falling capture mode */ - TIM_CAPTURE_ANY /*!< On both edges */ -} TIM_CAP_MODE_OPT; - -/** @brief Configuration structure in TIMER mode */ -typedef struct -{ - - uint8_t PrescaleOption; /**< Timer Prescale option, should be: - - TIM_PRESCALE_TICKVAL: Prescale in absolute value - - TIM_PRESCALE_USVAL: Prescale in microsecond value - */ - uint8_t Reserved[3]; /**< Reserved */ - uint32_t PrescaleValue; /**< Prescale value */ -} TIM_TIMERCFG_Type; - -/** @brief Configuration structure in COUNTER mode */ -typedef struct { - - uint8_t CounterOption; /**< Counter Option, should be: - - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn - - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn - */ - uint8_t CountInputSelect; - uint8_t Reserved[2]; -} TIM_COUNTERCFG_Type; - -/** @brief Match channel configuration structure */ -typedef struct { - uint8_t MatchChannel; /**< Match channel, should be in range - from 0..3 */ - uint8_t IntOnMatch; /**< Interrupt On match, should be: - - ENABLE: Enable this function. - - DISABLE: Disable this function. - */ - uint8_t StopOnMatch; /**< Stop On match, should be: - - ENABLE: Enable this function. - - DISABLE: Disable this function. - */ - uint8_t ResetOnMatch; /**< Reset On match, should be: - - ENABLE: Enable this function. - - DISABLE: Disable this function. - */ - - uint8_t ExtMatchOutputType; /**< External Match Output type, should be: - - TIM_EXTMATCH_NOTHING: Do nothing for external output pin if match - - TIM_EXTMATCH_LOW: Force external output pin to low if match - - TIM_EXTMATCH_HIGH: Force external output pin to high if match - - TIM_EXTMATCH_TOGGLE: Toggle external output pin if match. - */ - uint8_t Reserved[3]; /** Reserved */ - uint32_t MatchValue; /** Match value */ -} TIM_MATCHCFG_Type; - -/** @brief Capture Input configuration structure */ -typedef struct { - uint8_t CaptureChannel; /**< Capture channel, should be in range - from 0..1 */ - uint8_t RisingEdge; /**< caption rising edge, should be: - - ENABLE: Enable rising edge. - - DISABLE: Disable this function. - */ - uint8_t FallingEdge; /**< caption falling edge, should be: - - ENABLE: Enable falling edge. - - DISABLE: Disable this function. - */ - uint8_t IntOnCaption; /**< Interrupt On caption, should be: - - ENABLE: Enable interrupt function. - - DISABLE: Disable this function. - */ - -} TIM_CAPTURECFG_Type; - -/** - * @} - */ - - -/* Public Functions ----------------------------------------------------------- */ -/** @defgroup TIM_Public_Functions TIM Public Functions - * @{ - */ -/* Init/DeInit TIM functions -----------*/ -void TIM_Init(LPC_TIM_TypeDef *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct); -void TIM_DeInit(LPC_TIM_TypeDef *TIMx); - -/* TIM interrupt functions -------------*/ -void TIM_ClearIntPending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag); -void TIM_ClearIntCapturePending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag); -FlagStatus TIM_GetIntStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag); -FlagStatus TIM_GetIntCaptureStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag); - -/* TIM configuration functions --------*/ -void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct); -void TIM_ConfigMatch(LPC_TIM_TypeDef *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct); -void TIM_UpdateMatchValue(LPC_TIM_TypeDef *TIMx,uint8_t MatchChannel, uint32_t MatchValue); -void TIM_SetMatchExt(LPC_TIM_TypeDef *TIMx,TIM_EXTMATCH_OPT ext_match ); -void TIM_ConfigCapture(LPC_TIM_TypeDef *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct); -void TIM_Cmd(LPC_TIM_TypeDef *TIMx, FunctionalState NewState); - -uint32_t TIM_GetCaptureValue(LPC_TIM_TypeDef *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel); -void TIM_ResetCounter(LPC_TIM_TypeDef *TIMx); - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __LPC17XX_TIMER_H_ */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc_types.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc_types.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/lpc_types.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/lpc_types.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,212 +0,0 @@ -/********************************************************************** -* $Id$ lpc_types.h 2008-07-27 -*//** -* @file lpc_types.h -* @brief Contains the NXP ABL typedefs for C standard types. -* It is intended to be used in ISO C conforming development -* environments and checks for this insofar as it is possible -* to do so. -* @version 2.0 -* @date 27 July. 2008 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2008, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ - -/* Type group ----------------------------------------------------------- */ -/** @defgroup LPC_Types LPC_Types - * @ingroup LPC1700CMSIS_FwLib_Drivers - * @{ - */ - -#ifndef LPC_TYPES_H -#define LPC_TYPES_H - -/* Includes ------------------------------------------------------------------- */ -#include - - -/* Public Types --------------------------------------------------------------- */ -/** @defgroup LPC_Types_Public_Types LPC_Types Public Types - * @{ - */ - -/** - * @brief Boolean Type definition - */ -typedef enum {FALSE = 0, TRUE = !FALSE} Bool; - -/** - * @brief Flag Status and Interrupt Flag Status type definition - */ -typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState; -#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET)) - -/** - * @brief Functional State Definition - */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE)) - -/** - * @ Status type definition - */ -typedef enum {ERROR = 0, SUCCESS = !ERROR} Status; - - -/** - * Read/Write transfer type mode (Block or non-block) - */ -typedef enum -{ - NONE_BLOCKING = 0, /**< None Blocking type */ - BLOCKING /**< Blocking type */ -} TRANSFER_BLOCK_Type; - - -/** Pointer to Function returning Void (any number of parameters) */ -typedef void (*PFV)(); - -/** Pointer to Function returning int32_t (any number of parameters) */ -typedef int32_t(*PFI)(); - -/** - * @} - */ - - -/* Public Macros -------------------------------------------------------------- */ -/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros - * @{ - */ - -/* _BIT(n) sets the bit at position "n" - * _BIT(n) is intended to be used in "OR" and "AND" expressions: - * e.g., "(_BIT(3) | _BIT(7))". - */ -#undef _BIT -/* Set bit macro */ -#define _BIT(n) (1< = (any_expression) & _BITMASK(x), where 0 < x <= 32. - * If "any_expression" results in a value that is larger than can be - * contained in 'x' bits, the bits above 'x - 1' are masked off. When - * used with the _SBF example above, the example would be written: - * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16)) - * This ensures that the value written to a_reg is no wider than - * 16 bits, and makes the code easier to read and understand. - */ -#undef _BITMASK -/* Bitmask creation macro */ -#define _BITMASK(field_width) ( _BIT(field_width) - 1) - -/* NULL pointer */ -#ifndef NULL -#define NULL ((void*) 0) -#endif - -/* Number of elements in an array */ -#define NELEMENTS(array) (sizeof (array) / sizeof (array[0])) - -/* Static data/function define */ -#define STATIC static -/* External data/function define */ -#define EXTERN extern - -#if !defined(MAX) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -#if !defined(MIN) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -/** - * @} - */ - - -/* Old Type Definition compatibility ------------------------------------------ */ -/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types - * @{ - */ - -/** SMA type for character type */ -typedef char CHAR; - -/** SMA type for 8 bit unsigned value */ -typedef uint8_t UNS_8; - -/** SMA type for 8 bit signed value */ -typedef int8_t INT_8; - -/** SMA type for 16 bit unsigned value */ -typedef uint16_t UNS_16; - -/** SMA type for 16 bit signed value */ -typedef int16_t INT_16; - -/** SMA type for 32 bit unsigned value */ -typedef uint32_t UNS_32; - -/** SMA type for 32 bit signed value */ -typedef int32_t INT_32; - -/** SMA type for 64 bit signed value */ -typedef int64_t INT_64; - -/** SMA type for 64 bit unsigned value */ -typedef uint64_t UNS_64; - -/** 32 bit boolean type */ -typedef Bool BOOL_32; - -/** 16 bit boolean type */ -typedef Bool BOOL_16; - -/** 8 bit boolean type */ -typedef Bool BOOL_8; - -/** - * @} - */ - - -#endif /* LPC_TYPES_H */ - -/** - * @} - */ - -/* --------------------------------- End Of File ------------------------------ */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/Makefile cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/Makefile --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/Makefile 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,123 +0,0 @@ -CPU := Cortex-M3 -CPU_MODE := thumb -TARGET_PLATFORM :=armcc_$(CPU)_$(CPU_MODE) - -CPPUTEST_HOME := ../../.. - -# имя компонента -COMPONENT_NAME := Startup_LPC1768 - -# промежуточный каталог, где производится компиляция startup-файлов -OBJS_DIR = objs - -# каталог с библиотекой` -LIB_DIR := $(CPPUTEST_HOME)/lib/$(TARGET_PLATFORM) - -# каталог с файлами приложения -SRC_DIRS := . - -# каталог с заголовочными файлами -INCLUDE_DIRS := . - -# CYGWIN path -CYGWIN :=C:/CYGWIN/bin -MKDIR :=@$(CYGWIN)/mkdir -RM :=@$(CYGWIN)/rm -TOUCH :=@$(CYGWIN)/touch -ECHO :=@$(CYGWIN)/echo - -KEIL_DIR:=D:/Keil/ARM/ARMCC -CC:=@$(KEIL_DIR)/bin/armcc.exe -AS:=@$(KEIL_DIR)/bin/armasm.exe -AR:=@$(KEIL_DIR)/bin/armar.exe -# armcc system include path -SYS_INCLUDE_DIRS :=$(KEIL_DIR)/include - -# добавление системных заголовочных файлов для сборки CRT библиотеки -INCLUDE_DIRS +=$(SYS_INCLUDE_DIRS) - -CPUFLAGS :=--cpu=$(CPU) -ifeq ($(CPU_MODE), thumb) - CPUFLAGS +=--apcs=/interwork -endif -DEPFLAGS =-M $(INCLUDES) --depend_format=unix_escaped --depend_single_line --no_depend_system_headers -OPTFLAGS :=-O3 -CPPUTEST_CPPFLAGS =$(CPUFLAGS) $(OPTFLAGS) -c -g $(INCLUDES) \ - --$(CPU_MODE) \ - -D__CLK_TCK=1000 \ - -D__UART0 \ - -ARFLAGS := --debug_symbols - - -TARGET_LIB := \ - $(LIB_DIR)/lib$(COMPONENT_NAME).a - -#Helper Functions -get_src_from_dir = $(wildcard $1/*.c) $(wildcard $1/*.asm) -get_src_from_dir_list = $(foreach dir, $1, $(call get_src_from_dir,$(dir))) -__src_to = $(subst .asm,$1, $(subst .c,$1,$2)) -src_to = $(addprefix $3/,$(call __src_to,$1,$2)) -src_to_o = $(call src_to,.o,$1,$2) -src_to_d = $(call src_to,.d,$1,$2) -time = $(shell date +%s) -delta_t = $(eval minus, $1, $2) -debug_print_list = $(foreach word,$1,$(ECHO) " $(word)";) $(ECHO) - -# for building CRT library -SRC := $(call get_src_from_dir_list, $(SRC_DIRS)) -OBJ := $(call src_to_o,$(SRC),$(OBJS_DIR)) -INCLUDES += $(foreach dir, $(INCLUDE_DIRS), -I$(dir)) -DEP_FILES := $(call src_to_d, $(SRC), $(OBJS_DIR)) -STUFF_TO_CLEAN := $(OBJ) $(DEP_FILES) - -#Don't create CRT dependencies when we're cleaning, for instance -ifeq (0, $(words $(findstring $(MAKECMDGOALS), $(NODEPS)))) - -include $(DEP_FILES) -endif - -$(TARGET_LIB): $(OBJ) | $(LIB_DIR) - $(AR) $(ARFLAGS) --create $@ $^ - $(ECHO) Build CRT library done! - -.PHONY: crt -crt: - $(ECHO) - $(ECHO) CRT =$(CRT) - $(ECHO) SRC =$(SRC) - $(ECHO) OBJ =$(OBJ) - $(ECHO) INCLUDES =$(INCLUDES) - $(ECHO) DEP_FILES =$(DEP_FILES) - $(ECHO) STUFF_TO_CLEAN =$(STUFF_TO_CLEAN) - $(ECHO) OBJS_DIR =$(OBJS_DIR) - -$(LIB_DIR) $(OBJS_DIR): - $(ECHO) Updating directory $@ - $(MKDIR) -p $@ - -#This is the rule for creating the dependency files -$(OBJS_DIR)/%.d: %.c Makefile | $(OBJS_DIR) - $(ECHO) Compiling C file $< for dependency. Out file $@. - $(CC) $(DEPFLAGS) $< --depend=$@ --depend_target='$(patsubst %.d,%.o,$@)' - -$(OBJS_DIR)/%.d: %.asm | $(OBJS_DIR) - $(ECHO) Compiling ASM file $< for dependency. Out file $@. - $(TOUCH) $@ - -#This rule does the compilation C files -$(OBJS_DIR)/%.o: %.c $(OBJS_DIR)/%.d - $(ECHO) Compiling C file $<. Out file $@ - $(CC) $(CPPUTEST_CPPFLAGS) $< -o $@ - -#This rule does the compilation ASM -$(OBJS_DIR)/%.o: %.asm $(OBJS_DIR)/%.d - $(ECHO) Assembling file $<. Out file $@ - $(AS) $(CPUFLAGS) --diag-suppress 1786 $< -o $@ - - -clean: - @$(RM) -f $(STUFF_TO_CLEAN) - - -all: $(TARGET_LIB) - $(ECHO) Done! diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/README cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/README --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/README 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/README 1970-01-01 00:00:00.000000000 +0000 @@ -1,19 +0,0 @@ -Startup library for ARM C/C++ compiler and LPC1768 chip. -Semihosting is in use, so you may use standard printf() or std::cout << "Hello!" - -Requirements: -1. CYGWIN (rm.exe, mkdir.exe, make.exe, echo.exe) -2. Keil MDK-ARM - -Library libStartup_LPC1768.a is placed in ./lib/armcc_Cortex-M3_thumb - directory of home CppUTest directory. - -Time measure is done using LPC_TIM3. -Because of calling _clock_init() before main() by startup code, value of - SystemCoreClock is 0, and it is need to manually call _clock_init() in main() - or other place after updating SystemCoreClock. - It come from two quartz selection in system_LPC17xx.c, non-standard solution - of startup initialization. - To remove _clock_init() call from main(), you need to remove two quartz - configuration in system_LPC17xx.c and declare SystemCoreClock variable as - "const" with value of real clock frequency. diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/Retarget.c cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/Retarget.c --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/Retarget.c 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/Retarget.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,153 +0,0 @@ -/*---------------------------------------------------------------------------- - * Name: Retarget.c - * Purpose: 'Retarget' layer for target-dependent low level functions - * Note(s): - *---------------------------------------------------------------------------- - * This file is part of the uVision/ARM development tools. - * This software may only be used under the terms of a valid, current, - * end user licence from KEIL for a compatible version of KEIL software - * development tools. Nothing else gives you the right to use this software. - * - * This software is supplied "AS IS" without warranties of any kind. - * - * Copyright (c) 2011 Keil - An ARM Company. All rights reserved. - *----------------------------------------------------------------------------*/ - -#include -#include -#include -#include "Serial.h" -#include "lpc17xx_timer.h" - -/* Standard IO device handles. */ -#define STDIN 0x8001 -#define STDOUT 0x8002 -#define STDERR 0x8003 - - -#pragma import(__use_no_semihosting_swi) - -const char __stdin_name[] = "STDIN"; -const char __stdout_name[] = "STDOUT"; -const char __stderr_name[] = "STDERR"; - - -FILEHANDLE _sys_open(const char *name, int openmode) -{ - FILEHANDLE rc; - /* Register standard Input Output devices. */ - if (strcmp(name, "STDIN") == 0) rc = STDIN; - else if (strcmp(name, "STDOUT") == 0) rc = STDOUT; - else if (strcmp(name, "STDERR") == 0) rc = STDERR; - else rc = 1; - return (rc); -} - -int _sys_close(FILEHANDLE fh) -{ - return 0; -} - -int _sys_write(FILEHANDLE fh, const unsigned char *buf, - unsigned len, int mode) -{ - while (len) { - SER_PutChar(*buf); - buf++; - len--; - } - return len; -} - -int _sys_read(FILEHANDLE fh, unsigned char *buf, - unsigned len, int mode) -{ - return -1; /* not supported */ -} - -void _ttywrch(int ch) -{ - SER_PutChar(ch); -} - -int _sys_istty(FILEHANDLE fh) -{ - return 0; /* buffered output */ -} - -int _sys_seek(FILEHANDLE fh, long pos) -{ - return -1; /* not supported */ -} - -long _sys_flen(FILEHANDLE fh) -{ - return -1; /* not supported */ -} - -void _sys_exit(int return_code) { - while(1); -} - -char *_sys_command_string(char *cmd, int len) -{ - const char * const arg[] = { - "tst.axf", - "-v", - "-gSimpleStringBuffer", - "-ojunit"}; - int i, j; - char *rc = cmd; - if (len) { - /* Specify commandline arguments here as needed */ - len = sizeof(arg) / sizeof(char *); - for (i = 0; i < len; i++) { - j = strlen(arg[i])+1; - if (cmd - rc + j > len) { - rc = NULL; - break; - } - memcpy(cmd, arg[i], j); - cmd += j; - } - if (rc) rc = cmd; - } else rc = NULL; - return rc; -} - -void _clock_init(void) -{ - const TIM_TIMERCFG_Type config_us_timer = {TIM_PRESCALE_USVAL, {0,0,0}, 1000}; /* 1000 us for one timer tick */ - TIM_Init(LPC_TIM3, TIM_TIMER_MODE, (void *)&config_us_timer); /* TIMER3 for counting 1 ms */ - TIM_Cmd(LPC_TIM3, ENABLE); -} - -clock_t clock(void) -{ - return LPC_TIM3->TC; -} - -time_t time(time_t *timer) -{ - return 0; -} - - - -/* - * Замена встроенной в Keil MDK-ARM функции, которая создаёт связанный список - * адресов деструкторов глобальных или статических объектов в "куче" при - * инициализации окружения. - * Так как не планируется завершение программы, то ни один такой деструктор не - * должен вызываться, и можно подменить стандартную версию __aeabi_atexit на - * другую, которая не будет создавать такой список в "куче". - * Идея взята отсюда - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka3951.html - * Пример реализации взят отсюда - * http://infocenter.arm.com/help/topic/com.arm.doc.ihi0041d/IHI0041D_cppabi.pdf - */ -int __aeabi_atexit(void* object, void (*destroyer)(void*), void* dso_handle) -{ - return 1; // 0: failed; non-0: OK -// return __cxa_atexit(destroyer, object, dso_handle); /* стандартная версия из Keil MDK-ARM */ -} diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/Serial.c cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/Serial.c --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/Serial.c 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/Serial.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,82 +0,0 @@ -/*------------------------------------------------------------------------------ - * RL-ARM - *------------------------------------------------------------------------------ - * Name: Serial.c - * Purpose: Serial Input Output for NXP LPC17xx - * Note(s): Possible defines to select the used communication interface: - * __UART0 - COM0 (UART0) interface - * - COM1 (UART1) interface (default) - *------------------------------------------------------------------------------ - * This code is part of the RealView Run-Time Library. - * Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved. - *----------------------------------------------------------------------------*/ - -#include -#include "Serial.h" - -#ifdef __UART0 - #define UART LPC_UART0 -#else - #define UART LPC_UART1 -#endif - -static int init_UART_done = 0; - - -/*------------------------------------------------------------------------------ - * SER_Init: Initialize Serial Interface - *----------------------------------------------------------------------------*/ - -void SER_Init (void) { - -#ifdef __UART0 /* UART0 */ - LPC_SC->PCONP |= ((1 << 3) | (1 << 15)); /* enable power to UART0 & IOCON */ - - LPC_PINCON->PINSEL0 |= (1 << 4); /* Pin P0.2 used as TXD0 */ - LPC_PINCON->PINSEL0 |= (1 << 6); /* Pin P0.3 used as RXD0 */ -#else /* UART1 */ - LPC_SC->PCONP |= ((1 << 4) | (1 << 15)); /* enable power to UART1 & IOCON */ - - LPC_PINCON->PINSEL4 |= (2 << 0); /* Pin P2.0 used as TXD1 */ - LPC_PINCON->PINSEL4 |= (2 << 2); /* Pin P2.1 used as RXD1 */ -#endif - - UART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */ - UART->DLL = 9; /* 115200 Baud Rate @ 25.0 MHZ PCLK*/ - UART->FDR = 0x21; /* FR 1,507, DIVADDVAL=1, MULVAL=2 */ - UART->DLM = 0; /* High divisor latch = 0 */ - UART->LCR = 0x03; /* DLAB = 0 */ -} - - -/*------------------------------------------------------------------------------ - * SER_PutChar: Write a character to the Serial Port - *----------------------------------------------------------------------------*/ - -int32_t SER_PutChar (int32_t ch) { - - if (init_UART_done == 0) { - SER_Init(); - init_UART_done++; - } - while (!(UART->LSR & 0x20)); - UART->THR = ch; - return (ch); -} - - -/*------------------------------------------------------------------------------ - * SER_GetChar: Read a character from the Serial Port (non-blocking) - *----------------------------------------------------------------------------*/ - -int32_t SER_GetChar (void) { - - if (UART->LSR & 0x01) - return (UART->RBR); - return (-1); -} - - -/*------------------------------------------------------------------------------ - * End of file - *----------------------------------------------------------------------------*/ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/Serial.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/Serial.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/Serial.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/Serial.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,24 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: Serial.h - * Purpose: Serial I/O definitions - *----------------------------------------------------------------------------- - * This file is part of the uVision/ARM development tools. - * This software may only be used under the terms of a valid, current, - * end user licence from KEIL for a compatible version of KEIL software - * development tools. Nothing else gives you the right to use this software. - * - * This software is supplied "AS IS" without warranties of any kind. - * - * Copyright (c) 2004-2012 Keil - An ARM Company. All rights reserved. - *----------------------------------------------------------------------------*/ - -#ifndef __SERIAL_H -#define __SERIAL_H - -#include - -extern void SER_Init (void); -extern int32_t SER_GetChar (void); -extern int32_t SER_PutChar (int32_t ch); - -#endif /* __SERIAL_H */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/startup_LPC17xx.asm cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/startup_LPC17xx.asm --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/startup_LPC17xx.asm 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/startup_LPC17xx.asm 1970-01-01 00:00:00.000000000 +0000 @@ -1,281 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC17xx.s -; * @purpose: CMSIS Cortex-M3 Core Device Startup File -; * for the NXP LPC17xx Device Series -; * @version: V1.20 -; * @date: 07. October 2010 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2010 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00002000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00006000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, CODE, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; External Interrupts - DCD WDT_IRQHandler ; 16: Watchdog Timer - DCD TIMER0_IRQHandler ; 17: Timer0 - DCD TIMER1_IRQHandler ; 18: Timer1 - DCD TIMER2_IRQHandler ; 19: Timer2 - DCD TIMER3_IRQHandler ; 20: Timer3 - DCD UART0_IRQHandler ; 21: UART0 - DCD UART1_IRQHandler ; 22: UART1 - DCD UART2_IRQHandler ; 23: UART2 - DCD UART3_IRQHandler ; 24: UART3 - DCD PWM1_IRQHandler ; 25: PWM1 - DCD I2C0_IRQHandler ; 26: I2C0 - DCD I2C1_IRQHandler ; 27: I2C1 - DCD I2C2_IRQHandler ; 28: I2C2 - DCD SPI_IRQHandler ; 29: SPI - DCD SSP0_IRQHandler ; 30: SSP0 - DCD SSP1_IRQHandler ; 31: SSP1 - DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) - DCD RTC_IRQHandler ; 33: Real Time Clock - DCD EINT0_IRQHandler ; 34: External Interrupt 0 - DCD EINT1_IRQHandler ; 35: External Interrupt 1 - DCD EINT2_IRQHandler ; 36: External Interrupt 2 - DCD EINT3_IRQHandler ; 37: External Interrupt 3 - DCD ADC_IRQHandler ; 38: A/D Converter - DCD BOD_IRQHandler ; 39: Brown-Out Detect - DCD USB_IRQHandler ; 40: USB - DCD CAN_IRQHandler ; 41: CAN - DCD DMA_IRQHandler ; 42: General Purpose DMA - DCD I2S_IRQHandler ; 43: I2S - DCD ENET_IRQHandler ; 44: Ethernet - DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer - DCD MCPWM_IRQHandler ; 46: Motor Control PWM - DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface - DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup - DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup - - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WDT_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT SPI_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT PLL0_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT EINT0_IRQHandler [WEAK] - EXPORT EINT1_IRQHandler [WEAK] - EXPORT EINT2_IRQHandler [WEAK] - EXPORT EINT3_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - EXPORT CAN_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT I2S_IRQHandler [WEAK] - EXPORT ENET_IRQHandler [WEAK] - EXPORT RIT_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - EXPORT PLL1_IRQHandler [WEAK] - EXPORT USBActivity_IRQHandler [WEAK] - EXPORT CANActivity_IRQHandler [WEAK] - -WDT_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -PWM1_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -SPI_IRQHandler -SSP0_IRQHandler -SSP1_IRQHandler -PLL0_IRQHandler -RTC_IRQHandler -EINT0_IRQHandler -EINT1_IRQHandler -EINT2_IRQHandler -EINT3_IRQHandler -ADC_IRQHandler -BOD_IRQHandler -USB_IRQHandler -DMA_IRQHandler -CAN_IRQHandler -I2S_IRQHandler -ENET_IRQHandler -RIT_IRQHandler -MCPWM_IRQHandler -QEI_IRQHandler -PLL1_IRQHandler -USBActivity_IRQHandler -CANActivity_IRQHandler - - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_setup_stackheap -__user_setup_stackheap - - LDR R0, = Heap_Mem - LDR R2, = (Heap_Mem + Heap_Size) - LDR SP, =(Stack_Mem + Stack_Size) - BX LR - - ALIGN - - ENDIF - - - END diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/system_LPC17xx.c cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/system_LPC17xx.c --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/system_LPC17xx.c 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/system_LPC17xx.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,642 +0,0 @@ -/**************************************************************************//** - * @file system_LPC17xx.c - * @brief CMSIS Cortex-M3 Device System Source File for - * NXP LPC17xx Device Series - * @version V1.13 - * @date 18. April 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#include -#include "LPC17xx.h" - -/** @addtogroup LPC17xx_System - * @{ - */ - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration---------------- -// -// Clock Configuration -// System Controls and Status Register (SCS) with quartz 24 MHz -// OSCRANGE: Main Oscillator Range Select -// <0=> 1 MHz to 20 MHz -// <1=> 15 MHz to 25 MHz -// OSCEN: Main Oscillator Enable -// -// -// -// System Controls and Status Register (SCS) with quartz 12 MHz -// OSCRANGE: Main Oscillator Range Select -// <0=> 1 MHz to 20 MHz -// <1=> 15 MHz to 25 MHz -// OSCEN: Main Oscillator Enable -// -// - -// PLL0 Configuration (Main PLL) -// PLL0 Configuration Register (PLL0CFG) with quartz 24 MHz -// F_cco0 = (2 * M * F_in) / N -// F_in must be in the range of 32 kHz to 50 MHz -// F_cco0 must be in the range of 275 MHz to 550 MHz -// MSEL: PLL Multiplier Selection -// <6-32768><#-1> -// M Value -// NSEL: PLL Divider Selection -// <1-256><#-1> -// N Value -// -// PLL0 Configuration Register (PLL0CFG) with quartz 12 MHz -// F_cco0 = (2 * M * F_in) / N -// F_in must be in the range of 32 kHz to 50 MHz -// F_cco0 must be in the range of 275 MHz to 550 MHz -// MSEL: PLL Multiplier Selection -// <6-32768><#-1> -// M Value -// NSEL: PLL Divider Selection -// <1-256><#-1> -// N Value -// -// -// -// PLL1 Configuration (USB PLL) -// PLL1 Configuration Register (PLL1CFG) with quartz 24 MHz -// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) -// F_cco1 = F_osc * M * 2 * P -// F_cco1 must be in the range of 156 MHz to 320 MHz -// MSEL: PLL Multiplier Selection -// <1-32><#-1> -// M Value (for USB maximum value is 4) -// PSEL: PLL Divider Selection -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// P Value -// -// PLL1 Configuration Register (PLL1CFG) with quartz 12 MHz -// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) -// F_cco1 = F_osc * M * 2 * P -// F_cco1 must be in the range of 156 MHz to 320 MHz -// MSEL: PLL Multiplier Selection -// <1-32><#-1> -// M Value (for USB maximum value is 4) -// PSEL: PLL Divider Selection -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// P Value -// -// -// -// CPU Clock Configuration Register (CCLKCFG) -// CCLKSEL: Divide Value for CPU Clock from PLL0 -// <1-256><#-1> -// -// -// USB Clock Configuration Register (USBCLKCFG) -// USBSEL: Divide Value for USB Clock from PLL0 -// <0-15> -// Divide is USBSEL + 1 -// -// -// Clock Source Select Register (CLKSRCSEL) -// CLKSRC: PLL Clock Source Selection -// <0=> Internal RC oscillator -// <1=> Main oscillator -// <2=> RTC oscillator -// -// -// Peripheral Clock Selection Register 0 (PCLKSEL0) -// PCLK_WDT: Peripheral Clock Selection for WDT -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_UART0: Peripheral Clock Selection for UART0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_UART1: Peripheral Clock Selection for UART1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_PWM1: Peripheral Clock Selection for PWM1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_I2C0: Peripheral Clock Selection for I2C0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_SPI: Peripheral Clock Selection for SPI -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_SSP1: Peripheral Clock Selection for SSP1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_DAC: Peripheral Clock Selection for DAC -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_ADC: Peripheral Clock Selection for ADC -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_CAN1: Peripheral Clock Selection for CAN1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 6 -// PCLK_CAN2: Peripheral Clock Selection for CAN2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 6 -// PCLK_ACF: Peripheral Clock Selection for ACF -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 6 -// -// -// Peripheral Clock Selection Register 1 (PCLKSEL1) -// PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_GPIO: Peripheral Clock Selection for GPIOs -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_I2C1: Peripheral Clock Selection for I2C1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_SSP0: Peripheral Clock Selection for SSP0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_UART2: Peripheral Clock Selection for UART2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_UART3: Peripheral Clock Selection for UART3 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_I2C2: Peripheral Clock Selection for I2C2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_I2S: Peripheral Clock Selection for I2S -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_SYSCON: Peripheral Clock Selection for the System Control Block -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// PCLK_MC: Peripheral Clock Selection for the Motor Control PWM -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Cclk / 8 -// -// -// Power Control for Peripherals Register (PCONP) -// PCTIM0: Timer/Counter 0 power/clock enable -// PCTIM1: Timer/Counter 1 power/clock enable -// PCUART0: UART 0 power/clock enable -// PCUART1: UART 1 power/clock enable -// PCPWM1: PWM 1 power/clock enable -// PCI2C0: I2C interface 0 power/clock enable -// PCSPI: SPI interface power/clock enable -// PCRTC: RTC power/clock enable -// PCSSP1: SSP interface 1 power/clock enable -// PCAD: A/D converter power/clock enable -// PCCAN1: CAN controller 1 power/clock enable -// PCCAN2: CAN controller 2 power/clock enable -// PCGPIO: GPIOs power/clock enable -// PCRIT: Repetitive interrupt timer power/clock enable -// PCMC: Motor control PWM power/clock enable -// PCQEI: Quadrature encoder interface power/clock enable -// PCI2C1: I2C interface 1 power/clock enable -// PCSSP0: SSP interface 0 power/clock enable -// PCTIM2: Timer 2 power/clock enable -// PCTIM3: Timer 3 power/clock enable -// PCUART2: UART 2 power/clock enable -// PCUART3: UART 3 power/clock enable -// PCI2C2: I2C interface 2 power/clock enable -// PCI2S: I2S interface power/clock enable -// PCGPDMA: GP DMA function power/clock enable -// PCENET: Ethernet block power/clock enable -// PCUSB: USB interface power/clock enable -// -// -// Clock Output Configuration Register (CLKOUTCFG) -// CLKOUTSEL: Selects clock source for CLKOUT -// <0=> CPU clock -// <1=> Main oscillator -// <2=> Internal RC oscillator -// <3=> USB clock -// <4=> RTC oscillator -// CLKOUTDIV: Selects clock divider for CLKOUT -// <1-16><#-1> -// CLKOUT_EN: CLKOUT enable control -// -// -// -*/ - - - -/** @addtogroup LPC17xx_System_Defines LPC17xx System Defines - @{ - */ - -#define CLOCK_SETUP 1 -#define SCS_24_Val 0x00000030 -#define SCS_12_Val 0x00000020 -#define PLL0_SETUP 1 -#define PLL0CFG_24_Val 0x00030018 -#define PLL0CFG_12_Val 0x00010018 -#define PLL1_SETUP 1 -#define PLL1CFG_24_Val 0x00000021 -#define PLL1CFG_12_Val 0x00000023 -#define CCLKCFG_Val 0x00000002 -#define USBCLKCFG_Val 0x00000001 -#define CLKSRCSEL_Val 0x00000001 -#define PCLKSEL0_Val 0x08000000 -#define PCLKSEL1_Val 0x00000000 -#define PCONP_Val 0x4000A00E -#define CLKOUTCFG_Val 0x00000110 - - -/*--------------------- Flash Accelerator Configuration ---------------------- -// -// Flash Accelerator Configuration -// FLASHTIM: Flash Access Time -// <0=> 1 CPU clock (for CPU clock up to 20 MHz) -// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) -// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) -// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) -// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) -// <5=> 6 CPU clocks (for any CPU clock) -// -*/ -#define FLASH_SETUP 1 -#define FLASHCFG_Val 0x00004000 - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SCS_12_Val), ~0x00000030)) - #error "SCS_12: Invalid values of reserved bits!" -#endif -#if (CHECK_RSVD((SCS_24_Val), ~0x00000030)) - #error "SCS_24: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) - #error "CLKSRCSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((PLL0CFG_12_Val), ~0x00FF7FFF)) - #error "PLL0CFG_12: Invalid values of reserved bits!" -#endif -#if (CHECK_RSVD((PLL0CFG_24_Val), ~0x00FF7FFF)) - #error "PLL0CFG_24: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PLL1CFG_12_Val), ~0x0000007F)) - #error "PLL1CFG_12: Invalid values of reserved bits!" -#endif -#if (CHECK_RSVD((PLL1CFG_24_Val), ~0x0000007F)) - #error "PLL1CFG_24: Invalid values of reserved bits!" -#endif - -#if (PLL0_SETUP) /* if PLL0 is used */ - #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */ - #error "CCLKCFG_24: CCLKSEL must be greater then 1 if PLL0 is used!" - #endif -#endif - -#if (CHECK_RANGE((CCLKCFG_Val), 0, 255)) - #error "CCLKCFG_24: Value out of range!" -#endif - -#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) - #error "USBCLKCFG_24: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) - #error "PCLKSEL0: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) - #error "PCLKSEL1: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCONP_Val), 0x10100821)) - #error "PCONP: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) - #error "CLKOUTCFG: Invalid values of reserved bits!" -#endif - -/* Flash Accelerator Configuration -------------------------------------------*/ -#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) - #error "FLASHCFG: Invalid values of reserved bits!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL_24 (24000000UL) /* Oscillator frequency */ -#define XTAL_12 (12000000UL) /* Oscillator frequency */ -#define OSC_CLK_24 ( XTAL_24) /* Main oscillator frequency */ -#define OSC_CLK_12 ( XTAL_12) /* Main oscillator frequency */ -#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */ -#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ - - -/* F_cco0 = (2 * M * F_in) / N */ -#define __M_24 (((PLL0CFG_24_Val ) & 0x7FFF) + 1) -#define __M_12 (((PLL0CFG_12_Val ) & 0x7FFF) + 1) -#define __N_24 (((PLL0CFG_24_Val >> 16) & 0x00FF) + 1) -#define __N_12 (((PLL0CFG_12_Val >> 16) & 0x00FF) + 1) -#define __FCCO_24(__F_IN) ((2ULL * __M_24 * __F_IN) / __N_24) -#define __FCCO_12(__F_IN) ((2ULL * __M_12 * __F_IN) / __N_12) -#define __CCLK_DIV_24 (((CCLKCFG_Val ) & 0x00FF) + 1) -#define __CCLK_DIV_12 (((CCLKCFG_Val ) & 0x00FF) + 1) - -/* Determine core clock frequency according to settings */ - #if (PLL0_SETUP) - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK_24 (__FCCO_24(OSC_CLK_24) / __CCLK_DIV_24) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK_24 (__FCCO_24(RTC_CLK) / __CCLK_DIV_24) - #else - #define __CORE_CLK_24 (__FCCO_24(IRC_OSC) / __CCLK_DIV_24) - #endif - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK_12 (__FCCO_12(OSC_CLK_12) / __CCLK_DIV_12) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK_12 (__FCCO_12(RTC_CLK) / __CCLK_DIV_12) - #else - #define __CORE_CLK_12 (__FCCO_12(IRC_OSC) / __CCLK_DIV_12) - #endif - #else - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK_24 (OSC_CLK_24 / __CCLK_DIV_24) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK_24 (RTC_CLK / __CCLK_DIV_24) - #else - #define __CORE_CLK_24 (IRC_OSC / __CCLK_DIV_24) - #endif - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK_12 (OSC_CLK_12 / __CCLK_DIV_12) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK_12 (RTC_CLK / __CCLK_DIV_12) - #else - #define __CORE_CLK_12 (IRC_OSC / __CCLK_DIV_12) - #endif - #endif - - /** - * @} - */ - - -/** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables - @{ - */ -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ -const uint32_t SystemCoreClock12 = __CORE_CLK_12; /*!< System Clock Frequency (Core Clock)*/ -const uint32_t SystemCoreClock24 = __CORE_CLK_24; /*!< System Clock Frequency (Core Clock)*/ - -/** - * @} - */ - - -/** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions - @{ - */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - * Запрещено использовать любые вызовы, использующие указатель стека (т.к. стек ещё не проинициализирован) - */ -void SystemInit (void) -{ - if (1) { /* for 12 MHz Quartz */ -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_12_Val; - if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ - /* Periphral clock must be selected before PLL0 enabling and connecting - * - according errata.lpc1768-16.March.2010 - - */ - LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ - LPC_SC->PCLKSEL1 = PCLKSEL1_Val; - - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source sysclk / PLL0 */ - -#if (PLL0_SETUP) - LPC_SC->PLL0CFG = PLL0CFG_12_Val; /* configure PLL0 */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - - LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ - - LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while ((LPC_SC->PLL0STAT & ((1<<25) | (1<<24))) != ((1<<25) | (1<<24))); /* Wait for PLLC0_STAT & PLLE0_STAT */ -#endif - -#if (PLL1_SETUP) - LPC_SC->PLL1CFG = PLL1CFG_12_Val; - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - - LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ - - LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while ((LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))) != ((1<< 9) | (1<< 8))); /* Wait for PLLC1_STAT & PLLE1_STAT */ -#else - LPC_SC->USBCLKCFG = USBCLKCFG_12_Val; /* Setup USB Clock Divider */ -#endif - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - - LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val; -#endif - } else { /* for 24 MGz Quartz */ -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_24_Val; - if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ - /* Periphral clock must be selected before PLL0 enabling and connecting - * - according errata.lpc1768-16.March.2010 - - */ - LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ - LPC_SC->PCLKSEL1 = PCLKSEL1_Val; - - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source sysclk / PLL0 */ - -#if (PLL0_SETUP) - LPC_SC->PLL0CFG = PLL0CFG_24_Val; /* configure PLL0 */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - - LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ - - LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while ((LPC_SC->PLL0STAT & ((1<<25) | (1<<24))) != ((1<<25) | (1<<24))); /* Wait for PLLC0_STAT & PLLE0_STAT */ -#endif - -#if (PLL1_SETUP) - LPC_SC->PLL1CFG = PLL1CFG_24_Val; - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - - LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ - - LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while ((LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))) != ((1<< 9) | (1<< 8))); /* Wait for PLLC1_STAT & PLLE1_STAT */ -#else - LPC_SC->USBCLKCFG = USBCLKCFG_24_Val; /* Setup USB Clock Divider */ -#endif - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - - LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val; -#endif - } -} diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1768/system_LPC17xx.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/system_LPC17xx.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1768/system_LPC17xx.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1768/system_LPC17xx.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,72 +0,0 @@ -/**************************************************************************//** - * @file system_LPC17xx.h - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File - * for the NXP LPC17xx Device Series - * @version V1.02 - * @date 08. September 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC17xx_H -#define __SYSTEM_LPC17xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** @addtogroup LPC17xx_System - * @{ - */ - - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* __SYSTEM_LPC17xx_H */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1833/cmsis_18xx.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/cmsis_18xx.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1833/cmsis_18xx.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/cmsis_18xx.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,152 +0,0 @@ -/* - * @brief Basic CMSIS include file for LPC18XX - * - * @note - * Copyright(C) NXP Semiconductors, 2013 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __CMSIS_18XX_H_ -#define __CMSIS_18XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup CMSIS_18XX CHIP: LPC18xx CMSIS include file - * @ingroup CHIP_18XX_43XX_Drivers - * @{ - */ - - #pragma diag_suppress 2525 - #pragma push - #pragma anon_unions - -/** @defgroup CMSIS_18XX_COMMON CHIP: LPC18xx Cortex CMSIS definitions - * @{ - */ - -#define __CM3_REV 0x0201 -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0 /*!< FPU present or not */ - -/** - * @} - */ - -/** @defgroup CMSIS_18XX_IRQ CHIP: LPC18xx peripheral interrupt numbers - * @{ - */ - -typedef enum { - /* ------------------------- Cortex-M3 Processor Exceptions Numbers ----------------------------- */ - Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ - - /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */ - DAC_IRQn = 0,/*!< 0 DAC */ - RESERVED0_IRQn = 1, - DMA_IRQn = 2,/*!< 2 DMA */ - RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */ - RESERVED2_IRQn = 4, - ETHERNET_IRQn = 5,/*!< 5 ETHERNET */ - SDIO_IRQn = 6,/*!< 6 SDIO */ - LCD_IRQn = 7,/*!< 7 LCD */ - USB0_IRQn = 8,/*!< 8 USB0 */ - USB1_IRQn = 9,/*!< 9 USB1 */ - SCT_IRQn = 10,/*!< 10 SCT */ - RITIMER_IRQn = 11,/*!< 11 RITIMER */ - TIMER0_IRQn = 12,/*!< 12 TIMER0 */ - TIMER1_IRQn = 13,/*!< 13 TIMER1 */ - TIMER2_IRQn = 14,/*!< 14 TIMER2 */ - TIMER3_IRQn = 15,/*!< 15 TIMER3 */ - MCPWM_IRQn = 16,/*!< 16 MCPWM */ - ADC0_IRQn = 17,/*!< 17 ADC0 */ - I2C0_IRQn = 18,/*!< 18 I2C0 */ - I2C1_IRQn = 19,/*!< 19 I2C1 */ - RESERVED3_IRQn = 20, - ADC1_IRQn = 21,/*!< 21 ADC1 */ - SSP0_IRQn = 22,/*!< 22 SSP0 */ - SSP1_IRQn = 23,/*!< 23 SSP1 */ - USART0_IRQn = 24,/*!< 24 USART0 */ - UART1_IRQn = 25,/*!< 25 UART1 */ - USART2_IRQn = 26,/*!< 26 USART2 */ - USART3_IRQn = 27,/*!< 27 USART3 */ - I2S0_IRQn = 28,/*!< 28 I2S0 */ - I2S1_IRQn = 29,/*!< 29 I2S1 */ - RESERVED4_IRQn = 30, - RESERVED5_IRQn = 31, - PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */ - PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */ - PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */ - PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */ - PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */ - PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */ - PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */ - PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */ - GINT0_IRQn = 40,/*!< 40 GINT0 */ - GINT1_IRQn = 41,/*!< 41 GINT1 */ - EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */ - C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */ - RESERVED6_IRQn = 44, - RESERVED7_IRQn = 45,/*!< */ - ATIMER_IRQn = 46,/*!< 46 ATIMER */ - RTC_IRQn = 47,/*!< 47 RTC */ - RESERVED8_IRQn = 48, - WWDT_IRQn = 49,/*!< 49 WWDT */ - RESERVED9_IRQn = 50, - C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */ - QEI_IRQn = 52 /*!< 52 QEI */ -} LPC18XX_IRQn_Type; - -/** - * @} - */ - -typedef LPC18XX_IRQn_Type IRQn_Type; - -/* Cortex-M3 processor and core peripherals */ -#include "core_cm3.h" - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* ifndef __CMSIS_18XX_H_ */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1833/core_cm3.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/core_cm3.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1833/core_cm3.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/core_cm3.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,1550 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - - /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#include /* standard types definitions */ -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -static inline void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -static inline uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -static inline void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -static inline void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -static inline uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -static inline void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -static inline void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -static inline uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -static inline void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -static inline uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -static inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -static inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -static inline void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -static inline uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -static inline uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0) __nop(); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -static inline int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -static inline int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CMSIS_GENERIC */ - diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1833/core_cmFunc.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/core_cmFunc.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1833/core_cmFunc.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/core_cmFunc.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,312 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -static inline uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __asm("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -static inline void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __asm("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -static inline uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __asm("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -static inline uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __asm("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -static inline uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __asm("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -static inline uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __asm("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -static inline void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __asm("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -static inline uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __asm("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -static inline void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __asm("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -static inline uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __asm("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -static inline void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __asm("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -static inline uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __asm("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -static inline void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __asm("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -static inline uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __asm("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -static inline void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __asm("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -static inline uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __asm("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -static inline void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __asm("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1833/core_cmInstr.h cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/core_cmInstr.h --- cpputest-3.7.2/platforms_startup/armcc/LPC1833/core_cmInstr.h 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/core_cmInstr.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,303 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.20 - * @date 05. March 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -#pragma push -#pragma diag_suppress 667 - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) static inline __asm uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) static inline __asm int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#pragma pop - -#endif /* __CORE_CMINSTR_H */ diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1833/Makefile cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/Makefile --- cpputest-3.7.2/platforms_startup/armcc/LPC1833/Makefile 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,139 +0,0 @@ -SHELL = cmd.exe - -CPU := Cortex-M3 -CPU_MODE := thumb -TARGET_PLATFORM :=armcc_$(CPU)_$(CPU_MODE) - -CPPUTEST_HOME := ../../.. - -# имя компонента -COMPONENT_NAME := Startup_LPC1833 - -# промежуточный каталог, где производится компиляция startup-файлов -OBJS_DIR = objs - -# каталог с библиотекой` -LIB_DIR := $(CPPUTEST_HOME)/lib/$(TARGET_PLATFORM) - -# каталог с файлами приложения -SRC_DIRS := . - -# каталог с заголовочными файлами -INCLUDE_DIRS := . - -# CYGWIN path -CYGWIN :=C:/CYGWIN/bin -MKDIR :=@$(CYGWIN)/mkdir -RM :=@$(CYGWIN)/rm -TOUCH :=@$(CYGWIN)/touch - -KEIL_DIR:=D:/Keil/ARM/ARMCC -CC:=@$(KEIL_DIR)/bin/armcc.exe -AS:=@$(KEIL_DIR)/bin/armasm.exe -AR:=@$(KEIL_DIR)/bin/armar.exe -# armcc system include path -SYS_INCLUDE_DIRS :=$(KEIL_DIR)/include - -# добавление системных заголовочных файлов для сборки CRT библиотеки -INCLUDE_DIRS +=$(SYS_INCLUDE_DIRS) - -CPUFLAGS :=--cpu=$(CPU) --apcs=/interwork -DEPFLAGS =-M $(INCLUDES) --depend_format=unix_escaped --depend_single_line --no_depend_system_headers -OPTFLAGS :=-O0 -CCFLAGS =$(CPUFLAGS) \ - $(OPTFLAGS) \ - -c \ - --debug \ - $(INCLUDES) \ - --$(CPU_MODE) \ - --bss_threshold=0 \ - --strict_warnings \ - -D__CLK_TCK=1000 \ - -DCGU_IRC_FREQ=12000000 \ - -ARFLAGS := --debug_symbols - - -TARGET_LIB := \ - $(LIB_DIR)/lib$(COMPONENT_NAME).a - -#Helper Functions -get_src_from_dir = $(wildcard $1/*.c) $(wildcard $1/*.asm) -get_src_from_dir_list = $(foreach dir, $1, $(call get_src_from_dir,$(dir))) -__src_to = $(subst .asm,$1, $(subst .c,$1,$2)) -src_to = $(addprefix $3/,$(call __src_to,$1,$2)) -src_to_o = $(call src_to,.o,$1,$2) -src_to_d = $(call src_to,.d,$1,$2) -time = $(shell date +%s) -delta_t = $(eval minus, $1, $2) -debug_print_list = $(foreach word,$1,@echo " $(word)";) @echo - -# for building CRT library -SRC := $(call get_src_from_dir_list, $(SRC_DIRS)) -OBJ := $(call src_to_o,$(SRC),$(OBJS_DIR)) -INCLUDES += $(foreach dir, $(INCLUDE_DIRS), -I$(dir)) -DEP_FILES := $(call src_to_d, $(SRC), $(OBJS_DIR)) -STUFF_TO_CLEAN := $(OBJ) $(DEP_FILES) - -#Don't create CRT dependencies when we're cleaning, for instance -ifeq (0, $(words $(findstring $(MAKECMDGOALS), $(NODEPS)))) - -include $(DEP_FILES) -endif - -$(TARGET_LIB): $(OBJ) | $(LIB_DIR) - $(AR) $(ARFLAGS) --create $@ $^ - @echo Build CRT library done! - -.PHONY: crt -crt: - @echo - @echo CRT =$(CRT) - @echo SRC =$(SRC) - @echo OBJ =$(OBJ) - @echo INCLUDES =$(INCLUDES) - @echo DEP_FILES =$(DEP_FILES) - @echo STUFF_TO_CLEAN =$(STUFF_TO_CLEAN) - @echo OBJS_DIR =$(OBJS_DIR) - -$(LIB_DIR) $(OBJS_DIR): - @echo Updating directory $@ - $(MKDIR) -p $@ - -# Создание файлов зависимости для .c файлов -$(OBJS_DIR)/%.d: %.c | $(OBJS_DIR) - @echo Compiling C file $< for dependency. Out file $@. - $(CC) $(DEPFLAGS) --c99 $< --depend=$@ --depend_target='$(patsubst %.d,%.o,$@)' - -# Создание файлов зависимости для .cpp файлов -$(OBJS_DIR)/%.d: %.cpp | $(OBJS_DIR) - @echo Compiling C file $< for dependency. Out file $@. - $(CC) $(DEPFLAGS) $< --depend=$@ --depend_target='$(patsubst %.d,%.o,$@)' - -# Создание файлов зависимости для .asm файлов -$(OBJS_DIR)/%.d: %.asm | $(OBJS_DIR) - @echo Compiling ASM file $< for dependency. Out file $@. - $(TOUCH) $@ - - - -# Компиляция .asm файла -$(OBJS_DIR)/%.o: %.asm $(OBJS_DIR)/%.d - @echo Assembling file $<. Out file $@ - $(AS) $(CPUFLAGS) --keep --debug --predefine "NO_CRP SETL {TRUE}" $< -o $@ - -# Компиляция .c файла -$(OBJS_DIR)/%.o: %.c $(OBJS_DIR)/%.d - @echo Compiling C file $<. Out file $@ - $(CC) $(CCFLAGS) --c99 $< -o $@ - -# Компиляция .cpp файла -$(OBJS_DIR)/%.o: %.cpp $(OBJS_DIR)/%.d - @echo Compiling C++ file $<. Out file $@ - $(CC) $(CCFLAGS) $< -o $@ - -clean: - @$(RM) -f $(STUFF_TO_CLEAN) - - -all: $(TARGET_LIB) - @echo Done! diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1833/README cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/README --- cpputest-3.7.2/platforms_startup/armcc/LPC1833/README 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/README 1970-01-01 00:00:00.000000000 +0000 @@ -1,10 +0,0 @@ -Project for LPC1833 is based on LPCOpen. Unused functions is removed to make -a small code instead of a fat one. - -Semihosting is in use. For time measurement, SystemTimer in Cortex-M3 core is -used. Any pin is not initialized. - -Debug output is done using SWO (ITM channel 0). - -Working frequency is getting from Internal RC (12 MHz), so no PLL setup is used, -no quartz is required. diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1833/retarget.c cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/retarget.c --- cpputest-3.7.2/platforms_startup/armcc/LPC1833/retarget.c 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/retarget.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,224 +0,0 @@ -/* - * @brief IO redirection support - * - * This file adds re-direction support to the library for various - * projects. It can be configured in one of 3 ways - no redirection, - * redirection via a UART, or redirection via semihosting. If DEBUG - * is not defined, all printf statements will do nothing with the - * output being throw away. If DEBUG is defined, then the choice of - * output is selected by the DEBUG_SEMIHOSTING define. If the - * DEBUG_SEMIHOSTING is not defined, then output is redirected via - * the UART. If DEBUG_SEMIHOSTING is defined, then output will be - * attempted to be redirected via semihosting. If the UART method - * is used, then the Board_UARTPutChar and Board_UARTGetChar - * functions must be defined to be used by this driver and the UART - * must already be initialized to the correct settings. - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - - -/* Keil (Realview) support */ -#include -#include -#include -#include - -#include "cmsis_18xx.h" - - -#pragma import(__use_no_semihosting_swi) - -/* Standard IO device handles. */ -const FILEHANDLE STDIN = 0x8001; -const FILEHANDLE STDOUT = 0x8002; -const FILEHANDLE STDERR = 0x8003; - -const char __stdin_name[] = "STDIN"; -const char __stdout_name[] = "STDOUT"; -const char __stderr_name[] = "STDERR"; - -struct __FILE { int handle; /* Add whatever you need here */ }; - - - -/* number of system timer ticks */ -static time_t timer_ticks = 0; - - -FILEHANDLE _sys_open(const char *name, int openmode) -{ - FILEHANDLE rc; - /* Register standard Input Output devices. */ - if (strcmp(name, "STDIN") == 0) rc = STDIN; - else if (strcmp(name, "STDOUT") == 0) rc = STDOUT; - else if (strcmp(name, "STDERR") == 0) rc = STDERR; - else rc = -1; - return (rc); -} - - -int _sys_close(FILEHANDLE fh) -{ - return fh > 0x8000 ? 0 : 0; -} - - -/* Write to SWO */ -void _ttywrch(int ch) -{ - ITM_SendChar(ch); -} - - -int _sys_istty(FILEHANDLE fh) -{ - return fh > 0x8000 ? 1 : 0; -} - - -int _sys_seek(FILEHANDLE fh, long pos) -{ - return fh > 0x8000 ? -1 : 0; -} - - -long _sys_flen(FILEHANDLE fh) -{ - return fh > 0x8000 ? 0 : -1; -} - -/*--------------------------- _sys_tmpnam ------------------------------------*/ -int _sys_tmpnam (char *name, int sig, unsigned maxlen) -{ - return (1); -} - - -int _sys_write(FILEHANDLE fh, const unsigned char *buf, - unsigned len, int mode) -{ - int rc; - if (fh == STDOUT) { - while (len) { - _ttywrch(*buf); - buf++; - len--; - rc = 0; - } - } else if (fh > 0x8000) rc = -1; - else rc = -1; - return rc; -} - -int _sys_read(FILEHANDLE fh, unsigned char *buf, - unsigned len, int mode) -{ - return -1; -} - - -void _sys_exit(int return_code) -{ -label: - __WFI(); - goto label; /* endless loop */ -} - - -char *_sys_command_string(char *cmd, int len) -{ - const char * const arg[] = { - "tst.axf", - "-v", - "-gSimpleStringBuffer", - "-ojunit"}; - int i, j; - char *rc = cmd; - if (len) { - /* Specify commandline arguments here as needed */ - len = sizeof(arg) / sizeof(char *); - for (i = 0; i < len; i++) { - j = strlen(arg[i])+1; - if (cmd - rc + j > len) { - rc = NULL; - break; - } - memcpy(cmd, arg[i], j); - cmd += j; - } - if (rc) rc = cmd; - } else rc = NULL; - return rc; -} - - -void _clock_init(void) -{ - SysTick_Config(CGU_IRC_FREQ / 1000); /* 1 ms system ticks interrupt period */ -} - - -clock_t clock(void) -{ - return timer_ticks; -} - - -time_t time(time_t *timer) -{ - time_t rc = timer_ticks / CLOCKS_PER_SEC; - if (timer) *timer = rc; - return rc; -} - - -/* IRQ handler for Sys Tick timer */ -__irq void SysTick_Handler(void) -{ - timer_ticks++; -} - - -/* - * Замена встроенной в Keil MDK-ARM функции, которая создаёт связанный список - * адресов деструкторов глобальных или статических объектов в "куче" при - * инициализации окружения. - * Так как не планируется завершение программы, то ни один такой деструктор не - * должен вызываться, и можно подменить стандартную версию __aeabi_atexit на - * другую, которая не будет создавать такой список в "куче". - * Идея взята отсюда - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka3951.html - * Пример реализации взят отсюда - * http://infocenter.arm.com/help/topic/com.arm.doc.ihi0041d/IHI0041D_cppabi.pdf - */ -int __aeabi_atexit(void* object, void (*destroyer)(void*), void* dso_handle) -{ - return 1; // 0: failed; non-0: OK -// return __cxa_atexit(destroyer, object, dso_handle); /* стандартная версия из Keil MDK-ARM */ -} diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1833/startup_LPC18xx.asm cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/startup_LPC18xx.asm --- cpputest-3.7.2/platforms_startup/armcc/LPC1833/startup_LPC18xx.asm 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/startup_LPC18xx.asm 1970-01-01 00:00:00.000000000 +0000 @@ -1,337 +0,0 @@ -;/*********************************************************************** -; * @brief: LPC18xx/43xx M3/M4 startup code -; * -; * @note -; * Copyright(C) NXP Semiconductors, 2012 -; * All rights reserved. -; * -; * @par -; * Software that is described herein is for illustrative purposes only -; * which provides customers with programming information regarding the -; * LPC products. This software is supplied "AS IS" without any warranties of -; * any kind, and NXP Semiconductors and its licensor disclaim any and -; * all warranties, express or implied, including all implied warranties of -; * merchantability, fitness for a particular purpose and non-infringement of -; * intellectual property rights. NXP Semiconductors assumes no responsibility -; * or liability for the use of the software, conveys no license or rights under any -; * patent, copyright, mask work right, or any other intellectual property rights in -; * or to any products. NXP Semiconductors reserves the right to make changes -; * in the software without notification. NXP Semiconductors also makes no -; * representation or warranty that such application will be suitable for the -; * specified use without further testing or modification. -; * -; * @par -; * Permission to use, copy, modify, and distribute this software and its -; * documentation is hereby granted, under NXP Semiconductors' and its -; * licensor's relevant copyrights in the software, without fee, provided that it -; * is used in conjunction with NXP Semiconductors microcontrollers. This -; * copyright, permission, and disclaimer notice must appear in all copies of -; * this code. -; */ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00002000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00004000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, CODE, READONLY - EXPORT __Vectors - -Sign_Value EQU 0x5A5A5A5A - -__Vectors DCD __initial_sp ; 0 Top of Stack - DCD Reset_Handler ; 1 Reset Handler - DCD NMI_Handler ; 2 NMI Handler - DCD HardFault_Handler ; 3 Hard Fault Handler - DCD MemManage_Handler ; 4 MPU Fault Handler - DCD BusFault_Handler ; 5 Bus Fault Handler - DCD UsageFault_Handler ; 6 Usage Fault Handler - DCD Sign_Value ; 7 Reserved - DCD UnHandled_Vector ; 8 Reserved - DCD UnHandled_Vector ; 9 Reserved - DCD UnHandled_Vector ; 10 Reserved - DCD SVC_Handler ; 11 SVCall Handler - DCD DebugMon_Handler ; 12 Debug Monitor Handler - DCD UnHandled_Vector ; 13 Reserved - DCD PendSV_Handler ; 14 PendSV Handler - DCD SysTick_Handler ; 15 SysTick Handler - - ; External Interrupts - DCD DAC_IRQHandler ; 16 D/A Converter - DCD M0APP_IRQHandler ; 17 M0APP IRQ handler (LPC43XX ONLY) - DCD DMA_IRQHandler ; 18 General Purpose DMA - DCD UnHandled_Vector ; 19 Reserved - DCD FLASH_EEPROM_IRQHandler ; 20 ORed flash bank A, flash bank B, EEPROM interrupts - DCD ETH_IRQHandler ; 21 Ethernet - DCD SDIO_IRQHandler ; 22 SD/MMC - DCD LCD_IRQHandler ; 23 LCD - DCD USB0_IRQHandler ; 24 USB0 - DCD USB1_IRQHandler ; 25 USB1 - DCD SCT_IRQHandler ; 26 State Configurable Timer - DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer - DCD TIMER0_IRQHandler ; 28 Timer0 - DCD TIMER1_IRQHandler ; 29 Timer1 - DCD TIMER2_IRQHandler ; 30 Timer2 - DCD TIMER3_IRQHandler ; 31 Timer3 - DCD MCPWM_IRQHandler ; 32 Motor Control PWM - DCD ADC0_IRQHandler ; 33 A/D Converter 0 - DCD I2C0_IRQHandler ; 34 I2C0 - DCD I2C1_IRQHandler ; 35 I2C1 - DCD SPI_IRQHandler ; 36 SPI (LPC43XX ONLY) - DCD ADC1_IRQHandler ; 37 A/D Converter 1 - DCD SSP0_IRQHandler ; 38 SSP0 - DCD SSP1_IRQHandler ; 39 SSP1 - DCD UART0_IRQHandler ; 40 UART0 - DCD UART1_IRQHandler ; 41 UART1 - DCD UART2_IRQHandler ; 42 UART2 - DCD UART3_IRQHandler ; 43 UART3 - DCD I2S0_IRQHandler ; 44 I2S0 - DCD I2S1_IRQHandler ; 45 I2S1 - DCD SPIFI_IRQHandler ; 46 SPI Flash Interface - DCD SGPIO_IRQHandler ; 47 SGPIO (LPC43XX ONLY) - DCD GPIO0_IRQHandler ; 48 GPIO0 - DCD GPIO1_IRQHandler ; 49 GPIO1 - DCD GPIO2_IRQHandler ; 50 GPIO2 - DCD GPIO3_IRQHandler ; 51 GPIO3 - DCD GPIO4_IRQHandler ; 52 GPIO4 - DCD GPIO5_IRQHandler ; 53 GPIO5 - DCD GPIO6_IRQHandler ; 54 GPIO6 - DCD GPIO7_IRQHandler ; 55 GPIO7 - DCD GINT0_IRQHandler ; 56 GINT0 - DCD GINT1_IRQHandler ; 57 GINT1 - DCD EVRT_IRQHandler ; 58 Event Router - DCD CAN1_IRQHandler ; 59 C_CAN1 - DCD UnHandled_Vector ; 60 Reserved - DCD ADCHS_IRQHandler ; 61 ADCHS combined interrupt - DCD ATIMER_IRQHandler ; 62 ATIMER - DCD RTC_IRQHandler ; 63 RTC - DCD UnHandled_Vector ; 64 Reserved - DCD WDT_IRQHandler ; 65 WDT - DCD M0SUB_IRQHandler ; 66 M0SUB IRQ handler (LPC43XX ONLY) - DCD CAN0_IRQHandler ; 67 C_CAN0 - DCD QEI_IRQHandler ; 68 QEI - - -; IF :LNOT::DEF:NO_CRP -; AREA |.ARM.__at_0x02FC|, CODE, READONLY -;CRP_Key DCD 0xFFFFFFFF -; ENDIF - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -UnHandled_Vector PROC - EXPORT UnHandled_Vector [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT DAC_IRQHandler [WEAK] - EXPORT M0APP_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT FLASH_EEPROM_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USB1_IRQHandler [WEAK] - EXPORT SCT_IRQHandler [WEAK] - EXPORT RIT_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT I2S0_IRQHandler [WEAK] - EXPORT I2S1_IRQHandler [WEAK] - EXPORT SPIFI_IRQHandler [WEAK] - EXPORT SGPIO_IRQHandler [WEAK] - EXPORT GPIO0_IRQHandler [WEAK] - EXPORT GPIO1_IRQHandler [WEAK] - EXPORT GPIO2_IRQHandler [WEAK] - EXPORT GPIO3_IRQHandler [WEAK] - EXPORT GPIO4_IRQHandler [WEAK] - EXPORT GPIO5_IRQHandler [WEAK] - EXPORT GPIO6_IRQHandler [WEAK] - EXPORT GPIO7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT EVRT_IRQHandler [WEAK] - EXPORT CAN1_IRQHandler [WEAK] - EXPORT ADCHS_IRQHandler [WEAK] - EXPORT ATIMER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT M0SUB_IRQHandler [WEAK] - EXPORT CAN0_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - -DAC_IRQHandler -M0APP_IRQHandler -DMA_IRQHandler -FLASH_EEPROM_IRQHandler -ETH_IRQHandler -SDIO_IRQHandler -LCD_IRQHandler -USB0_IRQHandler -USB1_IRQHandler -SCT_IRQHandler -RIT_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -MCPWM_IRQHandler -ADC0_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI_IRQHandler -ADC1_IRQHandler -SSP0_IRQHandler -SSP1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -I2S0_IRQHandler -I2S1_IRQHandler -SPIFI_IRQHandler -SGPIO_IRQHandler -GPIO0_IRQHandler -GPIO1_IRQHandler -GPIO2_IRQHandler -GPIO3_IRQHandler -GPIO4_IRQHandler -GPIO5_IRQHandler -GPIO6_IRQHandler -GPIO7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -EVRT_IRQHandler -CAN1_IRQHandler -ADCHS_IRQHandler -ATIMER_IRQHandler -RTC_IRQHandler -WDT_IRQHandler -M0SUB_IRQHandler -CAN0_IRQHandler -QEI_IRQHandler - - B . - - ENDP - - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_setup_stackheap -__user_setup_stackheap - - LDR R0, = Heap_Mem - LDR R2, = (Heap_Mem + Heap_Size) - LDR SP, =(Stack_Mem + Stack_Size) - BX LR - - ALIGN - - ENDIF - - END - diff -Nru cpputest-3.7.2/platforms_startup/armcc/LPC1833/sysinit.c cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/sysinit.c --- cpputest-3.7.2/platforms_startup/armcc/LPC1833/sysinit.c 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/armcc/LPC1833/sysinit.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,45 +0,0 @@ -#include "cmsis_18xx.h" - -typedef struct { /*!< CREG Structure */ - __I uint32_t RESERVED0; - __IO uint32_t CREG0; /*!< Chip configuration register 32 kHz oscillator output and BOD control register. */ - __I uint32_t RESERVED1[62]; - __IO uint32_t MXMEMMAP; /*!< ARM Cortex-M3/M4 memory mapping */ - __I uint32_t RESERVED2[5]; - __IO uint32_t CREG5; /*!< Chip configuration register 5. Controls JTAG access. */ - __IO uint32_t DMAMUX; /*!< DMA muxing control */ - __IO uint32_t FLASHCFGA; /*!< Flash accelerator configuration register for flash bank A */ - __IO uint32_t FLASHCFGB; /*!< Flash accelerator configuration register for flash bank B */ - __IO uint32_t ETBCFG; /*!< ETB RAM configuration */ - __IO uint32_t CREG6; /*!< Chip configuration register 6. */ - __I uint32_t RESERVED4[52]; - __I uint32_t CHIPID; /*!< Part ID */ - __I uint32_t RESERVED5[191]; - __IO uint32_t USB0FLADJ; /*!< USB0 frame length adjust register */ - __I uint32_t RESERVED9[63]; - __IO uint32_t USB1FLADJ; /*!< USB1 frame length adjust register */ -} LPC_CREG_T; - -#define LPC_CREG_BASE 0x40043000 -#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE) - -static inline void Chip_CREG_SetFlashAcceleration(uint32_t Hz) -{ - uint32_t FAValue = Hz / 21510000; - - LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12); - LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12); -} - - -/* Set up and initialize hardware prior to call to main */ -void SystemInit(void) -{ - unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08; - - extern void *__Vectors; - *pSCB_VTOR = (unsigned int) &__Vectors; - - Chip_CREG_SetFlashAcceleration(CGU_IRC_FREQ); -} - diff -Nru cpputest-3.7.2/platforms_startup/README cpputest-3.7.2+dfsg/platforms_startup/README --- cpputest-3.7.2/platforms_startup/README 2015-05-04 05:44:16.000000000 +0000 +++ cpputest-3.7.2+dfsg/platforms_startup/README 1970-01-01 00:00:00.000000000 +0000 @@ -1,4 +0,0 @@ -Directory to place startup files for different toolchains/chips combinations. - -Source files from this directory is compiled to library placed in lib - directory in CppUTest home.