--- gcc-4.5-4.5.2.orig/debian/fixincludes.in +++ gcc-4.5-4.5.2/debian/fixincludes.in @@ -0,0 +1,8 @@ +#! /bin/sh + +PATH="/@LIBEXECDIR@/install-tools:$PATH" + +TARGET_MACHINE=`dpkg-architecture -qDEB_HOST_GNU_TYPE` +export TARGET_MACHINE + +exec fixinc.sh "$@" --- gcc-4.5-4.5.2.orig/debian/lib64objc2.symbols +++ gcc-4.5-4.5.2/debian/lib64objc2.symbols @@ -0,0 +1,3 @@ +libobjc.so.2 lib64objc2 #MINVER# +#include "libobjc2.symbols.common" + __gnu_objc_personality_v0@Base 4.2.1 --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.s390 +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.s390 @@ -0,0 +1,101 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.1.0@GCC_4.1.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GLIBC_2.0@GLIBC_2.0 1:4.1.1 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __ashldi3@GCC_3.0 1:4.1.1 + __ashrdi3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzsi2@GCC_3.4 1:4.1.1 + __cmpdi2@GCC_3.0 1:4.1.1 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzsi2@GCC_3.4 1:4.1.1 + __deregister_frame@GLIBC_2.0 1:4.1.1 + __deregister_frame_info@GLIBC_2.0 1:4.1.1 + __deregister_frame_info_bases@GCC_3.0 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divdi3@GLIBC_2.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + __divtc3@GCC_4.1.0 1:4.1.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 1:4.1.1 + __ffsdi2@GCC_3.0 1:4.1.1 + __ffssi2@GCC_4.3.0 1:4.3 + __fixdfdi@GCC_3.0 1:4.1.1 + __fixsfdi@GCC_3.0 1:4.1.1 + __fixtfdi@GCC_4.1.0 1:4.1.1 + __fixunsdfdi@GCC_3.0 1:4.1.1 + __fixunsdfsi@GCC_3.0 1:4.1.1 + __fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfsi@GCC_3.0 1:4.1.1 + __fixunstfdi@GCC_4.1.0 1:4.1.1 + __floatdidf@GCC_3.0 1:4.1.1 + __floatdisf@GCC_3.0 1:4.1.1 + __floatditf@GCC_4.1.0 1:4.1.1 + __floatundidf@GCC_4.2.0 1:4.2.1 + __floatundisf@GCC_4.2.0 1:4.2.1 + __floatunditf@GCC_4.2.0 1:4.2.1 + __frame_state_for@GLIBC_2.0 1:4.1.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __lshrdi3@GCC_3.0 1:4.1.1 + __moddi3@GLIBC_2.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __muldi3@GCC_3.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_4.1.0 1:4.1.1 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __negdi2@GCC_3.0 1:4.1.1 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __paritydi2@GCC_3.4 1:4.1.1 + __paritysi2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountsi2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_4.1.0 1:4.1.1 + __register_frame@GLIBC_2.0 1:4.1.1 + __register_frame_info@GLIBC_2.0 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GLIBC_2.0 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GLIBC_2.0 1:4.1.1 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __ucmpdi2@GCC_3.0 1:4.1.1 + __udivdi3@GLIBC_2.0 1:4.1.1 + __udivmoddi4@GCC_3.0 1:4.1.1 + __umoddi3@GLIBC_2.0 1:4.1.1 --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.armel +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.armel @@ -0,0 +1,2 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" --- gcc-4.5-4.5.2.orig/debian/rules.parameters +++ gcc-4.5-4.5.2/debian/rules.parameters @@ -0,0 +1,32 @@ +# configuration parameters taken from upstream source files +GCC_VERSION := 4.5.2 +NEXT_GCC_VERSION := 4.5.3 +BASE_VERSION := 4.5 +SOURCE_VERSION := 4.5.2-8ubuntu2 +DEB_VERSION := 4.5.2-8ubuntu2 +DEB_EVERSION := 1:4.5.2-8ubuntu2 +GDC_BASE_VERSION := +DEB_GDC_VERSION := +DEB_SOVERSION := 4.4 +DEB_SOEVERSION := 1:4.4 +DEB_LIBGCC_SOVERSION := 1:4.4 +DEB_LIBGCC_VERSION := 1:4.5.2-8ubuntu2 +DEB_STDCXX_SOVERSION := 4.4 +DEB_GCJ_SOVERSION := 4.4 +PKG_GCJ_EXT := 11 +PKG_LIBGCJ_EXT := 11 +DEB_GOMP_SOVERSION := 4.4 +DEB_GCCMATH_SOVERSION := 4.4 +GCC_SONAME := 1 +CXX_SONAME := 6 +FORTRAN_SONAME := 3 +OBJC_SONAME := 2 +GCJ_SONAME := 11 +GNAT_VERSION := 4.5 +GNAT_SONAME := 4.5 +FFI_SONAME := 4 +MUDFLAP_SONAME := 0 +SSP_SONAME := 0 +GOMP_SONAME := 1 +GCCMATH_SONAME := +LIBC_DEP := libc6 --- gcc-4.5-4.5.2.orig/debian/gpc-4.5-doc.doc-base.gpc +++ gcc-4.5-4.5.2/debian/gpc-4.5-doc.doc-base.gpc @@ -0,0 +1,15 @@ +Document: gpc-4.5-doc +Title: The GNU Pascal Compiler +Author: Various +Abstract: This manual documents how to run, install and maintain the + GNU Pascal compiler (GPC), as well as its new features and + incompatibilities, and how to report bugs. +Section: Programming/Pascal + +Format: html +Index: /usr/share/doc/gcc-4.5-base/pascal/gpc.html +Files: /usr/share/doc/gcc-4.5-base/pascal/gpc.html + +Format: info +Index: /usr/share/info/gpc-4.5.info.gz +Files: /usr/share/info/gpc-4.5* --- gcc-4.5-4.5.2.orig/debian/rules.sonames +++ gcc-4.5-4.5.2/debian/rules.sonames @@ -0,0 +1,60 @@ +ifneq ($(vafilt_defined),1) + $(error rules.defs must be included before rules.sonames) +endif + +ifeq (,$(wildcard debian/soname-cache)) + SONAME_VARS := $(shell \ + cache=debian/soname-cache; \ + rm -f $$cache; \ + v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \ + $(srcdir)/libstdc++-v3/configure.ac`; \ + echo CXX_SONAME=$$v >> $$cache; \ + v=`awk -F= '/^VERSION/ {split($$2,v,":"); print v[1]}' \ + $(srcdir)/libobjc/configure.ac`; \ + echo OBJC_SONAME=$$v >> $$cache; \ + v=`tail -1 $(srcdir)/libgfortran/libtool-version | cut -d: -f1`; \ + echo FORTRAN_SONAME=$$v >> $$cache; \ + v=`tail -1 $(srcdir)/libmudflap/libtool-version | cut -d: -f1`; \ + echo MUDFLAP_SONAME=$$v >> $$cache; \ + v=`tail -1 $(srcdir)/libssp/libtool-version | cut -d: -f1`; \ + echo SSP_SONAME=$$v >> $$cache; \ + v=`tail -1 $(srcdir)/libjava/libtool-version | cut -d: -f1`; \ + echo GCJ_SONAME=$$v >> $$cache; \ + if [ "$$v" -ge 70 ]; then \ + echo GCJ_SONAME1=`echo $$v | sed 's/.$$//'` >> $$cache; \ + echo GCJ_SONAME2=`echo $$v | sed 's/.*\(.\)$$/\1/'` >> $$cache; \ + else \ + echo GCJ_SONAME1=$$v >> $$cache; \ + echo GCJ_SONAME2= >> $$cache; \ + fi; \ + v=`tail -1 $(srcdir)/libffi/libtool-version | cut -d: -f1`; \ + echo FFI_SONAME=$$v >> $$cache; \ + v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \ + $(srcdir)/libgomp/configure.ac`; \ + echo GOMP_SONAME=$$v >> $$cache; \ + if [ "$(with_libgmath)" = yes ]; then \ + v=`tail -1 $(srcdir)/libgcc-math/libtool-version | cut -d: -f1`; \ + echo GCCMATH_SONAME=$$v >> $$cache; \ + fi; \ + v=`grep '[^_]Library_Version.*:' $(srcdir)/gcc/ada/gnatvsn.ads \ + | sed -e 's/.*"\([^"]*\)".*/\1/'`; \ + echo GNAT_SONAME=$$v >> $$cache; \ + cat $$cache) +else + SONAME_VARS := $(shell cat debian/soname-cache) +endif +CXX_SONAME = $(call vafilt,$(SONAME_VARS),CXX_SONAME) +OBJC_SONAME = $(call vafilt,$(SONAME_VARS),OBJC_SONAME) +FORTRAN_SONAME = $(call vafilt,$(SONAME_VARS),FORTRAN_SONAME) +MUDFLAP_SONAME = $(call vafilt,$(SONAME_VARS),MUDFLAP_SONAME) +SSP_SONAME = $(call vafilt,$(SONAME_VARS),SSP_SONAME) +GCJ_SONAME = $(call vafilt,$(SONAME_VARS),GCJ_SONAME) +GCJ_SONAME1 = $(call vafilt,$(SONAME_VARS),GCJ_SONAME1) +GCJ_SONAME2 = $(call vafilt,$(SONAME_VARS),GCJ_SONAME2) +FFI_SONAME = $(call vafilt,$(SONAME_VARS),FFI_SONAME) +GOMP_SONAME = $(call vafilt,$(SONAME_VARS),GOMP_SONAME) +GCCMATH_SONAME = $(call vafilt,$(SONAME_VARS),GCCMATH_SONAME) +GNAT_SONAME = $(call vafilt,$(SONAME_VARS),GNAT_SONAME) + +# alias +GFORTRAN_SONAME = $(FORTRAN_SONAME) --- gcc-4.5-4.5.2.orig/debian/gnatvsn.gpr +++ gcc-4.5-4.5.2/debian/gnatvsn.gpr @@ -0,0 +1,31 @@ +-- Project file for use with GNAT +-- Copyright (c) 2005, 2008 Ludovic Brenta +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- This project file is designed to help build applications that use +-- GNAT project files. Here is an example of how to use this project file: +-- +-- with "gnatvsn"; +-- project Example is +-- for Object_Dir use "obj"; +-- for Exec_Dir use "."; +-- for Main use ("example"); +-- end Example; + +project Gnatvsn is + for Library_Name use "gnatvsn"; + for Library_Dir use "/usr/lib"; + for Library_Kind use "dynamic"; + for Source_Dirs use ("/usr/share/ada/adainclude/gnatvsn"); + for Library_ALI_Dir use "/usr/lib/ada/adalib/gnatvsn"; + for Externally_Built use "true"; +end Gnatvsn; --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.ia64 +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.ia64 @@ -0,0 +1,5 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.10" +#include "libgfortran3.symbols.16" +#include "libgfortran3.symbols.64" --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.powerpc +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.powerpc @@ -0,0 +1,8 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" +#include "libstdc++6.symbols.excprop" + __gxx_personality_v0@CXXABI_1.3 4.1.1 +#include "libstdc++6.symbols.glibcxxmath" +#include "libstdc++6.symbols.ldbl.32bit" + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2 --- gcc-4.5-4.5.2.orig/debian/lib32stdc++6.symbols.kfreebsd-amd64 +++ gcc-4.5-4.5.2/debian/lib32stdc++6.symbols.kfreebsd-amd64 @@ -0,0 +1,6 @@ +libstdc++.so.6 lib32stdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" +#include "libstdc++6.symbols.excprop" + __gxx_personality_v0@CXXABI_1.3 4.1.1 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 --- gcc-4.5-4.5.2.orig/debian/g++-BV-CRB.preinst.in +++ gcc-4.5-4.5.2/debian/g++-BV-CRB.preinst.in @@ -0,0 +1,11 @@ +#!/bin/sh + +set -e + +if [ "$1" = "upgrade" ] || [ "$1" = "configure" ]; then + update-alternatives --quiet --remove @TARGET@-g++ /usr/bin/@TARGET@-g++-@BV@ +fi + +#DEBHELPER# + +exit 0 --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.sparc64 +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.sparc64 @@ -0,0 +1,5 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.16.powerpc" +#include "libgfortran3.symbols.16.powerpc64" +#include "libgfortran3.symbols.64" --- gcc-4.5-4.5.2.orig/debian/compat +++ gcc-4.5-4.5.2/debian/compat @@ -0,0 +1 @@ +5 --- gcc-4.5-4.5.2.orig/debian/gcc-dummy.texi +++ gcc-4.5-4.5.2/debian/gcc-dummy.texi @@ -0,0 +1,41 @@ +\input texinfo @c -*-texinfo-*- +@c %**start of header + +@settitle The GNU Compiler Collection (GCC) + +@c Create a separate index for command line options. +@defcodeindex op +@c Merge the standard indexes into a single one. +@syncodeindex fn cp +@syncodeindex vr cp +@syncodeindex ky cp +@syncodeindex pg cp +@syncodeindex tp cp + +@paragraphindent 1 + +@c %**end of header + +@copying +The current documentation is licensed under the same terms as the Debian packaging. +@end copying +@ifnottex +@dircategory Programming +@direntry +* @name@: (@name@). The GNU Compiler Collection (@name@). +@end direntry +@sp 1 +@end ifnottex + +@summarycontents +@contents +@page + +@node Top +@top Introduction +@cindex introduction +The official GNU compilers' documentation is released under the terms +of the GNU Free Documentation License with cover texts. This has been +considered non free by the Debian Project. Thus you will find it in the +non-free section of the Debian archive. +@bye --- gcc-4.5-4.5.2.orig/debian/libgcj-common.postinst +++ gcc-4.5-4.5.2/debian/libgcj-common.postinst @@ -0,0 +1,12 @@ +#! /bin/sh -e + +case "$1" in + configure) + docdir=/usr/share/doc/libgcj-common + if [ -d $docdir ] && [ ! -h $docdir ]; then + rm -rf $docdir + ln -s gcj-@BV@-base $docdir + fi +esac + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/lib64stdc++CXX.postinst +++ gcc-4.5-4.5.2/debian/lib64stdc++CXX.postinst @@ -0,0 +1,12 @@ +#! /bin/sh -e + +case "$1" in + configure) + docdir=/usr/share/doc/lib64stdc++@CXX@ + if [ -d $docdir ] && [ ! -h $docdir ]; then + rm -rf $docdir + ln -s gcc-@BV@-base $docdir + fi +esac + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/gcj-BV-jdk.doc-base +++ gcc-4.5-4.5.2/debian/gcj-BV-jdk.doc-base @@ -0,0 +1,15 @@ +Document: gcj-@BV@ +Title: The GNU Ahead-of-time Compiler for the Java Language +Author: Various +Abstract: This manual describes how to use gcj, the GNU compiler for + the Java programming language. gcj can generate both .class files and + object files, and it can read both Java source code and .class files. +Section: Programming/Java + +Format: html +Index: /usr/share/doc/gcc-@BV@-base/java/gcj.html +Files: /usr/share/doc/gcc-@BV@-base/java/gcj.html + +Format: info +Index: /usr/share/info/gcj-@BV@.info.gz +Files: /usr/share/info/gcj-@BV@* --- gcc-4.5-4.5.2.orig/debian/README.Bugs.m4 +++ gcc-4.5-4.5.2/debian/README.Bugs.m4 @@ -0,0 +1,333 @@ +Reporting Bugs in the GNU Compiler Collection for DIST +======================================================== + +Before reporting a bug, please +------------------------------ + +- Check that the behaviour really is a bug. Have a look into some + ANSI standards document. + +- Check the list of well known bugs: http://gcc.gnu.org/bugs.html#known + +- Try to reproduce the bug with a current GCC development snapshot. You + usually can get a recent development snapshot from the gcc-snapshot +ifelse(DIST,`Debian',`dnl + package in the unstable (or experimental) distribution. + + See: http://packages.debian.org/gcc-snapshot +', DIST, `Ubuntu',`dnl + package in the current development distribution. + + See: http://archive.ubuntu.com/ubuntu/pool/universe/g/gcc-snapshot/ +')dnl + +- Try to find out if the bug is a regression (an older GCC version does + not show the bug). + +- Check if the bug is already reported in the bug tracking systems. + +ifelse(DIST,`Debian',`dnl + Debian: http://bugs.debian.org/debian-gcc@lists.debian.org +', DIST, `Ubuntu',`dnl + Ubuntu: https://bugs.launchpad.net/~ubuntu-toolchain/+packagebugs + Debian: http://bugs.debian.org/debian-gcc@lists.debian.org +')dnl + Upstream: http://gcc.gnu.org/bugzilla/ + + +Where to report a bug +--------------------- + +ifelse(DIST,`Debian',`dnl +Please report bugs found in the packaging of GCC to the Debian bug tracking +system. See http://www.debian.org/Bugs/ for instructions (or use the +reportbug script). +', DIST, `Ubuntu',`dnl +Please report bugs found in the packaging of GCC to Launchpad. See below +how issues should be reported. +')dnl + +DIST's current policy is to closely follow the upstream development and +only apply a minimal set of patches (which are summarized in the README.Debian +document). + +ifelse(DIST,`Debian',`dnl +If you think you have found an upstream bug, you did check the section +above ("Before reporting a bug") and are able to provide a complete bug +report (see below "How to report a bug"), then you may help the Debian +GCC package maintainers, if you report the bug upstream and then submit +a bug report to the Debian BTS and tell us the upstream report number. +This way you are able to follow the upstream bug handling as well. If in +doubt, report the bug to the Debian BTS (but read "How to report a bug" +below). +', DIST, `Ubuntu',`dnl +If you think you have found an upstream bug, you did check the section +above ("Before reporting a bug") and are able to provide a complete bug +report (see below "How to report a bug"), then you may help the Ubuntu +GCC package maintainers, if you report the bug upstream and then submit +a bug report to Launchpad and tell us the upstream report number. +This way you are able to follow the upstream bug handling as well. If in +doubt, report the bug to Launchpad (but read "How to report a bug" below). + +Report the issue to https://bugs.launchpad.net/ubuntu/+source/SRCNAME. +')dnl + + +How to report a bug +------------------- + +There are complete instructions in the gcc info manual (found in the +gcc-doc package), section Bugs. + +The manual can be read using `M-x info' in Emacs, or if the GNU info +program is installed on your system by `info --node "(gcc)Bugs"'. Or see +the file BUGS included with the gcc source code. + +Online bug reporting instructions can be found at + + http://gcc.gnu.org/bugs.html + +[Some paragraphs taken from the above URL] + +The main purpose of a bug report is to enable us to fix the bug. The +most important prerequisite for this is that the report must be +complete and self-contained, which we explain in detail below. + +Before you report a bug, please check the list of well-known bugs and, +if possible in any way, try a current development snapshot. + +Summarized bug reporting instructions +------------------------------------- + +What we need + +Please include in your bug report all of the following items, the +first three of which can be obtained from the output of gcc -v: + + * the exact version of GCC; + * the system type; + * the options given when GCC was configured/built; + * the complete command line that triggers the bug; + * the compiler output (error messages, warnings, etc.); and + * the preprocessed file (*.i*) that triggers the bug, generated by + adding -save-temps to the complete compilation command, or, in + the case of a bug report for the GNAT front end, a complete set + of source files (see below). + +What we do not want + + * A source file that #includes header files that are left out + of the bug report (see above) + * That source file and a collection of header files. + * An attached archive (tar, zip, shar, whatever) containing all + (or some :-) of the above. + * A code snippet that won't cause the compiler to produce the + exact output mentioned in the bug report (e.g., a snippet with + just a few lines around the one that apparently triggers the + bug, with some pieces replaced with ellipses or comments for + extra obfuscation :-) + * The location (URL) of the package that failed to build (we won't + download it, anyway, since you've already given us what we need + to duplicate the bug, haven't you? :-) + * An error that occurs only some of the times a certain file is + compiled, such that retrying a sufficient number of times + results in a successful compilation; this is a symptom of a + hardware problem, not of a compiler bug (sorry) + * E-mail messages that complement previous, incomplete bug + reports. Post a new, self-contained, full bug report instead, if + possible as a follow-up to the original bug report + * Assembly files (*.s) produced by the compiler, or any binary files, + such as object files, executables, core files, or precompiled + header files + * Duplicate bug reports, or reports of bugs already fixed in the + development tree, especially those that have already been + reported as fixed last week :-) + * Bugs in the assembler, the linker or the C library. These are + separate projects, with separate mailing lists and different bug + reporting procedures + * Bugs in releases or snapshots of GCC not issued by the GNU + Project. Report them to whoever provided you with the release + * Questions about the correctness or the expected behavior of + certain constructs that are not GCC extensions. Ask them in + forums dedicated to the discussion of the programming language + + +Known Bugs and Non-Bugs +----------------------- + +[Please see /usr/share/doc/gcc/FAQ or http://gcc.gnu.org/faq.html first] + + +C++ exceptions don't work with C libraries +------------------------------------------ + +[Taken from the closed bug report #22769] C++ exceptions don't work +with C libraries, if the C code wasn't designed to be thrown through. +A solution could be to translate all C libraries with -fexceptions. +Mostly trying to throw an exception in a callback function (qsort, +Tcl command callbacks, etc ...). Example: + + #include + #include + + class A {}; + + static + int SortCondition(void const*, void const*) + { + printf("throwing 'sortcondition' exception\n"); + throw A(); + } + + int main(int argc, char *argv[]) + { + int list[2]; + + try { + SortCondition(NULL,NULL); + } catch (A) { + printf("caught test-sortcondition exception\n"); + } + try { + qsort(&list, sizeof(list)/sizeof(list[0]),sizeof(list[0]), + &SortCondition); + } catch (A) { + printf("caught real-sortcondition exception\n"); + } + return 0; +} + +Andrew Macleod responded: + +When compiled with the table driven exception handling, exception can only +be thrown through functions which have been compiled with the table driven EH. +If a function isn't compiled that way, then we do not have the frame +unwinding information required to restore the registers when unwinding. + +I believe the setjmp/longjmp mechanism will throw through things like this, +but its produces much messier code. (-fsjlj-exceptions) + +The C compiler does support exceptions, you just have to turn them on +with -fexceptions. + +Your main options are to: + a) Don't use callbacks, or at least don't throw through them. + b) Get the source and compile the library with -fexceptions (You have to + explicitly turn on exceptions in the C compiler) + c) always use -fsjlj-exceptions (boo, bad choice :-) + + +g++: "undefined reference" to static const array in class +--------------------------------------------------------- + +The following code compiles under GNU C++ 2.7.2 with correct results, +but produces the same linker error with GNU C++ 2.95.2. +Alexandre Oliva responded: + +All of them are correct. A static data member *must* be defined +outside the class body even if it is initialized within the class +body, but no diagnostic is required if the definition is missing. It +turns out that some releases do emit references to the missing symbol, +while others optimize it away. + +#include + +class Test +{ + public: + Test(const char *q); + protected: + static const unsigned char Jam_signature[4] = "JAM"; +}; + +Test::Test(const char *q) +{ + if (memcmp(q, Jam_signature, sizeof(Jam_signature)) != 0) + cerr << "Hello world!\n"; +} + +int main(void) +{ + Test::Test("JAM"); + return 0; +} + +g++: g++ causes passing non const ptr to ptr to a func with const arg + to cause an error (not a bug) +--------------------------------------------------------------------- + +Example: + +#include +void test(const char **b){ + printf ("%s\n",*b); +} +int main(void){ + char *test1="aoeu"; + test(&test1); +} + +make const +g++ const.cc -o const +const.cc: In function `int main()': +const.cc:7: passing `char **' as argument 1 of `test(const char **)' adds cv-quals without intervening `const' +make: *** [const] Error 1 + +Answer from "Martin v. Loewis" : + +> ok... maybe I missed something.. I haven't really kept up with the latest in +> C++ news. But I've never heard anything even remotly close to passing a non +> const var into a const arg being an error before. + +Thanks for your bug report. This is a not a bug in the compiler, but +in your code. The standard, in 4.4/4, puts it that way + +# A conversion can add cv-qualifiers at levels other than the first in +# multi-level pointers, subject to the following rules: +# Two pointer types T1 and T2 are similar if there exists a type T and +# integer n > 0 such that: +# T1 is cv(1,0) pointer to cv(1,1) pointer to ... cv(1,n-1) +# pointer to cv(1,n) T +# and +# T2 is cv(2,0) pointer to cv(2,1) pointer to ... cv(2,n-1) +# pointer to cv(2,n) T +# where each cv(i,j) is const, volatile, const volatile, or +# nothing. The n-tuple of cv-qualifiers after the first in a pointer +# type, e.g., cv(1,1) , cv(1,2) , ... , cv(1,n) in the pointer type +# T1, is called the cv-qualification signature of the pointer type. An +# expression of type T1 can be converted to type T2 if and only if the +# following conditions are satisfied: +# - the pointer types are similar. +# - for every j > 0, if const is in cv(1,j) then const is in cv(2,j) , +# and similarly for volatile. +# - if the cv(1,j) and cv(2,j) are different, then const is in every +# cv(2,k) for 0 < k < j. + +It is the last rule that your code violates. The standard gives then +the following example as a rationale: + +# [Note: if a program could assign a pointer of type T** to a pointer +# of type const T** (that is, if line //1 below was allowed), a +# program could inadvertently modify a const object (as it is done on +# line //2). For example, +# int main() { +# const char c = 'c'; +# char* pc; +# const char** pcc = &pc; //1: not allowed +# *pcc = &c; +# *pc = 'C'; //2: modifies a const object +# } +# - end note] + +If you question this line of reasoning, please discuss it in one of +the public C++ fora first, eg. comp.lang.c++.moderated, or +comp.std.c++. + + +cpp removes blank lines +----------------------- + +With the new cpp, you need to add -traditional to the "cpp -P" args, else +blank lines get removed. + +[EDIT ME: scan Debian bug reports and write some nice summaries ...] --- gcc-4.5-4.5.2.orig/debian/gcc-BV-source.overrides +++ gcc-4.5-4.5.2/debian/gcc-BV-source.overrides @@ -0,0 +1,5 @@ +gcc-@BV@-source: changelog-file-not-compressed + +# these are patches taken over unmodified from 4.3 +gcc-@BV@-source: script-not-executable +gcc-@BV@-source: shell-script-fails-syntax-check --- gcc-4.5-4.5.2.orig/debian/gcc-BV-doc.doc-base.gccint +++ gcc-4.5-4.5.2/debian/gcc-BV-doc.doc-base.gccint @@ -0,0 +1,17 @@ +Document: gccint-@BV@ +Title: Internals of the GNU C and C++ compiler +Author: Various +Abstract: This manual documents the internals of the GNU compilers, + including how to port them to new targets and some information about + how to write front ends for new languages. It corresponds to GCC + version @BV@.x. The use of the GNU compilers is documented in a + separate manual. +Section: Programming + +Format: html +Index: /usr/share/doc/gcc-@BV@-base/gccint.html +Files: /usr/share/doc/gcc-@BV@-base/gccint.html + +Format: info +Index: /usr/share/info/gccint-@BV@.info.gz +Files: /usr/share/info/gccint-@BV@* --- gcc-4.5-4.5.2.orig/debian/gcj-wrapper-BV.1 +++ gcc-4.5-4.5.2/debian/gcj-wrapper-BV.1 @@ -0,0 +1,20 @@ +.TH GCJ-WRAPPER 1 "June 6, 2002" gcj-wrapper "Java User's Manual" +.SH NAME +gcj-wrapper \- a wrapper around gcj + +.SH SYNOPSIS +gcj-wrapper [\fB\s-1OPTION\s0\fR] ... [\fI\s-1ARGS\s0\fR...] + +.SH DESCRIPTION + +\fBgcj-wrapper\fR is a wrapper around gcj(1) to be called as the java +compiler. Options different for javac(1) and gcj(1) are translated, +options unknown to gcj(1) are silently ignored. + +.SH OPTIONS +See gcj-@BV@(1) for a list of options that gcj understands. + +.SH "SEE ALSO" +.BR gcj-@BV@(1) +, +.BR javac(1) --- gcc-4.5-4.5.2.orig/debian/gcc-BV-doc.doc-base.gcc +++ gcc-4.5-4.5.2/debian/gcc-BV-doc.doc-base.gcc @@ -0,0 +1,14 @@ +Document: gcc-@BV@ +Title: The GNU C and C++ compiler +Author: Various +Abstract: This manual documents how to run, install and port the GNU compiler, + as well as its new features and incompatibilities, and how to report bugs. +Section: Programming + +Format: html +Index: /usr/share/doc/gcc-@BV@-base/gcc.html +Files: /usr/share/doc/gcc-@BV@-base/gcc.html + +Format: info +Index: /usr/share/info/gcc-@BV@.info.gz +Files: /usr/share/info/gcc-@BV@* --- gcc-4.5-4.5.2.orig/debian/rules2 +++ gcc-4.5-4.5.2/debian/rules2 @@ -0,0 +1,2147 @@ +#! /usr/bin/make -f +# -*- makefile -*- + +# Uncomment this to turn on verbose mode. +#export DH_VERBOSE=1 + +.SUFFIXES: + +include debian/rules.defs +include debian/rules.parameters + +# some tools +SHELL = /bin/bash -e # brace expansion in rules file +IR = install -m 644 # Install regular file +IP = install -m 755 # Install program +IS = install -m 755 # Install script + +#number of jobs to run for build +ifeq ($(USE_NJOBS),no) + NJOBS := + USE_CPUS := 1 +else + ifeq ($(with_java),yes) + MEM_PER_CPU = 192 + else + MEM_PER_CPU = 128 + endif + NUM_CPUS := $(shell if echo $(USE_NJOBS) | grep -q -E '^[0-9]+$$'; \ + then echo $(USE_NJOBS); \ + else getconf _NPROCESSORS_ONLN 2>/dev/null || echo 1; fi) + USE_CPUS := $(shell mt=`awk '/^MemTotal/ { print $$2 }' /proc/meminfo`; \ + awk -vn=$(NUM_CPUS) -vmt=$$mt -vm=$(MEM_PER_CPU) \ + 'END { mt/=1024; n2 = int(mt/m); print n==1 ? 1 : n2 in DEB_BUILD_OPTIONS (see #209008) +ifneq (,$(filter parallel=%,$(subst $(COMMA), ,$(DEB_BUILD_OPTIONS)))) + NJOBS := -j $(subst parallel=,,$(filter parallel=%,$(subst $(COMMA), ,$(DEB_BUILD_OPTIONS)))) +endif + +# kernel-specific ulimit hack +ifeq ($(findstring linux,$(DEB_HOST_GNU_SYSTEM)),linux) + ULIMIT_M = if [ -e /proc/meminfo ]; then \ + m=`awk '/^((Mem|Swap)Free|Cached)/{m+=$$2}END{print int(m*.9)}' \ + /proc/meminfo`; \ + else \ + m=`vmstat --free --swap-free --kilobytes|awk '{m+=$$2}END{print int(m*.9)}'`; \ + fi; \ + ulimit -m $$m; \ + echo "Limited memory for test runs to `ulimit -m`kB" +else + ULIMIT_M = true +endif + +ifeq ($(locale_data),generate) + SET_LOCPATH = LOCPATH=$(PWD)/locales +endif + +SET_PATH = PATH=$(PWD)/bin:/usr/$(libdir)/gcc/bin:$$PATH +ifeq ($(PKGSOURCE),gcc-snapshot) + ifneq (,$(findstring arm-linux-gnueabi,$(DEB_TARGET_GNU_TYPE))) + SET_PATH = PATH=/usr/lib/gcc-snapshot/bin:$(PWD)/bin:/usr/$(libdir)/gcc/bin:$$PATH + endif + ifneq (,$(findstring sparc64-linux,$(DEB_TARGET_GNU_TYPE))) + SET_PATH = PATH=/usr/lib/gcc-snapshot/bin:$(PWD)/bin:/usr/$(libdir)/gcc/bin:$$PATH + endif +endif + +# the recipient for the test summaries. Send with: debian/rules mail-summary +S_EMAIL = gcc@packages.debian.org gcc-testresults@gcc.gnu.org + +# build not yet prepared to take variables from the environment +define unsetenv + unexport $(1) + $(1) = +endef +$(foreach v, CPPFLAGS CFLAGS CXXFLAGS FFLAGS LDFLAGS, $(if $(filter environment,$(origin $(v))),$(eval $(call unsetenv, $(v))))) + +ifeq ($(REVERSE_CROSS),yes) + CC = +else + CC = $(if $(filter yes,$(with_ada)),gnatgcc,gcc) +endif + +ifneq ($(distribution),Ubuntu) + ifneq (,$(filter $(DEB_TARGET_ARCH), arm armel armhf mips mipsel)) + STAGE1_CFLAGS = -g -O2 + endif +endif + +ifeq ($(with_d),yes) + CFLAGS += -std=gnu99 + LDFLAGS += -lm +endif + +ifeq ($(with_ssp_default),yes) + STAGE1_CFLAGS = -g + BOOT_CFLAGS = -g -O2 + LIBCFLAGS = -g -O2 + LIBCXXFLAGS = -g -O2 -fno-implicit-templates + # Only use -fno-stack-protector when known to the stage1 compiler. + cc-fno-stack-protector := $(shell if $(CC) $(CFLAGS) -fno-stack-protector \ + -S -o /dev/null -xc /dev/null > /dev/null 2>&1; \ + then echo "-fno-stack-protector"; fi;) + $(foreach var,STAGE1_CFLAGS BOOT_CFLAGS LIBCFLAGS LIBCXXFLAGS,$(eval \ + $(var) += $(cc-fno-stack-protector))) +endif + +ifeq ($(DEB_CROSS),yes) + CFLAGS = -g -O2 +endif + +ifneq (,$(findstring static,$(DEB_BUILD_OPTIONS))) + LDFLAGS += -static +endif + +CFLAGS_TO_PASS = \ + $(if $(CFLAGS),CFLAGS="$(CFLAGS)") \ + $(if $(BOOT_CFLAGS),BOOT_CFLAGS="$(BOOT_CFLAGS)") \ + $(if $(LIBCFLAGS),LIBCFLAGS="$(LIBCFLAGS)") \ + $(if $(LIBCXXFLAGS),LIBCXXFLAGS="$(LIBCXXFLAGS)") +LDFLAGS_TO_PASS = \ + $(if $(LDFLAGS),LDFLAGS="$(LDFLAGS)") +STAGE1_CFLAGS_TO_PASS = \ + $(if $(STAGE1_CFLAGS),STAGE1_CFLAGS="$(STAGE1_CFLAGS)") + +docdir = usr/share/doc + +CONFARGS = -v \ + --with-pkgversion='$(distribution)$(if $(with_linaro_branch),/Linaro)___$(DEB_VERSION)' \ + --with-bugurl='file:///usr/share/doc/$(PKGSOURCE)/README.Bugs' + +CONFARGS += \ + --enable-languages=$(subst $(SPACE),$(COMMA),$(enabled_languages)) \ + --prefix=/$(PF) + +ifeq ($(versioned_packages),yes) + CONFARGS += --program-suffix=-$(BASE_VERSION) +endif + +# if this variable exists at all, it's reasonable to use it, giving us +# multiarch support for free +ifneq ($(DEB_HOST_MULTIARCH),) + MULTIARCH_CONFARG = --with-multiarch-defaults=$(DEB_HOST_MULTIARCH) +endif + +ifdef DEB_STAGE + CONFARGS += \ + --disable-libgomp \ + --disable-libmudflap \ + --disable-libssp \ + --disable-multiarch \ + --disable-multilib \ + --disable-threads \ + --libexecdir=/$(libexecdir) \ + --libdir=/$(PF)/$(libdir) \ + --with-build-sysroot=$(with_build_sysroot) \ + --with-sysroot=$(with_sysroot) + + ifeq ($(DEB_STAGE),stage1) + CONFARGS += \ + --disable-shared \ + --with-newlib \ + --without-headers + else + # stage2 + CONFARGS += \ + --enable-shared + endif +else + CONFARGS += \ + --enable-shared \ + --enable-multiarch \ + $(MULTIARCH_CONFARG) \ + --enable-linker-build-id \ + --with-system-zlib \ + +ifneq ($(PKGSOURCE),gcc-snapshot) + CONFARGS += \ + --libexecdir=/$(libexecdir) \ + --without-included-gettext \ + --enable-threads=posix \ + --with-gxx-include-dir=/$(cxx_inc_dir) \ + --libdir=/$(PF)/$(libdir) +endif + +ifneq ($(with_cpp),yes) + CONFARGS += --disable-cpp +endif + +ifeq ($(with_nls),yes) + CONFARGS += --enable-nls +else + CONFARGS += --disable-nls +endif + +ifeq ($(with_bootstrap),off) + CONFARGS += --disable-bootstrap +else ifneq ($(with_bootstrap),) + CONFARGS += --enable-bootstrap=$(with_bootstrap) +endif + +ifneq ($(with_sysroot),) + CONFARGS += --with-sysroot=$(with_sysroot) +endif +ifneq ($(with_build_sysroot),) + CONFARGS += --with-build-sysroot=$(with_build_sysroot) +endif + +ifeq ($(force_gnu_locales),yes) + CONFARGS += --enable-clocale=gnu +endif + +ifeq ($(with_cxx)-$(with_debug),yes-yes) + CONFARGS += --enable-libstdcxx-debug +endif + CONFARGS += --enable-libstdcxx-time=yes + +ifneq ($(with_ssp),yes) + CONFARGS += --disable-libssp +endif + +ifneq ($(with_mudflap),yes) + CONFARGS += --disable-libmudflap +endif + +ifneq ($(with_gomp),yes) + CONFARGS += --disable-libgomp +endif + +ifeq ($(with_plugins),yes) + CONFARGS += --enable-plugin +endif + +ifeq ($(with_gold),yes) + CONFARGS += --enable-gold --enable-ld=default + CONFARGS += --with-plugin-ld=ld.gold +endif + +jvm_name_short = java-1.5.0-gcj-$(BASE_VERSION)$(if $(findstring snap,$(PKGSOURCE)),-snap) +jvm_name_long = $(jvm_name_short)-1.5.0.0 + +ifeq ($(with_java),yes) + ifeq ($(PKGSOURCE),gcc-snapshot) + CONFARGS += --disable-browser-plugin + endif + ifneq (, $(findstring 4.5,$(PKGSOURCE))) + CONFARGS += --disable-browser-plugin + endif + ifeq ($(with_java_maintainer_mode),yes) + CONFARGS += --enable-java-maintainer-mode + endif + ifeq ($(with_java_biarch_awt),yes) + CONFARGS += --enable-java-awt=$(subst $(SPACE),$(COMMA),$(foreach p,$(java_awt_peers),$(p)-default)) + else + CONFARGS += --enable-java-awt=$(subst $(SPACE),$(COMMA),$(foreach p,$(java_awt_peers),$(p))) + endif + ifneq (,$(findstring gtk,$(java_awt_peers))) + CONFARGS += --enable-gtk-cairo + endif + jvm_dir = /usr/lib/jvm/$(jvm_name_short) + CONFARGS += --with-java-home=$(jvm_dir)/jre + CONFARGS += --enable-java-home \ + --with-jvm-root-dir=$(jvm_dir) \ + --with-jvm-jar-dir=/usr/lib/jvm-exports/$(jvm_name_short) + CONFARGS += --with-arch-directory=$(java_cpu) + ifeq (./,$(dir $(ecj_jar))) + CONFARGS += --with-ecj-jar=$(jvm_dir)/lib/ecj.jar + else + CONFARGS += --with-ecj-jar=$(ecj_jar) + endif +endif + +ifeq ($(with_gcj),yes) + ifeq ($(DEB_HOST_GNU_CPU),m32r) + CONFARGS += --enable-libgcj + endif +endif + +ifeq ($(with_objc)-$(with_objc_gc),yes-yes) + CONFARGS += --enable-objc-gc +endif + +ifneq (,$(filter $(DEB_TARGET_GNU_TYPE), i486-linux-gnu i586-linux-gnu i686-linux-gnu)) + ifeq ($(biarch64),yes) + CONFARGS += --enable-targets=all + endif +endif + +ifneq (,$(filter $(DEB_TARGET_GNU_TYPE), x86_64-linux-gnu)) + ifneq ($(biarch32),yes) + CONFARGS += --disable-multilib + endif +endif + +ifneq (,$(filter $(DEB_TARGET_GNU_TYPE), powerpc-linux-gnu powerpc-linux-gnuspe)) + CONFARGS += --enable-secureplt + ifeq ($(biarch64),yes) + CONFARGS += --disable-softfloat \ + --enable-targets=powerpc-linux,powerpc64-linux --with-cpu=default32 + else + CONFARGS += --disable-multilib + endif +endif + +ifneq (,$(findstring powerpc64-linux,$(DEB_TARGET_GNU_TYPE))) + CONFARGS += --enable-secureplt + ifeq ($(biarch32),yes) + CONFARGS += --disable-softfloat --enable-targets=powerpc64-linux,powerpc-linux + else + CONFARGS += --disable-multilib + endif + ifeq ($(distribution),Ubuntu) + CONFARGS += --with-cpu-32=power7 --with-cpu-64=power7 + endif +endif + +ifeq ($(REVERSE_CROSS),yes) + # FIXME: requires ppl and cloog headers for the target + CONFARGS += --without-ppl + # FIXME: build currently fails build the precompiled headers + CONFARGS += --disable-libstdcxx-pch +endif +endif # !DEB_STAGE + +ifeq ($(findstring powerpcspe,$(DEB_TARGET_ARCH)),powerpcspe) + CONFARGS += --with-cpu=8548 --enable-e500_double --with-long-double-128 +endif + +ifneq (,$(findstring softfloat,$(DEB_TARGET_GNU_CPU))) + CONFARGS += --with-float=soft +endif + +ifneq (,$(findstring arm-vfp,$(DEB_TARGET_GNU_CPU))) + CONFARGS += --with-fpu=vfp +endif + +ifneq (,$(findstring arm, $(DEB_TARGET_GNU_CPU))) + CONFARGS += --disable-sjlj-exceptions + # FIXME: libjava is not ported for thumb, this hack only works for + # separate gcj builds + # any Ubuntu arch or Debian armhf arch + ifneq (,$(filter Ubuntu-% Debian-armhf,$(distribution)-$(DEB_TARGET_ARCH))) + ifneq (,$(findstring gcj,$(PKGSOURCE))) + CONFARGS += --with-arch=armv6 + else + CONFARGS += --with-arch=armv7-a + endif + CONFARGS += --with-float=$(float_abi) --with-fpu=vfpv3-d16 + endif + ifeq ($(with_arm_thumb),yes) + CONFARGS += --with-mode=thumb + endif +endif + +ifeq ($(DEB_TARGET_GNU_CPU),$(findstring $(DEB_TARGET_GNU_CPU),m68k)) + CONFARGS += --disable-werror +endif +# FIXME: correct fix-warnings.dpatch +ifeq ($(distribution),Ubuntu) + CONFARGS += --disable-werror +endif + +ifneq (,$(findstring sparc-linux,$(DEB_TARGET_GNU_TYPE))) + ifeq ($(biarch64),yes) + CONFARGS += --enable-targets=all + endif +endif + +ifneq (,$(findstring sparc64-linux,$(DEB_TARGET_GNU_TYPE))) + ifneq ($(biarch32),yes) + CONFARGS += --disable-multilib + endif +endif + +ifneq (,$(findstring ia64-linux,$(DEB_TARGET_GNU_TYPE))) + CONFARGS += --with-system-libunwind +endif + +ifneq (,$(findstring sh4-linux,$(DEB_TARGET_GNU_TYPE))) + CONFARGS += --with-multilib-list=m4,m4-nofpu --with-cpu=sh4 +endif + +ifeq ($(DEB_TARGET_ARCH_OS),linux) + ifneq (,$(findstring $(DEB_TARGET_ARCH), alpha powerpc ppc64 s390 s390x sparc sparc64)) + ifeq ($(DEB_TARGET_ARCH),alpha) + glibc_version := $(shell dpkg -s libc6.1 | awk '/^Version:/ {print $$2}') + else + glibc_version := $(shell dpkg -s libc6 | awk '/^Version:/ {print $$2}') + endif + with_ldbl128 := $(shell dpkg --compare-versions $(glibc_version) gt 2.3.99 && echo yes) + ifeq ($(with_ldbl128),yes) + CONFARGS += --with-long-double-128 + endif + endif +endif + +ifneq (,$(filter $(DEB_TARGET_ARCH), amd64 i386 kfreebsd-i386 kfreebsd-amd64)) + ifeq ($(distribution),Ubuntu) + CONFARGS += --with-arch-32=i686 + else + CONFARGS += --with-arch-32=i586 + endif +endif + +ifneq (,$(filter $(DEB_TARGET_ARCH), hurd-i386)) + CONFARGS += --with-arch=i586 +endif + +ifeq ($(DEB_TARGET_ARCH),lpia) + CONFARGS += --with-arch=pentium-m --with-tune=i586 +endif + +ifneq (,$(filter $(DEB_TARGET_ARCH), amd64 i386 hurd-i386 kfreebsd-i386 kfreebsd-amd64)) + CONFARGS += --with-tune=generic +endif + +ifneq (,$(findstring mips-linux,$(DEB_TARGET_GNU_TYPE))) + CONFARGS += --with-mips-plt + CONFARGS += --with-arch-32=mips2 --with-tune-32=mips32 + ifeq ($(biarchn32)-$(biarch64),yes-yes) + CONFARGS += --enable-targets=all + CONFARGS += --with-arch-64=mips3 --with-tune-64=mips64 + endif +endif + +ifneq (,$(findstring mipsel-linux,$(DEB_TARGET_GNU_TYPE))) + CONFARGS += --with-mips-plt + CONFARGS += --with-arch-32=mips2 --with-tune-32=mips32 + ifeq ($(biarchn32)-$(biarch64),yes-yes) + CONFARGS += --enable-targets=all + CONFARGS += --with-arch-64=mips3 --with-tune-64=mips64 + endif +endif + +ifneq (,$(findstring s390-linux,$(DEB_TARGET_GNU_TYPE))) + ifeq ($(biarch64),yes) + CONFARGS += --enable-targets=all + endif +endif + +ifneq (,$(findstring hppa-linux,$(DEB_TARGET_GNU_TYPE))) + CONFARGS += --disable-libstdcxx-pch +endif + +ifeq ($(PKGSOURCE),gcc-snapshot) + ifeq ($(findstring --disable-werror, $(CONFARGS)),) + CONFARGS += --disable-werror + endif + CONFARGS += --enable-checking=yes +else + CONFARGS += --enable-checking=release +endif + +ifneq ($(DEB_CROSS),yes) + CONFARGS += \ + --build=$(DEB_BUILD_GNU_TYPE) \ + --host=$(DEB_HOST_GNU_TYPE) \ + --target=$(TARGET_ALIAS) +else + CONFARGS += \ + --program-prefix=$(TARGET_ALIAS)- \ + --includedir=/$(PF)/$(DEB_TARGET_GNU_TYPE)/include \ + --build=$(DEB_BUILD_GNU_TYPE) \ + --host=$(DEB_HOST_GNU_TYPE) \ + --target=$(TARGET_ALIAS) + ifndef DEB_STAGE + CONFARGS += \ + --with-headers=/$(PF)/$(DEB_TARGET_GNU_TYPE)/include \ + --with-libs=/$(PF)/$(DEB_TARGET_GNU_TYPE)/lib + endif + SET_CROSS_LIB_PATH = LD_LIBRARY_PATH=/lib:/usr/lib:$${LD_LIBRARY_PATH:+$$LD_LIBRARY_PATH:}/$(PF)/$(DEB_TARGET_GNU_TYPE)/lib$${DIRNAME} +endif + +ifeq ($(with_bootstrap),off) + bootstrap_target = +else ifeq ($(with_bootstrap),) + # no profiledbootstrap on the following architectures + # - m68k: we're happy that it builds at all + no_profiled_bs_archs := alpha arm hppa m68k + ifneq (,$(findstring $(DEB_TARGET_GNU_CPU),$(no_profiled_bs_archs))) + bootstrap_target = bootstrap-lean + else + bootstrap_target = profiledbootstrap + endif + ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION)) + bootstrap_target = bootstrap-lean + endif + ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION)) + bootstrap_target = bootstrap-lean + endif + ifeq ($(PKGSOURCE),gcc-snapshot) + bootstrap_target = bootstrap-lean + endif + + # disable profiled bootstrap on slow archs, get to testing first ... + ifeq ($(distribution),Debian) + ifneq (,$(filter $(DEB_TARGET_ARCH), arm armel armhf mips mipsel sparc)) + bootstrap_target = bootstrap-lean + endif + endif + ifeq ($(distribution),Ubuntu) + ifneq (,$(filter $(DEB_TARGET_ARCH), sparc)) + bootstrap_target = bootstrap-lean + endif + endif +endif + bootstrap_target = bootstrap-lean + +DEJAGNU_TIMEOUT=300 +# Increase the timeout for one testrun on slow architectures +ifeq ($(distribution),Debian) + ifneq (,$(findstring $(DEB_TARGET_ARCH),arm armel armhf hppa m68k sparc)) + DEJAGNU_TIMEOUT=600 + else ifneq (,$(findstring $(DEB_TARGET_GNU_CPU),amd64 i386 i486 i686 lpia)) + DEJAGNU_TIMEOUT=180 + endif + ifeq ($(DEB_TARGET_GNU_SYSTEM),gnu) + DEJAGNU_TIMEOUT=900 + endif +else ifeq ($(distribution),Ubuntu) + ifneq (,$(findstring $(DEB_TARGET_ARCH),armel armhf hppa ia64 sparc)) + DEJAGNU_TIMEOUT=600 + else ifneq (,$(findstring $(DEB_TARGET_GNU_CPU),amd64 i386 i486 i686 lpia)) + DEJAGNU_TIMEOUT=180 + endif +endif + +DEJAGNU_RUNS = +ifneq ($(PKGSOURCE),gcc-snapshot) +ifeq ($(with_ssp),yes) + ifneq ($(PKGSOURCE),gcc-snapshot) + DEJAGNU_RUNS += $(if $(filter yes,$(with_ssp_default)),-fno-stack-protector,-fstack-protector) + endif + # FIXME Ubuntu armel buildd hangs + ifneq (,$(findstring arm, $(DEB_TARGET_GNU_CPU))) + DEJAGNU_RUNS = + endif + ifeq ($(distribution),Ubuntu) + # the buildds are just slow ... don't check the non-default + ifneq (,$(findstring $(DEB_TARGET_GNU_CPU),ia64 powerpc sparc)) + DEJAGNU_RUNS = + endif + endif +endif +endif + +ifeq ($(distribution),Ubuntu) + ifneq (,$(findstring arm, $(DEB_TARGET_GNU_CPU))) + ifeq ($(with_arm_thumb),yes) +# DEJAGNU_RUNS += -marm + else + DEJAGNU_RUNS += -mthumb + endif + endif +endif + +ifeq ($(with_32bit_check),yes) + DEJAGNU_RUNS += -m32 +endif +ifeq ($(with_64bit_check),yes) + ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),mips mipsel)) + DEJAGNU_RUNS += -mabi=64 + else + DEJAGNU_RUNS += -m64 + endif +endif +ifeq ($(with_n32bit_check),yes) + DEJAGNU_RUNS += -mabi=n32 +endif + +# gdc is not multilib'd +ifneq (,$(findstring gdc, $(PKGSOURCE))) + DEJAGNU_RUNS = +endif + +# neither is gnat +ifneq (,$(findstring gnat, $(PKGSOURCE))) + DEJAGNU_RUNS = +endif + +ifneq (,$(DEJAGNU_RUNS)) + RUNTESTFLAGS = RUNTESTFLAGS="--target_board=unix\{,$(subst $(SPACE),$(COMMA),$(strip $(DEJAGNU_RUNS)))\}" +endif + +# PF is the installation prefix for the package without the leading slash. +# It's "usr" for gcc releases. +ifneq (,$(PF)) + # use value set in the environment +else ifeq ($(PKGSOURCE),gcc-snapshot) + PF = usr/lib/gcc-snapshot +else + PF = usr +endif + +# PFL is the installation prefix with DEB_TARGET_GNU_TYPE attached for cross builds +ifeq ($(DEB_CROSS),yes) + PFL = $(PF)/$(DEB_TARGET_GNU_TYPE) +else + PFL = $(PF) +endif + +# RPF is the base prefix or installation prefix with DEB_TARGET_GNU_TYPE attached for cross builds +ifeq ($(DEB_CROSS),yes) + RPF = $(PF)/$(DEB_TARGET_GNU_TYPE) +else + RPF = +endif + +ifeq ($(with_multiarch_lib),yes) + ifeq ($(DEB_CROSS),yes) + libdir = lib + else + libdir = lib/$(DEB_HOST_MULTIARCH) + endif +else + libdir = lib +endif +# /usr/libexec doesn't follow the FHS +ifeq ($(PKGSOURCE),gcc-snapshot) + libexecdir = $(PF)/libexec + spulibexecdir = $(PF)/libexec +else + libexecdir = $(PF)/$(libdir) + spulibexecdir = $(PF)/$(libdir) +endif +buildlibdir = $(builddir)/$(TARGET_ALIAS) + +ifeq ($(with_common_gcclibdir),yes) + gcc_lib_dir = $(PF)/$(libdir)/gcc/$(TARGET_ALIAS)/$(BASE_VERSION) + gcc_lexec_dir = $(libexecdir)/gcc/$(TARGET_ALIAS)/$(BASE_VERSION) + gcc_spu_lib_dir = $(PF)/spu/lib/gcc/spu/$(BASE_VERSION) + gcc_spu_lexec_dir = $(spulibexecdir)/gcc/spu/$(BASE_VERSION) +else + gcc_lib_dir = $(PF)/$(libdir)/gcc/$(TARGET_ALIAS)/$(GCC_VERSION) + gcc_lexec_dir = $(libexecdir)/gcc/$(TARGET_ALIAS)/$(GCC_VERSION) + gcc_spu_lib_dir = $(PF)/spu/lib/gcc/spu/$(GCC_VERSION) + gcc_spu_lexec_dir = $(spulibexecdir)/gcc/spu/$(GCC_VERSION) +endif + +lib32 = $(PF)/lib32 +lib64 = lib64 +libn32 = lib32 + +p_l= $(1)$(cross_lib_arch) +p_d= $(1)-dbg$(cross_lib_arch) +d_l= debian/$(p_l) +d_d= debian/$(p_d) + +ifeq ($(DEB_CROSS),yes) + usr_lib = $(PFL)/lib +else + usr_lib = $(PFL)/$(libdir) +endif +usr_lib32 = $(PFL)/lib32 +usr_libn32 = $(PFL)/lib32 +usr_lib64 = $(PFL)/lib64 + +gcc_lib_dir32 = $(gcc_lib_dir)/$(biarch32subdir) +gcc_lib_dirn32 = $(gcc_lib_dir)/$(biarchn32subdir) +gcc_lib_dir64 = $(gcc_lib_dir)/$(biarch64subdir) + +libgcc_dir = $(RPF)/$(libdir) +# yes, really; lib32gcc_s ends up in usr +libgcc_dir32 = $(PFL)/lib32 +libgcc_dirn32 = $(RPF)/lib32 +libgcc_dir64 = $(RPF)/lib64 + +# install_gcc_lib(lib,soname,flavour,package) +define install_gcc_lib + mv $(d)/$(usr_lib$(3))/$(1)*.a debian/$(4)/$(gcc_lib_dir$(3))/ + rm -f $(d)/$(usr_lib$(3))/$(1)*.{la,so} + dh_link -p$(4) \ + /$(usr_lib$(3))/$(1).so.$(2) /$(gcc_lib_dir$(3))/$(1).so + +endef + +checkdirs = $(builddir) +ifeq ($(with_separate_libgcj),yes) + ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION)) + ifneq ($(with_standalone_gcj),yes) + checkdirs = $(buildlibdir)/libffi $(buildlibdir)/libjava + endif + endif +endif +ifeq ($(with_separate_gnat),yes) + ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION)) + checkdirs = $(builddir)/gcc + endif +endif + +ifneq ($(DEB_CROSS),yes) + ifneq ($(PKGSOURCE),gcc-snapshot) + cxx_inc_dir = $(PF)/include/c++/$(BASE_VERSION) + else + cxx_inc_dir = $(PF)/include/c++/$(GCC_VERSION) + endif +else + cxx_inc_dir = $(PF)/$(TARGET_ALIAS)/include/c++/$(GCC_VERSION) +endif + +default: build + +configure: $(configure_dependencies) + +$(configure_dummy_stamp): + touch $(configure_dummy_stamp) + +$(configure_stamp): + dh_testdir + : # give information about the build process + @echo "------------------------ Build process variables ------------------------" + @echo "Number of parallel processes used for the build: $(USE_CPUS)" + @echo "Package source: $(PKGSOURCE)" + @echo "GCC version: $(GCC_VERSION)" + @echo "Base Debian version: $(BASE_VERSION)" + @echo -e "Configured with: $(subst ___, ,$(foreach i,$(CONFARGS),$(i)\n\t))" +ifeq ($(DEB_CROSS),yes) + @echo "Building cross compiler for $(DEB_TARGET_ARCH)" +endif + @echo "Using shell $(SHELL)" + @echo "Architecture: $(DEB_TARGET_ARCH) (GNU: $(TARGET_ALIAS))" + @echo "CPPFLAGS: $(CPPFLAGS)" + @echo "CFLAGS: $(CFLAGS)" + @echo "LDFLAGS: $(LDFLAGS)" + @echo "BOOT_CFLAGS: $(BOOT_CFLAGS)" + @echo "DEBIAN_BUILDARCH: $(DEBIAN_BUILDARCH)" + @echo "Install prefix: /$(PF)" +ifeq ($(biarchn32)-$(biarch64),yes-yes) + @echo "Will build the triarch compilers (o32/n32/64, defaulting to o32)" +else + ifeq ($(biarch64),yes) + @echo "Will build the biarch compilers (32/64, defaulting to 32bit)" + else + ifeq ($(biarch32),yes) + @echo "Will build the biarch compilers (64/32, defaulting to 64bit)" + else + @echo "Will not build the biarch compilers" + endif + endif +endif + +ifeq ($(with_cxx),yes) + @echo "Will build the C++ compiler" +else + @echo "Will not build the C++ compiler: $(with_cxx)" +endif +ifeq ($(with_objc),yes) + @echo "Will build the ObjC compiler." + ifeq ($(with_objc_gc),yes) + @echo "Will build the extra ObjC runtime for garbage collection." + else + @echo "Will not build the extra ObjC runtime for garbage collection." + endif +else + @echo "Will not build the ObjC compiler: $(with_objc)" +endif +ifeq ($(with_objcxx),yes) + @echo "Will build the Obj-C++ compiler" +else + @echo "Will not build the Obj-C++ compiler: $(with_objcxx)" +endif +ifeq ($(with_fortran),yes) + @echo "Will build the Fortran 95 compiler." +else + @echo "Will not build the Fortran 95 compiler: $(with_fortran)" +endif +ifeq ($(with_java),yes) + @echo "Will build the Java compiler." +else + @echo "Will not build the Java compiler: $(with_java)" +endif +ifeq ($(with_ada),yes) + @echo "Will build the Ada compiler." + ifeq ($(with_libgnat),yes) + @echo "Will build the shared Ada libraries." + else + @echo "Will not build the shared Ada libraries." + endif +else + @echo "Will not build the Ada compiler: $(with_ada)" +endif +ifeq ($(with_d),yes) + @echo "Will build the D compiler" +else + @echo "Will not build the D compiler: $(with_d)" +endif +ifeq ($(with_ssp),yes) + @echo "Will build with SSP support." +else + @echo "Will build without SSP support: $(with_ssp)" +endif +ifeq ($(with_check),yes) + @echo "Will run the testsuite." + ifeq ($(biarch64),yes) + ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),mips mipsel)) + @echo 'Will run the testsuite with -mabi=64: $(with_64bit_check)' + else + @echo 'Will run the testsuite with -m64: $(with_64bit_check)' + endif + endif + ifeq ($(biarch32),yes) + @echo 'Will run the testsuite with -m32: $(with_32bit_check)' + endif + ifeq ($(biarchn32),yes) + @echo 'Will run the testsuite with -mabi=n32: $(with_n32bit_check)' + endif +else + @echo "Will not run the testsuite: $(with_check)" +endif +ifeq ($(with_nls),yes) + @echo "Will enable national language support." +else + @echo "Will disable national language support: $(with_nls)" +endif + @echo "-----------------------------------------------------------------------------" + @echo "" +ifeq ($(with_check),yes) + @if echo "spawn true" | /usr/bin/expect -f - >/dev/null; then \ + : ; \ + else \ + echo "expect is failing on your system with the above error, which means the GCC"; \ + echo "testsuite will fail. Please resolve the above issues and retry the build."; \ + echo "-----------------------------------------------------------------------------"; \ + exit 1; \ + fi +endif + rm -f $(configure_stamp) $(build_stamp) + cp $(patch_stamp) debian/README.Debian.$(DEB_TARGET_ARCH) + + rm -rf $(builddir) + mkdir $(builddir) + + : # configure + cd $(builddir) \ + && $(SET_PATH) \ + CC="$(CC)" \ + $(SET_SHELL) \ + LD_LIBRARY_PATH=$${LD_LIBRARY_PATH:+$$LD_LIBRARY_PATH:}$(builddir)/gcc/ada/rts \ + ../src/configure $(subst ___, ,$(CONFARGS)) + + touch $(configure_stamp) + +build: $(build_dependencies) + +$(build_dummy_stamp): + touch $(build_dummy_stamp) + +$(build_locale_stamp): +ifeq ($(locale_data)-$(with_cxx),generate-yes) + : # build locales needed by libstdc++ testsuite + rm -rf locales + mkdir locales + - sh debian/locale-gen +endif + touch $(build_locale_stamp) + + +$(build_stamp): $(configure_stamp) $(build_locale_stamp) + dh_testdir + rm -f bootstrap-protocol +# DEB_CROSS is never set if REVERSE_CROSS is set and vice-versa. +# DEB_CROSS build +ifeq ($(DEB_CROSS),yes) + : # build cross compiler for $(TARGET_ALIAS) + ( \ + set +e; \ + $(SET_PATH) \ + $(SET_LOCPATH) \ + $(MAKE) -C $(builddir) $(NJOBS) \ + CC="$(CC)" \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) \ + ; \ + echo $$? > status; \ + ) 2>&1 | tee bootstrap-protocol + s=`cat status`; rm -f status; test $$s -eq 0 +else + # REVERSE_CROSS build + ifeq ($(REVERSE_CROSS),yes) + : # build cross compiler for $(TARGET_ALIAS) + ( \ + set +e; \ + $(SET_PATH) \ + $(SET_LOCPATH) \ + $(MAKE) -C $(builddir) $(NJOBS) \ + CC="$(CC)" \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) \ + ; \ + echo $$? > status; \ + ) 2>&1 | tee bootstrap-protocol + s=`cat status`; rm -f status; test $$s -eq 0 +else + # Native build + ifeq ($(with_java),yes) + mkdir -p bin + ln -sf /usr/bin/fastjar bin/jar + ifeq ($(with_native_ecj),yes) + : # prepare the standalone ecj jar + cp /usr/share/java/ecj.jar $(srcdir)/ecj-standalone.jar + zip -d $(srcdir)/ecj-standalone.jar 'org/eclipse/jdt/core/JDTCompilerAdapter*' + endif + ifeq ($(with_java_maintainer_mode),yes) + ( \ + echo '#!/bin/sh'; \ + echo 'exec gij-4.3 -cp /usr/share/java/ecj.jar org.eclipse.jdt.internal.compiler.batch.GCCMain "$$@"'; \ + ) > bin/ecj1 + chmod +x bin/ecj1 + : # If we don't have gjavah in PATH, try to build it with the old gij + mkdir -p bin + if [ -x /usr/bin/gjavah-4.3 ]; then \ + ln -sf /usr/bin/gjavah-4.3 bin/gjavah; \ + elif [ -x bin/gjavah ]; then \ + : ; \ + else \ + mkdir -p $(builddir)/java_hacks; \ + cd $(builddir)/java_hacks; \ + cp -a $(srcdir)/libjava/classpath/tools/external external; \ + mkdir -p gnu/classpath/tools; \ + cp -a $(srcdir)/libjava/classpath/tools/gnu/classpath/tools/{common,javah,getopt} \ + gnu/classpath/tools/; \ + cp -a $(srcdir)/libjava/classpath/resource/gnu/classpath/tools/common/Messages.properties \ + gnu/classpath/tools/common; \ + cd external/asm; \ + for i in `find . -name \*.java`; do gcj-4.3 --encoding ISO-8859-1 -C $$i -I.; done; \ + cd ../..; \ + for i in `find gnu -name \*.java`; do gcj-4.3 -C $$i -I. -Iexternal/asm/; done; \ + gcj-4.3 -findirect-dispatch -O2 -fmain=gnu.classpath.tools.javah.Main \ + -I. -Iexternal/asm/ `find . -name \*.class` -o $(PWD)/bin/gjavah.real; \ + ( \ + echo '#!/bin/sh'; \ + echo 'export CLASSPATH='`pwd`'$${CLASSPATH:+:$$CLASSPATH}'; \ + echo 'exec $(PWD)/bin/gjavah.real "$$@"'; \ + ) > $(PWD)/bin/gjavah; \ + chmod +x $(PWD)/bin/gjavah; \ + fi + endif + endif + : # build native compiler + ( \ + set +e; \ + $(SET_PATH) \ + $(SET_SHELL) \ + $(SET_LOCPATH) \ + $(MAKE) -C $(builddir) $(NJOBS) $(bootstrap_target) \ + CC="$(CC)" \ + $(CFLAGS_TO_PASS) \ + $(STAGE1_CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) \ + ; \ + echo $$? > status; \ + ) 2>&1 | tee bootstrap-protocol + s=`cat status`; rm -f status; test $$s -eq 0 +endif +endif + -chmod 755 $(srcdir)/contrib/warn_summary + if [ -x $(srcdir)/contrib/warn_summary ]; then \ + rm -f bootstrap-summary; \ + $(srcdir)/contrib/warn_summary bootstrap-protocol \ + > bootstrap-summary; \ + fi + + touch $(build_stamp) + +ifeq ($(versioned_packages),yes) + hppa64_configure_flags += --program-suffix=-$(BASE_VERSION) +endif + +ifeq ($(DEB_CROSS),yes) + CC_for_hppa64_cross = $(CC) +else + CC_for_hppa64_cross = $(builddir)/gcc/xgcc -B$(builddir)/gcc/ +endif + +$(configure_hppa64_stamp): $(build_stamp) + dh_testdir + rm -f $(configure_hppa64_stamp) $(build_hppa64_stamp) + rm -rf $(builddir_hppa64) + mkdir $(builddir_hppa64) + : # configure + cd $(builddir_hppa64) && \ + $(SET_PATH) \ + $(SET_SHELL) \ + CC="$(CC_for_hppa64_cross)" \ + ../src/configure \ + --enable-languages=c \ + --prefix=/$(PF) \ + --libexecdir=/$(libexecdir) \ + --enable-multiarch \ + $(MULTIARCH_CONFARG) \ + --disable-shared \ + --disable-nls \ + --disable-threads \ + --disable-libgomp \ + --disable-libmudflap \ + --disable-libssp \ + --with-system-zlib \ + --with-as=/usr/bin/hppa64-linux-gnu-as \ + --with-ld=/usr/bin/hppa64-linux-gnu-ld \ + --includedir=/usr/hppa64-linux-gnu/include \ + --build=$(DEB_BUILD_GNU_TYPE) \ + --host=$(DEB_HOST_GNU_TYPE) \ + --target=hppa64-linux-gnu + touch $(configure_hppa64_stamp) + +$(build_hppa64_stamp): $(configure_hppa64_stamp) + $(SET_PATH) \ + $(SET_SHELL) \ + $(SET_LOCPATH) \ + LD_LIBRARY_PATH=$${LD_LIBRARY_PATH:+$$LD_LIBRARY_PATH:}$(builddir)/gcc \ + $(MAKE) -C $(builddir_hppa64) $(NJOBS) \ + CC="$(CC_for_hppa64_cross)" \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) + touch $(build_hppa64_stamp) + +$(configure_neon_stamp): $(build_stamp) + dh_testdir + rm -f $(configure_neon_stamp) $(build_neon_stamp) + rm -rf $(builddir_neon) + mkdir $(builddir_neon) + : # configure + cd $(builddir_neon) && \ + $(SET_PATH) \ + $(SET_SHELL) \ + CC="$(builddir)/gcc/xgcc -B$(builddir)/gcc/" \ + ../src/configure \ + --disable-bootstrap \ + --enable-languages=c,c++,objc,fortran \ + --prefix=/$(PF) \ + --libexecdir=/$(libexecdir) \ + --program-suffix=-$(BASE_VERSION) \ + --enable-multiarch \ + $(MULTIARCH_CONFARG) \ + --disable-nls \ + --disable-libmudflap \ + --with-arch=armv7-a --with-tune=cortex-a8 \ + --with-float=$(float_abi) --with-fpu=neon \ + --host=arm-linux-gnueabi \ + --build=arm-linux-gnueabi \ + --target=arm-linux-gnueabi + touch $(configure_neon_stamp) + +$(build_neon_stamp): $(configure_neon_stamp) + $(SET_PATH) \ + $(SET_SHELL) \ + $(SET_LOCPATH) \ + $(MAKE) -C $(builddir_neon) $(NJOBS) \ + CC="$(builddir)/gcc/xgcc -B$(builddir)/gcc/" \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) + touch $(build_neon_stamp) + +$(configure_ia6432_stamp): $(build_stamp) + dh_testdir + rm -f $(configure_ia6432_stamp) $(build_ia6432_stamp) + rm -rf $(builddir_ia6432) + mkdir $(builddir_ia6432) + : # configure + cd $(builddir_ia6432) && \ + $(SET_PATH) \ + $(SET_SHELL) \ + CC="$(builddir)/gcc/xgcc -B$(builddir)/gcc/" \ + ../src/configure \ + --enable-languages=c \ + --prefix=/$(PF) \ + --libexecdir=/$(libexecdir) \ + --enable-multiarch \ + $(MULTIARCH_CONFARG) \ + --disable-nls \ + --disable-libmudflap \ + --program-suffix=-$(BASE_VERSION) \ + --host=ia64-linux-gnu \ + --build=ia64-linux-gnu \ + --target=i486-linux-gnu + touch $(configure_ia6432_stamp) + +$(build_ia6432_stamp): $(configure_ia6432_stamp) + $(SET_PATH) \ + $(SET_SHELL) \ + $(MAKE) -C $(builddir_ia6432) $(NJOBS) \ + CC="$(builddir)/gcc/xgcc -B$(builddir)/gcc/" \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) + touch $(build_ia6432_stamp) + +spu_configure_args = \ + --enable-languages=c,c++,fortran \ + --prefix=/$(PF) \ + --libexecdir=/$(spulibexecdir) \ + --disable-shared \ + --disable-nls \ + --disable-threads \ + --enable-checking=release \ + --disable-libssp \ + --with-system-zlib \ + --with-newlib \ + --program-prefix=spu- \ + --with-as=/usr/bin/spu-as \ + --with-ar=/usr/bin/spu-ar \ + --with-ld=/usr/bin/spu-ld + +# FIXME: --with-sysroot=/usr/spu breaks libgfortran build +#ifeq ($(PKGSOURCE),gcc-snapshot) +# spu_configure_args += \ +# --with-sysroot=/usr/spu +#else + spu_configure_args += \ + --includedir=/usr/spu/include \ + --libdir=/usr/spu/lib +#endif + +spu_configure_args += \ + --host=$(DEB_HOST_GNU_TYPE) \ + --build=$(DEB_BUILD_GNU_TYPE) \ + --target=spu + +$(configure_spu_stamp): $(src_spu_stamp) $(build_stamp) + dh_testdir + rm -f $(configure_spu_stamp) $(build_spu_stamp) + rm -rf $(builddir_spu) + mkdir $(builddir_spu) + : # configure + cd $(builddir_spu) && \ + $(SET_PATH) \ + $(SET_SHELL) \ + CC="$(builddir)/gcc/xgcc -B$(builddir)/gcc/" \ + ../src-spu/configure $(spu_configure_args) + touch $(configure_spu_stamp) + +$(build_spu_stamp): $(configure_spu_stamp) + $(SET_PATH) \ + $(SET_SHELL) \ + $(SET_LOCPATH) \ + $(MAKE) -C $(builddir_spu) $(NJOBS) \ + CC="$(builddir)/gcc/xgcc -B$(builddir)/gcc/" \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) + touch $(build_spu_stamp) + + +MANUALS = \ + $(srcdir)/gcc/doc/cpp.texi \ + $(srcdir)/gcc/doc/cppinternals.texi \ + $(srcdir)/gcc/doc/gcc.texi \ + $(srcdir)/gcc/doc/gccint.texi +ifeq ($(with_fortran),yes) + MANUALS += $(srcdir)/gcc/fortran/gfortran.texi +endif +ifeq ($(with_java),yes) + MANUALS += $(srcdir)/gcc/java/gcj.texi +endif +ifeq ($(with_ada),yes) + MANUALS += \ + $(builddir)/gcc/doc/gnat_ugn.texi \ + $(srcdir)/gcc/ada/gnat_rm.texi \ + $(srcdir)/gcc/ada/gnat-style.texi +endif +ifeq ($(with_gomp),yes) + MANUALS += $(srcdir)/libgomp/libgomp.texi +endif + +html-docs: $(build_html_stamp) +#$(build_html_stamp): html-texi2html +#$(build_html_stamp): html-makeinfo +$(build_html_stamp): html-makeinfo-nosplit + +html-texi2html: + rm -rf html $(builddir)/gcc/html + mkdir $(builddir)/gcc/html + ln -s $(builddir)/gcc/html html + cd $(builddir)/gcc; \ + for manual in $(MANUALS); do \ + outname=`basename $${manual} .texi`; \ + echo "generating $$outname ..."; \ + texi2html -number -split chapter \ + -I $(srcdir)/gcc/doc/include \ + -I $(srcdir)/gcc/p/doc \ + -I $(srcdir)/gcc/p/doc/generated \ + -I `dirname $${manual}` \ + -I $(builddir)/gcc \ + -subdir html \ + $${manual}; \ + done + +html-makeinfo: + rm -rf html + mkdir html + cd $(builddir)/gcc; \ + for manual in $(MANUALS); do \ + manual=`find $(srcdir) -name $${file}.texi`; \ + outname=`basename $${manual} .texi`; \ + echo "generating $$outname ..."; \ + if [ "$${manual}" ]; then \ + makeinfo --html --number-sections \ + -I $(srcdir)/gcc/doc/include -I `dirname $${manual}` \ + -I $(srcdir)/gcc/p/doc \ + -I $(srcdir)/gcc/p/doc/generated \ + -I $(builddir)/gcc \ + -o $${outname} \ + $${manual}; \ + fi; \ + done + +html-makeinfo-nosplit: + rm -rf html + mkdir html + cd $(builddir)/gcc; \ + for manual in $(MANUALS); do \ + outname=`basename $${manual} .texi`.html; \ + echo "generating $$outname ..."; \ + makeinfo --html --number-sections --no-split \ + -I $(srcdir)/gcc/doc/include -I `dirname $${manual}` \ + -I $(srcdir)/gcc/p/doc \ + -I $(srcdir)/gcc/p/doc/generated \ + -I $(builddir)/gcc \ + -o $(PWD)/html/$${outname} \ + $${manual}; \ + done + +# start the script only on architectures known to have slow autobuilders ... +logwatch_archs := alpha arm m68k mips mipsel sparc +ifeq ($(DEB_HOST_GNU_CPU), $(findstring $(DEB_HOST_GNU_CPU),$(logwatch_archs))) + start_logwatch = yes +endif +ifeq ($(DEB_HOST_GNU_SYSTEM),gnu) + start_logwatch = yes +endif + +stamps/mauve-build: stamps/build + rm -rf mauve + mkdir -p mauve +ifeq ($(with_mauve_check),yes) + tar xf $(wildcard /usr/src/mauve*.tar.*) + cd mauve \ + && aclocal \ + && automake \ + && autoconf2.59 \ + && PATH=$(CURDIR)/$(sdkimg)/bin:$$PATH ./configure --host=$(DEB_HOST_GNU_TYPE) --build=$(DEB_BUILD_GNU_TYPE) + PATH=$(CURDIR)/$(sdkimg)/bin:$$PATH $(MAKE) -C mauve +endif + touch $@ + +stamps/mauve-check: stamps/build stamps/mauve-build +ifeq ($(with_mauve_check),yes) + -cd mauve && \ + JAVA_HOME=$(CURDIR)/$(sdkimg) \ + PATH=$(CURDIR)/$(sdkimg)/bin:$$PATH \ + xvfb-run -s "-extension GLX" java Harness \ + -vm $(CURDIR)/$(sdkimg)/bin/java \ + -file $(CURDIR)/debian/mauve_tests \ + -timeout 30000 2>&1 \ + | tee mauve_output + @sleep 5 +else + echo "mauve testsuite not run for this build" > mauve/mauve_output +endif + touch $@ + +check: $(check_stamp) # $(if $(filter yes, $(with_java)),stamps/05-build-mauve-stamp) #$(check_inst_stamp) +$(check_stamp): $(build_stamp) $(build_locale_stamp) + rm -f test-protocol + + -chmod 755 $(srcdir)/contrib/test_summary +ifneq ($(with_common_libs),yes) + : # libstdc++6 built from newer gcc-4.x source, run testsuite against the installed lib + + sed 's/-L[^ ]*//g' $(buildlibdir)/libstdc++-v3/scripts/testsuite_flags \ + > $(buildlibdir)/libstdc++-v3/scripts/testsuite_flags.installed + -$(ULIMIT_M); \ + set +e; \ + for d in $(buildlibdir)/libstdc++-v3/testsuite; do \ + echo "Running testsuite in $$d ..."; \ + TEST_INSTALLED=1 \ + $(SET_SHELL) \ + $(SET_LOCPATH) \ + $(SET_PATH) \ + DEJAGNU_TIMEOUT=$(DEJAGNU_TIMEOUT) \ + DEB_GCC_NO_O3=1 \ + $(MAKE) -k -C $$d $(NJOBS) check $(RUNTESTFLAGS); \ + done 2>&1 | tee test-protocol2 + + BOOT_CFLAGS="$(BOOT_CFLAGS)" \ + $(srcdir)/contrib/test_summary -m "$(S_EMAIL)" > raw-test-summary + -( \ + sed -n '/^Mail/s/.*"\([^"][^"]*\)".*/\1/p' raw-test-summary; \ + awk '/^cat/, /^EOF/' raw-test-summary | grep -v EOF; \ + ) > libstdc++-test-summary + echo 'BEGIN installed libstdc++-v3 test-summary' + cat libstdc++-test-summary + echo 'END installed libstdc++-v3 test-summary' + find $(buildlibdir)/libstdc++-v3/testsuite -name '*.log' -o -name '*.sum' \ + | xargs -r rm -f +endif + +ifeq ($(start_logwatch),yes) + : # start logwatch script for regular output during test runs + chmod +x debian/logwatch.sh + -debian/logwatch.sh -t 900 -p $(builddir)/logwatch.pid \ + -m '\ntestsuite still running ...\n' \ + test-protocol \ + $(builddir)/gcc/testsuite/gcc/gcc.log \ + $(builddir)/gcc/testsuite/g++/g++.log \ + $(builddir)/gcc/testsuite/gfortran/gfortran.log \ + $(builddir)/gcc/testsuite/objc/objc.log \ + $(builddir)/gcc/testsuite/obj-c++/obj-c++.log \ + $(builddir)/gcc/testsuite/gnat/gnat.log \ + $(builddir)/gcc/testsuite/ada/acats/acats.log \ + $(builddir)/gcc/testsuite/gfortran/gfortran.log \ + $(builddir)/gcc/p/test/test_log \ + $(buildlibdir)/libstdc++-v3/testsuite/libstdc++-v3.log \ + $(buildlibdir)/libjava/testsuite/libjava.log \ + $(buildlibdir)/libmudflap/testsuite/libmudflap.log \ + $(buildlibdir)/libgomp/testsuite/libgomp.log \ + $(buildlibdir)/libffi/testsuite/libffi.log \ + & +endif + +ifeq ($(with_ada),yes) + chmod +x debian/acats-killer.sh + -debian/acats-killer.sh -p $(builddir)/acats-killer.pid \ + $(builddir)/gcc/testsuite/ada/acats/acats.log \ + $(builddir)/gcc/testsuite/g++.log \ + & +endif + + -$(ULIMIT_M); \ + set +e; \ + for d in $(checkdirs); do \ + echo "Running testsuite in $$d ..."; \ + $(SET_SHELL) \ + $(SET_LOCPATH) \ + $(SET_PATH) \ + EXTRA_TEST_PFLAGS=-g0 \ + DEJAGNU_TIMEOUT=$(DEJAGNU_TIMEOUT) \ + DEB_GCC_NO_O3=1 \ + $(MAKE) -k -C $$d $(NJOBS) check $(RUNTESTFLAGS); \ + done 2>&1 | tee test-protocol + + -ps aux | fgrep logwatch | fgrep -v fgrep + -if [ -f $(builddir)/logwatch.pid ]; then \ + kill -1 `cat $(builddir)/logwatch.pid`; \ + sleep 1; \ + kill -9 `cat $(builddir)/logwatch.pid`; \ + rm -f $(builddir)/logwatch.pid; \ + fi + -ps aux | fgrep logwatch | fgrep -v fgrep + +ifeq ($(with_ada),yes) + -if [ -f $(builddir)/acats-killer.pid ]; then \ + kill -1 `cat $(builddir)/acats-killer.pid`; \ + sleep 1; \ + kill -9 `cat $(builddir)/acats-killer.pid`; \ + rm -f $(builddir)/acats-killer.pid; \ + fi +endif + + : # running the libjava testsuite alone is missing this information + $(builddir)/gcc/xgcc -B$(builddir)/gcc/ -v > $(builddir)/compiler_version.sum 2>&1 + + if [ -x $(srcdir)/contrib/test_summary ]; then \ + rm -f test-summary; \ + ( \ + cd $(builddir); \ + echo '' > ts-include; \ + echo '' >> ts-include; \ + if [ -f $(builddir)/gcc/.bad_compare ]; then \ + echo 'Bootstrap comparison failure:' >> ts-include; \ + cat $(builddir)/gcc/.bad_compare >> ts-include; \ + echo '' >> ts-include; \ + echo '' >> ts-include; \ + fi; \ + echo "Build Dependencies:" >> ts-include; \ + dpkg -l g++-* binutils* `echo '$(LIBC_DEP)' | awk '{print $$1}'` \ + libgmp3-dev libmpfr-dev libmpc-dev libppl0.10-dev libcloog-ppl-dev \ + | fgrep -v '' >> ts-include; \ + echo '' >> ts-include; \ + cat ../$(patch_stamp) >> ts-include; \ + BOOT_CFLAGS="$(BOOT_CFLAGS)" \ + $(srcdir)/contrib/test_summary \ + -i ts-include -m "$(S_EMAIL)" \ + ) > raw-test-summary; \ + if [ -n "$(testsuite_tarball)" ]; then \ + echo "Test suite used: $(testsuite_srcdir)" > test-summary; \ + echo " Do not interpret the results on its own" >> test-summary; \ + echo " but compare them with the results from" >> test-summary; \ + echo " the gcc-snapshot package." >> test-summary; \ + fi; \ + sed -n '/^Mail/s/.*"\([^"][^"]*\)".*/\1/p' raw-test-summary \ + >> test-summary; \ + awk '/^cat/, /^EOF/' raw-test-summary | grep -v EOF >> test-summary; \ + if [ -f bootstrap-summary -a "$(bootstrap_target)" != profiledbootstrap ]; then \ + echo '' >> test-summary; \ + cat bootstrap-summary >> test-summary; \ + fi; \ + echo 'BEGIN test-summary'; \ + cat test-summary; \ + echo 'END test-summary'; \ + fi + + touch $(check_stamp) + +$(check_inst_stamp): $(check_stamp) + rm -f test-inst-protocol + +ifeq ($(start_logwatch),yes) + : # start logwatch script for regular output during test runs + chmod +x debian/logwatch.sh + -debian/logwatch.sh -t 900 -p $(builddir)/logwatch-inst.pid \ + -m '\ntestsuite (3.3) still running ...\n' \ + test-inst-protocol \ + check-inst/{gcc,g++,g77,objc}.log \ + & +endif + + rm -rf check-inst + mkdir check-inst + + echo "Running testsuite ..." + -$(ULIMIT_M) ; \ + $(SET_SHELL) \ + $(SET_LOCPATH) \ + EXTRA_TEST_PFLAGS=-g0 \ + DEJAGNU_TIMEOUT=$(DEJAGNU_TIMEOUT) \ + cd check-inst && $(srcdir)/contrib/test_installed \ + --with-gcc=gcc-3.3 --with-g++=g++-3.3 --with-g77=g77-3.3 \ + 2>&1 | tee test-inst-protocol + + -ps aux | fgrep logwatch | fgrep -v fgrep + if [ -f $(builddir)/logwatch-inst.pid ]; then \ + kill -1 `cat $(builddir)/logwatch-inst.pid`; \ + else \ + true; \ + fi + -ps aux | fgrep logwatch | fgrep -v fgrep + + -chmod 755 $(srcdir)/contrib/test_summary + if [ -x $(srcdir)/contrib/test_summary ]; then \ + rm -f test-inst-summary; \ + ( \ + cd check-inst; \ + echo '' > ts-include; \ + echo '' >> ts-include; \ + echo "Build Dependencies:" >> ts-include; \ + dpkg -l g++-* binutils* `echo '$(LIBC_DEP)' | awk '{print $$1}'` \ + libgmp3-dev libmpfr-dev libmpc-dev libppl0.10-dev libcloog-ppl-dev \ + | fgrep -v '' >> ts-include; \ + echo '' >> ts-include; \ + echo 'Results for the installed GCC-3.3 compilers' >> ts-include; \ + $(srcdir)/contrib/test_summary \ + -i ts-include -m "$(S_EMAIL)" \ + ) > raw-test-inst-summary; \ + sed -n '/^Mail/s/.*"\([^"][^"]*\)".*/\1/p' raw-test-inst-summary \ + >> test-inst-summary; \ + awk '/^cat/, /^EOF/' raw-test-inst-summary \ + | grep -v EOF >> test-inst-summary; \ + echo 'BEGIN test-installed-summary'; \ + cat test-inst-summary; \ + echo 'END test-installed-summary'; \ + fi + + chmod 755 debian/reduce-test-diff.awk + if diff -u test-inst-summary test-summary \ + | debian/reduce-test-diff.awk > diff-summary; \ + then \ + mv -f diff-summary testsuite-comparision; \ + else \ + ( \ + echo "WARNING: New failures in gcc-3.4 compared to gcc-3.3"; \ + echo ''; \ + cat diff-summary; \ + ) > testsuite-comparision; \ + rm -f diff-summary; \ + fi + touch $(check_inst_stamp) + +clean: debian/control + dh_testdir + rm -f pxxx status + rm -f *-summary *-protocol testsuite-comparision summary-diff + if [ -f $(srcdir)/gcc/p/config-lang.in.debian ]; then \ + mv -f $(srcdir)/gcc/p/config-lang.in.debian $(srcdir)/gcc/p/config-lang.in; \ + else true; fi + rm -f $(srcdir)/gcc/po/*.gmo + rm -f debian/lib{gcc,gcj,objc,stdc++}{-v3,[0-9]}*.{{pre,post}{inst,rm},shlibs} + fs=`echo debian/*BV* debian/*GCJ* debian/*CXX* debian/*LC* debian/*MF* | sort -u`; \ + for f in $$fs; do \ + [ -f $$f ] || continue; \ + f2=$$(echo $$f \ + | sed 's/BV/$(BASE_VERSION)/;s/CXX/$(CXX_SONAME)/;s/LGCJ/$(PKG_LIBGCJ_EXT)/;s/GCJ/$(PKG_GCJ_EXT)/;s/LC/$(GCC_SONAME)/;s/MF/$(MUDFLAP_SONAME)/;s/-CRB/$(cross_bin_arch)/;s/\.in$$//'); \ + rm -f $$f2; \ + done + rm -f debian/shlibs.local debian/substvars.local + rm -f debian/*.debhelper + -[ -d debian/bugs ] && $(MAKE) -C debian/bugs clean + rm -f debian/README.libstdc++-baseline debian/README.Bugs debian/README.Debian.* + rm -f debian/lib*gcj-bc.shlibs + rm -rf bin locales share + rm -rf check-inst + rm -rf .pc + dh_clean + +# ----------------------------------------------------------------------------- +# some abbrevations for the package names and directories; +# p_XXX is the package name, d_XXX is the package directory +# these macros are only used in the binary-* targets. + +ifeq ($(versioned_packages),yes) + pkg_ver := -$(BASE_VERSION) +endif + +ifneq ($(DEB_CROSS),yes) + p_base = gcc$(pkg_ver)-base + p_gcc = gcc$(pkg_ver) + p_cpp = cpp$(pkg_ver) + p_cppd = cpp$(pkg_ver)-doc + p_cxx = g++$(pkg_ver) + p_doc = gcc$(pkg_ver)-doc + p_lgcc = libgcc$(GCC_SONAME) +else + # only triggered if DEB_CROSS set + p_base = gcc$(pkg_ver)$(cross_bin_arch)-base + p_cpp = cpp$(pkg_ver)$(cross_bin_arch) + p_gcc = gcc$(pkg_ver)$(cross_bin_arch) + p_cxx = g++$(pkg_ver)$(cross_bin_arch) +endif +p_hppa64 = gcc$(pkg_ver)-hppa64 + +d = debian/tmp +d_base = debian/$(p_base) +d_gcc = debian/$(p_gcc) +d_cpp = debian/$(p_cpp) +d_cppd = debian/$(p_cppd) +d_cxx = debian/$(p_cxx) +d_doc = debian/$(p_doc) +d_lgcc = debian/$(p_lgcc) +d_hppa64= debian/$(p_hppa64) + +d_spu = debian/tmp-spu +d_neon = debian/tmp-neon + +common_substvars = \ + $(shell awk "{printf \"'-V%s' \", \$$0}" debian/substvars.local) + +ifeq ($(DEB_CROSS),yes) + lib_binaries := indep_binaries +else + lib_binaries := arch_binaries +endif + +# --------------------------------------------------------------------------- + +ifeq ($(PKGSOURCE),gcc-snapshot) + include debian/rules.d/binary-snapshot.mk +else + +ifneq ($(DEB_CROSS),yes) +ifeq ($(with_source),yes) + include debian/rules.d/binary-source.mk +endif +endif + +ifneq ($(BACKPORT),true) +ifeq ($(with_gccxbase),yes) + include debian/rules.d/binary-base.mk +endif + +ifeq ($(with_gccbase),yes) + include debian/rules.d/binary-base.mk +endif + +ifneq ($(DEB_STAGE),stage1) + include debian/rules.d/binary-libgcc.mk +endif + +ifeq ($(with_libgmath),yes) + include debian/rules.d/binary-libgccmath.mk +endif + +ifeq ($(with_libgomp),yes) + include debian/rules.d/binary-libgomp.mk +endif + +ifeq ($(with_cdev),yes) + include debian/rules.d/binary-cpp.mk +endif + +ifeq ($(with_fixincl),yes) + include debian/rules.d/binary-fixincl.mk +endif + +ifeq ($(with_mudflap),yes) + include debian/rules.d/binary-libmudflap.mk +endif + +ifeq ($(with_libssp),yes) + include debian/rules.d/binary-libssp.mk +endif + +ifeq ($(with_objcxx),yes) + include debian/rules.d/binary-objcxx.mk +endif + +ifeq ($(with_objc),yes) + include debian/rules.d/binary-objc.mk +endif +ifeq ($(with_libobjc),yes) + include debian/rules.d/binary-libobjc.mk +endif + +# include before cxx +ifeq ($(with_java),yes) + include debian/rules.d/binary-java.mk +endif + +ifeq ($(with_cxxdev),yes) + include debian/rules.d/binary-cxx.mk +endif +ifeq ($(with_cxx),yes) + include debian/rules.d/binary-libstdcxx.mk +endif + +ifeq ($(with_f77),yes) + include debian/rules.d/binary-f77.mk +endif + +ifeq ($(with_fortran),yes) + include debian/rules.d/binary-fortran.mk +endif + +ifeq ($(with_ada),yes) + include debian/rules.d/binary-ada.mk +endif + +ifeq ($(with_d),yes) + include debian/rules.d/binary-d.mk +endif + +ifeq ($(with_libnof),yes) + ifeq ($(DEB_TARGET_GNU_CPU),powerpc) + include debian/rules.d/binary-nof.mk + endif +endif + +# gcc must be moved/built after g77 and g++ +ifeq ($(with_cdev),yes) + include debian/rules.d/binary-gcc.mk +endif + +ifeq ($(with_hppa64),yes) + include debian/rules.d/binary-hppa64.mk +endif + +ifeq ($(with_neon),yes) + include debian/rules.d/binary-neon.mk +endif + +ifeq ($(with_spu),yes) + include debian/rules.d/binary-spu.mk +endif +endif + +endif # ($(PKGSOURCE),gcc-snapshot) + +# ---------------------------------------------------------------------- +install: $(install_dependencies) + +$(install_dummy_stamp): $(build_dummy_stamp) + touch $(install_dummy_stamp) + +$(install_snap_stamp): $(build_dependencies) + dh_testdir + dh_testroot + dh_clean -k + + : # Install directories + rm -rf $(d) + mkdir -p $(d)/$(PF) + +ifeq ($(with_hppa64),yes) + : # Install hppa64 + $(SET_PATH) \ + $(MAKE) -C $(builddir_hppa64) \ + CC="$(CC)" \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) \ + DESTDIR=$(PWD)/$(d) \ + install + + ls -l $(d)/$(PF)/bin + if [ ! -x $(d)/$(PF)/bin/hppa64-linux-gnu-gcc ]; then \ + mv $(d)/$(PF)/bin/hppa64-linux-gnu-gcc-4* $(d)/$(PF)/bin/hppa64-linux-gnu-gcc; \ + else \ + rm -f $(d)/$(PF)/bin/hppa64-linux-gnu-gcc-4*; \ + fi + + : # remove files not needed from the hppa64 build + rm -rf $(d)/$(PF)/share/info + rm -rf $(d)/$(PF)/share/man + rm -f $(d)/$(PF)/$(libdir)/libiberty.a + rm -f $(d)/$(PF)/bin/*{gcov,gccbug,gcc} + + rm -rf $(d)/$(PF)/hppa64-linux-gnu/include + rm -rf $(d)/$(PF)/hppa64-linux-gnu/lib + set -e; \ + cd $(d)/$(PF)/$(libdir)/gcc/hppa64-linux-gnu/$(GCC_VERSION)/include-fixed; \ + for i in *; do \ + case "$$i" in \ + README|features.h|syslimits.h|limits.h) ;; \ + linux|$(TARGET_ALIAS)) ;; \ + $(subst $(DEB_TARGET_GNU_CPU),$(biarch_cpu),$(TARGET_ALIAS))) ;; \ + *) echo "remove include-fixed/$$i"; rm -rf $$i; \ + esac; \ + done +endif + +ifeq ($(with_spu),yes) + : # Install spu + $(SET_PATH) \ + $(MAKE) -C $(builddir_spu) \ + CC="$(CC)" \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) \ + DESTDIR=$(PWD)/$(d) \ + install + + ls -l $(d)/$(PF)/bin + if [ ! -x $(d)/$(PF)/bin/spu-gcc ]; then \ + mv $(d)/$(PF)/bin/spu-gcc-4* $(d)/$(PF)/bin/spu-gcc; \ + else \ + rm -f $(d)/$(PF)/bin/spu-gcc-4*; \ + fi + if [ ! -x $(d)/$(PF)/bin/spu-g++ ]; then \ + mv $(d)/$(PF)/bin/spu-g++-4* $(d)/$(PF)/bin/spu-g++; \ + else \ + rm -f $(d)/$(PF)/bin/spu-g++-4*; \ + fi +ifneq (,$(findstring fortran, $(spu_configure_args))) + if [ ! -x $(d)/$(PF)/bin/spu-gfortran ]; then \ + mv $(d)/$(PF)/bin/spu-gfortran-4* $(d)/$(PF)/bin/spu-gfortran; \ + else \ + rm -f $(d)/$(PF)/bin/spu-gfortran-4*; \ + fi +endif + rm -f $(d)/$(PF)/bin/spu-c++* + + : # remove files not needed from the spu build + rm -rf $(d)/$(PF)/info $(d)/$(PF)/share/info + rm -rf $(d)/$(PF)/man $(d)/$(PF)/share/man + rm -rf $(d)/$(PF)/$(libdir)/gcc/spu/$(GCC_VERSION)/plugin + rm -f $(d)/$(PF)/$(libdir)/libiberty.a + rm -f $(d)/$(PF)/bin/*{gcov,gccbug,gcc} + +# FIXME +# rm -rf $(d)/$(PF)/spu/include +# rm -rf $(d)/$(PF)/spu/lib + -set -e; \ + cd $(d)/$(PF)/$(libdir)/gcc/spu/$(GCC_VERSION)/include-fixed; \ + for i in *; do \ + case "$$i" in \ + README|features.h|syslimits.h|limits.h) ;; \ + linux|$(TARGET_ALIAS)) ;; \ + $(subst $(DEB_TARGET_GNU_CPU),$(biarch_cpu),$(TARGET_ALIAS))) ;; \ + *) echo "remove include-fixed/$$i"; rm -rf $$i; \ + esac; \ + done +endif + + : # Work around PR lto/41569 + ln -sf gcc $(builddir)/prev-gcc + + : # Install everything + $(SET_PATH) \ + $(SET_SHELL) \ + $(MAKE) -C $(builddir) \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) \ + DESTDIR=$(PWD)/$(d) \ + infodir=/$(PF)/share/info \ + mandir=/$(PF)/share/man \ + install + + ls -l $(d)/$(PF)/bin + if [ ! -x $(d)/$(PF)/bin/$(TARGET_ALIAS)-gcc ]; then \ + mv $(d)/$(PF)/bin/$(TARGET_ALIAS)-gcc-4* $(d)/$(PF)/bin/$(TARGET_ALIAS)-gcc; \ + else \ + rm -f $(d)/$(PF)/bin/$(TARGET_ALIAS)-gcc-4*; \ + fi + set -e; \ + cd $(d)/$(gcc_lib_dir)/include-fixed; \ + for i in *; do \ + case "$$i" in \ + README|features.h|syslimits.h|limits.h) ;; \ + linux|$(TARGET_ALIAS)) ;; \ + $(subst $(DEB_TARGET_GNU_CPU),$(biarch_cpu),$(TARGET_ALIAS))) ;; \ + *) echo "remove include-fixed/$$i"; rm -rf $$i; \ + esac; \ + done + +ifeq ($(biarch64)-$(with_cxx),yes-yes) + ifneq (,$(filter libstdc++-v3, $(biarch_multidir_names))) + : # fix biarch C++ header installation + ifeq ($(DEB_TARGET_ARCH),i386) + mv $(d)/$(cxx_inc_dir)/x86_64-linux-gnu/64 \ + $(d)/$(cxx_inc_dir)/i486-linux-gnu/ + rmdir $(d)/$(cxx_inc_dir)/x86_64-linux-gnu + endif + ifeq ($(DEB_TARGET_ARCH),powerpc) + mv $(d)/$(cxx_inc_dir)/powerpc64-linux-gnu/64 \ + $(d)/$(cxx_inc_dir)/powerpc-linux-gnu/ + rmdir $(d)/$(cxx_inc_dir)/powerpc64-linux-gnu + endif + ifeq ($(DEB_TARGET_ARCH),s390) + mv $(d)/$(cxx_inc_dir)/s390x-linux-gnu/64 \ + $(d)/$(cxx_inc_dir)/s390-linux-gnu/ + rmdir $(d)/$(cxx_inc_dir)/s390x-linux-gnu + endif + endif +endif + +# FIXME: libjava/classpath not correctly patched +ifeq ($(with_java),yes) + -if [ -d $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME) ]; then \ + ls -l $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME); \ + mv $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME)/* \ + $(d)/$(PF)/lib/gcj-$(BASE_VERSION)-$(GCJ_SONAME)/; \ + rmdir $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME); \ + fi + + ln -sf libgcj.so.$(GCJ_SONAME).0.0 $(d)/$(PF)/lib/libgcj_bc.so.1.0.0 + + install -m 755 $(d)/$(PF)/lib/libgcj_bc.so.1 \ + $(d)/$(gcc_lib_dir)/libgcj_bc.so + $(builddir)/gcc/xgcc -B$(builddir)/gcc/ -shared -fpic -xc /dev/null \ + -o build/libgcj.so -Wl,-soname,libgcj.so.$(GCJ_SONAME) -nostdlib + $(builddir)/gcc/xgcc -B$(builddir)/gcc/ -shared -fpic \ + $(srcdir)/libjava/libgcj_bc.c \ + -o $(d)/$(gcc_lib_dir)/libgcj_bc.so \ + -Wl,-soname,libgcj_bc.so.1 $(builddir)/libgcj.so -shared-libgcc +endif + + -ls -l $(d)/usr + if [ -d $(d)/usr/man/man1 ]; then \ + mv $(d)/usr/man/man1/* $(d)/usr/share/man/man1/; \ + fi + + chmod 755 debian/dh_* + touch $(install_snap_stamp) + +$(install_stamp): $(build_stamp) + dh_testdir + dh_testroot + dh_clean -k -N$(p_hppa64) + + if [ -f $(binary_stamp)-hppa64 ]; then \ + mv $(binary_stamp)-hppa64 saved-stamp-hppa64; \ + fi + if [ -f $(binary_stamp)-spu ]; then \ + mv $(binary_stamp)-spu saved-stamp-spu; \ + fi + rm -f $(binary_stamp)* + if [ -f saved-stamp-hppa64 ]; then \ + mv saved-stamp-hppa64 $(binary_stamp)-hppa64; \ + fi + if [ -f saved-stamp-spu ]; then \ + mv saved-stamp-spu $(binary_stamp)-spu; \ + fi + + : # Install directories + rm -rf $(d) + mkdir -p $(d)/$(libdir) $(d)/$(PF) $(d)/$(PF)/$(libdir)/debug +ifeq ($(biarch32),yes) + mkdir -p $(d)/$(PF)/lib32/debug +endif +ifeq ($(biarch64),yes) + mkdir -p $(d)/$(PF)/lib64/debug +endif +ifeq ($(biarchn32),yes) + mkdir -p $(d)/$(PF)/$(libn32)/debug +endif + +ifneq (,$(filter $(DEB_TARGET_GNU_CPU),x86_64 sparc64)) + : # link lib to lib64 and $(PF)/lib to $(PF)/lib64 + : # (this works when CONFARGS contains '--disable-multilib') + ln -s $(libdir) $(d)/lib64 + mkdir -p $(d)/$(PF)/$(libdir) + ln -s $(libdir) $(d)/$(PF)/lib64 +endif + + : # Work around PR lto/41569 + ln -sf gcc $(builddir)/prev-gcc + + : # Install everything + $(SET_PATH) \ + $(SET_SHELL) \ + $(MAKE) -C $(builddir) \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) \ + DESTDIR=$(PWD)/$(d) \ + infodir=/$(PF)/share/info \ + mandir=/$(PF)/share/man \ + install + +ifeq ($(with_common_gcclibdir),yes) + mv $(d)/$(subst /$(BASE_VERSION),/$(GCC_VERSION),$(gcc_lib_dir)) \ + $(d)/$(gcc_lib_dir) + mv $(d)/$(PF)/share/gcc-$(GCC_VERSION) $(d)/$(PF)/share/gcc-$(BASE_VERSION) + ifneq ($(gcc_lib_dir),$(gcc_lexec_dir)) + mv $(d)/$(subst /$(BASE_VERSION),/$(GCC_VERSION),$(gcc_lexec_dir)) \ + $(d)/$(gcc_lexec_dir) + endif + ifeq ($(with_d),yes) + mv $(d)/$(PF)/include/d/$(GCC_VERSION) \ + $(d)/$(PF)/include/d/$(BASE_VERSION) + endif +endif + +ifeq ($(biarch64)-$(with_cxx),yes-yes) + ifneq (,$(filter libstdc++-v3, $(biarch_multidir_names))) + ifeq ($(DEB_TARGET_ARCH),i386) + : # fix biarch C++ header installation + mv $(d)/$(cxx_inc_dir)/x86_64-linux-gnu/64 \ + $(d)/$(cxx_inc_dir)/i486-linux-gnu/ + rmdir $(d)/$(cxx_inc_dir)/x86_64-linux-gnu + endif + ifeq ($(DEB_TARGET_ARCH),powerpc) + : # fix biarch C++ header installation + mv $(d)/$(cxx_inc_dir)/powerpc64-linux-gnu/64 \ + $(d)/$(cxx_inc_dir)/powerpc-linux-gnu/ + rmdir $(d)/$(cxx_inc_dir)/powerpc64-linux-gnu + endif + endif +endif + +# FIXME: libjava/classpath not correctly patched +ifeq ($(with_java),yes) + -if [ -d $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME) ]; then \ + ls -l $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME); \ + mv $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME)/* \ + $(d)/$(PF)/lib/gcj-$(BASE_VERSION)-$(GCJ_SONAME)/; \ + rmdir $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME); \ + fi +endif + + : # remove rpath settings from binaries and shared libs + for i in $$(chrpath -k $(d)/$(PF)/bin/* $(d)/$(PF)/lib*/lib*.so.* \ + $(d)/$(PF)/lib*/gcj$(pkg_ver)*/lib*.so.* \ + 2>/dev/null | awk -F: '/RPATH=/ {print $$1}'); \ + do \ + case "$$i" in ecj1|*gij-*|*libjawt*|*libjvm*) continue; esac; \ + [ -h $$i ] && continue; \ + chrpath --delete $$i; \ + echo "removed RPATH: $$i"; \ + done + + : # remove '*.la' and '*.lai' files, not shipped in any package. + find $(d) -name '*.la' -o -name '*.lai' | xargs -r rm -f + +ifneq ($(with_libgnat),yes) + rm -f $(d)/$(gcc_lib_dir)/adalib/lib*.so* +endif + +ifeq ($(GFDL_INVARIANT_FREE),yes) + for i in gcc gcov; do \ + I=`echo $$i | tr a-z A-Z`; \ + sed -e "s/@NAME@/$$I$(pkg_ver)/g" -e "s/@name@/$$i$(pkg_ver)/g" \ + debian/dummy-man.1 > $(d)/$(PF)/share/man/man1/$$i.1; \ + done + + ifeq ($(with_fortran),yes) + for i in g77; do \ + I=`echo $$i | tr a-z A-Z`; \ + sed -e "s/@NAME@/$$I$(pkg_ver)/g" -e "s/@name@/$$i$(pkg_ver)/g" \ + debian/dummy-man.1 > $(d)/$(PF)/share/man/man1/$$i.1; \ + done + endif + ifeq ($(with_java),yes) + for i in gcj gcjh gij jv-convert jv-scan jcf-dump grmic grmiregistry; \ + do \ + I=`echo $$i | tr a-z A-Z`; \ + sed -e "s/@NAME@/$$I$(pkg_ver)/g" -e "s/@name@/$$i$(pkg_ver)/g" \ + debian/dummy-man.1 > $(d)/$(PF)/share/man/man1/$$i.1; \ + done + endif +endif + +# ifeq ($(with_ada),yes) +# : # rename files (versioned ada binaries) +# for i in ; do \ +# mv $(d)/$(PF)/bin/$$i $(d)/$(PF)/bin/$$i-$(GNAT_VERSION); \ +# mv $(d)/$(PF)/share/man/man1/$$i.1 \ +# $(d)/$(PF)/share/man/man1/$$i-$(GNAT_VERSION).1; \ +# done +# for i in $(GNAT_TOOLS); do \ +# mv $(d)/$(PF)/bin/$$i $(d)/$(PF)/bin/$$i-$(GNAT_VERSION); \ +# done +# endif + +ifeq ($(DEB_CROSS),yes) + ifeq ($(DEB_TARGET_ARCH)-$(biarch64),s390-yes) + : # s390 64bit stuff happens to be in s390x-linux-gnu/lib64/ + mkdir -p $(d)/$(PF)/s390-linux-gnu/lib64 + cp -a $(d)/$(PF)/s390x-linux-gnu/lib64/* $(d)/$(PF)/s390-linux-gnu/lib64/ + endif + ifeq ($(DEB_TARGET_ARCH)-$(biarch64),powerpc-yes) + : # ppc 64bit build slaps libgcc and libstdc++ to powerpc64-linux-gnu + cp -a $(d)/$(PF)/powerpc64-linux-gnu/lib64/* $(d)/$(PF)/powerpc-linux-gnu/lib64/ + endif +endif + + chmod 755 debian/dh_* + +# tar cf tmp.tar debian/tmp + + touch $(install_stamp) + +$(install_hppa64_stamp): $(build_hppa64_stamp) + dh_testdir + dh_testroot + rm -rf $(d_hppa64) + mkdir -p $(d_hppa64)/$(PF) + + $(SET_PATH) \ + $(MAKE) -C $(builddir_hppa64) \ + CC="$(CC)" \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) \ + DESTDIR=$(PWD)/$(d_hppa64) \ + install + +ifeq ($(versioned_packages),yes) + mv $(d_hppa64)/$(PF)/bin/hppa64-linux-gnu-gcc-$(GCC_VERSION) \ + $(d_hppa64)/$(PF)/bin/hppa64-linux-gnu-gcc$(pkg_ver) + mv $(d_hppa64)/$(PF)/bin/hppa64-linux-gnu-cpp \ + $(d_hppa64)/$(PF)/bin/hppa64-linux-gnu-cpp$(pkg_ver) +endif + +ifneq ($(PKGSOURCE),gcc-snapshot) + : # remove files not needed + rm -rf $(d_hppa64)/$(PF)/info $(d_hppa64)/$(PF)/share/info + rm -rf $(d_hppa64)/$(PF)/man $(d_hppa64)/$(PF)/share/man + rm -rf $(d_hppa64)/$(PF)/$(libdir)/gcc/spu/$(GCC_VERSION)/plugin + rm -f $(d_hppa64)/$(PF)/$(libdir)/libiberty.a + rm -f $(d_hppa64)/$(PF)/bin/*{gcov,gccbug,gcc} + + rm -rf $(d_hppa64)/$(PF)/hppa64-linux-gnu/include + rm -rf $(d_hppa64)/$(PF)/hppa64-linux-gnu/lib + rm -rf $(d_hppa64)//$(PF)/$(libdir)/gcc/hppa64-linux-gnu/$(GCC_VERSION)/install-tools +endif + + touch $(install_hppa64_stamp) + +$(install_neon_stamp): $(build_neon_stamp) + dh_testdir + dh_testroot + rm -rf $(d_neon) + mkdir -p $(d_neon)/$(PF) + + $(SET_PATH) \ + $(MAKE) -C $(builddir_neon) \ + CC="$(CC)" \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) \ + DESTDIR=$(PWD)/$(d_neon) \ + install + touch $(install_neon_stamp) + +$(install_spu_stamp): $(build_spu_stamp) + dh_testdir + dh_testroot + rm -rf $(d_spu) + mkdir -p $(d_spu)/$(PF) + + $(SET_PATH) \ + $(MAKE) -C $(builddir_spu) \ + CC="$(CC)" \ + $(CFLAGS_TO_PASS) \ + $(LDFLAGS_TO_PASS) \ + DESTDIR=$(PWD)/$(d_spu) \ + install + +ifeq ($(with_common_gcclibdir),yes) + mv $(d_spu)/$(subst /$(BASE_VERSION),/$(GCC_VERSION),$(gcc_spu_lib_dir)) \ + $(d_spu)/$(gcc_spu_lib_dir) + ifneq ($(gcc_spu_lib_dir),$(gcc_spu_lexec_dir)) + mv $(d_spu)/$(subst /$(BASE_VERSION),/$(GCC_VERSION),$(gcc_spu_lexec_dir)) \ + $(d_spu)/$(gcc_spu_lexec_dir) + endif +endif + +ifeq ($(versioned_packages),yes) + mv $(d_spu)/$(PF)/bin/spu-cpp \ + $(d_spu)/$(PF)/bin/spu-cpp$(pkg_ver) + mv $(d_spu)/$(PF)/bin/spu-gcc-$(GCC_VERSION) \ + $(d_spu)/$(PF)/bin/spu-gcc$(pkg_ver) + mv $(d_spu)/$(PF)/bin/spu-g++ \ + $(d_spu)/$(PF)/bin/spu-g++$(pkg_ver) + ifneq (,$(findstring fortran, $(spu_configure_args))) + mv $(d_spu)/$(PF)/bin/spu-gfortran \ + $(d_spu)/$(PF)/bin/spu-gfortran$(pkg_ver) + endif + rm -f $(d_spu)/$(PF)/bin/spu-c++* + + ifneq ($(GFDL_INVARIANT_FREE),yes) + for i in spu-cpp spu-gcc spu-g++ spu-gcov spu-gfortran; do \ + mv $(d_spu)/$(PF)/share/man/man1/$$i.1 $(d_spu)/$(PF)/share/man/man1/$$i-$(BASE_VERSION).1; \ + done + endif +endif + +ifneq ($(PKGSOURCE),gcc-snapshot) + : # remove files not needed + rm -rf $(d_spu)/$(PF)/info +# rm -rf $(d_spu)/$(PF)/man + rm -f $(d_spu)/$(PF)/$(libdir)/libiberty.a + rm -f $(d_spu)/$(PF)/bin/*{gcov,gccbug,gcc} + +# rm -rf $(d_spu)/$(PF)/spu/include +# rm -rf $(d_spu)/$(PF)/spu/lib +endif + + touch $(install_spu_stamp) + +# ---------------------------------------------------------------------- +# Build architecture-dependent files here. +#binary-arch: build install $(foreach i,$(arch_binaries),$(binary_stamp)-$(i)) +binary-arch: $(foreach i,$(arch_binaries),$(binary_stamp)-$(i)) +ifeq ($(with_check),yes) + @echo Done +# : # Send Email about sucessfull build. +# # cat raw-test-summary | sh; echo "Sent mail to $(S_EMAIL)" +endif + +# ---------------------------------------------------------------------- +# Build architecture-independent files here. +#binary-indep: build install $(foreach i,$(indep_binaries),$(binary_stamp)-$(i)) +binary-indep: $(foreach i,$(indep_binaries),$(binary_stamp)-$(i)) + +source diff: + @echo >&2 'source and diff are obsolete - use dpkg-source -b'; false + +binary: binary-indep binary-arch +.PHONY: build clean binary-indep binary-arch binary --- gcc-4.5-4.5.2.orig/debian/gcc-BV-hppa64.prerm +++ gcc-4.5-4.5.2/debian/gcc-BV-hppa64.prerm @@ -0,0 +1,10 @@ +#! /bin/sh -e + +if [ "$1" != "upgrade" ]; then + update-alternatives --quiet \ + --remove hppa64-linux-gcc /usr/bin/hppa64-linux-gnu-gcc-@BV@ +fi + +#DEBHELPER# + +exit 0 --- gcc-4.5-4.5.2.orig/debian/gnat-BV-doc.doc-base.rm +++ gcc-4.5-4.5.2/debian/gnat-BV-doc.doc-base.rm @@ -0,0 +1,16 @@ +Document: gnat-rm-@BV@ +Title: GNAT (GNU Ada) Reference Manual +Author: Various +Abstract: This manual contains useful information in writing programs + using the GNAT compiler. It includes information on implementation + dependent characteristics of GNAT, including all the information + required by Annex M of the standard. +Section: Programming/Ada + +Format: html +Index: /usr/share/doc/gnat-@BV@-doc/gnat_rm.html +Files: /usr/share/doc/gnat-@BV@-doc/gnat_rm.html + +Format: info +Index: /usr/share/info/gnat_rm-@BV@.info.gz +Files: /usr/share/info/gnat_rm-@BV@* --- gcc-4.5-4.5.2.orig/debian/libgcjGCJ.overrides +++ gcc-4.5-4.5.2/debian/libgcjGCJ.overrides @@ -0,0 +1,2 @@ +# pick up the exact version, in case another gcj version is installed +libgcj@GCJ@ binary: binary-or-shlib-defines-rpath --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.sparc64 +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.sparc64 @@ -0,0 +1,9 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.64bit" +#include "libstdc++6.symbols.excprop" + _ZN9__gnu_cxx12__atomic_addEPVli@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx18__exchange_and_addEPVli@GLIBCXX_3.4 4.1.1 +# FIXME: Currently no ldbl symbols in the 64bit libstdc++ on sparc. +# #include "libstdc++6.symbols.ldbl.64bit" + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 --- gcc-4.5-4.5.2.orig/debian/lib32gfortran3.symbols +++ gcc-4.5-4.5.2/debian/lib32gfortran3.symbols @@ -0,0 +1,3 @@ +libgfortran.so.3 lib32gfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.10" --- gcc-4.5-4.5.2.orig/debian/README.Debian +++ gcc-4.5-4.5.2/debian/README.Debian @@ -0,0 +1,36 @@ + The Debian GNU Compiler Collection setup + ======================================== + +Please see the README.Debian in /usr/share/doc/gcc, contained in the +gcc package for a description of the setup of the different compiler +versions. + +For general discussion about the Debian toolchain (GCC, glibc, binutils) +please use the mailing list debian-toolchain@lists.debian.org; for GCC +specific things, please use debian-gcc@lists.debian.org. When in doubt +use the debian-toolchain ML. + + +Maintainers of these packages +----------------------------- + +Matthias Klose +Ray Dassen +Jeff Bailey (hurd-i386) +Joel Baker (netbsd-i386) +Philip Blundell (arm-linux) +Ben Collins (sparc-linux) +Randolph Chung (ia64-linux) +Falk Hueffner (alpha-linux) +Dan Jacobowitz (powerpc-linux) +Thiemo Seufer (mips*-linux) +Matt Taggart (hppa-linux) +Gerhard Tonn (s390-linux) +Roman Zippel (m68k-linux) +Ludovic Brenta (gnat) +Arthur Loiret (gdc) + +=============================================================================== + +Information about patches applied to this package can be found in +README.Debian.$arch for the corresponding architecture. --- gcc-4.5-4.5.2.orig/debian/gcc-BV-CRB.preinst.in +++ gcc-4.5-4.5.2/debian/gcc-BV-CRB.preinst.in @@ -0,0 +1,12 @@ +#!/bin/sh + +set -e + +if [ "$1" = "upgrade" ] || [ "$1" = "configure" ]; then + update-alternatives --quiet --remove @TARGET@-gcc /usr/bin/@TARGET@-gcc-@BV@ + update-alternatives --quiet --remove @TARGET@-gcov /usr/bin/@TARGET@-gcov-@BV@ +fi + +#DEBHELPER# + +exit 0 --- gcc-4.5-4.5.2.orig/debian/gnat-BV-doc.doc-base.style +++ gcc-4.5-4.5.2/debian/gnat-BV-doc.doc-base.style @@ -0,0 +1,16 @@ +Document: gnat-style-@BV@ +Title: GNAT Coding Style +Author: Various +Abstract: Most of GNAT is written in Ada using a consistent style to + ensure readability of the code. This document has been written to + help maintain this consistent style, while having a large group of + developers work on the compiler. +Section: Programming/Ada + +Format: html +Index: /usr/share/doc/gnat-@BV@-doc/gnat-style.html +Files: /usr/share/doc/gnat-@BV@-doc/gnat-style.html + +Format: info +Index: /usr/share/info/gnat-style-@BV@.info.gz +Files: /usr/share/info/gnat-style-@BV@* --- gcc-4.5-4.5.2.orig/debian/lib32stdc++CXX.postinst +++ gcc-4.5-4.5.2/debian/lib32stdc++CXX.postinst @@ -0,0 +1,12 @@ +#! /bin/sh -e + +case "$1" in + configure) + docdir=/usr/share/doc/lib32stdc++@CXX@ + if [ -d $docdir ] && [ ! -h $docdir ]; then + rm -rf $docdir + ln -s gcc-@BV@-base $docdir + fi +esac + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/libobjc2.symbols.arm +++ gcc-4.5-4.5.2/debian/libobjc2.symbols.arm @@ -0,0 +1,4 @@ +libobjc.so.2 libobjc2 #MINVER# +#include "libobjc2.symbols.common" + __gnu_objc_personality_sj0@Base 4.2.1 + __objc_exception_class@Base 4.4.0 --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.sparc +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.sparc @@ -0,0 +1,102 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GCC_LDBL_3.0@GCC_LDBL_3.0 1:4.2.1 + GCC_LDBL_4.0.0@GCC_LDBL_4.0.0 1:4.2.1 + GLIBC_2.0@GLIBC_2.0 1:4.1.1 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __ashldi3@GCC_3.0 1:4.1.1 + __ashrdi3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzsi2@GCC_3.4 1:4.1.1 + __cmpdi2@GCC_3.0 1:4.1.1 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzsi2@GCC_3.4 1:4.1.1 + __deregister_frame@GLIBC_2.0 1:4.1.1 + __deregister_frame_info@GLIBC_2.0 1:4.1.1 + __deregister_frame_info_bases@GCC_3.0 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divdi3@GLIBC_2.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + __divtc3@GCC_LDBL_4.0.0 1:4.2.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 1:4.1.1 + __ffsdi2@GCC_3.0 1:4.1.1 + __ffssi2@GCC_4.3.0 1:4.3 + __fixdfdi@GCC_3.0 1:4.1.1 + __fixsfdi@GCC_3.0 1:4.1.1 + __fixtfdi@GCC_LDBL_3.0 1:4.2.1 + __fixunsdfdi@GCC_3.0 1:4.1.1 + __fixunsdfsi@GCC_3.0 1:4.1.1 + __fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfsi@GCC_3.0 1:4.1.1 + __fixunstfdi@GCC_LDBL_3.0 1:4.2.1 + __floatdidf@GCC_3.0 1:4.1.1 + __floatdisf@GCC_3.0 1:4.1.1 + __floatditf@GCC_LDBL_3.0 1:4.2.1 + __floatundidf@GCC_4.2.0 1:4.2.1 + __floatundisf@GCC_4.2.0 1:4.2.1 + __floatunditf@GCC_4.2.0 1:4.2.1 + __frame_state_for@GLIBC_2.0 1:4.1.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __lshrdi3@GCC_3.0 1:4.1.1 + __moddi3@GLIBC_2.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __muldi3@GCC_3.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_LDBL_4.0.0 1:4.2.1 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __negdi2@GCC_3.0 1:4.1.1 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __paritydi2@GCC_3.4 1:4.1.1 + __paritysi2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountsi2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_LDBL_4.0.0 1:4.2.1 + __register_frame@GLIBC_2.0 1:4.1.1 + __register_frame_info@GLIBC_2.0 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GLIBC_2.0 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GLIBC_2.0 1:4.1.1 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __ucmpdi2@GCC_3.0 1:4.1.1 + __udivdi3@GLIBC_2.0 1:4.1.1 + __udivmoddi4@GCC_3.0 1:4.1.1 + __umoddi3@GLIBC_2.0 1:4.1.1 --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.ia64 +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.ia64 @@ -0,0 +1,145 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3.2@GCC_3.3.2 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4.4@GCC_3.4.4 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GCC_4.4.0@GCC_4.4.0 1:4.4.0 + GLIBC_2.0@GLIBC_2.0 1:4.1.1 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetBSP@GCC_3.3.2 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __absvti2@GCC_3.4.4 1:4.1.1 + __addtf3@GCC_4.4.0 1:4.4.0 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __addvti3@GCC_3.4.4 1:4.1.1 + __ashlti3@GCC_3.0 1:4.1.1 + __ashrti3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzti2@GCC_3.4 1:4.1.1 + __cmpti2@GCC_3.0 1:4.1.1 + __copysigntf3@GCC_4.4.0 1:4.4.0 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzti2@GCC_3.4 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divdf3@GCC_3.0 1:4.1.1 + __divdi3@GLIBC_2.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + __divsf3@GCC_3.0 1:4.1.1 + __divsi3@GCC_3.0 1:4.1.1 + __divtc3@GCC_4.4.0 1:4.4.0 + __divtf3@GCC_3.0 1:4.1.1 + __divti3@GCC_3.0 1:4.1.1 + __divxc3@GCC_4.0.0 1:4.1.1 + __divxf3@GCC_3.0 1:4.1.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 1:4.1.1 + __eqtf2@GCC_4.4.0 1:4.4.0 + __extenddftf2@GCC_4.4.0 1:4.4.0 + __extendsftf2@GCC_4.4.0 1:4.4.0 + __fabstf2@GCC_4.4.0 1:4.4.0 + __ffsdi2@GCC_3.0 1:4.1.1 + __ffsti2@GCC_3.0 1:4.1.1 + __fixdfti@GCC_3.0 1:4.1.1 + __fixsfti@GCC_3.0 1:4.1.1 + __fixtfdi@GCC_4.4.0 1:4.4.0 + __fixtfsi@GCC_4.4.0 1:4.4.0 + __fixtfti@GCC_3.0 1:4.1.1 + __fixunsdfdi@GCC_3.0 1:4.1.1 + __fixunsdfti@GCC_3.0 1:4.1.1 + __fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfti@GCC_3.0 1:4.1.1 + __fixunstfdi@GCC_4.4.0 1:4.4.0 + __fixunstfsi@GCC_4.4.0 1:4.4.0 + __fixunstfti@GCC_3.0 1:4.1.1 + __fixunsxfdi@GCC_3.0 1:4.1.1 + __fixunsxfti@GCC_3.0 1:4.1.1 + __fixxfti@GCC_3.0 1:4.1.1 + __floatditf@GCC_4.4.0 1:4.4.0 + __floatsitf@GCC_4.4.0 1:4.4.0 + __floattidf@GCC_3.0 1:4.1.1 + __floattisf@GCC_3.0 1:4.1.1 + __floattitf@GCC_3.0 1:4.1.1 + __floattixf@GCC_3.0 1:4.1.1 + __floatunditf@GCC_4.4.0 1:4.4.0 + __floatunsitf@GCC_4.4.0 1:4.4.0 + __floatuntidf@GCC_4.2.0 1:4.2.1 + __floatuntisf@GCC_4.2.0 1:4.2.1 + __floatuntixf@GCC_4.2.0 1:4.2.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __getf2@GCC_4.4.0 1:4.4.0 + __gttf2@GCC_4.4.0 1:4.4.0 + __ia64_nonlocal_goto@GCC_3.0 1:4.1.1 + __ia64_restore_stack_nonlocal@GCC_3.0 1:4.1.1 + __ia64_save_stack_nonlocal@GCC_3.0 1:4.1.1 + __ia64_trampoline@GCC_3.0 1:4.1.1 + __letf2@GCC_4.4.0 1:4.4.0 + __lshrti3@GCC_3.0 1:4.1.1 + __lttf2@GCC_4.4.0 1:4.4.0 + __moddi3@GLIBC_2.0 1:4.1.1 + __modsi3@GCC_3.0 1:4.1.1 + __modti3@GCC_3.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_4.4.0 1:4.4.0 + __multf3@GCC_4.4.0 1:4.4.0 + __multi3@GCC_3.0 1:4.1.1 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __mulvti3@GCC_3.4.4 1:4.1.1 + __mulxc3@GCC_4.0.0 1:4.1.1 + __negtf2@GCC_4.4.0 1:4.4.0 + __negti2@GCC_3.0 1:4.1.1 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __negvti2@GCC_3.4.4 1:4.1.1 + __netf2@GCC_4.4.0 1:4.4.0 + __paritydi2@GCC_3.4 1:4.1.1 + __parityti2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountti2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_4.4.0 1:4.4.0 + __powixf2@GCC_4.0.0 1:4.1.1 + __subtf3@GCC_4.4.0 1:4.4.0 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __subvti3@GCC_3.4.4 1:4.1.1 + __trunctfdf2@GCC_4.4.0 1:4.4.0 + __trunctfsf2@GCC_4.4.0 1:4.4.0 + __trunctfxf2@GCC_4.4.0 1:4.4.0 + __ucmpti2@GCC_3.0 1:4.1.1 + __udivdi3@GLIBC_2.0 1:4.1.1 + __udivmodti4@GCC_3.0 1:4.1.1 + __udivsi3@GCC_3.0 1:4.1.1 + __udivti3@GCC_3.0 1:4.1.1 + __umoddi3@GLIBC_2.0 1:4.1.1 + __umodsi3@GCC_3.0 1:4.1.1 + __umodti3@GCC_3.0 1:4.1.1 + __unordtf2@GCC_4.4.0 1:4.4.0 --- gcc-4.5-4.5.2.orig/debian/gcc-BV-spu.overrides +++ gcc-4.5-4.5.2/debian/gcc-BV-spu.overrides @@ -0,0 +1,2 @@ +gcc-@BV@-spu: non-standard-dir-in-usr usr/spu/ +gcc-@BV@-spu: file-in-unusual-dir --- gcc-4.5-4.5.2.orig/debian/control.m4 +++ gcc-4.5-4.5.2/debian/control.m4 @@ -0,0 +1,1755 @@ +divert(-1) + +define(`checkdef',`ifdef($1, , `errprint(`error: undefined macro $1 +')m4exit(1)')') +define(`errexit',`errprint(`error: undefined macro `$1' +')m4exit(1)') + +dnl The following macros must be defined, when called: +dnl ifdef(`SRCNAME', , errexit(`SRCNAME')) +dnl ifdef(`PV', , errexit(`PV')) +dnl ifdef(`ARCH', , errexit(`ARCH')) + +dnl The architecture will also be defined (-D__i386__, -D__powerpc__, etc.) + +define(`PN', `$1') +ifdef(`PRI', `', ` + define(`PRI', `$1') +') +define(`MAINTAINER', `Debian GCC Maintainers ') + +define(`ifenabled', `ifelse(index(enabled_languages, `$1'), -1, `dnl', `$2')') + +divert`'dnl +dnl -------------------------------------------------------------------------- +Source: SRCNAME +Section: devel +Priority: PRI(optional) +ifelse(DIST,`Ubuntu',`dnl +ifelse(regexp(SRCNAME, `gnat\|gdc-'),0,`dnl +Maintainer: Ubuntu MOTU Developers +', `dnl +Maintainer: Ubuntu Core developers +')dnl SRCNAME +XSBC-Original-Maintainer: MAINTAINER +', `dnl +Maintainer: MAINTAINER +')dnl DIST +ifelse(regexp(SRCNAME, `gnat'),0,`dnl +Uploaders: Ludovic Brenta +', regexp(SRCNAME, `gdc'),0,`dnl +Uploaders: Arthur Loiret +', `dnl +Uploaders: Matthias Klose , Arthur Loiret +')dnl SRCNAME +Standards-Version: 3.9.1 +ifdef(`TARGET',`dnl cross +Build-Depends: DPKG_BUILD_DEP debhelper (>= 5.0.62), dpkg-cross (>= 1.25.99), LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP LIBUNWIND_BUILD_DEP LIBATOMIC_OPS_BUILD_DEP AUTOGEN_BUILD_DEP CLOOG_BUILD_DEP AUTO_BUILD_DEP SOURCE_BUILD_DEP CROSS_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP zlib1g-dev, gawk, lzma, xz-utils, patchutils, BINUTILS_BUILD_DEP, bison (>= 1:2.3), flex, realpath (>= 1.9.12), lsb-release, make (>= 3.81), quilt +',`dnl native +Build-Depends: DPKG_BUILD_DEP debhelper (>= 5.0.62), g++-multilib [amd64 i386 mips mipsel powerpc ppc64 s390 sparc kfreebsd-amd64], LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP AUTO_BUILD_DEP AUTOGEN_BUILD_DEP libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], zlib1g-dev, gawk, lzma, xz-utils, patchutils, BINUTILS_BUILD_DEP, binutils-hppa64 (>= BINUTILSV) [hppa], gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext, texinfo (>= 4.3), FORTRAN_BUILD_DEP locales [locale_no_archs], procps, sharutils, JAVA_BUILD_DEP GNAT_BUILD_DEP SPU_BUILD_DEP CLOOG_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP ELF_BUILD_DEP CHECK_BUILD_DEP realpath (>= 1.9.12), chrpath, lsb-release, make (>= 3.81), quilt +ifelse(SRCNAME,gcc-snapshot,`',`dnl +Build-Depends-Indep: LIBSTDCXX_BUILD_INDEP JAVA_BUILD_INDEP +')dnl +')dnl +Build-Conflicts: binutils-gold +ifelse(regexp(SRCNAME, `gnat'),0,`dnl +Homepage: http://gcc.gnu.org/ +', regexp(SRCNAME, `gdc'),0,`dnl +Homepage: http://dgcc.sourceforge.net/ +', `dnl +Homepage: http://gcc.gnu.org/ +')dnl SRCNAME +XS-Vcs-Browser: http://svn.debian.org/viewsvn/gcccvs/branches/sid/gcc`'PV/ +XS-Vcs-Svn: svn://svn.debian.org/svn/gcccvs/branches/sid/gcc`'PV + +ifelse(SRCNAME,gcc-snapshot,`dnl +Package: gcc-snapshot +Architecture: any +Section: devel +Priority: extra +Depends: binutils`'TS (>= ${binutils:Version}), ${dep:libcbiarchdev}, ${dep:libcdev}, ${dep:libunwinddev}, ${snap:depends}, ${shlibs:Depends}, ${dep:ecj}, python, ${misc:Depends} +Recommends: ${snap:recommends} +Suggests: ${dep:gold} +Provides: c++-compiler`'TS`'ifdef(`TARGET)',`',`, c++abi2-dev') +Description: A SNAPSHOT of the GNU Compiler Collection + This package contains a recent development SNAPSHOT of all files + contained in the GNU Compiler Collection (GCC). + . + The source code for this package has been exported from SVN trunk. + . + DO NOT USE THIS SNAPSHOT FOR BUILDING DEBIAN PACKAGES! + . + This package will NEVER hit the testing distribution. It is used for + tracking gcc bugs submitted to the Debian BTS in recent development + versions of gcc. +',`dnl gcc-X.Y + +dnl default base package dependencies +define(`BASETARGET', `') +define(`BASEDEP', `gcc`'PV-base (= ${gcc:Version})') +define(`SOFTBASEDEP', `gcc`'PV-base (>= ${gcc:SoftVersion})') + +dnl base, when building libgcc out of the gcj source; needed if new symbols +dnl in libgcc are used in libgcj. +ifelse(index(SRCNAME, `gcj'), 0, ` +define(`BASEDEP', `gcj`'PV-base (= ${gcj:Version})') +define(`SOFTBASEDEP', `gcj`'PV-base (>= ${gcj:SoftVersion})') +') + +ifdef(`TARGET', `', ` +ifenabled(`gccbase',` + +Package: gcc`'PV-base +Architecture: any +ifdef(`MULTIARCH', `Multi-Arch: same +')`'dnl +Section: libs +Priority: PRI(required) +Depends: ${misc:Depends} +Replaces: ${base:Replaces} +Description: The GNU Compiler Collection (base package) + This package contains files common to all languages and libraries + contained in the GNU Compiler Collection (GCC). +ifdef(`BASE_ONLY', `dnl + . + This version of GCC is not yet available for this architecture. + Please use the compilers from the gcc-snapshot package for testing. +')`'dnl +')`'dnl +')`'dnl native + +ifenabled(`gccxbase',` +dnl override default base package dependencies to cross version +dnl This creates a toolchain that doesnt depend on the system -base packages +define(`BASETARGET', `PV`'TS') +define(`BASEDEP', `gcc`'BASETARGET-base (= ${gcc:Version})') +define(`SOFTBASEDEP', `gcc`'BASETARGET-base (>= ${gcc:SoftVersion})') + +Package: gcc`'BASETARGET-base +Architecture: any +Section: devel +Priority: PRI(extra) +Depends: ${misc:Depends} +Description: The GNU Compiler Collection (base package) + This package contains files common to all languages and libraries + contained in the GNU Compiler Collection (GCC). +')`'dnl + +ifenabled(`java',` +Package: gcj`'PV-base +Architecture: any +Section: libs +Priority: PRI(optional) +Depends: ${misc:Depends} +Description: The GNU Compiler Collection (gcj base package) + This package contains files common to all java related packages + built from the GNU Compiler Collection (GCC). +')`'dnl java + +ifenabled(`ada',` +Package: gnat`'PV-base +Architecture: any +Section: libs +Priority: PRI(optional) +Depends: ${misc:Depends} +Description: The GNU Compiler Collection (gnat base package) + This package contains files common to all Ada related packages + built from the GNU Compiler Collection (GCC). +')`'dnl ada + +ifenabled(`libgcc',` +Package: libgcc1`'LS +Architecture: ifdef(`TARGET',`all',`any') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',required) +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +ifdef(`TARGET',`Provides: libgcc1-TARGET-dcv1 +',ifdef(`MULTIARCH', `Multi-Arch: same +Pre-Depends: multiarch-support +'))`'dnl +Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: libgcc1-dbg`'LS +Architecture: ifdef(`TARGET',`all',`any') +Section: debug +Priority: extra +Depends: BASEDEP, libgcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') + Debug symbols for the GCC support library. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: libgcc2`'LS +Architecture: ifdef(`TARGET',`all',`m68k') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',required) +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +ifdef(`TARGET',`Provides: libgcc2-TARGET-dcv1 +',ifdef(`MULTIARCH', `Multi-Arch: same +Pre-Depends: multiarch-support +'))`'dnl +Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: libgcc2-dbg`'LS +Architecture: ifdef(`TARGET',`all',`m68k') +Section: debug +Priority: extra +Depends: BASEDEP, libgcc2`'LS (= ${gcc:Version}), ${misc:Depends} +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') + Debug symbols for the GCC support library. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl +')`'dnl libgcc + +ifenabled(`lib4gcc',` +Package: libgcc4`'LS +Architecture: ifdef(`TARGET',`all',`hppa') +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +Pre-Depends: multiarch-support +'))`'dnl +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',required) +Depends: ifdef(`STANDALONEJAVA',`gcj`'PV-base (>= ${gcj:Version})',`BASEDEP'), ${shlibs:Depends}, ${misc:Depends} +Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: libgcc4-dbg`'LS +Architecture: ifdef(`TARGET',`all',`hppa') +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +Section: debug +Priority: extra +Depends: BASEDEP, libgcc4`'LS (= ${gcc:Version}), ${misc:Depends} +Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') + Debug symbols for the GCC support library. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl +')`'dnl lib4gcc + +ifenabled(`lib64gcc',` +Package: lib64gcc1`'LS +Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} +ifdef(`TARGET',`Provides: lib64gcc1-TARGET-dcv1 +',`')`'dnl +Conflicts: libgcc`'GCC_SO`'LS (<= 1:3.3-0pre9) +Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (64bit) + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: lib64gcc1-dbg`'LS +Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Section: debug +Priority: extra +Depends: BASEDEP, lib64gcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') + Debug symbols for the GCC support library. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl +')`'dnl lib64gcc + +ifenabled(`lib32gcc',` +Package: lib32gcc1`'LS +Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Section: ifdef(`TARGET',`devel',`libs') +Priority: extra +Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} +Conflicts: ${confl:lib32} +ifdef(`TARGET',`Provides: lib32gcc1-TARGET-dcv1 +',`')`'dnl +Description: GCC support library (32 bit Version) + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: lib32gcc1-dbg`'LS +Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, lib32gcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') + Debug symbols for the GCC support library. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl +')`'dnl lib32gcc1 + +ifenabled(`libneongcc',` +Package: libgcc1-neon`'LS +Architecture: NEON_ARCHS +Section: libs +Priority: extra +Depends: BASEDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +Description: GCC support library [neon optimized] + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. + . + This set of libraries is optimized to use a NEON coprocessor, and will + be selected instead when running under systems which have one. +')`'dnl libneongcc1 + +ifenabled(`libn32gcc',` +Package: libn32gcc1`'LS +Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, ${dep:libcbiarch}, ${misc:Depends} +ifdef(`TARGET',`Provides: libn32gcc1-TARGET-dcv1 +',`')`'dnl +Conflicts: libgcc`'GCC_SO`'LS (<= 1:3.3-0pre9) +Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (n32) + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: libn32gcc1-dbg`'LS +Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, libn32gcc1`'LS (= ${gcc:EpochVersion}), ${misc:Depends} +Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `') + Debug symbols for the GCC support library. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl +')`'dnl libn32gcc + +ifdef(`TARGET', `', ` +ifenabled(`libgmath',` +Package: libgccmath`'GCCMATH_SO`'LS +Architecture: i386 +ifdef(`MULTIARCH', `Multi-Arch: same +Pre-Depends: multiarch-support +')`'dnl +Section: libs +Priority: PRI(optional) +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +Description: GCC math support library + Support library for GCC. + +Package: lib32gccmath`'GCCMATH_SO`'LS +Architecture: amd64 +Section: libs +Priority: PRI(optional) +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +Description: GCC math support library (32bit) + Support library for GCC. + +Package: lib64gccmath`'GCCMATH_SO`'LS +Architecture: i386 +Section: libs +Priority: PRI(optional) +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +Description: GCC math support library (64bit) + Support library for GCC. +')`'dnl +')`'dnl native + +ifenabled(`cdev',` +Package: gcc`'PV`'TS +Architecture: any +Section: devel +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, cpp`'PV`'TS (= ${gcc:Version}), binutils`'TS (>= ${binutils:Version}), ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends} +Recommends: ${dep:libcdev} +Suggests: ${gcc:multilib}, libmudflap`'MF_SO`'PV-dev`'LS (>= ${gcc:Version}), gcc`'PV-doc (>= ${gcc:SoftVersion}), gcc`'PV-locales (>= ${gcc:SoftVersion}), libgcc`'GCC_SO-dbg`'LS, libgomp`'GOMP_SO-dbg`'LS, libmudflap`'MF_SO-dbg`'LS, ${dep:libcloog}, ${dep:gold} +Provides: c-compiler`'TS +Description: The GNU C compiler`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') + This is the GNU C compiler, a fairly portable optimizing compiler for C. +ifdef(`TARGET', `dnl + . + This package contains C cross-compiler for TARGET architecture. +')`'dnl + +ifenabled(`multilib',` +Package: gcc`'PV-multilib`'TS +Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS) +Section: devel +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${shlibs:Depends}, ${misc:Depends} +Suggests: ${dep:libmudflapbiarch} +Description: The GNU C compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') + This is the GNU C compiler, a fairly portable optimizing compiler for C. + . + On architectures with multilib support, the package contains files + and dependencies for the non-default multilib architecture(s). +')`'dnl multilib + +ifenabled(`plugindev',` +Package: gcc`'PV-plugin-dev`'TS +Architecture: any +Section: devel +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), GMP_BUILD_DEP ${shlibs:Depends}, ${misc:Depends} +Description: Files for GNU GCC plugin development. + This package contains (header) files for GNU GCC plugin development. It + is only used for the development of GCC plugins, but not needed to run + plugins. +')`'dnl plugindev +')`'dnl cdev + +ifenabled(`cdev',` +Package: gcc`'PV-hppa64 +Architecture: ifdef(`TARGET',`any',hppa) +Section: devel +Priority: PRI(optional) +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +Conflicts: gcc-3.3-hppa64 (<= 1:3.3.4-5), gcc-3.4-hppa64 (<= 3.4.1-3) +Description: The GNU C compiler (cross compiler for hppa64) + This is the GNU C compiler, a fairly portable optimizing compiler for C. + +ifdef(`TARGET', `', ` +Package: gcc`'PV-spu +Architecture: powerpc ppc64 +Section: devel +Priority: PRI(optional) +Depends: BASEDEP, binutils-spu (>= 2.18.1~cvs20080103-3), newlib-spu, ${shlibs:Depends}, ${misc:Depends} +Provides: spu-gcc +Description: SPU cross-compiler (preprocessor and C compiler) + GNU Compiler Collection for the Cell Broadband Engine SPU (preprocessor + and C compiler). + +Package: g++`'PV-spu +Architecture: powerpc ppc64 +Section: devel +Priority: PRI(optional) +Depends: BASEDEP, gcc`'PV-spu (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Provides: spu-g++ +Description: SPU cross-compiler (C++ compiler) + GNU Compiler Collection for the Cell Broadband Engine SPU (C++ compiler). + +Package: gfortran`'PV-spu +Architecture: powerpc ppc64 +Section: devel +Priority: PRI(optional) +Depends: BASEDEP, gcc`'PV-spu (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Provides: spu-gfortran +Description: SPU cross-compiler (Fortran compiler) + GNU Compiler Collection for the Cell Broadband Engine SPU (Fortran compiler). + +')`'dnl native +')`'dnl cdev + +ifenabled(`cdev',` +Package: cpp`'PV`'TS +Architecture: any +Section: ifdef(`TARGET',`devel',`interpreters') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +Suggests: gcc`'PV-locales (>= ${gcc:SoftVersion}) +Description: The GNU C preprocessor + A macro processor that is used automatically by the GNU C compiler + to transform programs before actual compilation. + . + This package has been separated from gcc for the benefit of those who + require the preprocessor but not the compiler. +ifdef(`TARGET', `dnl + . + This package contains preprocessor configured for TARGET architecture. +')`'dnl + +ifdef(`TARGET', `', ` +ifenabled(`gfdldoc',` +Package: cpp`'PV-doc +Architecture: all +Section: doc +Priority: PRI(optional) +Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends} +Description: Documentation for the GNU C preprocessor (cpp) + Documentation for the GNU C preprocessor in info `format'. +')`'dnl gfdldoc +')`'dnl native + +ifdef(`TARGET', `', ` +Package: gcc`'PV-locales +Architecture: all +Section: devel +Priority: PRI(optional) +Depends: SOFTBASEDEP, cpp`'PV (>= ${gcc:SoftVersion}), ${misc:Depends} +Recommends: gcc`'PV (>= ${gcc:SoftVersion}) +Description: The GNU C compiler (native language support files) + Native language support for GCC. Lets GCC speak your language, + if translations are available. + . + Please do NOT submit bug reports in other languages than "C". + Always reset your language settings to use the "C" locales. +')`'dnl native +')`'dnl cdev + +ifenabled(`c++',` +ifenabled(`c++dev',` +Package: g++`'PV`'TS +Architecture: any +Section: devel +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Provides: c++-compiler`'TS`'ifdef(`TARGET)',`',`, c++abi2-dev') +Suggests: ${gxx:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libstdc++CXX_SO`'PV-dbg`'LS +Description: The GNU C++ compiler`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') + This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. +ifdef(`TARGET', `dnl + . + This package contains C++ cross-compiler for TARGET architecture. +')`'dnl + +ifenabled(`multilib',` +Package: g++`'PV-multilib`'TS +Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS) +Section: devel +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, g++`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libcxxbiarch}, ${shlibs:Depends}, ${misc:Depends} +Suggests: ${dep:libcxxbiarchdbg} +Description: The GNU C++ compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') + This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. + . + On architectures with multilib support, the package contains files + and dependencies for the non-default multilib architecture(s). +')`'dnl multilib +')`'dnl c++dev +')`'dnl c++ + +ifenabled(`mudflap',` +ifenabled(`libmudf',` +Package: libmudflap`'MF_SO`'LS +Architecture: ifdef(`TARGET',`all',`any') +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +Pre-Depends: multiarch-support +'))`'dnl +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +Description: GCC mudflap shared support libraries + The libmudflap libraries are used by GCC for instrumenting pointer and array + dereferencing operations. + +Package: libmudflap`'MF_SO-dbg`'LS +Architecture: ifdef(`TARGET',`all',`any') +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +Section: debug +Priority: extra +Depends: BASEDEP, libmudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Description: GCC mudflap shared support libraries (debug symbols) + The libmudflap libraries are used by GCC for instrumenting pointer and array + dereferencing operations. + +Package: lib32mudflap`'MF_SO`'LS +Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: libmudflap0 (<< 4.1) +Conflicts: ${confl:lib32} +Description: GCC mudflap shared support libraries (32bit) + The libmudflap libraries are used by GCC for instrumenting pointer and array + dereferencing operations. + +Package: lib32mudflap`'MF_SO-dbg`'LS +Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, lib32mudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Description: GCC mudflap shared support libraries (32 bit debug symbols) + The libmudflap libraries are used by GCC for instrumenting pointer and array + dereferencing operations. + +Package: lib64mudflap`'MF_SO`'LS +Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: libmudflap0 (<< 4.1) +Description: GCC mudflap shared support libraries (64bit) + The libmudflap libraries are used by GCC for instrumenting pointer and array + dereferencing operations. + +Package: lib64mudflap`'MF_SO-dbg`'LS +Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Section: debug +Priority: extra +Depends: BASEDEP, lib64mudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Description: GCC mudflap shared support libraries (64 bit debug symbols) + The libmudflap libraries are used by GCC for instrumenting pointer and array + dereferencing operations. + +Package: libn32mudflap`'MF_SO`'LS +Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: libmudflap0 (<< 4.1) +Description: GCC mudflap shared support libraries (n32) + The libmudflap libraries are used by GCC for instrumenting pointer and array + dereferencing operations. + +Package: libn32mudflap`'MF_SO-dbg`'LS +Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, libn32mudflap`'MF_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Description: GCC mudflap shared support libraries (n32 debug symbols) + The libmudflap libraries are used by GCC for instrumenting pointer and array + dereferencing operations. +')`'dnl libmudf + +Package: libmudflap`'MF_SO`'PV-dev`'LS +Architecture: ifdef(`TARGET',`all',`any') +Section: ifdef(`TARGET',`devel',`libdevel') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, libmudflap`'MF_SO`'LS (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} +Suggests: ${sug:libmudflapdev} +Conflicts: libmudflap0-dev +Description: GCC mudflap support libraries (development files) + The libmudflap libraries are used by GCC for instrumenting pointer and array + dereferencing operations. + . + This package contains the headers and the static libraries. +')`'dnl mudflap + +ifdef(`TARGET', `', ` +ifenabled(`ssp',` +Package: libssp`'SSP_SO`'LS +Architecture: any +ifdef(`MULTIARCH', `Multi-Arch: same +Pre-Depends: multiarch-support +')`'dnl +Section: libs +Priority: PRI(optional) +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +Description: GCC stack smashing protection library + GCC can now emit code for protecting applications from stack-smashing attacks. + The protection is realized by buffer overflow detection and reordering of + stack variables to avoid pointer corruption. + +Package: lib32ssp`'SSP_SO`'LS +Architecture: biarch32_archs +Section: libs +Priority: PRI(optional) +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: libssp0 (<< 4.1) +Conflicts: ${confl:lib32} +Description: GCC stack smashing protection library (32bit) + GCC can now emit code for protecting applications from stack-smashing attacks. + The protection is realized by buffer overflow detection and reordering of + stack variables to avoid pointer corruption. + +Package: lib64ssp`'SSP_SO`'LS +Architecture: biarch64_archs +Section: libs +Priority: PRI(optional) +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: libssp0 (<< 4.1) +Description: GCC stack smashing protection library (64bit) + GCC can now emit code for protecting applications from stack-smashing attacks. + The protection is realized by buffer overflow detection and reordering of + stack variables to avoid pointer corruption. + +Package: libn32ssp`'SSP_SO`'LS +Architecture: biarchn32_archs +Section: libs +Priority: PRI(optional) +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Replaces: libssp0 (<< 4.1) +Description: GCC stack smashing protection library (n32) + GCC can now emit code for protecting applications from stack-smashing attacks. + The protection is realized by buffer overflow detection and reordering of + stack variables to avoid pointer corruption. +')`'dnl +')`'dnl native + +ifenabled(`libgomp',` +Package: libgomp`'GOMP_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`all',`any') +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +Pre-Depends: multiarch-support +'))`'dnl +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +Description: GCC OpenMP (GOMP) support library + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: libgomp`'GOMP_SO-dbg`'LS +Architecture: ifdef(`TARGET',`all',`any') +Section: debug +Priority: extra +Depends: BASEDEP, libgomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +Description: GCC OpenMP (GOMP) support library (debug symbols) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: lib32gomp`'GOMP_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Conflicts: ${confl:lib32} +Description: GCC OpenMP (GOMP) support library (32bit) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: lib32gomp`'GOMP_SO-dbg`'LS +Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, lib32gomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Description: GCC OpenMP (GOMP) support library (32 bit debug symbols) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: lib64gomp`'GOMP_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: GCC OpenMP (GOMP) support library (64bit) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: lib64gomp`'GOMP_SO-dbg`'LS +Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Section: debug +Priority: extra +Depends: BASEDEP, lib64gomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Description: GCC OpenMP (GOMP) support library (64bit debug symbols) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: libn32gomp`'GOMP_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: GCC OpenMP (GOMP) support library (n32) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: libn32gomp`'GOMP_SO-dbg`'LS +Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, libn32gomp`'GOMP_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Description: GCC OpenMP (GOMP) support library (n32 debug symbols) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + +ifenabled(`libneongomp',` +Package: libgomp`'GOMP_SO-neon`'LS +Architecture: NEON_ARCHS +Section: libs +Priority: extra +Depends: BASEDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +Description: GCC OpenMP (GOMP) support library [neon optimized] + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + . + This set of libraries is optimized to use a NEON coprocessor, and will + be selected instead when running under systems which have one. +')`'dnl libneongomp +')`'dnl libgomp + +ifenabled(`objpp',` +ifenabled(`objppdev',` +Package: gobjc++`'PV`'TS +Architecture: any +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), g++`'PV`'TS (= ${gcc:Version}), ${shlibs:Depends}, libobjc`'OBJC_SO`'LS (>= ${gcc:Version}), ${misc:Depends} +Suggests: ${gobjcxx:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}) +Provides: objc++-compiler`'TS +Description: The GNU Objective-C++ compiler + This is the GNU Objective-C++ compiler, which compiles + Objective-C++ on platforms supported by the gcc compiler. It uses the + gcc backend to generate optimized code. +')`'dnl obcppdev + +ifenabled(`multilib',` +Package: gobjc++`'PV-multilib`'TS +Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS) +Section: devel +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, gobjc++`'PV`'TS (= ${gcc:Version}), g++`'PV-multilib`'TS (= ${gcc:Version}), gobjc`'PV-multilib`'TS (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: The GNU Objective-C++ compiler (multilib files) + This is the GNU Objective-C++ compiler, which compiles Objective-C++ on + platforms supported by the gcc compiler. + . + On architectures with multilib support, the package contains files + and dependencies for the non-default multilib architecture(s). +')`'dnl multilib +')`'dnl obcpp + +ifenabled(`objc',` +ifenabled(`objcdev',` +Package: gobjc`'PV`'TS +Architecture: any +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libobjc`'OBJC_SO`'LS (>= ${gcc:Version}), ${misc:Depends} +Suggests: ${gobjc:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libobjc`'OBJC_SO-dbg`'LS +Provides: objc-compiler`'TS +ifdef(`__sparc__',`Conflicts: gcc`'PV-sparc64', `dnl') +Description: The GNU Objective-C compiler + This is the GNU Objective-C compiler, which compiles + Objective-C on platforms supported by the gcc compiler. It uses the + gcc backend to generate optimized code. + +ifenabled(`multilib',` +Package: gobjc`'PV-multilib`'TS +Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS) +Section: devel +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libobjcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: The GNU Objective-C compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') + This is the GNU Objective-C compiler, which compiles Objective-C on platforms + supported by the gcc compiler. + . + On architectures with multilib support, the package contains files + and dependencies for the non-default multilib architecture(s). +')`'dnl multilib +')`'dnl objcdev + +ifenabled(`libobjc',` +Package: libobjc`'OBJC_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`all',`any') +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +Pre-Depends: multiarch-support +'))`'dnl +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications + Library needed for GNU ObjC applications linked against the shared library. + +Package: libobjc`'OBJC_SO-dbg`'LS +Section: debug +Architecture: ifdef(`TARGET',`all',`any') +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +Priority: extra +Depends: BASEDEP, libobjc`'OBJC_SO`'LS (= ${gcc:Version}), libgcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications (debug symbols) + Library needed for GNU ObjC applications linked against the shared library. +')`'dnl libobjc + +ifenabled(`lib64objc',` +Package: lib64objc`'OBJC_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications (64bit) + Library needed for GNU ObjC applications linked against the shared library. + +Package: lib64objc`'OBJC_SO-dbg`'LS +Section: debug +Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Priority: extra +Depends: BASEDEP, lib64objc`'OBJC_SO`'LS (= ${gcc:Version}), lib64gcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications (64 bit debug symbols) + Library needed for GNU ObjC applications linked against the shared library. +')`'dnl lib64objc + +ifenabled(`lib32objc',` +Package: lib32objc`'OBJC_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: gcc`'PV-base (>= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Conflicts: ${confl:lib32} +Description: Runtime library for GNU Objective-C applications (32bit) + Library needed for GNU ObjC applications linked against the shared library. + +Package: lib32objc`'OBJC_SO-dbg`'LS +Section: debug +Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Priority: extra +Depends: BASEDEP, lib32objc`'OBJC_SO`'LS (= ${gcc:Version}), lib32gcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications (32 bit debug symbols) + Library needed for GNU ObjC applications linked against the shared library. +')`'dnl lib32objc + +ifenabled(`libn32objc',` +Package: libn32objc`'OBJC_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: gcc`'PV-base (>= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications (n32) + Library needed for GNU ObjC applications linked against the shared library. + +Package: libn32objc`'OBJC_SO-dbg`'LS +Section: debug +Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Priority: extra +Depends: BASEDEP, libn32objc`'OBJC_SO`'LS (= ${gcc:Version}), libn32gcc`'GCC_SO-dbg`'LS, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications (n32 debug symbols) + Library needed for GNU ObjC applications linked against the shared library. +')`'dnl libn32objc + +ifenabled(`libneonobjc',` +Package: libobjc`'OBJC_SO-neon`'LS +Section: libs +Architecture: NEON_ARCHS +Priority: PRI(optional) +Depends: BASEDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications [NEON version] + Library needed for GNU ObjC applications linked against the shared library. + . + This set of libraries is optimized to use a NEON coprocessor, and will + be selected instead when running under systems which have one. +')`'dnl libneonobjc +')`'dnl objc + +ifenabled(`fortran',` +ifenabled(`fdev',` +Package: gfortran`'PV`'TS +Architecture: any +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libgfortran`'FORTRAN_SO`'LS (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} +Provides: fortran95-compiler +Suggests: ${gfortran:multilib}, gfortran`'PV-doc, libgfortran`'FORTRAN_SO-dbg`'LS +Replaces: libgfortran`'FORTRAN_SO-dev +Description: The GNU Fortran 95 compiler + This is the GNU Fortran compiler, which compiles + Fortran 95 on platforms supported by the gcc compiler. It uses the + gcc backend to generate optimized code. + +ifenabled(`multilib',` +Package: gfortran`'PV-multilib`'TS +Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS) +Section: devel +Priority: ifdef(`TARGET',`extra',`PRI(optional)') +Depends: BASEDEP, gfortran`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libgfortranbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: The GNU Fortran 95 compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') + This is the GNU Fortran compiler, which compiles Fortran 95 on platforms + supported by the gcc compiler. + . + On architectures with multilib support, the package contains files + and dependencies for the non-default multilib architecture(s). +')`'dnl multilib + +ifenabled(`gfdldoc',` +Package: gfortran`'PV-doc +Architecture: all +Section: doc +Priority: PRI(optional) +Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends} +Description: Documentation for the GNU Fortran compiler (gfortran) + Documentation for the GNU Fortran 95 compiler in info `format'. +')`'dnl gfdldoc +')`'dnl fdev + +ifenabled(`libgfortran',` +Package: libgfortran`'FORTRAN_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`all',`any') +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +Pre-Depends: multiarch-support +'))`'dnl +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Fortran applications + Library needed for GNU Fortran applications linked against the + shared library. + +Package: libgfortran`'FORTRAN_SO-dbg`'LS +Section: debug +Architecture: ifdef(`TARGET',`all',`any') +ifdef(`TARGET',`',ifdef(`MULTIARCH', `Multi-Arch: same +'))`'dnl +Priority: extra +Depends: BASEDEP, libgfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Description: Runtime library for GNU Fortran applications (debug symbols) + Library needed for GNU Fortran applications linked against the + shared library. +')`'dnl libgfortran + +ifenabled(`lib64gfortran',` +Package: lib64gfortran`'FORTRAN_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Fortran applications (64bit) + Library needed for GNU Fortran applications linked against the + shared library. + +Package: lib64gfortran`'FORTRAN_SO-dbg`'LS +Section: debug +Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Priority: extra +Depends: BASEDEP, lib64gfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Description: Runtime library for GNU Fortran applications (64bit debug symbols) + Library needed for GNU Fortran applications linked against the + shared library. +')`'dnl lib64gfortran + +ifenabled(`lib32gfortran',` +Package: lib32gfortran`'FORTRAN_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Conflicts: ${confl:lib32} +Description: Runtime library for GNU Fortran applications (32bit) + Library needed for GNU Fortran applications linked against the + shared library. + +Package: lib32gfortran`'FORTRAN_SO-dbg`'LS +Section: debug +Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Priority: extra +Depends: BASEDEP, lib32gfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Description: Runtime library for GNU Fortran applications (32 bit debug symbols) + Library needed for GNU Fortran applications linked against the + shared library. +')`'dnl lib32gfortran + +ifenabled(`libn32gfortran',` +Package: libn32gfortran`'FORTRAN_SO`'LS +Section: ifdef(`TARGET',`devel',`libs') +Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Fortran applications (n32) + Library needed for GNU Fortran applications linked against the + shared library. + +Package: libn32gfortran`'FORTRAN_SO-dbg`'LS +Section: debug +Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Priority: extra +Depends: BASEDEP, libn32gfortran`'FORTRAN_SO`'LS (= ${gcc:Version}), ${misc:Depends} +Description: Runtime library for GNU Fortran applications (n32 debug symbols) + Library needed for GNU Fortran applications linked against the + shared library. +')`'dnl libn32gfortran + +ifenabled(`libneongfortran',` +Package: libgfortran`'FORTRAN_SO-neon`'LS +Section: libs +Architecture: NEON_ARCHS +ifdef(`MULTIARCH', `Multi-Arch: same +Pre-Depends: multiarch-support +')`'dnl +Priority: extra +Depends: BASEDEP, libgcc1-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Fortran applications [NEON version] + Library needed for GNU Fortran applications linked against the + shared library. + . + This set of libraries is optimized to use a NEON coprocessor, and will + be selected instead when running under systems which have one. +')`'dnl libneongfortran +')`'dnl fortran + +ifenabled(`java',` +ifenabled(`gcj',` +Package: gcj`'PV-jdk +Section: java +Architecture: any +Priority: PRI(optional) +Depends: gcj`'PV-base (= ${gcj:Version}), ${dep:gcj}, ${dep:libcdev}, gcj`'PV-jre (= ${gcj:Version}), libgcj`'GCJ_SO-dev (= ${gcj:Version}), gcj`'PV-jre-lib (>= ${gcj:SoftVersion}), ${dep:ecj}, fastjar, libgcj-bc, java-common, libantlr-java, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends} +Recommends: libecj-java-gcj +Suggests: gcj`'PV-source (>= ${gcj:SoftVersion}), libgcj`'GCJ_SO-dbg +Provides: java-compiler, java-sdk, java2-sdk, java5-sdk +Conflicts: gcj-4.4, cpp-4.1 (<< 4.1.1), gcc-4.1 (<< 4.1.1) +Replaces: libgcj11 (<< 4.5-20100101-1) +Description: gcj and classpath development tools for Java(TM) + GCJ is a front end to the GCC compiler which can natively compile both + Java(tm) source and bytecode files. The compiler can also generate class + files. Other java development tools from classpath are included in this + package. + . + The package contains as well a collection of wrapper scripts and symlinks. + It is meant to provide a Java-SDK-like interface to the GCJ tool set. +')`'dnl gcj + +ifenabled(`libgcj',` +ifenabled(`libgcjcommon',` +Package: libgcj-common +Section: java +Architecture: all +Priority: PRI(optional) +Depends: gcj`'PV-base (>= ${gcj:SoftVersion}), ${misc:Depends} +Conflicts: classpath (<= 0.04-4) +Replaces: java-gcj-compat (<< 1.0.65-3), java-gcj-compat-dev (<< 1.0.65-3) +Description: Java runtime library (common files) + This package contains files shared by classpath and libgcj libraries. +')`'dnl libgcjcommon + +Package: gcj`'PV-jre-headless +Priority: optional +Section: java +Architecture: any +Depends: gcj`'PV-base (= ${gcj:Version}), libgcj`'LIBGCJ_EXT (= ${gcj:Version}), ${dep:prctl}, ${shlibs:Depends}, ${misc:Depends} +Suggests: fastjar, gcj`'PV-jdk (= ${gcj:Version}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}) +Conflicts: gij-4.4, java-gcj-compat (<< 1.0.76-4) +Provides: java5-runtime-headless, java2-runtime-headless, java1-runtime-headless, java-runtime-headless +Description: Java runtime environment using GIJ/classpath (headless version) + GIJ is a Java bytecode interpreter, not limited to interpreting bytecode. + It includes a class loader which can dynamically load shared objects, so + it is possible to give it the name of a class which has been compiled and + put into a shared library on the class path. + . + The package contains as well a collection of wrapper scripts and symlinks. + It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set, + limited to the headless tools and libraries. + +Package: gcj`'PV-jre +Section: java +Architecture: any +Priority: PRI(optional) +Depends: gcj`'PV-base (= ${gcj:Version}), gcj`'PV-jre-headless (= ${gcj:Version}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +Provides: java5-runtime, java2-runtime, java1-runtime, java-runtime +Description: Java runtime environment using GIJ/classpath + GIJ is a Java bytecode interpreter, not limited to interpreting bytecode. + It includes a class loader which can dynamically load shared objects, so + it is possible to give it the name of a class which has been compiled and + put into a shared library on the class path. + . + The package contains as well a collection of wrapper scripts and symlinks. + It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set. + +Package: libgcj`'LIBGCJ_EXT +Section: libs +Architecture: any +Priority: PRI(optional) +Depends: gcj`'PV-base (>= ${gcj:Version}), libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends} +Recommends: gcj`'PV-jre-lib (>= ${gcj:SoftVersion}) +Suggests: libgcj`'GCJ_SO-dbg, libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}) +Replaces: gij-4.4 (<< 4.4.0-1) +Description: Java runtime library for use with gcj + This is the runtime that goes along with the gcj front end to + gcc. libgcj includes parts of the Java Class Libraries, plus glue to + connect the libraries to the compiler and the underlying OS. + . + To show file names and line numbers in stack traces, the packages + libgcj`'GCJ_SO-dbg and binutils are required. + +Package: gcj`'PV-jre-lib +Section: java +Architecture: all +Priority: PRI(optional) +Depends: gcj`'PV-base (>= ${gcj:SoftVersion}), libgcj`'LIBGCJ_EXT (>= ${gcj:SoftVersion}), ${misc:Depends} +Description: Java runtime library for use with gcj (jar files) + This is the jar file that goes along with the gcj front end to gcc. + +ifenabled(`gcjbc',` +Package: libgcj-bc +Section: java +Architecture: any +Priority: PRI(optional) +Depends: gcj`'PV-base (>= ${gcj:Version}), libgcj`'LIBGCJ_EXT (>= ${gcj:Version}), ${misc:Depends} +Description: Link time only library for use with gcj + A fake library that is used at link time only. It ensures that + binaries built with the BC-ABI link against a constant SONAME. + This way, BC-ABI binaries continue to work if the SONAME underlying + libgcj.so changes. +')`'dnl gcjbc + +Package: libgcj`'LIBGCJ_EXT-awt +Section: libs +Architecture: any +Priority: PRI(optional) +Depends: gcj`'PV-base (>= ${gcj:Version}), libgcj`'LIBGCJ_EXT (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +Suggests: ${pkg:gcjqt} +Description: AWT peer runtime libraries for use with gcj + These are runtime libraries holding the AWT peer implementations + for libgcj (currently the GTK+ based peer library is required, the + QT bases library is not built). + +ifenabled(`gtkpeer',` +Package: libgcj`'GCJ_SO-awt-gtk +Section: libs +Architecture: any +Priority: PRI(optional) +Depends: gcj`'PV-base (= ${gcj:Version}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: AWT GTK+ peer runtime library for use with libgcj + This is the runtime library holding the GTK+ based AWT peer + implementation for libgcj. +')`'dnl gtkpeer + +ifenabled(`qtpeer',` +Package: libgcj`'GCJ_SO-awt-qt +Section: libs +Architecture: any +Priority: PRI(optional) +Depends: gcj`'PV-base (= ${gcj:Version}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: AWT QT peer runtime library for use with libgcj + This is the runtime library holding the QT based AWT peer + implementation for libgcj. +')`'dnl qtpeer +')`'dnl libgcj + +ifenabled(`libgcjdev',` +Package: libgcj`'GCJ_SO-dev +Section: libdevel +Architecture: any +Priority: PRI(optional) +Depends: gcj`'PV-base (= ${gcj:Version}), gcj`'PV-jdk (= ${gcj:Version}), gcj`'PV-jre-lib (>= ${gcj:SoftVersion}), libgcj`'LIBGCJ_EXT-awt (= ${gcj:Version}), libgcj-bc, ${pkg:gcjgtk}, ${pkg:gcjqt}, zlib1g-dev, ${shlibs:Depends}, ${misc:Depends} +Suggests: libgcj-doc +Description: Java development headers for use with gcj + These are the development headers that go along with the gcj front end + to gcc. libgcj includes parts of the Java Class Libraries, plus glue + to connect the libraries to the compiler and the underlying OS. + +Package: libgcj`'GCJ_SO-dbg +Section: debug +Architecture: any +Priority: extra +Depends: gcj`'PV-base (= ${gcj:Version}), libgcj`'LIBGCJ_EXT (= ${gcj:Version}), ${misc:Depends} +Recommends: binutils, libc6-dbg | libc-dbg +Description: Debugging symbols for libraries provided in libgcj`'GCJ_SO-dev + The package provides debugging symbols for the libraries provided + in libgcj`'GCJ_SO-dev. + . + binutils is required to show file names and line numbers in stack traces. + +Package: gcj`'PV-source +Section: java +Architecture: all +Priority: PRI(optional) +Depends: gcj`'PV-base (>= ${gcj:SoftVersion}), gcj`'PV-jdk (>= ${gcj:SoftVersion}), ${misc:Depends} +Description: GCJ java sources for use in IDEs like eclipse and netbeans + These are the java source files packaged as a zip file for use in development + environments like eclipse and netbeans. + +ifenabled(`gcjdoc',` +Package: libgcj-doc +Section: doc +Architecture: all +Priority: PRI(optional) +Depends: gcj`'PV-base (>= ${gcj:SoftVersion}), ${misc:Depends} +Enhances: libgcj`'GCJ_SO-dev +Provides: classpath-doc +Description: libgcj API documentation and example programs + Autogenerated documentation describing the API of the libgcj library. + Sources and precompiled example programs from the classpath library. +')`'dnl gcjdoc +')`'dnl libgcjdev +')`'dnl java + +ifenabled(`c++',` +ifenabled(`libcxx',` +Package: libstdc++CXX_SO`'LS +Architecture: ifdef(`TARGET',`all',`any') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',PRI(required)) +Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} +ifdef(`TARGET',`Provides: libstdc++CXX_SO-TARGET-dcv1 +',ifdef(`MULTIARCH', `Multi-Arch: same +Pre-Depends: multiarch-support +'))`'dnl +Conflicts: scim (<< 1.4.2-1) +Description: The GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') + This package contains an additional runtime library for C++ programs + built with the GNU compiler. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl +')`'dnl libcxx + +ifenabled(`lib32cxx',` +Package: lib32stdc++CXX_SO`'LS +Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Section: ifdef(`TARGET',`devel',`libs') +Priority: extra +Depends: BASEDEP, lib32gcc1`'LS, ${shlibs:Depends}, ${misc:Depends} +Conflicts: ${confl:lib32} +ifdef(`TARGET',`Provides: lib32stdc++CXX_SO-TARGET-dcv1 +',`')`'dnl +Description: The GNU Standard C++ Library v3 (32 bit Version) + This package contains an additional runtime library for C++ programs + built with the GNU compiler. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl +')`'dnl lib32cxx + +ifenabled(`lib64cxx',` +Package: lib64stdc++CXX_SO`'LS +Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, ${shlibs:Depends}, lib64gcc1`'LS, ${misc:Depends} +ifdef(`TARGET',`Provides: lib64stdc++CXX_SO-TARGET-dcv1 +',`')`'dnl +Description: The GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (64bit) + This package contains an additional runtime library for C++ programs + built with the GNU compiler. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl +')`'dnl lib64cxx + +ifenabled(`libn32cxx',` +Package: libn32stdc++CXX_SO`'LS +Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Section: ifdef(`TARGET',`devel',`libs') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, ${shlibs:Depends}, libn32gcc1`'LS, ${misc:Depends} +ifdef(`TARGET',`Provides: libn32stdc++CXX_SO-TARGET-dcv1 +',`')`'dnl +Description: The GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (n32) + This package contains an additional runtime library for C++ programs + built with the GNU compiler. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl +')`'dnl libn32cxx + +ifenabled(`libneoncxx',` +Package: libstdc++CXX_SO-neon`'LS +Architecture: NEON_ARCHS +Section: libs +Priority: extra +Depends: BASEDEP, libc6-neon`'LS, libgcc1-neon`'LS, ${shlibs:Depends}, ${misc:Depends} +Description: The GNU Standard C++ Library v3 [NEON version] + This package contains an additional runtime library for C++ programs + built with the GNU compiler. + . + This set of libraries is optimized to use a NEON coprocessor, and will + be selected instead when running under systems which have one. +')`'dnl + +ifenabled(`c++dev',` +Package: libstdc++CXX_SO`'PV-dev`'LS +Architecture: ifdef(`TARGET',`all',`any') +Section: ifdef(`TARGET',`devel',`libdevel') +Priority: ifdef(`TARGET',`extra',PRI(optional)) +Depends: BASEDEP, g++`'PV`'TS (= ${gcc:Version}), libstdc++CXX_SO`'LS (>= ${gcc:Version}), ${dep:libcdev}, ${misc:Depends} +ifdef(`TARGET',`',`dnl native +Conflicts: libg++27-dev, libg++272-dev (<< 2.7.2.8-1), libstdc++2.8-dev, libg++2.8-dev, libstdc++2.9-dev, libstdc++2.9-glibc2.1-dev, libstdc++2.10-dev (<< 1:2.95.3-2), libstdc++3.0-dev +Suggests: libstdc++CXX_SO`'PV-doc +')`'dnl native +Provides: libstdc++-dev`'LS`'dnl +ifdef(`TARGET',`, libstdc++-dev-TARGET-dcv1, libstdc++CXX_SO-dev-TARGET-dcv1 +',` +')`'dnl +Description: The GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET)',` (TARGET)', `') + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: libstdc++CXX_SO`'PV-pic`'LS +Architecture: ifdef(`TARGET',`all',`any') +Section: ifdef(`TARGET',`devel',`libdevel') +Priority: extra +Depends: BASEDEP, libstdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), ${misc:Depends} +ifdef(`TARGET',`Provides: libstdc++CXX_SO-pic-TARGET-dcv1 +',`')`'dnl +Description: The GNU Standard C++ Library v3 (shared library subset kit)`'ifdef(`TARGET)',` (TARGET)', `') + This is used to develop subsets of the libstdc++ shared libraries for + use on custom installation floppies and in embedded systems. + . + Unless you are making one of those, you will not need this package. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: libstdc++CXX_SO`'PV-dbg`'LS +Architecture: ifdef(`TARGET',`all',`any') +Section: debug +Priority: extra +Depends: BASEDEP, libstdc++CXX_SO`'LS (>= ${gcc:Version}), libgcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +ifdef(`TARGET',`Provides: libstdc++CXX_SO-dbg-TARGET-dcv1 +',`')`'dnl +Recommends: libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}) +Conflicts: libstdc++5-dbg`'LS, libstdc++5-3.3-dbg`'LS, libstdc++6-dbg`'LS, libstdc++6-4.0-dbg`'LS, libstdc++6-4.1-dbg`'LS, libstdc++6-4.2-dbg`'LS, libstdc++6-4.3-dbg`'LS, libstdc++6-4.4-dbg`'LS +Description: The GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') + This package contains the shared library of libstdc++ compiled with + debugging symbols. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: lib32stdc++CXX_SO`'PV-dbg`'LS +Architecture: ifdef(`TARGET',`all',`biarch32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, lib32stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), lib32gcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +ifdef(`TARGET',`Provides: lib32stdc++CXX_SO-dbg-TARGET-dcv1 +',`')`'dnl +Conflicts: lib32stdc++6-dbg`'LS, lib32stdc++6-4.0-dbg`'LS, lib32stdc++6-4.1-dbg`'LS, lib32stdc++6-4.2-dbg`'LS, lib32stdc++6-4.3-dbg`'LS, lib32stdc++6-4.4-dbg`'LS +Description: The GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') + This package contains the shared library of libstdc++ compiled with + debugging symbols. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: lib64stdc++CXX_SO`'PV-dbg`'LS +Architecture: ifdef(`TARGET',`all',`biarch64_archs') +Section: debug +Priority: extra +Depends: BASEDEP, lib64stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), lib64gcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +ifdef(`TARGET',`Provides: lib64stdc++CXX_SO-dbg-TARGET-dcv1 +',`')`'dnl +Conflicts: lib64stdc++6-dbg`'LS, lib64stdc++6-4.0-dbg`'LS, lib64stdc++6-4.1-dbg`'LS, lib64stdc++6-4.2-dbg`'LS, lib64stdc++6-4.3-dbg`'LS, lib64stdc++6-4.4-dbg`'LS +Description: The GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') + This package contains the shared library of libstdc++ compiled with + debugging symbols. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +Package: libn32stdc++CXX_SO`'PV-dbg`'LS +Architecture: ifdef(`TARGET',`all',`biarchn32_archs') +Section: debug +Priority: extra +Depends: BASEDEP, libn32stdc++CXX_SO`'LS (>= ${gcc:Version}), libstdc++CXX_SO`'PV-dev`'LS (= ${gcc:Version}), libn32gcc`'GCC_SO-dbg`'LS, ${shlibs:Depends}, ${misc:Depends} +ifdef(`TARGET',`Provides: libn32stdc++CXX_SO-dbg-TARGET-dcv1 +',`')`'dnl +Conflicts: libn32stdc++6-dbg`'LS, libn32stdc++6-4.0-dbg`'LS, libn32stdc++6-4.1-dbg`'LS, libn32stdc++6-4.2-dbg`'LS, libn32stdc++6-4.3-dbg`'LS, libn32stdc++6-4.4-dbg`'LS +Description: The GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `') + This package contains the shared library of libstdc++ compiled with + debugging symbols. +ifdef(`TARGET', `dnl + . + This package contains files for TARGET architecture, for use in cross-compile + environment. +')`'dnl + +ifdef(`TARGET', `', ` +Package: libstdc++CXX_SO`'PV-doc +Architecture: all +Section: doc +Priority: PRI(optional) +Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), ${misc:Depends} +Conflicts: libstdc++5-doc, libstdc++5-3.3-doc, libstdc++6-doc, libstdc++6-4.0-doc, libstdc++6-4.1-doc, libstdc++6-4.2-doc, libstdc++6-4.3-doc, libstdc++6-4.4-doc +Description: The GNU Standard C++ Library v3 (documentation files) + This package contains documentation files for the GNU stdc++ library. + . + One set is the distribution documentation, the other set is the + source documentation including a namespace list, class hierarchy, + alphabetical list, compound list, file list, namespace members, + compound members and file members. +')`'dnl native +')`'dnl c++dev +')`'dnl c++ + +ifenabled(`ada',` +Package: gnat`'-GNAT_V +Architecture: any +Priority: PRI(optional) +Depends: gnat`'PV-base (= ${gnat:Version}), gcc`'PV (>= ${gcc:SoftVersion}), ${dep:libgnat}, ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} +Suggests: gnat`'PV-doc, ada-reference-manual +Provides: ada-compiler +Conflicts: gnat (<< 4.1), gnat-3.1, gnat-3.2, gnat-3.3, gnat-3.4, gnat-3.5, gnat-4.0, gnat-4.1, gnat-4.2, gnat-4.3, gnat-4.4 +Description: The GNU Ada compiler + This is the GNU Ada compiler, which compiles Ada on platforms supported + by the gcc compiler. It uses the gcc backend to generate optimized code. + +ifenabled(`libgnat',` +Package: libgnat`'-GNAT_V +Section: libs +Architecture: any +Priority: PRI(optional) +Depends: gnat`'PV-base (= ${gnat:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Ada applications + Library needed for GNU Ada applications linked against the shared library. + +Package: libgnat`'-GNAT_V-dbg +Section: debug +Architecture: any +Priority: extra +Depends: gnat`'PV-base (= ${gnat:Version}), libgnat`'-GNAT_V (= ${gnat:Version}), ${misc:Depends} +Recommends: gnat-gdb (>= 6.4) +Description: Runtime library for GNU Ada applications + Debugging symbols for the library needed for GNU Ada applications linked + against the shared library. + +Package: libgnatvsn`'GNAT_V-dev +Section: libdevel +Architecture: any +Priority: PRI(optional) +Depends: gnat`'PV-base (= ${gnat:Version}), gnat`'PV (= ${gnat:Version}), libgnatvsn`'GNAT_V (= ${gnat:Version}), ${misc:Depends} +Conflicts: libgnatvsn-dev (<< `'GNAT_V), libgnatvsn4.1-dev, libgnatvsn4.3-dev, libgnatvsn4.4-dev +Description: GNU Ada compiler version library - development files + This library exports selected components of GNAT, the GNU Ada compiler, for use + in other packages, most notably ASIS and ASIS-based packages. It is licensed + under the GNAT-Modified GPL, allowing to link proprietary programs with it. + . + This package contains the development files and static library. + +Package: libgnatvsn`'GNAT_V +Architecture: any +Priority: PRI(optional) +Section: libs +Depends: gnat`'PV-base (= ${gnat:Version}), libgnat`'-GNAT_V (= ${gnat:Version}), ${misc:Depends} +Description: GNU Ada compiler version library + This library exports selected components of GNAT, the GNU Ada compiler, for use + in other packages, most notably ASIS and ASIS-based packages. It is licensed + under the GNAT-Modified GPL, allowing to link proprietary programs with it. + . + This package contains the run-time shared library. + +Package: libgnatvsn`'GNAT_V-dbg +Architecture: any +Priority: extra +Section: debug +Depends: gnat`'PV-base (= ${gnat:Version}), libgnatvsn`'GNAT_V (= ${gnat:Version}), ${misc:Depends} +Recommends: gnat-gdb (>= 6.4), libgnatvsn-dev (= ${gnat:Version}) +Description: GNU Ada compiler version library + This library exports selected components of GNAT, the GNU Ada compiler, for use + in other packages, most notably ASIS and ASIS-based packages. It is licensed + under the GNAT-Modified GPL, allowing to link proprietary programs with it. + . + This package contains the debugging symbols for the run-time shared library. + +Package: libgnatprj`'GNAT_V-dev +Section: libdevel +Architecture: any +Priority: PRI(optional) +Depends: gnat`'PV-base (= ${gnat:Version}), gnat`'PV (= ${gnat:Version}), libgnatprj`'GNAT_V (= ${gnat:Version}), libgnatvsn`'GNAT_V-dev (= ${gnat:Version}), ${misc:Depends} +Conflicts: libgnatprj-dev (<< `'GNAT_V), libgnatprj4.1-dev, libgnatprj4.3-dev, libgnatprj4.4-dev +Description: GNU Ada Project Manager development files + GNAT, the GNU Ada compiler, uses project files to organise source and object + files in large-scale development efforts. Several other tools, such as + ASIS tools (package asis-programs) and GNAT Programming Studio (package + gnat-gps) also use project files. This library contains the necessary + support; it was built from GNAT itself. It is licensed under the pure GPL; + all programs that use it must also be distributed under the GPL, or not + distributed at all. + . + This package contains development files: install it to develop applications + that understand GNAT project files. + +Package: libgnatprj`'GNAT_V +Architecture: any +Priority: PRI(optional) +Section: libs +Depends: gnat`'PV-base (= ${gnat:Version}), libgnat`'-GNAT_V (= ${gnat:Version}), libgnatvsn`'GNAT_V (= ${gnat:Version}), ${misc:Depends} +Description: GNU Ada Project Manager + GNAT, the GNU Ada compiler, uses project files to organise source and object + files in large-scale development efforts. Several other tools, such as + ASIS tools (package asis-programs) and GNAT Programming Studio (package + gnat-gps) also use project files. This library contains the necessary + support; it was built from GNAT itself. It is licensed under the pure GPL; + all programs that use it must also be distributed under the GPL, or not + distributed at all. + . + This package contains the run-time shared library. + +Package: libgnatprj`'GNAT_V-dbg +Architecture: any +Priority: extra +Section: debug +Depends: gnat`'PV-base (= ${gnat:Version}), libgnatprj`'GNAT_V (= ${gnat:Version}), ${misc:Depends} +Recommends: gnat-gdb (>= 6.4), libgnatprj-dev (= ${gnat:Version}) +Description: GNU Ada Project Manager + GNAT, the GNU Ada compiler, uses project files to organise source and object + files in large-scale development efforts. Several other tools, such as + ASIS tools (package asis-programs) and GNAT Programming Studio (package + gnat-gps) also use project files. This library contains the necessary + support; it was built from GNAT itself. It is licensed under the pure GPL; + all programs that use it must also be distributed under the GPL, or not + distributed at all. + . + This package contains the debugging symbols for the run-time shared library. +')`'dnl libgnat + +ifenabled(`lib64gnat',` +Package: lib64gnat`'-GNAT_V +Section: libs +Architecture: biarch64_archs +Priority: PRI(optional) +Depends: gnat`'PV-base (= ${gnat:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Ada applications + Library needed for GNU Ada applications linked against the shared library. +')`'dnl libgnat + +ifenabled(`gfdldoc',` +Package: gnat`'PV-doc +Architecture: all +Section: doc +Priority: PRI(optional) +Depends: dpkg (>= 1.15.4) | install-info, ${misc:Depends} +Suggests: gnat`'PV +Conflicts: gnat-4.1-doc, gnat-4.2-doc, gnat-4.3-doc, gnat-4.4-doc +Description: Documentation for the GNU Ada compiler (gnat) + Documentation for the GNU Ada compiler in info `format'. +')`'dnl gfdldoc +')`'dnl ada + +ifenabled(`d ',` +Package: gdc`'PV +Architecture: i386 amd64 powerpc ppc64 lpia kfreebsd-i386 kfreebsd-amd64 +Priority: PRI(optional) +Depends: SOFTBASEDEP, g++`'PV (>= ${gcc:SoftVersion}), zlib1g-dev, ${shlibs:Depends}, ${misc:Depends} +Provides: gdc, d-compiler +Description: The D compiler + This is the D compiler, which compiles D on platforms supported by the gcc + compiler. It uses the GCC backend to generate optimised code. +Homepage: http://dgcc.sourceforge.net/ +')`'dnl d + +ifdef(`TARGET',`',`dnl +ifenabled(`libs',` +Package: gcc`'PV-soft-float +Architecture: arm armel +Priority: PRI(optional) +Depends: BASEDEP, ifenabled(`cdev',`gcc`'PV (= ${gcc:Version}),') ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc-soft-float-ss +Description: The soft-floating-point gcc libraries (arm) + These are versions of basic static libraries such as libgcc.a compiled + with the -msoft-float option, for CPUs without a floating-point unit. +')`'dnl commonlibs +')`'dnl + +ifenabled(`fixincl',` +Package: fixincludes +Architecture: any +Priority: PRI(optional) +Depends: BASEDEP, gcc`'PV (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: Fix non-ANSI header files + FixIncludes was created to fix non-ANSI system header files. Many + system manufacturers supply proprietary headers that are not ANSI compliant. + The GNU compilers cannot compile non-ANSI headers. Consequently, the + FixIncludes shell script was written to fix the header files. + . + Not all packages with header files are installed on the system, when the + package is built, so we make fixincludes available at build time of other + packages, such that checking tools like lintian can make use of it. +')`'dnl fixincl + +ifenabled(`cdev',` +ifdef(`TARGET', `', ` +ifenabled(`gfdldoc',` +Package: gcc`'PV-doc +Architecture: all +Section: doc +Priority: PRI(optional) +Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends} +Conflicts: gcc-docs (<< 2.95.2) +Replaces: gcc (<=2.7.2.3-4.3), gcc-docs (<< 2.95.2) +Description: Documentation for the GNU compilers (gcc, gobjc, g++) + Documentation for the GNU compilers in info `format'. +')`'dnl gfdldoc +')`'dnl native +')`'dnl cdev + +ifdef(`TARGET',`',`dnl +ifenabled(`libnof',` +Package: gcc`'PV-nof +Architecture: powerpc +Priority: PRI(optional) +Depends: BASEDEP, ${shlibs:Depends}ifenabled(`cdev',`, gcc`'PV (= ${gcc:Version})'), ${misc:Depends} +Conflicts: gcc-3.2-nof +Description: The no-floating-point gcc libraries (powerpc) + These are versions of basic static libraries such as libgcc.a compiled + with the -msoft-float option, for CPUs without a floating-point unit. +')`'dnl libnof +')`'dnl + +ifenabled(`source',` +Package: gcc`'PV-source +Architecture: all +Priority: PRI(optional) +Depends: make (>= 3.81), autoconf2.64, automake, quilt, patchutils, ${misc:Depends} +Description: Source of the GNU Compiler Collection + This package contains the sources and patches which are needed to + build the GNU Compiler Collection (GCC). +')`'dnl source +dnl +')`'dnl gcc-X.Y +dnl last line in file --- gcc-4.5-4.5.2.orig/debian/README.libstdc++-baseline.in +++ gcc-4.5-4.5.2/debian/README.libstdc++-baseline.in @@ -0,0 +1,2 @@ +The libstdc++ baseline file is a list of symbols exported by the +libstdc++ library. --- gcc-4.5-4.5.2.orig/debian/README.ssp +++ gcc-4.5-4.5.2/debian/README.ssp @@ -0,0 +1,28 @@ +Stack smashing protection is a feature of GCC that enables a program to +detect buffer overflows and immediately terminate execution, rather than +continuing execution with corrupt internal data structures. It uses +"canaries" and local variable reordering to reduce the likelihood of +stack corruption through buffer overflows. + +Options that affect stack smashing protection: + +-fstack-protector + Enables protection for functions that are vulnerable to stack + smashing, such as those that call alloca() or use pointers. + +-fstack-protector-all + Enables protection for all functions. + +-Wstack-protector + Warns about functions that will not be protected. Only active when + -fstack-protector has been used. + +Applications built with stack smashing protection should link with the +ssp library by using the option "-lssp" for systems with glibc-2.3.x or +older; glibc-2.4 and newer versions provide this functionality in libc. + +The Debian architectures alpha, hppa, ia64, m68k, mips, mipsel do not +have support for stack smashing protection. + +More documentation can be found at the project's website: +http://researchweb.watson.ibm.com/trl/projects/security/ssp/ --- gcc-4.5-4.5.2.orig/debian/gfortran-BV-spu.overrides +++ gcc-4.5-4.5.2/debian/gfortran-BV-spu.overrides @@ -0,0 +1,2 @@ +gfortran-@BV@-spu: non-standard-dir-in-usr usr/spu/ +gfortran-@BV@-spu: file-in-unusual-dir --- gcc-4.5-4.5.2.orig/debian/lib32gccLC.postinst +++ gcc-4.5-4.5.2/debian/lib32gccLC.postinst @@ -0,0 +1,12 @@ +#! /bin/sh -e + +case "$1" in + configure) + docdir=/usr/share/doc/lib32gcc@LC@ + if [ -d $docdir ] && [ ! -h $docdir ]; then + rm -rf $docdir + ln -s gcc-@BV@-base $docdir + fi +esac + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/gcc-snapshot.prerm +++ gcc-4.5-4.5.2/debian/gcc-snapshot.prerm @@ -0,0 +1,5 @@ +#! /bin/sh -e + +rm -f /usr/lib/gcc-snapshot/share/python/*.py[co] + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.i386 +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.i386 @@ -0,0 +1,3 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.10" --- gcc-4.5-4.5.2.orig/debian/libobjc2.symbols +++ gcc-4.5-4.5.2/debian/libobjc2.symbols @@ -0,0 +1,3 @@ +libobjc.so.2 libobjc2 #MINVER# +#include "libobjc2.symbols.common" + __gnu_objc_personality_v0@Base 4.2.1 --- gcc-4.5-4.5.2.orig/debian/gcj-BV-jdk.prerm +++ gcc-4.5-4.5.2/debian/gcj-BV-jdk.prerm @@ -0,0 +1,15 @@ +#! /bin/sh -e + +if [ "$1" = "remove" ] || [ "$1" = "deconfigure" ]; then + update-alternatives --quiet --remove javac /usr/bin/gcj-wrapper-@BV@ + update-alternatives --quiet --remove jar /usr/bin/gjar-@BV@ + update-alternatives --quiet --remove jarsigner /usr/bin/gjarsigner-@BV@ + update-alternatives --quiet --remove javah /usr/bin/gjavah-@BV@ + update-alternatives --quiet --remove javadoc /usr/bin/gjdoc-@BV@ + update-alternatives --quiet --remove native2ascii /usr/bin/gnative2ascii-@BV@ + update-alternatives --quiet --remove rmic /usr/bin/grmic-@BV@ + update-alternatives --quiet --remove serialver /usr/bin/gserialver-@BV@ + update-alternatives --quiet --remove tnameserv /usr/bin/gtnameserv-@BV@ +fi + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/libgccLC.postinst +++ gcc-4.5-4.5.2/debian/libgccLC.postinst @@ -0,0 +1,12 @@ +#! /bin/sh -e + +case "$1" in + configure) + docdir=/usr/share/doc/libgcc@LC@ + if [ -d $docdir ] && [ ! -h $docdir ]; then + rm -rf $docdir + ln -s gcc-@BV@-base $docdir + fi +esac + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/README.snapshot +++ gcc-4.5-4.5.2/debian/README.snapshot @@ -0,0 +1,36 @@ +Debian gcc-snapshot package +=========================== + +This package contains a recent development SNAPSHOT of all files +contained in the GNU Compiler Collection (GCC). + +DO NOT USE THIS SNAPSHOT FOR BUILDING DEBIAN PACKAGES! + +This package will NEVER hit the testing distribution. It's used for +tracking gcc bugs submitted to the Debian BTS in recent development +versions of gcc. + +To use this snapshot, you should set the following environment variables: + + LD_LIBRARY_PATH=/usr/lib/gcc-snapshot/lib:$LD_LIBRARY_PATH + PATH=/usr/lib/gcc-snapshot/bin:$PATH + +You might also like to use a shell script to wrap up this +funcationality, e.g. + +place in /usr/local/bin/gcc-snapshot and chmod +x it + +----------- snip ---------- +#! /bin/sh +LD_LIBRARY_PATH=/usr/lib/gcc-snapshot/lib:$LD_LIBRARY_PATH +PATH=/usr/lib/gcc-snapshot/bin:$PATH +gcc "$@" +----------- snip ---------- + +Make the same for g++, g77, gij, gcj, cpp, ... + +Don't forget the quotes around the $@ or gcc will not parse it's +command line correctly! + +Unset these variables before building Debian packages destined for an +upload to ftp-master.debian.org. --- gcc-4.5-4.5.2.orig/debian/gcj-wrapper-BV +++ gcc-4.5-4.5.2/debian/gcj-wrapper-BV @@ -0,0 +1,91 @@ +#!/usr/bin/perl -w +# +# Starts the GNU Java compiler. +# +# Command-line arguments should be in the style of Sun's Java compiler; +# these will be converted to gcj arguments before being passed to the +# gcj itself. +# +# Copyright (C) 2002-2003 by Ben Burton +# Based on the original gcj-wrapper-3.2 shell script. + +use strict; + +# The real Java compiler: +my $javaCompiler = '/usr/bin/gcj-@BV@'; + +# The command-line arguments to pass to the real Java compiler: +my @commandLine; + +# The warning flags to pass to the GNU Java compiler: +my $warnings = '-Wall'; + +# Build the command-line from the arguments given. +my $parsingOptions = 1; +my $copyNextArg = 0; +my $ignoreNextArg = 0; +my $appendNextArg = ''; +foreach my $arg (@ARGV) { + # See if we already know what to do with this argument. + if ($ignoreNextArg) { + # Throw it away. + $ignoreNextArg = 0; + next; + } elsif ($copyNextArg or not $parsingOptions) { + # Copy it directly. + push @commandLine, $arg; + $copyNextArg = 0; + next; + } elsif ($appendNextArg) { + # Append it to $appendNextArg and then copy directly. + push @commandLine, ($appendNextArg . $arg); + $appendNextArg = ''; + next; + } + + # Try to interpret Sun-style options. + if ($arg eq '-version') { + push @commandLine, '--version'; + } elsif ($arg eq '-h' or $arg eq '-help') { + push @commandLine, '--help'; + } elsif ($arg eq '-classpath' or $arg eq '--classpath' or $arg eq '--cp') { + $appendNextArg = '--classpath='; + } elsif ($arg eq '-encoding' or $arg eq '-bootclasspath' or + $arg eq '-extdirs') { + $appendNextArg = '-' . $arg . '='; + } elsif ($arg eq '-d') { + push @commandLine, '-d'; + $copyNextArg = 1; + } elsif ($arg eq '-nowarn') { + $warnings = ''; + } elsif ($arg =~ /^-g/) { + # Some kind of debugging option - just switch debugging on. + push @commandLine, '-g' if ($arg ne '-g:none'); + } elsif ($arg eq '-O') { + push @commandLine, '-O2'; + } elsif ($arg eq '-Xss') { + push @commandLine, $arg; + } elsif ($arg =~ /^-X/) { + # An extended Sun option (which we don't support). + push @commandLine, '--help' if ($arg eq '-X'); + } elsif ($arg eq '-source' or $arg eq '-sourcepath' or $arg eq '-target') { + # An unsupported option with a following argument. + $ignoreNextArg = 1; + } elsif ($arg =~ /^-/) { + # An unsupported standalone option. + } else { + # Some non-option argument has been given. + # Stop parsing options at this point. + push @commandLine, $arg; + $parsingOptions = 0; + } +} + +# Was there a partial argument that was never completed? +push @commandLine, $appendNextArg if ($appendNextArg); + +# Call the real Java compiler. +my @fullCommandLine = ( $javaCompiler, '-C' ); +push @fullCommandLine, $warnings if ($warnings); +push @fullCommandLine, @commandLine; +exec @fullCommandLine or exit(1); --- gcc-4.5-4.5.2.orig/debian/lib64gcc1.symbols.i386 +++ gcc-4.5-4.5.2/debian/lib64gcc1.symbols.i386 @@ -0,0 +1,144 @@ +libgcc_s.so.1 lib64gcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4.4@GCC_3.4.4 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __absvti2@GCC_3.4.4 1:4.1.1 + __addtf3@GCC_4.3.0 1:4.3 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __addvti3@GCC_3.4.4 1:4.1.1 + __ashlti3@GCC_3.0 1:4.1.1 + __ashrti3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzti2@GCC_3.4 1:4.1.1 + __cmpti2@GCC_3.0 1:4.1.1 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzti2@GCC_3.4 1:4.1.1 + __deregister_frame@GCC_3.0 1:4.1.1 + __deregister_frame_info@GCC_3.0 1:4.1.1 + __deregister_frame_info_bases@GCC_3.0 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + __divtc3@GCC_4.0.0 1:4.3 + __divtc3@GCC_4.3.0 1:4.4.0 + __divtf3@GCC_4.3.0 1:4.3 + __divti3@GCC_3.0 1:4.1.1 + __divxc3@GCC_4.0.0 1:4.1.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 1:4.1.1 + __eqtf2@GCC_4.3.0 1:4.3 + __extenddftf2@GCC_4.3.0 1:4.3 + __extendsftf2@GCC_4.3.0 1:4.3 + __extendxftf2@GCC_4.3.0 1:4.3 + __ffsdi2@GCC_3.0 1:4.1.1 + __ffsti2@GCC_3.0 1:4.1.1 + __fixdfti@GCC_3.0 1:4.1.1 + __fixsfti@GCC_3.0 1:4.1.1 + __fixtfdi@GCC_4.3.0 1:4.3 + __fixtfsi@GCC_4.3.0 1:4.3 + __fixtfti@GCC_4.3.0 1:4.3 + __fixunsdfdi@GCC_3.0 1:4.1.1 + __fixunsdfti@GCC_3.0 1:4.1.1 + __fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfti@GCC_3.0 1:4.1.1 + __fixunstfdi@GCC_4.3.0 1:4.3 + __fixunstfsi@GCC_4.3.0 1:4.3 + __fixunstfti@GCC_4.3.0 1:4.3 + __fixunsxfdi@GCC_3.0 1:4.1.1 + __fixunsxfti@GCC_3.0 1:4.1.1 + __fixxfti@GCC_3.0 1:4.1.1 + __floatditf@GCC_4.3.0 1:4.3 + __floatsitf@GCC_4.3.0 1:4.3 + __floattidf@GCC_3.0 1:4.1.1 + __floattisf@GCC_3.0 1:4.1.1 + __floattitf@GCC_4.3.0 1:4.3 + __floattixf@GCC_3.0 1:4.1.1 + __floatunditf@GCC_4.3.0 1:4.3 + __floatunsitf@GCC_4.3.0 1:4.3 + __floatuntidf@GCC_4.2.0 1:4.2.1 + __floatuntisf@GCC_4.2.0 1:4.2.1 + __floatuntitf@GCC_4.3.0 1:4.3 + __floatuntixf@GCC_4.2.0 1:4.2.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __getf2@GCC_4.3.0 1:4.3 + __gttf2@GCC_3.0 1:4.3 + __gttf2@GCC_4.3.0 1:4.4.0 + __letf2@GCC_4.3.0 1:4.3 + __lshrti3@GCC_3.0 1:4.1.1 + __lttf2@GCC_3.0 1:4.3 + __lttf2@GCC_4.3.0 1:4.4.0 + __modti3@GCC_3.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_4.0.0 1:4.3 + __multc3@GCC_4.3.0 1:4.4.0 + __multf3@GCC_4.3.0 1:4.3 + __multi3@GCC_3.0 1:4.1.1 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __mulvti3@GCC_3.4.4 1:4.1.1 + __mulxc3@GCC_4.0.0 1:4.1.1 + __negtf2@GCC_4.3.0 1:4.3 + __negti2@GCC_3.0 1:4.1.1 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __negvti2@GCC_3.4.4 1:4.1.1 + __netf2@GCC_3.0 1:4.3 + __netf2@GCC_4.3.0 1:4.4.0 + __paritydi2@GCC_3.4 1:4.1.1 + __parityti2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountti2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_4.0.0 1:4.3 + __powitf2@GCC_4.3.0 1:4.4.0 + __powixf2@GCC_4.0.0 1:4.1.1 + __register_frame@GCC_3.0 1:4.1.1 + __register_frame_info@GCC_3.0 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GCC_3.0 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GCC_3.0 1:4.1.1 + __subtf3@GCC_4.3.0 1:4.3 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __subvti3@GCC_3.4.4 1:4.1.1 + __trunctfdf2@GCC_4.3.0 1:4.3 + __trunctfsf2@GCC_4.3.0 1:4.3 + __trunctfxf2@GCC_4.3.0 1:4.3 + __ucmpti2@GCC_3.0 1:4.1.1 + __udivmodti4@GCC_3.0 1:4.1.1 + __udivti3@GCC_3.0 1:4.1.1 + __umodti3@GCC_3.0 1:4.1.1 + __unordtf2@GCC_4.3.0 1:4.3 --- gcc-4.5-4.5.2.orig/debian/copyright.in +++ gcc-4.5-4.5.2/debian/copyright.in @@ -0,0 +1,338 @@ +This is the Debian GNU/Linux prepackaged version of the GNU compiler +collection, containing Ada, C, C++, Fortran 95, Java, Objective-C, +Objective-C++, and Treelang compilers, documentation, and support +libraries. In addition, Debian provides the gdc compiler, either in +the same source package, or built from a separate same source package. +Packaging is done by the Debian GCC Maintainers +, with sources obtained from: + + ftp://gcc.gnu.org/pub/gcc/releases/ (for full releases) + svn://gcc.gnu.org/svn/gcc/ (for prereleases) + http://bitbucket.org/goshawk/gdc (for D) + +The current gcc-@BV@ source package is taken from the SVN @SVN_BRANCH@. + +Changes: See changelog.Debian.gz + +Debian splits the GNU Compiler Collection into packages for each language, +library, and documentation as follows: + +Language Compiler package Library package Documentation +--------------------------------------------------------------------------- +Ada gnat-@BV@ libgnat-@BV@ gnat-@BV@-doc +C gcc-@BV@ gcc-@BV@-doc +C++ g++-@BV@ libstdc++6 libstdc++6-@BV@-doc +D gdc-@BV@ +Fortran 95 gfortran-@BV@ libgfortran3 gfortran-@BV@-doc +Java gcj-@BV@ libgcj10 libgcj-doc +Objective C gobjc-@BV@ libobjc2 +Objective C++ gobjc++-@BV@ + +For some language run-time libraries, Debian provides source files, +development files, debugging symbols and libraries containing position- +independent code in separate packages: + +Language Sources Development Debugging Position-Independent +------------------------------------------------------------------------------ +C++ libstdc++6-@BV@-dbg libstdc++6-@BV@-pic +D libphobos-@BV@-dev +Java libgcj10-src libgcj10-dev libgcj10-dbg + +Additional packages include: + +All languages: +libgcc1, libgcc2, libgcc4 GCC intrinsics (platform-dependent) +gcc-@BV@-base Base files common to all compilers +gcc-@BV@-soft-float Software floating point (ARM only) +gcc-@BV@-source The sources with patches + +Ada: +libgnatvsn-dev, libgnatvsn@BV@ GNAT version library +libgnatprj-dev, libgnatprj@BV@ GNAT Project Manager library + +C: +cpp-@BV@, cpp-@BV@-doc GNU C Preprocessor +libmudflap0-dev, libmudflap0 Library for instrumenting pointers +libssp0-dev, libssp0 GCC stack smashing protection library +fixincludes Fix non-ANSI header files +protoize Create/remove ANSI prototypes from C code + +Java: +gij The Java bytecode interpreter and VM +libgcj-common Common files for the Java run-time +libgcj10-awt The Abstract Windowing Toolkit +libgcj10-jar Java ARchive for the Java run-time + +C, C++ and Fortran 95: +libgomp1-dev, libgomp1 GCC OpenMP (GOMP) support library + +Biarch support: On some 64-bit platforms which can also run 32-bit code, +Debian provides additional packages containing 32-bit versions of some +libraries. These packages have names beginning with 'lib32' instead of +'lib', for example lib32stdc++6. Similarly, on some 32-bit platforms which +can also run 64-bit code, Debian provides additional packages with names +beginning with 'lib64' instead of 'lib'. These packages contain 64-bit +versions of the libraries. (At this time, not all platforms and not all +libraries support biarch.) The license terms for these lib32 or lib64 +packages are identical to the ones for the lib packages. + + +COPYRIGHT STATEMENTS AND LICENSING TERMS + + +GCC is Copyright (C) 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, +1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, +2008 Free Software Foundation, Inc. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Files that have exception clauses are licensed under the terms of the +GNU General Public License; either version 3, or (at your option) any +later version. + +On Debian GNU/Linux systems, the complete text of the GNU General +Public License is in `/usr/share/common-licenses/GPL', version 3 of this +license in `/usr/share/common-licenses/GPL-3'. + +The following runtime libraries are licensed under the terms of the +GNU General Public License (v3 or later) with version 3.1 of the GCC +Runtime Library Exception (included in this file): + + - libgcc (libgcc/, gcc/libgcc2.[ch], gcc/unwind*, gcc/gthr*, + gcc/coretypes.h, gcc/crtstuff.c, gcc/defaults.h, gcc/dwarf2.h, + gcc/emults.c, gcc/gbl-ctors.h, gcc/gcov-io.h, gcc/libgcov.c, + gcc/tsystem.h, gcc/typeclass.h). + - libdecnumber + - libgomp + - libssp + - libstdc++-v3 + - libobjc + - libmudflap + - libgfortran + - The libgnat-@BV@ Ada support library and libgnatvsn library. + - Various config files in gcc/config/ used in runtime libraries. + +In contrast, libgnatprj is licensed under the terms of the pure GNU +General Public License. + +The libgcj library is licensed under the terms of the GNU General +Public License, with a special exception: + + Linking this library statically or dynamically with other modules + is making a combined work based on this library. Thus, the terms + and conditions of the GNU General Public License cover the whole + combination. + + As a special exception, the copyright holders of this library give + you permission to link this library with independent modules to + produce an executable, regardless of the license terms of these + independent modules, and to copy and distribute the resulting + executable under terms of your choice, provided that you also + meet, for each linked independent module, the terms and conditions + of the license of that module. An independent module is a module + which is not derived from or based on this library. If you modify + this library, you may extend this exception to your version of the + library, but you are not obligated to do so. If you do not wish + to do so, delete this exception statement from your version. + +The libffi library is licensed under the following terms: + + libffi - Copyright (c) 1996-2003 Red Hat, Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + ``Software''), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS + OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL CYGNUS SOLUTIONS BE LIABLE FOR ANY CLAIM, DAMAGES OR + OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + OTHER DEALINGS IN THE SOFTWARE. + + +The documentation is licensed under the GNU Free Documentation License (v1.2). +On Debian GNU/Linux systems, the complete text of this license is in +`/usr/share/common-licenses/GFDL-1.2'. + + +GCC RUNTIME LIBRARY EXCEPTION + +Version 3.1, 31 March 2009 + +Copyright (C) 2009 Free Software Foundation, Inc. + +Everyone is permitted to copy and distribute verbatim copies of this +license document, but changing it is not allowed. + +This GCC Runtime Library Exception ("Exception") is an additional +permission under section 7 of the GNU General Public License, version +3 ("GPLv3"). It applies to a given file (the "Runtime Library") that +bears a notice placed by the copyright holder of the file stating that +the file is governed by GPLv3 along with this Exception. + +When you use GCC to compile a program, GCC may combine portions of +certain GCC header files and runtime libraries with the compiled +program. The purpose of this Exception is to allow compilation of +non-GPL (including proprietary) programs to use, in this way, the +header files and runtime libraries covered by this Exception. + +0. Definitions. + +A file is an "Independent Module" if it either requires the Runtime +Library for execution after a Compilation Process, or makes use of an +interface provided by the Runtime Library, but is not otherwise based +on the Runtime Library. + +"GCC" means a version of the GNU Compiler Collection, with or without +modifications, governed by version 3 (or a specified later version) of +the GNU General Public License (GPL) with the option of using any +subsequent versions published by the FSF. + +"GPL-compatible Software" is software whose conditions of propagation, +modification and use would permit combination with GCC in accord with +the license of GCC. + +"Target Code" refers to output from any compiler for a real or virtual +target processor architecture, in executable form or suitable for +input to an assembler, loader, linker and/or execution +phase. Notwithstanding that, Target Code does not include data in any +format that is used as a compiler intermediate representation, or used +for producing a compiler intermediate representation. + +The "Compilation Process" transforms code entirely represented in +non-intermediate languages designed for human-written code, and/or in +Java Virtual Machine byte code, into Target Code. Thus, for example, +use of source code generators and preprocessors need not be considered +part of the Compilation Process, since the Compilation Process can be +understood as starting with the output of the generators or +preprocessors. + +A Compilation Process is "Eligible" if it is done using GCC, alone or +with other GPL-compatible software, or if it is done without using any +work based on GCC. For example, using non-GPL-compatible Software to +optimize any GCC intermediate representations would not qualify as an +Eligible Compilation Process. + +1. Grant of Additional Permission. + +You have permission to propagate a work of Target Code formed by +combining the Runtime Library with Independent Modules, even if such +propagation would otherwise violate the terms of GPLv3, provided that +all Target Code was generated by Eligible Compilation Processes. You +may then convey such a combination under terms of your choice, +consistent with the licensing of the Independent Modules. + +2. No Weakening of GCC Copyleft. + +The availability of this Exception does not imply any general +presumption that third-party software is unaffected by the copyleft +requirements of the license of GCC. + + +D: +gdc-@BV@ GNU D Compiler +libphobos-@BV@-dev D standard runtime library + +The D source package is made up of the following components. + +The D front-end for GCC: + - d/* + +Copyright (C) 2004-2007 David Friedman +Modified by Vincenzo Ampolo, Michael Parrot, Iain Buclaw, (C) 2009, 2010 + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +On Debian GNU/Linux systems, the complete text of the GNU General +Public License is in `/usr/share/common-licenses/GPL', version 2 of this +license in `/usr/share/common-licenses/GPL-2'. + + +The DMD Compiler implementation of the D programming language: + - d/dmd/* + +Copyright (c) 1999-2010 by Digital Mars +All Rights Reserved +written by Walter Bright +http://www.digitalmars.com +License for redistribution is by either the Artistic License or +the GNU General Public License (v1). + +On Debian GNU/Linux systems, the complete text of the GNU General +Public License is in `/usr/share/common-licenses/GPL', the Artistic +license in `/usr/share/common-licenses/Artistic'. + + +The Zlib data compression library: + - d/phobos/etc/c/zlib/* + + (C) 1995-2004 Jean-loup Gailly and Mark Adler + + This software is provided 'as-is', without any express or implied + warranty. In no event will the authors be held liable for any damages + arising from the use of this software. + + Permission is granted to anyone to use this software for any purpose, + including commercial applications, and to alter it and redistribute it + freely, subject to the following restrictions: + + 1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + 2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + 3. This notice may not be removed or altered from any source distribution. + + +The Phobos standard runtime library: + - d/phobos/* + +Unless otherwise marked within the file, each file in the source +is under the following licenses: + +Copyright (C) 2004-2005 by Digital Mars, www.digitalmars.com +Written by Walter Bright + +This software is provided 'as-is', without any express or implied +warranty. In no event will the authors be held liable for any damages +arising from the use of this software. + +Permission is granted to anyone to use this software for any purpose, +including commercial applications, and to alter it and redistribute it +freely, in both source and binary form, subject to the following +restrictions: + + o The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + o Altered source versions must be plainly marked as such, and must not + be misrepresented as being the original software. + o This notice may not be removed or altered from any source + distribution. + +By plainly marking modifications, something along the lines of adding to each +file that has been changed a "Modified by Foo Bar" line +underneath the "Written by" line would be adequate. + --- gcc-4.5-4.5.2.orig/debian/libgcjGCJ-awt.overrides +++ gcc-4.5-4.5.2/debian/libgcjGCJ-awt.overrides @@ -0,0 +1,2 @@ +# pick up the exact version, in case another gcj version is installed +libgcj@GCJ@-awt binary: binary-or-shlib-defines-rpath --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.mips +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.mips @@ -0,0 +1,1219 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3.4@GCC_3.3.4 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GCC_4.4.0@GCC_4.4.0 1:4.4.0 + GLIBC_2.0@GLIBC_2.0 1:4.1.1 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + 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__satfractdqhq2@GCC_4.3.0 1:4.3 + __satfractdqqq2@GCC_4.3.0 1:4.3 + __satfractdqsa@GCC_4.3.0 1:4.3 + __satfractdqsq2@GCC_4.3.0 1:4.3 + __satfractdquda@GCC_4.3.0 1:4.3 + __satfractdqudq@GCC_4.3.0 1:4.3 + __satfractdquha@GCC_4.3.0 1:4.3 + __satfractdquhq@GCC_4.3.0 1:4.3 + __satfractdquqq@GCC_4.3.0 1:4.3 + __satfractdqusa@GCC_4.3.0 1:4.3 + __satfractdqusq@GCC_4.3.0 1:4.3 + __satfracthada2@GCC_4.3.0 1:4.3 + __satfracthadq@GCC_4.3.0 1:4.3 + __satfracthahq@GCC_4.3.0 1:4.3 + __satfracthaqq@GCC_4.3.0 1:4.3 + __satfracthasa2@GCC_4.3.0 1:4.3 + __satfracthasq@GCC_4.3.0 1:4.3 + __satfracthauda@GCC_4.3.0 1:4.3 + __satfracthaudq@GCC_4.3.0 1:4.3 + __satfracthauha@GCC_4.3.0 1:4.3 + __satfracthauhq@GCC_4.3.0 1:4.3 + __satfracthauqq@GCC_4.3.0 1:4.3 + __satfracthausa@GCC_4.3.0 1:4.3 + __satfracthausq@GCC_4.3.0 1:4.3 + __satfracthida@GCC_4.3.0 1:4.3 + __satfracthidq@GCC_4.3.0 1:4.3 + __satfracthiha@GCC_4.3.0 1:4.3 + __satfracthihq@GCC_4.3.0 1:4.3 + __satfracthiqq@GCC_4.3.0 1:4.3 + __satfracthisa@GCC_4.3.0 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__satfractqiudq@GCC_4.3.0 1:4.3 + __satfractqiuha@GCC_4.3.0 1:4.3 + __satfractqiuhq@GCC_4.3.0 1:4.3 + __satfractqiuqq@GCC_4.3.0 1:4.3 + __satfractqiusa@GCC_4.3.0 1:4.3 + __satfractqiusq@GCC_4.3.0 1:4.3 + __satfractqqda@GCC_4.3.0 1:4.3 + __satfractqqdq2@GCC_4.3.0 1:4.3 + __satfractqqha@GCC_4.3.0 1:4.3 + __satfractqqhq2@GCC_4.3.0 1:4.3 + __satfractqqsa@GCC_4.3.0 1:4.3 + __satfractqqsq2@GCC_4.3.0 1:4.3 + __satfractqquda@GCC_4.3.0 1:4.3 + __satfractqqudq@GCC_4.3.0 1:4.3 + __satfractqquha@GCC_4.3.0 1:4.3 + __satfractqquhq@GCC_4.3.0 1:4.3 + __satfractqquqq@GCC_4.3.0 1:4.3 + __satfractqqusa@GCC_4.3.0 1:4.3 + __satfractqqusq@GCC_4.3.0 1:4.3 + __satfractsada2@GCC_4.3.0 1:4.3 + __satfractsadq@GCC_4.3.0 1:4.3 + __satfractsaha2@GCC_4.3.0 1:4.3 + __satfractsahq@GCC_4.3.0 1:4.3 + __satfractsaqq@GCC_4.3.0 1:4.3 + __satfractsasq@GCC_4.3.0 1:4.3 + __satfractsauda@GCC_4.3.0 1:4.3 + __satfractsaudq@GCC_4.3.0 1:4.3 + __satfractsauha@GCC_4.3.0 1:4.3 + __satfractsauhq@GCC_4.3.0 1:4.3 + __satfractsauqq@GCC_4.3.0 1:4.3 + __satfractsausa@GCC_4.3.0 1:4.3 + __satfractsausq@GCC_4.3.0 1:4.3 + __satfractsfda@GCC_4.3.0 1:4.3 + __satfractsfdq@GCC_4.3.0 1:4.3 + __satfractsfha@GCC_4.3.0 1:4.3 + __satfractsfhq@GCC_4.3.0 1:4.3 + __satfractsfqq@GCC_4.3.0 1:4.3 + __satfractsfsa@GCC_4.3.0 1:4.3 + __satfractsfsq@GCC_4.3.0 1:4.3 + __satfractsfuda@GCC_4.3.0 1:4.3 + __satfractsfudq@GCC_4.3.0 1:4.3 + __satfractsfuha@GCC_4.3.0 1:4.3 + __satfractsfuhq@GCC_4.3.0 1:4.3 + __satfractsfuqq@GCC_4.3.0 1:4.3 + __satfractsfusa@GCC_4.3.0 1:4.3 + __satfractsfusq@GCC_4.3.0 1:4.3 + __satfractsida@GCC_4.3.0 1:4.3 + __satfractsidq@GCC_4.3.0 1:4.3 + __satfractsiha@GCC_4.3.0 1:4.3 + __satfractsihq@GCC_4.3.0 1:4.3 + __satfractsiqq@GCC_4.3.0 1:4.3 + __satfractsisa@GCC_4.3.0 1:4.3 + __satfractsisq@GCC_4.3.0 1:4.3 + __satfractsiuda@GCC_4.3.0 1:4.3 + __satfractsiudq@GCC_4.3.0 1:4.3 + __satfractsiuha@GCC_4.3.0 1:4.3 + __satfractsiuhq@GCC_4.3.0 1:4.3 + __satfractsiuqq@GCC_4.3.0 1:4.3 + __satfractsiusa@GCC_4.3.0 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__satfractudqha@GCC_4.3.0 1:4.3 + __satfractudqhq@GCC_4.3.0 1:4.3 + __satfractudqqq@GCC_4.3.0 1:4.3 + __satfractudqsa@GCC_4.3.0 1:4.3 + __satfractudqsq@GCC_4.3.0 1:4.3 + __satfractudquda@GCC_4.3.0 1:4.3 + __satfractudquha@GCC_4.3.0 1:4.3 + __satfractudquhq2@GCC_4.3.0 1:4.3 + __satfractudquqq2@GCC_4.3.0 1:4.3 + __satfractudqusa@GCC_4.3.0 1:4.3 + __satfractudqusq2@GCC_4.3.0 1:4.3 + __satfractuhada@GCC_4.3.0 1:4.3 + __satfractuhadq@GCC_4.3.0 1:4.3 + __satfractuhaha@GCC_4.3.0 1:4.3 + __satfractuhahq@GCC_4.3.0 1:4.3 + __satfractuhaqq@GCC_4.3.0 1:4.3 + __satfractuhasa@GCC_4.3.0 1:4.3 + __satfractuhasq@GCC_4.3.0 1:4.3 + __satfractuhauda2@GCC_4.3.0 1:4.3 + __satfractuhaudq@GCC_4.3.0 1:4.3 + __satfractuhauhq@GCC_4.3.0 1:4.3 + __satfractuhauqq@GCC_4.3.0 1:4.3 + __satfractuhausa2@GCC_4.3.0 1:4.3 + __satfractuhausq@GCC_4.3.0 1:4.3 + __satfractuhqda@GCC_4.3.0 1:4.3 + __satfractuhqdq@GCC_4.3.0 1:4.3 + __satfractuhqha@GCC_4.3.0 1:4.3 + __satfractuhqhq@GCC_4.3.0 1:4.3 + __satfractuhqqq@GCC_4.3.0 1:4.3 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1:4.3 + __usadduha3@GCC_4.3.0 1:4.3 + __usadduhq3@GCC_4.3.0 1:4.3 + __usadduqq3@GCC_4.3.0 1:4.3 + __usaddusa3@GCC_4.3.0 1:4.3 + __usaddusq3@GCC_4.3.0 1:4.3 + __usashluda3@GCC_4.3.0 1:4.3 + __usashludq3@GCC_4.3.0 1:4.3 + __usashluha3@GCC_4.3.0 1:4.3 + __usashluhq3@GCC_4.3.0 1:4.3 + __usashluqq3@GCC_4.3.0 1:4.3 + __usashlusa3@GCC_4.3.0 1:4.3 + __usashlusq3@GCC_4.3.0 1:4.3 + __usdivuda3@GCC_4.3.0 1:4.3 + __usdivudq3@GCC_4.3.0 1:4.3 + __usdivuha3@GCC_4.3.0 1:4.3 + __usdivuhq3@GCC_4.3.0 1:4.3 + __usdivuqq3@GCC_4.3.0 1:4.3 + __usdivusa3@GCC_4.3.0 1:4.3 + __usdivusq3@GCC_4.3.0 1:4.3 + __usmuluda3@GCC_4.3.0 1:4.3 + __usmuludq3@GCC_4.3.0 1:4.3 + __usmuluha3@GCC_4.3.0 1:4.3 + __usmuluhq3@GCC_4.3.0 1:4.3 + __usmuluqq3@GCC_4.3.0 1:4.3 + __usmulusa3@GCC_4.3.0 1:4.3 + __usmulusq3@GCC_4.3.0 1:4.3 + __usneguda2@GCC_4.3.0 1:4.3 + __usnegudq2@GCC_4.3.0 1:4.3 + __usneguha2@GCC_4.3.0 1:4.3 + __usneguhq2@GCC_4.3.0 1:4.3 + __usneguqq2@GCC_4.3.0 1:4.3 + __usnegusa2@GCC_4.3.0 1:4.3 + __usnegusq2@GCC_4.3.0 1:4.3 + __ussubuda3@GCC_4.3.0 1:4.3 + __ussubudq3@GCC_4.3.0 1:4.3 + __ussubuha3@GCC_4.3.0 1:4.3 + __ussubuhq3@GCC_4.3.0 1:4.3 + __ussubuqq3@GCC_4.3.0 1:4.3 + __ussubusa3@GCC_4.3.0 1:4.3 + __ussubusq3@GCC_4.3.0 1:4.3 --- gcc-4.5-4.5.2.orig/debian/cpp-BV-doc.doc-base.cppint +++ gcc-4.5-4.5.2/debian/cpp-BV-doc.doc-base.cppint @@ -0,0 +1,17 @@ +Document: cppinternals-@BV@ +Title: The GNU C preprocessor (internals) +Author: Various +Abstract: This brief manual documents the internals of cpplib, and + explains some of the tricky issues. It is intended that, along with + the comments in the source code, a reasonably competent C programmer + should be able to figure out what the code is doing, and why things + have been implemented the way they have. +Section: Programming + +Format: html +Index: /usr/share/doc/gcc-@BV@-base/cppinternals.html +Files: /usr/share/doc/gcc-@BV@-base/cppinternals.html + +Format: info +Index: /usr/share/info/cppinternals-@BV@.info.gz +Files: /usr/share/info/cppinternals-@BV@* --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.sh4 +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.sh4 @@ -0,0 +1,127 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3.4@GCC_3.3.4 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GCC_4.4.0@GCC_4.4.0 1:4.4.0 + GLIBC_2.2@GLIBC_2.2 1:4.1.1 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + 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_ZTVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 --- gcc-4.5-4.5.2.orig/debian/lib64gccLC.postinst +++ gcc-4.5-4.5.2/debian/lib64gccLC.postinst @@ -0,0 +1,12 @@ +#! /bin/sh -e + +case "$1" in + configure) + docdir=/usr/share/doc/lib64gcc@LC@ + if [ -d $docdir ] && [ ! -h $docdir ]; then + rm -rf $docdir + ln -s gcc-@BV@-base $docdir + fi +esac + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/lib64stdc++6.symbols.powerpc +++ gcc-4.5-4.5.2/debian/lib64stdc++6.symbols.powerpc @@ -0,0 +1,9 @@ +libstdc++.so.6 lib64stdc++6 #MINVER# +#include "libstdc++6.symbols.64bit" +#include "libstdc++6.symbols.excprop" + _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1 +#include "libstdc++6.symbols.glibcxxmath" +#include "libstdc++6.symbols.ldbl.64bit" + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2 --- gcc-4.5-4.5.2.orig/debian/TODO +++ gcc-4.5-4.5.2/debian/TODO @@ -0,0 +1,50 @@ +(It is recommended to edit this file with emacs' todoo mode) +Last updated: 2008-05-02 + +* General + +- Clean up the sprawl of debian/rules. I'm sure there are neater + ways to do some of it; perhaps split it up into some more files? + Partly done. + +- Make debian/rules control build the control file without unpacking + the sources or applying patches. Currently, it unpacks the sources, + patches them, creates the control file, and a subsequent + dpkg-buildpackage deletes the sources, re-unpacks them, and + re-patches them. + +- Reorganise debian/rules.defs to decide which packages to build in a + more straightforward and less error-prone fashion: (1) start with + all languages; override the list of languages depending on the name + of the source package (gcc-4.3, gnat-4.3, gdc-4.3, gcj-4.3). (2) + filter the list of languages depending on the target platform; (3) + depending on the languages to build, decide on which libraries to + build. + +o [Ludovic Brenta] Ada + +- Done: Link the gnat tools with libgnat.so, instead of statically. + +- Done: Build libgnatvsn containing parts of the compiler (version + string, etc.) under GNAT-Modified GPL. Link the gnat tools with it. + +- Done: Build libgnatprj containing parts of the compiler (the project + manager) under pure GPL. Link the gnat tools with it. + +- Done: Build both the zero-cost and setjump/longjump exceptions + versions of libgnat. In particular, gnat-glade (distributed systems) + works best with SJLJ. + +- Done: Re-enable running the test suite. + +- Add support for building cross-compilers. + +- Add support for multilib (not yet supported upstream). + +* Fortran + +- gfortran man page generation + +* Java + +- build java-gcj-compat from the gcc source? --- gcc-4.5-4.5.2.orig/debian/README.gnat +++ gcc-4.5-4.5.2/debian/README.gnat @@ -0,0 +1,22 @@ +If you want to develop Ada programs and libraries on Debian, please +read the Debian Policy for Ada: + +http://www.ada-france.org/debian/debian-ada-policy.html + +The default Ada compiler is and always will be the package `gnat'. +Debian contains many programs and libraries compiled with it, which +are all ABI-compatible. + +Starting with gnat-4.2, Debian provides both zero-cost and +setjump/longjump versions of the run-time library. The zero-cost +exception handling mechanism is the default as it provides the best +performance. The setjump/longjump exception handling mechanism is new +and only provided as a static library. It is necessary to use this +exception handling mechanism in distributed (annex E) programs. If +you wish to use the new sjlj library: + +1) call gnatmake with --RTS=sjlj +2) call gnatbind with -static + +Do NOT link your programs with libgnat-4.2.so, because it uses the ZCX +mechanism. --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.armel +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.armel @@ -0,0 +1,26 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" +#include "libstdc++6.symbols.excprop" + __gxx_personality_v0@CXXABI_1.3 4.1.1 +#include "libstdc++6.symbols.glibcxxmath" + CXXABI_ARM_1.3.3@CXXABI_ARM_1.3.3 4.4.0 + _ZNKSt9type_info6beforeERKS_@GLIBCXX_3.4 4.3.0 + _ZNKSt9type_infoeqERKS_@GLIBCXX_3.4 4.3.0 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0 + __aeabi_atexit@CXXABI_ARM_1.3.3 4.4.0 + __aeabi_vec_cctor_nocookie_nodtor@CXXABI_ARM_1.3.3 4.4.0 + __aeabi_vec_ctor_cookie_nodtor@CXXABI_ARM_1.3.3 4.4.0 + __aeabi_vec_ctor_nocookie_nodtor@CXXABI_ARM_1.3.3 4.4.0 + __aeabi_vec_delete3@CXXABI_ARM_1.3.3 4.4.0 + __aeabi_vec_delete3_nodtor@CXXABI_ARM_1.3.3 4.4.0 + __aeabi_vec_delete@CXXABI_ARM_1.3.3 4.4.0 + __aeabi_vec_dtor@CXXABI_ARM_1.3.3 4.4.0 + __aeabi_vec_dtor_cookie@CXXABI_ARM_1.3.3 4.4.0 + __aeabi_vec_new_cookie@CXXABI_ARM_1.3.3 4.4.0 + __aeabi_vec_new_cookie_noctor@CXXABI_ARM_1.3.3 4.4.0 + __aeabi_vec_new_cookie_nodtor@CXXABI_ARM_1.3.3 4.4.0 + __aeabi_vec_new_nocookie@CXXABI_ARM_1.3.3 4.4.0 + __cxa_begin_cleanup@CXXABI_1.3 4.3.0 + __cxa_end_cleanup@CXXABI_1.3 4.3.0 + __cxa_type_match@CXXABI_1.3 4.3.0 --- gcc-4.5-4.5.2.orig/debian/lib64gomp1.symbols +++ gcc-4.5-4.5.2/debian/lib64gomp1.symbols @@ -0,0 +1,4 @@ +libgomp.so.1 lib64gomp1 #MINVER# +#include "libgomp1.symbols.common" + GOMP_atomic_end@GOMP_1.0 4.2.1 + GOMP_atomic_start@GOMP_1.0 4.2.1 --- gcc-4.5-4.5.2.orig/debian/porting.html +++ gcc-4.5-4.5.2/debian/porting.html @@ -0,0 +1,30 @@ + + +Porting libstdc++-v3 + + + + + + + +

Porting libstdc++-v3

+
+

+Node: Top, +Next: , +Up: (dir) +
+
+ +The documentation in this file was removed, because it is licencensed +under a non DFSG conforming licencse. + + --- gcc-4.5-4.5.2.orig/debian/relink +++ gcc-4.5-4.5.2/debian/relink @@ -0,0 +1,74 @@ +#! /bin/sh +# +# Relink GNAT utilities using the shared library +# + +set -e + +pwd=`pwd` + +# why? +chmod a-w build/gcc/ada/rts/*.ali + +rm -rf tmp +ln -s $pwd/build/gcc/ada/rts/libgnat.so.1 tmp/libgnat.so + +LD_LIBRARY_PATH=$pwd/tmp +export LD_LIBRARY_PATH + +PATH=$pwd/debian:$pwd/tmp:$PATH +export PATH + +echo "#! /bin/sh" > tmp/dgcc +echo "$pwd/build/gcc/xgcc -B$pwd/build/gcc/ "'"$@"' >> tmp/dgcc +chmod 755 tmp/dgcc + +echo "#! /bin/sh" > tmp/dgnatlink +echo "$pwd/build/gcc/gnatlink --GCC=dgcc "'"$@"' >> tmp/dgnatlink +chmod 755 tmp/dgnatlink + +GMCMD="$pwd/build/gcc/gnatmake -I- -Irts -I. -a -m --GNATBIND=$pwd/build/gcc/gnatbind --GNATLINK=dgnatlink --GCC=dgcc" + +#cd $pwd/build/gcc/ada +#make CFLAGS="-O2" CC="../xgcc -B../" STAGE_PREFIX=../ a-link.o a-gmem.o +#cd $pwd + +[ -f build/gcc/gnatmake.old ] || cp -p build/gcc/gnatmake build/gcc/gnatmake.old +[ -f build/gcc/gnatlink.old ] || cp -p build/gcc/gnatlink build/gcc/gnatlink.old + +make -C build/gcc/ada \ + CFLAGS='-gnatp -gnata -O2 ' \ + ADA_INCLUDES="-I." \ + CC="../xgcc -B../" \ + STAGE_PREFIX=../ \ + ../gnatmake ../gnatlink + +mv gnatmake bgnatmake +mv gnatlink bgnatlink +exit 0 + +cd build/gcc/ada +for i in ../gnatchop ../gnatcmd \ + ../gnatkr ../gnatlbr \ + ../gnatls ../gnatmake \ + ../gnatprep ../gnatpsys \ + ../gnatxref ../gnatfind +do + rm -f $i + $GMCMD -O2 -gnatp -o $i `basename $i`.adb -largs -L.. +done + +rm -f ../gnatmem +$GMCMD -O2 -gnatp -o ../gnatmem gnatmem.adb -largs -L.. a-gmem.o +$GMCMD -O2 -gnatp -o ../gnatlink gnatlink -largs -L.. a-link.o +rm -f ../gnatpsta + +make CFLAGS="-O2" CC="../xgcc -B../" a-gettty.o a-deftar.o +$GMCMD -O2 -gnatp -o ../gnatpsta gnatpsta -largs -L.. a-gettty.o a-deftar.o +rm -f ../gnatbl + +make CFLAGS="-O2" CC="../xgcc -B../" gnatbl.o +../xgcc -B../ -o ../gnatbl gnatbl.o -L.. -lgnat +rm -f ../bgnatmake ../bgnatlink ../debian/dgcc ../debian/dgnatlink + +chmod +w rts/*.ali --- gcc-4.5-4.5.2.orig/debian/lib64gfortran3.symbols.sparc +++ gcc-4.5-4.5.2/debian/lib64gfortran3.symbols.sparc @@ -0,0 +1,5 @@ +libgfortran.so.3 lib64gfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.16.powerpc" +#include "libgfortran3.symbols.16.powerpc64" +#include "libgfortran3.symbols.64" --- gcc-4.5-4.5.2.orig/debian/NEWS.html +++ gcc-4.5-4.5.2/debian/NEWS.html @@ -0,0 +1,903 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +GCC 4.5 Release Series — Changes, New Features, and Fixes +- GNU Project - Free Software Foundation (FSF) + + + + + + + + + +

+GCC 4.5 Release Series
Changes, New Features, and Fixes +

+ +

Caveats

+ +
    +
  • GCC now requires the MPC library in order to + build. See the prerequisites + page for version requirements.
    • + +

  • Support for a number of older systems and recently + unmaintained or untested target ports of GCC has been declared + obsolete in GCC 4.5. Unless there is activity to revive them, the + next release of GCC will have their sources permanently + removed.

    + +

    The following ports for individual systems on + particular architectures have been obsoleted:

    + +
      +
    • IRIX releases before 6.5 (mips-sgi-irix5*, + mips-sgi-irix6.[0-4])
      • +
    • Solaris 7 (*-*-solaris2.7)
      • +
    • Tru64 UNIX releases before V5.1 (alpha*-dec-osf4*, + alpha-dec-osf5.0*)
      • +
    • Details for the IRIX, Solaris 7, and Tru64 UNIX obsoletions can + be found in the announcement.
      • +
    + +
    • + +
  • Support has been removed for all the + configurations obsoleted + in GCC 4.4.
    • + +
  • Support has been removed for the protoize + and unprotoize utilities, obsoleted in GCC 4.4.
    • + +
  • Support has been removed for tuning for Itanium1 (Merced) variants. + Note that code tuned for Itanium2 should also run correctly on Itanium1.
    • + +
  • GCC now generates unwind info also for epilogues. DWARF debuginfo + generated by GCC now uses more features of DWARF3 than it used to + do and also some DWARF4 features. GDB older than 7.0 is not able to + handle either of these, so to debug GCC 4.5 generated binaries or + libraries GDB 7.0 or later is needed. You can disable use of DWARF4 + features with -gdwarf-3 -gstrict-dwarf options, or with + -gdwarf-2 -gstrict-dwarf restrict GCC to just DWARF2 + standard, but epilogue unwind info is emitted unconditionally whenever + unwind info is emitted.
    • + +
  • On x86 targets, code containing floating-point calculations may + run significantly slower when compiled with GCC 4.5 in strict C99 + conformance mode than they did with earlier GCC versions. This is due + to stricter standard conformance of the compiler and can be avoided by + using the option -fexcess-precision=fast; also see + below.
    • + +
  • The function attribute noinline no longer prevents GCC + from cloning the function. A new attribute noclone + has been introduced for this purpose. Cloning a function means + that it is duplicated and the new copy is specialized for certain + contexts (for example when a parameter is a known constant).
    • +
+ +

General Optimizer Improvements

+ +
    + +
  • The -save-temps now takes an optional argument. The + -save-temps and -save-temps=cwd switches write + the temporary files in the current working directory based on the original + source file. The -save-temps=obj switch will write files into + the directory specified with the -o option, and the + intermediate filenames are based on the output file. This will allow the + user to get the compiler intermediate files when doing parallel builds + without two builds of the same filename located in different directories + from interfering with each other.
    • + +
  • Debugging dumps are now created in the same directory as the + object file rather than in the current working directory. This + allows the user to get debugging dumps when doing parallel builds + without two builds of the same filename interfering with each other.
    • + +
  • GCC has been integrated with the MPC library. This + allows GCC to evaluate complex arithmetic at compile time more + accurately. It also allows GCC to evaluate calls to complex + built-in math functions having constant arguments and replace them + at compile time with their mathematically equivalent results. In + doing so, GCC can generate correct results regardless of the math + library implementation or floating point precision of the host + platform. This also allows GCC to generate identical results + regardless of whether one compiles in native or cross-compile + configurations to a particular target. The following built-in + functions take advantage of this new capability: + cacos, cacosh, casin, + casinh, catan, catanh, + ccos, ccosh, cexp, + clog, cpow, csin, + csinh, csqrt, ctan, and + ctanh. The float and long + double variants of these functions (e.g. csinf + and csinl) are also handled.
    • + +
  • A new link-time optimizer has been added (-flto). + When this option is used, GCC generates a bytecode representation of + each input file and writes it to special ELF sections in each + object file. When the object files are linked together, all the + function bodies are read from these ELF sections and instantiated + as if they had been part of the same translation unit. This + enables interprocedural optimizations to work across different + files (and even different languages), potentially improving the + performance of the generated code. To use the link-timer optimizer, + -flto needs to be specified at compile time and during + the final link. If the program does not require any symbols to be + exported, it is possible to combine -flto and the + experimental -fwhopr with -fwhole-program to allow the interprocedural optimizers + to use more aggressive assumptions.
    • + +
  • The automatic parallelization pass was enhanced to support + parallelization of outer loops.
    • + +
  • Automatic parallelization can be enabled as part of Graphite. + In addition to -ftree-parallelize-loops=, specify + -floop-parallelize-all to enable the Graphite-based + optimization.
    • + +
  • The infrastructure for optimizing based on + restrict qualified pointers + has been rewritten and should result in code generation improvements. + Optimizations based on restrict qualified pointers are now also available + when using -fno-strict-aliasing.
    • + +
  • There is a new optimization pass that attempts to change prototype + of functions to avoid unused parameters, pass only relevant parts of + structures and turn arguments passed by reference to arguments passed + by value when possible. It is enabled by -O2 and above + as well as -Os and can be manually invoked using the new + command-line switch -fipa-sra.
    • + +
  • GCC now optimize exception handling code. In particular cleanup + regions that are proved to not have any effect are optimized out.
    • +
+ +

New Languages and Language specific improvements

+ +

All languages

+
    +
  • The -fshow-column option is now on by default. This + means error messages now have a column associated with them.
    • +
+ +

Ada

+ +
    +
  • Compilation of programs heavily using discriminated record types + with variant parts has been sped up and generates more compact code.
    • +
  • Stack checking now works reasonably well on most plaforms. In + some specific cases, stack overflows may still fail to be detected, + but a compile-time warning will be issued for these cases.
    • +
+ +

C family

+ +
    +
  • If a header named in a #include directive is not + found, the compiler exits immediately. This avoids a cascade of + errors arising from declarations expected to be found in that + header being missing.
    • +
  • A new built-in function __builtin_unreachable() + has been added that tells the compiler that control will never + reach that point. It may be used after asm + statements that terminate by transferring control elsewhere, and + in other places that are known to be unreachable.
    • +
  • The -Wlogical-op option now warns for logical + expressions such as (c == 1 && c == 2) and (c + != 1 || c != 2), which are likely to be mistakes. This + option is disabled by default.
    • +
  • An asm goto feature has been added to + allow asm statements that jump to C labels.
    • +
  • C++0x raw strings are supported for C++ and for C + with -std=gnu99.
    • +
  • The deprecated attribute now takes an optional + string argument, for example, + __attribute__((deprecated("text string"))), that will + be printed together with the deprecation warning.
    • + +
+ +

C

+
    +
  • The -Wenum-compare option, which warns when + comparing values of different enum types, now works for C. It + formerly only worked for C++. This warning is enabled + by -Wall. It may be avoided by using a + type cast.
    • +
  • The -Wcast-qual option now warns about casts + which are unsafe in that they permit const-correctness to be + violated without further warnings. Specifically, it warns about + cases where a qualifier is added when all the lower types are + not const. For example, it warns about a cast + from char ** to const char **.
    • +
  • The -Wc++-compat option is significantly + improved. It issues new warnings for: +
      +
    • Using C++ reserved operator names as identifiers.
      • +
    • Conversions to enum types without explicit casts.
      • +
    • Using va_arg with an enum type.
      • +
    • Using different enum types in the two branches + of ?:.
      • +
    • Using ++ or -- on a variable of + enum type.
      • +
    • Using the same name as both a struct, union or enum tag + and a typedef, unless the typedef refers to the tagged type + itself.
      • +
    • Using a struct, union, or enum which is defined within + another struct or union.
      • +
    • A struct field defined using a typedef if there is a field + in the struct, or an enclosing struct, whose name is the + typedef name.
      • +
    • Duplicate definitions at file scope.
      • +
    • Uninitialized const variables.
      • +
    • A global variable with an anonymous struct, union, or enum + type.
      • +
    • Using a string constant to initialize a char array whose + size is the length of the string.
      • +
    • +
  • The new -Wjump-misses-init option warns about + cases where a goto or switch skips the + initialization of a variable. This sort of branch is an error in + C++ but not in C. This warning is enabled + by -Wc++-compat.
    • +
  • GCC now ensures that a + C99-conforming <stdint.h> is present on most + targets, and uses information about the types in this header to + implement the Fortran bindings to those types. GCC does not + ensure the presence of such a header, and does not implement the + Fortran bindings, on the following targets: NetBSD, VxWorks, VMS, + SymbianOS, WinCE, LynxOS, Netware, QNX, Interix, TPF.
    • +
  • GCC now implements C90- and C99-conforming rules for constant + expressions. This may cause warnings or errors for some code + using expressions that can be folded to a constant but are not + constant expressions as defined by ISO C.
    • +
  • All known target-independent C90 and C90 Amendment 1 + conformance bugs, and all known target-independent C99 conformance + bugs not related to floating point or extended identifiers, have + been fixed.
    • +
  • The C decimal floating point support now includes support for + the FLOAT_CONST_DECIMAL64 pragma.
    • +
  • The named address space feature from ISO/IEC TR 18037 is now + supported. This is currently only implemented for the SPU + processor.
    • +
+ +

C++

+
    +
  • Improved experimental support for the + upcoming C++0x ISO C++ standard, including support for raw strings, + lambda expressions and explicit type conversion + operators.
    • + +
  • When printing the name of a class template specialization, G++ will + now omit any template arguments which come from default template + arguments. This behavior (and the pretty-printing of function template + specializations as template signature and arguments) can be disabled + with the -fno-pretty-templates option.
    • + +
  • Access control is now applied to typedef names used in + a template, which may cause G++ to reject some ill-formed code that was + accepted by earlier releases. The -fno-access-control + option can be used as a temporary workaround until the code is + corrected.
    • + +
  • Compilation time for code that uses templates should now scale + linearly with the number of instantiations rather than quadratically, + as template instantiations are now looked up using hash tables.
    • + +
  • Declarations of functions that look like builtin declarations of + library functions are only considered to be redeclarations if they + are declared with extern "C". This may cause problems with + code that omits extern "C" on hand-written declarations of + C library functions such as abort + or memcpy. Such code is ill-formed, but was accepted by + earlier releases.
    • + +
  • Diagnostics that used to complain about passing non-POD types to + ... or jumping past the declaration of a non-POD + variable now check for triviality rather than PODness, as per + C++0x.
    • + +
  • In C++0x mode local and anonymous classes are now allowed as + template arguments, and in declarations of variables and functions + with linkage, so long as any such declaration that is used is also + defined (DR 757).
    • + +
  • Labels may now have attributes, as has been permitted for a + while in C. This is only permitted when the label definition and + the attribute specifier is followed by a semicolon—i.e., the + label applies to an empty statement. The only useful attribute + for a label is unused.
    • + +
  • + G++ now implements + DR + 176. Previously G++ did not support using the + injected-class-name of a template base class as a type name, and + lookup of the name found the declaration of the template in the + enclosing scope. Now lookup of the name finds the + injected-class-name, which can be used either as a type or as a + template, depending on whether or not the name is followed by a + template argument list. As a result of this change, some code that + was previously accepted may be ill-formed because +
      +
    1. The injected-class-name is not accessible because it's from a + private base, or
      2. +
    2. The injected-class-name cannot be used as an argument for a + template template parameter.
      3. +
    + In either of these cases, the code can be fixed by adding a + nested-name-specifier to explicitly name the template. The first can + be worked around with -fno-access-control; the second is + only rejected with -pedantic. +
    • + +
  • A new standard mangling for SIMD vector types has been added, to + avoid name clashes on systems with vectors of varying length. By + default the compiler still uses the old mangling, but emits aliases + with the new mangling on targets that support strong aliases. Users + can switch over entirely to the new mangling + with -fabi-version=4 or -fabi-version=0. + -Wabi will now warn about code that uses the old mangling.
    • +
+

Runtime Library (libstdc++)

+ +
    +
  • + Improved experimental support for the upcoming ISO C++ standard, + C++0x, including: +
      +
    • Support for <future>, <functional>, + and <random>.
      • +
    • Existing facilities now exploit explicit operators and the + newly implemented core C++0x features.
      • +
    +
    • + +
  • +

    An experimental + profile mode has been added. This is an implementation of + many C++ standard library constructs with an additional analysis + layer that gives performance improvement advice based on + recognition of suboptimal usage patterns. For example, +

    + +
    +#include <vector>
+int main() 
+{
+  std::vector<int> v;
+  for (int k = 0; k < 1024; ++k) 
+    v.insert(v.begin(), k);
+}
+
    + +

    +When instrumented via the profile mode, can return suggestions about +the initial size and choice of the container used as follows: +

    + +
    +vector-to-list: improvement = 5: call stack = 0x804842c ...
+    : advice = change std::vector to std::list
+vector-size: improvement = 3: call stack = 0x804842c ...
+    : advice = change initial container size from 0 to 1024
+
    + +

    +These constructs can be substituted for the normal libstdc++ +constructs on a piecemeal basis, or all existing components can be +transformed via the -D_GLIBCXX_PROFILE macro. +

    +
    • + +
  • Support for decimal floating-point arithmetic + (aka ISO C++ TR 24733) has been added. This support is in header file + <decimal/decimal>, uses namespace + std::decimal, and includes classes decimal32, + decimal64, and decimal128.
    • + +
  • Sources have been audited for application of function attributes + nothrow, const, pure, and + noreturn.
    • + +
  • Python pretty-printers have been added for many standard + library components that simplify the internal representation and + present a more intuitive view of components when used with + appropriately-advanced versions of GDB. For more information, + please consult the + more detailed + description.
    • + +
  • The default behavior for comparing typeinfo names has changed, + so in <typeinfo>, + __GXX_MERGED_TYPEINFO_NAMES now defaults to zero.
    • + +
  • The new -static-libstdc++ option + directs g++ to link the C++ library statically, even + if the default would normally be to link it dynamically.
    • +
+ +

Fortran

+
    +
  • The COMMON default padding has been changed – + instead of adding the padding before a variable it is now added + afterwards, which increases the compatibility with other vendors + and helps to obtain the correct output in some cases. Cf. also the + -falign-commons option (added + in 4.4).
    • + +
  • The -finit-real= option now also supports the value + snan for signalling not-a-number; to be effective, + one additionally needs to enable trapping (e.g. via + -ffpe-trap=). Note: Compile-time optimizations can + turn a signalling NaN into a quiet one.
    • + +
  • The new option -fcheck= has been added with the + options bounds, array-temps, + do, pointer, and recursive. The + bounds and array-temps options are + equivalent to -fbounds-check and + -fcheck-array-temporaries. The do + option checks for invalid modification of loop iteration variables, + and the recursive option tests for recursive calls + to subroutines/functions which are not marked as recursive. With + pointer pointer association checks in calls are performed; + however, neither undefined pointers nor pointers in expressions are + handled. Using -fcheck=all enables all these run-time + checks.
    • + +
  • The run-time checking -fcheck=bounds now warns + about invalid string lengths of character dummy arguments. Additionally, + more compile-time checks have been added.
    • + +
  • The new option -fno-protect-parens has been added; if set, the + compiler may reorder REAL and COMPLEX expressions without regard + to parentheses.
    • + +
  • GNU Fortran no longer links against libgfortranbegin. + As before, MAIN__ (assembler symbol name) is the actual + Fortran main program, which is invoked by the main function. + However, main is now generated and put in the same object + file as MAIN__. For the time being, + libgfortranbegin still exists for backward + compatibility. For details see the new Mixed-Language + Programming chapter in the manual.
    • + +
  • The I/O library was restructured for performance and cleaner + code.
    • + +
  • Array assignments and WHERE are now run in parallel when + OpenMP's WORKSHARE is used.
    • + +
  • The experimental option -fwhole-file was added. The option + allows whole-file checking of procedure arguments and allows for better + optimizations. It can also be used with -fwhole-program, + which is now also supported in gfortran.
    • + +
  • More Fortran 2003 and Fortran 2008 mathematical functions can + now be used as initialization expressions.
    • +
  • Some extended attributes such as STDCALL are now + supported via the + GCC$ compiler directive.
    • +
  • For Fortran 77 compatibility: If -fno-sign-zero is + used, the SIGN intrinsic behaves now as if zero were always + positive.
    • +
  • For legacy compatibiliy: On Cygwin and MinGW, the special files + CONOUT$ and CONIN$ (and CONERR$ + which maps to CONOUT$) are now supported.
    • + +
  • Fortran 2003 support has been extended: +
      +
    • Procedure-pointer function results and procedure-pointer + components (including PASS),
      • +
    • allocatable scalars (experimental),
      • +
    • DEFERRED type-bound procedures,
      • +
    • the ERRMSG= argument of the ALLOCATE + and DEALLOCATE statements have been implemented.
      • +
    • The ALLOCATE statement supports type-specs and + the SOURCE= argument.
      • +
    • OPERATOR(*) and ASSIGNMENT(=) are now + allowed as GENERIC type-bound procedure (i.e. as + type-bound operators).
      • +
    • Rounding (ROUND=, RZ, ...) for output + is now supported.
      • +
    • The INT_FAST{8,16,32,64,128}_T kind type parameters + of the intrinsic module ISO_C_BINDING are now + supported, except for the targets listed above as ones where + GCC does not have <stdint.h> type information. +
      • +
    • Extensible derived types with type-bound procedure or procedure + pointer with PASS attribute now have to use + CLASS in line with the Fortran 2003 standard; the + workaround to use TYPE is no longer supported.
      • +
    • Experimental, incomplete + support for polymorphism, including CLASS, + SELECT TYPE and dynamic dispatch of type-bound + procedure calls. Some features do not work yet such as + unlimited polymorphism (CLASS(*)).
      • +
    +
    • + +
  • Fortran 2008 support has been extended: +
      +
    • The OPEN statement now supports the + NEWUNIT= option, which returns a unique file unit, + thus preventing inadvertent use of the same unit in different parts + of the program.
      • +
    • Support for unlimited format items has been added.
      • +
    • The INT{8,16,32} and REAL{32,64,128} + kind type parameters of the intrinsic module + ISO_FORTRAN_ENV are now supported.
      • +
    • Using complex arguments with TAN, SINH, + COSH, TANH, ASIN, + ACOS, and ATAN is now possible; the + functions ASINH, ACOSH, and + ATANH have been added (for real and complex arguments) + and ATAN(Y,X) is now an alias for ATAN2(Y,X). +
      • +
    • The BLOCK construct has been implemented.
      • +
    +
    • +
+ +

Java (GCJ)

+ +

New Targets and Target Specific Improvements

+ +

AIX

+
    +
  • Full cross-toolchain support now available with GNU Binutils
    • +
+ +

ARM

+
    +
  • GCC now supports the Cortex-M0 and Cortex-A5 processors.
    • +
  • GCC now supports the ARM v7E-M architecture.
    • +
  • GCC now supports VFPv4-based FPUs and FPUs with + single-precision-only VFP.
    • +
  • GCC has many improvements to optimization for other ARM + processors, including scheduling support for the integer pipeline + on Cortex-A9.
    • +
  • GCC now supports the IEEE 754-2008 half-precision + floating-point type, and a variant ARM-specific half-precision + type. This type is specified using __fp16, with the + layout determined by -mfp16-format. With + appropriate -mfpu options, the Cortex-A9 and VFPv4 + half-precision instructions will be used.
    • +
  • GCC now supports the variant of AAPCS that uses VFP registers + for parameter passing and return values.
    • +
+ +

AVR

+
    +
  • The -mno-tablejump option has been removed because it + has the same effect as the -fno-jump-tables option.
    • +
  • Added support for these new AVR devices: +
      +
    • ATmega8U2
      • +
    • ATmega16U2
      • +
    • ATmega32U2
      • +
    +
    • +
+ +

IA-32/x86-64

+
    +
  • GCC now will set the default for -march= based on + the configure target.
    • +
  • GCC now supports handling floating-point excess precision + arising from use of the x87 floating-point unit in a way that + conforms to ISO C99. This is enabled + with -fexcess-precision=standard and with standards + conformance options such as -std=c99, and may be + disabled using -fexcess-precision=fast.
    • +
  • Support for the Intel Atom processor is now available through the + -march=atom and -mtune=atom options.
    • +
  • A new -mcrc32 option is now available to enable + crc32 intrinsics.
    • +
  • A new -mmovbe option is now available to enable GCC + to use the movbe instruction to implement + __builtin_bswap32 and __builtin_bswap64. +
    • +
  • SSE math now can be enabled by default at configure time with the + new --with-fpmath=sse option.
    • +
  • There is a new intrinsic header file, <x86intrin.h>. It + should be included before using any IA-32/x86-64 intrinsics.
    • +
  • Support for the XOP, FMA4, and LWP instruction sets for the AMD + Orochi processors are now available with + the -mxop, -mfma4, + and -mlwp options.
    • +
  • The -mabm option enables GCC to use + the popcnt and lzcnt instructions on AMD + processors.
    • +
  • The -mpopcnt option enables GCC to use + the popcnt instructions on both AMD and Intel + processors.
    • +
+ +

M68K/ColdFire

+
    +
  • GCC now supports ColdFire 51xx, 5221x, 5225x, 52274, 52277, + 5301x and 5441x devices.
    • +
  • GCC now supports thread-local storage (TLS) on M68K and + ColdFire processors.
    • +
+ +

MeP

+ +

Support has been added for the Toshiba Media embedded Processor (MeP, or +mep-elf) embedded target.

+ +

MIPS

+
    +
  • GCC now supports MIPS 1004K processors.
    • +
  • GCC can now be configured with + options --with-arch-32, --with-arch-64, + --with-tune-32 and --with-tune-64 to + control the default optimization separately for 32-bit and 64-bit + modes.
    • +
  • MIPS targets now support an alternative _mcount interface, + in which register $12 points to the function's save slot + for register $31. This interface is selected by the + -mcount-ra-address option; see the documentation for + more details.
    • +
  • GNU/Linux targets can now generate read-only .eh_frame + sections. This optimization requires GNU binutils 2.20 or above, and + is only available if GCC is configured with a suitable version of + binutils.
    • +
  • GNU/Linux targets can now attach special relocations to indirect + calls, so that the linker can turn them into direct jumps or branches. + This optimization requires GNU binutils 2.20 or later, and is + automatically selected if GCC is configured with an appropriate + version of binutils. It can be explicitly enabled or disabled + using the -mrelax-pic-calls command-line option.
    • +
  • GCC now generates more heavily-optimized atomic operations on + Octeon processors.
    • +
  • MIPS targets now support the -fstack-protector option.
    • +
  • GCC now supports an -msynci option, which specifies + that synci is enough to flush the instruction cache, + without help from the operating system. GCC uses this information + to optimize automatically-generated cache flush operations, such as + those used for nested functions in C. There is also a + --with-synci configure-time option, which makes + -msynci the default.
    • +
  • GCC supports four new function attributes for interrupt + handlers: interrupt, use_shadow_register_set, + keep_interrupts_masked and + use_debug_exception_return. See the documentation + for more details about these attributes.
    • +
+ +

picochip

+ +

RS/6000 (POWER/PowerPC)

+
    +
  • GCC now supports the Power ISA 2.06, which includes the VSX + instructions that add vector 64-bit floating point support, new population + count instructions, and conversions between floating point and unsigned types.
    • +
  • Support for the power7 processor is now available through the + -mcpu=power7 and -mtune=power7.
    • +
  • GCC will now vectorize loops that contain simple math functions like copysign + when generating code for altivec or VSX targets.
    • +
  • Support for the A2 processor is now available through the + -mcpu=a2 and -mtune=a2 options.
    • +
  • Support for the 476 processor is now available through the + -mcpu={476,476fp} and -mtune={476,476fp} + options.
    • +
  • Support for the e500mc64 processor is now available through + the -mcpu=e500mc64 + and -mtune=e500mc64 options.
    • +
  • GCC can now be configured with + options --with-cpu-32, --with-cpu-64, + --with-tune-32 and --with-tune-64 to + control the default optimization separately for 32-bit and 64-bit + modes.
    • +
+ +

RX

+ +

Support has been added for the Renesas RX Processor (rx-elf) target.

+ +

Operating Systems

+ +

Windows (Cygwin and MinGW)

+
    +
  • GCC now installs all the major language runtime libraries as DLLs + when configured with the --enable-shared option.
    • +
  • GCC now makes use of the new support for aligned common variables in + versions of binutils >= 2.20 to fix bugs in the support for SSE data + types.
    • +
  • Improvements to the libffi support library increase the reliability + of code generated by GCJ on all Windows platforms. Libgcj is enabled + by default for the first time.
    • +
  • Libtool improvements simplify installation by placing the generated + DLLs in the correct binaries directory.
    • +
  • Numerous other minor bugfixes and improvements, and substantial + enhancements to the Fortran language support library.
    • +
+ +

Documentation improvements

+ +

Other significant improvements

+ +

Plugins

+
    +
  • It is now possible to extend the compiler without having to + modify its source code. A new option -fplugin=file.so + tells GCC to load the shared object file.so and execute + it as part of the compiler. The internal documentation describes + the details on how plugins can interact with the compiler.
    • +
+ +

Installation changes

+ +
    +
  • + The move to newer autotools changed default installation directories + and switches to control them: + + The --with-datarootdir, --with-docdir, + --with-pdfdir, and --with-htmldir switches are + not used any more. Instead, you can now use --datarootdir, + --docdir, --htmldir, and --pdfdir. + The default installation directories have changed as follows according to + the GNU Coding Standards: + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    datarootdirread-only architecture-independent data root [PREFIX/share]
    localedirlocale-specific message catalogs [DATAROOTDIR/locale]
    docdirdocumentation root [DATAROOTDIR/doc/PACKAGE]
    htmldirhtml documentation [DOCDIR]
    dvidirdvi documentation [DOCDIR]
    pdfdirpdf documentation [DOCDIR]
    psdirps documentation [DOCDIR]
    + + The following variables have new default values: + + + + + + + + + + + + + + + + +
    datadirread-only architecture-independent data [DATAROOTDIR]
    infodirinfo documentation [DATAROOTDIR/info]
    mandirman documentation [DATAROOTDIR/man]
    +
    • +
+ + + + + + + +
+ +

Please send FSF & GNU inquiries & questions to +gnu@gnu.org. +There are also other ways +to contact the FSF.

+ +

These pages are maintained by +the GCC team.

+ +
For questions related to the use of GCC, please consult these web +pages and the GCC manuals. If +that fails, the gcc-help@gcc.gnu.org +mailing list might help.
+Please send comments on these web pages and the development of GCC to our +developer mailing list at gcc@gnu.org +or gcc@gcc.gnu.org. All of our lists +have public archives. +
+ +

Copyright (C) Free Software Foundation, Inc., +51 Franklin St, Fifth Floor, Boston, MA 02110, USA.

+

Verbatim copying and distribution of this entire article is +permitted in any medium, provided this notice is preserved.

+ +
+ Last modified 2010-04-17 + + + Valid XHTML 1.0 + + +
+ +
+ + + + + + + --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.s390 +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.s390 @@ -0,0 +1,3 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.16.powerpc" --- gcc-4.5-4.5.2.orig/debian/gij-hppa +++ gcc-4.5-4.5.2/debian/gij-hppa @@ -0,0 +1,20 @@ +#! /bin/sh + +prctl= + +case "$(prctl --unaligned=)" in *signal) + echo >&2 "$(basename $0): ignore unaligned memory accesses" + prctl="prctl --unaligned=default" +esac + +exec $prctl /usr/bin/gij-4.4.bin "$@" +#! /bin/sh + +prctl= + +case "$(prctl --unaligned=)" in *signal) + echo >&2 "$(basename $0): ignore unaligned memory accesses" + prctl="prctl --unaligned=default" +esac + +exec $prctl /usr/bin/gij-4.4.bin "$@" --- gcc-4.5-4.5.2.orig/debian/dummy-man.1 +++ gcc-4.5-4.5.2/debian/dummy-man.1 @@ -0,0 +1,29 @@ +.TH @NAME@ 1 "May 24, 2003" @name@ "Debian Free Documentation" +.SH NAME +@name@ \- A program with a man page covered by the GFDL with invariant sections +.SH SYNOPSIS +@name@ [\fB\s-1OPTION\s0\fR] ... [\fI\s-1ARGS\s0\fR...] + +.SH DESCRIPTION + +\fB@name@\fR is documented by a man page, which is covered by the "GNU +Free Documentation License" (GFDL) containing invariant sections. +.P +In November 2002, version 1.2 of the GNU Free Documentation License (GNU +FDL) was released by the Free Software Foundation after a long period +of consultation. Unfortunately, some concerns raised by members of the +Debian Project were not addressed, and as such the GNU FDL can apply +to works that do not pass the Debian Free Software Guidelines (DFSG), +and may thus only be included in the non-free component of the Debian +archive, not the Debian distribution itself. + +.SH "SEE ALSO" +.BR http://gcc.gnu.org/onlinedocs/ +for the complete documentation, +.BR http://lists.debian.org/debian-legal/2003/debian-legal-200304/msg00307.html +for a proposed statement of Debian with respect to the GFDL, +.BR gfdl(7) + +.SH AUTHOR +This manual page was written by the Debian GCC maintainers, +for the Debian GNU/Linux system. --- gcc-4.5-4.5.2.orig/debian/runcheck.sh +++ gcc-4.5-4.5.2/debian/runcheck.sh @@ -0,0 +1,20 @@ +#! /bin/sh + +mkdir -p build + +cat >build/runcheck.c < +int main() +{ + return printf("yes\n") != 4; +} +EOF + +if m=$(${CC:-gcc} -o build/runcheck build/runcheck.c 2>&1); then + m=$(build/runcheck 2>&1) + echo ${m#* } > build/runcheck.out + echo ${m#* } +else + echo ${m##*:} > build/runcheck.out + echo ${m##*:} +fi --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.lpia +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.lpia @@ -0,0 +1,6 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" +#include "libstdc++6.symbols.excprop" + __gxx_personality_v0@CXXABI_1.3 4.1.1 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 --- gcc-4.5-4.5.2.orig/debian/libgomp1.symbols.common +++ gcc-4.5-4.5.2/debian/libgomp1.symbols.common @@ -0,0 +1,154 @@ + GOMP_1.0@GOMP_1.0 4.2.1 + GOMP_2.0@GOMP_2.0 4.4 + GOMP_atomic_end@GOMP_1.0 4.2.1 + GOMP_atomic_start@GOMP_1.0 4.2.1 + GOMP_barrier@GOMP_1.0 4.2.1 + GOMP_critical_end@GOMP_1.0 4.2.1 + GOMP_critical_name_end@GOMP_1.0 4.2.1 + GOMP_critical_name_start@GOMP_1.0 4.2.1 + GOMP_critical_start@GOMP_1.0 4.2.1 + GOMP_loop_dynamic_next@GOMP_1.0 4.2.1 + GOMP_loop_dynamic_start@GOMP_1.0 4.2.1 + GOMP_loop_end@GOMP_1.0 4.2.1 + GOMP_loop_end_nowait@GOMP_1.0 4.2.1 + GOMP_loop_guided_next@GOMP_1.0 4.2.1 + GOMP_loop_guided_start@GOMP_1.0 4.2.1 + GOMP_loop_ordered_dynamic_next@GOMP_1.0 4.2.1 + GOMP_loop_ordered_dynamic_start@GOMP_1.0 4.2.1 + GOMP_loop_ordered_guided_next@GOMP_1.0 4.2.1 + GOMP_loop_ordered_guided_start@GOMP_1.0 4.2.1 + GOMP_loop_ordered_runtime_next@GOMP_1.0 4.2.1 + GOMP_loop_ordered_runtime_start@GOMP_1.0 4.2.1 + GOMP_loop_ordered_static_next@GOMP_1.0 4.2.1 + GOMP_loop_ordered_static_start@GOMP_1.0 4.2.1 + GOMP_loop_runtime_next@GOMP_1.0 4.2.1 + GOMP_loop_runtime_start@GOMP_1.0 4.2.1 + GOMP_loop_static_next@GOMP_1.0 4.2.1 + GOMP_loop_static_start@GOMP_1.0 4.2.1 + GOMP_loop_ull_dynamic_next@GOMP_2.0 4.4 + GOMP_loop_ull_dynamic_start@GOMP_2.0 4.4 + GOMP_loop_ull_guided_next@GOMP_2.0 4.4 + GOMP_loop_ull_guided_start@GOMP_2.0 4.4 + GOMP_loop_ull_ordered_dynamic_next@GOMP_2.0 4.4 + GOMP_loop_ull_ordered_dynamic_start@GOMP_2.0 4.4 + GOMP_loop_ull_ordered_guided_next@GOMP_2.0 4.4 + GOMP_loop_ull_ordered_guided_start@GOMP_2.0 4.4 + GOMP_loop_ull_ordered_runtime_next@GOMP_2.0 4.4 + GOMP_loop_ull_ordered_runtime_start@GOMP_2.0 4.4 + GOMP_loop_ull_ordered_static_next@GOMP_2.0 4.4 + GOMP_loop_ull_ordered_static_start@GOMP_2.0 4.4 + GOMP_loop_ull_runtime_next@GOMP_2.0 4.4 + GOMP_loop_ull_runtime_start@GOMP_2.0 4.4 + GOMP_loop_ull_static_next@GOMP_2.0 4.4 + GOMP_loop_ull_static_start@GOMP_2.0 4.4 + GOMP_ordered_end@GOMP_1.0 4.2.1 + GOMP_ordered_start@GOMP_1.0 4.2.1 + GOMP_parallel_end@GOMP_1.0 4.2.1 + GOMP_parallel_loop_dynamic_start@GOMP_1.0 4.2.1 + GOMP_parallel_loop_guided_start@GOMP_1.0 4.2.1 + GOMP_parallel_loop_runtime_start@GOMP_1.0 4.2.1 + GOMP_parallel_loop_static_start@GOMP_1.0 4.2.1 + GOMP_parallel_sections_start@GOMP_1.0 4.2.1 + GOMP_parallel_start@GOMP_1.0 4.2.1 + GOMP_sections_end@GOMP_1.0 4.2.1 + GOMP_sections_end_nowait@GOMP_1.0 4.2.1 + GOMP_sections_next@GOMP_1.0 4.2.1 + GOMP_sections_start@GOMP_1.0 4.2.1 + GOMP_single_copy_end@GOMP_1.0 4.2.1 + GOMP_single_copy_start@GOMP_1.0 4.2.1 + GOMP_single_start@GOMP_1.0 4.2.1 + GOMP_task@GOMP_2.0 4.4 + GOMP_taskwait@GOMP_2.0 4.4 + OMP_1.0@OMP_1.0 4.2.1 + OMP_2.0@OMP_2.0 4.2.1 + OMP_3.0@OMP_3.0 4.4 + omp_destroy_lock@OMP_1.0 4.2.1 + omp_destroy_lock@OMP_3.0 4.4 + omp_destroy_lock_@OMP_1.0 4.2.1 + omp_destroy_lock_@OMP_3.0 4.4 + omp_destroy_nest_lock@OMP_1.0 4.2.1 + omp_destroy_nest_lock@OMP_3.0 4.4 + omp_destroy_nest_lock_@OMP_1.0 4.2.1 + omp_destroy_nest_lock_@OMP_3.0 4.4 + omp_get_active_level@OMP_3.0 4.4 + omp_get_active_level_@OMP_3.0 4.4 + omp_get_ancestor_thread_num@OMP_3.0 4.4 + omp_get_ancestor_thread_num_8_@OMP_3.0 4.4 + omp_get_ancestor_thread_num_@OMP_3.0 4.4 + omp_get_dynamic@OMP_1.0 4.2.1 + omp_get_dynamic_@OMP_1.0 4.2.1 + omp_get_level@OMP_3.0 4.4 + omp_get_level_@OMP_3.0 4.4 + omp_get_max_active_levels@OMP_3.0 4.4 + omp_get_max_active_levels_@OMP_3.0 4.4 + omp_get_max_threads@OMP_1.0 4.2.1 + omp_get_max_threads_@OMP_1.0 4.2.1 + omp_get_nested@OMP_1.0 4.2.1 + omp_get_nested_@OMP_1.0 4.2.1 + omp_get_num_procs@OMP_1.0 4.2.1 + omp_get_num_procs_@OMP_1.0 4.2.1 + omp_get_num_threads@OMP_1.0 4.2.1 + omp_get_num_threads_@OMP_1.0 4.2.1 + omp_get_schedule@OMP_3.0 4.4 + omp_get_schedule_8_@OMP_3.0 4.4 + omp_get_schedule_@OMP_3.0 4.4 + omp_get_team_size@OMP_3.0 4.4 + omp_get_team_size_8_@OMP_3.0 4.4 + omp_get_team_size_@OMP_3.0 4.4 + omp_get_thread_limit@OMP_3.0 4.4 + omp_get_thread_limit_@OMP_3.0 4.4 + omp_get_thread_num@OMP_1.0 4.2.1 + omp_get_thread_num_@OMP_1.0 4.2.1 + omp_get_wtick@OMP_2.0 4.2.1 + omp_get_wtick_@OMP_2.0 4.2.1 + omp_get_wtime@OMP_2.0 4.2.1 + omp_get_wtime_@OMP_2.0 4.2.1 + omp_in_parallel@OMP_1.0 4.2.1 + omp_in_parallel_@OMP_1.0 4.2.1 + omp_init_lock@OMP_1.0 4.2.1 + omp_init_lock@OMP_3.0 4.4 + omp_init_lock_@OMP_1.0 4.2.1 + omp_init_lock_@OMP_3.0 4.4 + omp_init_nest_lock@OMP_1.0 4.2.1 + omp_init_nest_lock@OMP_3.0 4.4 + omp_init_nest_lock_@OMP_1.0 4.2.1 + omp_init_nest_lock_@OMP_3.0 4.4 + omp_set_dynamic@OMP_1.0 4.2.1 + omp_set_dynamic_8_@OMP_1.0 4.2.1 + omp_set_dynamic_@OMP_1.0 4.2.1 + omp_set_lock@OMP_1.0 4.2.1 + omp_set_lock@OMP_3.0 4.4 + omp_set_lock_@OMP_1.0 4.2.1 + omp_set_lock_@OMP_3.0 4.4 + omp_set_max_active_levels@OMP_3.0 4.4 + omp_set_max_active_levels_8_@OMP_3.0 4.4 + omp_set_max_active_levels_@OMP_3.0 4.4 + omp_set_nest_lock@OMP_1.0 4.2.1 + omp_set_nest_lock@OMP_3.0 4.4 + omp_set_nest_lock_@OMP_1.0 4.2.1 + omp_set_nest_lock_@OMP_3.0 4.4 + omp_set_nested@OMP_1.0 4.2.1 + omp_set_nested_8_@OMP_1.0 4.2.1 + omp_set_nested_@OMP_1.0 4.2.1 + omp_set_num_threads@OMP_1.0 4.2.1 + omp_set_num_threads_8_@OMP_1.0 4.2.1 + omp_set_num_threads_@OMP_1.0 4.2.1 + omp_set_schedule@OMP_3.0 4.4 + omp_set_schedule_8_@OMP_3.0 4.4 + omp_set_schedule_@OMP_3.0 4.4 + omp_test_lock@OMP_1.0 4.2.1 + omp_test_lock@OMP_3.0 4.4 + omp_test_lock_@OMP_1.0 4.2.1 + omp_test_lock_@OMP_3.0 4.4 + omp_test_nest_lock@OMP_1.0 4.2.1 + omp_test_nest_lock@OMP_3.0 4.4 + omp_test_nest_lock_@OMP_1.0 4.2.1 + omp_test_nest_lock_@OMP_3.0 4.4 + omp_unset_lock@OMP_1.0 4.2.1 + omp_unset_lock@OMP_3.0 4.4 + omp_unset_lock_@OMP_1.0 4.2.1 + omp_unset_lock_@OMP_3.0 4.4 + omp_unset_nest_lock@OMP_1.0 4.2.1 + omp_unset_nest_lock@OMP_3.0 4.4 + omp_unset_nest_lock_@OMP_1.0 4.2.1 + omp_unset_nest_lock_@OMP_3.0 4.4 --- gcc-4.5-4.5.2.orig/debian/locale-gen +++ gcc-4.5-4.5.2/debian/locale-gen @@ -0,0 +1,48 @@ +#!/bin/sh + +LOCPATH=`pwd`/locales +export LOCPATH + +[ -d $LOCPATH ] || mkdir -p $LOCPATH + +umask 022 + +echo "Generating locales..." +while read locale charset; do + case $locale in \#*) continue;; esac + [ -n "$locale" -a -n "$charset" ] || continue + echo -n " `echo $locale | sed 's/\([^.\@]*\).*/\1/'`" + echo -n ".$charset" + echo -n `echo $locale | sed 's/\([^\@]*\)\(\@.*\)*/\2/'` + echo -n '...' + if [ -f $LOCPATH/$locale ]; then + input=$locale + else + input=`echo $locale | sed 's/\([^.]*\)[^@]*\(.*\)/\1\2/'` + fi + localedef -i $input -c -f $charset $LOCPATH/$locale #-A /etc/locale.alias + echo ' done'; \ +done <= 2.95) and gcc-snapshot +# Targets found in this makefile: +# - unpack tarballs +# - patch sources +# - (re)create the control file +# - create a debian/rules.parameters file, which is included +# by debian/rules2 +# All other targets are passed to the debian/rules2 file + +# Uncomment this to turn on verbose mode. +#export DH_VERBOSE=1 + +unexport LANG LC_ALL LC_CTYPE LC_COLLATE LC_TIME LC_NUMERIC LC_MESSAGES + +default: build + +include debian/rules.defs +include debian/rules.unpack +include debian/rules.patch + +control: $(control_dependencies) + -mkdir -p $(stampdir) + $(MAKE) -f debian/rules.conf $@ + +configure: $(configure_dependencies) +$(configure_stamp): control $(unpack_stamp) $(patch_stamp) + $(MAKE) -f debian/rules2 $@ +$(configure_dummy_stamp): control + $(MAKE) -f debian/rules2 $@ +$(configure_hppa64_stamp): $(build_stamp) + $(MAKE) -f debian/rules2 $@ +$(configure_neon_stamp): $(build_stamp) + $(MAKE) -f debian/rules2 $@ +$(configure_spu_stamp): $(build_stamp) + $(MAKE) -f debian/rules2 $@ + +pre-build: +#ifneq (,$(filter $(distrelease),squeeze sid)) +#ifeq (,$(filter $(DEB_TARGET_ARCH),amd64 i386)) +# @echo explicitely fail the build for $(DEB_TARGET_ARCH) +# @echo no bug report required. please ask the port maintainers if they support gcc-4.5. +# false +#endif +#endif + +build: pre-build $(build_dependencies) +$(build_stamp): $(unpack_stamp) $(patch_stamp) $(configure_stamp) + $(MAKE) -f debian/rules2 $@ +$(build_dummy_stamp): $(configure_dummy_stamp) + $(MAKE) -f debian/rules2 $@ +$(build_javadoc_stamp): $(build_stamp) + $(MAKE) -f debian/rules2 $@ +$(build_hppa64_stamp): $(configure_hppa64_stamp) + $(MAKE) -f debian/rules2 $@ +$(build_neon_stamp): $(configure_neon_stamp) + $(MAKE) -f debian/rules2 $@ +$(build_spu_stamp): $(configure_spu_stamp) + $(MAKE) -f debian/rules2 $@ + +check: $(check_stamp) +$(check_stamp): $(build_stamp) + $(MAKE) -f debian/rules2 $@ + +clean: + rm -rf $(stampdir) +# remove temporary dirs used for unpacking + rm -rf $(gcc_srcdir) $(gdc_srcdir) d + -$(MAKE) -f debian/rules2 $@ + rm -rf $(srcdir)* $(builddir)* debian/tmp* html + rm -f bootstrap-* first-move-stamp + rm -f autotools_files + rm -f debian/*.tmp + rm -f debian/soname-cache + find debian -name '.#*' | xargs -r rm -f + rm -f $(series_file)* + dh_clean + +install: $(install_dependencies) +$(install_stamp): $(build_stamp) + $(MAKE) -f debian/rules2 $@ +$(install_snap_stamp): $(build_stamp) + $(MAKE) -f debian/rules2 $@ +$(install_dummy_stamp): $(build_dummy_stamp) + $(MAKE) -f debian/rules2 $@ +$(install_hppa64_stamp): $(build_hppa64_stamp) + $(MAKE) -f debian/rules2 $@ +$(install_neon_stamp): $(build_neon_stamp) + $(MAKE) -f debian/rules2 $@ +$(install_spu_stamp): $(build_spu_stamp) + $(MAKE) -f debian/rules2 $@ + +html-docs doxygen-docs update-doxygen-docs update-ada-files xxx: + $(MAKE) -f debian/rules2 $@ + +binary-indep binary-arch binary: install + $(MAKE) -f debian/rules2 $@ + +source diff: + @echo >&2 'source and diff are obsolete - use dpkg-source -b'; false + +release: + foo=$(shell basename $(CURDIR)); \ + if [ "$$foo" != "gcc-3.4" ]; then \ + find -name CVS -o -name .cvsignore -o -name '.#*' | \ + xargs rm -rf; \ + fi + +.PHONY: build clean binary-indep binary-arch binary release --- gcc-4.5-4.5.2.orig/debian/libgcc4.symbols.hppa +++ gcc-4.5-4.5.2/debian/libgcc4.symbols.hppa @@ -0,0 +1,93 @@ +libgcc_s.so.4 libgcc4 #MINVER# + GCC_3.0@GCC_3.0 4.1.1 + GCC_3.3.1@GCC_3.3.1 4.1.1 + GCC_3.3@GCC_3.3 4.1.1 + GCC_3.4.2@GCC_3.4.2 4.1.1 + GCC_3.4@GCC_3.4 4.1.1 + GCC_4.0.0@GCC_4.0.0 4.1.1 + GCC_4.2.0@GCC_4.2.0 4.1.1 + GCC_4.3.0@GCC_4.3.0 4.3 + GLIBC_2.0@GLIBC_2.0 4.1.1 + _Unwind_Backtrace@GCC_3.3 4.1.1 + _Unwind_DeleteException@GCC_3.0 4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 4.1.1 + _Unwind_Find_FDE@GCC_3.0 4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 4.1.1 + _Unwind_GetCFA@GCC_3.3 4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 4.1.1 + _Unwind_GetGR@GCC_3.0 4.1.1 + _Unwind_GetIP@GCC_3.0 4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 4.1.1 + _Unwind_GetRegionStart@GCC_3.0 4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 4.1.1 + _Unwind_RaiseException@GCC_3.0 4.1.1 + _Unwind_Resume@GCC_3.0 4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 4.1.1 + _Unwind_SetGR@GCC_3.0 4.1.1 + _Unwind_SetIP@GCC_3.0 4.1.1 + __absvdi2@GCC_3.0 4.1.1 + __absvsi2@GCC_3.0 4.1.1 + __addvdi3@GCC_3.0 4.1.1 + __addvsi3@GCC_3.0 4.1.1 + __ashldi3@GCC_3.0 4.1.1 + __ashrdi3@GCC_3.0 4.1.1 + __bswapdi2@GCC_4.3.0 4.3 + __bswapsi2@GCC_4.3.0 4.3 + __clear_cache@GCC_3.0 4.1.1 + __clzdi2@GCC_3.4 4.1.1 + __clzsi2@GCC_3.4 4.1.1 + __cmpdi2@GCC_3.0 4.1.1 + __ctzdi2@GCC_3.4 4.1.1 + __ctzsi2@GCC_3.4 4.1.1 + __deregister_frame@GLIBC_2.0 4.1.1 + __deregister_frame_info@GLIBC_2.0 4.1.1 + __deregister_frame_info_bases@GCC_3.0 4.1.1 + __divdc3@GCC_4.0.0 4.1.1 + __divdi3@GLIBC_2.0 4.1.1 + __divsc3@GCC_4.0.0 4.1.1 + __emutls_get_address@GCC_4.3.0 4.3 + __emutls_register_common@GCC_4.3.0 4.3 + __enable_execute_stack@GCC_3.4.2 4.1.1 + __ffsdi2@GCC_3.0 4.1.1 + __ffssi2@GCC_4.3.0 4.3 + __fixdfdi@GCC_3.0 4.1.1 + __fixsfdi@GCC_3.0 4.1.1 + __fixunsdfdi@GCC_3.0 4.1.1 + __fixunsdfsi@GCC_3.0 4.1.1 + __fixunssfdi@GCC_3.0 4.1.1 + __fixunssfsi@GCC_3.0 4.1.1 + __floatdidf@GCC_3.0 4.1.1 + __floatdisf@GCC_3.0 4.1.1 + __floatundidf@GCC_4.2.0 4.2.1 + __floatundisf@GCC_4.2.0 4.2.1 + __frame_state_for@GLIBC_2.0 4.1.1 + __gcc_personality_v0@GCC_3.3.1 4.1.1 + __lshrdi3@GCC_3.0 4.1.1 + __moddi3@GLIBC_2.0 4.1.1 + __muldc3@GCC_4.0.0 4.1.1 + __muldi3@GCC_3.0 4.1.1 + __mulsc3@GCC_4.0.0 4.1.1 + __mulvdi3@GCC_3.0 4.1.1 + __mulvsi3@GCC_3.0 4.1.1 + __negdi2@GCC_3.0 4.1.1 + __negvdi2@GCC_3.0 4.1.1 + __negvsi2@GCC_3.0 4.1.1 + __paritydi2@GCC_3.4 4.1.1 + __paritysi2@GCC_3.4 4.1.1 + __popcountdi2@GCC_3.4 4.1.1 + __popcountsi2@GCC_3.4 4.1.1 + __powidf2@GCC_4.0.0 4.1.1 + __powisf2@GCC_4.0.0 4.1.1 + __register_frame@GLIBC_2.0 4.1.1 + __register_frame_info@GLIBC_2.0 4.1.1 + __register_frame_info_bases@GCC_3.0 4.1.1 + __register_frame_info_table@GLIBC_2.0 4.1.1 + __register_frame_info_table_bases@GCC_3.0 4.1.1 + __register_frame_table@GLIBC_2.0 4.1.1 + __subvdi3@GCC_3.0 4.1.1 + __subvsi3@GCC_3.0 4.1.1 + __ucmpdi2@GCC_3.0 4.1.1 + __udivdi3@GLIBC_2.0 4.1.1 + __udivmoddi4@GCC_3.0 4.1.1 + __umoddi3@GLIBC_2.0 4.1.1 --- gcc-4.5-4.5.2.orig/debian/lib64stdc++6.symbols.s390 +++ gcc-4.5-4.5.2/debian/lib64stdc++6.symbols.s390 @@ -0,0 +1,11 @@ +libstdc++.so.6 lib64stdc++6 #MINVER# +#include "libstdc++6.symbols.64bit" +#include "libstdc++6.symbols.excprop" + _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# ldexpf@GLIBCXX_3.4.3 4.1.1 +#DEPRECATED: 4.2.2-4# powf@GLIBCXX_3.4 4.1.1 +#include "libstdc++6.symbols.glibcxxmath" +#include "libstdc++6.symbols.ldbl.64bit" + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2 --- gcc-4.5-4.5.2.orig/debian/dh_doclink +++ gcc-4.5-4.5.2/debian/dh_doclink @@ -0,0 +1,12 @@ +#! /bin/sh + +pkg=`echo $1 | sed 's/^-p//'` +target=$2 + +[ -d debian/$pkg/usr/share/doc ] || mkdir -p debian/$pkg/usr/share/doc +if [ -d debian/$pkg/usr/share/doc/$p -a ! -h debian/$pkg/usr/share/doc/$p ] +then + echo "WARNING: removing doc directory $pkg" + rm -rf debian/$pkg/usr/share/doc/$pkg +fi +ln -sf $target debian/$pkg/usr/share/doc/$pkg --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.32bit.hurd +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.32bit.hurd @@ -0,0 +1,536 @@ +#include "libstdc++6.symbols.common" + _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEj@GLIBCXX_3.4.2 4.1.1 + _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEj@GLIBCXX_3.4.2 4.1.1 + _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcj@GLIBCXX_3.4.4 4.1.1 + _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEjj@GLIBCXX_3.4.4 4.1.1 + _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcj@GLIBCXX_3.4.4 4.1.1 + _ZN9__gnu_cxx6__poolILb1EE16_M_reserve_blockEjj@GLIBCXX_3.4.4 4.1.1 + _ZN9__gnu_cxx9free_list6_M_getEj@GLIBCXX_3.4.4 4.1.1 + _ZNK10__cxxabiv117__class_type_info12__do_dyncastEiNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE@CXXABI_1.3 4.1.1 + _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcEiPKvPKS0_S2_@CXXABI_1.3 4.1.1 + _ZNK10__cxxabiv120__si_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1 + _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1 + _ZNK10__cxxabiv121__vmi_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1 + _ZNK10__cxxabiv121__vmi_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwj@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwjj@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofERKS2_j@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEwj@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwj@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwjj@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofERKS2_j@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEwj@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4.5 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwj@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwjj@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS2_j@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEwj@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwj@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwjj@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS2_j@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEwj@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE2atEj@GLIBCXX_3.4 4.1.1 + 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gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.i386 +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.i386 @@ -0,0 +1,6 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" +#include "libstdc++6.symbols.excprop" + __gxx_personality_v0@CXXABI_1.3 4.1.1 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 --- gcc-4.5-4.5.2.orig/debian/gcj-BV-jre-headless.postrm +++ gcc-4.5-4.5.2/debian/gcj-BV-jre-headless.postrm @@ -0,0 +1,10 @@ +#! /bin/sh -e + +case "$1" in + purge) + rm -f /var/lib/gcj-@BV@/classmap.db +esac + +#DEBHELPER# + +exit 0 --- gcc-4.5-4.5.2.orig/debian/gij-wrapper-BV.1 +++ gcc-4.5-4.5.2/debian/gij-wrapper-BV.1 @@ -0,0 +1,22 @@ +.TH GIJ-WRAPPER 1 "August 11, 2001" gij-wrapper "Java User's Manual" +.SH NAME +gij-wrapper \- a wrapper around gij + +.SH SYNOPSIS +gij-wrapper [\fB\s-1OPTION\s0\fR] ... \fI\s-1JARFILE\s0\fR [\fI\s-1ARGS\s0\fR...] +.PP +gij-wrapper [\fB\-jar\fR] [\fB\s-1OPTION\s0\fR] ... \fI\s-1CLASS\s0\fR [\fI\s-1ARGS\s0\fR...] + +.SH DESCRIPTION + +\fBgij-wrapper\fR is a wrapper around gij(1) to be called as the java +interpreter. Options different for java(1) and gij(1) are translated, +options unknown to gij(1) are silently ignored. + +.SH OPTIONS +See gij-@BV@(1) for a list of options that gij understands. + +.SH "SEE ALSO" +.BR gij-@BV@(1) +, +.BR java(1) --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.10 +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.10 @@ -0,0 +1,96 @@ + __iso_c_binding_c_f_pointer_c10@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_r10@GFORTRAN_1.0 4.3 + _gfortran_arandom_r10@GFORTRAN_1.0 4.3 + _gfortran_cpu_time_10@GFORTRAN_1.0 4.3 + _gfortran_erfc_scaled_r10@GFORTRAN_1.1 4.4.0 + _gfortran_exponent_r10@GFORTRAN_1.0 4.3 + _gfortran_fraction_r10@GFORTRAN_1.0 4.3 + _gfortran_matmul_c10@GFORTRAN_1.0 4.3 + _gfortran_matmul_r10@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_4_r10@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_8_r10@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_4_r10@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_8_r10@GFORTRAN_1.0 4.3 + _gfortran_maxval_r10@GFORTRAN_1.0 4.3 + _gfortran_minloc0_4_r10@GFORTRAN_1.0 4.3 + _gfortran_minloc0_8_r10@GFORTRAN_1.0 4.3 + _gfortran_minloc1_4_r10@GFORTRAN_1.0 4.3 + _gfortran_minloc1_8_r10@GFORTRAN_1.0 4.3 + _gfortran_minval_r10@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_4_r10@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_8_r10@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_4_r10@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_8_r10@GFORTRAN_1.0 4.3 + _gfortran_mmaxval_r10@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_4_r10@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_8_r10@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_4_r10@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_8_r10@GFORTRAN_1.0 4.3 + _gfortran_mminval_r10@GFORTRAN_1.0 4.3 + _gfortran_mproduct_c10@GFORTRAN_1.0 4.3 + _gfortran_mproduct_r10@GFORTRAN_1.0 4.3 + _gfortran_msum_c10@GFORTRAN_1.0 4.3 + _gfortran_msum_r10@GFORTRAN_1.0 4.3 + _gfortran_nearest_r10@GFORTRAN_1.0 4.3 + _gfortran_pow_c10_i4@GFORTRAN_1.0 4.3 + _gfortran_pow_c10_i8@GFORTRAN_1.0 4.3 + _gfortran_pow_r10_i8@GFORTRAN_1.0 4.3 + _gfortran_product_c10@GFORTRAN_1.0 4.3 + _gfortran_product_r10@GFORTRAN_1.0 4.3 + _gfortran_random_r10@GFORTRAN_1.0 4.3 + _gfortran_reshape_c10@GFORTRAN_1.0 4.3 + _gfortran_reshape_r10@GFORTRAN_1.0 4.3 + _gfortran_rrspacing_r10@GFORTRAN_1.0 4.3 + _gfortran_set_exponent_r10@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_4_r10@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_8_r10@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_4_r10@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_8_r10@GFORTRAN_1.0 4.3 + _gfortran_smaxval_r10@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_4_r10@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_8_r10@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_4_r10@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_8_r10@GFORTRAN_1.0 4.3 + _gfortran_sminval_r10@GFORTRAN_1.0 4.3 + _gfortran_spacing_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__abs_c10@GFORTRAN_1.0 4.3 + _gfortran_specific__abs_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__acos_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__acosh_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__aimag_c10@GFORTRAN_1.0 4.3 + _gfortran_specific__aint_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__anint_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__asin_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__asinh_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__atan2_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__atan_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__atanh_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__conjg_10@GFORTRAN_1.0 4.3 + _gfortran_specific__cos_c10@GFORTRAN_1.0 4.3 + _gfortran_specific__cos_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__cosh_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__dim_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__exp_c10@GFORTRAN_1.0 4.3 + _gfortran_specific__exp_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__log10_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__log_c10@GFORTRAN_1.0 4.3 + _gfortran_specific__log_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__mod_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__nint_4_10@GFORTRAN_1.0 4.3 + _gfortran_specific__nint_8_10@GFORTRAN_1.0 4.3 + _gfortran_specific__sign_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__sin_c10@GFORTRAN_1.0 4.3 + _gfortran_specific__sin_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__sinh_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__sqrt_c10@GFORTRAN_1.0 4.3 + _gfortran_specific__sqrt_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__tan_r10@GFORTRAN_1.0 4.3 + _gfortran_specific__tanh_r10@GFORTRAN_1.0 4.3 + _gfortran_sproduct_c10@GFORTRAN_1.0 4.3 + _gfortran_sproduct_r10@GFORTRAN_1.0 4.3 + _gfortran_ssum_c10@GFORTRAN_1.0 4.3 + _gfortran_ssum_r10@GFORTRAN_1.0 4.3 + _gfortran_sum_c10@GFORTRAN_1.0 4.3 + _gfortran_sum_r10@GFORTRAN_1.0 4.3 + _gfortran_transpose_c10@GFORTRAN_1.0 4.3 + _gfortran_transpose_r10@GFORTRAN_1.0 4.3 --- gcc-4.5-4.5.2.orig/debian/lib32objc2.symbols +++ gcc-4.5-4.5.2/debian/lib32objc2.symbols @@ -0,0 +1,3 @@ +libobjc.so.2 lib32objc2 #MINVER# +#include "libobjc2.symbols.common" + __gnu_objc_personality_v0@Base 4.2.1 --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.amd64 +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.amd64 @@ -0,0 +1,5 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.10" +#include "libgfortran3.symbols.16" +#include "libgfortran3.symbols.64" --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.kfreebsd-i386 +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.kfreebsd-i386 @@ -0,0 +1,3 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.10" --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.alpha +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.alpha @@ -0,0 +1,5 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.16.powerpc" +#include "libgfortran3.symbols.16.powerpc64" +#include "libgfortran3.symbols.64" --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.kfreebsd-amd64 +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.kfreebsd-amd64 @@ -0,0 +1,7 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.64bit" +#include "libstdc++6.symbols.excprop" + _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 --- gcc-4.5-4.5.2.orig/debian/source.lintian-overrides.in +++ gcc-4.5-4.5.2/debian/source.lintian-overrides.in @@ -0,0 +1,2 @@ +@SRC@: invalid-arch-string-in-source-relation +@SRC@: quilt-build-dep-but-no-series-file --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.lpia +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.lpia @@ -0,0 +1,3 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.10" --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.16 +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.16 @@ -0,0 +1,178 @@ + __iso_c_binding_c_f_pointer_i16@GFORTRAN_1.0 4.3 + _gfortran_all_l16@GFORTRAN_1.0 4.3 + _gfortran_any_l16@GFORTRAN_1.0 4.3 + _gfortran_count_16_l@GFORTRAN_1.0 4.3 + _gfortran_cshift0_16@GFORTRAN_1.1 4.4.0 + _gfortran_cshift0_16_char@GFORTRAN_1.1 4.4.0 + _gfortran_cshift1_16@GFORTRAN_1.0 4.3 + _gfortran_cshift1_16_char4@GFORTRAN_1.1 4.4.0 + _gfortran_cshift1_16_char@GFORTRAN_1.0 4.3 + _gfortran_eoshift0_16@GFORTRAN_1.1 4.4.0 + _gfortran_eoshift0_16_char@GFORTRAN_1.1 4.4.0 + _gfortran_eoshift1_16@GFORTRAN_1.0 4.3 + _gfortran_eoshift1_16_char4@GFORTRAN_1.1 4.4.0 + _gfortran_eoshift1_16_char@GFORTRAN_1.0 4.3 + _gfortran_eoshift2_16@GFORTRAN_1.1 4.4.0 + _gfortran_eoshift2_16_char@GFORTRAN_1.1 4.4.0 + _gfortran_eoshift3_16@GFORTRAN_1.0 4.3 + _gfortran_eoshift3_16_char4@GFORTRAN_1.1 4.4.0 + _gfortran_eoshift3_16_char@GFORTRAN_1.0 4.3 + _gfortran_ishftc16@GFORTRAN_1.0 4.3 + _gfortran_matmul_i16@GFORTRAN_1.0 4.3 + _gfortran_matmul_l16@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_i16@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_i1@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_i2@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_i4@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_i8@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_r10@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_r4@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_r8@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_4_i16@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_8_i16@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_i16@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_i1@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_i2@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_i4@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_i8@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_r10@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_r4@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_r8@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_4_i16@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_8_i16@GFORTRAN_1.0 4.3 + _gfortran_maxval_i16@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_i16@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_i1@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_i2@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_i4@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_i8@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_r10@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_r4@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_r8@GFORTRAN_1.0 4.3 + _gfortran_minloc0_4_i16@GFORTRAN_1.0 4.3 + _gfortran_minloc0_8_i16@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_i16@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_i1@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_i2@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_i4@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_i8@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_r10@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_r4@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_r8@GFORTRAN_1.0 4.3 + _gfortran_minloc1_4_i16@GFORTRAN_1.0 4.3 + _gfortran_minloc1_8_i16@GFORTRAN_1.0 4.3 + _gfortran_minval_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_i1@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_i2@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_i4@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_i8@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_r10@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_r4@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_r8@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_4_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_8_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_i1@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_i2@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_i4@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_i8@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_r10@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_r4@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_r8@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_4_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_8_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxval_i16@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_i16@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_i1@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_i2@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_i4@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_i8@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_r10@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_r4@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_r8@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_4_i16@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_8_i16@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_i16@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_i1@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_i2@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_i4@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_i8@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_r10@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_r4@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_r8@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_4_i16@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_8_i16@GFORTRAN_1.0 4.3 + _gfortran_mminval_i16@GFORTRAN_1.0 4.3 + _gfortran_mproduct_i16@GFORTRAN_1.0 4.3 + _gfortran_msum_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_c10_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_c4_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_c8_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_i16_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_i16_i4@GFORTRAN_1.0 4.3 + _gfortran_pow_i16_i8@GFORTRAN_1.0 4.3 + _gfortran_pow_i4_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_i8_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_r10_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_r4_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_r8_i16@GFORTRAN_1.0 4.3 + _gfortran_product_i16@GFORTRAN_1.0 4.3 + _gfortran_reshape_16@GFORTRAN_1.0 4.3 + _gfortran_shape_16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_i16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_i1@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_i2@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_i4@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_i8@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_r10@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_r4@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_r8@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_4_i16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_8_i16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_i16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_i1@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_i2@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_i4@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_i8@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_r10@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_r4@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_r8@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_4_i16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_8_i16@GFORTRAN_1.0 4.3 + _gfortran_smaxval_i16@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_i16@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_i1@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_i2@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_i4@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_i8@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_r10@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_r4@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_r8@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_4_i16@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_8_i16@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_i16@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_i1@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_i2@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_i4@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_i8@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_r10@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_r4@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_r8@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_4_i16@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_8_i16@GFORTRAN_1.0 4.3 + _gfortran_sminval_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__abs_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__char_1_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__dim_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__index_1_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__len_1_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__mod_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__nint_16_10@GFORTRAN_1.0 4.3 + _gfortran_specific__nint_16_4@GFORTRAN_1.0 4.3 + _gfortran_specific__nint_16_8@GFORTRAN_1.0 4.3 + _gfortran_specific__sign_i16@GFORTRAN_1.0 4.3 + _gfortran_sproduct_i16@GFORTRAN_1.0 4.3 + _gfortran_ssum_i16@GFORTRAN_1.0 4.3 + _gfortran_sum_i16@GFORTRAN_1.0 4.3 + _gfortran_transpose_i16@GFORTRAN_1.0 4.3 --- gcc-4.5-4.5.2.orig/debian/gcc-BV-hppa64.postinst +++ gcc-4.5-4.5.2/debian/gcc-BV-hppa64.postinst @@ -0,0 +1,13 @@ +#! /bin/sh -e + +prio=$(echo @BV@ | sed 's/\.//g') + +update-alternatives --quiet \ + --install /usr/bin/hppa64-linux-gnu-gcc \ + hppa64-linux-gnu-gcc \ + /usr/bin/hppa64-linux-gnu-gcc-@BV@ \ + $prio + +#DEBHELPER# + +exit 0 --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.64 +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.64 @@ -0,0 +1,2 @@ + _gfortran_clz128@GFORTRAN_1.2 4.4.0 + _gfortran_ctz128@GFORTRAN_1.2 4.4.0 --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.amd64 +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.amd64 @@ -0,0 +1,144 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4.4@GCC_3.4.4 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __absvti2@GCC_3.4.4 1:4.1.1 + __addtf3@GCC_4.3.0 1:4.3 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __addvti3@GCC_3.4.4 1:4.1.1 + __ashlti3@GCC_3.0 1:4.1.1 + __ashrti3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzti2@GCC_3.4 1:4.1.1 + __cmpti2@GCC_3.0 1:4.1.1 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzti2@GCC_3.4 1:4.1.1 + __deregister_frame@GCC_3.0 1:4.1.1 + __deregister_frame_info@GCC_3.0 1:4.1.1 + __deregister_frame_info_bases@GCC_3.0 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + __divtc3@GCC_4.0.0 1:4.3 + __divtc3@GCC_4.3.0 1:4.4.0 + __divtf3@GCC_4.3.0 1:4.3 + __divti3@GCC_3.0 1:4.1.1 + __divxc3@GCC_4.0.0 1:4.1.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 1:4.1.1 + __eqtf2@GCC_4.3.0 1:4.3 + __extenddftf2@GCC_4.3.0 1:4.3 + __extendsftf2@GCC_4.3.0 1:4.3 + __extendxftf2@GCC_4.3.0 1:4.3 + __ffsdi2@GCC_3.0 1:4.1.1 + __ffsti2@GCC_3.0 1:4.1.1 + __fixdfti@GCC_3.0 1:4.1.1 + __fixsfti@GCC_3.0 1:4.1.1 + __fixtfdi@GCC_4.3.0 1:4.3 + __fixtfsi@GCC_4.3.0 1:4.3 + __fixtfti@GCC_4.3.0 1:4.3 + __fixunsdfdi@GCC_3.0 1:4.1.1 + __fixunsdfti@GCC_3.0 1:4.1.1 + __fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfti@GCC_3.0 1:4.1.1 + __fixunstfdi@GCC_4.3.0 1:4.3 + __fixunstfsi@GCC_4.3.0 1:4.3 + __fixunstfti@GCC_4.3.0 1:4.3 + __fixunsxfdi@GCC_3.0 1:4.1.1 + __fixunsxfti@GCC_3.0 1:4.1.1 + __fixxfti@GCC_3.0 1:4.1.1 + __floatditf@GCC_4.3.0 1:4.3 + __floatsitf@GCC_4.3.0 1:4.3 + __floattidf@GCC_3.0 1:4.1.1 + __floattisf@GCC_3.0 1:4.1.1 + __floattitf@GCC_4.3.0 1:4.3 + __floattixf@GCC_3.0 1:4.1.1 + __floatunditf@GCC_4.3.0 1:4.3 + __floatunsitf@GCC_4.3.0 1:4.3 + __floatuntidf@GCC_4.2.0 1:4.2.1 + __floatuntisf@GCC_4.2.0 1:4.2.1 + __floatuntitf@GCC_4.3.0 1:4.3 + __floatuntixf@GCC_4.2.0 1:4.2.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __getf2@GCC_4.3.0 1:4.3 + __gttf2@GCC_3.0 1:4.3 + __gttf2@GCC_4.3.0 1:4.4.0 + __letf2@GCC_4.3.0 1:4.3 + __lshrti3@GCC_3.0 1:4.1.1 + __lttf2@GCC_3.0 1:4.3 + __lttf2@GCC_4.3.0 1:4.4.0 + __modti3@GCC_3.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_4.0.0 1:4.3 + __multc3@GCC_4.3.0 1:4.4.0 + __multf3@GCC_4.3.0 1:4.3 + __multi3@GCC_3.0 1:4.1.1 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __mulvti3@GCC_3.4.4 1:4.1.1 + __mulxc3@GCC_4.0.0 1:4.1.1 + __negtf2@GCC_4.3.0 1:4.3 + __negti2@GCC_3.0 1:4.1.1 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __negvti2@GCC_3.4.4 1:4.1.1 + __netf2@GCC_3.0 1:4.3 + __netf2@GCC_4.3.0 1:4.4.0 + __paritydi2@GCC_3.4 1:4.1.1 + __parityti2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountti2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_4.0.0 1:4.3 + __powitf2@GCC_4.3.0 1:4.4.0 + __powixf2@GCC_4.0.0 1:4.1.1 + __register_frame@GCC_3.0 1:4.1.1 + __register_frame_info@GCC_3.0 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GCC_3.0 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GCC_3.0 1:4.1.1 + __subtf3@GCC_4.3.0 1:4.3 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __subvti3@GCC_3.4.4 1:4.1.1 + __trunctfdf2@GCC_4.3.0 1:4.3 + __trunctfsf2@GCC_4.3.0 1:4.3 + __trunctfxf2@GCC_4.3.0 1:4.3 + __ucmpti2@GCC_3.0 1:4.1.1 + __udivmodti4@GCC_3.0 1:4.1.1 + __udivti3@GCC_3.0 1:4.1.1 + __umodti3@GCC_3.0 1:4.1.1 + __unordtf2@GCC_4.3.0 1:4.3 --- gcc-4.5-4.5.2.orig/debian/README.source +++ gcc-4.5-4.5.2/debian/README.source @@ -0,0 +1,14 @@ +Patches applied to the Debian version of GCC +-------------------------------------------- + +Debian specific patches can be found in the debian/patches directory. +Quilt is used as the patch system. See /usr/share/doc/quilt/README.source +for details about quilt. + +Patches are applied by calling `debian/rules patch'. The `series' +file is constructed on the fly, configure scripts are regenerated +in the `patch' target. + +The source packages gcj-x.y and gnat-x.y do not contain copies of the +source code but build-depend on the appropriate gcc-x.y-source package +instead. --- gcc-4.5-4.5.2.orig/debian/lib64gcc1.symbols.s390 +++ gcc-4.5-4.5.2/debian/lib64gcc1.symbols.s390 @@ -0,0 +1,107 @@ +libgcc_s.so.1 lib64gcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4.4@GCC_3.4.4 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.1.0@GCC_4.1.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GLIBC_2.2@GLIBC_2.2 1:4.1.1 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __absvti2@GCC_3.4.4 1:4.1.1 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __addvti3@GCC_3.4.4 1:4.1.1 + __ashlti3@GCC_3.0 1:4.1.1 + __ashrti3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzti2@GCC_3.4 1:4.1.1 + __cmpti2@GCC_3.0 1:4.1.1 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzti2@GCC_3.4 1:4.1.1 + __deregister_frame@GLIBC_2.2 1:4.1.1 + __deregister_frame_info@GLIBC_2.2 1:4.1.1 + __deregister_frame_info_bases@GCC_3.0 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + __divtc3@GCC_4.1.0 1:4.1.1 + __divti3@GCC_3.0 1:4.1.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 1:4.1.1 + __ffsdi2@GCC_3.0 1:4.1.1 + __ffsti2@GCC_3.0 1:4.1.1 + __fixdfti@GCC_3.0 1:4.1.1 + __fixsfti@GCC_3.0 1:4.1.1 + __fixtfti@GCC_4.1.0 1:4.1.1 + __fixunsdfdi@GCC_3.0 1:4.1.1 + __fixunsdfti@GCC_3.0 1:4.1.1 + __fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfti@GCC_3.0 1:4.1.1 + __fixunstfti@GCC_4.1.0 1:4.1.1 + __floattidf@GCC_3.0 1:4.1.1 + __floattisf@GCC_3.0 1:4.1.1 + __floattitf@GCC_4.1.0 1:4.1.1 + __floatuntidf@GCC_4.2.0 1:4.2.1 + __floatuntisf@GCC_4.2.0 1:4.2.1 + __floatuntitf@GCC_4.2.0 1:4.2.1 + __frame_state_for@GLIBC_2.2 1:4.1.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __lshrti3@GCC_3.0 1:4.1.1 + __modti3@GCC_3.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_4.1.0 1:4.1.1 + __multi3@GCC_3.0 1:4.1.1 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __mulvti3@GCC_3.4.4 1:4.1.1 + __negti2@GCC_3.0 1:4.1.1 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __negvti2@GCC_3.4.4 1:4.1.1 + __paritydi2@GCC_3.4 1:4.1.1 + __parityti2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountti2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_4.1.0 1:4.1.1 + __register_frame@GLIBC_2.2 1:4.1.1 + __register_frame_info@GLIBC_2.2 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GLIBC_2.2 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GLIBC_2.2 1:4.1.1 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __subvti3@GCC_3.4.4 1:4.1.1 + __ucmpti2@GCC_3.0 1:4.1.1 + __udivmodti4@GCC_3.0 1:4.1.1 + __udivti3@GCC_3.0 1:4.1.1 + __umodti3@GCC_3.0 1:4.1.1 --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.glibcxxmath +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.glibcxxmath @@ -0,0 +1,22 @@ + acosl@GLIBCXX_3.4.3 4.1.1 + asinl@GLIBCXX_3.4.3 4.1.1 + atan2l@GLIBCXX_3.4 4.1.1 + atanl@GLIBCXX_3.4.3 4.1.1 + ceill@GLIBCXX_3.4.3 4.1.1 + coshl@GLIBCXX_3.4 4.1.1 + cosl@GLIBCXX_3.4 4.1.1 + expl@GLIBCXX_3.4 4.1.1 + floorl@GLIBCXX_3.4.3 4.1.1 + fmodl@GLIBCXX_3.4.3 4.1.1 + frexpl@GLIBCXX_3.4.3 4.1.1 + hypotl@GLIBCXX_3.4 4.1.1 + ldexpl@GLIBCXX_3.4.3 4.1.1 + log10l@GLIBCXX_3.4 4.1.1 + logl@GLIBCXX_3.4 4.1.1 + modfl@GLIBCXX_3.4.3 4.1.1 + powl@GLIBCXX_3.4 4.1.1 + sinhl@GLIBCXX_3.4 4.1.1 + sinl@GLIBCXX_3.4 4.1.1 + sqrtl@GLIBCXX_3.4 4.1.1 + tanhl@GLIBCXX_3.4 4.1.1 + tanl@GLIBCXX_3.4 4.1.1 --- gcc-4.5-4.5.2.orig/debian/rules.patch +++ gcc-4.5-4.5.2/debian/rules.patch @@ -0,0 +1,389 @@ +# -*- makefile -*- +# rules to patch the unpacked files in the source directory +# --------------------------------------------------------------------------- +# various rules to unpack addons and (un)apply patches. +# - patch / apply-patches +# - unpatch / reverse-patches + +.NOTPARALLEL: + +patchdir ?= debian/patches +series_file ?= $(patchdir)/series + +# which patches should be applied? + +debian_patches = \ + $(if $(with_linaro_branch),gcc-linaro) \ + $(if $(with_linaro_branch),gcc-linaro-updates) \ + $(if $(with_linaro_branch),linaro-volatile-bitfield-fix) \ + $(if $(with_linaro_branch),linaro-no-shrink-wrap) \ + svn-updates$(if $(with_linaro_branch),-linaro) \ + +# svn-updates \ +# $(if $(with_linaro_branch),gcc-linaro) \ +# $(if $(with_linaro_branch),linaro-volatile-bitfield-fix) \ + + +ifeq ($(with_java),yes) +# debian_patches += \ +# svn-class-updates +endif + +ifneq ($(GFDL_INVARIANT_FREE),yes) + debian_patches += \ + rename-info-files \ + gcc-plugindir-doc \ + $(if $(with_linaro_branch),gcc-linaro-doc) \ + $(if $(with_linaro_branch),linaro-no-shrink-wrap-doc) \ + $(if $(with_linaro_branch),,svn-doc-updates) \ + +# $(if $(with_linaro_branch),gcc-linaro-doc) + +endif + +# boehm-gc-nocheck: seems to work on the buildds \ + +debian_patches += \ + gcc-textdomain \ + gcc-driver-extra-langs + +ifeq ($(distribution),Ubuntu) + ifneq (,$(filter $(distrelease),dapper hardy intrepid jaunty karmic lucid)) + debian_patches += gcc-hash-style-both + else + debian_patches += gcc-hash-style-gnu + endif +else + debian_patches += gcc-hash-style-both +endif + +debian_patches += \ + libstdc++-pic \ + libstdc++-doclink \ + libstdc++-man-3cxx \ + libstdc++-test-installed \ + libjava-stacktrace \ + libjava-subdir \ + libjava-jnipath \ + libjava-sjlj \ + libjava-disable-plugin \ + alpha-no-ev4-directive \ + boehm-gc-getnprocs \ + note-gnu-stack \ + m68k-allow-gnu99 \ + libgomp-omp_h-multilib \ + sparc-force-cpu \ + $(if $(with_linaro_branch),,pr41848) \ + gcc-plugindir \ + gcc-java-align-data \ + linux-atomic-builtin-expect \ + pr24619 \ + pr45979 \ + no_fpr_in_libgcc \ + pr44364 \ + pr48226 \ + gcc-dw2-loc-tracking \ + libobjc-gc \ + +# libstdc++-nothumb-check \ +# TODO: update +# gcc-cloog-dl \ +# TODO: update ... +# libjava-rpath \ + +debian_patches += $(if $(with_linaro_branch),,pr40521-sequel) +ifneq ($(GFDL_INVARIANT_FREE),yes) + debian_patches += $(if $(with_linaro_branch),,pr40521-sequel-doc) +endif + +hardening_patches = +ifneq ($(distribution),Debian) + ifneq (,$(findstring gcc-4, $(PKGSOURCE))) + hardening_patches += gcc-default-format-security \ + gcc-default-fortify-source \ + gcc-default-relro$(if $(with_linaro_branch),-linaro) \ + testsuite-hardening-format \ + testsuite-hardening-fortify \ + testsuite-hardening-printf-types \ + $(if $(with_linaro_branch),,libgcc-no-ssp) + endif +endif +ifeq ($(with_ssp)-$(with_ssp_default),yes-yes) + ifeq ($(distribution),Ubuntu) + hardening_patches += gcc-default-ssp$(if $(filter ppc64,$(DEB_TARGET_ARCH)),-ppc64) + else + hardening_patches += gcc-default-ssp + endif +endif + +# FIXME 4.5: Drop and adjust symbols files +ifneq (,$(findstring 4.4, $(PKGSOURCE))) + debian_patches += pr39491 +endif + +ifeq ($(with_ada),yes) + debian_patches += \ + ada-driver-check \ + ada-gcc-name \ + ada-default-project-path \ + ada-symbolic-tracebacks \ + ada-library-project-files-soname \ + ada-polyorb-dsa + + ifeq ($(biarch64),yes) + debian_patches += \ + ada-nobiarch-check + endif + + ifeq ($(with_libgnat),yes) + debian_patches += \ + ada-gnatvsn \ + ada-link-lib \ + ada-libgnatvsn \ + ada-libgnatprj \ + ada-acats + ifeq ($(with_gnat_zcx)-$(with_gnat_sjlj),yes-yes) + debian_patches += \ + ada-sjlj + endif + endif +endif + +# gcc-4.4 is not yet supported by gdc +ifeq ($(with_d),yes) +# +else +# debian_patches += gcc-d-lang +endif + +ifeq ($(DEB_TARGET_ARCH_OS),hurd) + debian_patches += hurd-pthread +endif + +ifeq ($(DEB_TARGET_ARCH),alpha) + debian_patches += alpha-ieee mudflap-nocheck + ifneq ($(GFDL_INVARIANT_FREE),yes) + debian_patches += alpha-ieee-doc + endif +endif + +ifneq (,$(findstring $(DEB_TARGET_ARCH),arm armel armhf)) + debian_patches += libjava-armel-unwind +endif + +ifeq ($(DEB_TARGET_ARCH),m68k) + debian_patches += +endif + +ifeq ($(DEB_TARGET_ARCH),powerpcspe) + debian_patches += powerpc_remove_many +endif + +ifeq ($(DEB_TARGET_ARCH),ppc64) + ifeq ($(distribution),Ubuntu) + debian_patches += ibm-branch + endif +endif + +ifeq ($(DEB_TARGET_ARCH_OS),kfreebsd) + debian_patches += kbsd-gnu +endif + +ifeq ($(DEB_CROSS),yes) + debian_patches += cross-include cross-fixes +endif + +#spu_patches = cell-branch +#ifneq ($(GFDL_INVARIANT_FREE),yes) +# spu_patches += cell-branch-doc +#endif + +#debian_patches += link-libs + +# all patches below this line are applied for gcc-snapshot builds as well + +ifeq ($(PKGSOURCE),gcc-snapshot) + spu_patches = + debian_patches = +endif + +ifeq ($(DEB_TARGET_ARCH_OS),hurd) + debian_patches += hurd-changes +endif + +ifeq ($(PKGSOURCE),gcc-snapshot) + debian_patches += gcc-ice-hack-trunk gcc-ice-apport-trunk + debian_patches += gold-and-ld-trunk +else + debian_patches += gcc-ice-hack gcc-ice-apport + #debian_patches += gold-and-ld + debian_patches += $(if $(with_linaro_branch),,gcc-arm-earlyclobbers) +endif +debian_patches += libjava-disable-static libjava-fixed-symlinks +debian_patches += libstdc++-arm-wno-abi + +ifneq (,$(filter $(DEB_TARGET_ARCH), armel mipsel)) + # timeouts on the buildd's, (armel on both Debian and Ubuntu) + debian_patches += libstdc++-no-testsuite +endif +ifneq (,$(filter $(DEB_TARGET_ARCH), hppa)) + # timeouts on the buildd's + debian_patches += libmudflap-no-testsuite +endif +debian_patches += ada-mips + +ifeq ($(distribution),Debian) + debian_patches += arm-unbreak-eabi-armv4t +endif + +ifeq ($(PKGSOURCE),gcc-snapshot) + debian_patches += gcc-multiarch-trunk +else + debian_patches += gcc-multiarch$(if $(with_linaro_branch),-linaro) +endif +debian_patches += mips-triarch +debian_patches += libjava-nobiarch-check +debian_patches += config-ml +ifeq ($(biarch64),yes) + ifeq ($(DEB_CROSS),yes) + debian_patches += cross-biarch + endif +endif +debian_patches += s390-biarch +debian_patches += gcc-powerpc-nof +debian_patches += gcc-powerpc-undef +ifeq ($(with_multiarch_lib),yes) + debian_patches += gcc-multiarch+biarch + ifeq ($(biarch32),yes) + debian_patches += gcc-multiarch+biarch32 + endif + ifneq (,$(findstring sparc64,$(DEB_TARGET_ARCH))) + debian_patches += gcc-multiarch+biarch32 + endif +else + ifeq ($(biarch32),yes) + debian_patches += gcc-multilib64 + endif +endif +ifeq (,$(filter $(distrelease),lenny squeeze dapper hardy intrepid jaunty karmic lucid maverick natty)) + debian_patches += gcc-no-add-needed +endif +ifeq (,$(filter $(distrelease),lenny squeeze wheezy sid experimental dapper hardy intrepid jaunty karmic lucid maverick natty)) + debian_patches += gcc-as-needed +endif +debian_patches += mips-fix-loongson2f-nop +ifeq ($(distribution),Ubuntu) + ifeq ($(DEB_TARGET_ARCH),ppc64) + no_spu_patches += gcc-ppc64-O3 + endif +endif +debian_patches += $(no_spu_patches) +debian_patches += gcc-system-root + +debian_patches += armhf-triplet-backport + + +series_stamp = $(stampdir)/02-series-stamp +series: $(series_stamp) +$(series_stamp): + echo $(strip $(addsuffix .diff,$(debian_patches))) \ + | sed -r 's/ +/ /g' | tr " " "\n" > $(series_file) +ifneq (,$(strip $(hardening_patches))) + ifneq ($(DEB_CROSS),yes) + ifneq ($(PKGSOURCE),gcc-snapshot) + echo $(strip $(addsuffix .diff,$(hardening_patches))) \ + | sed -r 's/ +/ /g' | tr " " "\n" >> $(series_file) + endif + endif +endif + sed -r 's/(.)$$/\1 -p1/' -i $(series_file) + touch $@ + +autotools_files := $(addprefix ./,$(foreach file,$(shell lsdiff --no-filename \ + $(foreach patch,$(debian_patches),$(patchdir)/$(patch).diff) \ + | sed -r 's/[ab]\/src\//src\//' | sort | uniq),$(shell echo $(file) \ + | egrep 'configure\.(ac|in)|Makefile\.(am|in)|acinclude.m4'))) + +autoconf_version = 2.64 +ifeq ($(PKGSOURCE),gcc-snapshot) + # The actual version depends on the build-dependencies set by + # variable AUTO_BUILD_DEP in rules.conf. Here, we assume the + # correct version is installed. + #autoconf_version = +endif + +# FIXME: the auto* stuff is done every time for every subdir, which +# leads to build errors. Idea: record the auto* calls in the patch +# files (AUTO ) and run them separately, +# maybe only once per directory). +$(patch_stamp): $(unpack_stamp) $(series_stamp) + QUILT_PATCHES=$(patchdir) \ + quilt --quiltrc /dev/null push -a || test $$? = 2 + +ifneq (,$(filter svn-updates, $(debian_patches))) + awk '/^EOF/ {exit} p==1 {print} /EOF$$/ {p=1}' \ + $(patchdir)/svn-updates.diff > src/LAST_UPDATED +endif + + if ! test -f ./autotools_files ; then touch ./autotools_files ; fi + + cd $(srcdir)/fixincludes && ./genfixes + + for f in $(autotools_files) ; \ + do case $$f in \ + */classpath/m4/acinclude.m4) \ + : ;; \ + */configure.*|*/acinclude.m4) \ + if grep ^"$$(md5sum $$f)"$$ ./autotools_files >/dev/null ; \ + then echo "Skipping already regenerated file $$f." ; \ + else \ + echo "Running autoconf$(autoconf_version) in $$(dirname $$f)..." ; \ + dir="$(CURDIR)"; cd $(CURDIR)/$$(dirname $$f) \ + && AUTOM4TE=/usr/bin/autom4te$(autoconf_version) autoconf$(autoconf_version) \ + && cd $$dir \ + && echo "$$(md5sum $$f)" >> ./autotools_files ; \ + fi ;; \ + */Makefile.*) ;; \ + *) echo "Unknown file: $$f"; false; \ + esac; \ + done + + for i in $(debian_patches); do \ + echo -e "\n$$i:" >> pxxx; \ + sed -n 's/^# *DP: */ /p' $(patchdir)/$$i.diff >> pxxx; \ + done +# -$(srcdir)/move-if-change pxxx $@ + mv pxxx $@ + +unpatch: + QUILT_PATCHES=$(patchdir) \ + quilt --quiltrc /dev/null pop -a -R || test $$? = 2 + rm -rf .pc + for f in $(autotools_files); do \ + rm -f $$(echo $$f | sed -r 's/\.(ac|am|in)$$//'); \ + done + +$(src_spu_stamp): $(patch_stamp) + rm -rf src-spu +ifeq (,$(strip $(hardening_patches) $(no_spu_patches))) + ln -s src src-spu +else + cp -a src src-spu + set -e; \ + for p in $(no_spu_patches) $(hardening_patches); do \ + list="$$p $$list"; \ + done; \ + for p in $$list; do \ + echo "Revert for spu build: $$p"; \ + patch -d src-spu -p2 -R < debian/patches/$$p.diff; \ + done +endif + set -e; \ + for p in $(spu_patches); do \ + echo "Apply for spu build: $$p"; \ + patch -d src-spu -p2 < debian/patches/$$p.diff; \ + done + touch $@ + +patch: $(patch_stamp) +.PHONY: patch series quilt autotools --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.sparc +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.sparc @@ -0,0 +1,8 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" +#include "libstdc++6.symbols.excprop" + __gxx_personality_v0@CXXABI_1.3 4.1.1 +#include "libstdc++6.symbols.glibcxxmath" +#include "libstdc++6.symbols.ldbl.32bit" + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2 --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.excprop +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.excprop @@ -0,0 +1,17 @@ + _ZNKSt15__exception_ptr13exception_ptr20__cxa_exception_typeEv@CXXABI_1.3.3 4.4.0 + _ZNKSt15__exception_ptr13exception_ptrcvMS0_FvvEEv@CXXABI_1.3.3 4.4.0 + _ZNKSt15__exception_ptr13exception_ptrntEv@CXXABI_1.3.3 4.4.0 + _ZNSt15__exception_ptr13exception_ptr4swapERS0_@CXXABI_1.3.3 4.4.0 + _ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE@CXXABI_1.3.3 4.4.0 + _ZNSt15__exception_ptr13exception_ptrC1ERKS0_@CXXABI_1.3.3 4.4.0 + _ZNSt15__exception_ptr13exception_ptrC1Ev@CXXABI_1.3.3 4.4.0 + _ZNSt15__exception_ptr13exception_ptrC2EMS0_FvvE@CXXABI_1.3.3 4.4.0 + _ZNSt15__exception_ptr13exception_ptrC2ERKS0_@CXXABI_1.3.3 4.4.0 + _ZNSt15__exception_ptr13exception_ptrC2Ev@CXXABI_1.3.3 4.4.0 + _ZNSt15__exception_ptr13exception_ptrD1Ev@CXXABI_1.3.3 4.4.0 + _ZNSt15__exception_ptr13exception_ptrD2Ev@CXXABI_1.3.3 4.4.0 + _ZNSt15__exception_ptr13exception_ptraSERKS0_@CXXABI_1.3.3 4.4.0 + _ZNSt15__exception_ptreqERKNS_13exception_ptrES2_@CXXABI_1.3.3 4.4.0 + _ZNSt15__exception_ptrneERKNS_13exception_ptrES2_@CXXABI_1.3.3 4.4.0 + _ZSt17current_exceptionv@CXXABI_1.3.3 4.4.0 + _ZSt17rethrow_exceptionNSt15__exception_ptr13exception_ptrE@CXXABI_1.3.3 4.4.0 --- gcc-4.5-4.5.2.orig/debian/source.lintian-overrides +++ gcc-4.5-4.5.2/debian/source.lintian-overrides @@ -0,0 +1,2 @@ +gcc-4.5: invalid-arch-string-in-source-relation +gcc-4.5: quilt-build-dep-but-no-series-file --- gcc-4.5-4.5.2.orig/debian/lib32gomp1.symbols +++ gcc-4.5-4.5.2/debian/lib32gomp1.symbols @@ -0,0 +1,4 @@ +libgomp.so.1 lib32gomp1 #MINVER# +#include "libgomp1.symbols.common" + GOMP_atomic_end@GOMP_1.0 4.2.1 + GOMP_atomic_start@GOMP_1.0 4.2.1 --- gcc-4.5-4.5.2.orig/debian/rules.source +++ gcc-4.5-4.5.2/debian/rules.source @@ -0,0 +1,15 @@ +SOURCE_DIR := $(dir $(lastword $(MAKEFILE_LIST))) +patchdir = $(SOURCE_DIR)/patches + +include $(SOURCE_DIR)/debian/rules.defs +include $(SOURCE_DIR)/debian/rules.patch +include $(SOURCE_DIR)/debian/rules.unpack + +patch-source: $(patch_stamp) + +clean-source: + rm -rf $(stampdir) + rm -rf $(gcc_srcdir) $(gdc_srcdir) d + rm -rf bin + rm -rf $(srcdir) + --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.hurd-i386 +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.hurd-i386 @@ -0,0 +1,5 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit.hurd" + __gxx_personality_v0@CXXABI_1.3 4.1.1 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0 --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.16.powerpc +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.16.powerpc @@ -0,0 +1,96 @@ + __iso_c_binding_c_f_pointer_c16@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_r16@GFORTRAN_1.0 4.3 + _gfortran_arandom_r16@GFORTRAN_1.0 4.3 + _gfortran_cpu_time_16@GFORTRAN_1.0 4.3 + _gfortran_erfc_scaled_r16@GFORTRAN_1.1 4.4.0 + _gfortran_exponent_r16@GFORTRAN_1.0 4.3 + _gfortran_fraction_r16@GFORTRAN_1.0 4.3 + _gfortran_matmul_c16@GFORTRAN_1.0 4.3 + _gfortran_matmul_r16@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_4_r16@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_8_r16@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_4_r16@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_8_r16@GFORTRAN_1.0 4.3 + _gfortran_maxval_r16@GFORTRAN_1.0 4.3 + _gfortran_minloc0_4_r16@GFORTRAN_1.0 4.3 + _gfortran_minloc0_8_r16@GFORTRAN_1.0 4.3 + _gfortran_minloc1_4_r16@GFORTRAN_1.0 4.3 + _gfortran_minloc1_8_r16@GFORTRAN_1.0 4.3 + _gfortran_minval_r16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_4_r16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_8_r16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_4_r16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_8_r16@GFORTRAN_1.0 4.3 + _gfortran_mmaxval_r16@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_4_r16@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_8_r16@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_4_r16@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_8_r16@GFORTRAN_1.0 4.3 + _gfortran_mminval_r16@GFORTRAN_1.0 4.3 + _gfortran_mproduct_c16@GFORTRAN_1.0 4.3 + _gfortran_mproduct_r16@GFORTRAN_1.0 4.3 + _gfortran_msum_c16@GFORTRAN_1.0 4.3 + _gfortran_msum_r16@GFORTRAN_1.0 4.3 + _gfortran_nearest_r16@GFORTRAN_1.0 4.3 + _gfortran_pow_c16_i4@GFORTRAN_1.0 4.3 + _gfortran_pow_c16_i8@GFORTRAN_1.0 4.3 + _gfortran_pow_r16_i8@GFORTRAN_1.0 4.3 + _gfortran_product_c16@GFORTRAN_1.0 4.3 + _gfortran_product_r16@GFORTRAN_1.0 4.3 + _gfortran_random_r16@GFORTRAN_1.0 4.3 + _gfortran_reshape_c16@GFORTRAN_1.0 4.3 + _gfortran_reshape_r16@GFORTRAN_1.0 4.3 + _gfortran_rrspacing_r16@GFORTRAN_1.0 4.3 + _gfortran_set_exponent_r16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_4_r16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_8_r16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_4_r16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_8_r16@GFORTRAN_1.0 4.3 + _gfortran_smaxval_r16@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_4_r16@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_8_r16@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_4_r16@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_8_r16@GFORTRAN_1.0 4.3 + _gfortran_sminval_r16@GFORTRAN_1.0 4.3 + _gfortran_spacing_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__abs_c16@GFORTRAN_1.0 4.3 + _gfortran_specific__abs_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__acos_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__acosh_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__aimag_c16@GFORTRAN_1.0 4.3 + _gfortran_specific__aint_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__anint_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__asin_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__asinh_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__atan2_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__atan_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__atanh_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__conjg_16@GFORTRAN_1.0 4.3 + _gfortran_specific__cos_c16@GFORTRAN_1.0 4.3 + _gfortran_specific__cos_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__cosh_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__dim_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__exp_c16@GFORTRAN_1.0 4.3 + _gfortran_specific__exp_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__log10_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__log_c16@GFORTRAN_1.0 4.3 + _gfortran_specific__log_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__mod_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__nint_4_16@GFORTRAN_1.0 4.3 + _gfortran_specific__nint_8_16@GFORTRAN_1.0 4.3 + _gfortran_specific__sign_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__sin_c16@GFORTRAN_1.0 4.3 + _gfortran_specific__sin_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__sinh_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__sqrt_c16@GFORTRAN_1.0 4.3 + _gfortran_specific__sqrt_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__tan_r16@GFORTRAN_1.0 4.3 + _gfortran_specific__tanh_r16@GFORTRAN_1.0 4.3 + _gfortran_sproduct_c16@GFORTRAN_1.0 4.3 + _gfortran_sproduct_r16@GFORTRAN_1.0 4.3 + _gfortran_ssum_c16@GFORTRAN_1.0 4.3 + _gfortran_ssum_r16@GFORTRAN_1.0 4.3 + _gfortran_sum_c16@GFORTRAN_1.0 4.3 + _gfortran_sum_r16@GFORTRAN_1.0 4.3 + _gfortran_transpose_c16@GFORTRAN_1.0 4.3 + _gfortran_transpose_r16@GFORTRAN_1.0 4.3 --- gcc-4.5-4.5.2.orig/debian/libstdc++CXX-BV-doc.doc-base +++ gcc-4.5-4.5.2/debian/libstdc++CXX-BV-doc.doc-base @@ -0,0 +1,13 @@ +Document: libstdc++@CXX@-@BV@-doc +Title: The GNU Standard C++ Library v3 (gcc-@BV@) +Author: Various +Abstract: This package contains documentation files for the GNU stdc++ library. + One set is the distribution documentation, the other set is the + source documentation including a namespace list, class hierarchy, + alphabetical list, compound list, file list, namespace members, + compound members and file members. +Section: Programming/C++ + +Format: html +Index: /usr/share/doc/libstdc++@CXX@-@BV@-doc/libstdc++/html/index.html +Files: /usr/share/doc/libstdc++@CXX@-@BV@-doc/libstdc++/html*/* --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.16.powerpc64 +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.16.powerpc64 @@ -0,0 +1,178 @@ + __iso_c_binding_c_f_pointer_i16@GFORTRAN_1.0 4.3 + _gfortran_all_l16@GFORTRAN_1.0 4.3 + _gfortran_any_l16@GFORTRAN_1.0 4.3 + _gfortran_count_16_l@GFORTRAN_1.0 4.3 + _gfortran_cshift0_16@GFORTRAN_1.1 4.4.0 + _gfortran_cshift0_16_char@GFORTRAN_1.1 4.4.0 + _gfortran_cshift1_16@GFORTRAN_1.0 4.3 + _gfortran_cshift1_16_char4@GFORTRAN_1.1 4.4.0 + _gfortran_cshift1_16_char@GFORTRAN_1.0 4.3 + _gfortran_eoshift0_16@GFORTRAN_1.1 4.4.0 + _gfortran_eoshift0_16_char@GFORTRAN_1.1 4.4.0 + _gfortran_eoshift1_16@GFORTRAN_1.0 4.3 + _gfortran_eoshift1_16_char4@GFORTRAN_1.1 4.4.0 + _gfortran_eoshift1_16_char@GFORTRAN_1.0 4.3 + _gfortran_eoshift2_16@GFORTRAN_1.1 4.4.0 + _gfortran_eoshift2_16_char@GFORTRAN_1.1 4.4.0 + _gfortran_eoshift3_16@GFORTRAN_1.0 4.3 + _gfortran_eoshift3_16_char4@GFORTRAN_1.1 4.4.0 + _gfortran_eoshift3_16_char@GFORTRAN_1.0 4.3 + _gfortran_ishftc16@GFORTRAN_1.0 4.3 + _gfortran_matmul_i16@GFORTRAN_1.0 4.3 + _gfortran_matmul_l16@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_i16@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_i1@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_i2@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_i4@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_i8@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_r16@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_r4@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_16_r8@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_4_i16@GFORTRAN_1.0 4.3 + _gfortran_maxloc0_8_i16@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_i16@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_i1@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_i2@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_i4@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_i8@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_r16@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_r4@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_16_r8@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_4_i16@GFORTRAN_1.0 4.3 + _gfortran_maxloc1_8_i16@GFORTRAN_1.0 4.3 + _gfortran_maxval_i16@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_i16@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_i1@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_i2@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_i4@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_i8@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_r16@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_r4@GFORTRAN_1.0 4.3 + _gfortran_minloc0_16_r8@GFORTRAN_1.0 4.3 + _gfortran_minloc0_4_i16@GFORTRAN_1.0 4.3 + _gfortran_minloc0_8_i16@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_i16@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_i1@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_i2@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_i4@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_i8@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_r16@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_r4@GFORTRAN_1.0 4.3 + _gfortran_minloc1_16_r8@GFORTRAN_1.0 4.3 + _gfortran_minloc1_4_i16@GFORTRAN_1.0 4.3 + _gfortran_minloc1_8_i16@GFORTRAN_1.0 4.3 + _gfortran_minval_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_i1@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_i2@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_i4@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_i8@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_r16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_r4@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_16_r8@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_4_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc0_8_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_i1@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_i2@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_i4@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_i8@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_r16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_r4@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_16_r8@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_4_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxloc1_8_i16@GFORTRAN_1.0 4.3 + _gfortran_mmaxval_i16@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_i16@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_i1@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_i2@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_i4@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_i8@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_r16@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_r4@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_16_r8@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_4_i16@GFORTRAN_1.0 4.3 + _gfortran_mminloc0_8_i16@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_i16@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_i1@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_i2@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_i4@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_i8@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_r16@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_r4@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_16_r8@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_4_i16@GFORTRAN_1.0 4.3 + _gfortran_mminloc1_8_i16@GFORTRAN_1.0 4.3 + _gfortran_mminval_i16@GFORTRAN_1.0 4.3 + _gfortran_mproduct_i16@GFORTRAN_1.0 4.3 + _gfortran_msum_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_c16_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_c4_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_c8_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_i16_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_i16_i4@GFORTRAN_1.0 4.3 + _gfortran_pow_i16_i8@GFORTRAN_1.0 4.3 + _gfortran_pow_i4_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_i8_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_r16_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_r4_i16@GFORTRAN_1.0 4.3 + _gfortran_pow_r8_i16@GFORTRAN_1.0 4.3 + _gfortran_product_i16@GFORTRAN_1.0 4.3 + _gfortran_reshape_16@GFORTRAN_1.0 4.3 + _gfortran_shape_16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_i16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_i1@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_i2@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_i4@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_i8@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_r16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_r4@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_16_r8@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_4_i16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc0_8_i16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_i16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_i1@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_i2@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_i4@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_i8@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_r16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_r4@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_16_r8@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_4_i16@GFORTRAN_1.0 4.3 + _gfortran_smaxloc1_8_i16@GFORTRAN_1.0 4.3 + _gfortran_smaxval_i16@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_i16@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_i1@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_i2@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_i4@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_i8@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_r16@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_r4@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_16_r8@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_4_i16@GFORTRAN_1.0 4.3 + _gfortran_sminloc0_8_i16@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_i16@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_i1@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_i2@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_i4@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_i8@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_r16@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_r4@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_16_r8@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_4_i16@GFORTRAN_1.0 4.3 + _gfortran_sminloc1_8_i16@GFORTRAN_1.0 4.3 + _gfortran_sminval_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__abs_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__char_1_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__dim_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__index_1_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__len_1_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__mod_i16@GFORTRAN_1.0 4.3 + _gfortran_specific__nint_16_16@GFORTRAN_1.0 4.3 + _gfortran_specific__nint_16_4@GFORTRAN_1.0 4.3 + _gfortran_specific__nint_16_8@GFORTRAN_1.0 4.3 + _gfortran_specific__sign_i16@GFORTRAN_1.0 4.3 + _gfortran_sproduct_i16@GFORTRAN_1.0 4.3 + _gfortran_ssum_i16@GFORTRAN_1.0 4.3 + _gfortran_sum_i16@GFORTRAN_1.0 4.3 + _gfortran_transpose_i16@GFORTRAN_1.0 4.3 --- gcc-4.5-4.5.2.orig/debian/gcj-BV-jre-headless.prerm +++ gcc-4.5-4.5.2/debian/gcj-BV-jre-headless.prerm @@ -0,0 +1,13 @@ +#! /bin/sh -e + +if [ "$1" = "remove" ] || [ "$1" = "deconfigure" ]; then + update-alternatives --quiet --remove java /usr/bin/gij-@BV@ + update-alternatives --quiet --remove rmiregistry /usr/bin/grmiregistry-@BV@ + update-alternatives --quiet --remove keytool /usr/bin/gkeytool-@BV@ + update-alternatives --quiet --remove orbd /usr/bin/gorbd-@BV@ + update-alternatives --quiet --remove rmid /usr/bin/grmid-@BV@ +fi + +#DEBHELPER# + +exit 0 --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.sh4 +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.sh4 @@ -0,0 +1,2 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" --- gcc-4.5-4.5.2.orig/debian/libgcc2.symbols.m68k +++ gcc-4.5-4.5.2/debian/libgcc2.symbols.m68k @@ -0,0 +1,157 @@ +libgcc_s.so.2 libgcc2 #MINVER# + GCC_3.0@GCC_3.0 4.2.1 + GCC_3.3.1@GCC_3.3.1 4.2.1 + GCC_3.3.4@GCC_3.3.4 4.4.5 + GCC_3.3@GCC_3.3 4.2.1 + GCC_3.4.2@GCC_3.4.2 4.2.1 + GCC_3.4@GCC_3.4 4.2.1 + GCC_4.0.0@GCC_4.0.0 4.2.1 + GCC_4.2.0@GCC_4.2.0 4.2.1 + GCC_4.3.0@GCC_4.3.0 4.3.0 + GLIBC_2.0@GLIBC_2.0 4.2.1 + _Unwind_Backtrace@GCC_3.3 4.2.1 + _Unwind_DeleteException@GCC_3.0 4.2.1 + _Unwind_FindEnclosingFunction@GCC_3.3 4.2.1 + _Unwind_Find_FDE@GCC_3.0 4.2.1 + _Unwind_ForcedUnwind@GCC_3.0 4.2.1 + _Unwind_GetCFA@GCC_3.3 4.2.1 + _Unwind_GetDataRelBase@GCC_3.0 4.2.1 + _Unwind_GetGR@GCC_3.0 4.2.1 + _Unwind_GetIP@GCC_3.0 4.2.1 + _Unwind_GetIPInfo@GCC_4.2.0 4.2.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 4.2.1 + _Unwind_GetRegionStart@GCC_3.0 4.2.1 + _Unwind_GetTextRelBase@GCC_3.0 4.2.1 + _Unwind_RaiseException@GCC_3.0 4.2.1 + _Unwind_Resume@GCC_3.0 4.2.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 4.2.1 + _Unwind_SetGR@GCC_3.0 4.2.1 + _Unwind_SetIP@GCC_3.0 4.2.1 + __absvdi2@GCC_3.0 4.2.1 + __absvsi2@GCC_3.0 4.2.1 + __adddf3@GCC_3.0 4.4.5 + __addsf3@GCC_3.0 4.4.5 + __addvdi3@GCC_3.0 4.2.1 + __addvsi3@GCC_3.0 4.2.1 + __addxf3@GCC_3.0 4.4.5 + __ashldi3@GCC_3.0 4.2.1 + __ashrdi3@GCC_3.0 4.2.1 + __bswapdi2@GCC_4.3.0 4.3.0 + __bswapsi2@GCC_4.3.0 4.3.0 + __clear_cache@GCC_3.0 4.2.1 + __clzdi2@GCC_3.4 4.2.1 + __clzsi2@GCC_3.4 4.2.1 + __cmpdi2@GCC_3.0 4.2.1 + __ctzdi2@GCC_3.4 4.2.1 + __ctzsi2@GCC_3.4 4.2.1 + __deregister_frame@GLIBC_2.0 4.2.1 + __deregister_frame_info@GLIBC_2.0 4.2.1 + __deregister_frame_info_bases@GCC_3.0 4.2.1 + __divdc3@GCC_4.0.0 4.2.1 + __divdf3@GCC_3.0 4.4.5 + __divdi3@GLIBC_2.0 4.2.1 + __divsc3@GCC_4.0.0 4.2.1 + __divsf3@GCC_3.0 4.4.5 + __divsi3@GCC_3.0 4.4.5 + __divxc3@GCC_4.0.0 4.2.1 + __divxf3@GCC_3.0 4.4.5 + __emutls_get_address@GCC_4.3.0 4.3.0 + __emutls_register_common@GCC_4.3.0 4.3.0 + __enable_execute_stack@GCC_3.4.2 4.2.1 + __eqdf2@GCC_3.0 4.4.5 + __eqsf2@GCC_3.0 4.4.5 + __eqxf2@GCC_3.0 4.4.5 + __extenddfxf2@GCC_3.0 4.4.5 + __extendsfdf2@GCC_3.0 4.4.5 + __extendsfxf2@GCC_3.0 4.4.5 + __ffsdi2@GCC_3.0 4.2.1 + __ffssi2@GCC_4.3.0 4.3.0 + __fixdfdi@GCC_3.0 4.2.1 + __fixdfsi@GCC_3.0 4.4.5 + __fixsfdi@GCC_3.0 4.2.1 + __fixsfsi@GCC_3.0 4.4.5 + __fixunsdfdi@GCC_3.0 4.2.1 + __fixunsdfsi@GCC_3.0 4.2.1 + __fixunssfdi@GCC_3.0 4.2.1 + __fixunssfsi@GCC_3.0 4.2.1 + __fixunsxfdi@GCC_3.0 4.2.1 + __fixunsxfsi@GCC_3.0 4.2.1 + __fixxfdi@GCC_3.0 4.2.1 + __fixxfsi@GCC_3.0 4.4.5 + __floatdidf@GCC_3.0 4.2.1 + __floatdisf@GCC_3.0 4.2.1 + __floatdixf@GCC_3.0 4.2.1 + __floatsidf@GCC_3.0 4.4.5 + __floatsisf@GCC_3.0 4.4.5 + __floatsixf@GCC_3.0 4.4.5 + __floatundidf@GCC_4.2.0 4.2.1 + __floatundisf@GCC_4.2.0 4.2.1 + __floatundixf@GCC_4.2.0 4.2.1 + __floatunsidf@GCC_4.2.0 4.4.5 + __floatunsisf@GCC_4.2.0 4.4.5 + __floatunsixf@GCC_4.2.0 4.4.5 + __frame_state_for@GLIBC_2.0 4.2.1 + __gcc_personality_v0@GCC_3.3.1 4.2.1 + __gedf2@GCC_3.0 4.4.5 + __gesf2@GCC_3.0 4.4.5 + __gexf2@GCC_3.0 4.4.5 + __gtdf2@GCC_3.0 4.4.5 + __gtsf2@GCC_3.0 4.4.5 + __gtxf2@GCC_3.0 4.4.5 + __ledf2@GCC_3.0 4.4.5 + __lesf2@GCC_3.0 4.4.5 + __lexf2@GCC_3.0 4.4.5 + __lshrdi3@GCC_3.0 4.2.1 + __ltdf2@GCC_3.0 4.4.5 + __ltsf2@GCC_3.0 4.4.5 + __ltxf2@GCC_3.0 4.4.5 + __moddi3@GLIBC_2.0 4.2.1 + __modsi3@GCC_3.0 4.4.5 + __muldc3@GCC_4.0.0 4.2.1 + __muldf3@GCC_3.0 4.4.5 + __muldi3@GCC_3.0 4.2.1 + __mulsc3@GCC_4.0.0 4.2.1 + __mulsf3@GCC_3.0 4.4.5 + __mulsi3@GCC_3.0 4.4.5 + __mulvdi3@GCC_3.0 4.2.1 + __mulvsi3@GCC_3.0 4.2.1 + __mulxc3@GCC_4.0.0 4.2.1 + __mulxf3@GCC_3.0 4.4.5 + __nedf2@GCC_3.0 4.4.5 + __negdf2@GCC_3.0 4.4.5 + __negdi2@GCC_3.0 4.2.1 + __negsf2@GCC_3.0 4.4.5 + __negvdi2@GCC_3.0 4.2.1 + __negvsi2@GCC_3.0 4.2.1 + __negxf2@GCC_3.0 4.4.5 + __nesf2@GCC_3.0 4.4.5 + __nexf2@GCC_3.0 4.4.5 + __paritydi2@GCC_3.4 4.2.1 + __paritysi2@GCC_3.4 4.2.1 + __popcountdi2@GCC_3.4 4.2.1 + __popcountsi2@GCC_3.4 4.2.1 + __powidf2@GCC_4.0.0 4.2.1 + __powisf2@GCC_4.0.0 4.2.1 + __powixf2@GCC_4.0.0 4.2.1 + __register_frame@GLIBC_2.0 4.2.1 + __register_frame_info@GLIBC_2.0 4.2.1 + __register_frame_info_bases@GCC_3.0 4.2.1 + __register_frame_info_table@GLIBC_2.0 4.2.1 + __register_frame_info_table_bases@GCC_3.0 4.2.1 + __register_frame_table@GLIBC_2.0 4.2.1 + __subdf3@GCC_3.0 4.4.5 + __subsf3@GCC_3.0 4.4.5 + __subvdi3@GCC_3.0 4.2.1 + __subvsi3@GCC_3.0 4.2.1 + __subxf3@GCC_3.0 4.4.5 + __truncdfsf2@GCC_3.0 4.4.5 + __truncxfdf2@GCC_3.0 4.4.5 + __truncxfsf2@GCC_3.0 4.4.5 + __ucmpdi2@GCC_3.0 4.2.1 + __udivdi3@GLIBC_2.0 4.2.1 + __udivmoddi4@GCC_3.0 4.2.1 + __udivsi3@GCC_3.0 4.4.5 + __umoddi3@GLIBC_2.0 4.2.1 + __umodsi3@GCC_3.0 4.4.5 + __unorddf2@GCC_3.3.4 4.4.5 + __unordsf2@GCC_3.3.4 4.4.5 --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.mipsel +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.mipsel @@ -0,0 +1,1219 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3.4@GCC_3.3.4 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + 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1:4.3 + __satfractsqda@GCC_4.3.0 1:4.3 + __satfractsqdq2@GCC_4.3.0 1:4.3 + __satfractsqha@GCC_4.3.0 1:4.3 + __satfractsqhq2@GCC_4.3.0 1:4.3 + __satfractsqqq2@GCC_4.3.0 1:4.3 + __satfractsqsa@GCC_4.3.0 1:4.3 + __satfractsquda@GCC_4.3.0 1:4.3 + __satfractsqudq@GCC_4.3.0 1:4.3 + __satfractsquha@GCC_4.3.0 1:4.3 + __satfractsquhq@GCC_4.3.0 1:4.3 + __satfractsquqq@GCC_4.3.0 1:4.3 + __satfractsqusa@GCC_4.3.0 1:4.3 + __satfractsqusq@GCC_4.3.0 1:4.3 + __satfractudada@GCC_4.3.0 1:4.3 + __satfractudadq@GCC_4.3.0 1:4.3 + __satfractudaha@GCC_4.3.0 1:4.3 + __satfractudahq@GCC_4.3.0 1:4.3 + __satfractudaqq@GCC_4.3.0 1:4.3 + __satfractudasa@GCC_4.3.0 1:4.3 + __satfractudasq@GCC_4.3.0 1:4.3 + __satfractudaudq@GCC_4.3.0 1:4.3 + __satfractudauha2@GCC_4.3.0 1:4.3 + __satfractudauhq@GCC_4.3.0 1:4.3 + __satfractudauqq@GCC_4.3.0 1:4.3 + __satfractudausa2@GCC_4.3.0 1:4.3 + __satfractudausq@GCC_4.3.0 1:4.3 + __satfractudqda@GCC_4.3.0 1:4.3 + __satfractudqdq@GCC_4.3.0 1:4.3 + __satfractudqha@GCC_4.3.0 1:4.3 + __satfractudqhq@GCC_4.3.0 1:4.3 + __satfractudqqq@GCC_4.3.0 1:4.3 + __satfractudqsa@GCC_4.3.0 1:4.3 + __satfractudqsq@GCC_4.3.0 1:4.3 + __satfractudquda@GCC_4.3.0 1:4.3 + __satfractudquha@GCC_4.3.0 1:4.3 + __satfractudquhq2@GCC_4.3.0 1:4.3 + __satfractudquqq2@GCC_4.3.0 1:4.3 + __satfractudqusa@GCC_4.3.0 1:4.3 + __satfractudqusq2@GCC_4.3.0 1:4.3 + __satfractuhada@GCC_4.3.0 1:4.3 + __satfractuhadq@GCC_4.3.0 1:4.3 + __satfractuhaha@GCC_4.3.0 1:4.3 + __satfractuhahq@GCC_4.3.0 1:4.3 + __satfractuhaqq@GCC_4.3.0 1:4.3 + __satfractuhasa@GCC_4.3.0 1:4.3 + __satfractuhasq@GCC_4.3.0 1:4.3 + __satfractuhauda2@GCC_4.3.0 1:4.3 + __satfractuhaudq@GCC_4.3.0 1:4.3 + __satfractuhauhq@GCC_4.3.0 1:4.3 + __satfractuhauqq@GCC_4.3.0 1:4.3 + __satfractuhausa2@GCC_4.3.0 1:4.3 + __satfractuhausq@GCC_4.3.0 1:4.3 + __satfractuhqda@GCC_4.3.0 1:4.3 + __satfractuhqdq@GCC_4.3.0 1:4.3 + __satfractuhqha@GCC_4.3.0 1:4.3 + __satfractuhqhq@GCC_4.3.0 1:4.3 + __satfractuhqqq@GCC_4.3.0 1:4.3 + __satfractuhqsa@GCC_4.3.0 1:4.3 + __satfractuhqsq@GCC_4.3.0 1:4.3 + __satfractuhquda@GCC_4.3.0 1:4.3 + __satfractuhqudq2@GCC_4.3.0 1:4.3 + __satfractuhquha@GCC_4.3.0 1:4.3 + __satfractuhquqq2@GCC_4.3.0 1:4.3 + __satfractuhqusa@GCC_4.3.0 1:4.3 + __satfractuhqusq2@GCC_4.3.0 1:4.3 + __satfractunsdida@GCC_4.3.0 1:4.3 + __satfractunsdidq@GCC_4.3.0 1:4.3 + __satfractunsdiha@GCC_4.3.0 1:4.3 + __satfractunsdihq@GCC_4.3.0 1:4.3 + __satfractunsdiqq@GCC_4.3.0 1:4.3 + __satfractunsdisa@GCC_4.3.0 1:4.3 + __satfractunsdisq@GCC_4.3.0 1:4.3 + __satfractunsdiuda@GCC_4.3.0 1:4.3 + __satfractunsdiudq@GCC_4.3.0 1:4.3 + __satfractunsdiuha@GCC_4.3.0 1:4.3 + __satfractunsdiuhq@GCC_4.3.0 1:4.3 + __satfractunsdiuqq@GCC_4.3.0 1:4.3 + __satfractunsdiusa@GCC_4.3.0 1:4.3 + __satfractunsdiusq@GCC_4.3.0 1:4.3 + __satfractunshida@GCC_4.3.0 1:4.3 + __satfractunshidq@GCC_4.3.0 1:4.3 + __satfractunshiha@GCC_4.3.0 1:4.3 + __satfractunshihq@GCC_4.3.0 1:4.3 + __satfractunshiqq@GCC_4.3.0 1:4.3 + __satfractunshisa@GCC_4.3.0 1:4.3 + __satfractunshisq@GCC_4.3.0 1:4.3 + __satfractunshiuda@GCC_4.3.0 1:4.3 + __satfractunshiudq@GCC_4.3.0 1:4.3 + __satfractunshiuha@GCC_4.3.0 1:4.3 + __satfractunshiuhq@GCC_4.3.0 1:4.3 + __satfractunshiuqq@GCC_4.3.0 1:4.3 + __satfractunshiusa@GCC_4.3.0 1:4.3 + __satfractunshiusq@GCC_4.3.0 1:4.3 + __satfractunsqida@GCC_4.3.0 1:4.3 + __satfractunsqidq@GCC_4.3.0 1:4.3 + __satfractunsqiha@GCC_4.3.0 1:4.3 + __satfractunsqihq@GCC_4.3.0 1:4.3 + __satfractunsqiqq@GCC_4.3.0 1:4.3 + __satfractunsqisa@GCC_4.3.0 1:4.3 + __satfractunsqisq@GCC_4.3.0 1:4.3 + __satfractunsqiuda@GCC_4.3.0 1:4.3 + __satfractunsqiudq@GCC_4.3.0 1:4.3 + __satfractunsqiuha@GCC_4.3.0 1:4.3 + __satfractunsqiuhq@GCC_4.3.0 1:4.3 + __satfractunsqiuqq@GCC_4.3.0 1:4.3 + __satfractunsqiusa@GCC_4.3.0 1:4.3 + __satfractunsqiusq@GCC_4.3.0 1:4.3 + __satfractunssida@GCC_4.3.0 1:4.3 + __satfractunssidq@GCC_4.3.0 1:4.3 + __satfractunssiha@GCC_4.3.0 1:4.3 + __satfractunssihq@GCC_4.3.0 1:4.3 + __satfractunssiqq@GCC_4.3.0 1:4.3 + __satfractunssisa@GCC_4.3.0 1:4.3 + __satfractunssisq@GCC_4.3.0 1:4.3 + __satfractunssiuda@GCC_4.3.0 1:4.3 + __satfractunssiudq@GCC_4.3.0 1:4.3 + __satfractunssiuha@GCC_4.3.0 1:4.3 + __satfractunssiuhq@GCC_4.3.0 1:4.3 + __satfractunssiuqq@GCC_4.3.0 1:4.3 + __satfractunssiusa@GCC_4.3.0 1:4.3 + __satfractunssiusq@GCC_4.3.0 1:4.3 + __satfractuqqda@GCC_4.3.0 1:4.3 + __satfractuqqdq@GCC_4.3.0 1:4.3 + __satfractuqqha@GCC_4.3.0 1:4.3 + __satfractuqqhq@GCC_4.3.0 1:4.3 + __satfractuqqqq@GCC_4.3.0 1:4.3 + __satfractuqqsa@GCC_4.3.0 1:4.3 + __satfractuqqsq@GCC_4.3.0 1:4.3 + __satfractuqquda@GCC_4.3.0 1:4.3 + __satfractuqqudq2@GCC_4.3.0 1:4.3 + __satfractuqquha@GCC_4.3.0 1:4.3 + __satfractuqquhq2@GCC_4.3.0 1:4.3 + __satfractuqqusa@GCC_4.3.0 1:4.3 + __satfractuqqusq2@GCC_4.3.0 1:4.3 + __satfractusada@GCC_4.3.0 1:4.3 + __satfractusadq@GCC_4.3.0 1:4.3 + __satfractusaha@GCC_4.3.0 1:4.3 + __satfractusahq@GCC_4.3.0 1:4.3 + __satfractusaqq@GCC_4.3.0 1:4.3 + __satfractusasa@GCC_4.3.0 1:4.3 + __satfractusasq@GCC_4.3.0 1:4.3 + __satfractusauda2@GCC_4.3.0 1:4.3 + __satfractusaudq@GCC_4.3.0 1:4.3 + __satfractusauha2@GCC_4.3.0 1:4.3 + __satfractusauhq@GCC_4.3.0 1:4.3 + __satfractusauqq@GCC_4.3.0 1:4.3 + __satfractusausq@GCC_4.3.0 1:4.3 + __satfractusqda@GCC_4.3.0 1:4.3 + __satfractusqdq@GCC_4.3.0 1:4.3 + __satfractusqha@GCC_4.3.0 1:4.3 + __satfractusqhq@GCC_4.3.0 1:4.3 + __satfractusqqq@GCC_4.3.0 1:4.3 + __satfractusqsa@GCC_4.3.0 1:4.3 + __satfractusqsq@GCC_4.3.0 1:4.3 + __satfractusquda@GCC_4.3.0 1:4.3 + __satfractusqudq2@GCC_4.3.0 1:4.3 + __satfractusquha@GCC_4.3.0 1:4.3 + __satfractusquhq2@GCC_4.3.0 1:4.3 + __satfractusquqq2@GCC_4.3.0 1:4.3 + __satfractusqusa@GCC_4.3.0 1:4.3 + __ssaddda3@GCC_4.3.0 1:4.3 + __ssadddq3@GCC_4.3.0 1:4.3 + __ssaddha3@GCC_4.3.0 1:4.3 + __ssaddhq3@GCC_4.3.0 1:4.3 + __ssaddqq3@GCC_4.3.0 1:4.3 + __ssaddsa3@GCC_4.3.0 1:4.3 + __ssaddsq3@GCC_4.3.0 1:4.3 + __ssashlda3@GCC_4.3.0 1:4.3 + __ssashldq3@GCC_4.3.0 1:4.3 + __ssashlha3@GCC_4.3.0 1:4.3 + __ssashlhq3@GCC_4.3.0 1:4.3 + __ssashlqq3@GCC_4.3.0 1:4.3 + __ssashlsa3@GCC_4.3.0 1:4.3 + __ssashlsq3@GCC_4.3.0 1:4.3 + __ssdivda3@GCC_4.3.0 1:4.3 + __ssdivdq3@GCC_4.3.0 1:4.3 + __ssdivha3@GCC_4.3.0 1:4.3 + __ssdivhq3@GCC_4.3.0 1:4.3 + __ssdivqq3@GCC_4.3.0 1:4.3 + __ssdivsa3@GCC_4.3.0 1:4.3 + __ssdivsq3@GCC_4.3.0 1:4.3 + __ssmulda3@GCC_4.3.0 1:4.3 + __ssmuldq3@GCC_4.3.0 1:4.3 + __ssmulha3@GCC_4.3.0 1:4.3 + __ssmulhq3@GCC_4.3.0 1:4.3 + __ssmulqq3@GCC_4.3.0 1:4.3 + __ssmulsa3@GCC_4.3.0 1:4.3 + __ssmulsq3@GCC_4.3.0 1:4.3 + __ssnegda2@GCC_4.3.0 1:4.3 + __ssnegdq2@GCC_4.3.0 1:4.3 + __ssnegha2@GCC_4.3.0 1:4.3 + __ssneghq2@GCC_4.3.0 1:4.3 + __ssnegqq2@GCC_4.3.0 1:4.3 + __ssnegsa2@GCC_4.3.0 1:4.3 + __ssnegsq2@GCC_4.3.0 1:4.3 + __sssubda3@GCC_4.3.0 1:4.3 + __sssubdq3@GCC_4.3.0 1:4.3 + __sssubha3@GCC_4.3.0 1:4.3 + __sssubhq3@GCC_4.3.0 1:4.3 + __sssubqq3@GCC_4.3.0 1:4.3 + __sssubsa3@GCC_4.3.0 1:4.3 + __sssubsq3@GCC_4.3.0 1:4.3 + __subda3@GCC_4.3.0 1:4.3 + __subdf3@GCC_3.0 1:4.1.1 + __subdq3@GCC_4.3.0 1:4.3 + __subha3@GCC_4.3.0 1:4.3 + __subhq3@GCC_4.3.0 1:4.3 + __subqq3@GCC_4.3.0 1:4.3 + __subsa3@GCC_4.3.0 1:4.3 + __subsf3@GCC_3.0 1:4.1.1 + __subsq3@GCC_4.3.0 1:4.3 + __subuda3@GCC_4.3.0 1:4.3 + __subudq3@GCC_4.3.0 1:4.3 + __subuha3@GCC_4.3.0 1:4.3 + __subuhq3@GCC_4.3.0 1:4.3 + __subuqq3@GCC_4.3.0 1:4.3 + __subusa3@GCC_4.3.0 1:4.3 + __subusq3@GCC_4.3.0 1:4.3 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __sync_add_and_fetch_1@GCC_4.4.0 1:4.4.0 + __sync_add_and_fetch_2@GCC_4.4.0 1:4.4.0 + __sync_add_and_fetch_4@GCC_4.4.0 1:4.4.0 + __sync_and_and_fetch_1@GCC_4.4.0 1:4.4.0 + __sync_and_and_fetch_2@GCC_4.4.0 1:4.4.0 + __sync_and_and_fetch_4@GCC_4.4.0 1:4.4.0 + __sync_bool_compare_and_swap_1@GCC_4.4.0 1:4.4.0 + __sync_bool_compare_and_swap_2@GCC_4.4.0 1:4.4.0 + __sync_bool_compare_and_swap_4@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_add_1@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_add_2@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_add_4@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_and_1@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_and_2@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_and_4@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_nand_1@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_nand_2@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_nand_4@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_or_1@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_or_2@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_or_4@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_sub_1@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_sub_2@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_sub_4@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_xor_1@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_xor_2@GCC_4.4.0 1:4.4.0 + __sync_fetch_and_xor_4@GCC_4.4.0 1:4.4.0 + __sync_lock_test_and_set_1@GCC_4.4.0 1:4.4.0 + __sync_lock_test_and_set_2@GCC_4.4.0 1:4.4.0 + __sync_lock_test_and_set_4@GCC_4.4.0 1:4.4.0 + __sync_nand_and_fetch_1@GCC_4.4.0 1:4.4.0 + __sync_nand_and_fetch_2@GCC_4.4.0 1:4.4.0 + __sync_nand_and_fetch_4@GCC_4.4.0 1:4.4.0 + __sync_or_and_fetch_1@GCC_4.4.0 1:4.4.0 + __sync_or_and_fetch_2@GCC_4.4.0 1:4.4.0 + __sync_or_and_fetch_4@GCC_4.4.0 1:4.4.0 + __sync_sub_and_fetch_1@GCC_4.4.0 1:4.4.0 + __sync_sub_and_fetch_2@GCC_4.4.0 1:4.4.0 + __sync_sub_and_fetch_4@GCC_4.4.0 1:4.4.0 + __sync_synchronize@GCC_4.4.0 1:4.4.0 + __sync_val_compare_and_swap_1@GCC_4.4.0 1:4.4.0 + __sync_val_compare_and_swap_2@GCC_4.4.0 1:4.4.0 + __sync_val_compare_and_swap_4@GCC_4.4.0 1:4.4.0 + __sync_xor_and_fetch_1@GCC_4.4.0 1:4.4.0 + __sync_xor_and_fetch_2@GCC_4.4.0 1:4.4.0 + __sync_xor_and_fetch_4@GCC_4.4.0 1:4.4.0 + __truncdfsf2@GCC_3.0 1:4.1.1 + __ucmpdi2@GCC_3.0 1:4.1.1 + __udivdi3@GLIBC_2.0 1:4.1.1 + __udivmoddi4@GCC_3.0 1:4.1.1 + __udivuda3@GCC_4.3.0 1:4.3 + __udivudq3@GCC_4.3.0 1:4.3 + __udivuha3@GCC_4.3.0 1:4.3 + __udivuhq3@GCC_4.3.0 1:4.3 + __udivuqq3@GCC_4.3.0 1:4.3 + __udivusa3@GCC_4.3.0 1:4.3 + __udivusq3@GCC_4.3.0 1:4.3 + __umoddi3@GLIBC_2.0 1:4.1.1 + __unorddf2@GCC_3.3.4 1:4.1.1 + __unordsf2@GCC_3.3.4 1:4.1.1 + __usadduda3@GCC_4.3.0 1:4.3 + __usaddudq3@GCC_4.3.0 1:4.3 + __usadduha3@GCC_4.3.0 1:4.3 + __usadduhq3@GCC_4.3.0 1:4.3 + __usadduqq3@GCC_4.3.0 1:4.3 + __usaddusa3@GCC_4.3.0 1:4.3 + __usaddusq3@GCC_4.3.0 1:4.3 + __usashluda3@GCC_4.3.0 1:4.3 + __usashludq3@GCC_4.3.0 1:4.3 + __usashluha3@GCC_4.3.0 1:4.3 + __usashluhq3@GCC_4.3.0 1:4.3 + __usashluqq3@GCC_4.3.0 1:4.3 + __usashlusa3@GCC_4.3.0 1:4.3 + __usashlusq3@GCC_4.3.0 1:4.3 + __usdivuda3@GCC_4.3.0 1:4.3 + __usdivudq3@GCC_4.3.0 1:4.3 + __usdivuha3@GCC_4.3.0 1:4.3 + __usdivuhq3@GCC_4.3.0 1:4.3 + __usdivuqq3@GCC_4.3.0 1:4.3 + __usdivusa3@GCC_4.3.0 1:4.3 + __usdivusq3@GCC_4.3.0 1:4.3 + __usmuluda3@GCC_4.3.0 1:4.3 + __usmuludq3@GCC_4.3.0 1:4.3 + __usmuluha3@GCC_4.3.0 1:4.3 + __usmuluhq3@GCC_4.3.0 1:4.3 + __usmuluqq3@GCC_4.3.0 1:4.3 + __usmulusa3@GCC_4.3.0 1:4.3 + __usmulusq3@GCC_4.3.0 1:4.3 + __usneguda2@GCC_4.3.0 1:4.3 + __usnegudq2@GCC_4.3.0 1:4.3 + __usneguha2@GCC_4.3.0 1:4.3 + __usneguhq2@GCC_4.3.0 1:4.3 + __usneguqq2@GCC_4.3.0 1:4.3 + __usnegusa2@GCC_4.3.0 1:4.3 + __usnegusq2@GCC_4.3.0 1:4.3 + __ussubuda3@GCC_4.3.0 1:4.3 + __ussubudq3@GCC_4.3.0 1:4.3 + __ussubuha3@GCC_4.3.0 1:4.3 + __ussubuhq3@GCC_4.3.0 1:4.3 + __ussubuqq3@GCC_4.3.0 1:4.3 + __ussubusa3@GCC_4.3.0 1:4.3 + __ussubusq3@GCC_4.3.0 1:4.3 --- gcc-4.5-4.5.2.orig/debian/gij-wrapper-BV +++ gcc-4.5-4.5.2/debian/gij-wrapper-BV @@ -0,0 +1,98 @@ +#!/usr/bin/perl -w +# +# Starts the GNU Java interpreter. +# +# Command-line arguments should be in the style of Sun's Java runtime; +# these will be converted to gij arguments before being passed to the +# gij itself. +# +# The Debian JNI module directory and any other specified JNI +# directories will be included on the JNI search path. +# +# Copyright (C) 2002-2003 by Ben Burton +# Based on the original gij-wrapper-3.2 shell script. + +use strict; + +# The real Java runtime: +my $javaRuntime = '/usr/bin/gij-@BV@'; + +# The debian JNI module directory: +my $debianJNIDir = '/usr/lib/jni'; + +# The command-line arguments to pass to the real Java runtime: +my @commandLine; + +# The full JNI search path to use: +my $JNIPath = ''; + +# Build the command-line from the arguments given. +my $parsingOptions = 1; + +# Flag used to copy argument to -classpath or -cp. +my $copyNext = 0; +foreach my $arg (@ARGV) { + if (not $parsingOptions) { + # We're done parsing options; just copy all remaining arguments directly. + push @commandLine, $arg; + next; + } + if ($copyNext) { + push @commandLine, $arg; + $copyNext = 0; + next; + } + + # Try to interpret Sun-style options. + if ($arg eq '-version') { + push @commandLine, '--version'; + } elsif ($arg eq '-h' or $arg eq '-help') { + push @commandLine, '--help'; + } elsif ($arg eq '-cp' or $arg eq '--cp') { + push @commandLine, '-cp'; + $copyNext = 1; + } elsif ($arg eq '-classpath' or $arg eq '--classpath') { + push @commandLine, '-classpath'; + $copyNext = 1; + } elsif ($arg =~ /^-Djava.library.path=(.+)$/) { + # A component of the JNI search path has been given. + if ($JNIPath) { + $JNIPath = $JNIPath . ':' . $1; + } else { + $JNIPath = $1; + } + } elsif ($arg eq '-jar' or $arg =~ /^-D/) { + # Copy the argument directly. + push @commandLine, $arg; + } elsif ($arg =~ /^-/) { + # An unrecognised option has been passed - just drop it. + } else { + # Some non-option argument has been given. + # Stop parsing options at this point. + push @commandLine, $arg; + $parsingOptions = 0; + } +} + +# Add the debian JNI module directory to the JNI search path if it's not +# already there. +if ($JNIPath !~ /(^|:)$debianJNIDir($|:)/) { + if ($JNIPath) { + $JNIPath = $JNIPath . ':' . $debianJNIDir; + } else { + $JNIPath = $debianJNIDir; + } +} + +# Use environment variable $LTDL_LIBRARY_PATH to store the JNI path, +# since gij uses libltdl to dlopen JNI modules. +if ($ENV{LTDL_LIBRARY_PATH}) { + $ENV{LTDL_LIBRARY_PATH} = $ENV{LTDL_LIBRARY_PATH} . ':' . $JNIPath; +} else { + $ENV{LTDL_LIBRARY_PATH} = $JNIPath; +} + +# Call the real Java runtime. +my @fullCommandLine = ( $javaRuntime ); +push @fullCommandLine, @commandLine; +exec @fullCommandLine or exit(1); --- gcc-4.5-4.5.2.orig/debian/gcjh-wrapper-BV +++ gcc-4.5-4.5.2/debian/gcjh-wrapper-BV @@ -0,0 +1,86 @@ +#!/usr/bin/perl -w +# +# Starts the GNU Java header generator. +# +# Command-line arguments should be in the style of Sun's javah command; +# these will be converted to gcjh arguments before being passed to the +# gcjh itself. +# +# Copyright (C) 2003 by Peter Hawkins +# Haphazardly hacked up based on the gcj-wrapper perl script. +# Copyright (C) 2002-2003 by Ben Burton +# Based on the original gcj-wrapper-3.2 shell script. + +use strict; + +# The real Java header generator: +my $javaHeaderGen = '/usr/bin/gcjh-@BV@'; + +# The command-line arguments to pass to the real Java compiler: +my @commandLine; + +# Build the command-line from the arguments given. +my $parsingOptions = 1; +my $copyNextArg = 0; +my $ignoreNextArg = 0; +my $appendNextArg = ''; +foreach my $arg (@ARGV) { + # See if we already know what to do with this argument. + if ($ignoreNextArg) { + # Throw it away. + $ignoreNextArg = 0; + next; + } elsif ($copyNextArg or not $parsingOptions) { + # Copy it directly. + push @commandLine, $arg; + $copyNextArg = 0; + next; + } elsif ($appendNextArg) { + # Append it to $appendNextArg and then copy directly. + push @commandLine, ($appendNextArg . $arg); + $appendNextArg = ''; + next; + } + + # Try to interpret Sun-style options. + if ($arg eq '-version') { + push @commandLine, '--version'; + } elsif ($arg eq '-h' or $arg eq '-help') { + push @commandLine, '--help'; + } elsif ($arg eq '-verbose') { + push @commandLine, '--verbose'; + } elsif ($arg eq '-classpath' or $arg eq '--classpath' or $arg eq '--cp') { + $appendNextArg = '--classpath='; + } elsif ($arg eq '-encoding' or $arg eq '-bootclasspath' or + $arg eq '-extdirs') { + $appendNextArg = "-".$arg . '='; + } elsif ($arg eq '-d') { + push @commandLine, '-d'; + $copyNextArg = 1; + } elsif ($arg eq '-o') { + push @commandLine, '-o'; + $copyNextArg = 1; + } elsif ($arg eq '-stubs') { + push @commandLine, '-stubs'; + } elsif ($arg eq '-jni') { + push @commandLine, '-jni'; + } elsif ($arg =~ /^-old/) { + # An extended Sun option (which we don't support). + push @commandLine, '--help' if ($arg eq '-old'); + } elsif ($arg =~ /^-/) { + # An unsupported standalone option. + } else { + # Some non-option argument has been given. + # Stop parsing options at this point. + push @commandLine, $arg; + $parsingOptions = 0; + } +} + +# Was there a partial argument that was never completed? +push @commandLine, $appendNextArg if ($appendNextArg); + +# Call the real Java header generator. +my @fullCommandLine = ( $javaHeaderGen ); +push @fullCommandLine, @commandLine; +exec @fullCommandLine or exit(1); --- gcc-4.5-4.5.2.orig/debian/g++-BV-spu.overrides +++ gcc-4.5-4.5.2/debian/g++-BV-spu.overrides @@ -0,0 +1,2 @@ +g++-@BV@-spu: non-standard-dir-in-usr usr/spu/ +g++-@BV@-spu: file-in-unusual-dir --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.ia64 +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.ia64 @@ -0,0 +1,7 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.64bit" +#include "libstdc++6.symbols.excprop" + _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.sh4 +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.sh4 @@ -0,0 +1,7 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" + __gxx_personality_v0@CXXABI_1.3 4.1.1 +#include "libstdc++6.symbols.excprop" +#include "libstdc++6.symbols.glibcxxmath" + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0 --- gcc-4.5-4.5.2.orig/debian/libgcj-doc.doc-base +++ gcc-4.5-4.5.2/debian/libgcj-doc.doc-base @@ -0,0 +1,10 @@ +Document: libgcj-doc +Title: The GNU LibGCJ Classpath library +Author: Various +Abstract: Autogenerated documentation describing the libgcj + library (GCC 4.5), based on the classpath library. +Section: Programming/Java + +Format: html +Index: /usr/share/doc/gcj-4.5-base/api/index.html +Files: /usr/share/doc/gcj-4.5-base/api/*.html --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.kfreebsd-amd64 +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.kfreebsd-amd64 @@ -0,0 +1,138 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4.4@GCC_3.4.4 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __absvti2@GCC_3.4.4 1:4.1.1 + __addtf3@GCC_4.3.0 1:4.3 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __addvti3@GCC_3.4.4 1:4.1.1 + __ashlti3@GCC_3.0 1:4.1.1 + __ashrti3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzti2@GCC_3.4 1:4.1.1 + __cmpti2@GCC_3.0 1:4.1.1 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzti2@GCC_3.4 1:4.1.1 + __deregister_frame@GCC_3.0 1:4.1.1 + __deregister_frame_info@GCC_3.0 1:4.1.1 + __deregister_frame_info_bases@GCC_3.0 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + __divtc3@GCC_4.0.0 1:4.3 + __divtf3@GCC_4.3.0 1:4.3 + __divti3@GCC_3.0 1:4.1.1 + __divxc3@GCC_4.0.0 1:4.1.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 1:4.1.1 + __eqtf2@GCC_4.3.0 1:4.3 + __extenddftf2@GCC_4.3.0 1:4.3 + __extendsftf2@GCC_4.3.0 1:4.3 + __extendxftf2@GCC_4.3.0 1:4.3 + __ffsdi2@GCC_3.0 1:4.1.1 + __ffsti2@GCC_3.0 1:4.1.1 + __fixdfti@GCC_3.0 1:4.1.1 + __fixsfti@GCC_3.0 1:4.1.1 + __fixtfdi@GCC_4.3.0 1:4.3 + __fixtfsi@GCC_4.3.0 1:4.3 + __fixtfti@GCC_4.3.0 1:4.3 + __fixunsdfdi@GCC_3.0 1:4.1.1 + __fixunsdfti@GCC_3.0 1:4.1.1 + __fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfti@GCC_3.0 1:4.1.1 + __fixunstfdi@GCC_4.3.0 1:4.3 + __fixunstfsi@GCC_4.3.0 1:4.3 + __fixunstfti@GCC_4.3.0 1:4.3 + __fixunsxfdi@GCC_3.0 1:4.1.1 + __fixunsxfti@GCC_3.0 1:4.1.1 + __fixxfti@GCC_3.0 1:4.1.1 + __floatditf@GCC_4.3.0 1:4.3 + __floatsitf@GCC_4.3.0 1:4.3 + __floattidf@GCC_3.0 1:4.1.1 + __floattisf@GCC_3.0 1:4.1.1 + __floattitf@GCC_4.3.0 1:4.3 + __floattixf@GCC_3.0 1:4.1.1 + __floatunditf@GCC_4.3.0 1:4.3 + __floatunsitf@GCC_4.3.0 1:4.3 + __floatuntidf@GCC_4.2.0 1:4.2.1 + __floatuntisf@GCC_4.2.0 1:4.2.1 + __floatuntitf@GCC_4.3.0 1:4.3 + __floatuntixf@GCC_4.2.0 1:4.2.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __getf2@GCC_4.3.0 1:4.3 + __gttf2@GCC_3.0 1:4.3 + __letf2@GCC_4.3.0 1:4.3 + __lshrti3@GCC_3.0 1:4.1.1 + __lttf2@GCC_3.0 1:4.3 + __modti3@GCC_3.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_4.0.0 1:4.3 + __multf3@GCC_4.3.0 1:4.3 + __multi3@GCC_3.0 1:4.1.1 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __mulvti3@GCC_3.4.4 1:4.1.1 + __mulxc3@GCC_4.0.0 1:4.1.1 + __negtf2@GCC_4.3.0 1:4.3 + __negti2@GCC_3.0 1:4.1.1 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __negvti2@GCC_3.4.4 1:4.1.1 + __netf2@GCC_3.0 1:4.3 + __paritydi2@GCC_3.4 1:4.1.1 + __parityti2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountti2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_4.0.0 1:4.3 + __powixf2@GCC_4.0.0 1:4.1.1 + __register_frame@GCC_3.0 1:4.1.1 + __register_frame_info@GCC_3.0 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GCC_3.0 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GCC_3.0 1:4.1.1 + __subtf3@GCC_4.3.0 1:4.3 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __subvti3@GCC_3.4.4 1:4.1.1 + __trunctfdf2@GCC_4.3.0 1:4.3 + __trunctfsf2@GCC_4.3.0 1:4.3 + __trunctfxf2@GCC_4.3.0 1:4.3 + __ucmpti2@GCC_3.0 1:4.1.1 + __udivmodti4@GCC_3.0 1:4.1.1 + __udivti3@GCC_3.0 1:4.1.1 + __umodti3@GCC_3.0 1:4.1.1 + __unordtf2@GCC_4.3.0 1:4.3 --- gcc-4.5-4.5.2.orig/debian/cpp-BV-CRB.preinst.in +++ gcc-4.5-4.5.2/debian/cpp-BV-CRB.preinst.in @@ -0,0 +1,11 @@ +#!/bin/sh + +set -e + +if [ "$1" = "upgrade" ] || [ "$1" = "configure" ]; then + update-alternatives --quiet --remove @TARGET@-cpp /usr/bin/@TARGET@-cpp-@BV@ +fi + +#DEBHELPER# + +exit 0 --- gcc-4.5-4.5.2.orig/debian/rules.conf +++ gcc-4.5-4.5.2/debian/rules.conf @@ -0,0 +1,848 @@ +# -*- makefile -*- +# rules.conf +# - used to build debian/control and debian/rules.parameters +# - assumes unpacked sources + +include debian/rules.defs +include debian/rules.sonames + +# Helper to generate biarch/triarch dependencies. +# For example, $(eval $(call gen_multilib_deps,gomp)) will create the +# libgompbiarch variable, and make it contains the libgompbiarch{32,64,n32} +# variables if biarch{32,64,n32} is set to yes. +define gen_multilib_deps + lib$1biarch64 := lib64$1$$($(shell echo $1 | tr "a-z" "A-Z")_SONAME)$(LS) (>= $$$${gcc:Version}) + lib$1biarch32 := lib32$1$$($(shell echo $1 | tr "a-z" "A-Z")_SONAME)$(LS) (>= $$$${gcc:Version}) + lib$1biarchn32 := libn32$1$$($(shell echo $1 | tr "a-z" "A-Z")_SONAME)$(LS) (>= $$$${gcc:Version}) + ifeq ($$(biarch64),yes) + lib$1biarch := $$(lib$1biarch64) + endif + ifeq ($$(biarch32),yes) + lib$1biarch := $$(lib$1biarch32) + endif + ifeq ($$(biarchn32),yes) + ifeq ($$(biarch64),yes) + lib$1biarch := $$(lib$1biarch64), $$(lib$1biarchn32) + else + lib$1biarch := $$(lib$1biarchn32) + endif + endif +endef +$(foreach x,gomp mudflap ssp gfortran objc,$(eval $(call gen_multilib_deps,$(x)))) + +# Helper to generate _no_archs variables. +# For example, $(eval $(call gen_no_archs,java)) will create the java_no_archs +# variable, using the java_no_cpu and java_no_systems variables. +define gen_no_archs + $1_no_archs := + ifneq (,$$($1_no_cpus)) + $1_no_archs += $$(foreach cpu,$$(filter-out i386 amd64 alpha arm,$$($1_no_cpus)),!$$(cpu)) + ifneq (,$$(filter i386,$$($1_no_cpus))) + $1_no_archs += !i386 !hurd-i386 !kfreebsd-i386 !knetbsd-i386 + endif + ifneq (,$$(filter amd64,$$($1_no_cpus))) + $1_no_archs += !amd64 !kfreebsd-amd64 + endif + ifneq (,$$(filter alpha,$$($1_no_cpus))) + $1_no_archs += !alpha !hurd-alpha !knetbsd-alpha + endif + ifneq (,$$(filter arm,$$($1_no_cpus))) + $1_no_archs += !arm !armel !armhf + endif + ifneq (,$$(strip $3)) + $1_no_systems_tmp := $$(subst $$(SPACE)gnu$$(SPACE),$$(SPACE)hurd-gnu$$(SPACE),$$(SPACE)$3$$(SPACE)) + $1_no_archs += $$(foreach cpu,$$($1_no_cpus),$$(foreach system,$$($1_no_systems_tmp),!$$(subst gnu,$$(cpu),$$(system)))) + endif + endif + ifneq (,$$($1_no_systems)) + $1_no_systems_tmp := $$(subst $$(SPACE)gnu$$(SPACE),$$(SPACE)hurd-gnu$$(SPACE),$$(SPACE)$$($1_no_systems)$$(SPACE)) + $1_no_archs += $$(foreach system,$$($1_no_systems_tmp),$$(foreach cpu,$2,!$$(subst gnu,$$(cpu),$$(system)))) + endif + $1_no_archs := $$(strip $$($1_no_archs)) +endef +base_deb_cpus := i386 alpha +base_deb_systems := +$(foreach x,ada java java_plugin fortran libphobos libgc check locale,$(eval $(call gen_no_archs,$(x),$(base_deb_cpus),$(base_deb_systems)))) +linux_no_archs := !hurd-i386 !hurd-alpha !kfreebsd-i386 !kfreebsd-amd64 !knetbsd-i386 !knetbsd-alpha + +GCC_VERSION := $(strip $(shell cat $(srcdir)/gcc/BASE-VER)) +NEXT_GCC_VERSION := $(shell echo $(GCC_VERSION) | \ + awk -F. '{OFS="."; if (NF==2) $$3=1; else $$NF += 1; print}') +GCC_MAJOR_VERSION := $(shell echo $(GCC_VERSION) | sed -r 's/([0-9])\.[0-9]\.[0-9]/\1/') +GCC_MINOR_VERSION := $(shell echo $(GCC_VERSION) | sed -r 's/[0-9]\.([0-9])\.[0-9]/\1/') +GCC_RELEASE_VERSION := $(shell echo $(GCC_VERSION) | sed -r 's/[0-9]\.[0-9]\.([0-9])/\1/') +NEXT_GCC_MAJOR_VERSION := $(shell expr $(echo $(GCC_MAJOR_VERSION)) + 1) +NEXT_GCC_MINOR_VERSION := $(shell expr $(echo $(GCC_MINOR_VERSION)) + 1) +NEXT_GCC_RELEASE_VERSION := $(shell expr $(echo $(GCC_MAJOR_VERSION)) + 1) + +GCC_SOURCE_VERSION := $(shell echo $(DEB_VERSION) | sed 's/-.*//') +NEXT_GCC_SOURCE_VERSION := $(shell echo $(GCC_SOURCE_VERSION) | \ + awk -F. '{OFS="."; if (NF==2) $$3=1; else $$NF += 1; print}') + +ifeq ($(PKGSOURCE),gcc-snapshot) + BASE_VERSION := $(shell echo $(GCC_VERSION) | sed -e 's/\([1-9]\.[0-9]\).*/\1/') +endif +ifneq (,$(findstring gdc,$(PKGSOURCE))) + GDC_BASE_VERSION := $(word 1, $(subst -, ,$(DEB_VERSION))) + DEB_VERSION := $(shell echo $(DEB_VERSION) | sed -r 's/[0-9]{8}-//') + DEB_VERSION := $(subst $(GDC_BASE_VERSION)-,,$(DEB_VERSION)) +endif + +MAINTAINER = Debian GCC Maintainers +ifeq ($(distribution),Ubuntu) + ifneq (,$(findstring $(PKGSOURCE),gnat gdc)) + MAINTAINER = Ubuntu MOTU Developers + else + MAINTAINER = Ubuntu Core developers + endif +endif + +UPLOADERS = Matthias Klose +ifneq (,$(findstring $(PKGSOURCE),gnat)) + UPLOADERS = Ludovic Brenta +endif +ifneq (,$(findstring $(PKGSOURCE),gdc)) + UPLOADERS = Arthur Loiret +endif + +DPKG_BUILD_DEP = dpkg-dev (>= 1.14.15), +ifeq ($(with_multiarch_lib),yes) + DPKG_BUILD_DEP = dpkg-dev (>= 1.16.0~ubuntu4), +endif +ifeq ($(multiarch_stage1),yes) + DPKG_BUILD_DEP = dpkg-dev (>= 1.16.0~ubuntu4), +endif + +ifeq ($(DEB_CROSS),yes) + DPKG_BUILD_DEP += dpkg-cross (>= 1.25.99), +endif + +# The binutils version needed. +# The oldest suitable versions for the various platforms can be found in +# INSTALL/specific.html ; we take a tighter dependency if possible to be on +# the safe side (something like newest( version in stable, versions for the +# various platforms in INSTALL/specific.html) ). +# We need binutils (>= 2.19.1) for a new dwarf unwind expression opcode. +# See http://gcc.gnu.org/ml/gcc-patches/2008-09/msg01713.html +BINUTILSV = 2.20.51.20100418~ +# Lower the binutils build dependency for amd64/i386. gold seems to be good enough on these architectures. +BINUTILSV = 2.20.1-14~ +ifeq ($(DEB_CROSS),yes) + BINUTILS_BUILD_DEP = binutils$(TS) (>= $(BINUTILSV)) +else + BINUTILS_BUILD_DEP = binutils (>= $(BINUTILSV)) | binutils-multiarch (>= $(BINUTILSV)) +endif +# FIXME; stripping doesn't work with gold +#BINUTILS_BUILD_DEP += , binutils-gold (>= $(BINUTILSV)) [$(gold_archs)] + +# libc-dev dependencies +libc_ver := 2.5 +libc_dev_ver := $(libc_ver) +ifneq (,$(findstring gnat,$(PKGSOURCE))) + libc_ver := 2.9-21 +endif +ifeq ($(with_multiarch_lib),yes) + libc_dev_ver := 2.13-0ubuntu6 +endif +ifeq ($(DEB_TARGET_ARCH_OS),linux) + ifneq (,$(findstring $(DEB_TARGET_ARCH),alpha ia64)) + LIBC_DEP = libc6.1 + else + LIBC_DEP = libc6 + endif +else + ifeq ($(DEB_TARGET_ARCH_OS),hurd) + LIBC_DEP = libc0.3 + endif + ifeq ($(DEB_TARGET_ARCH_OS),kfreebsd) + LIBC_DEP = libc0.1 + endif + ifeq ($(DEB_TARGET_ARCH),uclibc) + LIBC_DEP ?= libuclibc + LIBC_DEV_DEP ?= libuclibc-dev + endif +endif +LIBC_DEV_DEP = $(LIBC_DEP)-dev +# for cross +ifeq ($(DEB_CROSS),yes) + LIBC_DEP ?= $(LIBC_DEP)$(LS) + LIBC_DEV_DEP ?= $(LIBC_DEV_DEP)$(LS) +endif + +# this is about Debian archs name, *NOT* GNU target triplet +biarch_deb_map := \ + i386=amd64 amd64=i386 \ + mips=mips64 mipsel=mips64 \ + powerpc=ppc64 ppc64=powerpc \ + sparc=sparc64 \ + s390=s390x \ + kfreebsd-amd64=i386 + +biarch_deb_arch := $(patsubst $(DEB_TARGET_ARCH)=%,%, \ + $(filter $(DEB_TARGET_ARCH)=%,$(biarch_deb_map))) + +LIBC_BIARCH_DEP := +LIBC_BIARCH_DEV_DEP := +LIBCXX_BIARCH_DEP := +LIBCXX_BIARCH_DBG_DEP := +ifneq (,$(findstring yes,$(biarch64) $(biarch32) $(biarchn32))) + LIBC_BIARCH_DEP := $(LIBC_DEP)-$(biarch_deb_arch)$(LS) (>= $(libc_ver)) + LIBC_BIARCH_DEV_DEP := $(LIBC_DEV_DEP)-$(biarch_deb_arch)$(LS) (>= $(libc_ver)) + ifeq ($(biarch64),yes) + LIBCXX_BIARCH_DEP := lib64stdc++$(CXX_SONAME)$(LS) (>= $${gcc:Version}) + LIBCXX_BIARCH_DBG_DEP := lib64stdc++$(CXX_SONAME)-$(BASE_VERSION)-dbg$(LS) + endif + ifeq ($(biarch32),yes) + LIBCXX_BIARCH_DEP := lib32stdc++$(CXX_SONAME)$(LS) (>= $${gcc:Version}) + LIBCXX_BIARCH_DBG_DEP := lib32stdc++$(CXX_SONAME)-$(BASE_VERSION)-dbg$(LS) + endif + ifeq ($(biarchn32),yes) + ifneq (,$(findstring $(DEB_TARGET_ARCH),mips mipsel)) + triarch := + ifeq ($(biarch64),yes) + triarch := $(COMMA)$(SPACE) + endif + LIBC_BIARCH_DEV_DEP += $(triarch)libc6-dev-mipsn32$(LS) (>= $(libc_ver)) + LIBC_BIARCH_DEP += $(triarch)libc6-mipsn32$(LS) (>= $(libc_ver)) + LIBCXX_BIARCH_DEP += $(triarch)libn32stdc++$(CXX_SONAME)$(LS) (>= $${gcc:Version}) + LIBCXX_BIARCH_DBG_DEP += $(triarch)libn32stdc++$(CXX_SONAME)-$(BASE_VERSION)-dbg$(LS) + endif + endif +endif + +# Add suffix and required version +LIBC_DEV_DEP := $(LIBC_DEV_DEP)$(LS) (>= $(libc_dev_ver)) + +# TODO: make this automatic, there must be a better way to define LIBC_DEP. +ifneq ($(DEB_CROSS),yes) + LIBC_BUILD_DEP = libc6.1-dev (>= $(libc_dev_ver)) [alpha ia64] | libc0.3-dev (>= $(libc_dev_ver)) [hurd-i386] | libc0.1-dev (>= $(libc_dev_ver)) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= $(libc_dev_ver)), + LIBC_BIARCH_BUILD_DEP = libc6-dev-amd64 [i386], libc6-dev-sparc64 [sparc], libc6-dev-s390x [s390], libc6-dev-i386 [amd64], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64], lib64gcc1 [i386 powerpc sparc s390], libc6-dev-mips64 [mips mipsel], libc6-dev-mipsn32 [mips mipsel], +else + LIBC_BUILD_DEP = $(LIBC_DEV_DEP), + ifneq ($(LIBC_BIARCH_DEV_DEP),) + LIBC_BIARCH_BUILD_DEP = $(LIBC_BIARCH_DEV_DEP), + else + LIBC_BIARCH_BUILD_DEP = + endif +endif + +GCC_MULTILIB_BUILD_DEP = gcc-multilib [$(multilib_archs)], + +LIBUNWIND_DEV_DEP := libunwind7-dev$(LS) (>= 0.98.5-6) +LIBUNWIND_BUILD_DEP := $(LIBUNWIND_DEV_DEP) [ia64], +LIBATOMIC_OPS_BUILD_DEP := libatomic-ops-dev$(LS) [ia64], +ifneq ($(DEB_TARGET_ARCH),ia64) + LIBUNWIND_DEV_DEP := # nothing +endif + +ifneq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid maverick natty)) + GMP_BUILD_DEP = libgmp3-dev, + MPFR_BUILD_DEP = libmpfr-dev, +else + GMP_BUILD_DEP = libgmp10-dev, + MPFR_BUILD_DEP = libmpfr-dev (>= 3.0.0-9~), +endif + +PPL_BUILD_DEP = libppl-dev (>= 0.10) | libppl0.10-dev (>= 0.10), +CLOOG_BUILD_DEP = libcloog-ppl-dev (>= 0.15.9-2~), +CLOOG_RUNTIME_DEP = libcloog-ppl0 (>= 0.15.9-2~), libppl-c2, libppl7 +MPC_BUILD_DEP = libmpc-dev, +ELF_BUILD_DEP = libelfg0-dev (>= 0.8.12), + +SOURCE_BUILD_DEP := +ifeq (,$(findstring gcc,$(PKGSOURCE))) + SOURCE_BUILD_DEP := gcc-$(BASE_VERSION)-source (>= $(GCC_SOURCE_VERSION)), gcc-$(BASE_VERSION)-source (<< $(NEXT_GCC_SOURCE_VERSION)), +endif + +CHECK_BUILD_DEP := dejagnu [$(check_no_archs)], +ifneq (,$(findstring gcc,$(PKGSOURCE))) + CHECK_BUILD_DEP += autogen, +endif + +AUTO_BUILD_DEP := m4, libtool, +AUTO_BUILD_DEP += autoconf2.64, automake (>= 1:1.11), automake (<< 1:1.12), + +ifneq ($(DEB_CROSS),yes) +LIBC_BUILD_DEP := libc6.1-dev (>= $(libc_dev_ver)) [alpha ia64] | libc0.3-dev (>= $(libc_dev_ver)) [hurd-i386] | libc0.1-dev (>= $(libc_dev_ver)) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= $(libc_dev_ver)) +JAVA_BUILD_DEP := libc6.1-dbg [alpha ia64] | libc0.3-dbg [hurd-i386] | libc0.1-dbg [kfreebsd-i386 kfreebsd-amd64] | libc6-dbg, zlib1g-dev, libantlr-java, + +ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION)) + bd_java_archs = +else ifeq ($(PKGSOURCE)-$(with_java),gcc-snapshot-yes) + bd_java_archs = +else + bd_java_archs = $(EMPTY) [$(java_no_archs)] +endif + +ifneq (,$(java_awt_peers)) + JAVA_BUILD_DEP += fastjar$(bd_java_archs), libmagic-dev$(bd_java_archs), + JAVA_BUILD_DEP += libecj-java (>= 3.3.0-2)$(bd_java_archs), zip$(bd_java_archs), + ifeq ($(with_java_maintainer_mode),yes) + # gcj-4.3 needed for gjavah-4.3. + JAVA_BUILD_DEP += gcj-4.4$(bd_java_archs), ecj (>= 3.3.0-2)$(bd_java_archs), + endif + JAVA_BUILD_DEP += libasound2-dev [$(java_no_archs) $(linux_no_archs)], + ifneq (,$(findstring gtk,$(java_awt_peers))) + JAVA_BUILD_DEP += libxtst-dev$(bd_java_archs), libxt-dev$(bd_java_archs), libgtk2.0-dev (>= 2.4.4-2)$(bd_java_archs), libart-2.0-dev$(bd_java_archs), libcairo2-dev$(bd_java_archs), + endif + ifneq (,$(findstring qt,$(java_awt_peers))) + JAVA_BUILD_DEP += libqt4-dev (>= 4.1.0)$(bd_java_archs), + endif + # gconf peer, disabled by default + #JAVA_BUILD_DEP += libgconf2-dev$(bd_java_archs), + # gstreamer peer + #JAVA_BUILD_DEP += libgstreamer-plugins-base0.10-dev$(bd_java_archs), + ifneq ($(PKGSOURCE),gcc-snapshot) + JAVA_BUILD_DEP += g++-4.5 [armel armhf], + endif +endif +ifneq ($(with_standalone_gcj),yes) + ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION)) + JAVA_BUILD_DEP += $(SOURCE_BUILD_DEP) + endif +endif +#JAVA_BUILD_INDEP := gcj-$(BASE_VERSION)-jdk +ifeq ($(PKGSOURCE),gcc-snapshot) + LIBSTDCXX_BUILD_INDEP = doxygen (>= 1.5.4), graphviz (>= 2.2), gsfonts-x11, texlive-latex-base + JAVA_BUILD_INDEP := +endif +ifeq ($(with_separate_libgcj),yes) + ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION)) + JAVA_BUILD_DEP := + JAVA_BUILD_INDEP := + endif +endif + +ifeq ($(with_ecj),yes) + ifneq (./,$(dir $(ecj_jar))) + ECJ_DEP = libecj-java (>= 3.5.1) + endif +else + ECJ_DEP = ecj, libecj-java (>= 3.5.1) + ECJ_DEP = ecj-gcj, libecj-java-gcj (>= 3.5.1) + ifneq (,$(filter $(DEB_HOST_ARCH),arm armel armhf)) + ECJ_DEP +=, ecj1 + endif +endif + +ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION)) + LIBSTDCXX_BUILD_INDEP = doxygen (>= 1.4.2), graphviz (>= 2.2), gsfonts-x11, texlive-latex-base + JAVA_BUILD_INDEP :=, $(JAVA_BUILD_INDEP) +endif + +SPU_BUILD_DEP := binutils-spu (>= $(BINUTILSV)) [powerpc ppc64], newlib-spu (>= 1.16.0) [powerpc ppc64], gcc-$(BASE_VERSION)-base [powerpc ppc64], +SPU_BUILD_DEP := binutils-spu (>= $(BINUTILSV)) [powerpc ppc64], newlib-spu (>= 1.16.0) [powerpc ppc64], + +ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION)) + ifneq ($(with_separate_gnat),yes) + # Build gnat as part of the combiled gcc-x.y source package. Do not fail + # if gnat is not present on unsupported architectures; the build scripts + # will not use gnat anyway. + GNAT_BUILD_DEP := gnat (>= 4.1) [$(ada_no_archs)], + endif +else ifeq ($(PKGSOURCE),gcc-snapshot) + # Ditto, as part of the gcc-snapshot package. + # FIXME: ad hoc dependency, better fix setting of ada_no_archs + #GNAT_BUILD_DEP := gnat (>= 4.1) [$(ada_no_archs)], gcc-snapshot (>= 20090821-1) [armel armhf], + GNAT_BUILD_DEP := gnat (>= 4.1) [!arm !armel !armhf !m68k !sparc64 !hurd-i386], gcc-snapshot (>= 20090113) [sparc64 armel armhf], +else ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION)) + # Special source package just for gnat. Fail early if gnat is not present, + # rather than waste CPU cycles and fail later. + GNAT_BUILD_DEP := gnat (>= 4.1), + GNAT_BUILD_DEP += $(SOURCE_BUILD_DEP) + JAVA_BUILD_DEP := + JAVA_BUILD_INDEP := + # gnat on spu should work ... + SPU_BUILD_DEP := +else ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION)) + # Special source package just for gcj. + GNAT_BUILD_DEP := + GDC_BUILD_DEP := + SPU_BUILD_DEP := +else ifeq ($(PKGSOURCE),gdc-$(BASE_VERSION)) + # Special source package just for gdc. + GNAT_BUILD_DEP := + JAVA_BUILD_DEP := + JAVA_BUILD_INDEP := + GDC_BUILD_DEP := $(SOURCE_BUILD_DEP) + SPU_BUILD_DEP := +endif + +else +# build cross compiler + CROSS_BUILD_DEP := libc6-dev$(cross_lib_arch), +ifeq ($(REVERSE_CROSS),yes) + CROSS_BUILD_DEP += zlib1g-dev$(cross_lib_arch), libmpfr-dev$(cross_lib_arch), +endif + SOURCE_BUILD_DEP := gcc-$(BASE_VERSION)-source (>= $(GCC_SOURCE_VERSION)), gcc-$(BASE_VERSION)-source (<< $(NEXT_GCC_SOURCE_VERSION)), + ifeq ($(with_java),yes) + JAVA_BUILD_DEP := zlib1g-dev, lib64z1-dev [i386 powerpc sparc s390], lib32z1-dev [amd64 ppc64 kfreebsd-amd64], + endif + JAVA_BUILD_INDEP := + GNAT_BUILD_DEP := + ifeq (,$(findstring spu,$(DEB_TARGET_GNU_CPU))) + SPU_BUILD_DEP := + endif +endif # cross compiler + +# The numeric part of the gcc version number (x.yy.zz) +NEXT_GCC_VERSION := $(shell echo $(GCC_VERSION) | \ + awk -F. '{OFS="."; if (NF==2) $$3=1; else $$NF += 1; print}') +# first version with a new path component in gcc_lib_dir (i.e. GCC_VERSION +# or TARGET_ALIAS changes), or last version available for all architectures +DEB_GCC_SOFT_VERSION := 4.5.1-1~ +DEB_GCJ_SOFT_VERSION := 4.5.1-1~ + +ifeq ($(with_d),yes) + DEB_GDC_VERSION := $(GDC_BASE_VERSION)-$(DEB_VERSION) +endif + +# semiautomatic ... +DEB_SOVERSION := $(DEB_VERSION) +DEB_SOVERSION := 4.4 +DEB_SOEVERSION := $(EPOCH):4.4 +DEB_STDCXX_SOVERSION := 4.4 +DEB_GCJ_SOVERSION := 4.4 +DEB_GOMP_SOVERSION := $(DEB_SOVERSION) +DEB_GCCMATH_SOVERSION := $(DEB_SOVERSION) + +DEB_GCC_VERSION := $(DEB_VERSION) +DEB_GCJ_VERSION := $(DEB_VERSION) +ifeq ($(with_separate_libgcj),yes) + ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION)) + DEB_GCC_VERSION := $(DEB_GCC_SOFT_VERSION) + endif +endif + +DEB_GNAT_VERSION := $(DEB_VERSION) +ifeq ($(with_separate_gnat),yes) + ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION)) + DEB_GCC_VERSION := $(DEB_GCC_SOFT_VERSION) + endif +endif + +# manual ... +ifeq ($(DEB_TARGET_GNU_CPU), $(findstring $(DEB_TARGET_GNU_CPU),hppa m68k)) + ifeq ($(DEB_TARGET_ARCH),m68k) + GCC_SONAME := 2 + endif + ifeq ($(DEB_TARGET_ARCH),hppa) + GCC_SONAME := 4 + endif + DEB_LIBGCC_SOVERSION := $(DEB_SOVERSION) + DEB_LIBGCC_VERSION := $(DEB_VERSION) +else + GCC_SONAME := 1 + DEB_LIBGCC_SOVERSION := $(DEB_SOEVERSION) + DEB_LIBGCC_VERSION := $(DEB_EVERSION) +endif + +LIBGCC_DEP := libgcc$(GCC_SONAME)$(LS) (>= $(DEB_LIBGCC_VERSION)) +LIBGCC_BIARCH_DEP := +ifeq ($(biarch64),yes) + LIBGCC_BIARCH_DEP := lib64gcc$(GCC_SONAME)$(LS) (>= $(DEB_LIBGCC_VERSION)) +endif +ifeq ($(biarch32),yes) + LIBGCC_BIARCH_DEP := lib32gcc$(GCC_SONAME)$(LS) (>= $(DEB_LIBGCC_VERSION)) +endif +ifeq ($(biarchn32),yes) + ifeq ($(biarch64),yes) + LIBGCC_BIARCH_DEP := lib64gcc$(GCC_SONAME)$(LS) (>= $(DEB_LIBGCC_VERSION)), libn32gcc$(GCC_SONAME)$(LS) (>= $(DEB_LIBGCC_VERSION)) + else + LIBGCC_BIARCH_DEP := libn32gcc$(GCC_SONAME)$(LS) (>= $(DEB_LIBGCC_VERSION)) + endif +endif + +GNAT_VERSION := $(BASE_VERSION) + +LIBGNAT_DEP := +ifeq ($(with_libgnat),yes) + LIBGNAT_DEP := libgnat-$(GNAT_VERSION) (= $(DEB_VERSION)) +endif + +pkg_ver := -$(BASE_VERSION) + +PKG_GCJ_EXT = $(GCJ_SONAME1) +PKG_LIBGCJ_EXT = $(GCJ_SONAME1)$(if $(GCJ_SONAME2),-$(GCJ_SONAME2)) + +ctrl_flags = \ + -DBINUTILSV=$(BINUTILSV) \ + -DSRCNAME=$(PKGSOURCE) \ + -D__$(DEB_TARGET_GNU_CPU)__ \ + -DARCH=$(DEB_TARGET_ARCH) \ + -DDIST=$(distribution) + +ctrl_flags += \ + -DLIBC_DEV_DEP="$(LIBC_DEV_DEP)" \ + -DLIBC_BIARCH_BUILD_DEP="$(LIBC_BIARCH_BUILD_DEP)" \ + -DFORTRAN_BUILD_DEP="$(FORTRAN_BUILD_DEP)" \ + -DGNAT_BUILD_DEP="$(GNAT_BUILD_DEP)" \ + -DJAVA_BUILD_DEP="$(JAVA_BUILD_DEP)" \ + -DJAVA_BUILD_INDEP="$(JAVA_BUILD_INDEP)" \ + -DLIBSTDCXX_BUILD_INDEP="$(LIBSTDCXX_BUILD_INDEP)" \ + -DGDC_BUILD_DEP="$(GDC_BUILD_DEP)" \ + -DSPU_BUILD_DEP="$(SPU_BUILD_DEP)" \ + -DBINUTILS_BUILD_DEP="$(BINUTILS_BUILD_DEP)" \ + -DLIBC_BUILD_DEP="$(LIBC_BUILD_DEP)" \ + -DCHECK_BUILD_DEP="$(CHECK_BUILD_DEP)" \ + -DAUTO_BUILD_DEP="$(AUTO_BUILD_DEP)" \ + -DAUTOGEN_BUILD_DEP="$(AUTOGEN_BUILD_DEP)" \ + -DCLOOG_BUILD_DEP="$(CLOOG_BUILD_DEP)" \ + -DGMP_BUILD_DEP="$(GMP_BUILD_DEP)" \ + -DMPFR_BUILD_DEP="$(MPFR_BUILD_DEP)" \ + -DMPC_BUILD_DEP="$(MPC_BUILD_DEP)" \ + -DELF_BUILD_DEP="$(ELF_BUILD_DEP)" \ + -DDPKG_BUILD_DEP="$(DPKG_BUILD_DEP)" \ + -DSOURCE_BUILD_DEP="$(SOURCE_BUILD_DEP)" \ + -DCROSS_BUILD_DEP="$(CROSS_BUILD_DEP)" \ + -DMULTILIB_ARCHS="$(multilib_archs)" \ + -DNEON_ARCHS="$(neon_archs)" \ + -DTP=$(TP) \ + -DTS=$(TS) \ + -DLS=$(LS) + +ifeq ($(DEB_CROSS),yes) + ctrl_flags += \ + -DTARGET=$(DEB_TARGET_ARCH) \ + -DLIBUNWIND_BUILD_DEP="$(LIBUNWIND_BUILD_DEP)" \ + -DLIBATOMIC_OPS_BUILD_DEP="$(LIBATOMIC_OPS_BUILD_DEP)" +else + # add '-DPRI=optional' to ctrl_flags if this is not the default compiler + # ctrl_flags += \ + # -DPRI=optional +endif + +ifeq ($(with_base_only),yes) + ctrl_flags += \ + -DBASE_ONLY=yes +endif + +ifeq ($(with_multiarch_lib),yes) + ctrl_flags += \ + -DMULTIARCH=yes +endif + +control: control-file readme-bugs-file parameters-file copyright-file substvars-file versioned-files + +# stage1 and stage2 compilers are only C +ifdef DEB_STAGE + languages = c + addons = cdev plugindev + ifeq ($(DEB_STAGE),stage2) + addons += libgcc gccxbase + endif +else +languages = c c++ fortran objc objpp +ifeq ($(DEB_CROSS),yes) + addons = gccxbase +else + addons = gccbase +endif +addons += cdev c++dev fdev objcdev source objppdev multilib +addons += plugindev +ifeq ($(with_libgcc),yes) + addons += libgcc lib4gcc lib32gcc lib64gcc libn32gcc +endif +ifeq ($(with_libcxx),yes) + addons += libcxx lib32cxx lib64cxx libn32cxx +endif +ifeq ($(with_mudflap),yes) + addons += mudflap + ifeq ($(with_libmudflap),yes) + addons += libmudf + endif +endif +ifeq ($(with_libgfortran),yes) + addons += libgfortran lib32gfortran lib64gfortran libn32gfortran +endif +ifeq ($(with_libobjc),yes) + addons += libobjc lib32objc lib64objc libn32objc +endif +ifeq ($(with_libgomp),yes) + addons += libgomp lib32gomp lib64gomp libn32gomp +endif + +ifneq ($(DEB_CROSS),yes) + + languages += ada java + addons += libgcj libgcjdev gcjdoc libgnat libs source # libgmath libnof lib64gnat ssp + + ifneq (,$(neon_archs)) + addons += libneongcc libneongomp libneonobjc libneongfortran libneoncxx + endif + ifeq ($(with_fixincl),yes) + addons += fixincl + endif + ifeq ($(with_libgcj_doc),yes) + addons += gcjdoc + endif +# ifneq (,$(findstring gtk, $(java_awt_peers))) +# addons += gtkpeer +# endif +# ifneq (,$(findstring qt, $(java_awt_peers))) +# addons += qtpeer +# endif + ifeq ($(with_separate_libgcj),yes) + ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION)) + languages := $(filter-out java,$(languages)) + addons := $(filter-out gcj libgcj libgcjdev gcjdoc gtkpeer qtpeer,$(addons)) + endif + ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION)) + languages = java + addons = gcj libgcj libgcjdev + ifeq ($(with_libgcj_doc),yes) + addons += gcjdoc + endif +# ifneq (,$(findstring gtk, $(java_awt_peers))) +# addons += gtkpeer +# endif +# ifneq (,$(findstring qt, $(java_awt_peers))) +# addons += qtpeer +# endif + ifeq ($(with_standalone_gcj),yes) + addons += libgcc lib4gcc lib64gcc lib32gcc libn32gcc + endif + endif + endif + ifeq ($(with_standalone_gcj),yes) + ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION)) + ctrl_flags += -DSTANDALONEJAVA + endif + endif + ifeq ($(with_separate_gnat),yes) + ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION)) + languages := $(filter-out ada,$(languages)) + addons := $(filter-out libgnat,$(addons)) + endif + ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION)) + languages = ada + addons = libgnat + endif + endif + ifeq ($(with_separate_gdc),yes) + ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION)) + languages := $(filter-out d,$(languages)) + endif + ifeq ($(PKGSOURCE),gdc-$(BASE_VERSION)) + languages = d + addons = + endif + endif + ifneq ($(GFDL_INVARIANT_FREE),yes) + addons += gfdldoc + endif +endif +endif # not stage + +control-file: + echo "addons: $(addons)"; \ + m4 $(ctrl_flags) \ + -DPV=$(pkg_ver) \ + -DCXX_SO=$(CXX_SONAME) \ + -DGCC_SO=$(GCC_SONAME) \ + -DOBJC_SO=$(OBJC_SONAME) \ + -DFORTRAN_SO=$(FORTRAN_SONAME) \ + -DGCJ_SO=$(PKG_GCJ_EXT) \ + -DLIBGCJ_EXT=$(PKG_LIBGCJ_EXT) \ + -DGNAT_SO=$(GNAT_SONAME) \ + -DGNAT_V=$(GNAT_VERSION) \ + -DGOMP_SO=$(GOMP_SONAME) \ + -DGCCMATH_SO=$(GCCMATH_SONAME) \ + -DMF_SO=$(MUDFLAP_SONAME) \ + -DSSP_SO=$(SSP_SONAME) \ + -Denabled_languages="$(languages) $(addons)" \ + -Dada_no_archs="$(ada_no_archs)" \ + -Djava_no_archs="$(java_no_archs)" \ + -Dfortran_no_archs="$(fortran_no_archs)" \ + -Dlibgc_no_archs="$(libgc_no_archs)" \ + -Dcheck_no_archs="$(check_no_archs)" \ + -Dlocale_no_archs="$(locale_no_archs)" \ + -Dlinux_gnu_archs="$(linux_gnu_archs)" \ + -Dbiarch32_archs="$(strip $(subst /, ,$(biarch32archs)))" \ + -Dbiarch64_archs="$(strip $(subst /, ,$(biarch64archs)))" \ + -Dbiarchn32_archs="$(strip $(subst /, ,$(biarchn32archs)))" \ + debian/control.m4 > debian/control.tmp2 + uniq debian/control.tmp2 | sed '/^Build/s/ *, */, /g' \ + > debian/control.tmp + rm -f debian/control.tmp2 + [ -e debian/control ] \ + && cmp -s debian/control debian/control.tmp \ + && rm -f debian/control.tmp && exit 0; \ + mv debian/control.tmp debian/control; touch $(control_stamp) + +readme-bugs-file: + m4 -DDIST=$(distribution) -DSRCNAME=$(PKGSOURCE) \ + debian/README.Bugs.m4 > debian/README.Bugs + +copyright-file: + rm -f debian/copyright + if echo $(SOURCE_VERSION) | grep -E ^'[0-9]\.[0-9]-[0-9]{8}' ; \ + then SVN_BRANCH="trunk" ; \ + else \ + SVN_BRANCH="gcc-$(subst .,_,$(BASE_VERSION))-branch" ; \ + fi ; \ + sed debian/copyright.in \ + -e "s/@BV@/$(BASE_VERSION)/g" \ + -e "s/@SVN_BRANCH@/$$SVN_BRANCH/g" \ + > debian/copyright + +substvars-file: + rm -f debian/substvars.local.tmp + ( \ + echo 'gcc:Version=$(DEB_GCC_VERSION)'; \ + echo 'gcc:EpochVersion=$(DEB_EVERSION)'; \ + echo 'gcc:SoftVersion=$(DEB_GCC_SOFT_VERSION)'; \ + echo 'gdc:Version=$(DEB_GDC_VERSION)'; \ + echo 'gcj:Version=$(DEB_GCJ_VERSION)'; \ + echo 'gcj:SoftVersion=$(DEB_GCJ_SOFT_VERSION)'; \ + echo 'gcj:BaseVersion=$(BASE_VERSION)'; \ + echo 'gnat:Version=$(DEB_GNAT_VERSION)'; \ + echo 'binutils:Version=$(BINUTILSV)'; \ + echo 'dep:libgcc=$(LIBGCC_DEP)'; \ + echo 'dep:libgccbiarch=$(LIBGCC_BIARCH_DEP)'; \ + echo 'dep:libcdev=$(LIBC_DEV_DEP)'; \ + echo 'dep:libcbiarch=$(LIBC_BIARCH_DEP)'; \ + echo 'dep:libcbiarchdev=$(LIBC_BIARCH_DEV_DEP)'; \ + echo 'dep:libunwinddev=$(LIBUNWIND_DEV_DEP)'; \ + echo 'dep:libcxxbiarch=$(LIBCXX_BIARCH_DEP)'; \ + echo 'dep:libcxxbiarchdbg=$(LIBCXX_BIARCH_DBG_DEP)'; \ + echo 'dep:libgnat=$(LIBGNAT_DEP)'; \ + echo 'dep:ecj=$(ECJ_DEP)'; \ + echo 'dep:libcloog=$(CLOOG_RUNTIME_DEP)'; \ + ) > debian/substvars.local.tmp +ifneq (,$(filter $(DEB_TARGET_ARCH), $(multilib_archs))) + ( \ + echo 'gcc:multilib=gcc-$(BASE_VERSION)-multilib$(TS)'; \ + echo 'gxx:multilib=g++-$(BASE_VERSION)-multilib$(TS)'; \ + echo 'gobjc:multilib=gobjc-$(BASE_VERSION)-multilib$(TS)'; \ + echo 'gobjcxx:multilib=gobjc++-$(BASE_VERSION)-multilib$(TS)'; \ + echo 'gfortran:multilib=gfortran-$(BASE_VERSION)-multilib$(TS)'; \ + ) >> debian/substvars.local.tmp +endif +ifeq ($(with_gold),yes) + echo 'dep:gold=binutils-gold (>= $(BINUTILSV))' \ + >> debian/substvars.local.tmp +endif +ifeq ($(with_libssp),yes) + echo 'dep:libssp=libssp$(SSP_SONAME) (>= $${gcc:Version})' \ + >> debian/substvars.local.tmp +endif +ifeq ($(with_gomp),yes) + echo 'dep:libgomp=libgomp$(GOMP_SONAME)$(LS) (>= $${gcc:Version})' \ + >> debian/substvars.local.tmp +endif +ifeq ($(multilib),yes) + echo 'dep:libgfortranbiarch=$(libgfortranbiarch)' \ + >> debian/substvars.local.tmp + echo 'dep:libobjcbiarch=$(libobjcbiarch)' \ + >> debian/substvars.local.tmp + ifeq ($(with_mudflap),yes) + echo 'dep:libmudflapbiarch=$(libmudflapbiarch)' \ + >> debian/substvars.local.tmp + endif + ifeq ($(with_libssp),yes) + echo 'dep:libsspbiarch=$(libsspbiarch)' \ + >> debian/substvars.local.tmp + endif + ifeq ($(with_gomp),yes) + echo 'dep:libgompbiarch=$(libgompbiarch)' \ + >> debian/substvars.local.tmp + endif +endif +ifneq ($(with_standalone_gcj),yes) + ifneq (,$(filter $(DEB_HOST_ARCH),armel armhf)) + echo 'dep:gcj=g++$(pkg_ver) (>= $(DEB_GCC_SOFT_VERSION))' \ + >> debian/substvars.local.tmp + else + echo 'dep:gcj=gcc$(pkg_ver) (>= $(DEB_GCC_SOFT_VERSION))' \ + >> debian/substvars.local.tmp + endif +endif +#ifneq (,$(findstring gtk, $(java_awt_peers))) +# echo 'pkg:gcjgtk=libgcj$(subst 0,,$(GCJ_SONAME))-awt-gtk (>= $(DEB_GCJ_VERSION))' \ +# >> debian/substvars.local.tmp +#endif +#ifneq (,$(findstring qt, $(java_awt_peers))) +# echo 'pkg:gcjqt=libgcj$(subst 0,,$(GCJ_SONAME))-awt-qt (>= $(DEB_GCJ_VERSION))' \ +# >> debian/substvars.local.tmp +#endif +ifeq ($(DEB_HOST_ARCH),hppa) + echo 'dep:prctl=prctl' >> debian/substvars.local.tmp +endif +ifneq (,$(filter $(DEB_TARGET_ARCH), powerpc ppc64)) + echo 'base:Replaces=gcc-$(BASE_VERSION)-spu (<< 4.4.0-1)' >> debian/substvars.local.tmp +endif +ifeq ($(distribution)-$(DEB_HOST_ARCH),Debian-amd64) + echo 'confl:lib32=libc6-i386 (<< 2.9-22)' >> debian/substvars.local.tmp +endif + [ -e debian/substvars.local ] \ + && cmp -s debian/substvars.local debian/substvars.local.tmp \ + && rm -f debian/substvars.local.tmp && exit 0; \ + mv debian/substvars.local.tmp debian/substvars.local; \ + touch $(control_stamp) + +parameters-file: + rm -f debian/rules.parameters.tmp + ( \ + echo '# configuration parameters taken from upstream source files'; \ + echo 'GCC_VERSION := $(GCC_VERSION)'; \ + echo 'NEXT_GCC_VERSION := $(NEXT_GCC_VERSION)'; \ + echo 'BASE_VERSION := $(BASE_VERSION)'; \ + echo 'SOURCE_VERSION := $(SOURCE_VERSION)'; \ + echo 'DEB_VERSION := $(DEB_VERSION)'; \ + echo 'DEB_EVERSION := $(DEB_EVERSION)'; \ + echo 'GDC_BASE_VERSION := $(GDC_BASE_VERSION)'; \ + echo 'DEB_GDC_VERSION := $(DEB_GDC_VERSION)'; \ + echo 'DEB_SOVERSION := $(DEB_SOVERSION)'; \ + echo 'DEB_SOEVERSION := $(DEB_SOEVERSION)'; \ + echo 'DEB_LIBGCC_SOVERSION := $(DEB_LIBGCC_SOVERSION)'; \ + echo 'DEB_LIBGCC_VERSION := $(DEB_LIBGCC_VERSION)'; \ + echo 'DEB_STDCXX_SOVERSION := $(DEB_STDCXX_SOVERSION)'; \ + echo 'DEB_GCJ_SOVERSION := $(DEB_GCJ_SOVERSION)'; \ + echo 'PKG_GCJ_EXT := $(PKG_GCJ_EXT)'; \ + echo 'PKG_LIBGCJ_EXT := $(PKG_LIBGCJ_EXT)'; \ + echo 'DEB_GOMP_SOVERSION := $(DEB_GOMP_SOVERSION)'; \ + echo 'DEB_GCCMATH_SOVERSION := $(DEB_GCCMATH_SOVERSION)'; \ + echo 'GCC_SONAME := $(GCC_SONAME)'; \ + echo 'CXX_SONAME := $(CXX_SONAME)'; \ + echo 'FORTRAN_SONAME := $(FORTRAN_SONAME)'; \ + echo 'OBJC_SONAME := $(OBJC_SONAME)'; \ + echo 'GCJ_SONAME := $(GCJ_SONAME)'; \ + echo 'GNAT_VERSION := $(GNAT_VERSION)'; \ + echo 'GNAT_SONAME := $(GNAT_SONAME)'; \ + echo 'FFI_SONAME := $(FFI_SONAME)'; \ + echo 'MUDFLAP_SONAME := $(MUDFLAP_SONAME)'; \ + echo 'SSP_SONAME := $(SSP_SONAME)'; \ + echo 'GOMP_SONAME := $(GOMP_SONAME)'; \ + echo 'GCCMATH_SONAME := $(GCCMATH_SONAME)'; \ + echo 'LIBC_DEP := $(LIBC_DEP)'; \ + ) > debian/rules.parameters.tmp + [ -e debian/rules.parameters ] \ + && cmp -s debian/rules.parameters debian/rules.parameters.tmp \ + && rm -f debian/rules.parameters.tmp && exit 0; \ + mv debian/rules.parameters.tmp debian/rules.parameters; \ + touch $(control_stamp) + +versioned-files: + fs=`echo debian/*BV* debian/*GCJ* debian/*CXX* debian/*LC* debian/*MF* | sort -u`; \ + for f in $$fs debian/source.lintian-overrides.in; do \ + [ -f $$f ] || echo "CANNOT FIND $$f"; \ + [ -f $$f ] || continue; \ + if [ -z "$(DEB_CROSS)" ]; then case "$$f" in *-CR*) continue; esac; fi; \ + f2=$$(echo $$f \ + | sed 's/BV/$(BASE_VERSION)/;s/CXX/$(CXX_SONAME)/;s/LGCJ/$(PKG_LIBGCJ_EXT)/;s/GCJ/$(PKG_GCJ_EXT)/;s/LC/$(GCC_SONAME)/;s/MF/$(MUDFLAP_SONAME)/;s/-CRB/$(cross_bin_arch)/;s/\.in$$//'); \ + sed -e 's/@BV@/$(BASE_VERSION)/g' \ + -e 's/@CXX@/$(CXX_SONAME)/g' \ + -e 's/@LGCJ@/$(PKG_LIBGCJ_EXT)/g' \ + -e 's/@GCJ@/$(PKG_GCJ_EXT)/g' \ + -e 's/@GCJSO@/$(GCJ_SONAME)/g' \ + -e 's/@LC@/$(GCC_SONAME)/g' \ + -e 's/@MF@/$(MUDFLAP_SONAME)/g' \ + -e 's/@SRC@/$(PKGSOURCE)/g' \ + -e 's/@GFDL@/$(if $(filter yes,$(GFDL_INVARIANT_FREE)),#)/g' \ + -e 's/@java_priority@/$(java_priority)/g' \ + -e 's/@gcc_priority@/$(subst .,,$(BASE_VERSION))/g' \ + -e 's/@TARGET@/$(DEB_TARGET_GNU_TYPE)/g' \ + $$f > $$f2; \ + touch -r $$f $$f2; \ + done --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.m68k +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.m68k @@ -0,0 +1,5 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" + __gxx_personality_v0@CXXABI_1.3 4.1.1 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0 --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.common +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.common @@ -0,0 +1,2948 @@ + CXXABI_1.3.1@CXXABI_1.3.1 4.1.1 + CXXABI_1.3.2@CXXABI_1.3.2 4.3 + CXXABI_1.3.3@CXXABI_1.3.3 4.4.0 + CXXABI_1.3.4@CXXABI_1.3.4 4.5 + CXXABI_1.3@CXXABI_1.3 4.1.1 + GLIBCXX_3.4.10@GLIBCXX_3.4.10 4.3 + GLIBCXX_3.4.11@GLIBCXX_3.4.11 4.4.0 + GLIBCXX_3.4.12@GLIBCXX_3.4.12 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_ZTVSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1 + _ZTVSt9bad_alloc@GLIBCXX_3.4 4.1.1 + _ZTVSt9basic_iosIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1 + _ZTVSt9basic_iosIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1 + _ZTVSt9exception@GLIBCXX_3.4 4.1.1 + _ZTVSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1 + _ZTVSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1 + _ZTVSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1 + _ZTVSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1 + _ZTVSt9strstream@GLIBCXX_3.4 4.1.1 + _ZTVSt9type_info@GLIBCXX_3.4 4.1.1 + _ZdaPv@GLIBCXX_3.4 4.1.1 + _ZdaPvRKSt9nothrow_t@GLIBCXX_3.4 4.1.1 + _ZdlPv@GLIBCXX_3.4 4.1.1 + _ZdlPvRKSt9nothrow_t@GLIBCXX_3.4 4.1.1 + __atomic_flag_for_address@GLIBCXX_3.4.11 4.4.0 + __atomic_flag_wait_explicit@GLIBCXX_3.4.11 4.4.0 + __cxa_allocate_exception@CXXABI_1.3 4.1.1 + __cxa_bad_cast@CXXABI_1.3 4.1.1 + __cxa_bad_typeid@CXXABI_1.3 4.1.1 + __cxa_begin_catch@CXXABI_1.3 4.1.1 + __cxa_call_unexpected@CXXABI_1.3 4.1.1 + __cxa_current_exception_type@CXXABI_1.3 4.1.1 + __cxa_demangle@CXXABI_1.3 4.1.1 + __cxa_end_catch@CXXABI_1.3 4.1.1 + __cxa_free_exception@CXXABI_1.3 4.1.1 + __cxa_get_exception_ptr@CXXABI_1.3.1 4.1.1 + __cxa_get_globals@CXXABI_1.3 4.1.1 + __cxa_get_globals_fast@CXXABI_1.3 4.1.1 + __cxa_guard_abort@CXXABI_1.3 4.1.1 + __cxa_guard_acquire@CXXABI_1.3 4.1.1 + __cxa_guard_release@CXXABI_1.3 4.1.1 + __cxa_pure_virtual@CXXABI_1.3 4.1.1 + __cxa_rethrow@CXXABI_1.3 4.1.1 + __cxa_throw@CXXABI_1.3 4.1.1 + __cxa_vec_cctor@CXXABI_1.3 4.1.1 + __cxa_vec_cleanup@CXXABI_1.3 4.1.1 + __cxa_vec_ctor@CXXABI_1.3 4.1.1 + __cxa_vec_delete2@CXXABI_1.3 4.1.1 + __cxa_vec_delete3@CXXABI_1.3 4.1.1 + __cxa_vec_delete@CXXABI_1.3 4.1.1 + __cxa_vec_dtor@CXXABI_1.3 4.1.1 + __cxa_vec_new2@CXXABI_1.3 4.1.1 + __cxa_vec_new3@CXXABI_1.3 4.1.1 + __cxa_vec_new@CXXABI_1.3 4.1.1 + __dynamic_cast@CXXABI_1.3 4.1.1 + __once_proxy@GLIBCXX_3.4.11 4.4.0 + atomic_flag_clear_explicit@GLIBCXX_3.4.11 4.4.0 + atomic_flag_test_and_set_explicit@GLIBCXX_3.4.11 4.4.0 --- gcc-4.5-4.5.2.orig/debian/gnat.1 +++ gcc-4.5-4.5.2/debian/gnat.1 @@ -0,0 +1,39 @@ +.\" Hey, Emacs! This is an -*- nroff -*- source file. +.\" +.\" Copyright (C) 1996 Erick Branderhorst +.\" +.\" This is free software; you can redistribute it and/or modify it under +.\" the terms of the GNU General Public License as published by the Free +.\" Software Foundation; either version 2, or (at your option) any later +.\" version. +.\" +.\" This is distributed in the hope that it will be useful, but WITHOUT +.\" ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +.\" FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +.\" for more details. +.\" +.\" You should have received a copy of the GNU General Public License with +.\" your Debian GNU/Linux system, in /usr/doc/copyright/GPL, or with the +.\" dpkg source package as the file COPYING. If not, write to the Free +.\" Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +.\" +.\" +.TH "GNAT TOOLBOX" 1 "Jun 2002" "Debian Project" "Debian Linux" +.SH NAME +gnat, gnatbind, gnatbl, gnatchop, gnatfind, gnatkr, gnatlink, +gnatls, gnatmake, gnatprep, gnatpsta, gnatpsys, gnatxref \- +GNAT toolbox +.SH DESCRIPTION +Those programs are part of GNU GNAT 4.1, a freely available Ada 95 compiler. +.PP +For accessing the full GNAT manuals, use +.B info gnat-ug-4.1 +and +.B info gnat-rm-4.1 +for the sections related to the reference manual. If those sections cannot +be found, you will have to install the gnat-3.4-doc package as well. +.SH SEE ALSO +.BR gcc-4.1 (1) +.SH AUTHOR +This manpage has been written by Samuel Tardieu , for the +Debian GNU/Linux project. --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.hurd-i386 +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.hurd-i386 @@ -0,0 +1,101 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 4.2.1 + GCC_3.3.1@GCC_3.3.1 4.2.1 + GCC_3.3@GCC_3.3 4.2.1 + GCC_3.4.2@GCC_3.4.2 4.2.1 + GCC_3.4@GCC_3.4 4.2.1 + GCC_4.0.0@GCC_4.0.0 4.2.1 + GCC_4.2.0@GCC_4.2.0 4.2.1 + GCC_4.3.0@GCC_4.3.0 1:4.3.0 + GLIBC_2.0@GLIBC_2.0 4.2.1 + _Unwind_Backtrace@GCC_3.3 4.2.1 + _Unwind_DeleteException@GCC_3.0 4.2.1 + _Unwind_FindEnclosingFunction@GCC_3.3 4.2.1 + _Unwind_Find_FDE@GCC_3.0 4.2.1 + _Unwind_ForcedUnwind@GCC_3.0 4.2.1 + _Unwind_GetCFA@GCC_3.3 4.2.1 + _Unwind_GetDataRelBase@GCC_3.0 4.2.1 + _Unwind_GetGR@GCC_3.0 4.2.1 + _Unwind_GetIP@GCC_3.0 4.2.1 + _Unwind_GetIPInfo@GCC_4.2.0 4.2.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 4.2.1 + _Unwind_GetRegionStart@GCC_3.0 4.2.1 + _Unwind_GetTextRelBase@GCC_3.0 4.2.1 + _Unwind_RaiseException@GCC_3.0 4.2.1 + _Unwind_Resume@GCC_3.0 4.2.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 4.2.1 + _Unwind_SetGR@GCC_3.0 4.2.1 + _Unwind_SetIP@GCC_3.0 4.2.1 + __absvdi2@GCC_3.0 4.2.1 + __absvsi2@GCC_3.0 4.2.1 + __addvdi3@GCC_3.0 4.2.1 + __addvsi3@GCC_3.0 4.2.1 + __ashldi3@GCC_3.0 4.2.1 + __ashrdi3@GCC_3.0 4.2.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 4.2.1 + __clzdi2@GCC_3.4 4.2.1 + __clzsi2@GCC_3.4 4.2.1 + __cmpdi2@GCC_3.0 4.2.1 + __ctzdi2@GCC_3.4 4.2.1 + __ctzsi2@GCC_3.4 4.2.1 + __deregister_frame@GLIBC_2.0 4.2.1 + __deregister_frame_info@GLIBC_2.0 4.2.1 + __deregister_frame_info_bases@GCC_3.0 4.2.1 + __divdc3@GCC_4.0.0 4.2.1 + __divdi3@GLIBC_2.0 4.2.1 + __divsc3@GCC_4.0.0 4.2.1 + __divxc3@GCC_4.0.0 4.2.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 4.2.1 + __ffsdi2@GCC_3.0 4.2.1 + __ffssi2@GCC_4.3.0 1:4.3 + __fixdfdi@GCC_3.0 4.2.1 + __fixsfdi@GCC_3.0 4.2.1 + __fixunsdfdi@GCC_3.0 4.2.1 + __fixunsdfsi@GCC_3.0 4.2.1 + __fixunssfdi@GCC_3.0 4.2.1 + __fixunssfsi@GCC_3.0 4.2.1 + __fixunsxfdi@GCC_3.0 4.2.1 + __fixunsxfsi@GCC_3.0 4.2.1 + __fixxfdi@GCC_3.0 4.2.1 + __floatdidf@GCC_3.0 4.2.1 + __floatdisf@GCC_3.0 4.2.1 + __floatdixf@GCC_3.0 4.2.1 + __floatundidf@GCC_4.2.0 4.2.1 + __floatundisf@GCC_4.2.0 4.2.1 + __floatundixf@GCC_4.2.0 4.2.1 + __frame_state_for@GLIBC_2.0 4.2.1 + __gcc_personality_v0@GCC_3.3.1 4.2.1 + __lshrdi3@GCC_3.0 4.2.1 + __moddi3@GLIBC_2.0 4.2.1 + __muldc3@GCC_4.0.0 4.2.1 + __muldi3@GCC_3.0 4.2.1 + __mulsc3@GCC_4.0.0 4.2.1 + __mulvdi3@GCC_3.0 4.2.1 + __mulvsi3@GCC_3.0 4.2.1 + __mulxc3@GCC_4.0.0 4.2.1 + __negdi2@GCC_3.0 4.2.1 + __negvdi2@GCC_3.0 4.2.1 + __negvsi2@GCC_3.0 4.2.1 + __paritydi2@GCC_3.4 4.2.1 + __paritysi2@GCC_3.4 4.2.1 + __popcountdi2@GCC_3.4 4.2.1 + __popcountsi2@GCC_3.4 4.2.1 + __powidf2@GCC_4.0.0 4.2.1 + __powisf2@GCC_4.0.0 4.2.1 + __powixf2@GCC_4.0.0 4.2.1 + __register_frame@GLIBC_2.0 4.2.1 + __register_frame_info@GLIBC_2.0 4.2.1 + __register_frame_info_bases@GCC_3.0 4.2.1 + __register_frame_info_table@GLIBC_2.0 4.2.1 + __register_frame_info_table_bases@GCC_3.0 4.2.1 + __register_frame_table@GLIBC_2.0 4.2.1 + __subvdi3@GCC_3.0 4.2.1 + __subvsi3@GCC_3.0 4.2.1 + __ucmpdi2@GCC_3.0 4.2.1 + __udivdi3@GLIBC_2.0 4.2.1 + __udivmoddi4@GCC_3.0 4.2.1 + __umoddi3@GLIBC_2.0 4.2.1 --- gcc-4.5-4.5.2.orig/debian/gfortran-BV-doc.doc-base +++ gcc-4.5-4.5.2/debian/gfortran-BV-doc.doc-base @@ -0,0 +1,14 @@ +Document: gfortran-@BV@ +Title: The GNU Fortran Compiler +Author: Various +Abstract: This manual documents how to run, install and port `gfortran', + as well as its new features and incompatibilities, and how to report bugs. +Section: Programming/Fortran + +Format: html +Index: /usr/share/doc/gcc-@BV@-base/fortran/gfortran.html +Files: /usr/share/doc/gcc-@BV@-base/fortran/gfortran.html + +Format: info +Index: /usr/share/info/gfortran-@BV@.info.gz +Files: /usr/share/info/gfortran-@BV@* --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.common +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.common @@ -0,0 +1,742 @@ + F2C_1.0@F2C_1.0 4.3 + GFORTRAN_1.0@GFORTRAN_1.0 4.3 + GFORTRAN_1.1@GFORTRAN_1.1 4.4.0 + GFORTRAN_1.2@GFORTRAN_1.2 4.4.0 + GFORTRAN_C99_1.0@GFORTRAN_C99_1.0 4.3 + GFORTRAN_C99_1.1@GFORTRAN_C99_1.1 4.5 + __iso_c_binding_c_f_pointer@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_c4@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_c8@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_d0@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_i1@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_i2@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_i4@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_i8@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_l1@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_l2@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_l4@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_l8@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_r4@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_r8@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_s0@GFORTRAN_1.0 4.3 + __iso_c_binding_c_f_pointer_u0@GFORTRAN_1.0 4.3 + _gfortran_abort@GFORTRAN_1.0 4.3 + _gfortran_access_func@GFORTRAN_1.0 4.3 + _gfortran_adjustl@GFORTRAN_1.0 4.3 + _gfortran_adjustl_char4@GFORTRAN_1.1 4.4.0 + _gfortran_adjustr@GFORTRAN_1.0 4.3 + _gfortran_adjustr_char4@GFORTRAN_1.1 4.4.0 + _gfortran_alarm_sub_i4@GFORTRAN_1.0 4.3 + _gfortran_alarm_sub_i8@GFORTRAN_1.0 4.3 + _gfortran_alarm_sub_int_i4@GFORTRAN_1.0 4.3 + _gfortran_alarm_sub_int_i8@GFORTRAN_1.0 4.3 + _gfortran_all_l1@GFORTRAN_1.0 4.3 + _gfortran_all_l2@GFORTRAN_1.0 4.3 + _gfortran_all_l4@GFORTRAN_1.0 4.3 + _gfortran_all_l8@GFORTRAN_1.0 4.3 + _gfortran_any_l1@GFORTRAN_1.0 4.3 + _gfortran_any_l2@GFORTRAN_1.0 4.3 + _gfortran_any_l4@GFORTRAN_1.0 4.3 + _gfortran_any_l8@GFORTRAN_1.0 4.3 + _gfortran_arandom_r4@GFORTRAN_1.0 4.3 + _gfortran_arandom_r8@GFORTRAN_1.0 4.3 + _gfortran_associated@GFORTRAN_1.0 4.3 + _gfortran_chdir_i4@GFORTRAN_1.0 4.3 + _gfortran_chdir_i4_sub@GFORTRAN_1.0 4.3 + _gfortran_chdir_i8@GFORTRAN_1.0 4.3 + _gfortran_chdir_i8_sub@GFORTRAN_1.0 4.3 + _gfortran_chmod_func@GFORTRAN_1.0 4.3 + _gfortran_chmod_i4_sub@GFORTRAN_1.0 4.3 + _gfortran_chmod_i8_sub@GFORTRAN_1.0 4.3 + _gfortran_compare_string@GFORTRAN_1.0 4.3 + _gfortran_compare_string_char4@GFORTRAN_1.1 4.4.0 + _gfortran_concat_string@GFORTRAN_1.0 4.3 + _gfortran_concat_string_char4@GFORTRAN_1.1 4.4.0 + _gfortran_convert_char1_to_char4@GFORTRAN_1.1 4.4.0 + _gfortran_convert_char4_to_char1@GFORTRAN_1.1 4.4.0 + _gfortran_count_1_l@GFORTRAN_1.0 4.3 + _gfortran_count_2_l@GFORTRAN_1.0 4.3 + _gfortran_count_4_l@GFORTRAN_1.0 4.3 + _gfortran_count_8_l@GFORTRAN_1.0 4.3 + _gfortran_cpu_time_4@GFORTRAN_1.0 4.3 + _gfortran_cpu_time_8@GFORTRAN_1.0 4.3 + _gfortran_cshift0_1@GFORTRAN_1.0 4.3 + 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_gfortran_string_trim_char4@GFORTRAN_1.1 4.4.0 + _gfortran_string_verify@GFORTRAN_1.0 4.3 + _gfortran_string_verify_char4@GFORTRAN_1.1 4.4.0 + _gfortran_sum_c4@GFORTRAN_1.0 4.3 + _gfortran_sum_c8@GFORTRAN_1.0 4.3 + _gfortran_sum_i1@GFORTRAN_1.0 4.3 + _gfortran_sum_i2@GFORTRAN_1.0 4.3 + _gfortran_sum_i4@GFORTRAN_1.0 4.3 + _gfortran_sum_i8@GFORTRAN_1.0 4.3 + _gfortran_sum_r4@GFORTRAN_1.0 4.3 + _gfortran_sum_r8@GFORTRAN_1.0 4.3 + _gfortran_symlnk_i4@GFORTRAN_1.0 4.3 + _gfortran_symlnk_i4_sub@GFORTRAN_1.0 4.3 + _gfortran_symlnk_i8@GFORTRAN_1.0 4.3 + _gfortran_symlnk_i8_sub@GFORTRAN_1.0 4.3 + _gfortran_system@GFORTRAN_1.0 4.3 + _gfortran_system_clock_4@GFORTRAN_1.0 4.3 + _gfortran_system_clock_8@GFORTRAN_1.0 4.3 + _gfortran_system_sub@GFORTRAN_1.0 4.3 + _gfortran_time8_func@GFORTRAN_1.0 4.3 + _gfortran_time_func@GFORTRAN_1.0 4.3 + _gfortran_transfer_array@GFORTRAN_1.0 4.3 + _gfortran_transfer_character@GFORTRAN_1.0 4.3 + _gfortran_transfer_character_wide@GFORTRAN_1.1 4.4.0 + _gfortran_transfer_complex@GFORTRAN_1.0 4.3 + _gfortran_transfer_integer@GFORTRAN_1.0 4.3 + _gfortran_transfer_logical@GFORTRAN_1.0 4.3 + _gfortran_transfer_real@GFORTRAN_1.0 4.3 + _gfortran_transpose@GFORTRAN_1.0 4.3 + _gfortran_transpose_c4@GFORTRAN_1.0 4.3 + _gfortran_transpose_c8@GFORTRAN_1.0 4.3 + _gfortran_transpose_char4@GFORTRAN_1.1 4.4.0 + _gfortran_transpose_char@GFORTRAN_1.0 4.3 + _gfortran_transpose_i4@GFORTRAN_1.0 4.3 + _gfortran_transpose_i8@GFORTRAN_1.0 4.3 + _gfortran_transpose_r4@GFORTRAN_1.0 4.3 + _gfortran_transpose_r8@GFORTRAN_1.0 4.3 + _gfortran_ttynam@GFORTRAN_1.0 4.3 + _gfortran_ttynam_sub@GFORTRAN_1.0 4.3 + _gfortran_umask_i4@GFORTRAN_1.0 4.3 + _gfortran_umask_i4_sub@GFORTRAN_1.0 4.3 + _gfortran_umask_i8@GFORTRAN_1.0 4.3 + _gfortran_umask_i8_sub@GFORTRAN_1.0 4.3 + _gfortran_unlink@GFORTRAN_1.0 4.3 + _gfortran_unlink_i4_sub@GFORTRAN_1.0 4.3 + _gfortran_unlink_i8_sub@GFORTRAN_1.0 4.3 + _gfortran_unpack0@GFORTRAN_1.0 4.3 + _gfortran_unpack0_char4@GFORTRAN_1.1 4.4.0 + _gfortran_unpack0_char@GFORTRAN_1.0 4.3 + _gfortran_unpack1@GFORTRAN_1.0 4.3 + _gfortran_unpack1_char4@GFORTRAN_1.1 4.4.0 + _gfortran_unpack1_char@GFORTRAN_1.0 4.3 --- gcc-4.5-4.5.2.orig/debian/control +++ gcc-4.5-4.5.2/debian/control @@ -0,0 +1,666 @@ +Source: gcc-4.5 +Section: devel +Priority: optional +Maintainer: Ubuntu Core developers +XSBC-Original-Maintainer: Debian GCC Maintainers +Uploaders: Matthias Klose , Arthur Loiret +Standards-Version: 3.9.1 +Build-Depends: dpkg-dev (>= 1.16.0~ubuntu4), debhelper (>= 5.0.62), g++-multilib [amd64 i386 mips mipsel powerpc ppc64 s390 sparc kfreebsd-amd64], libc6.1-dev (>= 2.13-0ubuntu6) [alpha ia64] | libc0.3-dev (>= 2.13-0ubuntu6) [hurd-i386] | libc0.1-dev (>= 2.13-0ubuntu6) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= 2.13-0ubuntu6), libc6-dev-amd64 [i386], libc6-dev-sparc64 [sparc], libc6-dev-s390x [s390], libc6-dev-i386 [amd64], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64], lib64gcc1 [i386 powerpc sparc s390], libc6-dev-mips64 [mips mipsel], libc6-dev-mipsn32 [mips mipsel], m4, libtool, autoconf2.64, automake (>= 1:1.11), automake (<< 1:1.12), libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], zlib1g-dev, gawk, lzma, xz-utils, patchutils, binutils (>= 2.20.1-14~) | binutils-multiarch (>= 2.20.1-14~), binutils-hppa64 (>= 2.20.1-14~) [hppa], gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext, texinfo (>= 4.3), locales [!m68k !knetbsd-i386 !knetbsd-alpha], procps, sharutils, binutils-spu (>= 2.20.1-14~) [powerpc ppc64], newlib-spu (>= 1.16.0) [powerpc ppc64], libcloog-ppl-dev (>= 0.15.9-2~), libmpc-dev, libmpfr-dev, libgmp3-dev, libelfg0-dev (>= 0.8.12), dejagnu [!m68k !hurd-i386 !hurd-alpha], autogen, realpath (>= 1.9.12), chrpath, lsb-release, make (>= 3.81), quilt +Build-Depends-Indep: doxygen (>= 1.4.2), graphviz (>= 2.2), gsfonts-x11, texlive-latex-base, +Build-Conflicts: binutils-gold +Homepage: http://gcc.gnu.org/ +XS-Vcs-Browser: http://svn.debian.org/viewsvn/gcccvs/branches/sid/gcc-4.5/ +XS-Vcs-Svn: svn://svn.debian.org/svn/gcccvs/branches/sid/gcc-4.5 + +Package: gcc-4.5-base +Architecture: any +Multi-Arch: same +Section: libs +Priority: required +Depends: ${misc:Depends} +Replaces: ${base:Replaces} +Description: The GNU Compiler Collection (base package) + This package contains files common to all languages and libraries + contained in the GNU Compiler Collection (GCC). + +Package: libgcc1 +Architecture: any +Section: libs +Priority: required +Depends: gcc-4.5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Multi-Arch: same +Pre-Depends: multiarch-support +Description: GCC support library + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. + +Package: libgcc1-dbg +Architecture: any +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), libgcc1 (= ${gcc:EpochVersion}), ${misc:Depends} +Multi-Arch: same +Description: GCC support library (debug symbols) + Debug symbols for the GCC support library. + +Package: libgcc2 +Architecture: m68k +Section: libs +Priority: required +Depends: gcc-4.5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Multi-Arch: same +Pre-Depends: multiarch-support +Description: GCC support library + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. + +Package: libgcc2-dbg +Architecture: m68k +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), libgcc2 (= ${gcc:Version}), ${misc:Depends} +Multi-Arch: same +Description: GCC support library (debug symbols) + Debug symbols for the GCC support library. + +Package: libgcc4 +Architecture: hppa +Multi-Arch: same +Pre-Depends: multiarch-support +Section: libs +Priority: required +Depends: gcc-4.5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: GCC support library + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. + +Package: libgcc4-dbg +Architecture: hppa +Multi-Arch: same +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), libgcc4 (= ${gcc:Version}), ${misc:Depends} +Description: GCC support library (debug symbols) + Debug symbols for the GCC support library. + +Package: lib64gcc1 +Architecture: i386 powerpc sparc s390 mips mipsel +Section: libs +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} +Conflicts: libgcc1 (<= 1:3.3-0pre9) +Description: GCC support library (64bit) + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. + +Package: lib64gcc1-dbg +Architecture: i386 powerpc sparc s390 mips mipsel +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), lib64gcc1 (= ${gcc:EpochVersion}), ${misc:Depends} +Description: GCC support library (debug symbols) + Debug symbols for the GCC support library. + +Package: lib32gcc1 +Architecture: amd64 ppc64 kfreebsd-amd64 +Section: libs +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} +Conflicts: ${confl:lib32} +Description: GCC support library (32 bit Version) + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. + +Package: lib32gcc1-dbg +Architecture: amd64 ppc64 kfreebsd-amd64 +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), lib32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends} +Description: GCC support library (debug symbols) + Debug symbols for the GCC support library. + +Package: libn32gcc1 +Architecture: mips mipsel +Section: libs +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} +Conflicts: libgcc1 (<= 1:3.3-0pre9) +Description: GCC support library (n32) + Shared version of the support library, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or + special needs for some languages. + +Package: libn32gcc1-dbg +Architecture: mips mipsel +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), libn32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends} +Description: GCC support library (debug symbols) + Debug symbols for the GCC support library. + +Package: gcc-4.5 +Architecture: any +Section: devel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), cpp-4.5 (= ${gcc:Version}), binutils (>= ${binutils:Version}), ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends} +Recommends: ${dep:libcdev} +Suggests: ${gcc:multilib}, libmudflap0-4.5-dev (>= ${gcc:Version}), gcc-4.5-doc (>= ${gcc:SoftVersion}), gcc-4.5-locales (>= ${gcc:SoftVersion}), libgcc1-dbg, libgomp1-dbg, libmudflap0-dbg, ${dep:libcloog}, ${dep:gold} +Provides: c-compiler +Description: The GNU C compiler + This is the GNU C compiler, a fairly portable optimizing compiler for C. + +Package: gcc-4.5-multilib +Architecture: amd64 i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 sparc +Section: devel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gcc-4.5 (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarch}, ${dep:libsspbiarch}, ${dep:libgompbiarch}, ${shlibs:Depends}, ${misc:Depends} +Suggests: ${dep:libmudflapbiarch} +Description: The GNU C compiler (multilib files) + This is the GNU C compiler, a fairly portable optimizing compiler for C. + . + On architectures with multilib support, the package contains files + and dependencies for the non-default multilib architecture(s). + +Package: gcc-4.5-plugin-dev +Architecture: any +Section: devel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gcc-4.5 (= ${gcc:Version}), libgmp3-dev, ${shlibs:Depends}, ${misc:Depends} +Description: Files for GNU GCC plugin development. + This package contains (header) files for GNU GCC plugin development. It + is only used for the development of GCC plugins, but not needed to run + plugins. + +Package: gcc-4.5-hppa64 +Architecture: hppa +Section: devel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Conflicts: gcc-3.3-hppa64 (<= 1:3.3.4-5), gcc-3.4-hppa64 (<= 3.4.1-3) +Description: The GNU C compiler (cross compiler for hppa64) + This is the GNU C compiler, a fairly portable optimizing compiler for C. + +Package: gcc-4.5-spu +Architecture: powerpc ppc64 +Section: devel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), binutils-spu (>= 2.18.1~cvs20080103-3), newlib-spu, ${shlibs:Depends}, ${misc:Depends} +Provides: spu-gcc +Description: SPU cross-compiler (preprocessor and C compiler) + GNU Compiler Collection for the Cell Broadband Engine SPU (preprocessor + and C compiler). + +Package: g++-4.5-spu +Architecture: powerpc ppc64 +Section: devel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gcc-4.5-spu (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Provides: spu-g++ +Description: SPU cross-compiler (C++ compiler) + GNU Compiler Collection for the Cell Broadband Engine SPU (C++ compiler). + +Package: gfortran-4.5-spu +Architecture: powerpc ppc64 +Section: devel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gcc-4.5-spu (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Provides: spu-gfortran +Description: SPU cross-compiler (Fortran compiler) + GNU Compiler Collection for the Cell Broadband Engine SPU (Fortran compiler). + +Package: cpp-4.5 +Architecture: any +Section: interpreters +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Suggests: gcc-4.5-locales (>= ${gcc:SoftVersion}) +Description: The GNU C preprocessor + A macro processor that is used automatically by the GNU C compiler + to transform programs before actual compilation. + . + This package has been separated from gcc for the benefit of those who + require the preprocessor but not the compiler. + +Package: cpp-4.5-doc +Architecture: all +Section: doc +Priority: optional +Depends: gcc-4.5-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends} +Description: Documentation for the GNU C preprocessor (cpp) + Documentation for the GNU C preprocessor in info format. + +Package: gcc-4.5-locales +Architecture: all +Section: devel +Priority: optional +Depends: gcc-4.5-base (>= ${gcc:SoftVersion}), cpp-4.5 (>= ${gcc:SoftVersion}), ${misc:Depends} +Recommends: gcc-4.5 (>= ${gcc:SoftVersion}) +Description: The GNU C compiler (native language support files) + Native language support for GCC. Lets GCC speak your language, + if translations are available. + . + Please do NOT submit bug reports in other languages than "C". + Always reset your language settings to use the "C" locales. + +Package: g++-4.5 +Architecture: any +Section: devel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gcc-4.5 (= ${gcc:Version}), libstdc++6-4.5-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Provides: c++-compiler, c++abi2-dev +Suggests: ${gxx:multilib}, gcc-4.5-doc (>= ${gcc:SoftVersion}), libstdc++6-4.5-dbg +Description: The GNU C++ compiler + This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. + +Package: g++-4.5-multilib +Architecture: amd64 i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 sparc +Section: devel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), g++-4.5 (= ${gcc:Version}), gcc-4.5-multilib (= ${gcc:Version}), ${dep:libcxxbiarch}, ${shlibs:Depends}, ${misc:Depends} +Suggests: ${dep:libcxxbiarchdbg} +Description: The GNU C++ compiler (multilib files) + This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. + . + On architectures with multilib support, the package contains files + and dependencies for the non-default multilib architecture(s). + +Package: libgomp1 +Section: libs +Architecture: any +Multi-Arch: same +Pre-Depends: multiarch-support +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: GCC OpenMP (GOMP) support library + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: libgomp1-dbg +Architecture: any +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), libgomp1 (= ${gcc:Version}), ${misc:Depends} +Multi-Arch: same +Description: GCC OpenMP (GOMP) support library (debug symbols) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: lib32gomp1 +Section: libs +Architecture: amd64 ppc64 kfreebsd-amd64 +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Conflicts: ${confl:lib32} +Description: GCC OpenMP (GOMP) support library (32bit) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: lib32gomp1-dbg +Architecture: amd64 ppc64 kfreebsd-amd64 +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), lib32gomp1 (= ${gcc:Version}), ${misc:Depends} +Description: GCC OpenMP (GOMP) support library (32 bit debug symbols) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: lib64gomp1 +Section: libs +Architecture: i386 powerpc sparc s390 mips mipsel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: GCC OpenMP (GOMP) support library (64bit) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: lib64gomp1-dbg +Architecture: i386 powerpc sparc s390 mips mipsel +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), lib64gomp1 (= ${gcc:Version}), ${misc:Depends} +Description: GCC OpenMP (GOMP) support library (64bit debug symbols) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: libn32gomp1 +Section: libs +Architecture: mips mipsel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: GCC OpenMP (GOMP) support library (n32) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + in the GNU Compiler Collection. + +Package: libn32gomp1-dbg +Architecture: mips mipsel +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), libn32gomp1 (= ${gcc:Version}), ${misc:Depends} +Description: GCC OpenMP (GOMP) support library (n32 debug symbols) + GOMP is an implementation of OpenMP for the C, C++, and Fortran 95 compilers + +Package: gobjc++-4.5 +Architecture: any +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gobjc-4.5 (= ${gcc:Version}), g++-4.5 (= ${gcc:Version}), ${shlibs:Depends}, libobjc2 (>= ${gcc:Version}), ${misc:Depends} +Suggests: ${gobjcxx:multilib}, gcc-4.5-doc (>= ${gcc:SoftVersion}) +Provides: objc++-compiler +Description: The GNU Objective-C++ compiler + This is the GNU Objective-C++ compiler, which compiles + Objective-C++ on platforms supported by the gcc compiler. It uses the + gcc backend to generate optimized code. + +Package: gobjc++-4.5-multilib +Architecture: amd64 i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 sparc +Section: devel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gobjc++-4.5 (= ${gcc:Version}), g++-4.5-multilib (= ${gcc:Version}), gobjc-4.5-multilib (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: The GNU Objective-C++ compiler (multilib files) + This is the GNU Objective-C++ compiler, which compiles Objective-C++ on + platforms supported by the gcc compiler. + . + On architectures with multilib support, the package contains files + and dependencies for the non-default multilib architecture(s). + +Package: gobjc-4.5 +Architecture: any +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gcc-4.5 (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libobjc2 (>= ${gcc:Version}), ${misc:Depends} +Suggests: ${gobjc:multilib}, gcc-4.5-doc (>= ${gcc:SoftVersion}), libobjc2-dbg +Provides: objc-compiler +Description: The GNU Objective-C compiler + This is the GNU Objective-C compiler, which compiles + Objective-C on platforms supported by the gcc compiler. It uses the + gcc backend to generate optimized code. + +Package: gobjc-4.5-multilib +Architecture: amd64 i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 sparc +Section: devel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gobjc-4.5 (= ${gcc:Version}), gcc-4.5-multilib (= ${gcc:Version}), ${dep:libobjcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: The GNU Objective-C compiler (multilib files) + This is the GNU Objective-C compiler, which compiles Objective-C on platforms + supported by the gcc compiler. + . + On architectures with multilib support, the package contains files + and dependencies for the non-default multilib architecture(s). + +Package: libobjc2 +Section: libs +Architecture: any +Multi-Arch: same +Pre-Depends: multiarch-support +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications + Library needed for GNU ObjC applications linked against the shared library. + +Package: libobjc2-dbg +Section: debug +Architecture: any +Multi-Arch: same +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), libobjc2 (= ${gcc:Version}), libgcc1-dbg, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications (debug symbols) + Library needed for GNU ObjC applications linked against the shared library. + +Package: lib64objc2 +Section: libs +Architecture: i386 powerpc sparc s390 mips mipsel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications (64bit) + Library needed for GNU ObjC applications linked against the shared library. + +Package: lib64objc2-dbg +Section: debug +Architecture: i386 powerpc sparc s390 mips mipsel +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), lib64objc2 (= ${gcc:Version}), lib64gcc1-dbg, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications (64 bit debug symbols) + Library needed for GNU ObjC applications linked against the shared library. + +Package: lib32objc2 +Section: libs +Architecture: amd64 ppc64 kfreebsd-amd64 +Priority: optional +Depends: gcc-4.5-base (>= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Conflicts: ${confl:lib32} +Description: Runtime library for GNU Objective-C applications (32bit) + Library needed for GNU ObjC applications linked against the shared library. + +Package: lib32objc2-dbg +Section: debug +Architecture: amd64 ppc64 kfreebsd-amd64 +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), lib32objc2 (= ${gcc:Version}), lib32gcc1-dbg, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications (32 bit debug symbols) + Library needed for GNU ObjC applications linked against the shared library. + +Package: libn32objc2 +Section: libs +Architecture: mips mipsel +Priority: optional +Depends: gcc-4.5-base (>= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications (n32) + Library needed for GNU ObjC applications linked against the shared library. + +Package: libn32objc2-dbg +Section: debug +Architecture: mips mipsel +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), libn32objc2 (= ${gcc:Version}), libn32gcc1-dbg, ${misc:Depends} +Description: Runtime library for GNU Objective-C applications (n32 debug symbols) + Library needed for GNU ObjC applications linked against the shared library. + +Package: gfortran-4.5 +Architecture: any +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gcc-4.5 (= ${gcc:Version}), libgfortran3 (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} +Provides: fortran95-compiler +Suggests: ${gfortran:multilib}, gfortran-4.5-doc, libgfortran3-dbg +Replaces: libgfortran3-dev +Description: The GNU Fortran 95 compiler + This is the GNU Fortran compiler, which compiles + Fortran 95 on platforms supported by the gcc compiler. It uses the + gcc backend to generate optimized code. + +Package: gfortran-4.5-multilib +Architecture: amd64 i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 sparc +Section: devel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gfortran-4.5 (= ${gcc:Version}), gcc-4.5-multilib (= ${gcc:Version}), ${dep:libgfortranbiarch}, ${shlibs:Depends}, ${misc:Depends} +Description: The GNU Fortran 95 compiler (multilib files) + This is the GNU Fortran compiler, which compiles Fortran 95 on platforms + supported by the gcc compiler. + . + On architectures with multilib support, the package contains files + and dependencies for the non-default multilib architecture(s). + +Package: gfortran-4.5-doc +Architecture: all +Section: doc +Priority: optional +Depends: gcc-4.5-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends} +Description: Documentation for the GNU Fortran compiler (gfortran) + Documentation for the GNU Fortran 95 compiler in info format. + +Package: libstdc++6 +Architecture: any +Section: libs +Priority: required +Depends: gcc-4.5-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Multi-Arch: same +Pre-Depends: multiarch-support +Conflicts: scim (<< 1.4.2-1) +Description: The GNU Standard C++ Library v3 + This package contains an additional runtime library for C++ programs + built with the GNU compiler. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. + +Package: lib32stdc++6 +Architecture: amd64 ppc64 kfreebsd-amd64 +Section: libs +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), lib32gcc1, ${shlibs:Depends}, ${misc:Depends} +Conflicts: ${confl:lib32} +Description: The GNU Standard C++ Library v3 (32 bit Version) + This package contains an additional runtime library for C++ programs + built with the GNU compiler. + +Package: lib64stdc++6 +Architecture: i386 powerpc sparc s390 mips mipsel +Section: libs +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), ${shlibs:Depends}, lib64gcc1, ${misc:Depends} +Description: The GNU Standard C++ Library v3 (64bit) + This package contains an additional runtime library for C++ programs + built with the GNU compiler. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. + +Package: libn32stdc++6 +Architecture: mips mipsel +Section: libs +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), ${shlibs:Depends}, libn32gcc1, ${misc:Depends} +Description: The GNU Standard C++ Library v3 (n32) + This package contains an additional runtime library for C++ programs + built with the GNU compiler. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. + +Package: libstdc++6-4.5-dev +Architecture: any +Section: libdevel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), g++-4.5 (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}), ${dep:libcdev}, ${misc:Depends} +Conflicts: libg++27-dev, libg++272-dev (<< 2.7.2.8-1), libstdc++2.8-dev, libg++2.8-dev, libstdc++2.9-dev, libstdc++2.9-glibc2.1-dev, libstdc++2.10-dev (<< 1:2.95.3-2), libstdc++3.0-dev +Suggests: libstdc++6-4.5-doc +Provides: libstdc++-dev +Description: The GNU Standard C++ Library v3 (development files) + This package contains the headers and static library files necessary for + building C++ programs which use libstdc++. + . + libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which + was included up to g++-2.95. The first version of libstdc++-v3 appeared + in g++-3.0. + +Package: libstdc++6-4.5-pic +Architecture: any +Section: libdevel +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}), libstdc++6-4.5-dev (= ${gcc:Version}), ${misc:Depends} +Description: The GNU Standard C++ Library v3 (shared library subset kit) + This is used to develop subsets of the libstdc++ shared libraries for + use on custom installation floppies and in embedded systems. + . + Unless you are making one of those, you will not need this package. + +Package: libstdc++6-4.5-dbg +Architecture: any +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}), libgcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Recommends: libstdc++6-4.5-dev (= ${gcc:Version}) +Conflicts: libstdc++5-dbg, libstdc++5-3.3-dbg, libstdc++6-dbg, libstdc++6-4.0-dbg, libstdc++6-4.1-dbg, libstdc++6-4.2-dbg, libstdc++6-4.3-dbg, libstdc++6-4.4-dbg +Description: The GNU Standard C++ Library v3 (debugging files) + This package contains the shared library of libstdc++ compiled with + debugging symbols. + +Package: lib32stdc++6-4.5-dbg +Architecture: amd64 ppc64 kfreebsd-amd64 +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), lib32stdc++6 (>= ${gcc:Version}), libstdc++6-4.5-dev (= ${gcc:Version}), lib32gcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Conflicts: lib32stdc++6-dbg, lib32stdc++6-4.0-dbg, lib32stdc++6-4.1-dbg, lib32stdc++6-4.2-dbg, lib32stdc++6-4.3-dbg, lib32stdc++6-4.4-dbg +Description: The GNU Standard C++ Library v3 (debugging files) + This package contains the shared library of libstdc++ compiled with + debugging symbols. + +Package: lib64stdc++6-4.5-dbg +Architecture: i386 powerpc sparc s390 mips mipsel +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), lib64stdc++6 (>= ${gcc:Version}), libstdc++6-4.5-dev (= ${gcc:Version}), lib64gcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Conflicts: lib64stdc++6-dbg, lib64stdc++6-4.0-dbg, lib64stdc++6-4.1-dbg, lib64stdc++6-4.2-dbg, lib64stdc++6-4.3-dbg, lib64stdc++6-4.4-dbg +Description: The GNU Standard C++ Library v3 (debugging files) + This package contains the shared library of libstdc++ compiled with + debugging symbols. + +Package: libn32stdc++6-4.5-dbg +Architecture: mips mipsel +Section: debug +Priority: extra +Depends: gcc-4.5-base (= ${gcc:Version}), libn32stdc++6 (>= ${gcc:Version}), libstdc++6-4.5-dev (= ${gcc:Version}), libn32gcc1-dbg, ${shlibs:Depends}, ${misc:Depends} +Conflicts: libn32stdc++6-dbg, libn32stdc++6-4.0-dbg, libn32stdc++6-4.1-dbg, libn32stdc++6-4.2-dbg, libn32stdc++6-4.3-dbg, libn32stdc++6-4.4-dbg +Description: The GNU Standard C++ Library v3 (debugging files) + This package contains the shared library of libstdc++ compiled with + debugging symbols. + +Package: libstdc++6-4.5-doc +Architecture: all +Section: doc +Priority: optional +Depends: gcc-4.5-base (>= ${gcc:SoftVersion}), ${misc:Depends} +Conflicts: libstdc++5-doc, libstdc++5-3.3-doc, libstdc++6-doc, libstdc++6-4.0-doc, libstdc++6-4.1-doc, libstdc++6-4.2-doc, libstdc++6-4.3-doc, libstdc++6-4.4-doc +Description: The GNU Standard C++ Library v3 (documentation files) + This package contains documentation files for the GNU stdc++ library. + . + One set is the distribution documentation, the other set is the + source documentation including a namespace list, class hierarchy, + alphabetical list, compound list, file list, namespace members, + compound members and file members. + +Package: gcc-4.5-soft-float +Architecture: arm armel +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gcc-4.5 (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Replaces: gcc-soft-float-ss +Description: The soft-floating-point gcc libraries (arm) + These are versions of basic static libraries such as libgcc.a compiled + with the -msoft-float option, for CPUs without a floating-point unit. + +Package: fixincludes +Architecture: any +Priority: optional +Depends: gcc-4.5-base (= ${gcc:Version}), gcc-4.5 (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: Fix non-ANSI header files + FixIncludes was created to fix non-ANSI system header files. Many + system manufacturers supply proprietary headers that are not ANSI compliant. + The GNU compilers cannot compile non-ANSI headers. Consequently, the + FixIncludes shell script was written to fix the header files. + . + Not all packages with header files are installed on the system, when the + package is built, so we make fixincludes available at build time of other + packages, such that checking tools like lintian can make use of it. + +Package: gcc-4.5-doc +Architecture: all +Section: doc +Priority: optional +Depends: gcc-4.5-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends} +Conflicts: gcc-docs (<< 2.95.2) +Replaces: gcc (<=2.7.2.3-4.3), gcc-docs (<< 2.95.2) +Description: Documentation for the GNU compilers (gcc, gobjc, g++) + Documentation for the GNU compilers in info format. + +Package: gcc-4.5-source +Architecture: all +Priority: optional +Depends: make (>= 3.81), autoconf2.64, automake, quilt, patchutils, ${misc:Depends} +Description: Source of the GNU Compiler Collection + This package contains the sources and patches which are needed to + build the GNU Compiler Collection (GCC). --- gcc-4.5-4.5.2.orig/debian/gcj-BV-jdk.postinst +++ gcc-4.5-4.5.2/debian/gcj-BV-jdk.postinst @@ -0,0 +1,45 @@ +#! /bin/sh -e + +if [ -d /usr/share/doc/gcc-@BV@-base/java ] && [ ! -h /usr/share/doc/gcc-@BV@-base/java ]; then + rm -rf /usr/share/doc/gcc-@BV@-base/java + ln -s ../gcj-@BV@-base /usr/share/doc/gcc-@BV@-base/java +fi + +prio=@java_priority@ +update-alternatives --quiet \ + --install /usr/bin/javac javac /usr/bin/gcj-wrapper-@BV@ $prio \ + @GFDL@--slave /usr/share/man/man1/javac.1.gz javac.1.gz /usr/share/man/man1/gcj-wrapper-@BV@.1.gz + +update-alternatives --quiet \ + --install /usr/bin/jar jar /usr/bin/gjar-@BV@ $prio \ + --slave /usr/share/man/man1/jar.1.gz jar.1.gz /usr/share/man/man1/gjar-@BV@.1.gz + +update-alternatives --quiet \ + --install /usr/bin/jarsigner jarsigner /usr/bin/gjarsigner-@BV@ $prio \ + --slave /usr/share/man/man1/jarsigner.1.gz jarsigner.1.gz /usr/share/man/man1/gjarsigner-@BV@.1.gz + +update-alternatives --quiet \ + --install /usr/bin/javah javah /usr/bin/gjavah-@BV@ $prio \ + --slave /usr/share/man/man1/javah.1.gz javah.1.gz /usr/share/man/man1/gjavah-@BV@.1.gz + +update-alternatives --quiet \ + --install /usr/bin/javadoc javadoc /usr/bin/gjdoc-@BV@ $prio \ + --slave /usr/share/man/man1/javadoc.1.gz javadoc.1.gz /usr/share/man/man1/gjdoc-@BV@.1.gz + +update-alternatives --quiet \ + --install /usr/bin/native2ascii native2ascii /usr/bin/gnative2ascii-@BV@ $prio \ + --slave /usr/share/man/man1/native2ascii.1.gz native2ascii.1.gz /usr/share/man/man1/gnative2ascii-@BV@.1.gz + +update-alternatives --quiet \ + --install /usr/bin/rmic rmic /usr/bin/grmic-@BV@ $prio \ + @GFDL@--slave /usr/share/man/man1/rmic.1.gz rmic.1.gz /usr/share/man/man1/grmic-@BV@.1.gz + +update-alternatives --quiet \ + --install /usr/bin/serialver serialver /usr/bin/gserialver-@BV@ $prio \ + --slave /usr/share/man/man1/serialver.1.gz serialver.1.gz /usr/share/man/man1/gserialver-@BV@.1.gz + +update-alternatives --quiet \ + --install /usr/bin/tnameserv tnameserv /usr/bin/gtnameserv-@BV@ $prio \ + --slave /usr/share/man/man1/tnameserv.1.gz tnameserv.1.gz /usr/share/man/man1/gtnameserv-@BV@.1.gz + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.lpia +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.lpia @@ -0,0 +1,133 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GCC_4.4.0@GCC_4.4.0 1:4.4.0 + GCC_4.5.0@GCC_4.5.0 1:4.5.0 + GLIBC_2.0@GLIBC_2.0 1:4.1.1 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __addtf3@GCC_4.4.0 1:4.4.0 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __ashldi3@GCC_3.0 1:4.1.1 + __ashrdi3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzsi2@GCC_3.4 1:4.1.1 + __cmpdi2@GCC_3.0 1:4.1.1 + __copysigntf3@GCC_4.4.0 1:4.4.0 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzsi2@GCC_3.4 1:4.1.1 + __deregister_frame@GLIBC_2.0 1:4.1.1 + __deregister_frame_info@GLIBC_2.0 1:4.1.1 + __deregister_frame_info_bases@GCC_3.0 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divdi3@GLIBC_2.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + 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1:4.1.1 + __register_frame_info@GLIBC_2.0 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GLIBC_2.0 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GLIBC_2.0 1:4.1.1 + __subtf3@GCC_4.4.0 1:4.4.0 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __trunctfdf2@GCC_4.4.0 1:4.4.0 + __trunctfsf2@GCC_4.4.0 1:4.4.0 + __trunctfxf2@GCC_4.4.0 1:4.4.0 + __ucmpdi2@GCC_3.0 1:4.1.1 + __udivdi3@GLIBC_2.0 1:4.1.1 + __udivmoddi4@GCC_3.0 1:4.1.1 + __umoddi3@GLIBC_2.0 1:4.1.1 + __unordtf2@GCC_4.4.0 1:4.4.0 --- gcc-4.5-4.5.2.orig/debian/NEWS.gcc +++ gcc-4.5-4.5.2/debian/NEWS.gcc @@ -0,0 +1,739 @@ +GCC 4.5 Release Series -- Changes, New Features, and Fixes +========================================================== + + +Caveats +======= + +- GCC now requires the MPC library in order to build. See the + prerequisites page for version requirements. + +- Support for a number of older systems and recently unmaintained or + untested target ports of GCC has been declared obsolete in GCC 4.5. + Unless there is activity to revive them, the next release of GCC will + have their sources permanently removed. + +- The following ports for individual systems on particular + architectures have been obsoleted: + + - IRIX releases before 6.5 (mips-sgi-irix5*, mips-sgi-irix6.[0-4]) + - Solaris 7 (*-*-solaris2.7) + - Tru64 UNIX releases before V5.1 (alpha*-dec-osf4*, alpha-dec-osf5.0*) + - Details for the IRIX, Solaris 7, and Tru64 UNIX obsoletions can + be found in the announcement. + +- Support has been removed for all the configurations obsoleted in GCC 4.4. + +- Support has been removed for the protoize and unprotoize utilities, + obsoleted in GCC 4.4. + +- Support has been removed for tuning for Itanium1 (Merced) variants. + Note that code tuned for Itanium2 should also run correctly on + Itanium1. + +- GCC now generates unwind info also for epilogues. DWARF debuginfo + generated by GCC now uses more features of DWARF3 than it used to + do and also some DWARF4 features. GDB older than 7.0 is not able + to handle either of these, so to debug GCC 4.5 generated binaries + or libraries GDB 7.0 or later is needed. You can disable use of + DWARF4 features with -gdwarf-3 -gstrict-dwarf options, or with + -gdwarf-2 -gstrict-dwarf restrict GCC to just DWARF2 standard, but + epilogue unwind info is emitted unconditionally whenever unwind + info is emitted. + +- On x86 targets, code containing floating-point calculations may run + significantly slower when compiled with GCC 4.5 in strict C99 + conformance mode than they did with earlier GCC versions. This is + due to stricter standard conformance of the compiler and can be + avoided by using the option -fexcess-precision=fast; also see + below. + +- The function attribute noinline no longer prevents GCC from cloning + the function. A new attribute noclone has been introduced for + this purpose. Cloning a function means that it is duplicated and + the new copy is specialized for certain contexts (for example when + a parameter is a known constant). + + +General Optimizer Improvements +============================== + + +- The -save-temps now takes an optional argument. The -save-temps and + -save-temps=cwd switches write the temporary files in the current + working directory based on the original source file. The + -save-temps=obj switch will write files into the directory + specified with the -o option, and the intermediate filenames are + based on the output file. This will allow the user to get the + compiler intermediate files when doing parallel builds without two + builds of the same filename located in different directories from + interfering with each other. + +- Debugging dumps are now created in the same directory as the object + file rather than in the current working directory. This allows + the user to get debugging dumps when doing parallel builds without + two builds of the same filename interfering with each other. + +- GCC has been integrated with the MPC library. This allows GCC to + evaluate complex arithmetic at compile time more accurately. It + also allows GCC to evaluate calls to complex built-in math + functions having constant arguments and replace them at compile + time with their mathematically equivalent results. In doing so, + GCC can generate correct results regardless of the math library + implementation or floating point precision of the host platform. + This also allows GCC to generate identical results regardless of + whether one compiles in native or cross-compile configurations to + a particular target. The following built-in functions take + advantage of this new capability: cacos, cacosh, casin, casinh, + catan, catanh, ccos, ccosh, cexp, clog, cpow, csin, csinh, csqrt, + ctan, and ctanh. The float and long double variants of these + functions (e.g. csinf and csinl) are also handled. + +- A new link-time optimizer has been added (-flto). When this option + is used, GCC generates a bytecode representation of each input + file and writes it to special ELF sections in each object file. + When the object files are linked together, all the function bodies + are read from these ELF sections and instantiated as if they had + been part of the same translation unit. This enables + interprocedural optimizations to work across different files (and + even different languages), potentially improving the performance + of the generated code. To use the link-timer optimizer, -flto + needs to be specified at compile time and during the final + link. If the program does not require any symbols to be exported, + it is possible to combine -flto and the experimental -fwhopr with + -fwhole-program to allow the interprocedural optimizers to use + more aggressive assumptions. + +- The automatic parallelization pass was enhanced to support + parallelization of outer loops. + +- Automatic parallelization can be enabled as part of Graphite. In + addition to -ftree-parallelize-loops=, specify + -floop-parallelize-all to enable the Graphite-based optimization. + +- The infrastructure for optimizing based on restrict qualified + pointers has been rewritten and should result in code generation + improvements. Optimizations based on restrict qualified pointers + are now also available when using -fno-strict-aliasing. + +- There is a new optimization pass that attempts to change prototype + of functions to avoid unused parameters, pass only relevant parts + of structures and turn arguments passed by reference to arguments + passed by value when possible. It is enabled by -O2 and above as + well as -Os and can be manually invoked using the new command-line + switch -fipa-sra. + +- GCC now optimize exception handling code. In particular cleanup + regions that are proved to not have any effect are optimized out. + + +New Languages and Language specific improvements +================================================ + +All languages +------------- + +- The -fshow-column option is now on by default. This + means error messages now have a column associated with them. + + +Ada +--- + +- Compilation of programs heavily using discriminated record types + with variant parts has been sped up and generates more compact + code. + +- Stack checking now works reasonably well on most plaforms. In some + specific cases, stack overflows may still fail to be detected, but a + compile-time warning will be issued for these cases. + + +C family +-------- + +- If a header named in a #include directive is not found, the compiler + exits immediately. This avoids a cascade of errors arising from + declarations expected to be found in that header being missing. + +- A new built-in function __builtin_unreachable() has been added that + tells the compiler that control will never reach that point. It may + be used after asm statements that terminate by transferring control + elsewhere, and in other places that are known to be unreachable. + +- The -Wlogical-op option now warns for logical expressions such as + (c == 1 && c == 2) and (c != 1 || c != 2), which are likely to be + mistakes. This option is disabled by default. + +- An asm goto feature has been added to allow asm statements that jump + to C labels. + +- C++0x raw strings are supported for C++ and for C with -std=gnu99. + +- The deprecated attribute now takes an optional string argument, for + example, __attribute__((deprecated("text string"))), that will be + printed together with the deprecation warning. + + +C +- + +- The -Wenum-compare option, which warns when comparing values of + different enum types, now works for C. It formerly only worked for + C++. This warning is enabled by -Wall. It may be avoided by using + a type cast. + +- The -Wcast-qual option now warns about casts which are unsafe in + that they permit const-correctness to be violated without further + warnings. Specifically, it warns about cases where a qualifier is + added when all the lower types are not const. For example, it warns + about a cast from char ** to const char **. + +- The -Wc++-compat option is significantly improved. It issues new + warnings for: + + - Using C++ reserved operator names as identifiers. + - Conversions to enum types without explicit casts. + - Using va_arg with an enum type. + - Using different enum types in the two branches of ?:. + - Using ++ or -- on a variable of enum type. + - Using the same name as both a struct, union or enum tag and a + typedef, unless the typedef refers to the tagged type itself. + - Using a struct, union, or enum which is defined within another + struct or union. + - A struct field defined using a typedef if there is a field in the + struct, or an enclosing struct, whose name is the typedef name. + - Duplicate definitions at file scope. + - Uninitialized const variables. + - A global variable with an anonymous struct, union, or enum type. + - Using a string constant to initialize a char array whose size + is the length of the string. + +- The new -Wjump-misses-init option warns about cases where a goto or + switch skips the initialization of a variable. This sort of branch + is an error in C++ but not in C. This warning is enabled by + -Wc++-compat. + +- GCC now ensures that a C99-conforming is present on most + targets, and uses information about the types in this header to + implement the Fortran bindings to those types. GCC does not ensure + the presence of such a header, and does not implement the Fortran + bindings, on the following targets: NetBSD, VxWorks, VMS, SymbianOS, + WinCE, LynxOS, Netware, QNX, Interix, TPF. + +- GCC now implements C90- and C99-conforming rules for constant + expressions. This may cause warnings or errors for some code using + expressions that can be folded to a constant but are not constant + expressions as defined by ISO C. + +- All known target-independent C90 and C90 Amendment 1 conformance + bugs, and all known target-independent C99 conformance bugs not + related to floating point or extended identifiers, have been fixed. + +- The C decimal floating point support now includes support for the + FLOAT_CONST_DECIMAL64 pragma. + +- The named address space feature from ISO/IEC TR 18037 is now + supported. This is currently only implemented for the SPU + processor. + + +C++ +--- + +- Improved experimental support for the upcoming C++0x ISO C++ + standard, including support for raw strings, lambda expressions and + explicit type conversion operators. + +- When printing the name of a class template specialization, G++ will + now omit any template arguments which come from default template + arguments. This behavior (and the pretty-printing of function + template specializations as template signature and arguments) can be + disabled with the -fno-pretty-templates option. + +- Access control is now applied to typedef names used in a template, + which may cause G++ to reject some ill-formed code that was accepted + by earlier releases. The -fno-access-control option can be used as + a temporary workaround until the code is corrected. + +- Compilation time for code that uses templates should now scale + linearly with the number of instantiations rather than + quadratically, as template instantiations are now looked up using + hash tables. + +- Declarations of functions that look like builtin declarations of + library functions are only considered to be redeclarations if they + are declared with extern "C". This may cause problems with code + that omits extern "C" on hand-written declarations of C library + functions such as abort or memcpy. Such code is ill-formed, but was + accepted by earlier releases. + +- Diagnostics that used to complain about passing non-POD types to + ... or jumping past the declaration of a non-POD variable now check + for triviality rather than PODness, as per C++0x. + +- In C++0x mode local and anonymous classes are now allowed as + template arguments, and in declarations of variables and functions + with linkage, so long as any such declaration that is used is also + defined (DR 757). + +- Labels may now have attributes, as has been permitted for a while in + C. This is only permitted when the label definition and the + attribute specifier is followed by a semicolon -- i.e., the label + applies to an empty statement. The only useful attribute for a + label is unused. + +- G++ now implements DR 176. Previously G++ did not support using the + injected-class-name of a template base class as a type name, and + lookup of the name found the declaration of the template in the + enclosing scope. Now lookup of the name finds the + injected-class-name, which can be used either as a type or as a + template, depending on whether or not the name is followed by a + template argument list. As a result of this change, some code that + was previously accepted may be ill-formed because + + 1) The injected-class-name is not accessible because it's from a + private base, or + 2) The injected-class-name cannot be used as an argument for a + template template parameter. + + In either of these cases, the code can be fixed by adding a + nested-name-specifier to explicitly name the template. The first + can be worked around with -fno-access-control; the second is only + rejected with -pedantic. + +- A new standard mangling for SIMD vector types has been added, to + avoid name clashes on systems with vectors of varying length. By + default the compiler still uses the old mangling, but emits aliases + with the new mangling on targets that support strong aliases. Users + can switch over entirely to the new mangling with -fabi-version=4 or + -fabi-version=0. -Wabi will now warn about code that uses the old + mangling. + + +Runtime Library (libstdc++) +--------------------------- + +- Improved experimental support for the upcoming ISO C++ standard, + C++0x, including: + + - Support for , , and . + - Existing facilities now exploit explicit operators and the + newly implemented core C++0x features. + +- An experimental profile mode has been added. This is an + implementation of many C++ standard library constructs with an + additional analysis layer that gives performance improvement advice + based on recognition of suboptimal usage patterns. For example, + + #include + int main() + { + std::vector v; + for (int k = 0; k < 1024; ++k) + v.insert(v.begin(), k); + } + + When instrumented via the profile mode, can return suggestions about + the initial size and choice of the container used as follows: + + vector-to-list: improvement = 5: call stack = 0x804842c ... + : advice = change std::vector to std::list + vector-size: improvement = 3: call stack = 0x804842c ... + : advice = change initial container size from 0 to 1024 + + These constructs can be substituted for the normal libstdc++ + constructs on a piecemeal basis, or all existing components can be + transformed via the -D_GLIBCXX_PROFILE macro. + +- Support for decimal floating-point arithmetic (aka ISO C++ TR 24733) + has been added. This support is in header file , + uses namespace std::decimal, and includes classes decimal32, + decimal64, and decimal128. + +- Sources have been audited for application of function attributes + nothrow, const, pure, and noreturn. + +- Python pretty-printers have been added for many standard library + components that simplify the internal representation and present a + more intuitive view of components when used with + appropriately-advanced versions of GDB. For more information, please + consult the more detailed description. + +- The default behavior for comparing typeinfo names has changed, so + in , __GXX_MERGED_TYPEINFO_NAMES now defaults to zero. + +- The new -static-libstdc++ option directs g++ to link the C++ library + statically, even if the default would normally be to link it + dynamically. + + +Fortran +------- + +- The COMMON default padding has been changed -- instead of adding the + padding before a variable it is now added afterwards, which + increases the compatibility with other vendors and helps to obtain + the correct output in some cases. Cf. also the -falign-commons + option (added in 4.4). + +- The -finit-real= option now also supports the value snan for + signalling not-a-number; to be effective, one additionally needs to + enable trapping (e.g. via -ffpe-trap=). Note: Compile-time + optimizations can turn a signalling NaN into a quiet one. + +- The new option -fcheck= has been added with the options bounds, + array-temps, do, pointer, and recursive. The bounds and array-temps + options are equivalent to -fbounds-check and + -fcheck-array-temporaries. The do option checks for invalid + modification of loop iteration variables, and the recursive option + tests for recursive calls to subroutines/functions which are not + marked as recursive. With pointer pointer association checks in + calls are performed; however, neither undefined pointers nor + pointers in expressions are handled. Using -fcheck=all enables all + these run-time checks. + +- The run-time checking -fcheck=bounds now warns about invalid string + lengths of character dummy arguments. Additionally, more + compile-time checks have been added. + +- The new option -fno-protect-parens has been added; if set, the + compiler may reorder REAL and COMPLEX expressions without regard to + parentheses. + +- GNU Fortran no longer links against libgfortranbegin. As before, + MAIN__ (assembler symbol name) is the actual Fortran main program, + which is invoked by the main function. However, main is now + generated and put in the same object file as MAIN__. For the time + being, libgfortranbegin still exists for backward compatibility. For + details see the new Mixed-Language Programming chapter in the + manual. + +- The I/O library was restructured for performance and cleaner code. + +- Array assignments and WHERE are now run in parallel when OpenMP's + WORKSHARE is used. + +- The experimental option -fwhole-file was added. The option allows + whole-file checking of procedure arguments and allows for better + optimizations. It can also be used with -fwhole-program, which is + now also supported in gfortran. + +- More Fortran 2003 and Fortran 2008 mathematical functions can + now be used as initialization expressions. + +- Some extended attributes such as STDCALL are now supported via the + GCC$ compiler directive. + +- For Fortran 77 compatibility: If -fno-sign-zero is used, the SIGN + intrinsic behaves now as if zero were always positive. + +- For legacy compatibiliy: On Cygwin and MinGW, the special files + CONOUT$ and CONIN$ (and CONERR$ which maps to CONOUT$) are now + supported. + +- Fortran 2003 support has been extended: + + - Procedure-pointer function results and procedure-pointer components + (including PASS), + - allocatable scalars (experimental), + - DEFERRED type-bound procedures, + - the ERRMSG= argument of the ALLOCATE and DEALLOCATE statements + have been implemented. + - The ALLOCATE statement supports type-specs and the SOURCE= argument. + - OPERATOR(*) and ASSIGNMENT(=) are now allowed as GENERIC type-bound + procedure (i.e. as type-bound operators). + - Rounding (ROUND=, RZ, ...) for output is now supported. + - The INT_FAST{8,16,32,64,128}_T kind type parameters of the intrinsic + module ISO_C_BINDING are now supported, except for the targets + listed above as ones where GCC does not have type + information. + - Extensible derived types with type-bound procedure or procedure + pointer with PASS attribute now have to use CLASS in line with the + Fortran 2003 standard; the workaround to use TYPE is no longer + supported. + - Experimental, incomplete support for polymorphism, including CLASS, + SELECT TYPE and dynamic dispatch of type-bound procedure calls. + Some features do not work yet such as unlimited polymorphism (CLASS(*)). + +- Fortran 2008 support has been extended: + + - The OPEN statement now supports the NEWUNIT= option, which returns + a unique file unit, thus preventing inadvertent use of the same unit + in different parts of the program. + - Support for unlimited format items has been added. + - The INT{8,16,32} and REAL{32,64,128} kind type parameters of the + intrinsic module ISO_FORTRAN_ENV are now supported. + - Using complex arguments with TAN, SINH, COSH, TANH, ASIN, ACOS, + and ATAN is now possible; the functions ASINH, ACOSH, and ATANH have + been added (for real and complex arguments) and ATAN(Y,X) is now an + alias for ATAN2(Y,X). + - The BLOCK construct has been implemented. + + +New Targets and Target Specific Improvements +============================================ + +AIX +--- + +- Full cross-toolchain support now available with GNU Binutils + + +ARM +--- + +- GCC now supports the Cortex-M0 and Cortex-A5 processors. + +- GCC now supports the ARM v7E-M architecture. + +- GCC now supports VFPv4-based FPUs and FPUs with + single-precision-only VFP. + +- GCC has many improvements to optimization for other ARM processors, + including scheduling support for the integer pipeline on Cortex-A9. + +- GCC now supports the IEEE 754-2008 half-precision floating-point + type, and a variant ARM-specific half-precision type. This type is + specified using __fp16, with the layout determined by -mfp16-format. + With appropriate -mfpu options, the Cortex-A9 and VFPv4 + half-precision instructions will be used. + +- GCC now supports the variant of AAPCS that uses VFP registers for + parameter passing and return values. + + +AVR +--- + +- The -mno-tablejump option has been removed because it + has the same effect as the -fno-jump-tables option. + +- Added support for these new AVR devices: + - ATmega8U2 + - ATmega16U2 + - ATmega32U2 + + +IA-32/x86-64 +------------ + +- GCC now will set the default for -march= based on the configure + target. + +- GCC now supports handling floating-point excess precision arising + from use of the x87 floating-point unit in a way that conforms to + ISO C99. This is enabled with -fexcess-precision=standard and with + standards conformance options such as -std=c99, and may be disabled + using -fexcess-precision=fast. + +- Support for the Intel Atom processor is now available through the + -march=atom and -mtune=atom options. + +- A new -mcrc32 option is now available to enable crc32 intrinsics. + +- A new -mmovbe option is now available to enable GCC to use the movbe + instruction to implement __builtin_bswap32 and __builtin_bswap64. + +- SSE math now can be enabled by default at configure time with the + new --with-fpmath=sse option. + +- There is a new intrinsic header file, . It should be + included before using any IA-32/x86-64 intrinsics. + +- Support for the XOP, FMA4, and LWP instruction sets for the AMD + Orochi processors are now available with the -mxop, -mfma4, and + -mlwp options. + +- The -mabm option enables GCC to use the popcnt and lzcnt + instructions on AMD processors. + +- The -mpopcnt option enables GCC to use the popcnt instructions on + both AMD and Intel processors. + + +M68K/ColdFire +------------- + +- GCC now supports ColdFire 51xx, 5221x, 5225x, 52274, 52277, 5301x + and 5441x devices. + +- GCC now supports thread-local storage (TLS) on M68K and ColdFire + processors. + + +MeP +--- + +- Support has been added for the Toshiba Media embedded Processor + (MeP, or mep-elf) embedded target. + + +MIPS +---- + +- GCC now supports MIPS 1004K processors. + +- GCC can now be configured with options --with-arch-32, + --with-arch-64, --with-tune-32 and --with-tune-64 to control the + default optimization separately for 32-bit and 64-bit modes. + +- MIPS targets now support an alternative _mcount interface, in which + register $12 points to the function's save slot for register $31. + This interface is selected by the -mcount-ra-address option; see the + documentation for more details. + +- GNU/Linux targets can now generate read-only .eh_frame sections. + This optimization requires GNU binutils 2.20 or above, and is only + available if GCC is configured with a suitable version of binutils. + +- GNU/Linux targets can now attach special relocations to indirect + calls, so that the linker can turn them into direct jumps or + branches. This optimization requires GNU binutils 2.20 or later, + and is automatically selected if GCC is configured with an + appropriate version of binutils. It can be explicitly enabled or + disabled using the -mrelax-pic-calls command-line option. + +- GCC now generates more heavily-optimized atomic operations on Octeon + processors. + +- MIPS targets now support the -fstack-protector option. + +- GCC now supports an -msynci option, which specifies that synci is + enough to flush the instruction cache, without help from the + operating system. GCC uses this information to optimize + automatically-generated cache flush operations, such as those used + for nested functions in C. There is also a --with-synci + configure-time option, which makes -msynci the default. + +- GCC supports four new function attributes for interrupt handlers: + interrupt, use_shadow_register_set, keep_interrupts_masked and + use_debug_exception_return. See the documentation for more details + about these attributes. + + +RS/6000 (POWER/PowerPC) +----------------------- + +- GCC now supports the Power ISA 2.06, which includes the VSX + instructions that add vector 64-bit floating point support, new + population count instructions, and conversions between floating + point and unsigned types. + +- Support for the power7 processor is now available through the + -mcpu=power7 and -mtune=power7. + +- GCC will now vectorize loops that contain simple math functions like + copysign when generating code for altivec or VSX targets. + +- Support for the A2 processor is now available through the -mcpu=a2 + and -mtune=a2 options. + +- Support for the 476 processor is now available through the + -mcpu={476,476fp} and -mtune={476,476fp} options. + +- Support for the e500mc64 processor is now available through the + -mcpu=e500mc64 and -mtune=e500mc64 options. + +- GCC can now be configured with options --with-cpu-32, --with-cpu-64, + --with-tune-32 and --with-tune-64 to control the default + optimization separately for 32-bit and 64-bit modes. + + +RX +-- + +- Support has been added for the Renesas RX Processor (rx-elf) target. + + +Operating Systems +================= + +Windows (Cygwin and MinGW) +-------------------------- + +- GCC now installs all the major language runtime libraries as DLLs + when configured with the --enable-shared option. + +- GCC now makes use of the new support for aligned common variables in + versions of binutils >= 2.20 to fix bugs in the support for SSE data + types. + +- Improvements to the libffi support library increase the reliability + of code generated by GCJ on all Windows platforms. Libgcj is + enabled by default for the first time. + +- Libtool improvements simplify installation by placing the generated + DLLs in the correct binaries directory. + +- Numerous other minor bugfixes and improvements, and substantial + enhancements to the Fortran language support library. + + +Other significant improvements +============================== + +Plugins +------- + +- It is now possible to extend the compiler without having to modify + its source code. A new option -fplugin=file.so tells GCC to load + the shared object file.so and execute it as part of the compiler. + The internal documentation describes the details on how plugins can + interact with the compiler. + + +Installation changes +==================== + +- The move to newer autotools changed default installation directories + and switches to control them: The --with-datarootdir, --with-docdir, + --with-pdfdir, and --with-htmldir switches are not used any more. + Instead, you can now use --datarootdir, --docdir, --htmldir, and + --pdfdir. The default installation directories have changed as + follows according to the GNU Coding Standards: + + datarootdir + read-only architecture-independent data root [PREFIX/share] + localedir + locale-specific message catalogs [DATAROOTDIR/locale] + docdir + documentation root [DATAROOTDIR/doc/PACKAGE] + htmldir + html documentation [DOCDIR] + dvidir + dvi documentation [DOCDIR] + pdfdir + pdf documentation [DOCDIR] + psdir + ps documentation [DOCDIR] + + The following variables have new default values: + + datadir + read-only architecture-independent data [DATAROOTDIR] + infodir + info documentation [DATAROOTDIR/info] + mandir + man documentation [DATAROOTDIR/man] + + +------------------------------------------------------------------------------ +Please send FSF & GNU inquiries & questions to gnu@gnu.org. There are +also other ways to contact the FSF. + +These pages are maintained by the GCC team. + +For questions related to the use of GCC, please consult these web +pages and the GCC manuals. If that fails, the gcc-help@gcc.gnu.org +mailing list might help. Please send comments on these web pages and +the development of GCC to our developer mailing list at gcc@gnu.org or +gcc@gcc.gnu.org. All of our lists have public archives. + +Copyright (C) Free Software Foundation, Inc., +51 Franklin St, Fifth Floor, Boston, MA 02110, USA. + +Verbatim copying and distribution of this entire article is +permitted in any medium, provided this notice is preserved. + +Last modified 2010-04-17 --- gcc-4.5-4.5.2.orig/debian/changelog-4.4 +++ gcc-4.5-4.5.2/debian/changelog-4.4 @@ -0,0 +1,36 @@ + * Closing reports reported against gcc-4.1 and fixed in gcc-4.4: + - General + + + - C + + + - C++/libstdc++ + + + - Fortran + - Java + - Architecture specific: + - mips + - sparc + * Closing reports reported against gcc-4.2 and fixed in gcc-4.4: + - General + + + - C + + + - C++/libstdc++ + + + - Fortran + - Java + - Architecture specific: + - mips + - sparc + * Closing reports reported against gcc-4.3 and fixed in gcc-4.4: + - General + + + - C + + + - C++/libstdc++ + + + - Fortran + - Java + - Architecture specific: + - mips + - sparc --- gcc-4.5-4.5.2.orig/debian/lib64gfortran3.symbols.mips +++ gcc-4.5-4.5.2/debian/lib64gfortran3.symbols.mips @@ -0,0 +1,5 @@ +libgfortran.so.3 lib64gfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.16.powerpc" +#include "libgfortran3.symbols.16.powerpc64" +#include "libgfortran3.symbols.64" --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.ldbl.32bit +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.ldbl.32bit @@ -0,0 +1,284 @@ + CXXABI_LDBL_1.3@CXXABI_LDBL_1.3 4.2.1 + GLIBCXX_LDBL_3.4.10@GLIBCXX_LDBL_3.4.10 4.3.0~rc2 + GLIBCXX_LDBL_3.4.7@GLIBCXX_LDBL_3.4.7 4.2.1 + GLIBCXX_LDBL_3.4@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt3tr14hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2 + _ZNKSt4hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2 + _ZGVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1 + _ZGVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1 + 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_ZTVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.mips +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.mips @@ -0,0 +1,2 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.amd64 +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.amd64 @@ -0,0 +1,7 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.64bit" +#include "libstdc++6.symbols.excprop" + _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 --- gcc-4.5-4.5.2.orig/debian/lib32gfortran3.symbols.ppc64 +++ gcc-4.5-4.5.2/debian/lib32gfortran3.symbols.ppc64 @@ -0,0 +1,3 @@ +libgfortran.so.3 lib32gfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.16.powerpc" --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.armel +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.armel @@ -0,0 +1,120 @@ +libgcc_s.so.1 libgcc1 #MINVER# +(ignore-blacklist)#include "libgcc1.symbols.aeabi" + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3.4@GCC_3.3.4 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_3.5@GCC_3.5 1:4.3.0 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GLIBC_2.0@GLIBC_2.0 1:4.1.1 + _Unwind_Backtrace@GCC_4.3.0 1:4.3.0 + _Unwind_Complete@GCC_3.5 1:4.3.0 + _Unwind_DeleteException@GCC_3.0 1:4.3.0 + _Unwind_ForcedUnwind@GCC_3.0 1:4.3.0 + _Unwind_GetCFA@GCC_3.3 1:4.3.0 + _Unwind_GetDataRelBase@GCC_3.0 1:4.3.0 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.3.0 + _Unwind_GetRegionStart@GCC_3.0 1:4.3.0 + _Unwind_GetTextRelBase@GCC_3.0 1:4.3.0 + _Unwind_RaiseException@GCC_3.0 1:4.3.0 + _Unwind_Resume@GCC_3.0 1:4.3.0 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.3.0 + _Unwind_VRS_Get@GCC_3.5 1:4.3.0 + _Unwind_VRS_Pop@GCC_3.5 1:4.3.0 + _Unwind_VRS_Set@GCC_3.5 1:4.3.0 + __absvdi2@GCC_3.0 1:4.3.0 + __absvsi2@GCC_3.0 1:4.3.0 + __adddf3@GCC_3.0 1:4.3.0 + __addsf3@GCC_3.0 1:4.3.0 + __addvdi3@GCC_3.0 1:4.3.0 + __addvsi3@GCC_3.0 1:4.3.0 + __ashldi3@GCC_3.0 1:4.3.0 + __ashrdi3@GCC_3.0 1:4.3.0 + __bswapdi2@GCC_4.3.0 1:4.3.0 + __bswapsi2@GCC_4.3.0 1:4.3.0 + __clear_cache@GCC_3.0 1:4.3.0 + __clzdi2@GCC_3.4 1:4.3.0 + __clzsi2@GCC_3.4 1:4.3.0 + __cmpdi2@GCC_3.0 1:4.3.0 + __ctzdi2@GCC_3.4 1:4.3.0 + __ctzsi2@GCC_3.4 1:4.3.0 + __divdc3@GCC_4.0.0 1:4.3.0 + __divdf3@GCC_3.0 1:4.3.0 + __divdi3@GLIBC_2.0 1:4.3.0 + __divsc3@GCC_4.0.0 1:4.3.0 + __divsf3@GCC_3.0 1:4.3.0 + __divsi3@GCC_3.0 1:4.3.0 + __emutls_get_address@GCC_4.3.0 1:4.3.0 + __emutls_register_common@GCC_4.3.0 1:4.3.0 + __enable_execute_stack@GCC_3.4.2 1:4.3.0 + __eqdf2@GCC_3.0 1:4.3.0 + __eqsf2@GCC_3.0 1:4.3.0 + __extendsfdf2@GCC_3.0 1:4.3.0 + __ffsdi2@GCC_3.0 1:4.3.0 + __ffssi2@GCC_4.3.0 1:4.3.0 + __fixdfdi@GCC_3.0 1:4.3.0 + __fixdfsi@GCC_3.0 1:4.3.0 + __fixsfdi@GCC_3.0 1:4.3.0 + __fixsfsi@GCC_3.0 1:4.3.0 + __fixunsdfdi@GCC_3.0 1:4.3.0 + __fixunsdfsi@GCC_3.0 1:4.3.0 + __fixunssfdi@GCC_3.0 1:4.3.0 + __fixunssfsi@GCC_3.0 1:4.3.0 + __floatdidf@GCC_3.0 1:4.3.0 + __floatdisf@GCC_3.0 1:4.3.0 + __floatsidf@GCC_3.0 1:4.3.0 + __floatsisf@GCC_3.0 1:4.3.0 + __floatundidf@GCC_4.2.0 1:4.3.0 + __floatundisf@GCC_4.2.0 1:4.3.0 + __floatunsidf@GCC_4.2.0 1:4.3.0 + __floatunsisf@GCC_4.2.0 1:4.3.0 + __gcc_personality_v0@GCC_3.3.1 1:4.3.0 + __gedf2@GCC_3.0 1:4.3.0 + __gesf2@GCC_3.0 1:4.3.0 + __gnu_unwind_frame@GCC_3.5 1:4.3.0 + __gtdf2@GCC_3.0 1:4.3.0 + __gtsf2@GCC_3.0 1:4.3.0 + __ledf2@GCC_3.0 1:4.3.0 + __lesf2@GCC_3.0 1:4.3.0 + __lshrdi3@GCC_3.0 1:4.3.0 + __ltdf2@GCC_3.0 1:4.3.0 + __ltsf2@GCC_3.0 1:4.3.0 + __moddi3@GLIBC_2.0 1:4.3.0 + __modsi3@GCC_3.0 1:4.3.0 + __muldc3@GCC_4.0.0 1:4.3.0 + __muldf3@GCC_3.0 1:4.3.0 + __muldi3@GCC_3.0 1:4.3.0 + __mulsc3@GCC_4.0.0 1:4.3.0 + __mulsf3@GCC_3.0 1:4.3.0 + __mulvdi3@GCC_3.0 1:4.3.0 + __mulvsi3@GCC_3.0 1:4.3.0 + __nedf2@GCC_3.0 1:4.3.0 + __negdf2@GCC_3.0 1:4.3.0 + __negdi2@GCC_3.0 1:4.3.0 + __negsf2@GCC_3.0 1:4.3.0 + __negvdi2@GCC_3.0 1:4.3.0 + __negvsi2@GCC_3.0 1:4.3.0 + __nesf2@GCC_3.0 1:4.3.0 + __paritydi2@GCC_3.4 1:4.3.0 + __paritysi2@GCC_3.4 1:4.3.0 + __popcountdi2@GCC_3.4 1:4.3.0 + __popcountsi2@GCC_3.4 1:4.3.0 + __powidf2@GCC_4.0.0 1:4.3.0 + __powisf2@GCC_4.0.0 1:4.3.0 + __subdf3@GCC_3.0 1:4.3.0 + __subsf3@GCC_3.0 1:4.3.0 + __subvdi3@GCC_3.0 1:4.3.0 + __subvsi3@GCC_3.0 1:4.3.0 + __truncdfsf2@GCC_3.0 1:4.3.0 + __ucmpdi2@GCC_3.0 1:4.3.0 + __udivdi3@GLIBC_2.0 1:4.3.0 + __udivmoddi4@GCC_3.0 1:4.3.0 + __udivsi3@GCC_3.0 1:4.3.0 + __umoddi3@GLIBC_2.0 1:4.3.0 + __umodsi3@GCC_3.0 1:4.3.0 + __unorddf2@GCC_3.3.4 1:4.3.0 + __unordsf2@GCC_3.3.4 1:4.3.0 --- gcc-4.5-4.5.2.orig/debian/lib64gfortran3.symbols +++ gcc-4.5-4.5.2/debian/lib64gfortran3.symbols @@ -0,0 +1,5 @@ +libgfortran.so.3 lib64gfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.10" +#include "libgfortran3.symbols.16" +#include "libgfortran3.symbols.64" --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.ldbl.64bit +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.ldbl.64bit @@ -0,0 +1,284 @@ + CXXABI_LDBL_1.3@CXXABI_LDBL_1.3 4.2.1 + GLIBCXX_LDBL_3.4.10@GLIBCXX_LDBL_3.4.10 4.3.0~rc2 + GLIBCXX_LDBL_3.4.7@GLIBCXX_LDBL_3.4.7 4.2.1 + GLIBCXX_LDBL_3.4@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt3tr14hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2 + _ZNKSt4hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2 + _ZGVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1 + _ZGVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1 + _ZGVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1 + _ZGVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1 + _ZGVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1 + _ZGVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1 + _ZGVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1 + _ZGVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIjEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIlEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intImEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intItEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIxEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIyEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16_M_extract_floatES4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1 + _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1 + 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_ZTINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTIPKg@CXXABI_LDBL_1.3 4.2.1 + _ZTIPg@CXXABI_LDBL_1.3 4.2.1 + _ZTIg@CXXABI_LDBL_1.3 4.2.1 + _ZTSNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTSNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTSNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTSNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTSNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTSNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTSNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTSNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTSPKg@CXXABI_LDBL_1.3 4.2.1 + _ZTSPg@CXXABI_LDBL_1.3 4.2.1 + _ZTSg@CXXABI_LDBL_1.3 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1 + _ZTVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1 --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.sparc64 +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.sparc64 @@ -0,0 +1,106 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4.4@GCC_3.4.4 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GLIBC_2.2@GLIBC_2.2 1:4.1.1 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __absvti2@GCC_3.4.4 1:4.1.1 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __addvti3@GCC_3.4.4 1:4.1.1 + __ashlti3@GCC_3.0 1:4.1.1 + __ashrti3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzti2@GCC_3.4 1:4.1.1 + __cmpti2@GCC_3.0 1:4.1.1 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzti2@GCC_3.4 1:4.1.1 + __deregister_frame@GLIBC_2.2 1:4.1.1 + __deregister_frame_info@GLIBC_2.2 1:4.1.1 + __deregister_frame_info_bases@GCC_3.0 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + __divtc3@GCC_4.0.0 1:4.1.1 + __divti3@GCC_3.0 1:4.1.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 1:4.1.1 + __ffsdi2@GCC_3.0 1:4.1.1 + __ffsti2@GCC_3.0 1:4.1.1 + __fixdfti@GCC_3.0 1:4.1.1 + __fixsfti@GCC_3.0 1:4.1.1 + __fixtfti@GCC_3.0 1:4.1.1 + __fixunsdfdi@GCC_3.0 1:4.1.1 + __fixunsdfti@GCC_3.0 1:4.1.1 + __fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfti@GCC_3.0 1:4.1.1 + __fixunstfti@GCC_3.0 1:4.1.1 + __floattidf@GCC_3.0 1:4.1.1 + __floattisf@GCC_3.0 1:4.1.1 + __floattitf@GCC_3.0 1:4.1.1 + __floatuntidf@GCC_4.2.0 1:4.2.1 + __floatuntisf@GCC_4.2.0 1:4.2.1 + __floatuntitf@GCC_4.2.0 1:4.2.1 + __frame_state_for@GLIBC_2.2 1:4.1.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __lshrti3@GCC_3.0 1:4.1.1 + __modti3@GCC_3.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_4.0.0 1:4.1.1 + __multi3@GCC_3.0 1:4.1.1 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __mulvti3@GCC_3.4.4 1:4.1.1 + __negti2@GCC_3.0 1:4.1.1 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __negvti2@GCC_3.4.4 1:4.1.1 + __paritydi2@GCC_3.4 1:4.1.1 + __parityti2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountti2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_4.0.0 1:4.1.1 + __register_frame@GLIBC_2.2 1:4.1.1 + __register_frame_info@GLIBC_2.2 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GLIBC_2.2 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GLIBC_2.2 1:4.1.1 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __subvti3@GCC_3.4.4 1:4.1.1 + __ucmpti2@GCC_3.0 1:4.1.1 + __udivmodti4@GCC_3.0 1:4.1.1 + __udivti3@GCC_3.0 1:4.1.1 + __umodti3@GCC_3.0 1:4.1.1 --- gcc-4.5-4.5.2.orig/debian/rules.unpack +++ gcc-4.5-4.5.2/debian/rules.unpack @@ -0,0 +1,238 @@ +# -*- makefile -*- +# rules to unpack the source tarballs in $(srcdir); if the source dir already +# exists, the rule exits with an error to prevent deletion of modified +# source files. It has to be deleted manually. + +tarballs = $(gcc_tarball) # $(gcj_tarball) +ifeq ($(with_d),yes) + tarballs += $(gdc_tarball) +endif + +unpack_stamps = $(foreach i,$(tarballs),$(unpack_stamp)-$(i)) + +unpack: stamp-dir $(unpack_stamp) debian-chmod +$(unpack_stamp): $(unpack_stamps) +$(unpack_stamp): $(foreach p,$(debian_tarballs),unpacked-$(p)) + echo -e "\nBuilt from Debian source package $(PKGSOURCE)-$(SOURCE_VERSION)" \ + > pxxx + echo -e "Integrated upstream packages in this version:\n" >> pxxx + for i in $(tarballs); do echo " $$i" >> pxxx; done + mv -f pxxx $@ + +debian-chmod: + @chmod 755 debian/dh_* + +# --------------------------------------------------------------------------- + +gfdl_texinfo_files = \ + gcc/doc/arm-neon-intrinsics.texi \ + gcc/doc/bugreport.texi \ + gcc/doc/c-tree.texi \ + gcc/doc/cfg.texi \ + gcc/doc/collect2.texi \ + gcc/doc/compat.texi \ + gcc/doc/configfiles.texi \ + gcc/doc/configterms.texi \ + gcc/doc/contrib.texi \ + gcc/doc/contribute.texi \ + gcc/doc/cpp.texi \ + gcc/doc/cppenv.texi \ + gcc/doc/cppinternals.texi \ + gcc/doc/cppopts.texi \ + gcc/doc/extend.texi \ + gcc/doc/fragments.texi \ + gcc/doc/frontends.texi \ + gcc/doc/gccint.texi \ + gcc/doc/gcov.texi \ + gcc/doc/generic.texi \ + gcc/doc/gimple.texi \ + gcc/doc/gnu.texi \ + gcc/doc/gty.texi \ + gcc/doc/headerdirs.texi \ + gcc/doc/hostconfig.texi \ + gcc/doc/implement-c.texi \ + gcc/doc/implement-cxx.texi \ + gcc/doc/install-old.texi \ + gcc/doc/install.texi \ + gcc/doc/interface.texi \ + gcc/doc/invoke.texi \ + gcc/doc/languages.texi \ + gcc/doc/libgcc.texi \ + gcc/doc/loop.texi \ + gcc/doc/makefile.texi \ + gcc/doc/md.texi \ + gcc/doc/objc.texi \ + gcc/doc/options.texi \ + gcc/doc/passes.texi \ + gcc/doc/plugin.texi \ + gcc/doc/portability.texi \ + gcc/doc/rtl.texi \ + gcc/doc/service.texi \ + gcc/doc/sourcebuild.texi \ + gcc/doc/standards.texi \ + gcc/doc/tm.texi \ + gcc/doc/tree-ssa.texi \ + gcc/doc/trouble.texi \ + gcc/doc/include/gcc-common.texi \ + gcc/doc/include/funding.texi \ + gcc/fortran/gfc-internals.texi \ + gcc/fortran/invoke.texi \ + gcc/fortran/intrinsic.texi \ + + +gfdl_toplevel_texinfo_files = \ + gcc/doc/gcc.texi \ + gcc/java/gcj.texi \ + gcc/ada/gnat-style.texi \ + gcc/ada/gnat_rm.texi \ + gcc/ada/gnat_ugn.texi \ + gcc/fortran/gfortran.texi \ + libgomp/libgomp.texi \ + +gfdl_manpages = \ + gcc/doc/cpp.1 \ + gcc/doc/g++.1 \ + gcc/doc/gc-analyze.1 \ + gcc/doc/gcc.1 \ + gcc/doc/gcj.1 \ + gcc/doc/gcj-dbtool.1 \ + gcc/doc/gcjh.1 \ + gcc/doc/gcov.1 \ + gcc/doc/gfortran.1 \ + gcc/doc/gij.1 \ + gcc/doc/grmic.1 \ + gcc/doc/grmiregistry.1 \ + gcc/doc/jcf-dump.1 \ + gcc/doc/jv-convert.1 \ + gcc/doc/fsf-funding.7 \ + +# --------------------------------------------------------------------------- +$(unpack_stamp)-$(gcc_tarball): $(gcc_tarpath) + : # unpack gcc tarball + -mkdir $(stampdir) + if [ -d $(srcdir) ]; then \ + echo >&2 "Source directory $(srcdir) exists. Delete by hand"; \ + false; \ + fi + rm -rf $(gcc_srcdir) + case $(gcc_tarball) in \ + *.bz2) tar -x --bzip2 -f $(gcc_tarpath);; \ + *.gz) tar -x --gzip -f $(gcc_tarpath);; \ + *.lzma) lzcat $(gcc_tarpath) | tar -x -f -;; \ + *.xz) xzcat $(gcc_tarpath) | tar -x -f -;; \ + *) false; \ + esac + mv $(gcc_srcdir) $(srcdir) +ifneq (,$(wildcard java-class-files.tar.xz.uue)) +# work around #533356 +# uudecode -o - java-class-files.tar.xz.uue | tar -C src -xvz + uudecode java-class-files.tar.xz.uue + xzcat java-class-files.tar.xz | tar -C src -xv -f - + rm -f java-class-files.tar.xz +endif +#ifeq ($(with_java),yes) +# tar -x -C $(srcdir)/libjava/testsuite/libmauve.exp \ +# $(wildcard /usr/src/mauve*.tar.*) +#endif +ifeq (0,1) + cd $(srcdir) && tar cfj ../gcc-4.1.1-doc.tar.bz2 \ + $(gfdl_texinfo_files) \ + $(gfdl_toplevel_texinfo_files) \ + $(gfdl_manpages) +endif +ifeq ($(GFDL_INVARIANT_FREE),yes) + ifneq ($(PKGSOURCE),gcc-snapshot) + rm -f $(srcdir)/gcc/doc/*.1 + rm -f $(srcdir)/gcc/doc/fsf-funding.7 + rm -f $(srcdir)/gcc/doc/*.info + rm -f $(srcdir)/gcc/fortran/*.info + rm -f $(srcdir)/libgomp/*.info + rm -f $(srcdir)/gcc/java/*.1 + rm -f $(srcdir)/gcc/java/*.info + for i in $(gfdl_texinfo_files); do \ + if [ -f $(srcdir)/$$i ]; then \ + cp $(SOURCE_DIR)debian/dummy.texi $(srcdir)/$$i; \ + else \ + echo >&2 "$$i does not exist, fix debian/rules.unpack"; \ + fi; \ + done + for i in $(gfdl_toplevel_texinfo_files); do \ + n=$$(basename $$i .texi); \ + if [ -f $(srcdir)/$$i ]; then \ + sed "s/@name@/$$n/g" $(SOURCE_DIR)debian/gcc-dummy.texi \ + > $(srcdir)/$$i; \ + else \ + echo >&2 "$$i does not exist, fix debian/rules.unpack"; \ + fi; \ + done + for i in $(gfdl_manpages); do \ + touch $(srcdir)/$$i; \ + done + rm -f $(srcdir)/INSTALL/*.html + endif +endif + echo "$(gcc_tarball) unpacked." > $@ + +# --------------------------------------------------------------------------- +ifneq (,$(gcj_tarball)) +$(unpack_stamp)-$(gcj_tarball): $(gcj_tarpath) $(unpack_stamp)-$(gcc_tarball) + : # unpack gcj tarball + rm -rf $(srcdir)/gcc/java $(srcdir)/libjava + tar -x -C $(srcdir) -f $(gcj_tarpath) +ifeq ($(GFDL_INVARIANT_FREE),yes) + ifneq ($(PKGSOURCE),gcc-snapshot) + rm -f $(srcdir)/gcc/java/*.1 + rm -f $(srcdir)/gcc/java/*.info + for i in $(gfdl_texinfo_files); do \ + if [ -f $(srcdir)/$$i ]; then \ + cp $(SOURCE_DIR)debian/dummy.texi $(srcdir)/$$i; \ + else \ + echo >&2 "$$i does not exist, fix debian/rules.unpack"; \ + fi; \ + done + for i in $(gfdl_toplevel_texinfo_files); do \ + n=$$(basename $$i .texi); \ + if [ -f $(srcdir)/$$i ]; then \ + sed "s/@name@/$$n/g" $(SOURCE_DIR)debian/gcc-dummy.texi \ + > $(srcdir)/$$i; \ + else \ + echo >&2 "$$i does not exist, fix debian/rules.unpack"; \ + fi; \ + done + endif +endif + echo "$(gcj_tarball) unpacked." > $@ +endif + +# --------------------------------------------------------------------------- +ifneq (,$(gdc_tarball)) +$(unpack_stamp)-$(gdc_tarball): $(gdc_tarpath) + : # unpack gdc tarball + -mkdir $(stampdir) + if [ -d $(srcdir)/gcc/d ]; then \ + echo >&2 "Source directory $(srcdir)/gcc/d exists. Delete by hand";\ + false; \ + fi + #rm -rf $(gdc_srcdir) + rm -rf d + case $(gdc_tarball) in \ + *.bz2) tar -x --bzip2 -f $(gdc_tarpath);; \ + *.gz) tar -x --gzip -f $(gdc_tarpath);; \ + *.lzma) lzcat $(gdc_tarpath) | tar -x -f -;; \ + *.xz) xzcat $(gdc_tarpath) | tar -x -f -;; \ + *) false; \ + esac + if [ -d d ]; then \ + mv d $(srcdir)/gcc/. ; \ + else \ + mv $(gdc_srcdir)/d $(srcdir)/gcc/. ; \ + rm -rf $(gdc_srcdir)/CVS; \ + rmdir $(gdc_srcdir); \ + fi + [ -d $(srcdir)/libphobos ] && rm -rf $(srcdir)/libphobos || true + mkdir $(srcdir)/libphobos && \ + cd $(srcdir)/libphobos && \ + ../symlink-tree ../gcc/d/phobos 2>&1 && \ + cd $(srcdir) + echo "$(gdc_tarball) unpacked." > $@ +endif --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.32bit +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.32bit @@ -0,0 +1,541 @@ +#include "libstdc++6.symbols.common" + _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEj@GLIBCXX_3.4.2 4.1.1 + _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEj@GLIBCXX_3.4.2 4.1.1 + _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcj@GLIBCXX_3.4.4 4.1.1 + _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEjj@GLIBCXX_3.4.4 4.1.1 + _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcj@GLIBCXX_3.4.4 4.1.1 + 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Eigler , Graydon Hoare + +Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2, or (at your option) any later +version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file into combinations with other programs, +and to distribute those combinations without any restriction coming +from the use of this file. (The General Public License restrictions +do apply in other respects; for example, they cover modification of +the file, and distribution when not linked into a combine +executable.) + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +On Debian GNU/Linux systems, the complete text of the GNU General +Public License can be found in `/usr/share/common-licenses/GPL'. --- gcc-4.5-4.5.2.orig/debian/gpc-4.5-doc.doc-base.gpcs +++ gcc-4.5-4.5.2/debian/gpc-4.5-doc.doc-base.gpcs @@ -0,0 +1,23 @@ +Document: gpcs-4.5-doc +Title: The GNU Pascal Coding Standards +Author: Various +Abstract: The GNU Pascal Coding Standards were designed by a group of + GNU Pascal project volunteers. The aim of this document is extending + the GNU Coding Standards with specific information relating Pascal + programming. As a matter of fact, the information contained in the + GNU Coding Standards mainly pertains to programs written in the C + language. On the other hand, they also explain many of the rules and + principles that are useful for writing portable, robust and reliable + programs. Most of those general topics could be shared with this + document with just a few specific notes, thus cross references are + provided which will lead you to the more extensive information + contained in the GNU Coding Standards. +Section: Programming/Pascal + +Format: html +Index: /usr/share/doc/gcc-4.5-base/pascal/gpcs.html +Files: /usr/share/doc/gcc-4.5-base/pascal/gpcs.html + +Format: info +Index: /usr/share/info/gpcs-4.5.info.gz +Files: /usr/share/info/gpcs-4.5* --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.alpha +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.alpha @@ -0,0 +1,107 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4.4@GCC_3.4.4 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GCC_LDBL_4.0.0@GCC_LDBL_4.0.0 1:4.2.1 + GLIBC_2.0@GLIBC_2.0 1:4.1.1 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __absvti2@GCC_3.4.4 1:4.1.1 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __addvti3@GCC_3.4.4 1:4.1.1 + __ashlti3@GCC_3.0 1:4.1.1 + __ashrti3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzti2@GCC_3.4 1:4.1.1 + __cmpti2@GCC_3.0 1:4.1.1 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzti2@GCC_3.4 1:4.1.1 + __deregister_frame@GLIBC_2.0 1:4.1.1 + __deregister_frame_info@GLIBC_2.0 1:4.1.1 + __deregister_frame_info_bases@GCC_3.0 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + __divtc3@GCC_LDBL_4.0.0 1:4.2.1 + __divti3@GCC_3.0 1:4.1.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 1:4.1.1 + __ffsdi2@GCC_3.0 1:4.1.1 + __ffsti2@GCC_3.0 1:4.1.1 + __fixdfti@GCC_3.0 1:4.1.1 + __fixsfti@GCC_3.0 1:4.1.1 + __fixtfti@GCC_3.0 1:4.2.1 + __fixunsdfdi@GCC_3.0 1:4.1.1 + __fixunsdfti@GCC_3.0 1:4.1.1 + __fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfti@GCC_3.0 1:4.1.1 + __fixunstfti@GCC_3.0 1:4.2.1 + __floattidf@GCC_3.0 1:4.1.1 + __floattisf@GCC_3.0 1:4.1.1 + __floattitf@GCC_3.0 1:4.2.1 + __floatuntidf@GCC_4.2.0 1:4.2.1 + __floatuntisf@GCC_4.2.0 1:4.2.1 + __floatuntitf@GCC_4.2.0 1:4.2.1 + __frame_state_for@GLIBC_2.0 1:4.1.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __lshrti3@GCC_3.0 1:4.1.1 + __modti3@GCC_3.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_LDBL_4.0.0 1:4.2.1 + __multi3@GCC_3.0 1:4.1.1 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __mulvti3@GCC_3.4.4 1:4.1.1 + __negti2@GCC_3.0 1:4.1.1 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __negvti2@GCC_3.4.4 1:4.1.1 + __paritydi2@GCC_3.4 1:4.1.1 + __parityti2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountti2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_LDBL_4.0.0 1:4.2.1 + __register_frame@GLIBC_2.0 1:4.1.1 + __register_frame_info@GLIBC_2.0 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GLIBC_2.0 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GLIBC_2.0 1:4.1.1 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __subvti3@GCC_3.4.4 1:4.1.1 + __ucmpti2@GCC_3.0 1:4.1.1 + __udivmodti4@GCC_3.0 1:4.1.1 + __udivti3@GCC_3.0 1:4.1.1 + __umodti3@GCC_3.0 1:4.1.1 --- gcc-4.5-4.5.2.orig/debian/reduce-test-diff.awk +++ gcc-4.5-4.5.2/debian/reduce-test-diff.awk @@ -0,0 +1,33 @@ +#! /usr/bin/gawk -f + +BEGIN { + skip=0 + warn=0 +} + +/^-(FAIL|ERROR|UNRESOLVED|WARNING)/ { + next +} + +# only compare gcc, g++, g77 and objc results +/=== treelang tests ===/ { + skip=1 +} + +# omit extra files appended to test-summary +/^\+Compiler version/ { + skip=1 +} + +skip == 0 { + print + next +} + +/^\+(FAIL|ERROR|UNRESOLVED|WARNING)/ { + warn=1 +} + +END { + exit warn +} --- gcc-4.5-4.5.2.orig/debian/lib64gfortran3.symbols.powerpc +++ gcc-4.5-4.5.2/debian/lib64gfortran3.symbols.powerpc @@ -0,0 +1,5 @@ +libgfortran.so.3 lib64gfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.16.powerpc" +#include "libgfortran3.symbols.16.powerpc64" +#include "libgfortran3.symbols.64" --- gcc-4.5-4.5.2.orig/debian/gcjh-wrapper-BV.1 +++ gcc-4.5-4.5.2/debian/gcjh-wrapper-BV.1 @@ -0,0 +1,20 @@ +.TH GCJH-WRAPPER 1 "June 6, 2002" gcjh-wrapper "Java User's Manual" +.SH NAME +gcjh-wrapper \- a wrapper around gcjh + +.SH SYNOPSIS +gcjh-wrapper [\fB\s-1OPTION\s0\fR] ... [\fI\s-1ARGS\s0\fR...] + +.SH DESCRIPTION + +\fBgcjh-wrapper\fR is a wrapper around gcjh(1) to be called as the java header +compiler. Options different for javah(1) and gcjh(1) are translated, +options unknown to gcjh(1) are silently ignored. + +.SH OPTIONS +See gcjh-@BV@(1) for a list of options that gcj understands. + +.SH "SEE ALSO" +.BR gcjh-@BV@(1) +, +.BR javah(1) --- gcc-4.5-4.5.2.orig/debian/lib64gfortran3.symbols.mipsel +++ gcc-4.5-4.5.2/debian/lib64gfortran3.symbols.mipsel @@ -0,0 +1,5 @@ +libgfortran.so.3 lib64gfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.16.powerpc" +#include "libgfortran3.symbols.16.powerpc64" +#include "libgfortran3.symbols.64" --- gcc-4.5-4.5.2.orig/debian/FAQ.gcj +++ gcc-4.5-4.5.2/debian/FAQ.gcj @@ -0,0 +1,494 @@ +The GCJ FAQ +=========== + + The latest version of this document is always available at + http://gcc.gnu.org/java/faq.html. + + General Questions + + What license is used for libgcj? + How can I report a bug in libgcj? + How can I contribute to libgcj + Is libgcj part of GCC? + Will gcj and libgcj work on my machine? + How can I debug my Java program? + Can I interface byte-compiled and native java code? + + + Java Feature Support + + What Java API's are supported? How complete is + the support? + Does GCJ support using straight C native methods + ala JNI? + Why does GCJ use CNI? + What is the state of AWT support? + How about support for Swing ? + What support is there for RMI ? + Can I use any code from other OpenSource projects + to supplement libgcj's current features ? + What features of the Java language are/arn't supported + + + Build Issues + + I need something more recent than the last release; how + should I build it? + Linker bug on Solaris + Can I configure/build in the source tree? + My libgcj build fails with "invalid use of undefined type + struct sigcontext_struct" + + + Gcj Compile/Link Questions + + Why do I get undefined reference to `main' errors? + Can GCJ only handle source code? + "gcj -C" Doesn't seem to work like javac/jikes. Whats going on? + Where does GCJ look for files? + How does gcj resolve wether to compile .class or .java files? + I'm getting link errors! + I'm getting 'undefined symbol: __dso_handle' + + + Runtime Questions + + My program is dumping core! What's going on? + When I run the debugger I get a SEGV in the GC! What's going on? + I have just compiled and benchmarked my Java application + and it seems to be running slower than than XXX JIT JVM. Is there + anything I can do to make it go faster? + Can I profile Garbage Collection? + How do I increase the runtime's initial and maximum heap sizes? + How can I profile my application? + My program seems to hang and doesn't produce any output + + + Programming Issues + + Are there any examples of how to use CNI? + Is it possible to invoke GCJ compiled Java code from a + C++ application? + +General Questions +================= + + 1.1 What license is used for libgcj? + + libgcj is distributed under the GPL, with the 'libgcc exception'. + This means that linking with libgcj does not by itself cause + your program to fall under the GPL. See LIBGCJ_LICENSE in + the source tree for more details. + + 1.2 How can I report a bug in libgcj? + + libgcj has a corresponding Gnats bug database which you can + browse. You can also submit new bug reports from the Gnats + page. + + 1.3 How can I contribute to libgcj? + + You can send simple bug fixes in as patches. Please follow + the GCC guidelines for submitting patches. For more complex + changes, you must sign copyright over to the Free Software + Foundation. See the contribution page for details. + + 1.4 Is libgcj part of GCC? + + Yes, libgcj is now part of GCC. It can be downloaded, + configured and built as one single tree. + + 1.5 Will gcj and libgcj work on my machine? + + Gcj and libgcj are known to work more or less with IA-32 and + Sparc Solaris, Tru64 Unix, as well as IA-32, IA-64, Alpha, + and PowerPC Linux. They might work on other + systems. Generally speaking, porting to a new system should + not be hard. This would be a good way to volunteer. + + 1.6 How can I debug my Java program? + + gdb 5.0 includes support for debugging gcj-compiled Java + programs. For more information please read Java Debugging + with gdb. + + 1.7 Can I interface byte-compiled and native java code + + libgcj has a bytecode interpreter that allows you to mix + .class files with compiled code. It works pretty + transparently: if a compiled version of a class is not found + in the application binary or linked shared libraries, the + class loader will search for a bytecode version in your + classpath, much like a VM would. Be sure to build libgcj + with the --enable-interpreter option to enable this + functionality. + + The program "gij" provides a front end to the interpreter + that behaves much like a traditional virtual machine. You + can even use "gij" to run a shared library which is compiled + from java code and contains a main method: + + $ gcj -shared -o lib-HelloWorld.so HelloWorld.java + $ gij HelloWorld + + This works because gij uses Class.forName, which knows how + to load shared objects. + +Java Feature Support +==================== + + 2.1 What Java API's are supported? How complete is + the support? + + Matt Welsh writes: + + Just look in the 'libjava' directory of libgcj and see + what classes are there. Most GUI stuff isn't there yet, + that's true, but many of the other classes are easy to add + if they don't yet exist. + + I think it's important to stress that there is a big + difference between Java and the many libraries which Java + supports. Unfortunately, Sun's promise of "write once, run + everywhere" assumes much more than a JVM: you also need + the full set of JDK libraries. Considering that new Java + APIs come out every week, it's going to be impossible to + track everything. + + To make things worse, you can't simply run Sun's JDK + classes on any old JVM -- they assume that a bunch of + native methods are also defined. Since this native method + requirement isn't defined by the JDK specs, you're + effectively constrained to using Sun's JVMs if you want to + use Sun's JDK libraries. Oh yes -- you could also + reimplement all of those native methods yourself, and make + sure they behave exactly as Sun's do. Note that they're + undocumented! + + 2.2 Does GCJ support using straight C native methods + ala JNI? + + Yes. libgcj now has experimental support for JNI, in + addition to its native Compiled Native Interface (CNI). gcjh + will generate JNI stubs and headers using the "-jni" + option. However, we do prefer CNI: it is more efficient, + easier to write, and (at least potentially) easier to debug. + + 2.3 Why does GCJ use CNI? + + Per Bothner explains: + + We use CNI because we think it is a better solution, + especially for a Java implementation that is based on the + idea that Java is just another programming language that + can be implemented using standard compilation + techniques. Given that, and the idea that languages + implemented using Gcc should be compatible where it makes + sense, it follows that the Java calling convention should + be as similar as practical to that used for other + languages, especially C++, since we can think of Java as a + subset of C++. CNI is just a set of helper functions and + conventions built on the idea that C++ and Java have the + *same* calling convention and object layout; they are + binary compatible. (This is a simplification, but close + enough.) + + 2.4 What is the state of AWT support? + + Work is in progress to implement AWT and Java2D. We intend + to support both GTK and xlib peers written using CNI. Some + components are already working atop the xlib peers. + + 2.5 How about support for Swing? + + Once AWT support is working then Swing support can be + considered. There is at least one free-software partial + implementations of Swing that may be usable. + + 2.6 What support is there for RMI? + + RMI code exists on the CVS trunk (aka gcc 3.1), but it has + not been heavily tested. This code was donated by + Transvirtual Technologies. + + 2.7 Can I use any code from other OpenSource + projects to supplement libgcj's current features? + + Certainly. However, in many cases, if you wanted to + contribute the code back into the official libgcj + distribution, we would require that the original author(s) + assign copyright to the Free Software Foundation. As of + March 6, 2000, libgcj has been relicenced, and copyright + has been assigned to the FSF. This allows us to share and + merge much of the libgcj codebase with the Classpath + project. Our eventual goal is for Classpath to be an + upstream source provider for libgcj, however it will be + some time before this becomes reality: libgcj and Classpath + have different implementations of many core java + classes. In order to merge them, we need to select the best + (most efficient, cleanest) implementation of each + method/class/package, resolve any conflicts created by the + merge, and test the final result. Needless to say, this is + a lot of work. If you can help out, please let us know! + + 2.8 What features of the Java language are/aren't supported. + + GCJ supports all Java language constructs as per the Java + language Specification. Recent GCJ snapshots have added + support for most JDK1.1 (and beyond) language features, + including inner classes. + +Build Issues +============ + + 3.1 I need something more recent than the last release. + How should I build it? + + Please read here: http://gcc.gnu.org/java/build-snapshot.html + + 3.2 Linker bug on Solaris + + There is a known problem with the native Solaris linker when + using gcc/gcj. A good indication you've run into this + problem is if you get an error that looks like the following + when building libgcj: + +ld: warning: option -o appears more than once, first setting taken +ld: fatal: file libfoo.so: cannot open file: No such file or directory +ld: fatal: File processing errors. No output written to .libs/libfoo.so +collect2: ld returned 1 exit status + + A known workaround for this and other reported link problems + on the various releases of Solaris is to build gcc/gcj with + the latest GNU binutils instead of the native Solaris + ld. The most straightforward way to do this is to build and + install binutils, and then reference it in the configure for + gcc via --with-ld=/path_to_binutils_install/bin/ld + (--with-as may also be similarly specified but is not + believed to be required). + + Please note, gcc/gcj must be built using GNU ld prior to + doing a clean build of libgcj! + + 3.3 Can I configure/build in the source tree? + + No. You cannot configure/build in the source tree. If you + try, you'll see something like: + + $ ./configure [...] + Configuring for a i686-pc-linux-gnu host. + *** Cannot currently configure in source tree. + + Instead, you must build in another directory. E.g.: + + $ mkdir build + $ cd build + $ ../configure [...] + + 3.4 My libgcj build fails with "invalid use of undefined type + struct sigcontext_struct" + + If you're using Linux, this probably means you need to + upgrade to a newwer, glibc (libc6) based Linux + distribution. libgcj does not support the older linux libc5. + It might be possible to get a working libgcj by changing + occurances of "sigcontext_struct" to "sigcontext", however + this has not been tested. Even if it works, it is likely + that there are other issues with older libc versions that + would prevent libgcj from working correctly (threads bugs, + for example). + +Gcj Compile/Link Questions +========================== + + 4.1 Why do I get undefined reference to `main' errors? + + When using gcj to link a Java program, you must use the --main= + option to indicate the class that has the desired main method. + This is because every Java class can have a main method, thus + you have to tell gcj which one to use. + + 4.2 Can GCJ only handle source code? + + GCJ will compile both source (.java) and bytecode (.class) + files. However, in many cases the native code produced by + compiling from source is better optimized than that compiled + from .class files. + + Per Bothner explains: + + The reason is that when you compile to bytecode you lose a + lot of information about program structure etc. That + information helps in generating better code. We can in + theory recover the information we need by analysing the + structure of the bytecodes, but it is sometimes difficult + - or sometimes it just that no-one has gotten around to + it. Specific examples include loop structure (gcc + generates better code with explicit loops rather than with + the equivalent spaghetti code), array initializers, and + the JDK 1.1 `CLASS.class' syntax, all of which are + represented using more low-level constructs in bytecode. + + 4.3 "gcj -C" Doesn't seem to work like javac/jikes. Whats going on? + + The behavior of "gcj -C" is not at all like javac or jikes, + which will compile (not just scan) all .java's which are out + of date with regard to their .class's. + + 4.4 Where does GCJ look for files? + + GCJ looks for classes to compile based on the CLASSPATH + environment variable. libgcj.jar and other files are found + relative to the path of the compiler itself, so it is safe + to move the entire compiler tree to a different path, and + there is no need to include libgcj.jar in your CLASSPATH. + + 4.5 How does gcj resolve whether to compile .class or .java files? + + GCJ compiles only the files presented to it on the command + line. However, it also needs to scan other files in order to + determine the layout of other classes and check for errors + in your code. For these dependencies, GCJ will favour + .class files if they are available because it is faster to + parse a class file than source code. + + 4.6 I'm getting link errors + + If you get errors at link time that refer to 'undefined + reference to `java::lang::Object type_info function', verify + that you have compiled any CNI C++ files with the -fno-rtti + option. This is only required for versions of GCJ earlier + than 3.0. + + 4.7 I'm getting 'undefined symbol: __dso_handle' + + Some versions of the GNU linker have broken support for the + '.hidden' directive, which results in problems with shared + libraries built with recent versions of gcc. + + There are three solutions: + + - downgrade to binutils that don't support .hidden at all, + - upgrade to a recent binutils, or + - undef the HAVE_GAS_HIDDEN definition in gcc's auto-host.h + (and rebuild gcc). + +Runtime Questions +================= + + 5.1 My program is dumping core! What's going on? + + It could be any number of things. One common mistake is + having your CLASSPATH environment variable pointing at a + third party's java.lang and friends. Either unset CLASSPATH, + or make sure it does not refer to core libraries other than + those found in libgcj.jar.Note that newwer versions of GCJ + will reject the core class library if it wasn't generated by + GCJ itself. + + 5.2 When I run the debugger I get a SEGV in the GC! What's going on? + + This is "normal"; the Garbage Collector (GC) uses it to + determine stack boundaries. It is ordinarily caught and + handled by the GC -- you can see this in the debugger by + using cont to continue to the "real" segv. + + 5.3 I have just compiled and benchmarked my Java application + and it seems to be running slower than than XXX JIT JVM. Is there + anything I can do to make it go faster? + + A few things: + + - If your programs allocate many small, short lived objects, + the heap could be filling and triggering GC too + regularly. Try increasing the initial and maximum heap sizes + as per 5.5 How do I increase the runtime's initial and + maximum heap size? + - RE - array accesses. We have sub-optimal runtime checking + code, and the compiler is still not so smart about + automatically removing array checks. If your code is ready, + and it doesn't rely on them, try compiling with + --no-bounds-check. + - Try static linking. On many platforms, dynamic (PIC) + function calls are more expensive than static ones. In + particular, the interaction with boehm-gc seems to incur + extra overhead when shared libraries are used. + - If your Java application doesn't need threads, try + building libgcj using --enable-threads=none. Portions of the + libgcj runtime are still more efficient when + single-threaded. + + 5.4 Can I profile Garbage Collection? + + It is possible to turn on verbose GC output by supressing + the -DSILENT flag during build. One way to do this is to + comment out the line with #define SILENT 1 from + boehm-gc/configure before configuring libgcj. The GC will + print collection statistics to stdout. (Rebuilding boehm-gc + alone without this flag doesn't seem to work.) + + 5.5 How do I increase the runtime's initial and maximum heap sizes? + + Some programs that allocate many small, short-lived objects + can cause the default-sized heap to fill quickly and GC + often. With the 2.95.1 release there is no means to adjust + the heap at runtime. Recent snapshots provide the -ms and + -mx arguments to gij to specify the initial and maximum heap + sizes, respectively. + + 5.6 How can I profile my application? + + Currently, only single threaded Java code may be used by the + profiler (gprof). POSIX threads seem to be incompatible with + the gmon stuff. A couple of other tools that have been + mentioned on the GCJ mailing list are sprof and cprof. The + former is part of GNU libc. + + 5.7 My program seems to hang and doesn't produce any output + + Some versions had a bug in the iconv support. You can work + around it by setting LANG=en_US.UTF-8 at runtime, or give + the following option during compile time + -Dfile.encoding=UTF-8. This problem should no longer occur + as of November 1, 2000. + +Programming Issues +================== + + 6.1 Are there any examples of how to use CNI? + + Glenn Chambers has created a couple of trivial examples for + version 2.95 and version 3.0. As a comparison, here is the + same example as a JNI application using Kaffe. The same + code will work with GCJ, as shown here. + + Note that for version 2.95, you must compile the C++ files + used for CNI with the -fno-rtti option. This constraint + does not apply in version 3.0 and later. + + The primary source of documentation for CNI is at + http://gcc.gnu.org/java/papers/cni/t1.html + + 6.2 Is it possible to invoke GCJ compiled Java code from a + C++ application? + + Yes, GCJ 3.1 supports a CNI-based invocation interface as + well as the traditional JNI invocation API. See the GCJ + Manual for more details on how to use the CNI interface. + +Please send FSF & GNU inquiries & questions tognu@gnu.org.There are +also other waysto contact the FSF. + +These pages are maintained by The GCC team. + +Please send comments on these web pages and GCC to our publicmailing +list at gcc@gnu.org orgcc@gcc.gnu.org, send other questions to +gnu@gnu.org. + +Copyright (C) Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111, USA. + +Verbatim copying and distribution of this entire article is permitted +in any medium, provided this notice is preserved. + +Last modified 2003-04-30 --- gcc-4.5-4.5.2.orig/debian/lib32gcc1.symbols.amd64 +++ gcc-4.5-4.5.2/debian/lib32gcc1.symbols.amd64 @@ -0,0 +1,134 @@ +libgcc_s.so.1 lib32gcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GCC_4.4.0@GCC_4.4.0 1:4.4.0 + GCC_4.5.0@GCC_4.5.0 1:4.5.0 + GLIBC_2.0@GLIBC_2.0 1:4.1.1 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __addtf3@GCC_4.4.0 1:4.4.0 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __ashldi3@GCC_3.0 1:4.1.1 + __ashrdi3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzsi2@GCC_3.4 1:4.1.1 + __cmpdi2@GCC_3.0 1:4.1.1 + __copysigntf3@GCC_4.4.0 1:4.4.0 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzsi2@GCC_3.4 1:4.1.1 + __deregister_frame@GLIBC_2.0 1:4.1.1 + __deregister_frame_info@GLIBC_2.0 1:4.1.1 + __deregister_frame_info_bases@GCC_3.0 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divdi3@GLIBC_2.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + __divtc3@GCC_4.4.0 1:4.4.0 + __divtf3@GCC_4.4.0 1:4.4.0 + __divxc3@GCC_4.0.0 1:4.1.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 1:4.1.1 + __eqtf2@GCC_4.4.0 1:4.4.0 + __extenddftf2@GCC_4.4.0 1:4.4.0 + __extendsftf2@GCC_4.4.0 1:4.4.0 + __extendxftf2@GCC_4.5.0 1:4.5.0 + __fabstf2@GCC_4.4.0 1:4.4.0 + __ffsdi2@GCC_3.0 1:4.1.1 + __ffssi2@GCC_4.3.0 1:4.3 + __fixdfdi@GCC_3.0 1:4.1.1 + __fixsfdi@GCC_3.0 1:4.1.1 + __fixtfdi@GCC_4.4.0 1:4.4.0 + __fixtfsi@GCC_4.4.0 1:4.4.0 + __fixunsdfdi@GCC_3.0 1:4.1.1 + __fixunsdfsi@GCC_3.0 1:4.1.1 + __fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfsi@GCC_3.0 1:4.1.1 + __fixunstfdi@GCC_4.4.0 1:4.4.0 + __fixunstfsi@GCC_4.4.0 1:4.4.0 + __fixunsxfdi@GCC_3.0 1:4.1.1 + __fixunsxfsi@GCC_3.0 1:4.1.1 + __fixxfdi@GCC_3.0 1:4.1.1 + __floatdidf@GCC_3.0 1:4.1.1 + __floatdisf@GCC_3.0 1:4.1.1 + __floatditf@GCC_4.4.0 1:4.4.0 + __floatdixf@GCC_3.0 1:4.1.1 + __floatsitf@GCC_4.4.0 1:4.4.0 + __floatundidf@GCC_4.2.0 1:4.2.1 + __floatundisf@GCC_4.2.0 1:4.2.1 + __floatunditf@GCC_4.4.0 1:4.4.0 + __floatundixf@GCC_4.2.0 1:4.2.1 + __floatunsitf@GCC_4.4.0 1:4.4.0 + __frame_state_for@GLIBC_2.0 1:4.1.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __getf2@GCC_4.4.0 1:4.4.0 + __gttf2@GCC_4.4.0 1:4.4.0 + __letf2@GCC_4.4.0 1:4.4.0 + __lshrdi3@GCC_3.0 1:4.1.1 + __lttf2@GCC_4.4.0 1:4.4.0 + __moddi3@GLIBC_2.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __muldi3@GCC_3.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_4.4.0 1:4.4.0 + __multf3@GCC_4.4.0 1:4.4.0 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __mulxc3@GCC_4.0.0 1:4.1.1 + __negdi2@GCC_3.0 1:4.1.1 + __negtf2@GCC_4.4.0 1:4.4.0 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __netf2@GCC_4.4.0 1:4.4.0 + __paritydi2@GCC_3.4 1:4.1.1 + __paritysi2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountsi2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_4.4.0 1:4.4.0 + __powixf2@GCC_4.0.0 1:4.1.1 + __register_frame@GLIBC_2.0 1:4.1.1 + __register_frame_info@GLIBC_2.0 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GLIBC_2.0 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GLIBC_2.0 1:4.1.1 + __subtf3@GCC_4.4.0 1:4.4.0 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __trunctfdf2@GCC_4.4.0 1:4.4.0 + __trunctfsf2@GCC_4.4.0 1:4.4.0 + __trunctfxf2@GCC_4.4.0 1:4.4.0 + __ucmpdi2@GCC_3.0 1:4.1.1 + __udivdi3@GLIBC_2.0 1:4.1.1 + __udivmoddi4@GCC_3.0 1:4.1.1 + __umoddi3@GLIBC_2.0 1:4.1.1 + __unordtf2@GCC_4.4.0 1:4.4.0 --- gcc-4.5-4.5.2.orig/debian/libmudflapMF.postinst +++ gcc-4.5-4.5.2/debian/libmudflapMF.postinst @@ -0,0 +1,12 @@ +#! /bin/sh + +set -e + +case "$1" in configure) + if [ -d /usr/share/doc/libmudflap@MF@ ] && [ ! -h /usr/share/doc/libmudflap@MF@ ]; then + rm -rf /usr/share/doc/libmudflap@MF@ + ln -s gcc-@BV@-base /usr/share/doc/libmudflap@MF@ + fi +esac + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.mips +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.mips @@ -0,0 +1,7 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" + __gxx_personality_v0@CXXABI_1.3 4.1.1 +#include "libstdc++6.symbols.excprop" +#include "libstdc++6.symbols.glibcxxmath" + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0 --- gcc-4.5-4.5.2.orig/debian/lib64gfortran3.symbols.s390 +++ gcc-4.5-4.5.2/debian/lib64gfortran3.symbols.s390 @@ -0,0 +1,5 @@ +libgfortran.so.3 lib64gfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.16.powerpc" +#include "libgfortran3.symbols.16.powerpc64" +#include "libgfortran3.symbols.64" --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.hppa +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.hppa @@ -0,0 +1,8 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" + __gxx_personality_v0@CXXABI_1.3 4.1.1 +#include "libstdc++6.symbols.excprop" +# removed, see PR libstdc++/39491 __signbitl@GLIBCXX_3.4 4.2.1 +#include "libstdc++6.symbols.glibcxxmath" + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.kfreebsd-i386 +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.kfreebsd-i386 @@ -0,0 +1,6 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" +#include "libstdc++6.symbols.excprop" + __gxx_personality_v0@CXXABI_1.3 4.1.1 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.arm +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.arm @@ -0,0 +1,6 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" + __gxx_personality_sj0@CXXABI_1.3 4.1.1 +#include "libstdc++6.symbols.glibcxxmath" + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0 --- gcc-4.5-4.5.2.orig/debian/copyright +++ gcc-4.5-4.5.2/debian/copyright @@ -0,0 +1,338 @@ +This is the Debian GNU/Linux prepackaged version of the GNU compiler +collection, containing Ada, C, C++, Fortran 95, Java, Objective-C, +Objective-C++, and Treelang compilers, documentation, and support +libraries. In addition, Debian provides the gdc compiler, either in +the same source package, or built from a separate same source package. +Packaging is done by the Debian GCC Maintainers +, with sources obtained from: + + ftp://gcc.gnu.org/pub/gcc/releases/ (for full releases) + svn://gcc.gnu.org/svn/gcc/ (for prereleases) + http://bitbucket.org/goshawk/gdc (for D) + +The current gcc-4.5 source package is taken from the SVN gcc-4_5-branch. + +Changes: See changelog.Debian.gz + +Debian splits the GNU Compiler Collection into packages for each language, +library, and documentation as follows: + +Language Compiler package Library package Documentation +--------------------------------------------------------------------------- +Ada gnat-4.5 libgnat-4.5 gnat-4.5-doc +C gcc-4.5 gcc-4.5-doc +C++ g++-4.5 libstdc++6 libstdc++6-4.5-doc +D gdc-4.5 +Fortran 95 gfortran-4.5 libgfortran3 gfortran-4.5-doc +Java gcj-4.5 libgcj10 libgcj-doc +Objective C gobjc-4.5 libobjc2 +Objective C++ gobjc++-4.5 + +For some language run-time libraries, Debian provides source files, +development files, debugging symbols and libraries containing position- +independent code in separate packages: + +Language Sources Development Debugging Position-Independent +------------------------------------------------------------------------------ +C++ libstdc++6-4.5-dbg libstdc++6-4.5-pic +D libphobos-4.5-dev +Java libgcj10-src libgcj10-dev libgcj10-dbg + +Additional packages include: + +All languages: +libgcc1, libgcc2, libgcc4 GCC intrinsics (platform-dependent) +gcc-4.5-base Base files common to all compilers +gcc-4.5-soft-float Software floating point (ARM only) +gcc-4.5-source The sources with patches + +Ada: +libgnatvsn-dev, libgnatvsn4.5 GNAT version library +libgnatprj-dev, libgnatprj4.5 GNAT Project Manager library + +C: +cpp-4.5, cpp-4.5-doc GNU C Preprocessor +libmudflap0-dev, libmudflap0 Library for instrumenting pointers +libssp0-dev, libssp0 GCC stack smashing protection library +fixincludes Fix non-ANSI header files +protoize Create/remove ANSI prototypes from C code + +Java: +gij The Java bytecode interpreter and VM +libgcj-common Common files for the Java run-time +libgcj10-awt The Abstract Windowing Toolkit +libgcj10-jar Java ARchive for the Java run-time + +C, C++ and Fortran 95: +libgomp1-dev, libgomp1 GCC OpenMP (GOMP) support library + +Biarch support: On some 64-bit platforms which can also run 32-bit code, +Debian provides additional packages containing 32-bit versions of some +libraries. These packages have names beginning with 'lib32' instead of +'lib', for example lib32stdc++6. Similarly, on some 32-bit platforms which +can also run 64-bit code, Debian provides additional packages with names +beginning with 'lib64' instead of 'lib'. These packages contain 64-bit +versions of the libraries. (At this time, not all platforms and not all +libraries support biarch.) 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See the GNU General Public License +for more details. + +Files that have exception clauses are licensed under the terms of the +GNU General Public License; either version 3, or (at your option) any +later version. + +On Debian GNU/Linux systems, the complete text of the GNU General +Public License is in `/usr/share/common-licenses/GPL', version 3 of this +license in `/usr/share/common-licenses/GPL-3'. + +The following runtime libraries are licensed under the terms of the +GNU General Public License (v3 or later) with version 3.1 of the GCC +Runtime Library Exception (included in this file): + + - libgcc (libgcc/, gcc/libgcc2.[ch], gcc/unwind*, gcc/gthr*, + gcc/coretypes.h, gcc/crtstuff.c, gcc/defaults.h, gcc/dwarf2.h, + gcc/emults.c, gcc/gbl-ctors.h, gcc/gcov-io.h, gcc/libgcov.c, + gcc/tsystem.h, gcc/typeclass.h). + - libdecnumber + - libgomp + - libssp + - libstdc++-v3 + - libobjc + - libmudflap + - libgfortran + - The libgnat-4.5 Ada support library and libgnatvsn library. + - Various config files in gcc/config/ used in runtime libraries. + +In contrast, libgnatprj is licensed under the terms of the pure GNU +General Public License. + +The libgcj library is licensed under the terms of the GNU General +Public License, with a special exception: + + Linking this library statically or dynamically with other modules + is making a combined work based on this library. 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No Weakening of GCC Copyleft. + +The availability of this Exception does not imply any general +presumption that third-party software is unaffected by the copyleft +requirements of the license of GCC. + + +D: +gdc-4.5 GNU D Compiler +libphobos-4.5-dev D standard runtime library + +The D source package is made up of the following components. + +The D front-end for GCC: + - d/* + +Copyright (C) 2004-2007 David Friedman +Modified by Vincenzo Ampolo, Michael Parrot, Iain Buclaw, (C) 2009, 2010 + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +On Debian GNU/Linux systems, the complete text of the GNU General +Public License is in `/usr/share/common-licenses/GPL', version 2 of this +license in `/usr/share/common-licenses/GPL-2'. + + +The DMD Compiler implementation of the D programming language: + - d/dmd/* + +Copyright (c) 1999-2010 by Digital Mars +All Rights Reserved +written by Walter Bright +http://www.digitalmars.com +License for redistribution is by either the Artistic License or +the GNU General Public License (v1). + +On Debian GNU/Linux systems, the complete text of the GNU General +Public License is in `/usr/share/common-licenses/GPL', the Artistic +license in `/usr/share/common-licenses/Artistic'. + + +The Zlib data compression library: + - d/phobos/etc/c/zlib/* + + (C) 1995-2004 Jean-loup Gailly and Mark Adler + + This software is provided 'as-is', without any express or implied + warranty. In no event will the authors be held liable for any damages + arising from the use of this software. + + Permission is granted to anyone to use this software for any purpose, + including commercial applications, and to alter it and redistribute it + freely, subject to the following restrictions: + + 1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + 2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + 3. This notice may not be removed or altered from any source distribution. + + +The Phobos standard runtime library: + - d/phobos/* + +Unless otherwise marked within the file, each file in the source +is under the following licenses: + +Copyright (C) 2004-2005 by Digital Mars, www.digitalmars.com +Written by Walter Bright + +This software is provided 'as-is', without any express or implied +warranty. In no event will the authors be held liable for any damages +arising from the use of this software. + +Permission is granted to anyone to use this software for any purpose, +including commercial applications, and to alter it and redistribute it +freely, in both source and binary form, subject to the following +restrictions: + + o The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + o Altered source versions must be plainly marked as such, and must not + be misrepresented as being the original software. + o This notice may not be removed or altered from any source + distribution. + +By plainly marking modifications, something along the lines of adding to each +file that has been changed a "Modified by Foo Bar" line +underneath the "Written by" line would be adequate. + --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.mipsel +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.mipsel @@ -0,0 +1,2 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" --- gcc-4.5-4.5.2.orig/debian/dh_rmemptydirs +++ gcc-4.5-4.5.2/debian/dh_rmemptydirs @@ -0,0 +1,10 @@ +#! /bin/sh -e + +pkg=`echo $1 | sed 's/^-p//'` + +: # remove empty directories, when all components are in place +for d in `find debian/$pkg -depth -type d -empty 2> /dev/null`; do \ + while rmdir $d 2> /dev/null; do d=`dirname $d`; done; \ +done + +exit 0 --- gcc-4.5-4.5.2.orig/debian/cpp-BV-doc.doc-base.cpp +++ gcc-4.5-4.5.2/debian/cpp-BV-doc.doc-base.cpp @@ -0,0 +1,16 @@ +Document: cpp-@BV@ +Title: The GNU C preprocessor +Author: Various +Abstract: The C preprocessor is a "macro processor" that is used automatically + by the C compiler to transform your program before actual compilation. + It is called a macro processor because it allows you to define "macros", + which are brief abbreviations for longer constructs. +Section: Programming + +Format: html +Index: /usr/share/doc/gcc-@BV@-base/cpp.html +Files: /usr/share/doc/gcc-@BV@-base/cpp.html + +Format: info +Index: /usr/share/info/cpp-@BV@.info.gz +Files: /usr/share/info/cpp-@BV@* --- gcc-4.5-4.5.2.orig/debian/lib64stdc++6.symbols.i386 +++ gcc-4.5-4.5.2/debian/lib64stdc++6.symbols.i386 @@ -0,0 +1,31 @@ +libstdc++.so.6 lib64stdc++6 #MINVER# +#include "libstdc++6.symbols.64bit" +#include "libstdc++6.symbols.excprop" + _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# acosl@GLIBCXX_3.4.3 4.1.1 +#DEPRECATED: 4.2.2-4# asinl@GLIBCXX_3.4.3 4.1.1 +#DEPRECATED: 4.2.2-4# atan2l@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# atanl@GLIBCXX_3.4.3 4.1.1 +#DEPRECATED: 4.2.2-4# ceill@GLIBCXX_3.4.3 4.1.1 +#DEPRECATED: 4.2.2-4# coshl@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# cosl@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# expl@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# floorl@GLIBCXX_3.4.3 4.1.1 +#DEPRECATED: 4.2.2-4# fmodl@GLIBCXX_3.4.3 4.1.1 +#DEPRECATED: 4.2.2-4# frexpl@GLIBCXX_3.4.3 4.1.1 +#DEPRECATED: 4.2.2-4# hypotl@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# ldexpf@GLIBCXX_3.4.3 4.1.1 +#DEPRECATED: 4.2.2-4# ldexpl@GLIBCXX_3.4.3 4.1.1 +#DEPRECATED: 4.2.2-4# log10l@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# logl@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# modfl@GLIBCXX_3.4.3 4.1.1 +#DEPRECATED: 4.2.2-4# powf@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# powl@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# sinhl@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# sinl@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# sqrtl@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# tanhl@GLIBCXX_3.4 4.1.1 +#DEPRECATED: 4.2.2-4# tanl@GLIBCXX_3.4 4.1.1 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.s390 +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.s390 @@ -0,0 +1,547 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.common" +#include "libstdc++6.symbols.excprop" + _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEm@GLIBCXX_3.4.2 4.1.1 + _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEm@GLIBCXX_3.4.2 4.1.1 + _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1 + _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1 + _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1 + _ZN9__gnu_cxx6__poolILb1EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1 + _ZN9__gnu_cxx9free_list6_M_getEm@GLIBCXX_3.4.4 4.1.1 + _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2 + _ZNK10__cxxabiv117__class_type_info12__do_dyncastEiNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE@CXXABI_1.3 4.1.1 + _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcEiPKvPKS0_S2_@CXXABI_1.3 4.1.1 + _ZNK10__cxxabiv120__si_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1 + _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1 + _ZNK10__cxxabiv121__vmi_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1 + _ZNK10__cxxabiv121__vmi_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwmm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofERKS2_m@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwmm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofERKS2_m@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwmm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS2_m@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwmm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS2_m@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE4copyEPwmm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwmm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE4findERKS2_m@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE4findEwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwmm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE5rfindERKS2_m@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE6substrEmm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKw@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKwm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_mm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE8_M_checkEmPKc@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEE8_M_limitEmm@GLIBCXX_3.4 4.1.1 + _ZNKSbIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4 4.1.1 + _ZNKSs12find_last_ofEPKcm@GLIBCXX_3.4 4.1.1 + _ZNKSs12find_last_ofEPKcmm@GLIBCXX_3.4 4.1.1 + _ZNKSs12find_last_ofERKSsm@GLIBCXX_3.4 4.1.1 + _ZNKSs12find_last_ofEcm@GLIBCXX_3.4 4.1.1 + _ZNKSs13find_first_ofEPKcm@GLIBCXX_3.4 4.1.1 + _ZNKSs13find_first_ofEPKcmm@GLIBCXX_3.4 4.1.1 + _ZNKSs13find_first_ofERKSsm@GLIBCXX_3.4 4.1.1 + _ZNKSs13find_first_ofEcm@GLIBCXX_3.4 4.1.1 + _ZNKSs15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1 + _ZNKSs15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1 + _ZNKSs16find_last_not_ofEPKcm@GLIBCXX_3.4 4.1.1 + _ZNKSs16find_last_not_ofEPKcmm@GLIBCXX_3.4 4.1.1 + _ZNKSs16find_last_not_ofERKSsm@GLIBCXX_3.4 4.1.1 + _ZNKSs16find_last_not_ofEcm@GLIBCXX_3.4 4.1.1 + _ZNKSs17find_first_not_ofEPKcm@GLIBCXX_3.4 4.1.1 + _ZNKSs17find_first_not_ofEPKcmm@GLIBCXX_3.4 4.1.1 + _ZNKSs17find_first_not_ofERKSsm@GLIBCXX_3.4 4.1.1 + _ZNKSs17find_first_not_ofEcm@GLIBCXX_3.4 4.1.1 + _ZNKSs2atEm@GLIBCXX_3.4 4.1.1 + _ZNKSs4copyEPcmm@GLIBCXX_3.4 4.1.1 + _ZNKSs4findEPKcm@GLIBCXX_3.4 4.1.1 + _ZNKSs4findEPKcmm@GLIBCXX_3.4 4.1.1 + _ZNKSs4findERKSsm@GLIBCXX_3.4 4.1.1 + _ZNKSs4findEcm@GLIBCXX_3.4 4.1.1 + _ZNKSs5rfindEPKcm@GLIBCXX_3.4 4.1.1 + _ZNKSs5rfindEPKcmm@GLIBCXX_3.4 4.1.1 + _ZNKSs5rfindERKSsm@GLIBCXX_3.4 4.1.1 + _ZNKSs5rfindEcm@GLIBCXX_3.4 4.1.1 + _ZNKSs6substrEmm@GLIBCXX_3.4 4.1.1 + _ZNKSs7compareEmmPKc@GLIBCXX_3.4 4.1.1 + _ZNKSs7compareEmmPKcm@GLIBCXX_3.4 4.1.1 + _ZNKSs7compareEmmRKSs@GLIBCXX_3.4 4.1.1 + _ZNKSs7compareEmmRKSsmm@GLIBCXX_3.4 4.1.1 + _ZNKSs8_M_checkEmPKc@GLIBCXX_3.4 4.1.1 + _ZNKSs8_M_limitEmm@GLIBCXX_3.4 4.1.1 + _ZNKSsixEm@GLIBCXX_3.4 4.1.1 + _ZNKSt11__timepunctIcE6_M_putEPcmPKcPK2tm@GLIBCXX_3.4 4.1.1 + _ZNKSt11__timepunctIwE6_M_putEPwmPKwPK2tm@GLIBCXX_3.4 4.1.1 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt7codecvtIcc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1 + _ZNKSt7codecvtIwc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1 + _ZNKSt7collateIcE12_M_transformEPcPKcm@GLIBCXX_3.4 4.1.1 + _ZNKSt7collateIwE12_M_transformEPwPKwm@GLIBCXX_3.4 4.1.1 + _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE12_M_group_intEPKcmcRSt8ios_basePcS9_Ri@GLIBCXX_3.4 4.1.1 + _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE14_M_group_floatEPKcmcS6_PcS7_Ri@GLIBCXX_3.4 4.1.1 + _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6_M_padEciRSt8ios_basePcPKcRi@GLIBCXX_3.4 4.1.1 + _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE12_M_group_intEPKcmwRSt8ios_basePwS9_Ri@GLIBCXX_3.4 4.1.1 + _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE14_M_group_floatEPKcmwPKwPwS9_Ri@GLIBCXX_3.4 4.1.1 + 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_ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1 + _ZTv0_n12_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1 + _Znam@GLIBCXX_3.4 4.1.1 + _ZnamRKSt9nothrow_t@GLIBCXX_3.4 4.1.1 + _Znwm@GLIBCXX_3.4 4.1.1 + _ZnwmRKSt9nothrow_t@GLIBCXX_3.4 4.1.1 + __gxx_personality_v0@CXXABI_1.3 4.1.1 +#include "libstdc++6.symbols.glibcxxmath" +#include "libstdc++6.symbols.ldbl.32bit.s390" + _ZNSt12__basic_fileIcEC1EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1 + _ZNSt12__basic_fileIcEC2EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1 --- gcc-4.5-4.5.2.orig/debian/libgcj-common.preinst +++ gcc-4.5-4.5.2/debian/libgcj-common.preinst @@ -0,0 +1,12 @@ +#! /bin/sh -e + +case "$1" in + upgrade|install) + if [ -n "$2" ] && [ -h /usr/share/doc/libgcj-common ] \ + && dpkg --compare-versions "$2" lt 1:4.0.2-10 + then + rm -f /usr/share/doc/libgcj-common + fi +esac + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/jdb.sh +++ gcc-4.5-4.5.2/debian/jdb.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +# Placeholder script to fake a +# JDK compatible JAVA_HOME directory. + +echo >&2 "This script is only a placeholder." +echo >&2 "Some programs need a JDK rather than only a JRE to work." +echo >&2 "They test for this tool to detect a JDK installation, but" +echo >&2 "don't really need its functionality to work correctly." --- gcc-4.5-4.5.2.orig/debian/rules.defs +++ gcc-4.5-4.5.2/debian/rules.defs @@ -0,0 +1,1270 @@ +# -*- makefile -*- +# definitions used in more than one Makefile / rules file + +# common vars +SHELL = /bin/bash -e # brace expansion used in rules file +PWD := $(shell pwd) +srcdir = $(PWD)/src +builddir = $(PWD)/build +stampdir = stamps + +distribution := $(shell lsb_release -is) +distrelease := $(shell lsb_release -cs) + +# On non official archives, "lsb_release -cs" default to "n/a". Assume +# sid in that case +ifeq ($(distrelease),n/a) +distrelease := sid +endif + +on_buildd := $(shell [ -f /CurrentlyBuilding -o "$$LOGNAME" = buildd ] && echo yes) + +# creates {srcdir,builddir}_{hppa64,ia6432,spu} +$(foreach x,srcdir builddir,$(foreach target,hppa64 ia6432 spu neon,$(eval \ + $(x)_$(target) := $($(x))-$(target)))) + +# for architecture dependent variables and changelog vars +vafilt = $(subst $(2)=,,$(filter $(2)=%,$(1))) +# for rules.sonames +vafilt_defined = 1 + +DPKG_VARS := $(shell dpkg-architecture) +DEB_BUILD_GNU_TYPE ?= $(call vafilt,$(DPKG_VARS),DEB_BUILD_GNU_TYPE) +DEB_HOST_ARCH ?= $(call vafilt,$(DPKG_VARS),DEB_HOST_ARCH) +DEB_HOST_GNU_CPU ?= $(call vafilt,$(DPKG_VARS),DEB_HOST_GNU_CPU) +DEB_HOST_GNU_SYSTEM ?= $(call vafilt,$(DPKG_VARS),DEB_HOST_GNU_SYSTEM) +DEB_HOST_GNU_TYPE ?= $(call vafilt,$(DPKG_VARS),DEB_HOST_GNU_TYPE) +DEB_HOST_MULTIARCH ?= $(call vafilt,$(DPKG_VARS),DEB_HOST_MULTIARCH) + +CHANGELOG_VARS := $(shell dpkg-parsechangelog | \ + sed -n 's/ /_/g;/^[^_]/s/^\([^:]*\):_\(.*\)/\1=\2/p') + +# the name of the source package +PKGSOURCE := $(call vafilt,$(CHANGELOG_VARS),Source) +# those are required here too +SOURCE_VERSION := $(call vafilt,$(CHANGELOG_VARS),Version) +DEB_VERSION := $(strip $(shell echo $(SOURCE_VERSION) | \ + sed -e 's/.*://' -e 's/ds[0-9]*//')) +# epoch used for gcc versions up to 3.3.x, now used for some remaining +# libraries: libgcc1, libobjc1 +EPOCH := 1 +DEB_EVERSION := $(EPOCH):$(DEB_VERSION) +BASE_VERSION := $(shell echo $(DEB_VERSION) | sed -e 's/\([1-9]\.[0-9]\).*-.*/\1/') + +# push glibc stack traces into stderr +export LIBC_FATAL_STDERR_=1 + +# --------------------------------------------------------------------------- +# set target +# - GNU triplet via DEB_TARGET_GNU_TYPE +# - Debian arch in debian/target +# - Debian arch via DEB_GCC_TARGET or GCC_TARGET +# +# alias +ifdef GCC_TARGET + DEB_GCC_TARGET := $(GCC_TARGET) +endif +ifdef DEB_TARGET_GNU_TYPE + TARGET_VARS := $(shell dpkg-architecture -f -t$(DEB_TARGET_GNU_TYPE) 2>/dev/null) +else + # allow debian/target to be used instead of DEB_GCC_TARGET - this was requested + # by toolchain-source maintainer + DEBIAN_TARGET_FILE := $(strip $(if $(wildcard debian/target),$(shell cat debian/target 2>/dev/null))) + ifndef DEB_TARGET_ARCH + ifneq (,$(DEBIAN_TARGET_FILE)) + DEB_TARGET_ARCH := $(DEBIAN_TARGET_FILE) + else + ifdef DEB_GCC_TARGET + DEB_TARGET_ARCH := $(DEB_GCC_TARGET) + else + DEB_TARGET_ARCH := $(DEB_HOST_ARCH) + endif + endif + endif + TARGET_VARS := $(shell dpkg-architecture -f -a$(DEB_TARGET_ARCH) 2>/dev/null) +endif + +DEB_TARGET_ARCH ?= $(call vafilt,$(TARGET_VARS),DEB_HOST_ARCH) +DEB_TARGET_ARCH_OS ?= $(call vafilt,$(TARGET_VARS),DEB_HOST_ARCH_OS) +DEB_TARGET_ARCH_CPU ?= $(call vafilt,$(TARGET_VARS),DEB_HOST_ARCH_CPU) +DEB_TARGET_GNU_CPU ?= $(call vafilt,$(TARGET_VARS),DEB_HOST_GNU_CPU) +DEB_TARGET_GNU_TYPE ?= $(call vafilt,$(TARGET_VARS),DEB_HOST_GNU_TYPE) +DEB_TARGET_GNU_SYSTEM ?= $(call vafilt,$(TARGET_VARS),DEB_HOST_GNU_SYSTEM) + +ifeq ($(DEB_TARGET_ARCH),) + $(error Invalid architecure.) +endif + +# including unversiond symlinks for binaries +#with_unversioned = yes + +# --------------------------------------------------------------------------- +# cross-compiler config +# - typical cross-compiler +# - reverse cross (built to run on the target) +# - full canadian +# - native +# +# build != host && host == target : reverse cross (REVERSE_CROSS == yes) +# build == host && host != target : typical cross (DEB_CROSS == yes) +# build != host && host != target : canadian (DEB_CROSS == yes) +# build == host && host == target : native +ifneq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE)) + ifneq ($(DEB_HOST_GNU_TYPE),$(DEB_TARGET_GNU_TYPE)) + DEB_CROSS = yes + else + REVERSE_CROSS = yes + endif +else + ifneq ($(DEB_HOST_GNU_TYPE),$(DEB_TARGET_GNU_TYPE)) + DEB_CROSS = yes + else + # first ones are squeeze+1 and maverick + ifeq (,$(filter $(distrelease),lenny etch squeeze sid dapper hardy jaunty karmic lucid)) + with_sysroot = / + endif + endif +endif + +# --------------------------------------------------------------------------- +# cross compiler support +ifeq ($(DEB_CROSS),yes) + # TARGET: Alias to DEB_TARGET_ARCH (Debian arch name) + # TP: Target Prefix. Used primarily as a prefix for cross tool + # names (e.g. powerpc-linux-gcc). + # TS: Target Suffix. Used primarily at the end of cross compiler + # package names (e.g. gcc-powerpc). + # LS: Library Suffix. Used primarily at the end of cross compiler + # library package names (e.g. libgcc-powerpc-cross). + DEB_TARGET_ALIAS ?= $(DEB_TARGET_GNU_TYPE) + TARGET := $(DEB_TARGET_ARCH) + TP := $(subst _,-,$(DEB_TARGET_GNU_TYPE))- + TS := -$(subst _,-,$(DEB_TARGET_ALIAS)) + LS := -$(subst _,-,$(DEB_TARGET_ARCH))-cross + + cross_bin_arch := -$(subst _,-,$(DEB_TARGET_ALIAS)) + cross_lib_arch := -$(subst _,-,$(DEB_TARGET_ARCH))-cross + cmd_prefix := $(DEB_TARGET_GNU_TYPE)- + + TARGET_ALIAS := $(DEB_TARGET_ALIAS) + + lib_binaries := indep_binaries + cross_shlibdeps = $(SET_CROSS_LIB_PATH) ARCH=$(DEB_TARGET_ARCH) MAKEFLAGS="CC=something" +else + TARGET_ALIAS := $(DEB_TARGET_GNU_TYPE) + + ifeq ($(TARGET_ALIAS),i386-gnu) + TARGET_ALIAS := i586-gnu + endif + + cmd_prefix := + + #ifeq ($(TARGET_ALIAS),i486-linux-gnu) + # TARGET_ALIAS := i686-linux-gnu + #endif + + TARGET_ALIAS := $(subst i386,i486,$(TARGET_ALIAS)) + + # configure as linux-gnu, not linux + #ifeq ($(findstring linux,$(TARGET_ALIAS))/$(findstring linux-gnu,$(TARGET_ALIAS)),linux/) + # TARGET_ALIAS := $(TARGET_ALIAS)-gnu + #endif + + # configure as linux, not linux-gnu + #TARGET_ALIAS := $(subst linux-gnu,linux,$(TARGET_ALIAS)) + + lib_binaries := arch_binaries + cross_shlibdeps := +endif + +printarch: + @echo DEB_TARGET_ARCH: $(DEB_TARGET_ARCH) + @echo DEB_TARGET_ARCH_OS: $(DEB_TARGET_ARCH_OS) + @echo DEB_TARGET_ARCH_CPU: $(DEB_TARGET_ARCH_CPU) + @echo DEB_TARGET_GNU_SYSTEM: $(DEB_TARGET_GNU_SYSTEM) + @echo TARGET_ALIAS: $(TARGET_ALIAS) + @echo TP: $(TP) + @echo TS: $(TS) + +# ------------------------------------------------------------------- +# bootstrap options +ifdef WITH_BOOTSTRAP + # "yes" is the default and causes a 3-stage bootstrap. + # "off" runs a complete build with --disable-bootstrap + # "no" means to just build the first stage, and not create the stage1 + # directory. + # "lean" means a lean 3-stage bootstrap, i.e. delete each stage when no + # longer needed. + with_bootstrap = $(WITH_BOOTSTRAP) +endif +ifneq ($(findstring nostrap, $(DEB_BUILD_OPTIONS)),) + with_bootstrap := off +endif + +# ------------------------------------------------------------------- +# stage options +ifdef DEB_STAGE + with_cdev := yes + separate_lang := yes + # "stage1" is minimal compiler with static libgcc + # "stage2" is minimal compiler with shared libgcc + ifeq ($(DEB_STAGE),stage1) + with_shared_libgcc := no + endif + ifeq ($(DEB_STAGE),stage2) + with_libgcc := yes + with_shared_libgcc := yes + endif +endif + +ifeq ($(BACKPORT),true) + with_dev := no + with_source := yes + with_base_only := yes +endif + +# ------------------------------------------------------------------- +# sysroot options +ifdef WITH_SYSROOT + with_sysroot = $(WITH_SYSROOT) +endif +ifdef WITH_BUILD_SYSROOT + with_build_sysroot = $(WITH_BUILD_SYSROOT) +endif + +# ------------------------------------------------------------------- +# for components configuration + +COMMA = , +SPACE = $(EMPTY) $(EMPTY) + +# lang= overwrites all of nolang=, overwrites all of WITHOUT_LANG + +DEB_LANG_OPT := $(filter lang=%,$(DEB_BUILD_OPTIONS)) +DEB_LANG := $(strip $(subst $(COMMA), ,$(patsubst lang=%,%,$(DEB_LANG_OPT)))) +DEB_NOLANG_OPT := $(filter nolang=%,$(DEB_BUILD_OPTIONS)) +DEB_NOLANG := $(strip $(subst $(COMMA), ,$(patsubst nolang=%,%,$(DEB_NOLANG_OPT)))) +lfilt = $(strip $(if $(DEB_LANG), \ + $(if $(filter $(1) $(2),$(DEB_LANG)),yes),$(3))) +nlfilt = $(strip $(if $(DEB_NOLANG), \ + $(if $(filter $(1) $(2),$(DEB_NOLANG)),disabled by $(DEB_NOLANG_OPT),$(3)))) +wlfilt = $(strip $(if $(filter $(1) $(2), $(subst $(COMMA), ,$(WITHOUT_LANG))), \ + disabled by WITHOUT_LANG=$(WITHOUT_LANG),$(3))) +envfilt = $(strip $(or $(call lfilt,$(1),$(2)),$(call nlfilt,$(1),$(3)),$(call wlfilt,$(1),$(3)),$(4))) + +# ------------------------------------------------------------------- +# architecture specific config + +# FIXME: libjava is not ported for thumb, this hack only works for +# separate gcj builds +ifeq (,$(findstring gcj,$(PKGSOURCE))) + ifeq ($(distribution),Ubuntu) + with_arm_thumb := yes + endif + ifeq ($(DEB_TARGET_ARCH),armhf) + with_arm_thumb := yes + endif +endif + +# build using fsf or linaro +ifeq ($(distribution),Ubuntu) + ifeq (,$(findstring gnat, $(PKGSOURCE))) + ifneq (,$(findstring $(DEB_TARGET_ARCH),amd64 armel armhf i386 powerpc)) + with_linaro_branch = yes + endif + endif +endif +ifeq ($(DEB_TARGET_ARCH),armhf) + with_linaro_branch := yes +endif + +# check if we're building for armel or armhf +ifeq ($(DEB_TARGET_ARCH),armhf) + float_abi := hard +else ifneq (,$(filter $(DEB_TARGET_ARCH), arm armel)) + float_abi := softfp +endif + +# ------------------------------------------------------------------- +# basic config + +# common things --------------- +# build common packages, where package names don't differ in different +# gcc versions (fixincludes, libgcj-common) ... +with_common_pkgs := yes +# ... and some libraries, which do not change (libgcc1, libmudflap, libssp0). +with_common_libs := yes +# XXX: should with_common_libs be "yes" only if this is the default compiler +# version on the targeted arch? + +# is this a multiarch-enabled build? +ifeq (,$(filter $(distrelease),lenny etch squeeze wheezy sid dapper hardy jaunty karmic lucid maverick)) + with_multiarch_lib := yes +endif + +ifeq (,$(filter $(distrelease),lenny etch squeeze wheezy sid dapper hardy jaunty karmic lucid maverick)) + multiarch_stage1 := yes +endif + +ifneq ($(DEB_STAGE),stage1) + # build a -base package. + ifneq ($(DEB_CROSS),yes) + with_gccbase := yes + else + with_gccxbase := yes + endif +endif + +# build dev packages. +with_dev := yes + +with_cpp := yes + +# set lang when built from a different source package. +separate_lang := no + +ifneq ($(PKGSOURCE),gcc-snapshot) + # --program-suffix=-$(BASE_VERSION) + versioned_packages := yes + ifneq ($(DEB_CROSS),yes) + with_common_gcclibdir := yes + endif +else + # for control.in + gcc_snapshot := yes +endif + +#no_dummy_cpus := ia64 i386 hppa s390 sparc +#ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(no_dummy_cpus))) +# with_base_only := no +# with_common_libs := yes +# with_common_pkgs := yes +#else +# with_base_only := yes +# with_common_libs := no +# with_common_pkgs := no +# with_dev := no +#endif + +# Debian has both 4.5 and 4.6 in unstable for most archs +ifeq ($(distribution),Debian) + ifeq (,$(filter $(distrelease), lenny squeeze)) + ifeq (,$(filter $(DEB_TARGET_ARCH),alpha avr32 m68k)) + with_common_libs := no + with_common_pkgs := no + endif + endif +endif + +ifeq ($(versioned_packages),yes) + pkg_ver := -$(BASE_VERSION) + PV := $(pkg_ver) +endif + +# ------------------------------------------------------------------- +# configure languages + +# C --------------------------- +enabled_languages := c + +# Build all packages needed for C development +ifneq ($(with_base_only),yes) + ifeq ($(with_dev),yes) + with_cdev := yes + endif +endif + +ifndef DEB_STAGE +# Ada -------------------- +ada_no_cpus := m32r m68k sh3 sh3eb sh4 sh4eb +ada_no_systems := gnu knetbsd-gnu +ada_no_cross := yes +ada_no_snap := no + +ifeq ($(with_dev),yes) + ifneq ($(separate_lang),yes) + with_ada := yes + endif +endif +ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU),$(ada_no_cpus))) + with_ada := disabled for cpu $(DEB_TARGET_ARCH_CPU) +endif +ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(ada_no_systems))) + with_ada := disabled for system $(DEB_TARGET_GNU_SYSTEM) +endif +ifeq ($(ada_no_cross)-$(DEB_CROSS),yes-yes) + with_ada := disabled for cross compiler package +endif +ifeq ($(ada_no_snap)-$(PKGSOURCE),yes-gcc-snapshot) + with_ada := disabled for snapshot build +endif +with_ada := $(call envfilt, ada, , , $(with_ada)) + +ifneq ($(PKGSOURCE),gcc-snapshot) + with_separate_gnat := yes +endif +ifeq ($(with_ada)-$(with_separate_gnat),yes-yes) + ifneq (,$(findstring gnat,$(PKGSOURCE))) + languages := c + separate_lang := yes + else + debian_extra_langs += ada + with_ada := built from separate source + with_libgnat := built from separate source + endif +endif + +ifeq ($(with_ada),yes) + enabled_languages += ada + with_libgnat := yes + # There are two exception handling mechanisms: ZCX (Zero-Cost + # eXceptions) and SJLJ (setjump/longjump), selected and supported by + # libgnat. Thus we build both versions of libgnat on architectures + # that support both (see ada-sjlj.diff). Most cpus support both + # mechanisms; here, we declare the few that support only one. + libgnat_zcx_only_cpus := + libgnat_sjlj_only_cpus := arm armel armhf + ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(libgnat_sjlj_only_cpus))) + with_gnat_zcx := no + else + with_gnat_zcx := yes + endif + ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(libgnat_zcx_only_cpus))) + with_gnat_sjlj := no + else + with_gnat_sjlj := yes + endif + ifeq ($(with_gnat_zcx)-$(with_gnat_sjlj),no-no) + # TODO: support cpus that do not support exceptions at all, + # perhaps by building a restricted runtime library? For now, flag + # this as a packaging error. + $(error this target supports neither ZCX nor SJLJ) + endif +endif + +# C++ ------------------------- +cxx_no_cpus := avr +ifneq ($(with_base_only),yes) + ifneq ($(separate_lang),yes) + with_cxx := yes + endif +endif +ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU),$(cxx_no_cpus))) + with_cxx := disabled for cpu $(DEB_TARGET_ARCH_CPU) +endif +with_cxx := $(call envfilt, c++, obj-c++ java, , $(with_cxx)) + +# Build all packages needed for C++ development +ifeq ($(with_cxx),yes) + ifeq ($(with_dev),yes) + with_cxxdev := yes + with_libcxxdbg := yes + endif + ifeq ($(with_common_pkgs),yes) + with_libcxx := yes + endif + + # debugging versions of libstdc++ + ifeq ($(with_cxxdev),yes) + with_debug := yes + debug_no_cpus := + ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU),$(debug_no_cpus))) + with_debug := disabled for cpu $(DEB_TARGET_GNU_CPU) + endif + endif + with_debug := $(call envfilt, debug, , , $(with_debug)) + + enabled_languages += c++ +endif + +# Java -------------------- +# - To build a standalone gcj package (with no corresponding gcc +# package): with_separate_libgcj=yes, with_standalone_gcj=yes +# - To build the java packages from the gcc source package: +# with_separate_libgcj=no, with_standalone_gcj=no +# - To build gcc and java from separate sources: +# with_separate_libgcj=yes, with_standalone_gcj=no + +java_no_cpus := # mips mipsel +java_no_systems := knetbsd-gnu +java_no_cross := yes + +ifneq ($(PKGSOURCE),gcc-snapshot) + with_separate_libgcj := yes +endif +with_standalone_gcj := no +with_separate_libgcj := yes + +ifneq ($(separate_lang),yes) + with_java := yes +endif + +# java converted for V3 C++ ABI for some archs +ifeq ($(with_base_only),yes) + with_java := no +endif +ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU),$(java_no_cpus))) + with_java := disabled for cpu $(DEB_TARGET_ARCH_CPU) +endif +ifneq (,$(filter $(DEB_TARGET_GNU_SYSTEM),$(java_no_systems))) + with_java := disabled for system $(DEB_TARGET_GNU_SYSTEM) +endif +ifeq ($(java_no_cross)-$(DEB_CROSS),yes-yes) + with_java := diasbled for cross compiler package +endif +with_java := $(call envfilt, java, , c++, $(with_java)) + +ifeq ($(with_java)-$(with_separate_libgcj),yes-yes) + ifneq (,$(findstring gcj, $(PKGSOURCE))) + languages := c c++ + separate_lang := yes + else + debian_extra_langs += java + with_java := built from separate source + with_gcj := built from separate source + with_libgcj := buit from separate source + endif +endif + +with_java_plugin := no + +ifeq ($(with_java),yes) + # use the same names as OpenJDK + java_cpu_map = armel=arm armhf=arm hppa=parisc i686=i386 i586=i386 i486=i386 mipsel=mips powerpc=ppc sh4=sh + java_cpu = $(patsubst $(DEB_TARGET_ARCH_CPU)=%,%, \ + $(filter $(DEB_TARGET_ARCH_CPU)=%,$(java_cpu_map))) + ifeq (,$(java_cpu)) + java_cpu = $(DEB_TARGET_ARCH_CPU) + endif + java_priority = 10$(subst .,,$(BASE_VERSION)) + + with_libgcj := yes + with_libgcjbc := no + + ifneq (,$(findstring gcj-4,$(PKGSOURCE))) + ifneq (,$(filter $(DEB_TARGET_ARCH), arm)) + with_gcj_base_only := yes + endif + endif + + ifeq ($(PKGSOURCE),gcc-snapshot) + with_ecj := yes + endif + + #ifneq (,$(filter $(DEB_TARGET_ARCH),hppa)) + # with_native_ecj := yes + #endif + + with_java_maintainer_mode := no + + # used as well in debian/rules.conf to determine the build deps + java_awt_peers = gtk # qt # xlib + + ifeq ($(with_common_libs),yes) + with_libgcj_doc := yes + endif + + # Build all packages needed for Java development (gcj, libgcj-dev) + ifeq ($(with_dev),yes) + with_javadev := yes + with_gcj := yes + endif + + with_java_alsa := yes + ifeq (,$(filter $(DEB_TARGET_GNU_SYSTEM),linux-gnu)) + with_java_alsa := no + endif + + enabled_languages += java +endif + +# D --------------------------- +d_no_cross := yes +d_no_snap := yes + +ifneq ($(PKGSOURCE),gcc-snapshot) + with_separate_gdc := yes +endif + +ifneq ($(separate_lang),yes) + with_d := yes +endif +ifeq ($(d_no_snap)-$(PKGSOURCE),yes-gcc-snapshot) + with_d := disabled for snapshot build +endif +with_d := not yet ported to GCC 4.4 + +ifeq ($(with_d)-$(with_separate_gdc),yes-yes) + ifneq (,$(findstring gdc,$(PKGSOURCE))) + languages := c c++ + separate_lang := yes + else + debian_extra_langs += d + with_d := built from separate source + endif +endif + +ifeq ($(with_base_only),yes) + with_d := no +endif + +ifeq ($(with_d),yes) + # no suffix for D 1.0 + libphobos_version := + # still experimental + #libphobos_version := 2 + + with_libphobos := yes + + libphobos_no_cpus := sparc + libphobos_no_systems := gnu + ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU),$(libphobos_no_cpus))) + with_libphobos := disabled for cpu $(DEB_TARGET_ARCH_CPU) + endif + ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(libphobos_no_systems))) + with_libphobos := disabled for system $(DEB_TARGET_GNU_SYSTEM) + endif + + enabled_languages += d +endif + +# Fortran 95 ------------------- +fortran_no_cross := yes +fortran_no_cross := no + +ifneq ($(with_base_only),yes) + ifneq ($(separate_lang),yes) + with_fortran := yes + endif +endif +ifeq ($(fortran_no_cross)-$(DEB_CROSS),yes-yes) + with_fortran := diasbled for cross compiler package +endif +with_fortran := $(call envfilt, fortran, , , $(with_fortran)) + +# Build all packages needed for Fortran development +ifeq ($(with_fortran),yes) + ifeq ($(with_dev),yes) + with_fdev := yes + endif + ifeq ($(with_common_libs),yes) + with_libgfortran := yes + endif + enabled_languages += fortran +endif + +# ObjC ------------------------ +objc_no_cross := no + +ifneq ($(with_base_only),yes) + ifneq ($(separate_lang),yes) + with_objc := yes + endif +endif +ifeq ($(objc_no_cross)-$(DEB_CROSS),yes-yes) + with_objc := diasbled for cross compiler package +endif +with_objc := $(call envfilt, objc, obj-c++, , $(with_objc)) + +ifeq ($(with_objc),yes) + # the ObjC runtime with garbage collection enabled needs the Boehm GC + with_objc_gc := yes + + # disable ObjC garbage collection library (needs libgc) + libgc_no_cpus := avr mips mipsel # alpha amd64 arm armel armhf hppa i386 ia64 m68k mips mipsel powerpc ppc64 s390 sparc + libgc_no_systems := knetbsd-gnu + ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU),$(libgc_no_cpus))) + with_objc_gc := disabled for cpu $(DEB_TARGET_ARCH_CPU) + endif + ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(libgc_no_systems))) + with_objc_gc := disabled for system $(DEB_TARGET_GNU_SYSTEM) + endif + + # Build all packages needed for Objective-C development + ifeq ($(with_dev),yes) + with_objcdev := yes + endif + # libobjc soname change in 4.6 + #ifeq ($(with_common_libs),yes) + with_libobjc := yes + #endif + + enabled_languages += objc +endif + +# ObjC++ ---------------------- +objcxx_no_cross := no + +ifneq ($(with_base_only),yes) + ifneq ($(separate_lang),yes) + with_objcxx := yes + endif +endif +ifeq ($(objcxx_no_cross)-$(DEB_CROSS),yes-yes) + with_objcxx := diasbled for cross compiler package +endif +with_objcxx := $(call envfilt, obj-c++, , c++ objc, $(with_objcxx)) + +ifeq ($(with_objcxx),yes) + enabled_languages += obj-c++ +endif + +# ------------------------------------------------------------------- +# other config + +# not built from the main source package +ifeq (,$(findstring gcc,$(PKGSOURCE))) + extra_package := yes +endif + +with_nls := yes +ifeq ($(PKGSOURCE),gcc-snapshot) + with_nls := no +endif +with_nls := $(call envfilt, nls, , , $(with_nls)) + +# powerpc nof libraries ----- +with_libnof := no + +ifneq (,$(findstring gcc-4,$(PKGSOURCE))) + with_source := yes +endif +with_source := $(call envfilt, source, , , $(with_source)) + +# ssp & libssp ------------------------- +with_ssp := yes +ssp_no_archs = alpha hppa ia64 m68k mips mipsel +ifneq (, $(filter $(DEB_TARGET_ARCH),$(ssp_no_archs) $(ssp_no_archs:%=uclibc-%))) + with_ssp := not available on $(DEB_TARGET_ARCH) +endif +with_ssp := $(call envfilt, ssp, , , $(with_ssp)) + +ifeq ($(with_ssp),yes) + ifneq ($(distribution),Debian) + ifneq (,$(findstring gcc-4, $(PKGSOURCE))) + with_ssp_default := yes + endif + endif +endif + +# mudflap ------------------- +with_mudflap := yes +with_mudflap := $(call envfilt, mudflap, , , $(with_mudflap)) + +# gomp -------------------- +with_gomp := yes +with_gomp := $(call envfilt, gomp, , , $(with_gomp)) + +# gold -------------------- +# armel with binutils 2.20.51 only +gold_archs = amd64 armel armhf i386 lpia powerpc ppc64 sparc +ifneq (,$(filter $(DEB_TARGET_ARCH),$(gold_archs))) + with_gold := yes +endif + +# plugins -------------------- +with_plugins := yes + +endif # ifndef DEB_STAGE + +# Don't include docs with GFDL invariant sections +GFDL_INVARIANT_FREE := yes +ifeq ($(distribution),Ubuntu) + GFDL_INVARIANT_FREE := no +endif + +# ------------------------------------------------------------------- +# non-extra config +ifeq ($(extra_package),yes) + ifeq ($(with_separate_libgcj)-$(with_standalone_gcj),yes-no) + # build stuff + with_mudflap := + + # package stuff + with_gccbase := no + with_cdev := no + with_cxx := no + with_cxxdev := no + endif +else + # libssp ------------------ + ifeq ($(with_ssp)-$(with_common_libs),yes-yes) + #ifneq ($(DEB_CROSS),yes) + with_libssp := $(if $(wildcard $(builddir)/gcc/auto-host.h), \ + $(shell if grep -qs '^\#define TARGET_LIBC_PROVIDES_SSP 1' $(builddir)/gcc/auto-host.h; then echo 'libc provides ssp'; else echo 'yes'; fi)) + #endif + endif + + # libmudflap -------------- + ifeq ($(with_mudflap)-$(with_common_libs),yes-yes) + with_libmudflap := yes + endif + + # libgomp ----------------- + ifeq ($(with_gomp)-$(with_common_libs),yes-yes) + #ifneq ($(DEB_CROSS),yes) + with_libgomp := yes + #endif + endif + + # fixincludes ------- + ifneq ($(DEB_CROSS),yes) + ifeq ($(with_common_pkgs),yes) + with_fixincl := yes + endif + endif + + # Shared libgcc -------------------- + ifeq ($(with_common_libs),yes) + with_libgcc := yes + with_shared_libgcc := yes + endif + + # libgcc-math -------------------- + with_libgmath := no + ifneq (,$(findstring i486,$(DEB_TARGET_ARCH))) + #with_libgccmath := yes + #with_lib64gmath := yes + #with_libgmathdev := yes + endif + ifeq ($(DEB_TARGET_ARCH),amd64) + #with_libgccmath := yes + #with_lib32gmath := yes + #with_libgmathdev := yes + endif + + # hppa64 build ---------------- + hppa64_no_snap := no + ifeq ($(DEB_TARGET_ARCH),hppa) + with_hppa64 := yes + endif + ifeq ($(hppa64_no_snap)-$(PKGSOURCE),yes-gcc-snapshot) + with_hppa64 := disabled for snapshot build + endif + with_hppa64 := $(call envfilt, hppa64, , , $(with_hppa64)) + + # ia6432 build ---------------- + ia6432_no_snap := no + ifeq ($(DEB_TARGET_ARCH),ia64) + ifneq ($(DEB_CROSS),yes) + with_ia6432 := yes + endif + endif + ifeq ($(ia6432_no_snap)-$(PKGSOURCE),yes-gcc-snapshot) + with_ia6432 := disabled for snapshot build + endif + with_ia6432 := disabled + with_ia6432 := $(call envfilt, ia6432, , , $(with_ia6432)) + + # spu build ------------------- + spu_no_snap := no + ifneq (,$(findstring $(DEB_TARGET_ARCH),powerpc ppc64)) + ifneq ($(DEB_CROSS),yes) + with_spu := yes + endif + endif + ifeq ($(spu_no_snap)-$(PKGSOURCE),yes-gcc-snapshot) + with_spu := disabled for snapshot build + endif + with_spu := $(call envfilt, spu, , , $(with_spu)) + + ifeq ($(with_spu),yes) + ifneq ($(PKGSOURCE),gcc-snapshot) + with_spucache := yes + with_spumea64 := yes + endif + endif + + # neon build ------------------- + # FIXME: build as a cross compiler to build on armv4 as well + ifneq (,$(findstring gcc-4, $(PKGSOURCE))) + ifeq ($(distribution),Ubuntu) +# neon_archs = armel armhf +# ifneq (, $(filter $(DEB_TARGET_ARCH),$(neon_archs))) +# with_neon = yes +# endif + endif + endif +endif + +# run testsuite --------------- +with_check := yes +# if you don't want to run the gcc testsuite, uncomment the next line +#with_check := disabled by hand +ifeq ($(with_base_only),yes) + with_check := no +endif +ifeq ($(DEB_CROSS),yes) + with_check := disabled for cross compiler package +endif +ifeq ($(REVERSE_CROSS),yes) + with_check := disabled for reverse cross build +endif +check_no_cpus := m68k +check_no_systems := gnu +ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU),$(check_no_cpus))) + with_check := disabled for cpu $(DEB_TARGET_ARCH_CPU) +endif +ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(check_no_systems))) + with_check := disabled for system $(DEB_TARGET_GNU_SYSTEM) +endif +ifeq ($(distribution)-$(DEB_HOST_ARCH),Ubuntu-hppa) + ifneq ($(PKGSOURCE),gcc-snapshot) + with_check := disabled, testsuite timeouts with expect + endif +endif +ifneq (,$(findstring gdc,$(PKGSOURCE))) + with_check := disabled for D +endif +with_check := $(call envfilt, check, , , $(with_check)) +ifdef WITHOUT_CHECK + with_check := disabled by environment +endif +ifneq ($(findstring nocheck, $(DEB_BUILD_OPTIONS)),) + with_check := disabled by DEB_BUILD_OPTIONS +endif + +# not a dependency on all archs, but if available, use it for the testsuite +ifneq (,$(wildcard /usr/bin/localedef)) + locale_data = generate +endif + +all_enabled_languages := $(enabled_languages) +languages_without_lang_opt := c++ objc obj-c++ + +debian_extra_langs := $(subst obj-c++,objcp,$(debian_extra_langs)) +export debian_extra_langs + +# multilib +ifeq (,$(filter $(distrelease),lenny etch squeeze sid dapper hardy jaunty karmic lucid)) + biarch_map := i686=x86_64 powerpc=powerpc64 sparc=sparc64 s390=s390x \ + x86_64=i686 powerpc64=powerpc mips=mips64 mipsel=mips64el +else + biarch_map := i486=x86_64 powerpc=powerpc64 sparc=sparc64 s390=s390x \ + x86_64=i486 powerpc64=powerpc mips=mips64 mipsel=mips64el +endif +biarch_cpu := $(strip $(patsubst $(DEB_TARGET_GNU_CPU)=%,%, \ + $(filter $(DEB_TARGET_GNU_CPU)=%,$(biarch_map)))) + +biarch64 := no +biarch32 := no +biarchn32 := no +flavours := +define gen_biarch + ifneq (yes,$$(call envfilt, biarch, , ,yes)) + biarch$1archs := + endif + ifneq (,$$(findstring /$$(DEB_TARGET_ARCH)/,$$(biarch$1archs))) + biarch$1 := yes + flavours += $1 + #biarch$1subdir = $$(biarch_cpu)-$$(DEB_TARGET_GNU_SYSTEM) + biarch$1subdir = $1 + ifeq ($$(with_libgcc),yes) + with_lib$1gcc := yes + endif + ifeq ($$(with_libcxx),yes) + with_lib$1cxx := yes + endif + ifeq ($$(with_libcxxdbg),yes) + with_lib$1cxxdbg := yes + endif + ifeq ($$(with_libobjc),yes) + with_lib$1objc := yes + endif + ifeq ($$(with_libgfortran),yes) + with_lib$1gfortran := yes + endif + ifeq ($$(with_libmudflap),yes) + with_lib$1mudflap := yes + endif + ifeq ($$(with_libssp),yes) + with_lib$1ssp := yes + endif + ifeq ($$(with_libgomp),yes) + with_lib$1gomp:= yes + endif + + biarch_multidir_names = libiberty libgcc + ifneq (,$$(findstring gcc-, $$(PKGSOURCE))) + biarch_multidir_names += libstdc++-v3 libobjc libgfortran libssp \ + libgomp libmudflap zlib + ifeq ($$(with_objc_gc),yes) + biarch_multidir_names += boehm-gc + endif + endif + ifeq ($(with_java),yes) + biarch_multidir_names += libffi + endif + export biarch_multidir_names + ifneq (,$$(findstring 32,$1)) + TARGET64_MACHINE := $$(strip $$(subst $$(DEB_TARGET_GNU_CPU),$$(biarch_cpu), \ + $$(TARGET_ALIAS))) + TARGET32_MACHINE := $$(TARGET_ALIAS) + else + TARGET64_MACHINE := $$(TARGET_ALIAS) + TARGET64_MACHINE := $$(strip $$(subst $$(DEB_TARGET_GNU_CPU),$$(biarch_cpu), \ + $$(TARGET_ALIAS))) + endif + export TARGET32_MACHINE + export TARGET64_MACHINE + endif +endef +biarch32archs := /amd64/ppc64/kfreebsd-amd64/ +biarch64archs := /i386/powerpc/sparc/s390/mips/mipsel/ +biarchn32archs := /mips/mipsel/ +$(foreach x,32 64 n32,$(eval $(call gen_biarch,$(x)))) + +ifneq (,$(filter yes,$(biarch32) $(biarch64) $(biarchn32))) + multilib := yes +endif + +multilib_archs = $(sort $(subst /, , $(biarch64archs) $(biarch32archs) $(biarchn32archs))) + +biarchsubdirs := \ + $(if $(filter yes,$(biarch64)),$(biarch64subdir),) \ + $(if $(filter yes,$(biarch32)),$(biarch32subdir),) \ + $(if $(filter yes,$(biarchn32)),$(biarchn32subdir),) +biarchsubdirs := {$(strip $(shell echo $(biarchsubdirs) | tr " " ","))} + +#ifeq ($(DEB_TARGET_ARCH),ia64) +# biarch32 := yes +#endif + +ifeq ($(PKGSOURCE),gcc-snapshot) + no_biarch_libs := yes +endif +ifdef DEB_CROSS_NO_BIARCH + no_biarch_libs := yes +endif +ifeq ($(with_d)-$(with_separate_gdc),yes-yes) + no_biarch_libs := yes +endif + +ifeq ($(no_biarch_libs),yes) + with_lib64gcc := no + with_lib64cxx := no + with_lib64cxxdbg := no + with_lib64objc := no + with_lib64ffi := no + with_lib64gcj := no + with_lib64gfortran := no + with_lib64mudflap := no + with_lib64ssp := no + with_lib64gomp := no + + with_lib32gcc := no + with_lib32cxx := no + with_lib32cxxdbg := no + with_lib32objc := no + with_lib32ffi := no + with_lib32gcj := no + with_lib32gfortran := no + with_lib32mudflap := no + with_lib32ssp := no + with_lib32gomp := no + + with_libn32gcc := no + with_libn32cxx := no + with_libn32cxxdbg := no + with_libn32objc := no + with_libn32ffi := no + with_libn32gcj := no + with_libn32gfortran := no + with_libn32mudflap := no + with_libn32ssp := no + with_libn32gomp := no + + ifeq ($(PKGSOURCE),gcc-snapshot) + #biarch64 := disabled for snapshot build + #biarch32 := disabled for snapshot build + #biarchn32 := disabled for snapshot build + with_java_plugin := no + endif + + ifdef DEB_CROSS_NO_BIARCH + biarch64 := disabled by DEB_CROSS_NO_BIARCH + biarch32 := disabled by DEB_CROSS_NO_BIARCH + biarchn32 := disabled by DEB_CROSS_NO_BIARCH + endif + + ifeq ($(with_d)-$(with_separate_gdc),yes-yes) + biarch64 := disabled for D + biarch32 := disabled for D + biarchn32 := disabled for D + endif + +endif + +ifeq ($(biarch32),yes) + with_32bit_check := $(strip $(if $(wildcard build/runcheck.out), \ + $(shell cat build/runcheck.out), \ + $(shell CC="gcc -m32" bash debian/runcheck.sh))) +endif + +ifeq ($(biarch64),yes) + ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),mips mipsel)) + with_64bit_check := $(strip $(if $(wildcard build/runcheck.out), \ + $(shell cat build/runcheck.out), \ + $(shell CC="gcc -mabi=64" bash debian/runcheck.sh))) + else + with_64bit_check := $(strip $(if $(wildcard build/runcheck.out), \ + $(shell cat build/runcheck.out), \ + $(shell CC="gcc -m64" bash debian/runcheck.sh))) + endif +endif + +ifeq ($(biarchn32),yes) + with_n32bit_check := $(strip $(if $(wildcard build/runcheck.out), \ + $(shell cat build/runcheck.out), \ + $(shell CC="gcc -mabi=n32" bash debian/runcheck.sh))) +endif + +# GNU locales +force_gnu_locales := yes +locale_no_cpus := m68k +locale_no_systems := knetbsd-gnu +ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(locale_no_systems))) + force_gnu_locales := disabled for system $(DEB_TARGET_GNU_SYSTEM) +endif + +gcc_tarpath := $(firstword $(wildcard gcc-*.tar.* /usr/src/gcc-$(BASE_VERSION)/gcc-*.tar.*)) +gcc_tarball := $(notdir $(gcc_tarpath)) +gcc_srcdir := $(subst -dfsg,,$(patsubst %.tar.xz,%,$(patsubst %.tar.lzma,%,$(patsubst %.tar.gz,%,$(gcc_tarball:.tar.bz2=))))) + +ifeq ($(with_d),yes) + gdc_tarpath := $(firstword $(wildcard gdc-*.tar.* /usr/src/gcc-$(BASE_VERSION)/gdc-*.tar.*)) + gdc_tarball := $(notdir $(gdc_tarpath)) + gdc_srcdir := $(patsubst %.tar.xz,%,$(patsubst %.tar.lzma,%,$(patsubst %.tar.gz,%,$(gdc_tarball:.tar.bz2=)))) +endif + +ecj_jar := $(firstword $(wildcard ecj.jar /usr/share/java/eclipse-ecj.jar /usr/share/java/ecj.jar)) + +unpack_stamp := $(stampdir)/01-unpack-stamp +pre_patch_stamp := $(stampdir)/02-pre-patch-stamp +patch_stamp := $(stampdir)/02-patch-stamp +src_spu_stamp := $(stampdir)/02-src-spu-stamp +control_stamp := $(stampdir)/03-control-stamp +configure_stamp := $(stampdir)/04-configure-stamp +build_stamp := $(stampdir)/05-build-stamp +build_html_stamp := $(stampdir)/05-build-html-stamp +build_locale_stamp := $(stampdir)/05-build-locale-stamp +build_doxygen_stamp := $(stampdir)/05-build-doxygen-stamp +build_javasrc_stamp := $(stampdir)/05-build-javasrc-stamp +build_javadoc_stamp := $(stampdir)/05-build-javadoc-stamp +check_stamp := $(stampdir)/06-check-stamp +check_inst_stamp := $(stampdir)/06-check-inst-stamp +install_stamp := $(stampdir)/07-install-stamp +install_snap_stamp := $(stampdir)/07-install-snap-stamp +binary_stamp := $(stampdir)/08-binary-stamp + +configure_dummy_stamp := $(stampdir)/04-configure-dummy-stamp +build_dummy_stamp := $(stampdir)/05-build-dummy-stamp +install_dummy_stamp := $(stampdir)/07-install-dummy-stamp + +configure_hppa64_stamp := $(stampdir)/04-configure-hppa64-stamp +build_hppa64_stamp := $(stampdir)/05-build-hppa64-stamp +install_hppa64_stamp := $(stampdir)/07-install-hppa64-stamp + +configure_neon_stamp := $(stampdir)/04-configure-neon-stamp +build_neon_stamp := $(stampdir)/05-build-neon-stamp +install_neon_stamp := $(stampdir)/07-install-neon-stamp + +configure_ia6432_stamp := $(stampdir)/04-configure-ia6432-stamp +build_ia6432_stamp := $(stampdir)/05-build-ia6432-stamp +install_ia6432_stamp := $(stampdir)/07-install-ia6432-stamp + +configure_ia6432_stamp := $(stampdir)/04-configure-ia6432-stamp +build_ia6432_stamp := $(stampdir)/05-build-ia6432-stamp +install_ia6432_stamp := $(stampdir)/07-install-ia6432-stamp + +configure_spu_stamp := $(stampdir)/04-configure-spu-stamp +build_spu_stamp := $(stampdir)/05-build-spu-stamp +install_spu_stamp := $(stampdir)/07-install-spu-stamp + +control_dependencies := $(patch_stamp) + +ifeq ($(PKGSOURCE),gcc-snapshot) + configure_dependencies = $(configure_stamp) + build_dependencies = $(build_stamp) + install_dependencies = $(install_snap_stamp) + ifeq ($(with_check),yes) + check_dependencies += $(check_stamp) + endif +else + ifeq ($(with_base_only),yes) + configure_dependencies = $(configure_dummy_stamp) + build_dependencies = $(build_dummy_stamp) + install_dependencies = $(install_dummy_stamp) + else + configure_dependencies = $(configure_stamp) + build_dependencies = $(build_stamp) + install_dependencies = $(install_stamp) + ifeq ($(with_check),yes) + check_dependencies += $(check_stamp) + endif + endif +endif + +ifneq (,$(findstring gcj-, $(PKGSOURCE))) + ifeq ($(with_gcj_base_only),yes) + configure_dependencies = $(configure_dummy_stamp) + build_dependencies = $(build_dummy_stamp) + install_dependencies = $(install_dummy_stamp) + endif +endif + +ifeq ($(with_neon),yes) + build_dependencies += $(build_neon_stamp) + install_dependencies += $(install_neon_stamp) +endif + +ifeq ($(with_hppa64),yes) + build_dependencies += $(build_hppa64_stamp) + ifneq ($(PKGSOURCE),gcc-snapshot) + install_dependencies += $(install_hppa64_stamp) + endif +endif + +ifeq ($(with_ia6432),yes) + build_dependencies += $(build_ia6432_stamp) + ifneq ($(PKGSOURCE),gcc-snapshot) + install_dependencies += $(install_ia6432_stamp) + endif +endif + +ifeq ($(with_spu),yes) + control_dependencies += $(src_spu_stamp) + build_dependencies += $(build_spu_stamp) + ifneq ($(PKGSOURCE),gcc-snapshot) + install_dependencies += $(install_spu_stamp) + endif +endif + +build_dependencies += $(check_dependencies) + +stamp-dir: + mkdir -p $(stampdir) + +ifeq ($(DEB_CROSS),yes) + define cross_mangle_shlibs + sed -i s/$(cross_lib_arch)//g debian/$(1)/DEBIAN/shlibs + endef + define cross_mangle_substvars + sed -i 's/lib[^ ,(]*/&$(cross_lib_arch)/g' debian/$(1).substvars + endef +else + define cross_mangle_shlibs + endef + define cross_mangle_substvars + endef +endif + +ifneq (,$(filter $(DEB_TARGET_ARCH), mips mipsel)) + define cross_mangle_control + $(if $(findstring 64,$(1)),sed -i -r '/^(Dep|Rec|Sug)/s/[a-z0-9-]+32[^$(COMMA)]+($(COMMA) *|$$)//g;/^(Dep|Rec|Sug)/s/$(p_lgcc)/$(p_l64gcc)/;/^(Dep|Rec|Sug)/s/ *$(COMMA) *$$//' debian/$(1)/DEBIAN/control,@:) + $(if $(findstring n32,$(1)),sed -i -r '/^(Dep|Rec|Sug)/s/[a-z0-9-]+64[^$(COMMA)]+($(COMMA) *|$$)//g;/^(Dep|Rec|Sug)/s/$(p_lgcc)/$(p_ln32gcc)/;/^(Dep|Rec|Sug)/s/ *$(COMMA) *$$//' debian/$(1)/DEBIAN/control,@:) + endef +else + define cross_mangle_control + endef +endif --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.aeabi +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.aeabi @@ -0,0 +1,67 @@ + __aeabi_cdcmpeq@GCC_3.5 1:4.4.0 + __aeabi_cdcmple@GCC_3.5 1:4.4.0 + __aeabi_cdrcmple@GCC_3.5 1:4.4.0 + __aeabi_cfcmpeq@GCC_3.5 1:4.4.0 + __aeabi_cfcmple@GCC_3.5 1:4.4.0 + __aeabi_cfrcmple@GCC_3.5 1:4.4.0 + __aeabi_d2f@GCC_3.5 1:4.4.0 + __aeabi_d2iz@GCC_3.5 1:4.4.0 + __aeabi_d2lz@GCC_3.5 1:4.4.0 + __aeabi_d2uiz@GCC_3.5 1:4.4.0 + __aeabi_d2ulz@GCC_3.5 1:4.4.0 + __aeabi_dadd@GCC_3.5 1:4.4.0 + __aeabi_dcmpeq@GCC_3.5 1:4.4.0 + __aeabi_dcmpge@GCC_3.5 1:4.4.0 + __aeabi_dcmpgt@GCC_3.5 1:4.4.0 + __aeabi_dcmple@GCC_3.5 1:4.4.0 + __aeabi_dcmplt@GCC_3.5 1:4.4.0 + __aeabi_dcmpun@GCC_3.5 1:4.4.0 + __aeabi_ddiv@GCC_3.5 1:4.4.0 + __aeabi_dmul@GCC_3.5 1:4.4.0 + __aeabi_dneg@GCC_3.5 1:4.4.0 + __aeabi_drsub@GCC_3.5 1:4.4.0 + __aeabi_dsub@GCC_3.5 1:4.4.0 + __aeabi_f2d@GCC_3.5 1:4.4.0 + __aeabi_f2iz@GCC_3.5 1:4.4.0 + __aeabi_f2lz@GCC_3.5 1:4.4.0 + __aeabi_f2uiz@GCC_3.5 1:4.4.0 + __aeabi_f2ulz@GCC_3.5 1:4.4.0 + __aeabi_fadd@GCC_3.5 1:4.4.0 + __aeabi_fcmpeq@GCC_3.5 1:4.4.0 + __aeabi_fcmpge@GCC_3.5 1:4.4.0 + __aeabi_fcmpgt@GCC_3.5 1:4.4.0 + __aeabi_fcmple@GCC_3.5 1:4.4.0 + __aeabi_fcmplt@GCC_3.5 1:4.4.0 + __aeabi_fcmpun@GCC_3.5 1:4.4.0 + __aeabi_fdiv@GCC_3.5 1:4.4.0 + __aeabi_fmul@GCC_3.5 1:4.4.0 + __aeabi_fneg@GCC_3.5 1:4.4.0 + __aeabi_frsub@GCC_3.5 1:4.4.0 + __aeabi_fsub@GCC_3.5 1:4.4.0 + __aeabi_i2d@GCC_3.5 1:4.4.0 + __aeabi_i2f@GCC_3.5 1:4.4.0 + __aeabi_idiv@GCC_3.5 1:4.4.0 + __aeabi_idiv0@GCC_3.5 1:4.5.0 + __aeabi_idivmod@GCC_3.5 1:4.4.0 + __aeabi_l2d@GCC_3.5 1:4.4.0 + __aeabi_l2f@GCC_3.5 1:4.4.0 + __aeabi_lasr@GCC_3.5 1:4.4.0 + __aeabi_lcmp@GCC_3.5 1:4.4.0 + __aeabi_ldivmod@GCC_3.5 1:4.4.0 + __aeabi_ldiv0@GCC_3.5 1:4.5.0 + __aeabi_llsl@GCC_3.5 1:4.4.0 + __aeabi_llsr@GCC_3.5 1:4.4.0 + __aeabi_lmul@GCC_3.5 1:4.4.0 + __aeabi_ui2d@GCC_3.5 1:4.4.0 + __aeabi_ui2f@GCC_3.5 1:4.4.0 + __aeabi_uidiv@GCC_3.5 1:4.4.0 + __aeabi_uidivmod@GCC_3.5 1:4.4.0 + __aeabi_ul2d@GCC_3.5 1:4.4.0 + __aeabi_ul2f@GCC_3.5 1:4.4.0 + __aeabi_ulcmp@GCC_3.5 1:4.4.0 + __aeabi_uldivmod@GCC_3.5 1:4.4.0 + __aeabi_unwind_cpp_pr0@GCC_3.5 1:4.4.0 + __aeabi_uread4@GCC_3.5 1:4.4.0 + __aeabi_uread8@GCC_3.5 1:4.4.0 + __aeabi_uwrite4@GCC_3.5 1:4.4.0 + __aeabi_uwrite8@GCC_3.5 1:4.4.0 --- gcc-4.5-4.5.2.orig/debian/libgnatprjBV.overrides +++ gcc-4.5-4.5.2/debian/libgnatprjBV.overrides @@ -0,0 +1 @@ +libgnatprj@BV@: missing-dependency-on-libc --- gcc-4.5-4.5.2.orig/debian/logwatch.sh +++ gcc-4.5-4.5.2/debian/logwatch.sh @@ -0,0 +1,104 @@ +#! /bin/sh + +# script to trick the build daemons and output something, if there is +# still test/build activity + +# $1: primary file to watch. if there is activity on this file, we do nothing +# $2+: files to watch to look for activity despite no output in $1 +# if the files are modified or are newly created, then the message +# is printed on stdout. +# if nothing is modified, don't output anything (so the buildd timeout +# hits). + +pidfile=logwatch.pid +timeout=3600 +message='\nlogwatch still running\n' + +usage() +{ + echo >&2 "usage: `basename $0` [-p ] [-t ] [-m ]" + echo >&2 " [ ...]" + exit 1 +} + +while [ $# -gt 0 ]; do + case $1 in + -p) + pidfile=$2 + shift + shift + ;; + -t) + timeout=$2 + shift + shift + ;; + -m) + message="$2" + shift + shift + ;; + -*) + usage + ;; + *) + break + esac +done + +[ $# -gt 0 ] || usage + +logfile="$1" +shift +otherlogs="$@" + +cleanup() +{ + rm -f $pidfile + exit 0 +} + +#trap cleanup 0 1 3 15 + +echo $$ > $pidfile + +update() +{ + _logvar=$1 + _othervar=$2 + + # logfile may not exist yet + if [ -r $logfile ]; then + _logtail="`tail -10 $logfile | md5sum` $f" + else + _logtail="does not exist: $logfile" + fi + eval $_logvar="'$_logtail'" + + _othertails='' + for f in $otherlogs; do + if [ -r $f ]; then + _othertails="$_othertails `tail -10 $f | md5sum` $f" + else + _othertails="$_othertails does not exist: $f" + fi + done + eval $_othervar="'$_othertails'" +} + +update logtail othertails +while true; do + sleep $timeout + update newlogtail newothertails + if [ "$logtail" != "$newlogtail" ]; then + # there is still action in the primary logfile. do nothing. + logtail="$newlogtail" + elif [ "$othertails" != "$newothertails" ]; then + # there is still action in the other log files, so print the message + /bin/echo -e $message + othertails="$newothertails" + else + # nothing changed in the other log files. maybe a timeout ... + : + fi +done --- gcc-4.5-4.5.2.orig/debian/README.maintainers +++ gcc-4.5-4.5.2/debian/README.maintainers @@ -0,0 +1,237 @@ +-*- Outline -*- + +Read this file if you are a Debian Developer or would like to become +one, or if you would like to create your own binary packages of GCC. + +* Overview + +From the GCC sources, Debian currently builds 3 source packages and +almost 100 binary packages, using a single set of build scripts. The +3 source packages are: + +gcc-4.3: C, C++, Fortran, Objective-C and Objective-C++, plus many + common libraries like libssp, libmudflap, and libgcc. +gcj-4.3: Java. +gnat-4.3: Ada. + +The way we do this is quite peculiar, so listen up :) + +When we build from the gcc-4.3 source package, we produce, among many +others, a gcc-4.3-source binary package that contains the pristine +upstream tarball and some Debian-specific patches. Any user can then +install this package on their Debian system, and will have the full +souces in /usr/src/gcc-4.3/gcc-.tar.bz2, along with the +Makefile snippets that unpack and patch them. + +The intended use for this package is twofold: (a) allow users to build +their own cross-compilers, and (b) build the other two packages, +gcj-4.3 and gnat-4.3. + +For gcj-4.3 and gnat-4.3, the "source tarball" just contains an empty +directory; e.g.: + +$ tar tzf gnat-4.3_4.3-20070609.orig.tar.gz +gnat-4.3-4.3-20070609.orig/ + +The build scripts for all source packages are the same, and they are +included, as usual, in the .diff.gz file. + +* The build sequence + +As for all other Debian packages, you build GCC by calling +debian/rules. + +The first thing debian/rules does it to look at the top-most entry in +debian/changelog: this tells it which source package it is building. +For example, if the first entry in debian/changelog reads: + +gcj-4.3 (4.3-20070609-1) unstable; urgency=low + + * Upload as gcj-4.3. + + -- Ludovic Brenta Tue, 26 Jun 2007 00:26:42 +0200 + +then, debian/rules will build only the Java binary packages. + +The second step is to unpack the GCC source tarball. This tarball is +either in the build directory (when building gcc-4.3), or in +/usr/src/gcc-4.3/gcc-.tar.bz2 (when building the other +source packages). + +The third step is to build debian/control from debian/control.m4 and a +complex set of rules specified in debian/rules.conf. The resulting +control file contains only the binary packages to be built. + +The fourth step is to select which patches to apply (this is done in +debian/rules.defs), and then to apply the selected patches (see +debian/rules.patch). + +The fifth step is to create a "build" directory, cd into it, call +../src/configure, and bootstrap the compiler and libraries selected. +This is in debian/rules2. + +The sixth step is to call "make install" in the build directory: this +installs the compiler and libraries into debian/tmp +(i.e. debian/tmp/usr/bin/gcc, etc.) + +The seventh step is to run the GCC test suite (this actually takes at +least as much time as bootstrapping, and you can disable it by setting +WITHOUT_CHECK to "yes" in the environment). + +The eighth step is to build the binary packages, i.e. the .debs. This +is done by a set of language- and architecture-dependent Makefile +snippets in the debian/rules.d/ directory, which move files from the +debian/tmp tree to the debian/ trees. + +* Making your own packages + +In this example, we will build our own gnat-4.3 package. + +1) Create a .orig.tar.gz tarball containing a single, empty directory. + +$ mkdir gnat-4.3-4.3-20070609.orig +$ tar czf gnat-4.3_4.3-20070609.orig.tar.gz gnat-4.3-4.3-20070609.orig + +2) Install gcc-4.3-source, which contains the real sources: + +# apt-get install gcc-4.3-source + +3) Create a build directory: + +$ mkdir gnat-4.3-4.3-20070609; cd gnat-4.3-4.3-20070609 + +4) Checkout from Subversion: + +$ svn checkout svn://svn.debian.org/gcccvs/branches/sid/gcc-4.3/debian + +5) Edit the debian/changelog file, adding a new entry at the top that + starts with "gnat-4.3" instead of "gcc-4.3". + +6) Generate the debian/control file, adjusted for gnat: + +$ debian/rules control + +7) Build: + +$ dpkg-buildpackage -rfakeroot + +* Hints + +You need a powerful machine to build GCC. The larger, the better. +The build scripts take advantage of as many CPU threads as are +available in your box (for example: 2 threads on a dual-core amd64; 4 +threads on a dual-core POWER5; 32 threads on an 8-core UltraSPARC T1, +etc.). + +If you have 2 GB or more of physical RAM, you can achieve maximum +performance by building in a tmpfs, like this: + +1) as root, create the new tmpfs: + +# mount -t tmpfs -o size=1280m none /home/lbrenta/src/debian/ram + +By default, the tmpfs will be limited to half your physical RAM. The +beauty of it is that it only consumes as much physical RAM as +necessary to hold the files in it; deleting files frees up RAM. + +2) As your regular user, create the working directory in the tmpfs + +$ cp --archive ~/src/debian/gcc-4.3-4.3-20070901 ~/src/debian/ram + +3) Build in there. On my dual-core, 2 GHz amd64, it takes 34 minutes + to build gnat, and the tmpfs takes 992 MiB of physical RAM but + exceeds 1 GiB during the build. + +Note that the build process uses a lot of temporary files. Your $TEMP +directory should therefore also be in a ram disk. You can achieve +that either by mounting it as tmpfs, or by setting TEMP to point to +~/src/debian/ram. + +Also note that each thread in your processor(s) will run a compiler in +it and use up RAM. Therefore your physical memory should be: + +Physical_RAM >= 1.2 + 0.4 * Threads (in GiB) + +(this is an estimate; your mileage may vary). If you have less +physical RAM than recommended, reduce the number of threads allocated +to the build process, or do not use a tmpfs to build. + +* Patching GCC + +Debian applies a large number of patches to GCC as part of the build +process. The patches are shell scripts located in debian/patches. +The file debian/rules.defs selects the language front-ends and +libraries to build. Then, based on that, debian/rules.patch selects +which patches to apply and in which order, then applies them and +produces a file listing the applied patches in order in +stamps/02-patch-stamp. + +There is currently no tool to help modify patches; you have to do it +by hand. Here is one possible way to do it: + +1) Apply all patches up to and EXCLUDING the patch you intend to + modify, in order. + +2) Make a deep copy of the src directory, e.g. + $ cp --archive src src.bak + +3) Apply the patch you intend to modify. + +4) Open the .dpatch file in your editor and remove the entire patch + section; leave alone the shell script part at the top. + +5) Change the files you want in the src directory. After making + changes, you can experiment with + $ make -C build -jK + (where K is the number of processor threads you have) + +6) $ diff -rNu src.bak src >> debian/patches/.dpatch + +7) Apply all remaining patches, to see if your change broke any of + them. + +8) $ svn commit debian/patches/.dpatch + +If you want to add a new patch, the procedure is similar. You must +first choose where in the list of patches you want to insert your new +patch. Then, apply all patches up to that point and start editing. +Do not forget to add a reference to your patch at the proper place in +debian/rules.patch. + +** Patching GCC with Quilt + +The above method uses an entire copy of the source tree, which is +currently 474 megabytes in size. If you are in a one-gigabyte ram +disk (see Hints above), this may be a problem. One solution to this +problem is to use quilt, which will only keep copies of the files +touched by patches, not all files. It also automates the updating of +a patch after you change the sources. + +Quilt however does not take into account the selection of patches made +in debian/rules.defs; instead it has a static list of patches. After +calling "debian/rules patch", you can generate such a list like this: + +$ egrep '^[^ ]+:' stamps/02-patch-stamp | \ + sed 's!:!.dpatch -p0!' > debian/patches/series + +Unfortunately, not all patches are applied with -p0; you must then +edit debian/patches/series by hand to replace -p0 with -p1 for a few +patches. + +Once you have your debian/patches/series: + +$ debian/rules unpatch +$ export QUILT_PATCHES=$PWD/debian/patches +$ cd src +$ quilt push -a (or quilt push ) +edit files at will; quilt add to add a new file to the patch +$ make -C ../build +$ quilt refresh +$ quilt push -a # check that no patch is broken +$ quilt pop -a +$ cd .. +$ debian/rules clean build +$ svn commit + +-- +Ludovic Brenta, 2007-12-05. --- gcc-4.5-4.5.2.orig/debian/dummy.texi +++ gcc-4.5-4.5.2/debian/dummy.texi @@ -0,0 +1 @@ +@c This file is empty because the original one has a non DFSG free license (GFDL) --- gcc-4.5-4.5.2.orig/debian/libgcjLGCJ.postrm +++ gcc-4.5-4.5.2/debian/libgcjLGCJ.postrm @@ -0,0 +1,12 @@ +#! /bin/sh -e + +case "$1" in + remove|purge) + # only purge if no other library is installed. + if [ -z "$(ls /usr/lib/libgcj.so.@GCJ@* 2>/dev/null)" ]; then + rm -f /var/lib/gcj-@BV@/classmap.db + rmdir --ignore-fail-on-non-empty /var/lib/gcj-@BV@ 2>&1 || true + fi +esac + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.64bit +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.64bit @@ -0,0 +1,540 @@ +#include "libstdc++6.symbols.common" + _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEm@GLIBCXX_3.4.2 4.1.1 + _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEm@GLIBCXX_3.4.2 4.1.1 + _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPcl@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKcl@GLIBCXX_3.4.10 4.3.0~rc2 + _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2 + 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__fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfti@GCC_3.0 1:4.1.1 + __fixunstfti@GCC_3.0 1:4.1.1 + __floattidf@GCC_3.0 1:4.1.1 + __floattisf@GCC_3.0 1:4.1.1 + __floattitf@GCC_3.0 1:4.1.1 + __floatuntidf@GCC_4.2.0 1:4.2.1 + __floatuntisf@GCC_4.2.0 1:4.2.1 + __floatuntitf@GCC_4.2.0 1:4.2.1 + __frame_state_for@GLIBC_2.2 1:4.1.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __lshrti3@GCC_3.0 1:4.1.1 + __modti3@GCC_3.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_4.0.0 1:4.1.1 + __multi3@GCC_3.0 1:4.1.1 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __mulvti3@GCC_3.4.4 1:4.1.1 + __negti2@GCC_3.0 1:4.1.1 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __negvti2@GCC_3.4.4 1:4.1.1 + __paritydi2@GCC_3.4 1:4.1.1 + __parityti2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountti2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_4.0.0 1:4.1.1 + __register_frame@GLIBC_2.2 1:4.1.1 + __register_frame_info@GLIBC_2.2 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GLIBC_2.2 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GLIBC_2.2 1:4.1.1 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __subvti3@GCC_3.4.4 1:4.1.1 + __ucmpti2@GCC_3.0 1:4.1.1 + __udivmodti4@GCC_3.0 1:4.1.1 + __udivti3@GCC_3.0 1:4.1.1 + __umodti3@GCC_3.0 1:4.1.1 --- gcc-4.5-4.5.2.orig/debian/libgnat-BV.overrides +++ gcc-4.5-4.5.2/debian/libgnat-BV.overrides @@ -0,0 +1 @@ +libgnat-@BV@: package-name-doesnt-match-sonames --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.sparc +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.sparc @@ -0,0 +1,3 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.16.powerpc" --- gcc-4.5-4.5.2.orig/debian/changelog +++ gcc-4.5-4.5.2/debian/changelog @@ -0,0 +1,9658 @@ +gcc-4.5 (4.5.2-8ubuntu4) natty; urgency=low + + * For Linaro based builds, do not turn on -fshrink-wrap by default on armel + (was already disabled for other architectures). LP: #736081. + + -- Matthias Klose Mon, 18 Apr 2011 13:25:46 +0200 + +gcc-4.5 (4.5.2-8ubuntu3) natty; urgency=low + + * Avoid warning building GC enabled libobjc on amd64 (which the production + buildd now turns into a hard error). + + -- Matthias Klose Sun, 10 Apr 2011 19:19:09 +0200 + +gcc-4.5 (4.5.2-8ubuntu2) natty; urgency=low + + * For the natty release, do not pass --no-add-needed by default to the + linker. + The --no-add-needed flag will be default again for the o-series. + + -- Matthias Klose Sat, 09 Apr 2011 18:07:53 +0200 + +gcc-4.5 (4.5.2-8ubuntu1) natty; urgency=low + + * libjava-jnipath.diff: Add /usr/lib//jni as jnipath too. + + -- Matthias Klose Fri, 01 Apr 2011 19:49:27 +0200 + +gcc-4.5 (4.5.2-8) unstable; urgency=low + + * Update to SVN 20110329 (r171685) from the gcc-4_5-branch. + - Fix PR target/47553, PR other/48254, PR other/48179, PR other/48234. + + [ Matthias Klose ] + * Don't build packages now built from gcc-4.6 (on architectures with + a successful gcc-4.6 build). + * Apply proposed patch to reduce the overhead of dwarf2 location tracking. + (Richard Sandiford). Closes: #618748. + + [ Marcin Juszkiewicz ] + * Fixes issues with staged cross builds. LP: #741855, #741853. + * Fix libdir setting for multiarch enabled cross builds. LP: #741846. + * Drop alternatives for cross builds. LP: #676454. + + -- Matthias Klose Tue, 29 Mar 2011 20:27:12 +0200 + +gcc-4.5 (4.5.2-7) unstable; urgency=low + + * Update to SVN 20110323 (r171351) from the gcc-4_5-branch. + - Fix PR c++/47125, PR fortran/47348, PR libstdc++/48114, + PR libfortran/48066, PR target/48171, PR target/47862. + PR preprocessor/48192. + + [ Steve Langasek ] + * Make dpkg-dev versioned build-dependency conditional on whether we want + to build for multiarch. + * Add a new patch, gcc-multiarch+biarch.diff, used only when building for + multiarch to set our multilib paths to the correct relative directories. + * debian/rules.defs: support turning on multiarch build by architecture; + but don't enable this yet, we still need to wait for dpkg-dev. + * When DEB_HOST_MULTIARCH is available (i.e., with the next dpkg upload), + use it as our multiarch path. + * debian/rules.d/binary-java.mk: jvm-exports path is /usr/lib/jvm-exports, + not $(libdir)/jvm-exports. + * OTOH, libgcj_bc *is* in $(libdir). + * the spu build is not a multiarch build; look in the correct + non-multiarch directory. + * debian/rules2: pass --libdir also for stageX builds, needed in order to + successfully build for multiarch. + * debian/rules2: $(usr_lib) for a cross-build should not include the + multiarch dir as part of the path. + * debian/patches/gcc-multiarch+biarch.diff: restore the original intent of + the patch, namely, that the multilib dir for the default variant is + always equal to libdir (the multiarch dir), and we walk up the tree + to find lib for the secondary variant. + * debian/patches/gcc-multiarch+biarch32.diff: apply the same multilib + directory rewriting for biarch paths with multiarch as we do without; + still needed in the near term. + * Put our list of patches in README.Debian.$(DEB_TARGET_ARCH) instead of + in README.Debian, so that the individual files are architecture-neutral + and play nicely with multiarch. LP: #737846. + * Add a comment at the bottom of README.Debian with a pointer to the new + file listing the patches. + + [ Loic Minier ] + * Rework config/vxworks-dummy.h installation snippet to test + DEB_TARGET_GNU_CPU against patterns close to the upstream ones (arm% mips% + sh% sparc%) as to also install this header on other ports targetting the + relevant upstream CPUs such as armhf. Add a comment pointing at the + upstream bug. + * Update __aeabi symbol handling to test whether DEB_TARGET_GNU_TYPE matches + arm-linux-gnueabi% instead of testing whether DEB_TARGET_ARCH equals + armel. Add a comment pointing at the Debian bug and indicating that this + is only useful for older dpkg-dev versions. + * debian/rules.def: fix "armel" entry to "arm" in list of + DEB_TARGET_ARCH_CPUs for Debian experimental GCC 4.5/4.6 libraries. + * debian/rules2: drop commented out GCC #42509 workaround as this was fixed + upstream in 4.4+. + * Change bogus DEB_TARGET_GNU_CPU test on armel and armhf to just test for + arm as ths is what the Debian arm, armel and armhf port use. + * Rework snippet setting armv7 on Debian armhf / Ubuntu to avoid + duplication, as a comment called out for. + * Use "arm" instead of armel/armhf in DEB_TARGET_GNU_CPU test when deciding + whether to enable profiledbootstrap. + * Set DEJAGNU_TIMEOUT=600 on Ubuntu armhf as well. + * Fix a couple more uses of armel or armhf against DEB_TARGET_GNU_CPU. + * Patched a couple of comments mentioning armel to also mention armhf. + * Add patch armhf-triplet-backport, support for arm-linux-*eabi* backported + from a patch sent on the upstream mailing-list. + + [ Matthias Klose ] + * Fix PR target/48226, Allow Iterator::vector vector on powerpc with VSX, + taken from the trunk. + * Fix PR preprocessor/48192, make conditional macros not defined for + #ifdef, proposed patch. + * Build the gold LTO plugin for ppc64 (Hiroyuki Yamamoto). Closes: #618864. + * Fix issue with volatile bitfields, default to -fstrict-volatile-bitfields + again on armel for Linaro builds. LP: #675347. + + -- Matthias Klose Wed, 23 Mar 2011 15:44:01 +0100 + +gcc-4.5 (4.5.2-6ubuntu5) natty; urgency=low + + [ Loïc Minier ] + * Rework config/vxworks-dummy.h installation snippet to test + DEB_TARGET_GNU_CPU against patterns close to the upstream ones (arm% mips% + sh% sparc%) as to also install this header on other ports targetting the + relevant upstream CPUs such as armhf. Add a comment pointing at the + upstream bug. + * Update __aeabi symbol handling to test whether DEB_TARGET_GNU_TYPE matches + arm-linux-gnueabi% instead of testing whether DEB_TARGET_ARCH equals + armel. Add a comment pointing at the Debian bug and indicating that this + is only useful for older dpkg-dev versions. + * debian/rules.def: fix "armel" entry to "arm" in list of + DEB_TARGET_ARCH_CPUs for Debian experimental GCC 4.5/4.6 libraries. + * debian/rules2: drop commented out GCC #42509 workaround as this was fixed + upstream in 4.4+. + * Change bogus DEB_TARGET_GNU_CPU test on armel and armhf to just test for + arm as ths is what the Debian arm, armel and armhf port use. + * Rework snippet setting armv7 on Debian armhf / Ubuntu to avoid + duplication, as a comment called out for. + * Use "arm" instead of armel/armhf in DEB_TARGET_GNU_CPU test when deciding + whether to enable profiledbootstrap. + * Set DEJAGNU_TIMEOUT=600 on Ubuntu armhf as well. + * Fix a couple more uses of armel or armhf against DEB_TARGET_GNU_CPU. + * Patched a couple of comments mentioning armel to also mention armhf. + * Rename Vcs-* fields to XS-Debian-Vcs-*. + * Add patch armhf-triplet-backport, support for arm-linux-*eabi* backported + from a patch sent on the upstream mailing-list. + + [ Steve Langasek ] + * debian/rules2: pass --libdir also for stageX builds, needed in order to + successfully build for multiarch. + * debian/rules2: $(usr_lib) for a cross-build should not include the + multiarch dir as part of the path. + * debian/patches/gcc-multiarch+biarch.diff: restore the original intent of + the patch, namely, that the multilib dir for the default variant is + always equal to libdir (the multiarch dir), and we walk up the tree + to find lib for the secondary variant. + * debian/patches/gcc-multiarch+biarch32.diff: apply the same multilib + directory rewriting for biarch paths with multiarch as we do without; + still needed in the near term. + * Put our list of patches in README.Debian.$(DEB_TARGET_ARCH) instead of + in README.Debian, so that the individual files are architecture-neutral + and play nicely with multiarch. LP: #737846. + * Add a comment at the bottom of README.Debian with a pointer to the new + file listing the patches. + + -- Steve Langasek Sun, 20 Mar 2011 23:39:24 -0700 + +gcc-4.5 (4.5.2-6ubuntu4) natty; urgency=low + + * the spu build is not a multiarch build; look in the correct directory. + + -- Steve Langasek Wed, 16 Mar 2011 22:03:44 -0700 + +gcc-4.5 (4.5.2-6ubuntu3) natty; urgency=low + + * Build for multiarch, installing our libraries to multiarch paths. + * Bump the libc build-dependency to the official Ubuntu version for + multiarch. + + [ Matthias Klose ] + * debian/patches/ibm-branch.diff: updates from the ibm/4.5 branch up to + 20110315 (r171000). + + -- Steve Langasek Tue, 15 Mar 2011 19:30:48 -0700 + +gcc-4.5 (4.5.2-6ubuntu2) natty; urgency=low + + * Make dpkg-dev versioned build-dependency conditional on whether we want + to build for multiarch. + * Add a new patch, gcc-multiarch+biarch.diff, used only when building for + multiarch to set our multilib paths to the correct relative directories. + * debian/rules.defs: support turning on multiarch build by distribution. + * When DEB_HOST_MULTIARCH is available (i.e., with the next dpkg upload), + use it as our multiarch path. + * Build for final multiarch paths for stage 1 of the multiarch bootstrap. + (FFe: LP: #733501) + + -- Steve Langasek Mon, 14 Mar 2011 19:31:56 -0700 + +gcc-4.5 (4.5.2-6ubuntu1) natty; urgency=low + + * Merge with Debian. + + -- Matthias Klose Sun, 13 Mar 2011 21:08:59 +0100 + +gcc-4.5 (4.5.2-6) unstable; urgency=low + + * Update to SVN 20110312 (r170895) from the gcc-4_5-branch. + - Fix PR tree-optimization/45967, PR tree-optimization/47278, + PR target/47862, PR c++/44629, PR c++/45651, PR c++/47289, PR c++/47705, + PR c++/47488, PR libgfortran/47778, PR c++/48029. + + [ Steve Langasek ] + * Make sure our libs Pre-Depend on 'multiarch-support' when building for + multiarch. + * debian/patches/gcc-multiarch*, debian/rules.patch: use i386 in the + multiarch path for amd64 / kfreebsd-amd64, not i486 or i686. This lets + us use a common set of paths on both Debian and Ubuntu, regardless of + the target default optimization level. + * debian/rules.conf: when building for multiarch, we need to be sure we + are building against a libc-dev that supports the corresponding paths. + (the referenced version number for this needs to be bumped once this is + officially in the archive.) + + [ Matthias Klose ] + * Don't run the libmudflap testsuite on hppa; times out on the buildd. + * Don't run the libstdc++ testsuite on mipsel; times out on the buildd. + * Post Linaro 4.5-2011.03-0 release changes (up to 20110313). + * Undefine LINK_EH_SPEC before redefining it to turn off warnings on + powerpc. + * Update gmp (build) dependencies. + + [ Aurelien Jarno ] + * Add symbol files on kfreebsd-i386. + * Add symbol files on kfreebsd-amd64. + * Add symbol files on sparc64. + * Add symbol files on sh4. + + -- Matthias Klose Sun, 13 Mar 2011 17:30:48 +0100 + +gcc-4.5 (4.5.2-5ubuntu2) natty; urgency=low + + * Update to SVN 20110308 (r170777) from the gcc-4_5-branch. + - Fix PR tree-optimization/45967, PR tree-optimization/47278, + PR target/47862, PR libgfortran/47778. + * For Linaro based builds, do not turn on -fshrink-wrap by default with + -O2 except for ARM native and ARM cross builds. LP: #730860. + + -- Matthias Klose Tue, 08 Mar 2011 15:17:39 +0100 + +gcc-4.5 (4.5.2-5ubuntu1) natty; urgency=low + * Post Linaro 4.5-2011.03-0 release updates. + * Undefine LINK_EH_SPEC before redefining it to turn off warnings on + powerpc. + + * For the natty release, do not pass --as-needed by default to the linker. + The --as-needed flag will be default again for the o-series. + + -- Matthias Klose Sun, 06 Mar 2011 12:22:47 +0100 + +gcc-4.5 (4.5.2-5) unstable; urgency=low + + * Update to SVN 20110305 (r170696) from the gcc-4_5-branch. + - Fix PR target/43810, PR fortran/47886, PR tree-optimization/47615, + PR middle-end/47639, PR tree-optimization/47890, PR libfortran/47830, + PR tree-optimization/46723, PR target/45261, PR target/45808, + PR c++/46159, PR c++/47904, PR fortran/47886, PR libstdc++/47433, + PR target/42240, PR fortran/47878, PR libfortran/47694. + * Update the Linaro support to the 4.5-2011.03-0 release. + - Fix LP: #705689, LP: #695302, LP: #710652, LP: #710623, LP: #721021, + LP: #721021, LP: #709453. + + -- Matthias Klose Sun, 06 Mar 2011 02:58:01 +0100 + +gcc-4.5 (4.5.2-4) unstable; urgency=low + + * Update to SVN 20110222 (r170382) from the gcc-4_5-branch. + - Fix PR target/43653, PR fortran/47775, PR target/47840, + PR libfortran/47830. + + [ Matthias Klose ] + * Don't apply a patch twice. + * Build libgcc_s with -fno-stack-protector, when not building from the + Linaro branch. + * Backport proposed fix for PR tree-optimization/46723 from the trunk. + + [ Steve Langasek ] + * debian/control.m4: add missing Multi-Arch: same for libgcc4; make sure + Multi-Arch: same doesn't get set for libmudflap when building an + Architecture: all cross-compiler package. + * debian/rules2: use $libdir for libiberty.a. + * debian/patches/gcc-multiarch-*.diff: make sure we're using the same + set_multiarch_path definition for all variants. + + [ Sebastian Andrzej Siewior ] + * PR target/44364 + * Remove -many on powerpcspe (__SPE__) + * Remove classic FPU opcodes from libgcc if target has no support for them + (powerpcspe) + + -- Matthias Klose Wed, 23 Feb 2011 00:35:54 +0100 + +gcc-4.5 (4.5.2-3ubuntu3) natty; urgency=low + + * Update to SVN 20110222 (r170382) from the gcc-4_5-branch. + - Fix PR target/43653, PR fortran/47775, PR target/47840. + * Update the ibm/gcc-4_5-branch to 20110221. LP: #722270. + * Build libgcc_s with -fno-stack-protector, when not building from the + Linaro branch. + * Update the Linaro support to the 4.5 branch 20110303. + - Fix LP: #705689, LP: #695302, LP: #710652, LP: #710623, LP: #721021, + LP: #721021, LP: #709453. + + -- Matthias Klose Tue, 22 Feb 2011 03:33:20 +0100 + +gcc-4.5 (4.5.2-3ubuntu2) natty; urgency=low + + [ Matthias Klose ] + * Backport proposed fix for PR tree-optimization/46723 from the trunk. + * On ppc64, run the tests with the env var DEB_GCC_NO_O3 set. + * For spu, don't replace -O1 and -O2 with -O3. + + [ Steve Langasek ] + * debian/control.m4: add missing Multi-Arch: same for libgcc4; make sure + Multi-Arch: same doesn't get set for libmudflap when building an + Architecture: all cross-compiler package. + * debian/rules2: use $libdir for libiberty.a. + * debian/patches/gcc-multiarch-*.diff: make sure we're using the same + set_multiarch_path definition for all variants. + + -- Matthias Klose Sat, 19 Feb 2011 16:23:31 +0100 + +gcc-4.5 (4.5.2-3ubuntu1) natty; urgency=low + + * Merge with Debian. + + -- Matthias Klose Wed, 16 Feb 2011 15:37:37 +0100 + +gcc-4.5 (4.5.2-3) experimental; urgency=low + + * Update to SVN 20110215 (r170181) from the gcc-4_5-branch. + - Fix PR rtl-optimization/44469, PR tree-optimization/47411, + PR bootstrap/44699, PR target/44392, PR fortran/47331, PR fortran/47448, + PR pch/14940, PR rtl-optimization/47166, PR target/47272, PR target/47580, + PR tree-optimization/47541, PR target/44606, PR boehm-gc/34544, + PR fortran/47569, PR libstdc++/47709, PR libstdc++/46914, PR libffi/46661. + * Update the Linaro support to the 4.5 2011.02-0 release. + * Pass --no-add-needed by default to the linker. See + http://wiki.debian.org/ToolChain/DSOLinking, section "Not resolving symbols + in indirect dependent shared libraries" for more information. + + -- Matthias Klose Wed, 16 Feb 2011 15:29:26 +0100 + +gcc-4.5 (4.5.2-2ubuntu3) natty; urgency=low + + * Fix if-env-unset calling syntax. + * Remove debian/lib32gomp1.symbols.ppc64; the ppc64-specific symbols here + do not seem to exist. + + -- Colin Watson Fri, 11 Feb 2011 10:28:26 +0000 + +gcc-4.5 (4.5.2-2ubuntu2) natty; urgency=low + + * PPC64 changes: + - Apply the ibm/gcc-4_5-branch. + - Configure ppc64 for power7. + - Replace -O1 and -O2 with -O3, unless the env var DEB_GCC_NO_O3 is set. + + -- Matthias Klose Thu, 27 Jan 2011 14:58:39 +0100 + +gcc-4.5 (4.5.2-2ubuntu1) natty; urgency=low + + * Update to SVN 20110127 (r169330) from the gcc-4_5-branch. + - Fix PR rtl-optimization/44469, PR tree-optimization/47411, + PR bootstrap/44699, PR target/44392, PR fortran/47331, PR fortran/47448. + * Update the Linaro support to the 4.5 2011.02-0 release. + + -- Matthias Klose Thu, 27 Jan 2011 14:11:30 +0100 + +gcc-4.5 (4.5.2-2) experimental; urgency=low + + * Update to SVN 20110123 (r169142) from the gcc-4_5-branch. + - Fix PR target/46915, PR target/46729, PR libgcj/46774, PR target/47038, + PR target/46685, PR target/45447, PR tree-optimization/46758, + PR tree-optimization/45552, PR tree-optimization/43023, + PR middle-end/46734, PR fortran/45338, PR preprocessor/39213, + PR target/43309, PR fortran/46874, PR tree-optimization/47286, + PR tree-optimization/44592, PR target/47201, PR c/47150, PR target/46880, + PR middle-end/45852, PR tree-optimization/43655, PR debug/46893, + PR rtl-optimization/46804, PR rtl-optimization/46865, PR target/41082, + PR tree-optimization/46864, PR fortran/45777, PR tree-optimization/47365, + PR tree-optimization/47167, PR target/47318, PR target/46655, + PR fortran/47394, PR libstdc++/47354. + + [ Matthias Klose ] + * Update the Linaro support to the 4.5 2011.01-1 release. + * Don't build packages now built from the gcc-4.6 package for architectures + with a sucessful gcc-4.6 build. + + [ Kees Cook ] + * debian/patches/gcc-default-ssp.patch: do not ignore -fstack-protector-all + (LP: #691722). + + [ Marcin Juszkiewicz ] + * Fix biarch/triarch cross builds. + - dpkg-shlibdeps failed to find libraries for 64 or n32 builds + - LD_LIBRARY_PATH for dpkg-shlibdeps lacked host dirs. + + -- Matthias Klose Sun, 23 Jan 2011 11:54:52 +0100 + +gcc-4.5 (4.5.2-1ubuntu6) natty; urgency=low + + * Update to SVN 20110117 (r168896) from the gcc-4_5-branch. + - Fix PR target/43309, PR fortran/46874, PR tree-optimization/47286, + PR tree-optimization/44592, PR target/47201, PR c/47150, PR target/46880, + PR middle-end/45852, PR tree-optimization/43655, PR debug/46893, + PR rtl-optimization/46804, PR rtl-optimization/46865, PR target/41082, + PR tree-optimization/46864, PR fortran/45777. + * Apply proposed patch for PR rtl-optimization/47299. LP: #685352. + + -- Matthias Klose Mon, 17 Jan 2011 18:03:28 +0100 + +gcc-4.5 (4.5.2-1ubuntu5) natty; urgency=low + + * Update the Linaro support to the 4.5 2011.01-1 release. LP: #701733. + + -- Matthias Klose Thu, 13 Jan 2011 23:52:30 +0100 + +gcc-4.5 (4.5.2-1ubuntu4) natty; urgency=low + + * Update to SVN 20110113 (r168766) from the gcc-4_5-branch. + - Fix PR target/43309. + * Update the Linaro support to the 4.5 2011.01 release. + + -- Matthias Klose Tue, 11 Jan 2011 22:52:27 +0100 + +gcc-4.5 (4.5.2-1ubuntu3) natty; urgency=low + + * Update to SVN 20110107 (r168562) from the gcc-4_5-branch. + - Fix PR target/47038, + PR target/46685, PR target/45447, PR tree-optimization/46758, + PR tree-optimization/45552, PR tree-optimization/43023, + PR middle-end/46734, PR fortran/45338, PR preprocessor/39213. + + [ Kees Cook ] + * debian/patches/gcc-default-ssp.patch: do not ignore -fstack-protector-all + (LP: #691722). + + -- Matthias Klose Fri, 07 Jan 2011 16:19:05 +0100 + +gcc-4.5 (4.5.2-1ubuntu2) natty; urgency=low + + * Update to SVN 20101220 (r168097) from the gcc-4_5-branch. + - Fix PR target/46915, PR target/46729, PR libgcj/46774. + * Work around a build failure of the spu cross compiler when built + from the Linaro branch (Ulrich Weigand). + + -- Matthias Klose Tue, 21 Dec 2010 01:23:35 +0100 + +gcc-4.5 (4.5.2-1ubuntu1) natty; urgency=low + + * Merge with Debian, remaining changes: + - Build from the upstream tarball, including GFDL documents. + + -- Matthias Klose Sat, 18 Dec 2010 14:50:59 +0100 + +gcc-4.5 (4.5.2-1) experimental; urgency=low + + * GCC 4.5.2 release. + + -- Matthias Klose Sat, 18 Dec 2010 14:14:38 +0100 + +gcc-4.5 (4.5.1-12ubuntu1) natty; urgency=low + + * Merge with Debian, remaining changes: + - Build from the upstream tarball, including GFDL documents. + + -- Matthias Klose Fri, 10 Dec 2010 20:19:12 +0100 + +gcc-4.5 (4.5.1-12) experimental; urgency=low + + * Update to SVN 20101210 (r167686) from the gcc-4_5-branch (4.5.2 rc). + - Fix PR fortran/45742, PR tree-optimization/46498, PR target/45807, + PR target/44266, PR rtl-optimization/46315, PR tree-optimization/44545, + PR tree-optimization/46491, PR rtl-optimization/46571, PR target/31100, + PR c/46547, PR fortran/46638, PR tree-optimization/46675, PR debug/46258, + PR ada/40777, PR fortran/46753, PR libgomp/45240, PR target/43897, + PR rtl-optimization/46777, PR rtl-optimization/46614, + PR middle-end/46629, PR middle-end/46499, PR tree-optimization/44676, + PR target/45870, PR middle-end/46534, PR rtl-optimization/46440, + PR c++/46401, PR tree-optimization/46806, PR tree-optimization/46663, + PR debug/46123, PR middle-end/46651, PR c++/46538, PR c++/46058, + PR fortran/46794, PR target/45693, PR libgcj/42986. + + [ Matthias Klose ] + * Use lib instead of lib64 as the 64bit system dir on biarch + architectures defaulting to 64bit. Closes: #603597. + * Fix powerpc and s390 builds when biarch is disabled. + * Backport PR bootstrap/44768, miscompilation of dpkg on ARM + with -O2 (Chung-Lin Tang). LP: #674146. + * Update libgcc2 symbols file. Closes: #602099. + * Update the Linaro support to the 4.5 2010.12 release. + + [ Marcin Juszkiewicz ] + * Do not depend on target mpfr and zlib -dev packages for cross builds. + LP: #676027. + * Apply ARM target configure options for stage1/stage2 cross builds. + LP: #684625. + * Allow to build only the -source package, and include the version + in the package name. LP: #682333. + + [ Konstantinos Margaritis ] + * Add support for new target architecture `armhf'. Closes: #603948. + + -- Matthias Klose Fri, 10 Dec 2010 20:11:08 +0100 + +gcc-4.5 (4.5.1-11) experimental; urgency=low + + * Update to SVN 20101114 (r166728) from the gcc-4_5-branch. + - Fix PR fortran/45742. + * Don't hardcode debian/patches when referencing patches. Closes: #600502. + + -- Matthias Klose Sun, 14 Nov 2010 08:36:27 +0100 + +gcc-4.5 (4.5.1-10ubuntu3) natty; urgency=low + + * Update to SVN 20101126 (r167167) from the gcc-4_5-branch. + - Fix PR rtl-optimization/46571, PR target/31100, PR c/46547, + PR fortran/46638. + + [ Matthias Klose ] + * Fix powerpc and s390 builds when biarch is disabled. + * Revert Linaro issue #1259. + * Backport PR bootstrap/44768, miscompilation of dpkg on ARM + with -O2 (Chung-Lin Tang). LP: #674146. + + [ Konstantinos Margaritis ] + * Add support for new target architecture `armhf'. Closes: #603948. + + -- Matthias Klose Fri, 26 Nov 2010 17:29:48 +0100 + +gcc-4.5 (4.5.1-10ubuntu2) natty; urgency=low + + * Update to SVN 20101117 (r166863) from the gcc-4_5-branch. + - Fix PR fortran/45742, PR tree-optimization/46498, PR target/45807, + PR target/44266, PR rtl-optimization/46315, PR tree-optimization/44545, + PR tree-optimization/46491. + + [ Matthias Klose ] + * Use lib instead of lib64 as the 64bit system dir on biarch + architectures defaulting to 64bit. Closes: #603597. + * Backport PR bootstrap/44768, miscompilation of dpkg on ARM + with -O2 (Chung-Lin Tang). LP: #674146. + + [ Marcin Juszkiewicz ] + * Do not depend on target mpfr and zlib -dev packages for cross builds. + LP: #676027. + + -- Matthias Klose Wed, 17 Nov 2010 13:05:48 +0100 + +gcc-4.5 (4.5.1-11) experimental; urgency=low + + * Update to SVN 20101114 (r166728) from the gcc-4_5-branch. + - Fix PR fortran/45742. + * Don't hardcode debian/patches when referencing patches. Closes: #600502. + + -- Matthias Klose Sun, 14 Nov 2010 08:36:27 +0100 + +gcc-4.5 (4.5.1-10ubuntu1) natty; urgency=low + + * On linux targets pass --as-needed by default to the linker. + * Update the Linaro support to the 4.5 2010.11 release. + + -- Matthias Klose Fri, 12 Nov 2010 19:11:58 +0100 + +gcc-4.5 (4.5.1-10) experimental; urgency=low + + * Update to SVN 20101112 (r166653) from the gcc-4_5-branch. + - Fix PR rtl-optimization/44691, PR tree-optimization/46355, + PR tree-optimization/46177, PR c/44772, PR tree-optimization/46099, + PR middle-end/43690, PR tree-optimization/46165, PR middle-end/46419, + PR tree-optimization/46107, PR tree-optimization/45314, PR debug/45939, + PR rtl-optimization/46237, PR middle-end/44569, PR middle-end/44569, + PR tree-optimization/45902, PR target/46153, PR rtl-optimization/46226, + PR tree-optimization/46167, PR target/46098, PR target/45946, + PR fortran/42169, PR middle-end/46019, PR c/45969, PR c++/45894, + PR c++/46160, PR c++/45983, PR fortran/46152, PR fortran/46140, + PR libstdc++/45999, PR libgfortran/46373, PR libgfortran/46010, + PR fortran/46007, PR c++/46024. + * Update the Linaro support to the 4.5 2010.11 release. + * Update gcc-4.5 source dependencies. Closes: #600503. + * ARM: Fix Thumb-1 reload ICE with nested functions (Julian Brown), + taken from the trunk. + * Fix earlyclobbers on some arm.md DImode shifts (may miscompile "x >> 1"), + taken from the trunk. Closes: #600888. + + -- Matthias Klose Fri, 12 Nov 2010 18:34:47 +0100 + +gcc-4.5 (4.5.1-9ubuntu1) natty; urgency=low + + * Merge with Debian; remaining changes: + - Build from the upstream tarball, including GFDL documents. + - Build from the Linaro 4.5-2010.08-1 release on amd64, armel, i386 + and powerpc. + + -- Matthias Klose Thu, 14 Oct 2010 19:19:02 +0200 + +gcc-4.5 (4.5.1-9) experimental; urgency=low + + * Update to SVN 20101014 (r165474) from the gcc-4_5-branch. + - Fix PR target/45820, PR tree-optimization/45854, PR target/45843, + PR target/43764, PR rtl-optimization/43358, PR bootstrap/44621, + PR libffi/45677, PR middle-end/45869, PR middle-end/45569, + PR tree-optimization/45752, PR fortran/45748, PR libstdc++/45403, + PR libstdc++/45924, PR libfortran/45710, PR bootstrap/44455, + PR java/43839, PR debug/45656, PR debug/44832, PR libstdc++/45711, + PR tree-optimization/45982. + + [ Matthias Klose ] + * Update the Linaro support to the 4.5 2010.10 release. + * Just try to build java on mips/mipsel (was disabled in 4.5.0-9, when + java was built from the same source package). Addresses: #599976. + * Remove the gpc packaging support. + * Fix libmudflap.so symlink. Addresses: #600161. + * Fix pch test failures with heap randomization on armel (PR pch/45979). + + [ Kees Cook ] + * Don't enable -fstack-protector with -ffreestanding. + + -- Matthias Klose Thu, 14 Oct 2010 19:17:41 +0200 + +gcc-4.5 (4.5.1-8ubuntu2) natty; urgency=low + + * Update to SVN 20101011 (r165313) from the gcc-4_5-branch. + - Fix PR target/45820, PR tree-optimization/45854, PR target/45843, + PR target/43764, PR rtl-optimization/43358, PR bootstrap/44621, + PR libffi/45677, PR middle-end/45869, PR middle-end/45569, + PR tree-optimization/45752, PR fortran/45748, PR libstdc++/45403, + PR libstdc++/45924, PR libfortran/45710, PR bootstrap/44455, + PR java/43839, PR debug/45656. + * Update the Linaro support to the 4.5 2010.10 release. + + -- Matthias Klose Mon, 11 Oct 2010 21:20:00 +0200 + +gcc-4.5 (4.5.1-8) experimental; urgency=low + + * Update to SVN 20100925 (r164618) from the gcc-4_5-branch. + - Fix PR middle-end/44763, PR java/44095, PR target/35664, + PR rtl-optimization/41085, PR rtl-optimization/45051, + PR target/45694, PR middle-end/45678, PR middle-end/45678, + PR middle-end/45704, PR rtl-optimization/45728, PR libfortran/45532, + PR rtl-optimization/45695, PR rtl-optimization/42775, PR target/45726, + PR tree-optimization/45623, PR tree-optimization/45709, PR debug/43628, + PR tree-optimization/45709, PR rtl-optimization/45593, PR fortran/45081, + * Find 32bit system libraries on sparc64, s390x. + * Remove README.Debian from the source package to avoid confusion for + readers of the packaging. + * Don't include info files and man pages in hppa64 and spu builds. + Closes: #597435. + * Apply proposed patch for PR mudflap/24619 (instrumentation of dlopen) + (Brian M. Carlson) Closes: #507514. + + -- Matthias Klose Sat, 25 Sep 2010 14:11:39 +0200 + +gcc-4.5 (4.5.1-7ubuntu1) maverick; urgency=low + + * Build from the Linaro 4.5 2010.09 release. + * gcc-4.5: Include the Linaro changelog. + + * The package version identifier specified with --with-pkg-version, e.g. + gcc-4.5 (Ubuntu/Linaro 4.5.1-7ubuntu1) 4.5.1 + changes with every upload of this package and should not be used + to define any ABI or API version in other package builds. + + -- Matthias Klose Tue, 14 Sep 2010 14:37:42 +0200 + +gcc-4.5 (4.5.1-7) experimental; urgency=low + + * Update to SVN 20100914 (r164279) from the gcc-4_5-branch. + - Fix PR target/40959, PR middle-end/45567, PR debug/45660, + PR rtl-optimization/41087, PR rtl-optimization/44919, PR target/36502, + PR target/42313, PR target/44651. + * Add support to build from the Linaro 4.5 2010.09 release (disabled by + default). + * gcc-4.5-plugin-dev: Install config/arm/arm-cores.def. + * Remove non-existing URL's in README.c++ (Osamu Aoki). Closes: #596406. + * Don't provide c++abi2-dev for g++ cross builds. + * Don't pass -mimplicit-it=thumb if -mthumb to as on ARM, rejected upstream. + + -- Matthias Klose Tue, 14 Sep 2010 14:23:35 +0200 + +gcc-4.5 (4.5.1-6ubuntu1) maverick; urgency=low + + * Merge with Debian; remaining changes: + - Build from the upstream tarball, including GFDL documents. + - Build from the Linaro 4.5-2010.08-1 release on amd64, armel, i386 + and powerpc. + + -- Matthias Klose Sat, 11 Sep 2010 13:17:13 +0200 + +gcc-4.5 (4.5.1-6) experimental; urgency=low + + * Update to SVN 20100909 (r164132) from the gcc-4_5-branch. + - Fix PR middle-end/45312, PR bootstrap/43847, PR middle-end/44554, + PR middle-end/40386, PR other/45443, PR c++/45200, PR c++/45293, + PR c++/45558, PR fortran/45595, PR fortran/45530, PR fortran/45489, + PR fortran/45019, PR libstdc++/45398. + + [ Matthias Klose ] + * Tighten binutils dependencies to 2.20.1-14. + * gcc-4.5-plugin-dev: Install config/arm/arm-cores.def. + + [ Marcin Juszkiewicz ] + * Fix the gcc-4.5-plugin-dev package name for cross builds. LP: #631474. + * Build the gcc-4.5-plugin-dev for stage1 cross builds. + * Fix priorities and sections for some cross packages. + + [ Al Viro ] + * Fix installation of libgcc_s.so as a linker script for biarch builds. + + [ Kees Cook ] + * Push glibc stack traces into stderr when building the package. + * debian/patches/gcc-default-ssp.patch: Lower ssp-buffer-size to 4. + + -- Matthias Klose Fri, 10 Sep 2010 21:25:37 +0200 + +gcc-4.5 (4.5.1-5ubuntu1) maverick; urgency=low + + * Merge with Debian; remaining changes: + - Build from the upstream tarball, including GFDL documents. + - Build from the Linaro 4.5-2010.08-1 release on amd64, armel, i386 + and powerpc. + + -- Matthias Klose Sat, 04 Sep 2010 13:56:39 +0200 + +gcc-4.5 (4.5.1-5) experimental; urgency=low + + * Always add dependencies on multilib library packages in *-multilib + packages. + * Fix installation of libgcc_s.so on architectures when libgcc_s.so is + a linker script, not a symlink (Steve Langasek). Closes: #595474. + + -- Matthias Klose Sat, 04 Sep 2010 12:41:40 +0200 + +gcc-4.5 (4.5.1-4ubuntu1) maverick; urgency=low + + * Merge with Debian; remaining changes: + - Build from the upstream tarball, including GFDL documents. + - Build from the Linaro 4.5-2010.08-1 release on amd64, armel, i386 + and powerpc. + + -- Matthias Klose Sat, 04 Sep 2010 01:53:21 +0200 + +gcc-4.5 (4.5.1-4) experimental; urgency=low + + * Update to SVN 20100902 (r163775) from the gcc-4_5-branch. + - Fix PR target/45070, PR middle-end/45458, PR rtl-optimization/45353, + PR middle-end/45423, PR c/45079, PR tree-optimization/45393, + PR c++/44991. + + [ Matthias Klose ] + * Install config/vxworks-dummy.h in the gcc-4.5-plugin-dev package + on armel, mipsel and sparc64 too. + * Cleanup packaging files in gcc-source package. + * [ARM] Provide __builtin_expect() hints in linux-atomic.c (backport). + + [ Al Viro ] + * Fix builds with disabled biarch library packages. + * New variables {usr_lib,gcc_lib_dir,libgcc_dir}{,32,64,n32}, and switch + to using them in rules.d/*; as the result, most of the explicit pathnames + in there are gone _and_ we get uniformity across different flavours. + * New variables {usr_lib,gcc_lib_dir,libgcc_dir}{,32,64,n32}, and switch + to using them in rules.d/*; as the result, most of the explicit pathnames + in there are gone _and_ we get uniformity across different flavours. + * Merge bi-/tri-arch stuff in binary-gcc.mk. + * Merge rules for libgcc biarch variants. + * Merge rules for libstdc++ biarch variants. Fix n32 variant of + libstdc++-dbg removing _pic.a from the wrong place. + * Merge libgfortran rules. + * Merge rules for cxx-multi and objc-multi packages. + * Enable gcc-hppa64 in cross-gcc-to-hppa build. + + [ Marcin Juszkiewicz ] + * Create libgcc1 and gcc-*-base packages for stage2 cross builds. + LP: #628855. + + -- Matthias Klose Wed, 01 Sep 2010 14:16:08 +0200 + +gcc-4.5 (4.5.1-3) experimental; urgency=low + + * Update to SVN 20100829 (r163627) from the gcc-4_5-branch. + - Fix PR target/45327, PR middle-end/45292, PR fortran/45344, + PR target/41484, PR rtl-optimization/44858, PR rtl-optimization/45400, + PR tree-optimization/45260, PR c++/45315. + + [ Matthias Klose ] + * Don't run the libstdc++ testsuite on armel on the buildds. + * Integrate and extend bi/tri-arch cross builds patches. + * Fix dependencies for mips* triarch library packages depend on *both* lib64* + and libn32* packages. Closes: #594540. + * Tighten binutils dependencies to 2.20.1-13. + * Update LAST_UPDATED file when applying upstream updates. + + [ Al Viro ] + * Bi/tri-arch cross builds patches. + * Fix installation paths in bi/tri-arch libobjc and libmudflap packages. + * Merge rules for all flavours of libgomp, libmudflap, libobjc. + * Crossbuild fix for lib32gomp (use $(PFL)/lib32 instead of $(lib32)). + * gcc-4.5: libgcc_s.so.1 symlink creation on cross-builds. + * Enable gcc-multilib for cross-builds and fix what needs fixing. + * Enable g++-multilib for cross-builds, fix pathnames. + * Enable gobjc/gobjc++ multilib for cross-builds, fixes. + * Enable gfortran multilib for cross-builds, fix paths. + * Multilib dependency fixes for cross-builds. + + -- Matthias Klose Sun, 29 Aug 2010 18:24:37 +0200 + +gcc-4.5 (4.5.1-2ubuntu2) maverick; urgency=low + + * Don't run the libstdc++ testsuite on armel on the buildds. + + -- Matthias Klose Mon, 23 Aug 2010 03:36:28 +0200 + +gcc-4.5 (4.5.1-2ubuntu1) maverick; urgency=low + + * Merge with Debian; remaining changes: + - Build from the upstream tarball, including GFDL documents. + - Build from the Linaro 4.5-2010.08-1 release on amd64, armel, i386 + and powerpc. + + -- Matthias Klose Wed, 18 Aug 2010 07:08:34 +0200 + +gcc-4.5 (4.5.1-2) experimental; urgency=low + + * Update to SVN 20100818 (r163323) from the gcc-4_5-branch. + - Fix PR target/41089, PR tree-optimization/44914, PR c++/45112, + PR fortran/44929, PR middle-end/45262, PR debug/45259, PR debug/45055, + PR target/44805, PR middle-end/45034, PR tree-optimization/45109, + PR target/44942, PR fortran/31588, PR fortran/43954, PR fortran/44660, + PR fortran/42051, PR fortran/44064, PR fortran/45151, PR libstdc++/44963, + PR tree-optimization/45241, PR middle-end/44632 (closes: #585925), + PR libstdc++/45283, PR target/45296. + + [ Matthias Klose ] + * Allow overwriting of the PF macro used in the build from the environment + (Jim Heck). Closes: #588381. + * Fix libc-dbg build dependency for java enabled builds. Addresses: #591424. + * gcj: Align data in .rodata.jutf8.* sections, patch taken from the trunk. + * Configure with --enable-checking+release. LP: #612822. + * Add the complete packaging to the -source package. LP: #608650. + * Drop the gcc-ix86-asm-generic32.diff patch. + * Tighten (build-) dependency on cloog-ppl (>= 0.15.9-2). + * Apply proposed patch for PR middle-end/45292. + * Re-enable running the libstdc++ testsuite on armel and ia64 on the buildds. + + [ Steve Langasek ] + * s,/lib/,/$(libdir)/, throughout debian/rules*; a no-op in the current + case, but required for us to find the libraries when building for + multiarch + * Don't append multiarch paths to any multilib paths except for the default; + our biarch (multilib) builds need to remain independent of multiarch in + the near term, so we want to make sure we can find /usr/lib32 without + /usr/lib/i486-linux-gnu being available. + * debian/control.m4, debian/rules.conf: conditionally set packages to be + Multi-Arch: yes when MULTIARCH is defined. + + [ Marcin Juszkiewicz ] + * Allow building intermediate stages for cross builds. LP: #603497. + + -- Matthias Klose Wed, 18 Aug 2010 07:00:12 +0200 + +gcc-4.5 (4.5.1-1ubuntu2) maverick; urgency=low + + * Build from the Linaro 4.5-2010.08-1 release on amd64, armel, i386 + and powerpc. + * Update to SVN 20100813 (r163226) from the gcc-4_5-branch. + - Fix PR target/41089, PR tree-optimization/44914, PR c++/45112, + PR fortran/44929, PR middle-end/45262, PR debug/45259, PR debug/45055, + PR target/44805, PR middle-end/45034, PR tree-optimization/45109, + PR boehm-gc/34544, PR target/44942, PR fortran/31588, PR fortran/43954, + PR fortran/44660, PR fortran/42051, PR fortran/44064, PR fortran/45151, + PR libstdc++/44963. + + [ Matthias Klose ] + * Allow overwriting of the PF macro used in the build from the environment + (Jim Heck). Closes: #588381. + * Fix libc-dbg build dependency for java enabled builds. Addresses: #591424. + * gcj: Align data in .rodata.jutf8.* sections, patch taken from the trunk. + * Configure with --enable-checking+release. LP: #612822. + * Add the complete packaging to the -source package. LP: #608650. + * Drop the gcc-ix86-asm-generic32.diff patch. + + [ Steve Langasek ] + * s,/lib/,/$(libdir)/, throughout debian/rules*; a no-op in the current + case, but required for us to find the libraries when building for + multiarch + * Don't append multiarch paths to any multilib paths except for the default; + our biarch (multilib) builds need to remain independent of multiarch in + the near term, so we want to make sure we can find /usr/lib32 without + /usr/lib/i486-linux-gnu being available. + * debian/control.m4, debian/rules.conf: conditionally set packages to be + Multi-Arch: yes when MULTIARCH is defined. + + [ Marcin Juszkiewicz ] + * Allow building intermediate stages for cross builds. LP: #603497. + + -- Matthias Klose Sat, 14 Aug 2010 18:10:45 +0200 + +gcc-4.5 (4.5.1-1ubuntu1) maverick; urgency=low + + * Merge with Debian. + + -- Matthias Klose Sat, 31 Jul 2010 16:46:14 +0200 + +gcc-4.5 (4.5.1-1) experimental; urgency=low + + * GCC-4.5.1 release. + * Update to SVN 20100731 (r162781) from the gcc-4_5-branch. + - Fix PR tree-optimization/45052, PR target/43698. + * Apply proposed fixes for PR c++/45112, PR c/45079. + * Install config/vxworks-dummy.h in the gcc-4.5-plugin-dev package + on armel, mips, mipsel, sh4, sparc, sparc64. Closes: #590054. + * Link executables statically when `static' is passed in DEB_BUILD_OPTIONS + (Jim Heck). Closes: #590102. + * Stop building java packages from the gcc-4.5 source package. + + -- Matthias Klose Sat, 31 Jul 2010 16:30:20 +0200 + +gcc-4.5 (4.5.0-10) experimental; urgency=low + + * Update to SVN 20100725 (r162508) from the gcc-4_5-branch. + - Fix PR tree-optimization/45047, PR c++/43016, PR c++/45008. + * Disable building gcj/libjava on mips/mipsel (fails to link libgcj). + * Update libstdc++6 symbols files. + + -- Matthias Klose Sun, 25 Jul 2010 16:39:11 +0200 + +gcc-4.5 (4.5.0-9) experimental; urgency=low + + * Update to SVN 20100723 (r162448) from the gcc-4_5-branch (post + GCC-4.5.1 release candidate 1). + - Fix PR debug/45015, PR target/44942, PR tree-optimization/44900, + PR tree-optimization/44977, PR c++/44996, PR fortran/44929, + PR fortran/30668, PR fortran/31346, PR fortran/34260, + PR fortran/40011. + + [ Marcin Juszkiewicz ] + * Fix dependencies on cross library packages. + * Copy all debian/rules* files to the -source package. + + [ Matthias Klose ] + * Fix versioned build dependency on gcc-4.x-source package for cross builds. + LP: #609060. + * Set Vcs attributes in control file. + + -- Matthias Klose Fri, 23 Jul 2010 13:08:07 +0200 + +gcc-4.5 (4.5.0-8ubuntu1) maverick; urgency=low + + * Merge with Debian. + + -- Matthias Klose Sun, 18 Jul 2010 11:07:02 +0200 + +gcc-4.5 (4.5.0-8) experimental; urgency=low + + * Update to SVN 20100718 (r161892) from the gcc-4_5-branch. + - Fixes: PR target/44531, PR bootstrap/44820, PR target/44597, + PR target/44705, PR middle-end/44777, PR debug/44694, PR c++/44039, + PR tree-optimization/43801, PR target/44575, PR debug/44104, + PR middle-end/44671, PR middle-end/44686, PR tree-optimization/44357, + PR debug/44694, PR middle-end/43866, PR debug/42278, PR c++/44059, + PR tree-optimization/43905, PR middle-end/44133, PR tree-optimize/44063, + PR tree-optimization/44683, PR rtl-optimization/43332, PR debug/44610, + PR middle-end/44684, PR tree-optimization/44393, PR middle-end/44674, + PR c++/44628, PR c++/44587, PR fortran/44582, PR fortran/43841, + PR fortran/43843, PR libstdc++/44708, PR tree-optimization/44886, + PR target/43888, PR tree-optimization/44284, PR middle-end/44828, + PR middle-end/41355, PR c++/44703, PR ada/43731, PR fortran/44773, + PR fortran/44847. + + [ Marcin Juszkiewicz ] + * debian/rules2: Merge rules.d includes. + * Properly -name -dbg packages for cross builds. + * Various cross build fixes. + * Build libmudflap packages for cross builds. + * Fix generation of maintainer scripts for cross packages. + * Build a gcc-base package for cross builds. + + [ Kees Cook ] + * Fix additional libstdc++ testsuite failures for hardening defaults. + + [ Samuel Thibault ] + * Update hurd patch for 4.5, fixing build failure. Closes: #584819. + + [ Matthias Klose ] + * gcc-arm-implicit-it.diff: Only pass -mimplicit-it=thumb when in + thumb mode (Andrew Stubbs). + + -- Matthias Klose Sun, 18 Jul 2010 10:53:51 +0200 + +gcc-4.5 (4.5.0-7ubuntu1) maverick; urgency=low + + * Merge with Debian. + + -- Matthias Klose Fri, 25 Jun 2010 16:03:24 +0200 + +gcc-4.5 (4.5.0-7) experimental; urgency=low + + * Update to SVN 20100625 (r161383) from the gcc-4_5-branch. + - Fixes: PR bootstrap/44426, PR target/44546, PR target/44261, + PR target/43740, PR libstdc++/44630 (closes: #577458), + PR c++/44627 (LP: #503668), PR target/39690, PR target/44615, + PR fortran/44556, PR c/44555. + - Update libstdc++'s pretty printer for python2.6. Closes: #585202. + + [ Matthias Klose ] + * Fix libstdc++ symbols files for powerpc and sparc. + * Add maintainer scripts for cross packages. + + [ Samuel Thibault ] + * Update hurd patch for 4.5, fixing build failure. Closes: #584454, + #584819. + + [ Marcin Juszkiewicz ] + * Merge the rules.d/binary-*-cross.mk files into rules.d/binary-*.mk. + + -- Matthias Klose Fri, 25 Jun 2010 15:57:38 +0200 + +gcc-4.5 (4.5.0-6ubuntu2) maverick; urgency=low + + * Fix typo in ix86 libgcc1 symbols files. + + -- Matthias Klose Fri, 18 Jun 2010 01:07:15 +0200 + +gcc-4.5 (4.5.0-6ubuntu1) maverick; urgency=low + + * Merge with Debian. + + -- Matthias Klose Thu, 17 Jun 2010 15:50:52 +0200 + +gcc-4.5 (4.5.0-6) experimental; urgency=low + + [ Matthias Klose ] + + * Update to SVN 20100617 (r161901) from the gcc-4_5-branch. Fixes: + PR target/44169, PR bootstrap/43170, PR objc/35996, PR objc++/32052, + PR objc++/23716, PR lto/44464, PR rtl-optimization/42461, PR fortran/44536, + PR tree-optimization/44258, PR tree-optimization/44423, PR target/44534, + PR bootstrap/44426, PR tree-optimization/44508, PR tree-optimization/44507, + PR lto/42776, PR target/44481, PR debug/41371, PR bootstrap/37304, + PR target/44067, PR debug/41371, PR debug/41371, PR target/44075, + PR c++/44366, PR c++/44401, PR fortran/44347, PR fortran/44430, + PR lto/42776, PR libstdc++/44487, PR other/43838, PR libgcj/44216. + * debian/patches/cross-fixes.diff: Update for 4.5 (Marcin Juszkiewicz). + * debian/patches/libstdc++-pic.diff: Fix installation for cross builds. + * Fix PR bootstrap/43847, --enable-plugin for cross builds. + * Export long double versions of "C" math library for arm-linux-gnueabi, + m68k-linux-gnu (ColdFire), mips*-linux-gnu (o32 ABI), sh*-linux-gnu + (not 32 bit). Merge the libstdc++-*-ldbl-compat.diff patches. + * Merge binary-libgcc.mk packaging changes into binary-libgcc-cross.mk + (Loic Minier). + * Update libgcc and libstdc++ symbols files. + + [ Aurelien Jarno ] + + * libstdc++-mips-ldbl-compat.diff: On MIPS provide the long double + versions of "C" math functions in libstdc++ as we need to keep the + ABI. Closes: #584610. + + -- Matthias Klose Thu, 17 Jun 2010 14:56:14 +0200 + +gcc-4.5 (4.5.0-5ubuntu1) maverick; urgency=low + + * Update to SVN 20100603 (r160230) from the gcc-4_5-branch. Fixes: + PR target/44169. + * debian/patches/cross-fixes.diff: Update for 4.5 (Marcin Juszkiewicz). + + -- Matthias Klose Thu, 03 Jun 2010 19:38:06 +0200 + +gcc-4.5 (4.5.0-5) experimental; urgency=low + + * Update to SVN 20100602 (r160097) from the gcc-4_5-branch. Fixes: + PR target/44338, PR middle-end/44337, PR tree-optimization/44182, + PR target/44161, PR c++/44358, PR fortran/44360, PR lto/44385. + * Fix PR target/44261, taken from the trunk. Closes: #582787. + * Fix passing the expanded -iplugindir option. + * Disable broken profiled bootstrap on alpha. + * On ix86, pass -mtune=generic32 in 32bit mode to the assembler, when + configured for i586-linux-gnu or i686-linux-gnu. + + -- Matthias Klose Thu, 03 Jun 2010 00:44:37 +0200 + +gcc-4.5 (4.5.0-4ubuntu1) maverick; urgency=low + + * Merge with Debian. + + -- Matthias Klose Thu, 27 May 2010 18:05:57 +0200 + +gcc-4.5 (4.5.0-4) experimental; urgency=low + + * Update to SVN 20100527 (r159910) from the gcc-4_5-branch. Fixes: + PR rtl-optimization/44164, PR middle-end/44069, PR target/44199, + PR lto/44196, PR target/43733, PR target/44245, PR target/43869, + PR debug/44223, PR tree-optimization/44038, PR tree-optimization/43949, + PR debug/44205, PR debug/44178, PR bootstrap/43870, PR target/44202, + PR target/44074, PR lto/43455, PR lto/42653, PR lto/42425, PR lto/43080, + PR lto/43946, PR c++/43382, PR c++/41510, PR c++/44193, PR c++/44157, + PR c++/44158, PR lto/44256, PR libstdc++/44190. + + [ Matthias Klose ] + + * Enable multilibs again on powerpcspe. Closes: #579780. + * Fix setting CC for REVERSE_CROSS build (host == target,host != build). + Closes: #579779. + * Fix setting biarch_cpu macro. + * Don't bother with un-normalized paths in .la files, just remove them. + * debian/locale-gen: Update locales needed for the libstdc++-v3 testsuite. + * If libstdc++6 is built from newer gcc-4.x source, run the libstdc++-v3 + testsuite against the installed lib too. + + [ Aurelien Jarno ] + + * Fix $(distrelease) on non-official archives. Fix powerpcspe, sh4 and + sparc64 builds. + + -- Matthias Klose Thu, 27 May 2010 17:52:15 +0200 + +gcc-4.5 (4.5.0-3ubuntu1) maverick; urgency=low + + * Target i686 instead of i486 on i386. + + -- Matthias Klose Wed, 19 May 2010 11:05:44 +0200 + +gcc-4.5 (4.5.0-3) experimental; urgency=low + + * Update to SVN 20100519 (r159556) from the gcc-4_5-branch. Fixes: + PR c++/43704, PR fortran/43339, PR middle-end/43337, PR target/43635, + PR tree-optimization/43783, PR tree-optimization/43796, PR middle-end/43570, + PR libgomp/43706, PR libgomp/43569, PR middle-end/43835, PR c/43893, + PR tree-optimization/43572, PR tree-optimization/43845, PR libgcj/40860, + PR target/43744, PR debug/43370, PR c++/43880, PR middle-end/43671, + PR debug/43972, PR target/43921, PR c++/38064, PR c++/43953, + PR fortran/43985, PR fortran/43592, PR fortran/40539, PR c++/43787, + PR middle-end/44085, PR middle-end/44071, PR middle-end/43812, + PR debug/44028, PR rtl-optimization/44012, PR target/44046, + PR documentation/44016, PR fortran/44036, PR fortran/40728, + PR libstdc++/44014, PR lto/44184, PR bootstrap/42347, PR middle-end/44102, + PR c++/44127, PR debug/44136, PR target/44088, PR tree-optimization/44124, + PR fortran/43591, PR fortran/44135, PR libstdc++/43259. + + [ Matthias Klose ] + * Revert gcj-arm-no-merge-exidx-entries patch, fixed by PR libgcj/40860. + * Don't run the libstdc++-v3 testsuite on the ia64 buildds. Timeouts. + * Backport two libjava fixes from the trunk to run josm with gcj. + * Ubuntu only: + - Pass --hash-style=gnu instead of --hash-style=both to the linker. + * Preliminary architecture port for powerpcspe (Kyle Moffett). + Closes: #579780. + * Update configury to be able to target i686 instead of i486 on i386. + + [ Aurelien Jarno] + * Don't link with --hash-style=both on mips/mipsel as GNU hash is not + compatible with the MIPS ABI. + * Default to -mplt on mips(el), -march=mips2 and -mtune=mips32 on 32-bit + mips(el), -march=mips3 and -mtune=mips64 on 64-bit mips(el). + + -- Matthias Klose Wed, 19 May 2010 09:48:20 +0200 + +gcc-4.5 (4.5.0-2ubuntu3) maverick; urgency=low + + * Update to SVN 20100514 (r159388) from the gcc-4_5-branch. Fixes: + PR target/43744, PR debug/43370, PR c++/43880, PR middle-end/43671, + PR debug/43972, PR target/43921, PR c++/38064, PR c++/43953, + PR fortran/43985, PR fortran/43592, PR fortran/40539, PR c++/43787, + PR middle-end/44085, PR middle-end/44071, PR middle-end/43812, + PR debug/44028, PR rtl-optimization/44012, PR target/44046, + PR documentation/44016, PR fortran/44036, PR fortran/40728, + PR libstdc++/44014. + * Configure --with-arch-32=i686. + * Pass --hash-style=gnu instead of --hash-style=both to the linker. + + -- Matthias Klose Fri, 14 May 2010 10:13:59 +0200 + +gcc-4.5 (4.5.0-2ubuntu2) maverick; urgency=low + + * gcc-plugindir-doc.diff: Fix mismatched } to fix FTBFS. + + -- Martin Pitt Tue, 04 May 2010 09:40:41 +0000 + +gcc-4.5 (4.5.0-2ubuntu1) maverick; urgency=low + + * Update to SVN 20100506 (r158683) from the gcc-4_5-branch. Fixes: + PR c++/43704, PR fortran/43339, PR middle-end/43337, PR target/43635, + PR tree-optimization/43783, PR tree-optimization/43796, PR middle-end/43570, + PR libgomp/43706, PR libgomp/43569, PR middle-end/43835, PR c/43893, + PR tree-optimization/43572, PR tree-optimization/43845, PR libgcj/40860. + + [ Matthias Klose ] + * Revert gcj-arm-no-merge-exidx-entries patch, fixed by PR libgcj/40860. + * Don't run the libstdc++-v3 testsuite on the ia64 buildds. Timeouts. + * Backport two libjava fixes from the trunk to run josm with gcj. + + -- Matthias Klose Thu, 06 May 2010 14:54:38 +0200 + +gcc-4.5 (4.5.0-2) experimental; urgency=low + + * Update to SVN 20100419 from the gcc-4_5-branch. + - Fix PR tree-optimization/43627, c++/43641, PR c++/43621, PR c++/43611, + PR fortran/31538, PR fortran/30073, PR target/43662, + PR tree-optimization/43572, PR tree-optimization/43771. + * Install the linker plugin. + * Search the linker plugin as a readable, not an executable file. + * Link with --hash-style=both on mips/mipsel. + * On mips, pass -mfix-loongson2f-nop to as, if -mno-fix-loongson2f-nop + is not passed. + * Sequel to PR40521, fix -g to generate .eh_frame on ARM. + * On ARM, let gcj pass --no-merge-exidx-entries to the linker. + * Build-depend/depend on binutils snapshot. + * Update NEWS.html and NEWS.gcc. + + -- Matthias Klose Mon, 19 Apr 2010 15:22:55 +0200 + +gcc-4.5 (4.5.0-1) experimental; urgency=low + + * GCC 4.5.0 release. + * Always apply biarch patches. + * Build the lto-linker plugin again. Closes: #575448. + * Run the libstdc++v3 testsuite on armel again. + * Fix --enable-libstdcxx-time documentation, show configure result. + * On linux targets always pass --no-add-needed to the linker. + * Update the patch to search for plugins in a default plugin directory. + * Fix java installations in snapshot builds. + * Configure --with-plugin-ld=ld.gold. + * Linker selection: ld is used by default, to use the gold linker, + pass -fuse-linker-plugin (no other side effects if -flto/-fwhopr + is not passed). To force ld.bfd or ld.gold, pass -B/usr/lib/compat-ld + for ld.bfd or /usr/lib/gold-ld for ld.gold. + * Don't apply the gold-and-ld patch for now. + * Stop building the documentation for dfsg compliant builds. Closes: #571759. + + -- Matthias Klose Wed, 14 Apr 2010 13:29:20 +0200 + +gcc-4.5 (4.5-20100404-1) experimental; urgency=low + + * Update to SVN 20100404 from the trunk. + * Fix build failures building cross compilers configure --with-ld. + * lib32gcc1: Set priority to `extra'. + * Apply proposed patch to search for plugins in a default plugin directory. + * In snapshot builds, use for javac/ecj1 the jvm provided by the package. + * libstdc++-arm-ldbl-compat.diff: On ARM provide the long double versions + of "C" math functions in libstdc++; these are dropped when built + against glibc-2.11. + + -- Matthias Klose Sun, 04 Apr 2010 15:51:25 +0200 + +gcc-4.5 (4.5-20100321-1) experimental; urgency=low + + * Update to SVN 20100321 from the trunk. + * gcj-4.5-jre-headless: Stop providing java-virtual-machine. + * gcj-4.5-plugin-dev: Don't suggest mudflap packages. + * Apply proposed patch to enable both gold and ld in a single toolchain. + New option -fuse-ld=ld.bfd, -fuse-ld=gold. + + -- Matthias Klose Sun, 21 Mar 2010 11:45:48 +0100 + +gcc-4.5 (4.5-20100227-1) experimental; urgency=low + + * Update to SVN 20100227 from the trunk. + * Don't run the libstdc++-v3 testsuite on arm*-*-linux-gnueabi, when + defaulting to thumb mode (Timeouts on the Ubuntu buildd). + + -- Matthias Klose Sat, 27 Feb 2010 08:29:55 +0100 + +gcc-4.5 (4.5-20100222-1) experimental; urgency=low + + * Update to SVN 20100222 from the trunk. + - Install additional header files needed by plugins. Closes: #562881. + * gcc-4.5-plugin-dev: Should depend on libgmp3-dev. Closes: #566366. + * Update libstdc++6 symbols files. + + -- Matthias Klose Tue, 23 Feb 2010 02:16:22 +0100 + +gcc-4.5 (4.5-20100216-0ubuntu1~ppa1) lucid; urgency=low + + * Update to SVN 20100216 from the trunk. + * Don't call dh_makeshlibs with -V for shared libraries with + symbol files. + * Don't run the libstdc++-v3 testsuite in thumb mode on armel + to work around buildd timeout (see PR target/42509). + + -- Matthias Klose Wed, 17 Feb 2010 02:06:02 +0100 + +gcc-4.5 (4.5-20100204-1) experimental; urgency=low + + * Update to SVN 20100204 from the trunk. + + -- Matthias Klose Thu, 04 Feb 2010 19:44:19 +0100 + +gcc-4.5 (4.5-20100202-1) experimental; urgency=low + + * Update to SVN 20100202 from the trunk. + - gcc-stack_chk_fail-check.diff: Remove, applied upstream. + * Update libstdc++6 symbol files. + * Build gnat in snapshot builds on arm. + * Configure with --enable-checking=yes for snapshot builds, and for + 4.5 builds before the release. + * Temporary workaround: On arm-linux-gnueabi run the libstdc++v3 testsuite + with -Wno-abi. + * When building the hppa64 cross compiler, add $(builddir)/gcc to + LD_LIBRARY_PATH to find the just built libgcc6. Closes: #565862. + * On sh4-linux, use sh as java architecture name instead of sh4. + * On armel, build gnat-4.5 using gcc-snapshot. + * Revert the bump of the libgcc soversion on hppa (6 -> 4). + + -- Matthias Klose Tue, 02 Feb 2010 19:35:25 +0100 + +gcc-4.5 (4.5-20100107-1) experimental; urgency=low + + [ Matthias Klose ] + * Update to SVN 20100107 from the trunk. + * Revert the workaround for the alpha build (PR bootstrap/42511 is fixed). + * testsuite-hardening-format.diff: Add a fix for the libstdc++ testsuite. + * Build-depend again on autogen. + * Work around PR lto/41569 (installation bug when configured with + --enabled-gold). + * On armel run the testsuite both in arm and thumb mode, when the + distribution is supporthing tumb processors. + * Work around PR target/42509 (armel), not setting BOOT_CFLAGS, but + applying libcpp-arm-workaround.diff. + + [ Nobuhiro Iwamatsu ] + * Update gcc-multiarch patch for sh4. + + -- Matthias Klose Thu, 07 Jan 2010 16:34:57 +0100 + +gcc-4.5 (4.5-20100106-0ubuntu1) lucid; urgency=low + + * Update to SVN 20100106 from the trunk. + * gcj-4.5-jdk: Include /usr/lib/jvm-exports. + * Rename libgcc symbols file for hppa. + * On alpha and armel, set BOOT_CFLAGS to -g -O1 to work around bootstrap + failures (see PR target/42509 (armel) and PR bootstrap/42511 (alpha)). + * Base the source build-dependency on the package version instead of the + gcc version. + + -- Matthias Klose Wed, 06 Jan 2010 14:17:29 +0100 + +gcc-4.5 (4.5-20100103-1) experimental; urgency=low + + * Update to SVN 20100103 from the trunk. + + [ Samuel Thibault ] + * Update hurd patch for 4.5. Closes: #562802. + + [ Aurelien Jarno ] + * Remove patches/kbsd-gnu-ada.diff (merged upstream). + + [ Matthias Klose ] + * libgcj11: Move .so symlinks into gcj-4.5-jdk. Addresses: #563280. + * gcc-snapshot: On sparc64, use gcc-snapshot as bootstrap compiler. + * Don't use expect-tcl8.3 on hppa anymore. + * Merge gnat-4.4 changes back from 4.4.2-5. + * Bump libgcc soversion on hppa (4 -> 6). + * Default to v9a (ultrasparc) on sparc*-linux. + + -- Matthias Klose Sun, 03 Jan 2010 17:25:27 +0100 + +gcc-4.5 (4.5-20091226-1) experimental; urgency=low + + * Update to SVN 20091226 from the trunk. + * Fix powerpc spu installation. + * Enable multiarch for sh4. + * Fix libffi multilib test runs. + * Configure the hppa -> hppa64 cross compiler --with-system-zlib. + * gcc-4.5-hppa64: Don't ship info dir file. + * lib32stdc++6{,-dbg}: Add dependency on 32bit glibc. + + -- Matthias Klose Sat, 26 Dec 2009 15:38:23 +0100 + +gcc-4.5 (4.5-20091223-1) experimental; urgency=low + + * Update to SVN 20091223 from the trunk. + + [ Matthias Klose ] + * Update hardening patches for 4.5. + * Don't call install-info directly, depend on dpkg | install-info instead. + * Add conflicts with packages built from GCC 4.4 sources. + * On ARM, pass --hash-style=both to ld. + * Update libgfortran3 symbols file. + * Update libstdc++6 symbols file. + + [ Arthur Loiret ] + * debian/rules.conf (gen_no_archs): Handle multiple arm ports. + + -- Matthias Klose Wed, 23 Dec 2009 18:02:24 +0100 + +gcc-4.5 (4.5-20091220-1) experimental; urgency=low + + * Update to SVN 20091220 from the trunk. + - Remove patches applied upstream: arm-boehm-gc-locks.diff, + arm-gcc-gcse.diff, deb-protoize.diff, gcc-arm-thumb2-sched.diff, + gcc-atom-doc.diff, gcc-atom.diff, gcc-build-id.diff, + gcc-unwind-debug-hook.diff, gcj-use-atomic-builtins-doc.diff, + gcj-use-atomic-builtins.diff, libjava-atomic-builtins-eabi.diff, + libjava-nobiarch-check-snap.diff, lp432222.diff, pr25509-doc.diff, + pr25509.diff, pr39429.diff, pr40133.diff, pr40134.diff, rev146451.diff, + s390-biarch-snap.diff, sh4-scheduling.diff, sh4_atomic_update.diff. + - Update patches: gcc-multiarch.diff, gcc-textdomain.diff, + libjava-nobiarch-check.diff, libjava-subdir.diff, libstdc++-doclink.diff, + libstdc++-man-3cxx.diff, libstdc++-pic.diff, note-gnu-stack.diff, + rename-info-files.diff, s390-biarch.diff. + * Stop building the protoize package, removed from the GCC 4.5 sources. + * gcc-4.5: Install lto1, lto-wrapper, and new header files for intrinsics. + * libstdc++6-4.5-dbg: Install the python files for use with gdb. + * Build java packages from the gcc-4.5 source package. + + -- Matthias Klose Sun, 20 Dec 2009 10:56:56 +0100 + +gcc-4.4 (4.4.2-6) unstable; urgency=low + + * Update to SVN 20091220 from the gcc-4_4-branch (r155367). + Fix PR c++/42387, PR c++/41183. + + [ Matthias Klose ] + * Apply svn-doc-updates.diff for non DFSG builds. + * gcc-snapshot: + - Remove patches integrated upstream: pr40133.diff. Closes: #561550. + + [ Nobuhiro Iwamatsu ] + * Backport linux atomic ops changes for sh4 from the trunk. Closes: #561550. + * Backport from trunk: [SH] Not run scheduling before reload as default. + Closes: #561429. + + [ Arthur Loiret ] + * Apply spu patches independently of the hardening patches; fix build + failure on powerpc. + + -- Matthias Klose Sun, 20 Dec 2009 10:20:19 +0100 + +gcc-4.4 (4.4.2-5) unstable; urgency=low + + * Update to SVN 20091212 from the gcc-4_4-branch (r155122). + Revert the fix for PR libstdc++/42261, fix PR fortran/42268, + PR target/42263, PR target/42263, PR target/41196, PR target/41939, + PR rtl-optimization/41574. + + [ Matthias Klose ] + * Regenerate svn-updates.diff. + * Disable biarch testsuite runs for libffi (broken and unused). + * Support xz compression of source tarballs. + * Fix typo in PR libstdc++/40133 to do the link tests. + * gcc-snapshot: + - Remove patches integrated upstream: pr40134-snap.diff. + - Update s390-biarch.diff for trunk. + + [ Aurelien Jarno ] + * Add sparc64 support: disable multilib and install the libraries + in /lib. + + -- Matthias Klose Sun, 13 Dec 2009 10:28:19 +0100 + +gcc-4.4 (4.4.2-4) unstable; urgency=low + + * Update to SVN 20091210 from the gcc-4_4-branch (r155122), Fixes: + PR target/42165, PR target/42113, PR libgfortran/42090, + PR middle-end/42049, PR c++/42234, PR fortran/41278, PR libstdc++/42261, + PR libstdc++/42273 PR java/41991. + + [ Matthias Klose ] + * gcc-arm-thumb2-sched.diff: Don't restrict reloads to LO_REGS for Thumb-2. + * PR target/40134: Don't redefine LIB_SPEC on hppa. + * PR target/42263, fix wrong code bugs in SMP support on ARM, backport from + the trunk. + * Pass -mimplicit-it=thumb to as by default on ARM, when configured + --with-mode=thumb. + * Fix boehm-gc build on ARM --with-mode=thumb. + * ARM: Don't copy uncopyable instructions in gcse.c (backport from trunk). + * Build the spu cross compiler for powerpc from the cell-4_4-branch. + * gcj: add option -fuse-atomic-builtins (backport from the trunk). + + [ Arthur Loiret ] + * Make svn update interdiffs more readable. + + -- Matthias Klose Thu, 10 Dec 2009 04:29:36 +0100 + +gcc-4.4 (4.4.2-3) unstable; urgency=low + + * Update to SVN 20091118 from the gcc-4_4-branch (r154294). + Fix PR PR c++/9381, PR c++/21008, PR c++/35067, PR c++/36912, PR c++/37037, + PR c++/37093, PR c++/38699, PR c++/39786, c++/36959, PR c++/41754, + PR c++/41876, PR c++/41967, PR c++/41972, PR c++/41994, PR c++/42059, + PR c++/42061, + PR fortran/41772, PR fortran/41850, PR fortran/41909, + PR middle-end/40946, PR middle-end/41317, R tree-optimization/41643, + PR target/41900, PR rtl-optimization/41917, PR middle-end/41963, + PR middle-end/42029. + * Snapshot builds: + - Patch updates. + - Configure with --disable-browser-plugin. + * Configure with --disable-libstdcxx-pch on hppa. + * Backport armel patches form the trunk: + - Fix PR objc/41848 - workaround ObjC and -fsection-anchors. + - Enable scheduling for Thumb-2, including the fix for PR target/42031. + - Fix PR target/41939, EABI violation in accessing values below the stack. + + -- Matthias Klose Wed, 18 Nov 2009 08:37:18 -0600 + +gcc-4.4 (4.4.2-2) unstable; urgency=low + + * Update to SVN 20091031 from the gcc-4_4-branch (r153603). + - Fix PR debug/40521, PR target/40913, PR middle-end/22072, + PR target/41665, PR c++/38798, PR c++/40092, PR c++/37875, + PR c++/37204, PR fortran/41755, PR libstdc++/40654, PR libstdc++/40826, + PR target/41702, PR c/41842, PR target/41762, PR c++/40808, + PR fortran/41777, PR libstdc++/40852. + * Snapshot builds: + - Configure with --enable-plugin, disable the gcjwebplugin by a patch. + Addresses: #551200. + - Proposed patch for PR lto/41652, compile lto-plugin with + -D_FILE_OFFSET_BITS=64 + - Allow disabling the ada build via DEB_BUILD_OPTIONS nolang=ada. + * Fixes for reverse cross builds. + * On sparc default to v9 in 32bit mode. + * Fix __stack_chk_fail check for cross builds configured --with-headers. + * Apply some fixes for uClibc cross builds (Jonas Meyer, Hector Oron). + + -- Matthias Klose Sat, 31 Oct 2009 14:16:03 +0100 + +gcc-4.4 (4.4.2-1) unstable; urgency=low + + * GCC 4.4.2 release. + - Fixes PR target/26515, PR target/41680, PR rtl-optimization/41646, + PR c++/39863, PR c++/41038. + * Fix setting timeout for testsuite runs. + * gcj-4.4/gcc-snapshot: Drop build-dependency on libgconf2-dev, disabled + by default. + * gcj-4.4: Run the libffi testsuite as well. + * Add explicit build dependency on zlib1g-dev. + * Fix cross builds, add support for gomp and gfortran (only tested for + non-biarch targets). + * (Build-)depend on binutils-2.20. + * Fix up omp.h for multilibs (taken from Fedora). + + -- Matthias Klose Sun, 18 Oct 2009 02:31:32 +0200 + +gcc-4.4 (4.4.1-6) unstable; urgency=low + + * Snapshot builds: + - Add build dependency on libelfg0-dev (>= 0.8.12). + - Add build dependency on binutils-gold where available. + - Suggest binutils-gold; not perfect, it is required when using + -use-linker-plugin. + - Work around installation failure in the lto-plugin (PR lto/41569). + - Install java home symlinks in /usr/lib/jvm. + - Revert the dwarf2cfi_asm workaround, obsoleted by PR debug/40521. + * PR debug/40521: + - Apply patch for PR debug/40521, taken from the trunk. + - Revert the dwarf2cfi_asm workaround, obsoleted by PR debug/40521. + - Depend on binutils (>= 2.19.91.20091005). + * Update to SVN 20091005 from the gcc-4_4-branch (r152450). + - Fixes PR fortran/41479. + * In the test summary, add more information about package versions + used for the build. + + -- Matthias Klose Wed, 07 Oct 2009 02:12:56 +0200 + +gcc-4.4 (4.4.1-5) unstable; urgency=medium + + * Update to SVN 20091003 from the gcc-4_4-branch (r152174). + - Fixes PR target/22093, PR c/39779, PR libffi/40242, PR target/40473, + PR debug/40521, PR c/41049, PR debug/41065, PR ada/41100, + PR tree-optimization/41101, PR libgfortran/41328, PR libffi/41443, + PR fortran/41515. + * Updates for snapshot builds: + - Fix build dependency on automake for snapshot builds. + - Update patches pr40134-snap and libjava-nobiarch-check-snap. + * Fix lintian errors in libstdc++ packages and lintian warnings in the + source package. + * Add debian/README.source. + * Don't apply PR libstdc++/39491 for the trunk anymore. + * Install java home symlinks for snapshot builds in /usr/lib/jvm, + including javac. Depend on ecj. Addresses #536102. + * Fix build failure on armel with -mfloat-abi=softfp. + * Don't pessimize the code for newer armv6 and armv7 processors. + * libjava: Use atomic builtins For Linux ARM/EABI, backported from the + trunk. + * Proposed patch to fix wrong-code on powerpc (Alan Modra). LP: #432222. + * Link against -ldl instead of -lcloog -lppl. Exit with an error when using + the Graphite loop transformation infrastructure without having the + libcloog-ppl0 package installed (patch taken from Fedora). Packages + using these optimizations should build-depend on libcloog-ppl0. + gcc-4.4: Suggest the cloog runtime libraries. + * Install a hook _Unwind_DebugHook, called during unwinding. Intended as + a hook for a debugger to intercept exceptions. CFA is the CFA of the + target frame. HANDLER is the PC to which control will be transferred + (patch taken from Fedora). + + -- Matthias Klose Sat, 03 Oct 2009 13:33:05 +0100 + +gcc-4.4 (4.4.1-4) unstable; urgency=low + + * Update to SVN 20090911 from the gcc-4_4-branch (r151649). + - Fixes PR target/34412, PR middle-end/41094, PR target/40718, + PR fortran/41062, PR libstdc++/41005, PR target/41184, + PR bootstrap/41180, PR c++/41127, PR fortran/41258, + PR rtl-optimization/40861, PR target/41315, PR fortran/39876. + + [ Matthias Klose ] + * Avoid underscores in doc-base document id's to workaround a + dh_installdocs bug. + * Update file names for the Ada user's guide. + * Set Homepage attribute for packages. + * Update the patch for gnat on armel. + * gcj-4.4-jdk: Depend on libantlr-java. Addresses: #546062. + * Backport patch for PR tree-optimization/41101 from the trunk. + Closes: #541816. + * Update libstdc++6.symbols for symbols introduced with the fix + for PR libstdc++/41005. + * Apply proposed patches for PR libstdc++/40133 and PR target/40134. + Add symbols exception propagation support in libstdc++ on armel + to the libstdc++6 symbols. + + [ Ludovic Brenta] + Merge from gnat-4.4 (4.4.1-3) unstable; urgency=low + * debian/rules.defs, debian/rules.d/binary-ada.mk, debian/rules.patch: + better support for architectures that support only one exception + handling mechanism (SJLJ or ZCX). + + -- Matthias Klose Sat, 12 Sep 2009 03:18:17 +0200 + +gcc-4.4 (4.4.1-3) unstable; urgency=low + + * Update to SVN 20090822 from the gcc-4_4-branch (r151011). + - Fixes PR tree-optimization/41016, PR tree-optimization/41011, + PR tree-optimization/41008, PR tree-optimization/40991, + PR tree-optimization/40964, PR target/8603 (closes: #161432), + PR target/41019, PR target/41015, PR target/40957, PR target/40934, + PR rtl-optimization/41033, PR middle-end/41047, PR middle-end/41006, + PR fortran/41070, PR fortran/40995, PR fortran/40847, PR debug/40990, + PR debug/37801, PR c/41046, PR c/40948, PR c/40866, PR bootstrap/41018, + PR middle-end/41123,PR target/40971, PR c++/41131, PR fortran/41102, + PR libfortran/40962. + + [ Arthur Loiret ] + * Only use -fno-stack-protector when known to the stage1 compiler. + + [ Aurelien Jarno ] + * lib32* packages: remove the Pre-Depends: libc6-i386 (>= 2.9-18) and + upgrade the Conflicts: libc6-i386 from (<< 2.9-18) to (<< 2.9-22). + Closes: #537466. + * kbsd-gnu-ada.dpatch: add support for kfreebsd-amd64. + + [ Matthias Klose ] + * Build gnat on armel, the gnat-4.4 build still failing, gcc-snapshot + builds good enough to build itself. + * Merge enough of the gnat-4.4 changes back to allow a combined build + from the gcc-4.4 source. + * Build libgnatprj for armel. + * On armel build just one version of the ada run-time library. + * Update auto* build dependencies for snapshot builds. + * Apply proposed patch for PR target/40718. + + -- Matthias Klose Sun, 23 Aug 2009 11:50:38 +0200 + +gcc-4.4 (4.4.1-2) unstable; urgency=low + + [ Matthias Klose ] + * Update to SVN 20090808 from the gcc-4_4-branch (r150577). + - Fixes PR target/40832, PR rtl-optimization/40710, + PR tree-optimization/40321, PR build/40010, PR fortran/40727, + PR build/40010, PR rtl-optimization/40924, PR c/39902, + PR middle-end/40943, PR target/40577, PR c++/39987, PR debug/39706, + PR c++/40948, PR c++/40749, PR fortran/40851, PR fortran/40878, + PR target/40906. + * Bump GCC version required in dependencies to 4.4.1. + * Enable Ada for snapshot builds on all archs with a gnat package + available in the archive. + * Build-depend on binutils 2.19.51.20090805, needed at least for armel. + + [ Aurelien Jarno ] + * kbsd-gnu-ada.dpatch: new patch to fix build on GNU/kFreeBSD. + + -- Matthias Klose Sat, 08 Aug 2009 10:17:39 +0200 + +gcc-4.4 (4.4.1-1) unstable; urgency=low + + * GCC 4.4.1 release. + - Fixes PR target/39943, PR tree-optimization/40792, PR c++/40780, + PR middle-end/40747, PR libstdc++/40691, PR libfortran/40714, + PR tree-optimization/40813 (ICE in OpenJDK build on sparc). + * Apply proposed patch for PR target/39429, an ARM wrong-code error. + * Fix a typo in the arm back-end (proposed patch). + * Build-depend on libmpc-dev for snapshot builds. + * Fix build failure in cross builds (Hector Oron). Closes: #522597. + * Run the testsuite as part of the build target, not the install target. + + -- Matthias Klose Wed, 22 Jul 2009 13:24:39 +0200 + +gcc-4.4 (4.4.0-11) unstable; urgency=medium + + [ Matthias Klose ] + * Update to SVN 20090715 from the gcc-4_4-branch (r149690). + - Corresponds to the 4.4.1 release candidate. + - Fixes PR target/38900, PR debug/40666, PR middle-end/40669, + PR middle-end/40328, PR target/40587, PR middle-end/40585, + PR c++/40566, PR tree-optimization/40542, PR c/39902, + PR tree-optimization/40579, PR tree-optimization/40550, PR c++/40684, + PR c++/35828, PR c++/37816, PR c++/40639, PR c++/40633, PR c++/40619, + PR c++/40595, PR fortran/40440, PR fortran/40551, PR fortran/40638, + PR fortran/40443, PR libstdc++/40600, PR rtl-optimization/40667, PR c++/40740, + PR c++/36628, PR c++/37206, PR c++/40689, PR c++/40502, PR middle-end/40747. + * Backport of PR c/25509, new option -Wno-unused-result. LP: #305176. + * gcc-4.4: Depend on libgomp1, even if not building the libgomp1 package. + * Add proposed patches for PR libstdc++/40133, PR target/40134; don't apply + yet. + + [Emilio Pozuelo Monfort] + * Backport build-id support, configure with --enable-linker-build-id. + + -- Matthias Klose Tue, 14 Jul 2009 16:09:33 -0400 + +gcc-4.4 (4.4.0-10) unstable; urgency=low + + [ Arthur Loiret ] + * debian/rules.patch: Record the auto* calls to run them once only. + + [ Matthias Klose ] + * Update to SVN 20090627 from the gcc-4_4-branch (r149023). + - Fixes PR other/40024. + * Fix typo, adding blacklisted symbols to the libgcc1 symbols file on armel. + * On mips/mipsel use -O2 in STAGE1_CFLAGS until binutils is updated. + + -- Matthias Klose Sun, 28 Jun 2009 10:13:08 +0200 + +gcc-4.4 (4.4.0-9) unstable; urgency=high + + * Update to SVN 20090624 from the gcc-4_4-branch (r148821). + - Fix PR objc/28050 (LP: #362217), PR libstdc++/40297, PR c++/40342. + * Continue the well planned lib32 transition on amd64, adding pre-dependencies + on libc6-i386 (>= 2.9-18) on Debian. Closes: #533767. + * Enable SSP on arm and armel, run the testsuite with -fstack-protector. + LP: #375189. + * Fix spu fortran build in gcc-snapshot builds. + * Add missing symbols for 64bit libgfortran library. + * Update libstdc++ symbol files for sparc 64bit, adding symbols + for exception propagation support. + * Explicitely add __aeabi symbols to the libgcc1 symbols file on armel. + Closes: #533843. + + -- Matthias Klose Wed, 24 Jun 2009 23:46:02 +0200 + +gcc-4.4 (4.4.0-8) unstable; urgency=medium + + * Let all 32bit libs conflict with libc6-i386 (<< 2.9-17). Closes: #533767. + * Update to SVN 20090620 from the gcc-4_4-branch (r148747). + - Fixes PR fortran/39800, PR fortran/40402. + * Work around tar bug on kfreebsd unpacking java class file updates (#533356). + + -- Matthias Klose Sat, 20 Jun 2009 15:15:22 +0200 + +gcc-4.4 (4.4.0-7) unstable; urgency=medium + + * Update to SVN 20090618 from the gcc-4_4-branch (r148685). + - Fixes PR middle-end/40446, PR middle-end/40389, PR middle-end/40460, + PR fortran/40168, PR target/40470. + * On amd64, install 32bit libraries into /lib32 and /usr/lib32. + * lib32gcc1, lib32gomp1, lib32stdc++6: Conflict with libc6-i386 (= 2.9-15), + libc6-i386 (= 2.9-16). + * Handle serialver alternative in -jdk install scripts, not in -jre-headless. + + -- Matthias Klose Fri, 19 Jun 2009 01:36:00 +0200 + +gcc-4.4 (4.4.0-6) unstable; urgency=low + + [ Matthias Klose ] + * Update to SVN 20090612 from the gcc-4_4-branch (r148433). + - Fixes PR c++/38064, PR c++/40139, PR target/40017, PR target/40266, + PR bootstrap/40027, PR tree-optimization/40087, PR target/39856, + PR rtl-optimization/40105, PR target/39942, PR middle-end/40204, + PR debug/40109, PR tree-optimization/39999, PR libfortran/37754, + PR fortran/22423, PR libfortran/39667, PR libfortran/39782, + PR libfortran/38668, PR libfortran/39665, PR libfortran/39702, + PR libfortran/39709, PR libfortran/39665i, PR libgfortran/39664, + PR fortran/38654, PR libfortran/37754, PR libfortran/37754, + PR libfortran/25561, PR libfortran/37754, PR middle-end/40291, + PR target/40017, PR middle-end/40340, PR c++/40308, PR c++/40311, + PR c++/40306, PR c++/40307, PR c++/40370, PR c++/40372, PR c++/40373, + PR c++/40381, PR fortran/40019, PR fortran/39893. + * gcj-4.4-jdk: Depend on libecj-java-gcj instead of libecj-java. + * Let gjdoc --version use the Configuration class instead of + version.properties (Alexander Sack). LP: #385682. + * Preserve libgcc_s.so linker scripts. Closes: #532263. + + [Ludovic Brenta] + * debian/patches/ppc64-ada.dpatch, + debian/patches/ada-mips.dpatch, + debian/patches/ada-mipsel.dpatch: remove, merged upstream. + * debian/patches/*ada*.dpatch: + - rename to *.diff; + - remove the dpatch prologue shell script + - refresh with quilt -p ab and without time stamps + - adjust to GCC 4.4 + * debian/patches/ada-library-project-files-soname.diff, + debian/patches/ada-polyorb-dsa.diff, + debian/patches/pr39856.diff: new. + * debian/rules.patch: adjust accordingly. + * debian/rules.defs: re-enable Ada. + * debian/rules2: do a lean bootstrap when building Ada. + * debian/rules.d/binary-ada.mk: do not build gnatbl or gprmake anymore, + removed upstream. + + -- Matthias Klose Fri, 12 Jun 2009 18:34:13 +0200 + +gcc-4.4 (4.4.0-5) unstable; urgency=medium + + * Update to SVN 20090517 from the gcc-4_4-branch (r147630). + - Fixes PR tree-optimization/40062, PR middle-end/39986, + PR middle-end/40057, PR fortran/39879, PR libstdc++/40038, + PR middle-end/40035, PR target/37179, PR middle-end/39666, + PR tree-optimization/40074, PR fortran/40018, PR fortran/38863, + PR middle-end/40147, PR fortran/40018, PR target/40153. + + [ Matthias Klose ] + * Update libstdc++ symbols files. + * Update libgcc, libobjc, libstdc++ symbols files for armel. + * Fix version symlink in gcc_lib_dir. Closes: #527837. + * Fix symlinks for javac and header files in /usr/lib/jvm. + Closes: #528084. + * Don't build the stage1 compiler with -O with recent binutils (trunk). + * Revert doing link tests to check for the atomic builtins, disabling + exception propagation support in libstdc++ on armel. See PR40133, PR40134. + * On mips/mipsel don't run the java testsuite with -mabi=64. + * Default to armv4 for the gcc-snapshot package as well. Closes: #523936. + * Mention GCC trunk in the gcc-snapshot package description. Closes: #526309. + * Remove unneed '..' elements from symlinks in JAVA_HOME. + * Fix some lintian warnings for gcc-snapshot. + + [ Arthur Loiret ] + * Add missing dir separator to multiarch path. Closes: #527537. + + -- Matthias Klose Sun, 17 May 2009 11:15:52 +0200 + +gcc-4.4 (4.4.0-4) unstable; urgency=medium + + * Update to SVN 20090506 from the gcc-4_4-branch (r147161). + - Fixes PR rtl-optimization/39914, PR testsuite/39776, + PR tree-optimization/40022, PR libstdc++/39909. + + [ Matthias Klose ] + * gcc-4.4-source: Don't depend on gcc-4.4-base, depend on quilt + and patchutils. + * On armel, link the shared libstdc++ with both -lgcc_s and -lgcc. + * Update libgcc and libstdc++ symbol files for mips and mipsel. + * Update libstdc++ symbol files for armel and hppa, adding symbols + for exception propagation support. + * Add ARM EABI symbols to libstdc++ symbol files for armel. + * Add libobjc symbols file for armel. + * Fix PR libstdc++/40038, missing ceill/tanhl symbols in libstdc++. + + [ Aurelien Jarno ] + * Fix libc name for biarch packages on kfreebsd-amd64. + + -- Matthias Klose Wed, 06 May 2009 15:10:36 +0200 + +gcc-4.4 (4.4.0-3) unstable; urgency=low + + * libstdc++-doc: Install the man pages again. + * Fix build configuration for the GC enabled ObjC runtime library. + * Fix thinko in autotools_files, resulting in autoconf not run in + some cases. + * Do link tests to check for the atomic builtins, enables exception + propagation support in libstdc++ on armel and hppa. + + -- Matthias Klose Sun, 03 May 2009 23:38:56 +0200 + +gcc-4.4 (4.4.0-2) unstable; urgency=low + + [ Samuel Thibault ] + * Enable java build on the hurd. + + [ Matthias Klose ] + * libobjc2.symbols.armel: Remove, use the default one. + * Address PR libstdc++/39491, removing __signbitl from the libstdc++6 + symbols file on hppa. + * libstdc++6.symbols.armel: Fix error introduced with copy from the + arm symbols file. + * libstdc++6.symbols.*: Don't assume exception propagation support + enabled for all architectures (although it should on armel, hppa, + sparc). + * Disable the build of the ObjC garbage collection library on mips*, + working around a build failure. + + -- Matthias Klose Sat, 02 May 2009 14:22:35 +0200 + +gcc-4.4 (4.4.0-1) unstable; urgency=low + + [ Matthias Klose ] + * Update to SVN 20090429 from the gcc-4_4-branch (r146989). + * Configure java enabled builds with --enable-java-home. + * Integrate the bits previously found in java-gcj-compat. + * Rename the packages using the naming schema used for OpenJDK: + gcj-X.Y-{jre-headless,jre,jre-lib,jdk,source}. The packages + {gij,gcj,gappletviewer}-X.Y and libgcjN-{jar,source} are gone. + * Build the libgcj documentation with the just built gjdoc. + * Don't use profiled bootstrap when building the gcj source. + * Apply proposed patch for PR target/39856. + * Fix some lintian warnings. + * Don't include debug symbols for libstdc++.so.6, if the library is + built by a newer GCC version. + * Adjust hrefs to point to the local libstdc++ documentation. LP: #365414. + * Update libgcc, libgfortran, libobjc, libstdc++ symbol files. + * gcc-4.4: Include libssp_nonshared.a. + * For ix86, set the java architecture directory to i386. + + [ Samuel Thibault ] + * Update Hurd changes. + * Configure with --enable-clocale=gnu on hurd-i386. + * debian/patches/hurd-pthread.diff: Reapply. + + -- Matthias Klose Thu, 30 Apr 2009 00:30:20 +0200 + +gcc-4.4 (4.4.0-1~exp2) experimental; urgency=low + + * Update to SVN 20090423 from the gcc-4_4-branch. + + [ Aurelien Jarno ] + * kbsd-gnu.diff: remove parts merged upstream. + + [ Matthias Klose ] + * Remove conflicts/replaces for *-spu packages. + * Configure the spu cross compiler without --with-sysroot and + --enable-multiarch. + * Fix and reenable the gfortran-spu build. + * Work around build failures with missing libstdc++ baseline files. + * Install gjdoc man page. + * Fix java configuration with --enable-java-home and include symlinks + for JAVA_HOME in /usr/lib/jvm. + * Apply proposed fix for PR middle-end/39794. + * Install libstdc++ man pages with suffix .3cxx instead of .3. + Closes: #525244. + * lib*stdc++6-{dbg,doc}: Add conflicts to the corresponding 4.3 packages. + + -- Matthias Klose Thu, 23 Apr 2009 18:11:49 +0200 + +gcc-4.4 (4.4.0-1~exp1) experimental; urgency=low + + * Final GCC 4.4.0 release. + + * Don't build the Fortran SPU cross compiler, currently broken. + * spu cross build: Build without spucache and spumea64. + * Configure --with-arch-32=i486 on amd64, i386, and kfreebsd-{amd64,i386}, + --with-arch-32=i586 on hurd-i386, --with-cpu=atom on lpia. + * Build using profiled bootstrap. + * Remove the gcc-4.4-base.postinst. Addresses: #524708. + * Update debian/copyright: Include runtime library exception, remove + D and Phobas license. + * Apply proposed patch for PR libstdc++/39491, missing symbol in libstdc++ + on hppa. + * Remove unsused soft-fp functions in the 64bit libgcc on powerpc (PR39828). + * Update NEWS files for 4.4. + * Build again libgfortran for the non-default multilib configuration. + * Restore missing chunks in note-gnu-stack.diff, lost during the conversion + to quilt. + + -- Matthias Klose Wed, 22 Apr 2009 00:53:16 +0200 + +gcc-4.4 (4.4-20090418-1) experimental; urgency=low + + * Update to SVN 20090418 from the gcc-4_4-branch. + + [ Arthur Loiret ] + * Update patches: + - boehm-gc-nocheck, cross-include, libjava-rpath, link-libs: + Rebase on trunk. + - gcc-m68k-pch, libjava-debuginfo, libjava-loading-constraints: + Remove, merged in trunk. + - cell-branch, cell-branch-doc: Remove, there is no upstream cell 4.4 + branch yet. + - gdc-fix-build-kbsd-gnu, svn-gdc-updates, gpc-4.1, gpc-gcc-4.x, + gpc-names: Remove, gpc and gdc are not ported to GCC 4.4 yet. + - svn-class-updates, svn-doc-updates, svn-updates: Make empty. + - Refresh all others, and convert them all to quilt. + + * Build system improvements: + - Partial rewrite/refactor of rules files. + - Switch patch system to quilt. + - Autogenerate debian/copyright. + - Use the autoconf2.59 package. + + * multilib/multiarch support improvements: Closes: #369064, #484589. + - mips-triarch.diff: Replace with a newer version (approved upstream). + - s390-biarch.diff: Ditto. + - debian/rules2: Configure with --enable-targets=all on mips-linux, + mipsel-linux and s390-linux. + - gcc-multiarch.diff: New, add multiarch include directories and + libraries path to the system paths. + - debian/rules2: Configure with --enable-multiarch. Configure spu build + with --with-multiarch-defaults=spu-elf. + - multiarch-include.diff: Remove. + - debian/multiarch.inc: Ditto. + + * cross-compilers changes: + - Never build a separated -base package, don't symlink any doc dir. + - Build gobjc again. + + * Run the 64-bit tests with -mabi=64 instead of -m64 on mips/mipsel to + hopefully fix the massive failure. + * Always set $(distribution) to "Debian" on mips/mipsel, workarounds FTBFS + on those archs due to a kernel bug triggered by lsb_release call. + Adresses: #524416. + * debian/rules.patch: Only apply the ada-nobiarch-check patch when ada is + enabled. Remove gpc and gdc patches. + * debian/rules.unpack (install_autotools_stamp): Remove. + * debian/rules.defs (configure_dependencies): Remove autotools dependency. + * debian/rules.conf: Add a copyright-file target. + * debian/control.m4: Build-Depends on autoconf2.59 and patchutils. + Make gcc-4.4-source Depends on autoconf2.59. + Add myself to Uploaders. + * debian/rules.d/binary-source.mk: Don't build and install an embedded + copy or autoconf2.59 in gcc-4.4-source. + * debian/copyright.in: New. + + [ Matthias Klose ] + * Build gcj on hppa. + * Add support to build vfp optimized runtime libraries on armel. + * gcc-4.4-spu: Depend on newlib-spu. + * Fix sections of -dbg and java packages. + * gcc-default-ssp.dpatch: Set the default as well, when calling the + preprocessor. LP: #346126. + * Build-depend on quilt. + * Keep the copyright file in the archive. + * Remove conflict of the gcc-X.Y-source packages. + * Update removal of gfdl doc files for 4.4. + * Don't re-run the autotools (introduced with the switch to quilt). + * On arm and armel, install the arm_neon.h header. LP: #360819. + * When hardening options are turned on by default, patch the testsuite + to handle the hardening defaults (Kees Cook). + * Only run the patch target once. Avoids multiple autotool runs, but + doesn't reflect changes in the series file anymore. + * libgcj-doc: Fix documentation title. + * Fix gcj source build with recent build changes. + * Don't check for libraries in DEB_BUILD_OPTIONS/nolang. + * gappletviewer: Include missing binary. + + [ Aurelien Jarno ] + * Remove: patches/kbsd-gnu-ada.dpatch (merged upstream). + * kbsd-gnu.diff: add fix for stuff broken by upstream. + + -- Matthias Klose Mon, 20 Apr 2009 01:34:26 +0200 + +gcc-4.4 (4.4-20090317-1) experimental; urgency=low + + * Initial upload of GCC-4.4, based on trunk 20090317 (r144904). + + [Matthias Klose] + * Branch from the gcc-4.3 packaging. + * Remove *-trunk patches, update remaining patches for the trunk. + * Remove patches integrated upstream: libobjc-gc-link, libjava-file-support, + libjava-realloc-leak, libjava-armel-ldflags, libstdc++-symbols-hppa, + gcc-m68k-pch, libjava-extra-cflags, libjava-javah-bridge-tgts, + hppa-atomic-builtins, armel-atomic-builtins, libssp-gnu, libobjc-armel, + gfortran-armel-updates, sparc-biarch, libjava-xulrunner-1.9. + * Update patches for 4.4, mostly using the patches converted for quilt by + Arthur Loiret. + * debian/patches/libjava-soname.dpatch: Remove, unmodifed upstream library. + * debian/patches/gcc-driver-extra-langs.dpatch: Search Ada files in subdir. + * debian/rules.unpack, debian/rules.d/binary-source.mk: Update for included + autoconf tarball. + * debian/rules.d/binary-{gcc,java}.mk: Install new header files. + * debian/libgfortran3.symbols.common: Remove symbol not generated by + gfortran (__iso_c_binding_c_f_procpointer@GFORTRAN_1.0), PR38871. + * debian/rules.conf: Update for 4.4. + * Fix build dependencies and configure options for 4.4, which were applied + for snapshot builds only. + + [Arthur Loiret] + * Update patches from debian/patches: + - Remove backported fixes: + PR ada: pr10768.dpatch, pr15808.dpatch, pr15915.dpatch, pr16086.dpatch, + pr16087.dpatch, pr16098.dpatch, pr17985.dpatch, pr18680.dpatch, + pr22255.dpatch, pr22387.dpatch, pr28305.dpatch, pr28733.dpatch, + pr29015.dpatch, pr30740.dpatch, pr30827.dpatch pr33688.dpatch, + pr34466.dpatch, pr35050.dpatch, pr35792.dpatch. + PR target: pr27880.dpatch, pr28102.dpatch, pr30961.dpatch, + pr35965.dpatch, pr37661.dpatch. + PR libgcj: pr24170.dpatch, pr35020.dpatch. + PR gcov-profile: pr38292.dpatch. + PR other: pr28322.dpatch. + * debian/rules.patch: Update. + * debian/symbols/libgomp1.symbols.common: Add new symbols from OpenMP 3.0. + + -- Matthias Klose Tue, 17 Mar 2009 02:28:01 +0100 + +gcc-4.3 (4.3.3-5) unstable; urgency=low + + Merge from gnat-4.3 (4.3.3-1): + + [Petr Salinger] + * debian/patches/ada-libgnatprj.dpatch: enable support for GNU/kFreeBSD. + Fixes: #512277. + + [Ludovic Brenta] + * debian/patches/ada-acats.dpatch: attempt to fix ACATS tests (not entirely + successful yet). + * New upstream version. Fixes: #514565. + + [Matthias Klose] + * Update to SVN 20090301 from the gcc-4_3-branch. + - Fix PR c/35446, PR c++/38950, PR fortran/38852, PR fortran/39006, + PR c++/39225 (closes: #516727), PR c++/38950, PR target/38056, + PR target/39228, PR middle-end/36578, PR inline-asm/39058, + PR middle-end/37861. + * Don't provide the 4.3.2 symlink in gcc_lib_dir anymore. + * Require binutils-2.19.1. + + -- Matthias Klose Sun, 01 Mar 2009 14:18:09 +0100 + +gcc-4.3 (4.3.3-4) unstable; urgency=low + + * Fix Fix PR gcov-profile/38292 (wrong profile information), taken + from the trunk. + * Update to SVN 20090215 from the gcc-4_3-branch. + Fix PR c/35435, PR tree-optimization/39100, PR rtl-optimization/39076, + PR c/35433, PR tree-optimization/39041, PR target/38988, + PR middle-end/38969, PR c++/36897, PR c++/39054, PR c/39035, PR c/35434, + PR c/36432, PR target/38991, PR c/39084, PR target/39118. + * Reapply the fix for PR middle-end/38615. + * Include autoconf-2.59 sources into the source package, and install as + part of the gcc-4.3-source package. + * Explicitely use autoconf-1.9. + * Disable building the gcjwebplugin. + * Don't configure with --enable-cld on amd64 and i386. + + -- Matthias Klose Sun, 15 Feb 2009 23:40:09 +0100 + +gcc-4.3 (4.3.3-3) unstable; urgency=medium + + * Revert fix for PR middle-end/38615. Closes: #513420. + + -- Matthias Klose Thu, 29 Jan 2009 07:05:15 +0100 + +gcc-4.3 (4.3.3-2) unstable; urgency=low + + * Update to SVN 20090127 from the gcc-4_3-branch. + - Fix PR tree-optimization/38359. Closes: #492505. + - Fix PR tree-optimization/38932 (ice-on-valid-code), PR target/38931 + (ice-on-valid-code), PR rtl-optimization/38879 (wrong-code), + PR c++/23287 (rejects-valid), PR fortran/38907 (ice-on-valid-code), + PR fortran/38859 (wrong-code), PR fortran/38657 (rejects-valid), + PR fortran/38672 (ice-on-valid-code). + * Fix PR middle-end/38969, taken from the trunk. Closes: #513007. + + -- Matthias Klose Tue, 27 Jan 2009 23:42:45 +0100 + +gcc-4.3 (4.3.3-1) unstable; urgency=low + + * GCC-4.3.3 release (no changes compared to the 4.3.2-4 upload). + * Fix PR middle-end/38615 (wrong code, taken from the trunk). + + -- Matthias Klose Sat, 24 Jan 2009 14:43:09 +0100 + +gcc-4.3 (4.3.2-4) unstable; urgency=medium + + * Update to SVN 20090119 from the gcc-4_3-branch. + - Fix PR tree-optimization/36765 (wrong code). + * Remove patch for PR 34571, applied upstream (fix build failure on alpha). + * Apply proposed patch for PR middle-end/38902 (wrong code). + + -- Matthias Klose Tue, 20 Jan 2009 00:22:41 +0100 + +gcc-4.3 (4.3.2-3) unstable; urgency=low + + * Update to SVN 20090117 from the gcc-4_3-branch (4.3.3 release candidate). + - Fix PR target/34571, PR debug/7055, PR tree-optimization/37194, + PR tree-optimization/38529, PR fortran/38763, PR fortran/38765, + PR fortran/38669, PR fortran/38487, PR fortran/35681, PR fortran/38657, + PR c++/36019, PR c++/31488, PR c++/37646, PR c++/36334, PR c++/38357, + PR c++/31260, PR c++/38877, PR libstdc++/36801, PR libgcj/38396. + - debian/patches/libgcj-bc.dpatch: Remove, applied upstream. + * Fix PR middle-end/38616 (wrong code with -fstack-protector). + * Update backport for PR28322 (Gunther Nikl). + + -- Matthias Klose Sat, 17 Jan 2009 21:09:35 +0100 + +gcc-4.3 (4.3.2-2) unstable; urgency=low + + * Update to SVN 20090110 from the gcc-4_3-branch. + - Fix PR target/36654, PR tree-optimization/38752, PR fortran/38675, + PR fortran/37469, PR libstdc++/38000. + + -- Matthias Klose Sat, 10 Jan 2009 18:32:34 +0100 + +gcc-4.3 (4.3.2-2~exp5) experimental; urgency=low + + * Adjust build-dependencies for cross builds. Closes: #499998. + * Update to SVN 20081231 from the gcc-4_3-branch. + - Fix PR middle-end/38565, PR target/38062, PR bootstrap/38383, + PR target/38402, PR testsuite/35677, PR tree-optimization/38478, + PR target/38054, PR middle-end/29056, PR testsuite/28870, + PR target/38254. + - Fix PR libstdc++/37144, PR c++/37582, PR libstdc++/38080. + - Fix PR fortran/38602, PR fortran/38602, PR fortran/38487, + PR fortran/38113, PR fortran/35983, PR fortran/35937, PR testsuite/36889. + * Update the spu cross compiler from the cell-gcc-4_3-branch 20081217. + * debian/patches/libobjc-armel.dpatch: Don't define EH_USES. + * Apply the Atomic builtins patch for PARISC. + + -- Matthias Klose Thu, 18 Dec 2008 00:34:46 +0100 + +gcc-4.3 (4.3.2-2~exp4) experimental; urgency=low + + * Update to SVN 20081130 from the gcc-4_3-branch. + - Fix PR bootstrap/33304, PR middle-end/37807, PR middle-end/37809, + PR rtl-optimization/37489, PR target/35574, PR c/37924, + PR tree-optimization/37879, PR middle-end/37858, PR middle-end/37870, + PR target/38016, PR target/37939, PR rtl-optimization/37769, + PR target/37909, PR fortran/37597, PR fortran/35820, PR fortran/37445, + PR fortran/PR35769, PR fortran/37903, PR fortran/37749. + - Fix PR target/37640, PR tree-optimization/37868, PR bootstrap/33100, + PR other/38214, PR c++/37142, PR c++/35405, PR c++/37563, PR c++/38030, + PR c++/37932, PR c++/38007. + - Fix PR fortran/37836, PR fortran/38171, PR fortran/35681, + PR fortran/37792, PR fortran/37926, PR fortran/38033, PR fortran/36526. + - Fix PR target/38287. Closes: #506713. + * Atomic builtins using kernel helpers for PARISC and ARM Linux/EABI, taken + from the trunk. + + -- Matthias Klose Mon, 01 Dec 2008 01:29:51 +0100 + +gcc-4.3 (4.3.2-2~exp3) experimental; urgency=low + + * Update to SVN 20081117 from the gcc-4_3-branch. + * Add build dependencies on spu packages for snapshot builds. + * Add build dependency on libantlr-java for snapshot builds. + * Disable fortran on spu for snapshot builds. + * Add dependency on binutils-{hppa64,spu} for snapshot builds. + + -- Matthias Klose Mon, 17 Nov 2008 21:57:51 +0100 + +gcc-4.3 (4.3.2-2~exp2) experimental; urgency=low + + * Update to SVN 20081023 from the gcc-4_3-branch. + - General regression fixes: PR rtl-optimization/37882 (wrong code), + - Fortran regression fixes: PR fortran/37787, PR fortran/37723. + * Use gij-4.3 for builds in java maintainer mode. + * Don't run the testsuite with -fstack-protector for snapshot builds. + * Update the spu cross compiler from the cell-gcc-4_3-branch 20081023. + Don't disable multilibs, install additional components in the gcc-4.3-spu + package. + * Enable building the spu cross compiler for powerpc and ppc64 snapshot + builds. + * Apply proposed patch for PR tree-optimization/37868 (wrong code). + * Apply proposed patch to parallelize make check. + * For biarch builds, disable the gnat testsuite for the non-default + architecture (no biarch support in gnat yet). + + -- Matthias Klose Thu, 23 Oct 2008 22:06:38 +0200 + +gcc-4.3 (4.3.2-2~exp1) experimental; urgency=low + + * Update to SVN 20081017 from the gcc-4_3-branch. + - General regression fixes: PR rtl-optimization/37408 (wrong code), + PR tree-optimization/36630, PR tree-optimization/37102 (wrong code), + PR c/35437 (ice on invalid code), PR middle-end/37731 (wrong code), + PR target/37603 (wrong code, hppa), PR tree-optimization/35737 (ice on + valid code), PR middle-end/36575 (wrong code), PR c/37645 (ice on valid + code), PR tree-optimization/37539 (compile time hog), PR middle-end/37236 + (ice on invalid code), PR tree-optimization/36343 (wrong code), + PR rtl-optimization/37544 (wrong code), PR target/35620 (ice on valid + code), PR target/35713 (ice on valid code, wrong code), PR c/35712 (wrong + code), PR target/37466 (wrong code, AVR). + - C++ regression fixes: PR c++/37389 (LP: #252301), PR c++/37555 (ice on + invalid code). + - Fortran regression fixes: PR fortran/37199, PR fortran/36214, + PR fortran/35770, PR fortran/36454, PR fortran/36374, PR fortran/37274, + PR fortran/37583, PR fortran/36700, PR fortran/35945, PR fortran/37626, + PR fortran/37504, PR fortran/37580, PR fortran/37706, PR fortran/35680, + PR fortran/37794. + * Remove obsolete patches: ada-driver.dpatch, pr33148.dpatch. + * Fix naming of bridge targets in gjavah (wrong header generation). + * Fix PR target/37661, SPARC64 int-to-TFmode conversions. + * Include the complete test summaries in a binary package, to allow + regression checking from the previous build. + * Tighten inter-package dependencies to (>= 4.3.2-1). + * Drop the 4.3.1 symlink in gcc_lib_dir, add a 4.3.3 symlink to 4.3. + + -- Matthias Klose Fri, 17 Oct 2008 23:26:50 +0200 + +gcc-4.3 (4.3.2-1) unstable; urgency=medium + + [Matthias Klose] + * Final gcc-4.3.2 release (regression fixes). + - Remove the generated install docs from the tarball (GFDL licensed). + - C++ regression fixes: PR debug/37156. + - general regression fixes: PR debug/37156, PR target/37101. + - Java regression fixes: PR libgcj/8995. + * Update to SVN 20080905 from the gcc-4_3-branch. + - C++ regression fixes: PR c++/36741 (wrong diagnostic), + - general regression fixes: PR target/37184 (ice on valid code), + PR target/37191 (ice on valid code), PR target/37197 (ice on valid code), + PR middle-end/36817 (ice on valid code), PR middle-end/36548 (wrong code), + PR middle-end/37125 (wrong code), PR c/37261 (wrong diagnostic), + PR target/37168 (ice on valid code), PR middle-end/36449 (wrong code), + PR middle-end/37248 (missed optimization), PR target/36332 (wrong code). + - Fortran regression fixes: PR fortran/37193 (rejects valid code). + * Move symlinks in gcc_lib_dir from cpp-4.3 to gcc-4.3-base. Closes: #497369. + * Don't build-depend on autogen on architectures where it is not installable + (needed for the fixincludes testsuite only); don't build-depend on it for + source packages not running the fixincludes testsuite. + + [Ludovic Brenta] + * Add sdefault.ads to libgnatprj4.3-dev. Fixes: #492866. + * turn gnatvsn.gpr and gnatprj.gpr into proper library project files. + * Unconditionally build-depend on gnat when building gnat-4.3. + Fixes: #487564. + * (debian/rules.d/binary-ada.mk): Add a symlink libgnat.so to + /usr/lib/libgnat-4.3.so in the adalib directory. Fixes: #493814. + * (debian/patches/ada-sjlj.dpatch): remove dangling symlinks from all + adalib directories. + * debian/patches/ada-alpha.dpatch: remove, applied upstream. + + [Samuel Tardieu, Ludovic Brenta] + * debian/patches/pr16086.dpatch: new; backport from GCC 4.4. + Closes: #248172. + * debian/patches/pr35792.dpatch: new; backport from GCC 4.4. + * debian/patches/pr15808.dpatch (fixes: #246392), + debian/patches/pr30827.dpatch: new; backport from the trunk. + + -- Matthias Klose Fri, 05 Sep 2008 22:52:58 +0200 + +gcc-4.3 (4.3.1-9) unstable; urgency=low + + * Update to SVN 20080814 from the gcc-4_3-branch. + - C++/libstdc++ regression fixes: PR c++/36688, PR c++/37016, PR c++/36999, + PR c++/36405, PR c++/36767, PR c++/36852. + - general regression fixes: PR target/36613, PR rtl-optimization/36998, + PR middle-end/37042, PR middle-end/35432, PR target/35659, + PR middle-end/37026, PR middle-end/36691, PR tree-optimization/36991, + PR rtl-optimization/35542, PR bootstrap/35752, PR rtl-optimization/36419, + PR debug/36278, PR preprocessor/36649, PR rtl-optimization/36929, + PR tree-optimization/36830, PR c/35746, PR middle-end/37014, + PR middle-end/37103. + - Fortran regression fixes: PR fortran/36132. + - Java regression fixes: PR libgcj/31890. + - Fixes PR middle-end/37090. Closes: #494815. + + -- Matthias Klose Thu, 14 Aug 2008 18:02:52 +0000 + +gcc-4.3 (4.3.1-8) unstable; urgency=low + + * Undo Revert PR tree-optimization/36262 on i386 (PR 36917 is invalid). + + -- Matthias Klose Fri, 25 Jul 2008 21:47:52 +0200 + +gcc-4.3 (4.3.1-7) unstable; urgency=low + + * Update to SVN 20080722 from the gcc-4_3-branch. + - Fix PR middle-end/36811, infinite loop building with -O3. + - C++/libstdc++ regression fixes: PR c++/36407, PR c++/34963, + PR libstdc++/36832, PR libstdc++/36552, PR libstdc++/36729. + - Fortran regression fixes: PR fortran/36366, PR fortran/36824. + - general regression fixes: PR middle-end/36877, PR target/36780, + PR target/36827, PR rtl-optimization/35281, PR rtl-optimization/36753, + PR target/36827, PR target/36784, PR target/36782, PR middle-end/36369, + PR target/36780, PR target/35492, PR middle-end/36811, + PR rtl-optimization/36419, PR target/35802, PR target/36736, + PR target/34780. + * Revert PR tree-optimization/36262 on i386, causing miscompilation of + OpenJDK hotspot. + * gij/gcj: Don't remove alternatives on upgrade. Addresses: #479950. + + -- Matthias Klose Tue, 22 Jul 2008 23:55:54 +0200 + +gcc-4.3 (4.3.1-6) unstable; urgency=low + + * Start the logwatch script on alpha as well to avoid timeouts in + the testsuite. + + -- Matthias Klose Mon, 07 Jul 2008 11:31:58 +0200 + +gcc-4.3 (4.3.1-5) unstable; urgency=low + + * Update to SVN 20080705 from the gcc-4_3-branch. + - Fix PR target/36634, wrong-code on powerpc with -msecure-plt. + * Fix PR target/35965, PIC + -fstack-protector on arm/armel. Closes: #469517. + * Don't run the libjava testsuite with -mabi=n32. + * Update patch for PR other/28322, that unknown -Wno-* options do not + cause errors, but warnings instead. + * On m68k, add -fgnu89-inline when in gnu99 mode (requested by Michael + Casadeval for the m68k port). Closes: #489234. + + -- Matthias Klose Sun, 06 Jul 2008 01:39:30 +0200 + +gcc-4.3 (4.3.1-4) unstable; urgency=low + + * Revert: debian/patches/gcc-multilib64dir.dpatch: Remove obsolete patch. + * Remove obsolete multiarch-lib patch. + + -- Matthias Klose Mon, 30 Jun 2008 23:05:17 +0200 + +gcc-4.3 (4.3.1-3) unstable; urgency=medium + + [Arthur Loiret] + * debian/rules2: + - configure sh4-linux with --with-multilib-list=m4,m4-nofpu + and --with-cpu=sh4. + - configure sparc-linux with --enable-targets=all on snapshot builds + (change already in 4.3.1-1). + * debian/rules.patch: Don't apply sh4-multilib.dpatch. + + [Matthias Klose] + * Update to SVN 20080628 from the gcc-4_3-branch. + - Fix PR target/36533, wrong-code with incorrectly assumed aligned_operand. + Closes: #487115. + * debian/rules.defs: Remove hurd-i386 from ssp_no_archs (Samuel Thibault). + Closes: #483613. + * Do not create a /usr/lib/gcc//4.3.0 symlink. + * debian/patches/gcc-multilib64dir.dpatch: Remove obsolete patch. + * libjava/classpath: Set and use EXTRA_CFLAGS (taken from the trunk). + + -- Matthias Klose Sat, 28 Jun 2008 16:00:38 +0200 + +gcc-4.3 (4.3.1-2) unstable; urgency=low + + * Update to SVN 20080610 from the gcc-4_3-branch. + - config.gcc: Fix quoting for in the enable_cld test. + * Use GNU locales on hurd-i386 (Samuel Thibault). Closes: #485395. + * libstdc++-doc: Fix URL's for locally installed docs. Closes: #485133. + * libjava: On armel apply kludge to fix unwinder infinitely looping 'til + it runs out of memory. + * Adjust dependencies to require GCC 4.3.1. + + -- Matthias Klose Wed, 11 Jun 2008 00:35:38 +0200 + +gcc-4.3 (4.3.1-1) unstable; urgency=high + + [Samuel Tardieu, Ludovic Brenta] + * debian/patches/pr16087.dpatch: new. Fixes: #248173. + * Correct the patches from the previous upload. + + [Ludovic Brenta] + * debian/patches/ada-acats.dpatch: really run the just-built gnat, not the + bootstrap gnat. + * debian/rules2: when running the Ada test suite, do not run the multilib + tests as gnat does not support multilib yet. + * Run the ACATS testsuite again (patch it so it correctly finds gnatmake). + + [Thiemo Seufer] + * debian/patches/ada-libgnatprj.dpatch, + debian/patches/ada-mips{,el}.dpatch: complete support for mips and mipsel. + Fixes: #482433. + + [Matthias Klose] + * GCC-4.3.1 release. + * Do not include standard system paths in libgcj pkgconfig file. + * Suggest the correct libmudflap0-dbg package. + * Fix PR libjava/35020, taken from the trunk. + * Apply proposed patch for PR tree-optimization/36343. + * On hurd-i386 with -fstack-protector do not link with libssp_nonshared + (Samuel Thibault). Closes: #483613. + * Apply proposed patch for PR tree-optimization/34244. + * Remove debian-revision in symbols files. + * Fix installation of all biarch -multilib packages which are not triarch. + * Fix some lintian warnings. + * Include library symlinks in gobjc and gfortran multilib packages, when + not building the library packages. + * Fix sections in doc-base files. + * Don't apply the sparc-biarch patch when building the gcc-snapshot package. + * libjava: Add @file support for gjavah & gjar. + * Apply patch for PR rtl-optimization/36111, taken from the trunk. + + * Closing reports reported against gcc-4.0 and fixed in gcc-4.3: + - General + + Fix PR optimization/3511, inlined strlen() could be smarter. + Close: #86251. + - C + + Fix PR c/9072, Split of -Wconversion in two different flags. + Closes: #128950, #226952. + - C++/libstdc++ + + PR libstdc++/24660, implement versioning weak symbols in libstdc++. + Closes: #328421. + - Architecture specific: + - mips + + PR target/26560, unable to find a register to spill in class + 'FP_REGS'. Closes: #354439. + - sparc + + Fix PR rtl-optimization/23454, ICE in invert_exp_1. Closes: #340951. + * Closing reports reported against gcc-4.1 and fixed in gcc-4.2: + - General + + PR tree-optimization/30132, ICE in find_lattice_value. Closes: #400484. + + PR other/29534, ICE in "gcc -O -ftrapv" with decreasing array index. + Closes: #405065. + + Incorrect SSE2 code generation for vector initialization. + Closes: #406442. + + Fix segfault in cc1 due to infinite loop in error() when using -ftrapv. + Closes: #458072. + + Fix regression in code size with -Os compared to GCC-3.3. + Closes: #348298. + - C++ + + Fix initialization of global variables with non-constant initializer. + Closes: #446067. + + Fix ICE building muse. Closes: #429385. + * Closing reports reported against gcc-4.1 and fixed in gcc-4.3: + - C++ + + PR c++/28705, ICE: in type_dependent_expression_p. Closes: #406324. + + PR c++/7302, -Wnon-virtual-dtor should't complain of protected dtor. + Closes: #356316. + + PR c++/28316, PR c++/24791, PR c++/20133, ICE in instantiate_decl. + Closes: #327346, #355909. + - Fortran + + PR fortran/31639, ICE in gfc_conv_constant. Closes: #401496. + - Java + + Fix ICE using gcj with --coverage. Closes: #416326. + + PR libgcj/29869, LogManager class loading failure. Closes: #399251 + + PR swing/29547 setText (String) of JButton does not work + with HTML code. Closes: #392791. + + PR libgcj/29178, CharsetEncoder.canEncode() gives different results + than Sun version. Closes: #388596. + + PR java/8923, ICE when modifying a variable decleared "final static". + Closes: #351512. + + PR java/22507, segfault building Apache Cocoon. Closes: #318534. + + PR java/2499, class members should be inherited from implemented + interfaces. Closes: #225434. + + PR java/10581, ICE compiling freenet. Closes: #186922. + + PR libgcj/28340, gij ignores -Djava.security.manager. Closes: #421098. + + PR java/32846, build failure on GNU/Hurd. Closes: #408888. + + PR java/29194, fails to import package from project. Closes: #369873. + + PR libgcj/31700, -X options not recognised by JNI_CreateJavaVM. + Closes: #426742. + + java.util.Calendar.setTimeZone fails to set ZONE_OFFSET. + Closes: #433636. + - Architecture specific: + - alpha + + C++, fix segfault in constructor with -Os. Closes: #438436. + - hppa + + PR target/30131, ICE in propagate_one_insn. Closes: #397341. + - m32r + + PR target/28508, assembler error (operand out of range). + Closes: #417542. + - m68k + + PR target/34688, ICE in output_operand. Closes: #459429. + * Closing reports reported against gcc-4.2 and fixed in gcc-4.3: + - General + + PR tree-optimization/33826, wrong code generation for infinitely + recursive functions. Closes: #445536. + - C++ + + PR c++/24791, ICE on invalid instantiation of template's static member. + Closes: #446698. + + [Aurelien Jarno] + * Really apply arm-funroll-loops.dpatch on arm and armel. Closes: #476460. + + -- Matthias Klose Sat, 07 Jun 2008 23:16:21 +0200 + +gcc-4.3 (4.3.0-5) unstable; urgency=medium + + * Update to SVN 20080523 from the gcc-4_3-branch. + - Remove gcc-i386-emit-cld patch. + - On Debian amd64 and i386 configure with --enable-cld. + * Fix PR tree-optimization/36129, ICE with -fprofile-use. + * Add spu build dependencies independent of the architecture. + * Move arm -funroll-loops fix to arm-funroll-loops from + gfortran-armel-updates. Apply it on both arm and armel. + Closes: #476460. + * Use iceape-dev as a build dependency for Java enabled builds. + * Build the sru cross compiler from a separate source dir without applying + the hardening patches. + + -- Matthias Klose Fri, 23 May 2008 10:12:02 +0200 + +gcc-4.3 (4.3.0-4) unstable; urgency=low + + [ Aurelien Jarno ] + * Fix gnat-4.3 build on mips/mipsel. + * Update libgcc1 symbols for hurd-i386. + + [ Arthur Loiret ] + * Make gcc-4.3-spu Recommends newlib-spu. Closes: #476088 + * Build depend on spu build dependencies only when building + as gcc-4.x source package. + * Disable spu for snapshot builds. + * Support sh4 targets: + - sh4-multilib.dpatch: Add, fix multilib (m4/m4-nofpu) for sh4-linux + - multiarch-include.dpatch: Don't apply on sh4. + + [ Matthias Klose ] + * Stop building libffi packages. + * Update to SVN 20080501 from the gcc-4_3-branch. + - Fix PR target/35662, wrong gfortran code on mips/mipsel. Closes: #476427. + - Fixes mplayer build on powerpc. Closes: #475153. + * Stop building gij/gcj on alpha, arm and hppa. Closes: #459560. + * libstdc++6-4.3-doc: Fix file location in doc-base file. Closes: #476253. + * debian/patches/template.dpatch: Remove the `exit 0' line. + * Fix alternative names for amd64 cross builds. Addresses: #466422. + * debian/copyright: Update to GPLv3, remove the text of the GFDL + and reference the copy in common-licenses. + * Generate the locale data for the testsuite, if the locales package + is installed (not a dependency on all archs). + * Update libgcc2 symbols for m68k, libstdc++6 symbols for arm, m68k, mips + and mipsel. + * Do not include a symbols file for libobjc_gc.so. + * Add four more symbols to libgcj_bc, patch taken from the trunk. + * Adjust names of manual pages in the spu build on powerpc. + * ARM EABI (armel) updates (Andrew Jenner, Julian Brown): + - Add Objective-C support. + - Fortran support patches. + - Fix ICE in gfortran.dg/vector_subscript_1.f90 for -Os -mthumb reload. + * Build ObjC and Obj-C++ packages on armel. + * Reenable running the testsuite on m68k. + + [Samuel Tardieu, Ludovic Brenta] + * debian/patches/gnalasup_to_lapack.dpatch: new. + * debian/patches/pr34466.dpatch, + debian/patches/pr22255.dpatch, + debian/patches/pr33688.dpatch, + debian/patches/pr10768.dpatch, + debian/patches/pr28305.dpatch, + debian/patches/pr17985.dpatch (#278685) + debian/patches/pr15915.dpatch, + debian/patches/pr16098.dpatch, + debian/patches/pr18680.dpatch, + debian/patches/pr28733.dpatch, + debian/patches/pr22387.dpatch, + debian/patches/pr29015.dpatch: new; backport Ada bug fixes from GCC 4.4. + * debian/patches/rules.patch: apply them. + * debian/patches/pr35050.dpatch: update. + + [Andreas Jochens] + * debian/patches/ppc64-ada.dpatch: update, adding support for ppc64. + (#476868). + + [Ludovic Brenta] + * Apply ppc64-ada.dpatch whenever we build libgnat, not just on ppc64. + * debian/patches/pr28322.dpatch: never pass -Wno-overlength-strings to + the bootstrap compiler, as the patch breaks the detection of whether + the bootstrap compiler supports this option or not. + Fixes: #471192. Works around #471767. + * Merge Aurélien Jarno's mips patch. Fixes: #472854. + + [ Samuel Tardieu ] + * debian/patches/pr30740.dpatch: new Ada bug fix. + * debian/patches/pr35050.dpatch: new Ada bug fix. + + [ Xavier Grave ] + * debian/patches/ada-mips{,el}.dpatch: new; split mips/mipsel support + into new patches, out of ada-sjlj.dpatch. + * debian/rules.d/binary-ada.mk: fix the version number of libgnarl-4.3.a. + + [Roman Zippel] + * PR target/25343, fix gcc.dg/pch/pch for m68k. + + -- Matthias Klose Thu, 01 May 2008 21:08:09 +0200 + +gcc-4.3 (4.3.0-3) unstable; urgency=medium + + [ Matthias Klose ] + * Update to SVN 20080401 from the gcc-4_3-branch. + - Fix PR middle-end/35705 (hppa only). + * Update libstdc++6 symbols for hurd-i386. Closes: #472334. + * Update symbol files for libgomp (ppc64). + * Only apply the gcc-i386-emit-cld patch on amd64 and i386 architectures. + * Update libstdc++ baseline symbols for hppa. + * Install powerpc specific header files new in 4.3. + * gcc-4.3-hppa64: Don't include the install tools in the package. + + [ Aurelien Jarno ] + * Fix gobjc-4.3-multilib dependencies. Closes: #473455. + * Fix gnat-4.3 build on mips/mipsel. + * patches/ada-alpha.dpatch: new patch to fix gnat-4.3 build on alpha. + Closes: #472852. + * patches/config-ml.dpatch: also check for n32 multidir. + + [ Arthur Loiret ] + * Build-Depends on binutils (>= 2.18.1~cvs20080103-2) on mips and mipsel, + required for triarch. + * libstdc++-pic.dpatch: Update, don't fail anymore if shared lib is disabled. + + [ Andreas Jochens ] + * Fix build failures on ppc64. Closes: #472917. + - gcc-multilib64dir.dpatch: Remove "msoft-float" and "nof" from MULTILIB + variables. + - Removed ppc64-biarch.dpatch. + - Add debian/lib32gfortan3.symbols.ppc64. + + [ Arthur Loiret, Matthias Klose ] + * Build compilers for spu-elf target on powerpc and ppc64. + - Add gcc-4.3-spu, g++-4.3-spu and gfortran-4.3-spu packages. + - Partly based on the work in Ubuntu on the spu toolchain. + + -- Matthias Klose Tue, 01 Apr 2008 23:29:21 +0000 + +gcc-4.3 (4.3.0-2) unstable; urgency=low + + [Matthias Klose] + * Update to SVN 20080321 from the gcc-4_3-branch. + - Remove some broken code that attempts to enforce linker + constraints. Closes: #432541. + * Temporary fix, will be removed once a fixed kernel is available + in testing: Emit cld instruction when stringops are used (i386). + Do not expose the -mcld option until added upstream. Closes: #469567. + * Update NEWS files. + * libjava: Don't leak upon failed realloc (taken from the trunk). + * debian/rules2: The build is not yet prepared to take variables from + the environment; unexport and unset those. + + [Arthur Loiret/Aurelien Jarno] + * MIPS tri-arch support: + - mips-triarch.dpatch: new patch to default to o32 and follow the + glibc convention for n32 & 64 bit names. + - Rename $(biarch) and related vars into $(biarch64). + - Fix biarchsubdir to allow triarch. + - Add biarchn32 support. + - Add mips and mipsel to biarch64 and biarchn32 archs. + - Update binary rules for biarchn32 and libn32 targets. + - Fix multilib deps for triarch. + - control.m4: Add libn32 packages. + + -- Matthias Klose Sat, 22 Mar 2008 00:06:33 +0100 + +gcc-4.3 (4.3.0-1) unstable; urgency=low + + [Matthias Klose] + * GCC-4.3.0, final release. + * Update to SVN 20080309 from the gcc-4_3-branch. + * Build from a modified tarball, without GFDL documentation with + invariant sections and cover texts. + * debian/rules.unpack: Avoid make warnings. + * debian/rules.d/binary-cpp.mk: Add 4.3.0 symlink in gcclibdir. + * Stop building treelang (removed upstream). + * gcj-4.3: Hardcode libgcj-bc dependency, don't run dh_shlibdeps on ecj1. + + [Aurelien Jarno] + * Update libssp-gnu.dpatch and reenable it. + + -- Matthias Klose Sun, 09 Mar 2008 15:18:08 +0100 + +gcc-4.3 (4.3.0~rc2-1) unstable; urgency=medium + + * Update to SVN 20080301 from the gcc-4_3-branch. + * Include the biarch libobjc_gc library in the packages. + * Link libobjc_gc with libgcjgc_convenience.la. + * Add new symbols to libstdc++6 symbol files, remove the symbols for + support (reverted upstream for the 4.3 branch). + * Disable running the testsuite on m68k. + * Update PR other/28322, ignore only unknown -W* options. + + -- Matthias Klose Sat, 01 Mar 2008 15:09:16 +0100 + +gcc-4.3 (4.3-20080227-1) unstable; urgency=low + + [Matthias Klose] + * Update to SVN 20080227 from the gcc-4_3-branch. + * Fix PR other/28322, GCC new warnings and compatibility. + Addresses: #367657. + + [Hector Oron] + * Fix cross-compile builds. Closes: #467471. + + -- Matthias Klose Thu, 28 Feb 2008 00:30:38 +0100 + +gcc-4.3 (4.3-20080219-1) unstable; urgency=medium + + [Matthias Klose] + * Update to SVN 20080219 from the gcc-4_3-branch. + * Apply proposed patch for PR target/34571 (alpha). + * libgcj9-dev: Don't claim that the package contains the static + libraries. + * libjava-xulrunner1.9.dpatch: Add configure check for xulrunner-1.9. + Name the alternative xulrunner-1.9-javaplugin.so. + * libgcj-doc: Don't include the examples; these cannot be built + with the existing Makefile anyway. Addresses: #449608. + * Manpages for gc-analyze and grmic are GFDL. Don't include these when + building DFSG compliant packages. + * Fix build failure building amd64 cross-target libstdc++ packages + (Tim Bagot). Addresses: #464365. + * Fix typos in rename-info-files patch (Richard Guenther). + * Fix PR libgcj/24170. + + [Aurelien Jarno] + * kbsd-gnu-ada.dpatch: new patch to fix build on GNU/kFreeBSD. + + [Ludovic Brenta] + * debian/rules.defs: Temporarily disable the testsuite when building gnat. + * debian/patches/libffi-configure.dpatch: run autoconf in the top-level + directory, where we've changed configure.ac; not in src/gcc. + * debian/patches/ada-sjlj.dpatch: do not run autoconf since we don't + change configure.ac. + * debian/control.m4 (gnat-4.3-doc): conflict with gnat-4.[12]-doc. + Closes: #464801. + + -- Matthias Klose Tue, 19 Feb 2008 23:20:45 +0000 + +gcc-4.3 (4.3-20080202-1) unstable; urgency=low + + [ Matthias Klose ] + * Update to SVN 20080202 from the trunk. + - Fix PR c/35017, pedwarns about valid code. Closes: #450506. + - Fix PR target/35045, wrong code generation with -O3 on i386. + Closes: #463478. + * gcj-4.3: On armel depend on g++-4.3. + * Re-enable build of libobjc_gc, using the internal version of boehm-gc. + Closes: #212248. + + [Ludovic Brenta] + * debian/patches/ada-default-project-path.dpatch, + debian/patches/ada-gcc-name.dpatch, + debian/patches/ada-symbolic-tracebacks.dpatch, + debian/patches/ada-link-lib.dpatch, + debian/patches/ada-libgnatvsn.dpatch, + debian/patches/ada-libgnatprj.dpatch, + debian/patches/ada-sjlj.dpatch: adjust to GCC 4.3. + * debian/README.gnat, debian/TODO, + debian/rules.d/binary-ada.mk: merge from gnat-4.2. + * debian/README.maintainers: add instructions for patching GCC. + * debian/patches/ada-driver.dpatch: remove, no longer used. + * debian/patches/libffi-configure.dpatch: do not patch the top-level + configure anymore; instead, rerun autoconf. This allows removing the + patch cleanly. + * debian/rules2: use gnatgcc as the bootstrap compiler, not gcc-4.2. + + -- Matthias Klose Sat, 02 Feb 2008 19:58:48 +0100 + +gcc-4.3 (4.3-20080127-1) unstable; urgency=low + + [ Matthias Klose ] + * Update to SVN 20080126 from the trunk. + * Tighten build dependency on doxygen. + * Update libstdc++ patches to current svn. + * gij-4.3: Provide java*-runtime-headless instead of java*-runtime. + + [ Aurelien Jarno] + * debian/multiarch.inc: change mipsel64 into mips64el. + + -- Matthias Klose Sun, 27 Jan 2008 01:33:35 +0100 + +gcc-4.3 (4.3-20080116-1) unstable; urgency=medium + + * Update to SVN 20080116 from the trunk. + * Update debian/watch. + * Build libgomp documentation without building libgomp. Addresses: #460660. + * Handle lzma compressed tarballs. + * Fix dependency generation for the gcc-snapshot package: Addresses: #454667. + * Restore lost chunk in libjava-subdir.dpatch. + + -- Matthias Klose Wed, 16 Jan 2008 20:33:50 +0100 + +gcc-4.3 (4.3-20080112-1) unstable; urgency=low + + * Update to SVN 20080112 from the trunk. + * Tighten build-dependency on dpkg-dev (closes: #458894). + * Update symbol definitions for alpha. + * Build-depend on libmpfr-dev for all source packages. + + -- Matthias Klose Sun, 13 Jan 2008 00:40:28 +0100 + +gcc-4.3 (4.3-20080104-1) unstable; urgency=low + + * Update to SVN 20080104 from the trunk. + * Update symbol definitions for alpha, hppa, ia64, mips, mipsel, powerpc, + s390, sparc. + + -- Matthias Klose Fri, 04 Jan 2008 07:34:15 +0100 + +gcc-4.3 (4.3-20080102-1) unstable; urgency=low + + [ Matthias Klose ] + * Update to SVN 20080102 from the trunk. + - Fix 64bit biarch builds (addresses: #447443). + * debian/rules.d/binary-java.mk: Reorder packaging to get shlibs + dependencies right. + * Use lib instead of lib64 as multilibdir on amd64 and ppc64. + * Build the java plugin always using libxul-dev. + * Add libgcj_bc to the libgcj9-0 shlibs file. + * Add symbol files for libgcc1, lib32gcc1, lib64gcc1, libstdc++6, + lib32stdc++6, lib64stdc++6, libgomp1, lib32gomp1, lib64gomp1, libffi4, + lib32ffi4, lib64ffi4, libobjc2, lib32objc2, lib64objc2, libgfortran3, + lib32gfortran3, lib64gfortran3. + Adjust build dependencies on dpkg-dev and debhelper. + * Do not build the java packages from the gcc-4.3 source package. + + [ Aurelien Jarno ] + * Disable amd64-biarch patch on kfreebsd-amd64. + + -- Matthias Klose Wed, 02 Jan 2008 23:48:14 +0100 + +gcc-4.3 (4.3-20071124-1) experimental; urgency=low + + [ Matthias Klose ] + * Update to SVN 20071124 from the trunk. + * Fix dependencies of lib*gcc1-dbg packages. + * gcjwebplugin: Fix path of the gcj subdirectory. LP: #149792. + * gij-hppa: Call gij-4.2, not gij-4.1. Addresses: #446282. + * Don't run the testsuite on hppa when expect-tcl8.3 is not available. + * Fix libgcc1-dbg doc directory symlink. Closes: #447969. + + [ Aurelien Jarno ] + * Update kbsd-gnu patch. + * Remove kbsd-gnu-ada patch (merged upstream). + + -- Matthias Klose Sat, 24 Nov 2007 13:14:29 +0100 + +gcc-4.3 (4.3-20070930-1) experimental; urgency=low + + [Matthias Klose] + * Update to SVN 20070929 from the trunk. + * Update debian patches to the current trunk. + * Regenerate the control file. + * On powerpc-linux-gnu and i486-linux-gnu cross-compile the 64bit + multilib libraries to allow a sucessful build on 32bit kernels + (our buildds). Although we won't get 64bit test results this way ... + * Remove the build dependency on expect-tcl8.3. + * Fix MULTILIB_OSDIRNAMES for cross builds targeted for amd64 and ppc64. + * When -fstack-protector is the default (Ubuntu), do not enable + -fstack-protector when -nostdlib is specified. LP: #77865. + * Always set STAGE1_CFLAGS to -g -O2, only pass other settings + when configuring when required. + * Configure --with-bugurl, adjust the bug reporting instructions. + * gcc-4.3: Install new cpuid.h header. + * Fix installation of the s390 libstdc++ biarch headers. + * Install new bmmintrin.h, mmintrin-common.h headers. + * Build -dbg packages for libgcc, libgomp, libmudflap, libffi, libobjc, + libgfortran. + * Downgrade libmudflap-dev recommendation to a suggestion. Closes: #443929. + + [Riku Voipio] + * Configure armeabi with --disable-sjlj-exceptions. + * armel testsuite takes ages, adjust build accordingly. + + -- Matthias Klose Sun, 30 Sep 2007 12:06:02 +0200 + +gcc-4.3 (4.3-20070902-1) experimental; urgency=low + + * Upload to experimental. + + -- Matthias Klose Sun, 2 Sep 2007 20:51:16 +0200 + +gcc-4.3 (4.3-20070902-0ubuntu1) gutsy; urgency=low + + * Update to SVN 20070902 from the trunk. + * Fix the build logic for the Ubuntu i386 buildd; we can't build biarch. + * Only remove libgcj9's classmap db if no other libgcj9* library is + installed. + * A lot more updates for 4.3 packaging. + + -- Matthias Klose Sat, 01 Sep 2007 21:01:43 +0200 + +gcc-4.3 (4.3-20070901-0ubuntu1) gutsy; urgency=low + + * Update to SVN 20070901 from the trunk. + * First gcc-4.3 package build. + - Update patches for the *-linux-gnu builds. + - Update build files for 4.3. + * Add proposed patch for PR middle-end/33029. + * gcj-4.3: Install gc-analyze. + + -- Matthias Klose Sat, 1 Sep 2007 20:52:16 +0200 + +gcc-4.2 (4.2.2-7) unstable; urgency=low + + * Update to SVN 20080114 from the ubuntu/gcc-4_2-branch. + - Fix PR middle-end/34762. LP: #182412. + * Update debian/watch. Closes: #459259. Addresses: #459391, #459392. + * Build libgomp documentation without building libgomp. Closes: #460660. + * Restore gomp development files. Closes: #460736. + + -- Matthias Klose Mon, 14 Jan 2008 23:20:04 +0100 + +gcc-4.2 (4.2.2-6) unstable; urgency=low + + * Update to SVN 20080113 from the ubuntu/gcc-4_2-branch. + * Adjust build-dependency on debhelper, dpkg-dev. + * Fix gnat-4.2 build failure (addresses: #456867). + * Do not build packages built from the gcc-4.3 source. + + -- Matthias Klose Sun, 13 Jan 2008 13:48:49 +0100 + +gcc-4.2 (4.2.2-5) unstable; urgency=low + + [Matthias Klose] + * Update to SVN 20080102 from the ubuntu/gcc-4_2-branch. + - Fix PR middle-end/32889, ICE in delete_output_reload. + Closes: #444873, #445336, #451047. + - Fix PR target/34215, ICE in assign_386_stack_local. + Closes: #446714, #452451. + - Fix PR target/33848, reference to non-existent label at -O1 on + mips/mipsel. Closes: #441633. + * debian/rules.d/binary-java.mk: dpkg-shlibsdeps can't handle the dangling + symlink to libgcj_bc.so.1. Remove it temporarily. + * Add libgcj_bc to the libgcj8-1 shlibs file. + * Fix build failures for gnat-4.2, gpc-4.2, gdc-4.2 introduced by recent + gdc changes. + * Add symbol files for libgcc1, lib32gcc1, lib64gcc1, libstdc++6, + lib32stdc++6, lib64stdc++6, libgomp1, lib32gomp1, lib64gomp1, libffi4, + lib32ffi4, lib64ffi4, libobjc2, lib32objc2, lib64objc2. Adjust build + dependencies on dpkg-dev and debhelper. + Adjust build-dependency on dpkg-dev. + + [Arthur Loiret] + * Fix gdc-4.2 build failure. + * Update gdc to upstream SVN 20071124. + - d-bi-attrs: Support attributes on declarations in other modules. + - d-codegen.cc (IRState::attributes): Support constant declarations as + string arguments. + * Enable libphobos: + - gdc-4.2.dpatch: Fix ICEs. + - gdc-4.2-build.dpatch: Update, make it cleaner. + * Install libphobos in the private gcc lib dir. + * gdc-4.2.dpatch: Update from gdc-4.1.dpatch. + - gcc/tree-sra.c: Do not use SRA on structs with aliased fields created + for anonymous unions. + - gcc/predict.c: Add null-pointer check. + * debian/rules.defs: Disable phobos on hurd-i386. + - gdc-hurd-proc_maps.dpatch: Remove. + + -- Matthias Klose Wed, 02 Jan 2008 15:49:30 +0100 + +gcc-4.2 (4.2.2-4) unstable; urgency=low + + [Matthias Klose] + * Update to SVN 20071123 from the ubuntu/gcc-4_2-branch. + - Fix PR middle-end/34130, wrong code with some __builtin_abs expressions. + Closes: #452108. + * Don't run the testsuite on hppa when expect-tcl8.3 is not available. + * Fix libgcc1-dbg doc directory symlink. Closes: #447969. + * Use gcc-multilib as build-dependency instead of gcc-4.1-mulitlib. + * Support for fast-math on hurd-i386 (Michael Banck). Closes: #451520. + * Fix again profiling support on the Hurd (Thomas Schwinge). Closes: #434937. + + [Arthur Loiret] + * Merge gdc-4.1 patches and build infrastructure: + - gdc-4.2.dpatch: Add, setup gcc-4.2.x for D. + - gdc-4.2-build.dpatch: Add, update gdc builtins and driver objs. + - gdc-driver-zlib.dpatch: Add, use up-to-date system zlib. + - gdc-driver-defaultlib.dpatch: Add, add -defaultlib/-debuglib switches. + - gdc-driver-nophobos.dpatch: Add, disable libphobos when unsupported. + - gdc-libphobos-build.dpatch: Add, enable libphobos build when supported. + - gdc-fix-build.dpatch: Add, fix build on non-biarched 64bits targets. + - gdc-libphobos-std-format.dpatch: Add, replace assert when formating a + struct on non-x86_64 archs by a FormatError. + - gdc-arm-unwind_ptr.dpatch: Add, fix build on arm. + - gdc-mips-gcc-config.dpatch: Add, fix build on mips. + - gdc-hurd-proc_maps.dpatch: Add, fix build on hurd. + + -- Matthias Klose Sat, 24 Nov 2007 12:01:06 +0100 + +gcc-4.2 (4.2.2-3) unstable; urgency=low + + * Update to SVN 20071014 from the ubuntu/gcc-4_2-branch. + - Fix build failure in libjava on mips/mipsel. + * Make 4.2.2-2 a requirement for frontends built from separate sources. + Addresses: #446596. + + -- Matthias Klose Sun, 14 Oct 2007 14:13:00 +0200 + +gcc-4.2 (4.2.2-2) unstable; urgency=low + + * Update to SVN 20071011 from the ubuntu/gcc-4_2-branch. + - Fix PR middle-end/33448, ICE in create_tmp_var. Closes: #439687. + - Remove debian/patches/pr31899.dpatch, applied upstream. + - Remove debian/patches/pr33381.dpatch, applied upstream. + * gij-hppa: Call gij-4.2, not gij-4.1. Addresses: #446282. + + -- Matthias Klose Thu, 11 Oct 2007 23:41:52 +0200 + +gcc-4.2 (4.2.2-1) unstable; urgency=low + + * Update to SVN 20071008 from the ubuntu/gcc-4_2-branch, corresponding + to the GCC-4.2.2 release. + * Fix dependencies of lib*gcc1-dbg packages. Closes: #445190. + * Remove libjava-armeabi patch integrated upstream. + * gcjwebplugin: Fix path of the gcj subdirectory. LP: #149792. + * Apply proposed patch for PR debug/31899. Closes: #445268. + + * Add niagara2 optimization support (David Miller). + + -- Matthias Klose Mon, 08 Oct 2007 21:12:41 +0200 + +gcc-4.2 (4.2.1-6) unstable; urgency=high + + [Matthias Klose] + * Update to SVN 20070929 from the ubuntu/gcc-4_2-branch. + - Fix PR middle-end/33382, ICE (closes: #441481). + - Fix PR tree-optimization/28544 (4.2.1, closes: #380482). + - Fix PR libffi/28313, port to mips64 (closes: #358235). + * Fix PR tree-optimization/33099, PR tree-optimization/33381, + wrong code generation with VRP/SCEV. Closes: #440545, #443576. + * Update Hurd fixes (Samuel Thibault). + * When -fstack-protector is the default (Ubuntu), do not enable + -fstack-protector when -nostdlib is specified. LP: #77865. + * Add -g to BOOT_CFLAGS, set STAGE1_CFLAGS to -g -O, only pass + other settings when required. + * Fix installation of the s390 libstdc++ biarch headers. + * Allow the powerpc build on a 32bit machine (without running the + biarch testsuite). + * Build -dbg packages for libgcc, libgomp, libmudflap, libffi, libobjc, + libgfortran. + * Drop the build dependency on expect-tcl8.3 (the hppa testsuite seems + to complete sucessfully with the expect package). + * Downgrade libmudflap-dev recommendation to a suggestion. Closes: #443929. + + * Closing reports reported against gcc-4.1 and fixed in gcc-4.2: + - General + + PR rtl-optimization/21299, error in invalid asm statement. + Closes: #380121. + - C++ + + PR libstdc++/19664, libstdc++ headers have pop/push of the visibility + around the declarations (closes: #307207, #324290, #423547). + + PR c++/21581, functions in anonymous namespaces default to "hidden" + visibility (closes: #278310). + + PR c++/4882, specialization of inner template using outer template + argument (closes: #269513). + + PR c++/6634, wrong parsing of "long long double" (closes: #247112). + + PR c++/10891, code using dynamic_cast causes segfaults when -fno-rtti + is used (closes: #188943). + + PR libstdc++/14991, stream::attach(int fd) porting entry out-of-date. + Closes: #178561. + + PR libstdc++/31638, string usage leads to warning with -Wcast-align. + Closes: #382153. + + Fix memory hog seen with g++-4.1. Closes: #411234. + - Fortran + + PR fortran/29228, ICE in gfc_trans_deferred_array (closes: #387222). + + PR fortran/24285, allow dollars everywhere in format (closes: #324600). + + PR libfortran/28354, 0.99999 printed as 0. instead of 1. by + format(f3.0). Closes: #397671. + + Fix ICE in gfc_get_extern_function_decl (closes: #396292). + - Architecture specific: + - i386 + + Fix error with -m64 (unable to find a register to spill in class + 'DIREG'). Closes: #430049. + - mips + + Fix ICE in tsubst (closes: #422303). + - s390 + + Fix ICE (segmentation fault) building dcmtk (closes: #435736). + + [Roman Zippel] + * Update the m68k patches. + + [Riku Voipio] + * Configure armeabi with --disable-sjlj-exceptions. + * armel testsuite takes ages, adjust build accordingly. + + [Ludovic Brenta and Xavier Grave] + * Add a version of the Ada run-time library using the setjump/longjump + exception handling mechanism (static library only). Use with + gnatmake --RTS=sjlj. Particularly useful for distributed (Annex E) + programs. + * Restore building libgnatvsn-dev and libgnatprj-dev. + + -- Matthias Klose Sat, 29 Sep 2007 11:19:40 +0200 + +gcc-4.2 (4.2.1-5) unstable; urgency=low + + * Update to SVN 20070825 from the ubuntu/gcc-4_2-branch. + - Fix PR debug/32610, LP: #121911. + * Apply proposed patches: + - Improve debug info for packed arrays with constant bounds + (PR fortran/22244). + - Fix ICE in rtl_for_decl_init on const vector initializers + (PR debug/32914). + - Fix (neg (lt X 0)) optimization (PR rtl-optimization/33148). + - Fix libgcc.a(tramp.o) on ppc32. + - Fix redundant reg/mem stores/moves (PR target/30961). + * Update the -fdirectives-only backport. + * gappletviewer-4.2: Include the gcjwebplugin binary. LP: #131114. + * Update gpc patches and build support (not yet enabled). + * Fix gcc-snapshot hppa64 install target. + * Set the priority of the source package to optional. + * Remove .la files from the biarch libstdc++ debug packages, + conflict with the 3.4 package. Closes: #440490. + + [Arthur Loiret] + * Add build support for GDC. + + -- Matthias Klose Mon, 27 Aug 2007 01:39:32 +0200 + +gcc-4.2 (4.2.1-4) unstable; urgency=medium + + * gcc-4.2: Include missing std*.h header files. + + -- Matthias Klose Tue, 14 Aug 2007 11:14:35 +0200 + +gcc-4.2 (4.2.1-3) unstable; urgency=low + + * Update to SVN 20070812 from the ubuntu/gcc-4_2-branch. + * debian/rules.defs: Fix typo, run the checks in biarch mode too. + * libgcj8-awt: Loosen dependency on gcj-4.2-base. + * Build only needed multilib libraries when building as gcj or gnat. + * Always build biarch libgomp in biarch builds. + * debian/rules2: Adjust testsuite logs files for logwatch.sh. + * Include header files from $/gcc_lib_dir)/include-fixed. + * Backport from trunk: -fdirectives-only (when preprocessing, handle + directives, but do not expand macros). + * Report an ICE to apport (if apport is available and the environment + variable GCC_NOAPPORT is not set) + * Fix gcj build failure on the Hurd (Samuel Thibault). Closes: #437470. + + -- Matthias Klose Sun, 12 Aug 2007 21:11:00 +0200 + +gcc-4.2 (4.2.1-2) unstable; urgency=low + + [Matthias Klose] + * Update to SVN 20070804 from the ubuntu/gcc-4_2-branch (20070804): + - Merge gcc-4_2-branch SVN 20070804. + - Imported classpath CVS 20070727. + - Bump the libgcj soname, add conflict with java-gcj-compat (<< 1.0.76-4). + - Remove patches integrated in the branches: pr32862. + - Update patches: libjava-subdir, libjava-jar. + - Add regenerated class files: svn-class-updates. + + * Fix profiling support on the Hurd (Michael Casadeval). Closes: #434937. + * Fix build on kfreebsd-amd64 (Aurelien Jarno). Closes: #435053. + * Period of grace is over, run the testsuite on m68k-linux again. + * Update infrastructure for the gcc-source package (Bastian Blank). + * Update profiling on the Hurd (Samuel Thibault, Michael Casadevall). + Closes: #433539. + * debian/rules2: Allow DEB_BUILD_OPTIONS=parallel= to overwrite NJOBS. + * Allow lang=, nolang= in DEB_BUILD_OPTIONS; deprecating + WITHOUT_LANG, and WITHOUT_CHECK. + * debian/rules.defs, debian/rules.conf: Cache some often used macros. + + * Preliminary work: Enable Java for ARM EABI (Andrew Haley), build + libffi for armel. + * gcj: Don't build the browser plugin in gcc-snapshot builds to get + rid of the xulrunner dependency. + * gcjwebplugin: Register for more browsers (package currently not built). + * gij/boehm-gc: Use sysconf as fallback, if reading /proc/stat fails. + Closes: #422469. + * libjava: Avoid dependency on MAXHOSTNAMELEN (Samuel Thibault). + * gcj: On arm and armel, use the ecj1 binary built from the ecj package. + * gcj: Don't require javac without java maintainer mode, remove build + dependencies on gcj and ecj, add build dependency on libecj-java. + + -- Matthias Klose Sun, 05 Aug 2007 15:56:07 +0200 + +gcc-4.2 (4.2.1-1) unstable; urgency=medium + + [Ludovic Brenta] + * debian/patches/ada-symbolic-tracebacks.c: remove all trace of + the function convert_addresses from adaint.c. Fixes FTBFS on alpha, + s390 and possibly other platforms. Closes: #433633. + * debian/control.m4: list myself as uploader if the source package name + is gnat. Relax build-dependency on gnat-4.2-source. + * debian/control.m4, debian/rules.conf: Build-depend on libmpfr-dev only + if building Fortran. + + [Matthias Klose] + * debian/rules.conf: Fix breakage of Fortran build dependencies introduced + by merge of the Ada bits. + * Don't include the gccbug binary anymore in the gcc package; upstream bug + reports should be reported to the upstream bug tracker at + http://gcc.gnu.org/bugzilla. + * Don't build and test libjava for the biarch architecture. + * Install gappletviewer man page. Addresses: #423094. + * debian/patches/m68k-java.dpatch: Readd. + * gjar: support @ arguments. + * Update to SVN 20070726 from the ubuntu/gcc-4_2-branch. + - Fix mips/mipsel builds. + * libmudflap0: Fix update leaving an empty doc dir. Closes: #428306. + * arm/armel doesn't have ssp support. Closes: #433172. + * Update kbsd-gnu-ada patch (Aurelien Jarno): Addresses: #434754. + * gcj-4.2: Build depend on gcj-4.2 to build the classpath examples files + for the binary-indep target. + * Fix PR java/32862, bugs in EnumMap implementation. Addresses: #423160. + + [Arthur Loiret] + * Fix cross builds targeting x86_64. Closes: LP: #121834. + + -- Matthias Klose Thu, 26 Jul 2007 21:46:03 +0200 + +gcc-4.2 (4.2.1-0) unstable; urgency=low + + [Matthias Klose] + * Update to SVN 20070719 from the ubuntu/gcc-4_2-branch, corresponding + to the GCC-4.2.1 release. + - debian/patches/arm-gij.dpatch: Remove. Closes: #433714. + * Apply proposed patch for PR tree-optimization/32723. + * Tighten build dependency on libmpfr-dev. + * On ia64, apply proposed patch for PR target/27880. Closes: #433719. + + [Hector Oron] + * Fix cross and reverse-cross builds. Closes: #432356. + + -- Matthias Klose Thu, 19 Jul 2007 17:59:37 +0200 + +gnat-4.2 (4.2-20070712-1) unstable; urgency=low + + * debian/rules.d/binary-ada.mk, debian/control.m4: + disable building libgnatvsn-dev and libgnatprj-dev, as they conflict + with packages from gnat-4.1. Will reenable them for the transition to + gnat-4.2. + * Upload as gnat-4.2. Closes: #432525. + + -- Ludovic Brenta Sat, 14 Jul 2007 15:12:34 +0200 + +gcc-4.2 (4.2-20070712-1) unstable; urgency=high + + [Matthias Klose] + * Update to SVN 20070712 from the ubuntu/gcc-4_2-branch. + - 4.2.1 RC2, built from SVN. + - same as gcc-4_2-branch, plus backport of gcc/java, boehm-gc, libffi, + libjava, zlib from the trunk. + - debian/patches/arm-libffi.dpatch: Remove. + - Fixes ICE in update_equiv_regs. Closes: #432604. + * debian/control.m4: Restore build dependency on dejagnu. + * debian/patches/arm-gij.dpatch: Update. + * i386-biarch.dpatch: Update for the backport for PR target/31868. + Closes: #432599. + + -- Matthias Klose Fri, 13 Jul 2007 08:07:51 +0200 + +gcc-4.2 (4.2-20070707-1) unstable; urgency=low + + [Matthias Klose] + * Update to SVN 20070707 from the ubuntu/gcc-4_2-branch. + - debian/patches/libjava-soname.dpatch: Remove. + - debian/patches/disable-configure-run-check.dpatch: Update. + * Only suggest multilib packages on multilib architectures. + * Point ICE messages to the 4.2 docdir. + * Explicitely use fastjar to build gcj-4.1. Addresses: #416001. + * Configure with --enable-libgcj on m32r (Kazuhiro Inaoka). + * Include the hppa64 cross compiler on hppa snapshot builds. + * debian/patches/arm-libffi.dpatch: Update. + * libgcj-doc: Include the generated documentation. + * Fix building the libjava/classpath examples. + * Support reverse cross builds (Neil Williams). Closes: #431086. + + -- Matthias Klose Sat, 07 Jul 2007 10:59:26 +0200 + +gcc-4.2 (4.2-20070627-1) unstable; urgency=high + + [Matthias Klose] + * Update to SVN gcc-4_2-branch/20070626. + * Update to SVN trunk/20070626 (gcc/java, libjava, libffi, boehm-gc). + * On mips*-linux, always imply -lpthread for -pthread (Thiemo Seufer). + Addresses: #428741. + * Fix libstdc++ cross builds (Arthur Loiret). Closes: #430395. + * README.Debian: Point to debian-toolchain for general toolchain topics. + * Use the generated locales for the libstdc++ build to fix the setting + of the gnu locale model. Closes: #428926, #429660. + * For ix86 lpia targets, configure --with-tune=i586. + * Make build dependency on gcc-4.1-multilib architecture specific. + * Do not ignore bootstrap comparision failure on ia64. + + [Ludovic Brenta] + * ada-link-lib.dpatch: update to apply cleanly on GCC 4.2. + * ada-libgnat{vsn,prj}.dpatch: adjust to GCC 4.2. Reenable in rules.patch. + * rules.conf: do not build libgomp as part of gnat-4.2. + * rules.conf, control.m4: build-depend on libz-dev, lib32z-dev or + lib64-dev only when building Java. + * rules2, rules.defs: $(with_mudflap): remove, use $(with_libmudflap) only. + * config.m4, binary-ada.mk: tighten dependencies; no Ada package depends + on gcc-4.2-base anymore. + * TODO: rewrite. + * README.gnat: include in gnat-4.2-base. Remove outdated information. + * README.maintainers: new. Include in gnat-4.2-base. + + [Hector Oron] + * Merge DEB_CROSS_INDEPENDENT with DEB_CROSS. + * Disables libssp0 for arm and armel targets when cross compiling. + * Updates README.cross. + * Fixes linker mapping problem on binary-libstdcxx-cross.mk. Closes: #430688. + + -- Matthias Klose Wed, 27 Jun 2007 21:54:08 +0200 + +gcc-4.2 (4.2-20070609-1) unstable; urgency=low + + * Update to SVN gcc-4_2-branch/20070609. + - Remove patches integrated upstream: pr30052, hppa-caller-save-pic-tls. + * Update to SVN trunk/20070609 (gcc/java, libjava, libffi, boehm-gc). + - Remove patches integrated upstream: libjava-qt-peer, + classpath-config-guess. + * Do not build with --enable-java-maintainer-mode. + * debian/rules.patch: Comment out m68k-peephole, requires m68k-split_shift. + * Add target to apply patches up to a specific patch (Wouter Verhelst). + Closes: #424855. + * libstdc++6-4.2-*: Add conflicts with 4.1 packages. Closes: #419511. + * Apply proposed fix for PR target/28102. Closes: #426905. + * Fix build failure for cross compiler builds (Jiri Palecek). Closes: #393897. + * Update build macros for kfreebsd-amd64. Closes: #424693. + + -- Matthias Klose Sat, 9 Jun 2007 06:54:13 +0200 + +gcc-4.2 (4.2-20070528-1) unstable; urgency=low + + * Update to SVN gcc-4_2-branch/20070528. + * Add backport for PR middle-end/20218. + * Add proposed PTA solver backport, PR tree-optimization/30052. + * Add backport for PR target/31868. + * Reenable the testsuite for arm, mips, mipsel. + + -- Matthias Klose Mon, 28 May 2007 09:03:04 +0200 + +gcc-4.2 (4.2-20070525-1) unstable; urgency=low + + * Update to SVN gcc-4_2-branch/20070525. + * Update to SVN trunk/20070520 (gcc/java, libjava, libffi, boehm-gc). + * Do not explicitely configure for __cxa_atexit. + * libstdc++6-4.2-doc: Conflict with libstdc++6-4.1-doc. Closes: #424896. + * Update m68k patches: + - Remove patches applied upstream: m68k-jumptable, m68k-gc, + - Reenable patches: m68k-save_pic, m68k-dwarf, m68k-limit_reload, + m68k-prevent-qipush, m68k-peephole, m68k-return, m68k-sig-unwind, + m68k-align-code m68k-align-stack, m68k-symbolic-operand, + m68k-bitfield-offset. + - Update: m68k-return, m68k-secondary-addr-reload, m68k-notice-move + m68k-secondary-addr-reload, m68k-notice-move. + - TODO: m68k-split_shift, m68k-dwarf3, m68k-fpcompare. + * Update the kfreebsd and arm patches (Aurelien Jarno). Closes: #425011. + * Temporarily disable the testsuite on slow architectures to get the + package built soon. + + -- Matthias Klose Fri, 25 May 2007 07:14:36 +0200 + +gcc-4.2 (4.2-20070516-1) unstable; urgency=low + + * Update to SVN gcc-4_2-branch/20070516. + * Update to SVN trunk/20070516 (gcc/java, libjava, libffi, boehm-gc). + * Merge changes from gcc-4.1_4.1.2-7. + * Update NEWS files. + + -- Matthias Klose Wed, 16 May 2007 02:33:57 +0200 + +gcc-4.2 (4.2-20070502-1) unstable; urgency=low + + * Update to SVN gcc-4_2-branch/20070502. + - Remove pr11953 patch, integrated upstream. + * Update to SVN trunk/20070502 (gcc/java, libjava, libffi, boehm-gc). + * Adjust tetex/tex-live build dependency. + * Fix gobjc-4.2's, gobjc++-4.2's dependency on libobjc2. + * Tighten (build) dependency on binutils. Addresses: #421197. + * gfortran-4.2: Depend on libgfortran2, provide the libgfortran.so + symlink. Adresses: #421362. + * Build-depend on gcc-multilib [amd64 i386 powerpc ppc64 s390 sparc]. + * (Build-) depend on glibc (>= 2.5) for all architectures. + * Remove libssp packages from the control file. + + -- Matthias Klose Wed, 2 May 2007 18:46:57 +0200 + +gcc-4.2 (4.2-20070405-1) experimental; urgency=low + + * Update to SVN gcc-4_2-branch/20070405. + * Update to SVN trunk/20070405 (gcc/java, libjava, libffi, boehm-gc). + * gcc-4.2-hppa64: Don't depend on libc6-dev. + * Robustify setting of make's -j flag. Closes: #410919. + * gcc-snapshot: Use the install_snap_stamp target for installation. + + -- Matthias Klose Thu, 5 Apr 2007 23:56:35 +0200 + +gcc-4.2 (4.2-20070307-1) experimental; urgency=low + + * Update to SVN gcc-4_2-branch/20070307. + * Update to SVN trunk/20070307 (gcc/java, libjava, libffi, boehm-gc). + * Build gnat from separate sources. + * Merge changes from gcc-4.1-4.1.2-1. + * Install into /usr/lib/gcc//4.2, to ease upgrades + between subminor versions. + * Configure --with-gxx-include-dir=/usr/include/c++/4.2 + + -- Matthias Klose Thu, 8 Mar 2007 02:52:00 +0100 + +gcc-4.2 (4.2-20070210-1) experimental; urgency=low + + * Merge Java backport from Ubuntu: + - Update to SVN gcc-4_2-branch/20070210. + - Update to SVN trunk/20070210 (gcc/java, libjava). + - Backout trunk specific gcc/java changes. + - Build-depend on gcj-4.1 and ecj-bootstrap. + - gcj-4.2: Depend on ecj-bootstrap, recommend ecj-bootstrap-gcj. + - Merge libgcj8-awt-gtk back into libgcj8-awt; the Qt peers + are disabled by upstream again. + - Generate manual pages for the classpath tools from the classpath + documentation. + - Adopt packaging for the merged libjava. + - Update patches for the merged libjava: libjava-lib32-properties, + i386-biarch, reporting, libjava-soname, libjava-subdir, + libjava-lib32subdir. + - Remove obsolete patches: libjava-plugin-binary, libjava-ia32fix, + libstdc++-docfixes. + + * Set priority of development packages to optional. + * debian/libgcjGCJ.postrm: Don't fail on purge when directories + don't exist anymore. Closes: #406017. + * debian/patches/gcc-textdomain.dpatch: Update for 4.2. + * Generate and install libgomp docs into gcc-4.2-doc. + + -- Matthias Klose Sat, 10 Feb 2007 16:53:11 +0100 + +gcc-4.2 (4.2-20070105-1) experimental; urgency=low + + * Update to SVN 20070105. + * Add tetex-extra to Build-Depend-Indep (libstd++ doxygen docs), + fix doxygen build (libstdc++-docfixes.dpatch). + * Enable parallel build by default on SMP machines. + + -- Matthias Klose Fri, 5 Jan 2007 22:42:18 +0100 + +gcc-4.2 (4.2-20061217-1) experimental; urgency=low + + * Update to SVN 20061217. + * Merge changes from gcc-4.1_4.1.1-16 to gcc-4.1_4.1.1-21. + * Update patches to the current branch. + * Add multilib packages for gcc, g++, gobjc, gobjc++, gfortran. + * Link using --hash-style=gnu (alpha, amd64, ia64, i386, powerpc, ppc64, + s390, sparc). + + -- Matthias Klose Sun, 17 Dec 2006 15:54:54 +0100 + +gcc-4.2 (4.2-20061003-1) experimental; urgency=low + + * libgcj.postinst: Remove /var/lib/gcj-4.2 on package removal. + * Don't install backup files in the doc directory, only one gcc-4.1 + upgrade was broken. Closes: #389366. + * Merge gcc-biarch-generic.dpatch into i386-biarch.dpatch. + * Update link-libs.dpatch. + * Merge libgfortran2-dev into gfortran-4.2. + + -- Matthias Klose Tue, 3 Oct 2006 16:26:38 +0000 + +gcc-4.2 (4.2-20060923-1) experimental; urgency=low + + * Update to SVN 20060923. + * Remove patches applied upstream: kbsd-gnu-java, kbsd-gnu. + + -- Matthias Klose Sat, 23 Sep 2006 15:11:36 +0200 + +gcc-4.2 (4.2-20060905-1) experimental; urgency=low + + * Update to SVN 20060905. + * Merge changes from gcc-4.1 (4.1.1-10 - 4.1.1-12). + * Move gomp development files into gcc and gfortran. + * Build-depend on binutils (>= 2.17). + + -- Matthias Klose Tue, 5 Sep 2006 03:33:00 +0200 + +gcc-4.2 (4.2-20060818-1) experimental; urgency=low + + * Update to SVN 20060818. + - libjava-libgcjbc.dpatch: Remove, applied upstream. + * Merge changes from the Ubuntu gcj-4.2 package: + - libjava-soname.dpatch: Remove, applied upstream. + - libjava-native-libdir.dpatch: update. + - libffi-without-libgcj.dpatch: Remove, new libffi-configure to + enable --disable-libffi. + - Changes required for the classpath-0.92 update: + - New packages gappletviewer-4.2, gcjwebplugin-4.2. + - gij-4.2: Add keytool alternative. + - gcj-4.2: Add jarsigner alternative. + - libgcj8-dev: Remove conflicts with older libgcjX-dev packages. + - lib32gcj8: Populate the /usr/lib32/gcj-4.2 directory. + - libjava-library-path.dpatch: + - When running the i386 binaries on amd64, look in + /usr/lib32/gcj-x.y and /usr/lib32/jni instead. + - Add /usr/lib/jni to java.library.path. Adresses: #364820. + - Add more debugging symbols to libgcj8-dbg. Adresses: #383705. + - Fix and renable the biarch build for sparc. + * Disable gnat for alpha, fails to build. + * Configure without --enable-objc-gc, fails to build. + + -- Matthias Klose Sat, 19 Aug 2006 18:25:50 +0200 + +gcc-4.2 (4.2-20060709-1) experimental; urgency=low + + * Test build, SVN trunk 20060709. + * Merge libssp0-dev into gcc-4.1 (-fstack-protector is a common option). + * Rename libmudflap0-dev to libmudflap0-4.2-dev. + * Ignore compiler warnings when checking whether compiler driver understands + Ada fails. + * Merge changes from the gcc-4.1 package. + + -- Matthias Klose Sun, 9 Jul 2006 14:28:03 +0200 + +gcc-4.2 (4.2-20060617-1) experimental; urgency=low + + * Test build, SVN trunk 20060617. + + [Matthias Klose] + * Configure using --enable-objc-gc, using the internal boehm-gc. + * Build-depend on bison (>= 1:2.3). + * Build the QT based awt peer library, not yet the same functionality + as the GTK based peer library. + * Update libjava-* patches. + + [Ludovic Brenta] + * Do not provide the symbolic link /usr/bin/gnatgcc; this will now + be provided by package gnat from the source package gcc-defaults. + * debian/control.m4, debian/control (gnat): conflict with gnat (<< 4.1), + not all versions of gnat, since gcc-defaults will now provide gnat (= 4.1) + which depends on gnat-4.1. + + [Bastian Blank] + * Make it possible to overwrite arch per DEB_TARGET_ARCH and + DEB_TARGET_GNU_TYPE. + * Disable biarch only on request for cross builds. + * Use correct source directory for tarballs. + * Produce correct multiarch.inc for source builds. + + -- Matthias Klose Sat, 17 Jun 2006 19:02:01 +0200 + +gcc-4.2 (4.2-20060606-1) experimental; urgency=low + + * Test build, SVN trunk 20060606. + * Remove obsolete patches, update patches for 4.2. + * Update the biarch-include patches to work with mips-triarch. + * Disable Ada, not yet updated. + * New packages: libgomp*. + * Remove fastjar, not included upstream anymore. + + -- Matthias Klose Tue, 6 Jun 2006 10:52:28 +0200 + +gcc-4.1 (4.1.2-12) unstable; urgency=high + + * i386-biarch.dpatch: Update for the backport for PR target/31868. + Closes: #427185. + * m68k-libffi2.dpatch: Update. Closes: #425399. + + -- Matthias Klose Mon, 4 Jun 2007 23:53:23 +0200 + +gcc-4.1 (4.1.2-11) unstable; urgency=low + + * Update to SVN 20070601. + * Build the libmudflap0-dev package again. + * Don't build libffi, when the packages are not built. + + -- Matthias Klose Fri, 1 Jun 2007 23:55:22 +0200 + +gcc-4.1 (4.1.2-10) unstable; urgency=low + + * Regenerate the control file. + + -- Matthias Klose Wed, 30 May 2007 00:29:29 +0200 + +gcc-4.1 (4.1.2-9) unstable; urgency=low + + * Update to SVN 20070528. + * Don't build packages now built from the gcc-4.2 source (arm, m68k, + mips, mipsel). + * Add backport for PR middle-end/20218. + * Add backport for PR target/31868. + + -- Matthias Klose Tue, 29 May 2007 00:01:12 +0200 + +gcc-4.1 (4.1.2-8) unstable; urgency=low + + * Update to SVN 20070518. + * Don't build packages now built from the gcc-4.2 source. + + [ Aurelian Jarno ] + * Update libffi patch for ARM. Closes: #425011. + * arm-pr30486, arm-pr28516, arm-unbreak-eabi-armv4t: New. + * Disable FFI, Java, ObjC for armel. + + -- Matthias Klose Sun, 20 May 2007 10:31:24 +0200 + +gcc-4.1 (4.1.2-7) unstable; urgency=low + + * Update to SVN 20070514. + * Link using --hash-style=both on supported architectures. Addresses: #421790. + * On hppa, build ecjx as a native binary. + * note-gnu-stack.dpatch: Fix ARM comment marker (Daniel Jacobowitz). + Closes: #422978. + * Add build dependency on libxul-dev for *-freebsd. Closes: #422995. + * Update config.guess/config.sub and build gcjwebplugin on GNU/kFreeBSD + (Aurelian Jarno). Closes: #422995. + * Disable ssp on hurd-i386. Closes: #423757. + + -- Matthias Klose Mon, 14 May 2007 08:40:08 +0200 + +gcc-4.1 (4.1.2-6) unstable; urgency=low + + * Update libjava from the gcc-4.1 Fedora branch 20070504. + * gfortran-4.1: Fix the target of the libgfortran.so symlink. + Closes: #421362. + * Build-depend on gcc-multilib [amd64 i386 powerpc ppc64 s390 sparc]. + * Readd build dependency on binutils on arm. + * (Build-) depend on glibc (>= 2.5) for all architectures. + * Remove libssp packages from the control file. + * Fix wrong code generation on hppa when TLS variables are used. + Closes: #422421. + + -- Matthias Klose Sun, 6 May 2007 10:00:23 +0200 + +gcc-4.1 (4.1.2-5) unstable; urgency=low + + * Update to SVN 20070429. + * Update libjava from the gcc-4.1 Fedora branch 20070428. + * Update m68k patches: + - Remove pr25514, pr27736, applied upstream. + - Update m68k-java. + * Link using --hash-style=gnu/both. + * Tighten (build) dependency on binutils. Closes: #421197. + * gij-4.1: Add a conflict with java-gcj-compat (<< 1.0.69). + * gfortran-4.1: Depend on libgfortran1, provide the libgfortran.so + symlink. Closes: #421362. + * gcc-4.1, gcc-4.1-multilib: Fix compatibility symlinks. Closes: #421382. + * Temporarily remove build dependency on locales on arm, hppa, m68k, mipsel. + * Temporarily remove build dependency on binutils on arm. + * Fix FTBFS on GNU/kFreeBSD (Aurelian Jarno). Closes: #421423. + * gij-4.1 postinst: Create /var/lib/gcj-4.1. Closes: #421526. + + -- Matthias Klose Mon, 30 Apr 2007 08:13:32 +0200 + +gcc-4.1 (4.1.2-4) unstable; urgency=medium + + * Update to SVN 20070423. + - Remove pr11953, applied upstream. + - Fix ld version detection in libstdc++v3. + * Update libjava from the gcc-4.1 Fedora branch 20070423. + * Merge libgfortran1-dev into gfortran-4.1. + * Add multilib packages for gcc, g++, gobjc, gobjc++, gfortran. + * Don't link using --hash-style=gnu/both; loosen dependency on binutils. + * Don't revert the patch to fix PR c++/27227. + + -- Matthias Klose Mon, 23 Apr 2007 23:13:14 +0200 + +gcc-4.1 (4.1.2-3) experimental; urgency=low + + * Update to SVN 20070405. + * Update libjava from the gcc-4.1 Fedora branch 20070405. + * Robustify setting of make's -j flag. Closes: #414316. + * Only build the libssp packages, when building the common libraries. + * gcc-4.1-hppa64: Don't depend on libc6-dev. + + -- Matthias Klose Fri, 6 Apr 2007 00:28:29 +0200 + +gcc-4.1 (4.1.2-2) experimental; urgency=low + + * Update to SVN 20070306. + * Update libjava from the gcc-4.1 Fedora branch 20070306. + + [Matthias Klose] + * Don't install gij-wrapper anymore, directly register gij as a java + alternative. + * Don't install gcjh-wrapper anymore. + * Don't use exact versioned dependencies on gcj-base for libgcj and + libgcj-awt. + * Fix glibc build dependency for alpha. + * Support -ffast-math on hurd-i386 (Samuel Thibault). Closes: #413342. + * Update kfreebsd-amd64 patches (Aurelien Jarno). Closes: #406015. + * gij: Consistently use $(dbexecdir) to reference the gcj sub dir. + * Install into /usr/lib/gcc//4.1, to ease upgrades + between minor versions. + Add compatibility symlinks in /4.1.2 to build gnat-4.1 + and gcj-4.1 from separate sources. + + -- Matthias Klose Wed, 7 Mar 2007 03:51:47 +0100 + +gcc-4.1 (4.1.2-1) experimental; urgency=low + + [Matthias Klose] + * Update to gcc-4.1.2. + * Update libjava backport patches, split out boehm-gc-backport patch. + * Enable the cpu-default-generic patch (i386, amd64), backport from 4.2. + * Correct mfctl instruction syntax (hppa), backport from the trunk. + * Backport PR java/9861 (name mangling updates). + * gcc.c (main): Call expandargv (backport from 4.2). + * Apply gcc dwarf2 unwinding patches from the trunk. + * Apply backport for PR 20208 on amd64 i386 powerpc ppc64 sparc s390. + * Apply patches from the 4.1 branch for PR rtl-optimization/28772, + PR middle-end/30313, PR middle-end/30473, PR c++/30536, PR debug/30189, + PR fortran/30478, PR rtl-optimization/30787, PR tree-optimization/30823, + PR rtl-optimization/28173, PR ada/30684, bug in pointer dependency test, + PR rtl-optimization/30931, PR fortran/25392, PR fortran/30400, + PR libgfortran/30910, PR libgfortran/30918, PR fortran/29441, + PR target/30634. + * Update NEWS files. + * Include a backport of the ecj+generics java updates as + gcj-ecj-20070215.tar.bz2. Install it into the gcc-4.1-source package. + * Do not build fastjar anymore from this source. + * debian/control.m4: Move expect-tcl8.3 before dejagnu. + * Work around firefox/icewhatever dropping plugin dependencies on xpcom. + * Refactor naming of libgcj packages in the build files. + * Make libstdc++-doc's build dependencies depending on the source package. + * Do not build packages on architectures, which are already built by gcc-4.2. + + * Merge the gcj generics backport from Ubuntu: + + - Merge the Java bits (eclipse based compiler, 1.5 compatibility, + classpath generics) from the gcc-4.1 Fedora branch. + - Drop all previous patches from the classpath-0.93 merge, keep + the boehm-gc backport (splitted out as a separate patch). + - Add a gcj-ecj-generics.tar.bz2 tarball, containing gcc/java, libjava, + config/unwind_ipinfo.m4, taken from the Fedora branch. + - Drop the libjava-hppa, libjava-plugin-binary, pr29362, pr29805 patches + integrated in the backport. + - Update patches for the merge: reporting, libjava-subdir, i386-biarch, + classpath-tooldoc, pr26885 + - Add libjava-dropped, libjava-install; dropped chunks from the merge. + - Add pr9861-nojava mangling changes, non-java parts for PR 9861. + - Add gcc-expandv, expand `@' parameters on the commandline; backport + from the trunk. + - Disable the m68k-gc patch, needs update for the merge. + - Configure --with-java-home set for 1.5.0. + - Configure with --enable-java-maintainer-mode to build the header + and class files on the fly. + - Add build dependency on ecj-bootstrap, configure --with-ecj-jar. + - Build an empty libgcj-doc package; gjdoc currently cannot handle + generics. + - Apply gcc dwarf2 unwinding patches from the trunk, allowing the Events + testcase to pass. + - Tighten dependencies on shared libraries. + - Use /usr/lib/gcj-4-1-71 as private gcj subdir. + - Bump the libgcj soversion to 71, rename the libgcj7-0 package + to libgcj7-1, rename the libgcj7-awt package to libgcj7-1-awt. + - gij-4.1: Add and provide alternatives for gorbd, grmid, gserialver. + - gcj-4.1: Remove gcjh, gcjh-wrapper, gjnih. + - gcj-4.1: Add and provide alternatives for jar, javah, native2ascii, + tnameserv. + - gcj-4.1: Add dependency on ecj-bootstrap, recommend fastjar, + ecj-bootstrap-gcj. + - Add build dependency on ecj-bootstrap version providing the GCCMain + class. + - libgcj7-1: Recommend libgcj7-1-awt. + - Add build dependency on libmagic-dev. + - Build-depend on gcj-4.1; build our own ecj1 and gjdoc before + starting the build. + - Make ecj1 available when running the testsuite. + - Fix build failure on sparc-linux. + - Fix gjavah compatibility problems (PR cp-tools/3070[67]). + - Fixed driver issue source files (PR driver/30714). + - Add (rudimentary) manual pages for classpath tools. + + [Kevin Brown] + * debian/control.m4, debian/rules.d/binary-ada.mk: provide new packages + containing debugging symbols for Ada libraries: libgnat-4.1-dbg, + libgnatprj4.1-dbg, and libgnatvsn4.1-dbg. Adresses: #401385. + + -- Matthias Klose Sat, 3 Mar 2007 23:12:08 +0100 + +gcc-4.1 (4.1.1ds2-30) experimental; urgency=low + + * Update to SVN 20070106. + * Do not revert the fixes for PR 25878, PR 29138, PR 29408. + * Don't build the packages built by gcc-4.2 source. + * debian/patches/note-gnu-stack.dpatch: Add .note.GNU-stack sections + for gcc's crt files, libffi and boehm-gc. Taken from FC. Closes: #382741. + * Merge from Ubuntu: + - Backport g++ visibility patches from the FC gcc-4_1-branch. + - Update the long-double patches; require glibc-2.4 as a build dependency + on alpha, powerpc, sparc, s390. Bump the shlibs dependencies to + require 4.1.1-21. + - On powerpc-linux configure using --enable-secureplt. Closes: #382748. + - When using the cpu-default-generic patch, build for generic x86-64 + on amd64 and i386 biarch. + - Link using --hash-style=both (alpha, amd64, ia64, i386, powerpc, ppc64, + s390, sparc). + * gij-4.1: Recommends libgcj7-awt instead of suggesting it. Closes: #394917. + * Split the gcc-long-double patch into a code and doc part. + * Set priority of development packages to optional. + * Add support for kfreebsd-amd64 (Aurelian Jarno). Closes: #406015. + + -- Matthias Klose Sat, 6 Jan 2007 10:35:42 +0100 + +gcc-4.1 (4.1.1ds2-22) unstable; urgency=high + + * Enable -pthread for GNU/Hurd (Michael Banck). Closes: #400031. + * Update the m68k-fpcompare patch (Roman Zippel). Closes: #401585. + + -- Matthias Klose Sun, 10 Dec 2006 12:35:06 +0100 + +gcc-4.1 (4.1.1ds2-20) unstable; urgency=low + + [Matthias Klose] + * Update to SVN 20061115. + - Fix PR tree-optimization/27891, ICE in tree_split_edge. + Closes: #370248, #391657, #394630. + - Fix PR tree-optimization/9814, duplicate of PR tree-optimization/29797. + Closes: #181096. + * Apply the libjava/net backport from the redhat/gcc-4_1-branch. + * Apply proposed patch for PR java/29805. + + [Roman Zippel] + * Build the ObjC and ObjC++ compilers in cross builds. + * debian/patches/m68k-symbolic-operand.dpatch: Better recognize + symbolic operands in addresses. + * debian/patches/m68k-bitfield-offset.dpatch: Only use constant offset + for register bitfields (combine expects shifts, but does a rotate). + * debian/patches/m68k-bitfield-offset.dpatch: Update and apply. + + [Daniel Jacobowitz] + * Don't try to use _Unwind_Backtrace on SJLJ targets. + See bug #387875, #388505, GCC PR 29206. + + -- Matthias Klose Wed, 15 Nov 2006 08:59:53 -0800 + +gcc-4.1 (4.1.1ds2-19) unstable; urgency=low + + * Fix typo in arm-pragma-pack.dpatch. + + -- Matthias Klose Sat, 28 Oct 2006 11:04:00 +0200 + +gcc-4.1 (4.1.1ds2-18) unstable; urgency=medium + + [Matthias Klose] + * Update to SVN 20061028. + * Fix #pragma pack on ARM (Paul Brook). Closes: #394703. + * Revert PR c++/29138, PR c++/29408. Closes: #392559. + * Revert PR c++/25878. Addresses: #387989. + * fastjar: Provide jar. Closes: #395397. + + [Ludovic Brenta] + * debian/control.m4 (libgnatprj-dev): depend on libgnatvsn-dev. + debian/gnatprj.gpr: with gnatvsn.gpr. Closes: #395000. + + -- Matthias Klose Thu, 26 Oct 2006 23:51:10 +0200 + +gcc-4.1 (4.1.1ds2-17) unstable; urgency=low + + [Matthias Klose] + * Update to SVN 20061020. + - Fix PR debug/26881, ICE in dwarf2out_finish. Closes: #377613. + - Fix PR PR c++/29408, parse error for valid code. Closes: #392327, #393010. + - Fix PR c++/29435, segfault with sizeof and templates. Closes: #393071. + - Fix PR target/29338, segfault with -finline-limit on arm. Closes: 390620. + - Fix 3.4/4.0 backwards compatibility problem in libstdc++. + * Fix PR classpath/29362, taken from the redhat/gcc-4_1-branch. + * Remove the INSTALL directory from the source tarball. Closes: #392974. + * Disable building the static libgcj; non-functional, and cutting + down build times. + * libgcj7-0: Tighten dependency on libgcj-common. + * libgcj7-dev: Install .pc file as libgcj-4.1.pc. + * README.cross: Updated (Hector Oron). Addresses: #380251. + * config-ml.dpatch: Use *-linux-gnu as *_GNU_TYPE. Closes: #394034. + + [Nikita V. Youshchenko] + * Fix typo in the cross build scripts. Closes: #391445. + + [Falk Hueffner] + * alpha-no-ev4-directive.dpatch: Fix kernel build failure. + + [Roman Zippel] + * debian/patches/m68k-align-code.dpatch: Use "move.l %a4,%a4" to advance + within code. + * debian/patches/m68k-align-stack.dpatch: Try to keep the stack word aligned. + * debian/patches/m68k-dwarf3.dpatch: Emit correct dwarf info for cfa offset + and register with -fomit-frame-pointer. + * debian/patches/m68k-fpcompare.dpatch: Bring fp compare early to its + desired form to relieve reload. Closes: #390879. + * debian/patches/m68k-prevent-swap.dpatch: Don't swap operands + during reloads. + * debian/patches/m68k-reg-inc.dpatch: Reinsert REG_INC notes after splitting + an instruction. + * debian/patches/m68k-secondary-addr-reload.dpatch: Add secondary reloads + to allow reload to get byte values into addr regs. Closes: #385327. + * debian/patches/m68k-symbolic-operand.dpatch: Better recognize symbolic + operands in addresses. + * debian/patches/m68k-limit_reload.dpatch: Remove, superseded by + m68k-secondary-addr-reload.dpatch. + * debian/patches/m68k-notice-move.dpatch: Apply, was checked in in -16. + * debian/patches/m68k-autoinc.dpatch: Updated, don't attempt to increment + the register, if it's used multiple times in the instruction . + + -- Matthias Klose Sat, 21 Oct 2006 00:25:05 +0200 + +gcc-4.1 (4.1.1ds1-16) unstable; urgency=low + + [Matthias Klose] + * Update to SVN 20061008. + - Fix PR c++/29226, ICE in make_decl_rtl. Closes: #388263. + * libgcj7-0: Fix package removal. Closes: #390874. + * Configure with --disable-libssp on architectures that don't + support it (alpha, hppa, ia64, m68k, mips, mipsel). + * On hppa, remove build-dependency on dash. + * gij/gcj: Do not install slave links for the non DFSG manpages. + Closes: #390425, #390532. + * libgcj-common: rebuild-gcj-db: Don't do anything, if no classmap + files are found. Closes: #390966. + * Fix PR libstdc++/11953, extended for all linux architectures. + Closes: #391268. + * libffi4-dev: Conflict with libffi. Closes: #387561. + * Backport PR target/27880 to the gcc-4_1-branch. Patch by Steve Ellcey. + Closes: #390693. + * On ia64, don't use _Unwind_GetIPInfo in libjava and libstdc++. + * Add a README.ssp with minimal documentation about stack smashing + protection. Closes: #366094. + * Do not build libgcj-common from the gcc-4.1/gcj-4.1 sources anymore. + + [Roman Zippel] + * debian/patches/m68k-notice-move.dpatch: Don't set cc_status + for fp move without fp register. + + -- Matthias Klose Sun, 8 Oct 2006 02:21:49 +0200 + +gcc-4.1 (4.1.1ds1-15) unstable; urgency=medium + + * Update to SVN 20060927. + - Fix PR debug/29132, exception handling on mips. Closes: #389468, #390042. + - Fix typo in gcc documentation. Closes: #386180. + - Fix PR target/29230, wrong code generation on arm. Closes: #385505. + * libgcj-common: Ignore exit value of gcj-dbtool in rebuild-gcj-db on + arm, m68k, hppa. Adresses: #388505. + * libgcj-common: Replaces java-gcj-compat-dev and java-gcj-compat. + Closes: #389539. + * libgcj-common: /usr/share/gcj/debian_defaults: Define gcj_native_archs. + * Update the java backport from the redhat/gcc-4_1-branch upto 2006-09-27; + remove libjava-str2double.dpatch, pr28661.dpatch. + * Disable ssp on hppa, not supported. + * i386-biarch.dpatch: Avoid warnings about macro redefinitions. + + -- Matthias Klose Fri, 29 Sep 2006 22:32:41 +0200 + +gcc-4.1 (4.1.1ds1-14) unstable; urgency=medium + + [Matthias Klose] + * Update to SVN 20060920. + - Fix PR c++/26957. Closes: #373257, #386910. + - Fix PR rtl-optimization/28243. Closes: #378325. + * Remove patch for PR rtl-optimization/28634, applied upstream. + * Fix FTBFS on GNU/kFreeBSD (fallout from the backport of classpath-0.92). + (Petr Salinger). Closes: #385974. + * Merge from Ubuntu: + - Do not encode the subminor version in the jar files. + - Fix typo for the versioned gcj subdirectory in lib32gcj-0. + - When running the i386 binaries on amd64, adjust the properties + java.home, gnu.classpath.home.url, sun.boot.class.path, + gnu.gcj.precompiled.db.path. + - Configure the 32bit build on amd64 + --with-java-home=/usr/lib32/jvm/java-1.4.2-gcj-4.1-1.4.2.0/jre. + - Configure --with-long-double-128 for glibc-2.4 on alpha, powerpc, ppc64, + s390, s390x, sparc, sparc64. + - Update the java backport from the redhat/gcc-4_1-branch upto 2006-09-20. + - Fix PR java/29013, invalid byte code generation. Closes: #386926. + - debian/patches/gcc-pfrs-2.dpatch: Apply a fix for a regression in the + backport of PR 28946 from the trunk (H.J. Lu). + * Backport PR classpath/28661 from the trunk. + * Don't ship the .la files for the java modules. Closes: #386228. + * gcj-4.1: Remove dangling symlink. Closes: #386430. + * gij: Suggest java-gcj-compat, gcj: Suggest java-gcj-compat-dev. + Closes: #361942. + * Fix infinite loop in string-to-double conversion on 64bit targets. + Closes: #348792. + * gij-4.1: Ignore exit value of gcj-dbtool in postinst. Adresses: #388505. + * libgcj-common: Move rebuild-gcj-db from java-gcj-compat into libgcj-common. + * On hppa, install a wrapper around gij-4.1 to ignore unaligned memory + accesses. Works around buildd configurations enabling this check by + default. Addresses: #364819. + + [Ludovic Brenta] + * debian/patches/ada-libgnatprj.dpatch: Build mlib-tgt-linux.adb instead of + mlib-tgt.adb. Closes: #387826. + * debian/patches/ada-pr15802.dpatch: Backport from the trunk. + Closes: #246384. + * debian/control.m4 (gnat-4.1): do not provide gnat (supplied by + gcc-defaults instead); conflict with gnat-4.2 which will soon be in + unstable. + + [Roman Zippel] + * debian/patches/m68k-dwarf2.dpatch: Recognize stack adjustments also + in the src of an instruction. + * debian/patches/m68k-jumptable.dpatch: Don't force byte offset when + accessing the jumptable, gas can generate the correct offset size instead. + * debian/patches/m68k-peephole.dpatch: Convert some text peepholes to rtl + peepholes, so the correct DWARF2 information can be generated for stack + manipulations (Keep a few peepholes temporarily disabled). + * debian/patches/m68k-peephole-note.dpatch: Don't choke on notes while + reinserting REG_EH_REGION notes. + * debian/patches/m68k-return.dpatch: Don't use single return if fp register + have to be restored. Closes: #386864. + * debian/patches/m68k-sig-unwind.dpatch: Add support for unwinding over + signal frames. + * Fix PR rtl-optimization/27736, backport from the trunk. + * Add java support for m68k. Closes: #312830, #340874, #381022. + + -- Matthias Klose Sun, 24 Sep 2006 19:36:31 +0200 + +gcc-4.1 (4.1.1ds1-13) unstable; urgency=medium + + * Update to SVN 20060901; remove patches applied upstream: + - PR target/24367. + - PR c++/26670. + * Apply proposed patch for PR fortran/28908. + * Fix biarch symlinks in lib64stdc++ for cross builds. + * Fix biarch symlinks in lib32objc on amd64. + + -- Matthias Klose Fri, 1 Sep 2006 00:04:05 +0200 + +gcc-4.1 (4.1.1ds1-12) unstable; urgency=medium + + [Matthias Klose] + * Update to SVN 20060830. + * Add backport of PR other/26208, bump libgcc1 shlibs dependency. + * Add backport of PR c++/26670. Closes: #356548. + * Apply proposed patch for PR target/24367 (s390). + * Add /usr/lib/jni to the libjava dlsearch path. Closes: #364820. + * Build without GFDL licensed docs. Closes: #384036. + - debian/patches/{svn-doc-updates,pr25524-doc,pr26885-doc}.dpatch: + Split out -doc specific patches. + - debian/*.texi, debian/porting.html: Add dummy documentation. + - debian/rules.unpack, debian/rules.patch: Update for non-gfdl build. + - fastjar.texi: Directly define the gcctabopt and gccoptlist macros. + + * Merge from Ubuntu: + - Backport the classpath-0.92, libjava, gcc/java merge from the + redhat/gcc-4_1-branch branch. + - Apply the proposed patch for PR libgcj/28698. + - Change the libgcj/libgij sonames. Rename libgcj7 to libgcj7-0. + - Do not remove the rpath from libjvm.so and libjawt.so. Some + configure scripts rely on being able to link that libraries + directly. + - When running the i386 binaries on amd64, look in + /usr/lib32/gcj-x.y and /usr/lib32/jni instead. + - Add /usr/lib/jni to java.library.path. Closes: #364820. + - Add debugging symbols for more binary packages to libgcj7-dbg. + Closes: #383705. + - libgcj7-dev: Remove conflicts with older libgcjX-dev packages. + - Do not build the libgcj-bc and lib32gcj-bc packages anymore from + the gcj-4.1 source. + + [Roman Zippel] + * debian/patches/m68k-limit_reload.dpatch: Correctly limit reload class. + Closes: #375522. + * debian/patches/m68k-split_shift.dpatch: Use correct predicates for long long + shifts and use more splits. Closes: #381572. + * debian/patches/m68k-prevent-qipush.dpatch: Prevent combine from creating + a byte push on the stack (invalid on m68k). Closes: #385021. + * debian/patches/m68k-autoinc.dpatch: Recognize a few more autoinc possibilities. + * debian/patches/pr25514.dpatch: Backport from the trunk. + * debian/patches/m68k-gc.dpatch: Change STACKBOTTOM to LINUX_STACKBOTTOM + so it works with 2.6 kernels. + * Other m68k bug reports fixed in 4.1.1-11 and 4.1.1-12: + Closes: #378599, #345574, #344041, #323426, #340293. + * Build the stage1 compiler using -g -O2; saves a few hours build time + and apparently is working at the moment. + + -- Matthias Klose Tue, 29 Aug 2006 21:37:28 +0200 + +gcc-4.1 (4.1.1-11) unstable; urgency=low + + * The "Our priority are our users, remove the documentation!" release. + + [Matthias Klose] + * Fix build failure building the hppa->hppa64 cross compiler. + * Update to SVN 20060814. + - Fix directory traversal vulnerability in fastjar. Closes: #368397. + CVE-2006-3619. + - Fix PR rtl-optimization/23454, ICE in invert_exp_1 on sparc. + Closes: #321215. + - Fix PR c++/26757, C++ front-end producing two DECLs with the same UID. + Closes: #356569. + * Remove patch for PR rtl-optimization/28075, applied upstream. + * Apply proposed patch for PR rtl-optimization/28634, rounding problem with + -fdelayed-branch on hppa/mips. Closes: #381710. + * Fixed at least in 4.1.1-10: boost::date_time build failure. + Closes: #382352. + * Build-depend on make (>= 3.81), add make (>= 3.81) as dependency to + gcc-4.1-source. Closes: #381117. + * Backport of libffi from the trunk; needed for the java backport in + experimental. + * libffi4-dev: Install the libffi_convenience library as libffi_pic.a. + * When building a package without the GFDL'd documentation, don't create + the alternative's slave links for manual pages for the java tools. + * Do not build the -doc packages and derived manual pages licensed under + the GFDL with invariant sections or cover texts. + * Only build the libssp package, if the target libc doesn't provide + ssp support. + * Run the complete testsuite, when building a standalone gcj package. + + [Roman Zippel] + * debian/patches/m68k-fjump.dpatch: + Always use as fjcc pseudo op, we rely heavily on as to generate the + right size for the jump instructions. Closes: #359281. + * debian/patches/m68k-gc.dpatch: + The thread suspend handler has to save all registers. + Reenable MPROTECT_VDB, it should work, otherwise it's probably a kernel bug. + * debian/patches/m68k-save_pic.dpatch: + Correctly save the pic register, when not done by reload(). + (fixes _Unwind_RaiseException and thus exception handling). + * debian/patches/m68k-libffi.dpatch: Add support for closures. + * debian/patches/m68k-bitfield.dpatch: Avoid propagation of mem expression + past a zero_extract lvalue. + * debian/patches/m68k-dwarf.dpatch: Correct the dwarf frame information, + but preserve compatibility. + + [Christian Aichinger] + * Fix building a cross compiler targeted for ia64. Closes: #382627. + + -- Matthias Klose Tue, 15 Aug 2006 00:41:00 +0200 + +gcc-4.1 (4.1.1-10) unstable; urgency=low + + * Update to SVN 20060729. + - Fix PR c++/28225, segfault in type_dependent_expression_p. + Closes: #376148. + * Apply proposed patch for PR rtl-optimization/28075. + Closes: #373820. + * Apply proposed backport and proposed patch for PR rtl-optimization/28221. + Closes: #376084. + * libgcj7-jar: Loosen dependency on gcj-4.1-base. + * Add ssp header files to the private gcc includedir. + * Do not build the Ada packages from the gcc-4.1 source, introducing + a new gnat-4.1 source package. + * Build libgnat on alpha and s390 as well. + * Do not build the gnat-4.1-doc package (GFDL with invariant sections or + cover texts). + * Remove references to the stl-manual package. Closes: #378698. + + -- Matthias Klose Sat, 29 Jul 2006 22:08:59 +0200 + +gcc-4.1 (4.1.1-9) unstable; urgency=low + + * Update to SVN 20060715. + - Fix PR c++/28016, do not emit uninstantiated static data members. + Closes: #373895, #376871. + * Revert the patch to fix PR c++/27227. Closes: #378321. + * multiarch-include.dpatch: Renamed from biarch-include.dpatch; + apply for all architectures. + * Do not build the java compiler in gcc-4.1 package, just include the + options and specs in the gcc driver. + * Remove gnat-4.0 as an alternative build dependency. + * Add a patch to enable -fstack-protector by default for C, C++, ObjC, ObjC++. + The patch is disabled by default. + + -- Matthias Klose Sat, 15 Jul 2006 17:07:29 +0200 + +gcc-4.1 (4.1.1-8) unstable; urgency=medium + + * Update to SVN 20060708. + - Fix typo in gcov documentation. Closes: #375140. + - Fix typo in gccint documentation. Closes: #376412. + - [alpha], Fix -fvisibility-inlines-hidden segfaults on reference to + static method. PR target/27082. Closes: #369642. + + * Fix ppc64 architecture string in debian/multiarch.inc. Closes: #374535. + * Fix conflict, replace and provide libssp0-dev for cross compilers. + Closes: #377012. + * Ignore compiler warnings when checking whether compiler driver understands + Ada fails. Closes: #376660. + * Backport fix for PR libmudflap/26864 from the trunk. Closes: #26864. + * README.C++: Remove non-existing URL. Closes: #347601. + * gij-4.1: Provide java2-runtime. Closes: #360906. + + * Closed reports reported against gcc-3.0 and fixed in gcc-4.1: + - C++ + + PR libstdc++/13943, call of overloaded `llabs(int)' is ambiguous. + Closes: #228645. + - Java + + Fixed segmentation fault on compiling bad program. Closes: #165635 + * Closed reports reported against gcc-3.3 and fixed in gcc-4.1: + - Stack protector available. Closes: #213994, #233208. + - Better documentation of -finline-limit option. Closes: #296047. + * Closed reports reported against gcc-3.4 and fixed in gcc-4.1: + - General + + Fixed [unit-at-a-time] Using -O2 cannot detect missing return + statement in a function. Closes: #276843. + - C++ + + PR13943, call of overloaded `llabs(int)' is ambiguous. Closes: #228645. + + PR c++/21280, #pragma interface, templates, and "inline function used + but never defined". Closes: #364412. + - Architecture specific: + - m68k + + Segfault building glibc. Closes: #353618. + + ICE when trying to build boost. Closes: #321486. + * Closed reports reported against gcc-4.0 and fixed in gcc-4.1: + - General + + Handling of #pragma GCC visibility for builtin functions. + Closes: #330279. + + gettext interpretation the two conditional strings as one. + Closes: #227193. + + ICE due to if-conversion. Closes: #335078. + + Fix unaligned accesses with __attribute__(packed) and memcpy. + Closes: #355297. + + Fix ICE in expand_expr_real_1, at expr.c. Closes: #369817. + - Ada + + Link error not finding -laddr2line. Closes: #322849. + + ICE on invalid code. Closes: #333564. + - C++ + + libstdc++: bad thousand separator with fr_FR.UTF-8. Closes: #351786. + + The Compiler uses less memory than 4.0. Closes: #336225. + + Fix "fails to compare reverse map iterators". Closes: #362840. + + Fix "fail to generate code for base destructor defined inline with + pragma interface". Closes: #356435. + + Fix ICE in cp_expr_size, at cp/cp-objcp-common.c. Closes: #317455. + + Fix wrong warning: control may reach end of non-void function. + Closes: #319309. + + Fix bogus warning "statement has no effect" with template and + statement-expression. Closes: #336915. + + Fixed segfault on syntax error. Closes: #349087. + + Fix ICE with __builtin_constant_p in template argument. + Closes: #353366. + + Implement DR280 (fixing "no operator!= for const_reverse_iterator"). + Closes: #244894. + - Fortran + + Fix wrong behaviour in unformatted writing. Closes: #369547. + - Java + + Fixed segfault on -fdump-tree-all-all. Closes: #344265. + + Fixed ant code completion in eclipse generating a nullpointer + exception. Closes: #337510. + + Fixed abort in gnu_java_awt_peer_gtk_GtkImage.c. Closes: #343112. + + Fixed assertion failure in gij with rhdb-explain. Closes: #335650. + + Fixed assertion failure when calling JTabbedPane.addTab(null, ...). + Closes: #314704. + + Fixed error when displaying empty window with bound larger than the + displayed content. Closes: #324502. + + Fixed: Exception in JComboBox.removeAllItems(). Closes: #314706. + + Fixed assertian error in gnu_java_awt_peer_gtk_GtkImage.c. + Closes: #333733. + - libmudflap + + PR libmudflap/23170, libmudflap should not use functions marked + obsolescent by POSIX/SUS. Closes: #320398. + - Architecture specific: + - m68k + + FTBFS building tin. Closes: #323016. + + ICE with -g -fomit-frame-pointer. Closes: #331150. + + ICE in instantiate_virtual_regs_lossage. Closes: #333536. + + Wrong code generation with loop unrolling. Closes: #342121. + + ICEs while building gst-ffmpeg. Closes: #343692. + - mips + + Fix gjdoc build failure. Closes: #344986. + + Fix link failure for static libs and object files when xgot + needs to be used. Closes: #274942. + * gnat bug reports fixed since gnat-3.15p: + - GNAT miscounts UTF8 characters in string with -gnaty. Closes: #66175. + - Bug box from "with Text_IO" when compiling optimized. Closes: #243795. + - Nonconforming parameter lists not detected. Closes: #243796. + - Illegal use clause not detected. Closes: #243797. + - Compiler enters infinite loop on illegal program with tagged records. + Closes: #243799. + - Compiler crashes on illegal program (missing discriminant, unconstrained + parent). Closes: #243800. + - Bug box at sinfo.adb:1215 on illegal program. Closes: #243801. + - Bug box at sinfo.adb:1651 on illegal program. Closes: #243802. + - Illegal program not detected (entry families). Closes: #243803. + - Illegal program not detected, RM 10.1.1(14). Closes: #243807. + - Bug box at exp_ch9.adb:7254 on illegal code. Closes: #243812. + - Illegal program not detected, RM 4.1.4(14). Closes: #243816. + - Bug box in Gigi, code=116, on legal program. Closes: #244225. + - Illegal program not detected, 12.7(10) (generic parameter is visible, + shouldn't be). Closes: #244483. + - Illegal program not detected, ambiguous aggregate. Closes: #244496. + - Bug box at sem_ch3.adb:8003. Closes: #244940. + - Bug box in Gigi, code=103, on illegal program. Closes: #244945. + - Legal program rejected, overloaded procedures. Closes: #246188. + - Bug box in Gigi, code=999, on legal program. Closes: #246388. + - Illegal program not detected, RM 10.1.6(3). Closes: #246389. + - Illegal program not detected, RM 3.10.2(24). Closes: #247014. + - Illegal program not detected, RM 3.9(17). Closes: #247015. + - Legal program rejected. Closes: #247016. + - Legal program rejected. Closes: #247021. + - Illegal program not detected, RM 4.7(3). Closes: #247022. + - Illegal program not detected, RM 3.10.2(27). Closes: #247562. + - Legal program rejected, "limited type has no stream attributes". + Closes: #247563. + - Wrong output from legal program. Closes: #247565. + - Compiler enters infinite loop on illegal program. Closes: #247567. + - Illegal program not detected, RM 8.6(31). Closes: #247568. + - Legal program rejected, visible declaration not seen. Closes: #247572. + - Illegal program not detected, RM 8.2(9). Closes: #247573. + - Wrong output from legal program, dereferencing access all T'Class. + Closes: #248171. + - Compiler crashes on illegal program, RM 5.2(6). Closes: #248174. + - Cannot find generic package body, RM 1.1.3(4). Closes: #248677. + - Illegal program not detected, RM 3.4.1(5). Closes: #248679. + - Compiler ignores legal override of abstract subprogram. Closes: #248686. + - Bug box, Assert_Failure at sinfo.adb:2365 on illegal program. + Closes: #251266. + - Ada.Numerics.Generic_Elementary_Functions.Log erroneout with -gnatN. + Closes: #263498. + - Bug box, Assert_Failure at atree.adb:2906 or Gigi abort, code=102 + with -gnat -gnatc. Closes: #267788. + - Bug box in Gigi, code=116, 'Unrestricted_Access of a protected + subprogram. Closes: #269775. + - Stack overflow on illegal program, AI-306. Closes: #276225. + - Illegal program not detected, RM B.1(24). Closes: #276226. + - Wrong code generated with -O -fPIC. Closes: #306833. + - Obsolete: bashism's in debian/rules file. Closes: #370681. + - Supports more debian architectures. Closes: #171477. + + -- Matthias Klose Sat, 8 Jul 2006 16:24:47 +0200 + +gcc-4.1 (4.1.1-7) unstable; urgency=low + + * Prefer gnat-4.1 over gnat-4.0 as a build dependency. + * libssp0: Set priority to standard. + + -- Matthias Klose Sun, 2 Jul 2006 10:22:50 +0000 + +gcc-4.1 (4.1.1-6) unstable; urgency=low + + [Ludovic Brenta] + * Do not provide the symbolic link /usr/bin/gnatgcc; this will now + be provided by package gnat from the source package gcc-defaults. + * debian/control.m4, debian/control (gnat): conflict with gnat (<< 4.1), + not all versions of gnat, since gcc-defaults will now provide gnat (= 4.1) + which depends on gnat-4.1. + + [Matthias Klose] + * libjava: Change the default for enable_hash_synchronization_default + on PA-RISC. Tighten the libgcj7 shlibs version on hppa. + * Update to SVN 20060630. + * Apply proposed patch for PR 26991. + * Don't use the version for the libstdc++ shlibs dependency for the libgcj + shlibs dependency. + * Merge from Ubuntu edgy: + - Fix %g7 usage in TLS, add patch sparc-g7.dpatch, fixes glibc-2.4 build + failure on sparc (Fabio M. Di Nitto). + - Merge libssp0-dev into gcc-4.1 (-fstack-protector is a common option). + - Run the testsuite with -fstack-protector as well. + + [Bastian Blank] + * Make it possible to overwrite arch per DEB_TARGET_ARCH and DEB_TARGET_GNU_TYPE. + * Disable biarch only on request for cross builds. + * Use correct source directory for tarballs. + * Produce correct multiarch.inc for source builds. + + -- Matthias Klose Sat, 1 Jul 2006 01:49:55 +0200 + +gcc-4.1 (4.1.1-5) unstable; urgency=low + + * Fix build error running with dpkg-buildpackage -rsudo. + + -- Matthias Klose Wed, 14 Jun 2006 01:54:13 +0200 + +gcc-4.1 (4.1.1-4) unstable; urgency=low + + * Really do not backout the fix for PR c++/26068. + Closes: #372152, #372559. + * Update fastjar version string to 4.1. + * Disable pascal again. + + -- Matthias Klose Mon, 12 Jun 2006 20:29:57 +0200 + +gcc-4.1 (4.1.1-3) unstable; urgency=low + + * Update to SVN 20060608, do not revert the fix for PR c++/26068. + Closes: #372152, #372559. + * Fix build failures for Pascal, enable Pascal on all architectures. + * Fix another build failure on GNU/kFreeBSD (Aurelien Jarno). + Closes: #370661. + * Fix build fauilure in gcc/p with parallel make. + * Remove cross-configure patch (Kazuhiro Inaoka). Closes: #370649. + * Only build the gcc-4.1-source package, when building from the gcc-4.1 + source. + * Fix upgrade problem from standalone gcj-4.1. + * Fix build error using bison-2.2, build-depend on bison (>= 2.3). + Closes: #372605. + * Backport PR libstdc++/25524 from the trunk, update the biarch-include + patch. mips triarch support can be added more easily. + + -- Matthias Klose Mon, 12 Jun 2006 00:23:45 +0200 + +gcc-4.1 (4.1.1-2) unstable; urgency=low + + * Update to SVN 20060604. + - Fix PR c++/26757, C++ front-end producing two DECLs with the same UID. + Closes: #356569. + - Fix PR target/27158, ICE in extract_insn with -maltivec. + Closes: #362307. + * Revert PR c++/26068 to work around PR c++/27884 (Martin Michlmayr). + Closes: #370308. + * Mention Ada in copyright, update copyright file (Ludovic Brenta). + Closes: #366744. + * Fix kbsd-gnu-java.dpatch (Petr Salinger). Closes: #370320. + * Don't include version control files in gcc-4.1-source. + + -- Matthias Klose Sun, 4 Jun 2006 19:13:37 +0000 + +gcc-4.1 (4.1.1-1) unstable; urgency=low + + [Matthias Klose] + * Update to SVN 20060601. + * Reenable the gpc build. + * PR libgcj/26483, libffi patch for IA-64 denorms, taken from trunk. + * Disable Ada for m32r targets. Closes: #367595. + * lib32gfortran1: Do not create empty directory /usr/lib32. Closes: #367999. + * gcc-4.1: Add a conflict to the gcj-4.1 version with a different + gcc_libdir. + * Build gij/gcj for GNU/k*BSD. Closes: #367166. + * Update hurd-changes patch (Michael Banck). Closes: #369690. + * debian/copyright: Add exception for the gpc runtime library. + * Update gpc/gpc-doc package descriptions. + + [Ludovic Brenta] + * patches/ada-libgnatprj.dpatch: add prj-pars.ad[bs] and sfn_scan.ad[bs] + to libgnatprj; remove them from gnatmake. + + -- Matthias Klose Thu, 1 Jun 2006 20:35:54 +0200 + +gcc-4.1 (4.1.0-4) unstable; urgency=low + + [Ludovic Brenta] + * Fix a stupid bug whereby fname.ad{b,s} would be included in both + libgnatvsn-dev and libgnatprj-dev, preventing use of gnatprj.gpr. + Closes: #366733. + + -- Matthias Klose Thu, 11 May 2006 04:34:50 +0200 + +gcc-4.1 (4.1.0-3) unstable; urgency=low + + * Update to SVN 20060507. + * debian/rules.d/binary-java.mk: Use $(lib32) everywhere. Closes: #365388. + * Always configure hppa64-linux-gnu with + --includedir=/usr/hppa64-linux-gnu/include. + * Make libgnatvsn4.1 and libgnatprj4.1 priority optional. Closes: #365900. + * Call autoconf2.13 explicitely in the Ada patches, build-depend on + autoconf2.13. Closes: #365780. + * Fix libgnatprj-dev and libgnatvsn-dev dependencies on their shared + libraries. + * Deduce softfloat and vfp (ARM) configure options (Pjotr Kourzanov). + * Update proposed patch for PR26885 (May 2 version). + * Build the libxxstdc++-dbg packages, when not building the library pacakges. + * Do not include the _pic library in the libxxstdc++-dbg packages. + + -- Matthias Klose Sun, 7 May 2006 15:29:53 +0200 + +gcc-4.1 (4.1.0-2) unstable; urgency=medium + + * Update to SVN 20060428. + * Apply proposed patches for PR26885. + + * Keep libffi doc files in its own directory. Closes: #360466. + * Update ppc64 patches for 4.1 (Andreas Jochens). Closes: #360498. + * Fix PR tree-optimization/26763, wrong-code, taken from the 4.1 branch. + Closes: #356896. CVE-2006-1902. + * hppa-cbranch, hppa-cbranch2 patches: Fix for PR target/26743, + PR target/11254, PR target/10274, backport from trunk (Randolph Chung). + * Let libgccN provide -dcv1 when cross-compiling (Pjotr Kourzanov). + Closes: #363289. + * (Build-)depend on glibc-2.3.6-7. Closes: #360895, #361904. + * Fix a pedantic report about a package description. Add a hint that + we do not like bug reports with locales other than "C". Closes: #361409. + * Enable the libjava interpreter on mips/mipsel. + * gcc-4.1-source: Depend on gcc-4.1-base. + * gnat-4.1: Fix permissions of .ali files. + * Build lib32gcj7 on amd64. + * debian/patches/ada-gnatvsn.dpatch: New. Apply proposed fix for + PR27194. + + [Ludovic Brenta] + * debian/patches/ada-default-project-path.dpatch: new. Change the + default search path for project files to the one specified + by the Debian Policy for Ada: /usr/share/ada/adainclude. + * debian/patches/ada-symbolic-tracebacks.dpatch: new. Enable support for + symbolic tracebacks in exceptions. + * debian/patches/ada-missing-lib.dpatch: remove, superseded by the above. + * debian/patches/ada-link-lib.dpatch: changed. + - Instead of building libada as a target library only, build it as + both a host and, if different, target library. + - Build the GNAT tools in their top-level directory; do not use + recursive makefiles. + - Link the GNAT tools dynamically against libgnat. + - Apply proposed fix for PR27300. + - Rerun autoconf (Matthias Klose). + * debian/patches/ada-libgnatvsn.dpatch: new. + - Introduce a new shared library named libgnatvsn, containing + common components of GNAT under the GNAT-Modified GPL, for + use in GNAT tools, ASIS, GLADE and GPS. + - Link the gnat tools against this new library. + - Rerun autoconf (Matthias Klose). + * debian/patches/ada-libgnatprj.dpatch: new. + - Introduce a new shared library named libgnatprj, containing the + GNAT Project Manager, i.e. the parts of GNAT that parses project + files (*.gpr). Licensed under pure GPL; for use in GLADE and GPS. + - Link the gnat tools against this new library. + - Rerun autoconf (Matthias Klose). + * debian/patches/ada-acats.dpatch: new. + - When running the ACATS, look for the gnat tools in their new + directory (build/gnattools), and for the shared libraries in + build/gcc/ada/rts, build/libgnatvsn and build/libgnatprj. + * debian/gnatvsn.gpr, debian/gnatprj.gpr: new. + * debian/rules.d/binary-ada.mk, debian/control.m4: new binary packages: + libgnatvsn-dev, libgnatvsn4.1, libgnatprj-dev, libgnatprj4.1. Place + the *.gpr files in their respective -dev packages. + + -- Matthias Klose Sat, 29 Apr 2006 00:32:09 +0200 + +gcc-4.1 (4.1.0-1) unstable; urgency=low + + * libstdc++CXX-BV-dev.preinst: Remove (handling of c++ include dir for 4.0). + * libgcj-common: Move removal of docdir from preinst into postinst. + * libgcj7: Move removal of docdir from preinst into postinst. + * Drop alternative build dependency on gnat-3.4, not built anymore. + * Fix PR libgcj/26103, wrong exception thrown (4.1 branch). + * debian/patches/libjava-stacktrace.dpatch: Add support to print file names + and line numbers in stacktraces. + * Add debugging symbols for libgcjawt and lib-gnu-java-awt-peer-gtk + in the libgcj7-dbg and lib32gcj7-dbg packages. + * Remove dependency of the libgcj-dbg packages on the libgcj-dev packages, + add recommendations on binutils and libgcj-dev. Mention the requirement + of binutils for the stacktraces. + * Fix upgrade from version 4.0.2-9, loosing the Debian changelog. + Closes: #355439. + * gij/gcj: Install one alternative for each command, do not use slave + links for rmiregistry, javah, rmic. Ubuntu #26781. Closes: #342557. + * Fix for PR tree-optimization/26587, taken from the 4.1 branch. + * Fix PR libstdc++/26526 (link failure when _GLIBCXX_DEBUG is defined). + * Configure with --enable-clocale=gnu, even if not building C++ packages. + * Remove runtime path from biarch libraries as well. + * PR middle-end/26557 (ice-on-vaild-code, regression), taken from + the gcc-4_1-branch. Closes: #349083. + * PR tree-optimization/26672 (ice-on-vaild-code, regression), taken from + the gcc-4_1-branch. Closes: #356231. + * PR middle-end/26004 (rejects-vaild-code, regression), taken from + the gcc-4_1-branch. + * When building as standalone gcj, build libgcc4 (hppa only) and fastjar. + * Configure --with-cpu=v8 on sparc. + * debian/patches/libjava-hppa.dpatch: pa/pa32-linux.h + (CRT_CALL_STATIC_FUNCTION): Define when CRTSTUFFS_O is defined. + (John David Anglin). Closes: #353346. + * Point to the 4.1 version of README.Bugs (closes: #356230). + * Disable the libmudflap testsuite on alpha (getting killed). + + -- Matthias Klose Sat, 18 Mar 2006 23:00:39 +0100 + +gcc-4.1 (4.1.0-0) experimental; urgency=low + + * GCC 4.1.0 final release. + * Build the packages for the Java language from a separate source. + * Update NEWS.html, NEWS.gcc. + * libgcj-doc: Auto generated API documentation for libgcj7, classpath + example programs. + * Add gjdoc to Build-Depends-Indep. + * On amd64, build-depend on libc6-dev-i386 instead of ia32-libs-dev. + * Internal ssp headers now installed in the gcc libdir. + * Do not build gcj-4.1-base when building the gcc-4.1 packages. + * When building as gcj-4.1, use the tarball from the gcc-4.1-source + package. + + [Ludovic Brenta] + * Allow to enable and disable NLS and bootstrapping from the environment. + - Adding "nls" to WITHOUT_LANG disables NLS support. + - If WITH_BOOTSTRAP is set, debian/rules2 calls configure + --enable-bootstrap=$(WITH_BOOTSTRAP) and just "make". If + WITH_BOOTSTRAP is unset, it calls configure without a bootstrapping + option and calls "make profiledbootstrap" or "make bootstrap-lean" + depending on the target CPU. + Currently overwritten to default to "bootstrap". + + -- Matthias Klose Thu, 2 Mar 2006 00:03:45 +0100 + +gcc-4.1 (4.1ds9-0exp9) experimental; urgency=low + + * Update to GCC 4.1.0 release candidate 1 (gcc-4.1.0-20060219 tarball). + * Update gcc-version patch for gcc-4.1. + * libgccN, libstdc++N*: Fix upgrade of /usr/share/doc symlinks. + * libjava awt & swing update, taken from trunk 2006-02-16. + * libgcj7-dev: Suggest libgcj-doc, built from a separate source package. + * Shorten build-dependency line (work around buildd problems + on arm* and mips*). + * New patch gcc-ice-hack (saving the preprocessed source on an ICE), + taken from Fedora. + + -- Matthias Klose Mon, 20 Feb 2006 10:07:23 +0100 + +gcc-4.1 (4.1ds8-0exp8) experimental; urgency=low + + * Update to SVN 20060212, taken from the 4.1 release branch. + * libgccN: Fix upgrade of /usr/share/doc/libgccN symlink. + + -- Matthias Klose Sun, 12 Feb 2006 19:48:31 +0000 + +gcc-4.1 (4.1ds7-0exp7) experimental; urgency=low + + * Update to SVN 20060127, taken from the 4.1 release branch. + - On hppa, bump the libgcc soversion to 4. + * Add an option not to depend on the system -base package for cross compiler + (Ian Wienand). Closes: #347484. + * Remove workaround increasing the stack size limit for some architectures, + not needed anymore on ia64. + * On amd64, build-depend on libc6-dev-i386, depend on libc6-i386, where + available. + * libstdc++6: Properly upgrade the doc directory. Closes: #346171. + * libstdc++6: Add a conflict to scim (<< 1.4.2-1). Closes: #343313. + * Set default 32bit ix86 architecture to i486. + + -- Matthias Klose Fri, 27 Jan 2006 22:23:22 +0100 + +gcc-4.1 (4.1ds6-0ubuntu6) experimental; urgency=low + + * Update to SVN 20060107, taken from the 4.1 release branch. + - Remove fix for PR ada/22533, fixed by patch for PR c++/23171. + * Remove binary packages from the control file, which aren't built + yet on any architecture. + * gcc-hppa64: Use /usr/hppa64-linux-gnu/include as location for the glibc + headers, tighten glibc (build-)dependency. + * libffi [arm]: Add support for closures, libjava [arm]: enable the gij + interpreter (Phil Blundell). Addresses: #337263. + * For the gcj standalone build, include cc1 into the gcj-4.1 package, + needed for linking java programs compiled to native code. + + -- Matthias Klose Sat, 7 Jan 2006 03:36:33 +0100 + +gcc-4.1 (4.1ds4-0exp4) experimental; urgency=low + + * Update to SVN 20051210, taken from the 4.1 release branch. + * Prepare to build the java packages from it's own source (merged + from Ubuntu). + - Build the java packages from the gcc-4.1 source, as long as packages + are prepared for experimental. + - When built as gcj, run only the libjava testsuite, don't build the + libstdc++ debug packages, don't package the gcc source. + - Loosen package dependencies, when java packages are built from + separate sources. + - Fix gcj hppa build, when java packages are built from separate sources. + - gij-4.1: Install test-summary, when doing separate builds. + - Allow java packages be installed independent from other packages built + from the source package. + - Rename libgcj7-common to libgcj7-jar. + - Introduce a gcj-4.1-base package to completely separate the two and not + duplicate the changelog in each gcj/gij package. + * Java related changes: + - libjava-xml-transform: Update from classpath trunk, needed for + eclipse (Michael Koch), applied upstream. + - Fix java wrapper scripts to point to 4.1 (closes: #341710). + - Reenable java on mips and mipsel. + - Fix libgcj6 dependency. Ubuntu #19935. + - Add libxt-dev as a java build dependency. autoconf explicitely checks + for X11/Intrinsic.h. + * Ada related changes: + - Apply proposed fix for PR ada/22533, reenable ada on alpha, powerpc, + mips, mipsel and s390. + - Add Ada support for GNU/kFreeBSD (Aurelien Jarno). Closes: #341356. + - Remove ada bootstrap workaround for alpha. + * Build a separate gcc-4.1-source package (Bastian Blank). Closes: #333922. + * Remove obsolete patch: libstdc++-automake. + * Remove patch integrated upstream: libffi-mips. + * Fix the installation of the hppa64 compiler in snapshot builds. + * Rename libgfortran0* to libgfortran1* (upstream soversion change). + * Add a dependency on libc-dev for all compilers / -dev packages except + gcc (which can be used for kernel builds without libc-dev). + * libffi4-dev: Fix package description. + * On amd64, install 32bit libraries into /emul/ia32-linux/usr/lib. + Addresses: #341147. + * Fix installation of biarch libstdc++ headers on amd64. + * Configure --with-tune=i686 on ix86 architectures (on Ubuntu with + -mtune=pentium4). Remove the cpu-default-* patches. + * debian/control.m4: Fix libxxgcc package names. + * Update the build infrastructure to build cross compilers + (Nikita V. Youshchenko). + * Tighten binutils (build-)dependency. Closes: #342484. + * Symlink more doc directories. + * debian/control.m4: Explicitely set Architecture for biarch packages. + + -- Matthias Klose Sat, 10 Dec 2005 16:56:45 +0100 + +gcc-4.1 (4.1ds1-0ubuntu1) UNRELEASED; urgency=low + + * Build Java packages only. + * Update to SVN 20051121, taken from the 4.1 release branch. + - Remove libjava-saxdriver-fix patch, applied upstream. + - Remove ada-gnat-version patch, applied upstream. + * Fix FTBFS in biarch builds on 32bit kernels. + * Update libstdc++-doc doc-base file (closes: #339046). + * Remove obsolete patch: gcc-alpha-ada_fix. + * Fix installation of biarch libstdc++ headers (Ubuntu #19655). + * Fix sparc and s390 biarch patches to build the 64bit libffi. + * Work around biarch build failure in libjava/classpath/native/jni/midi-alsa. + * Install spe.h header on powerpc. + * Add libasound build dependencies. + * libgcj: Fix installation of libgjsmalsa library. + * Remove patches not used anymore: libjava-no-rpath, i386-config-ml-nomf, + libobjc, multiarch-include, disable-biarch-check-mf, gpc-profiled, + gpc-no-gpidump, libgpc-shared, acats-expect. + * Fix references to manuals in gnat(1). Ubuntu #19772. + * Remove build dependency on xlibs-dev, add libxtst-dev. + * Do not configure with --disable-werror. + * Merge *-config-ml patches into one config-ml patch, configure the biarch + libs in debian/rules.defs. + * debian/gcj-wrapper: Accept -Xss. + * Do not build biarch java on Debian (missing biarch libasound). + * Do not build the java packages from this source package, avoiding + dependencies on X. + + -- Matthias Klose Mon, 21 Nov 2005 20:29:43 +0100 + +gcc-4.1 (4.1ds0-0exp0) experimental; urgency=low + + * Configure libstdc++ using the default allocator. + * Update to 20051112, taken from the svn trunk. + + -- Matthias Klose Sat, 12 Nov 2005 23:47:01 +0100 + +gcc-4.1 (4.1ds0-0ubuntu0) breezy; urgency=low + + * UNRELEASED + * First snapshot of gcc-4.1 (CVS 20051019). + - adds SSP support (closes: #213994, #233208). + * Remove patches applied upstream/not needed anymore. + * Update patches for 4.1: link-libs, gcc-textdomain, libjava-dlsearch-path, + rename-info-files, reporting, classmap-path, i386-biarch, sparc-biarch, + libjava-biarch-awt, ada-gcc-name. + * Disable patches: + - 323016, m68k, necessary for 4.1? + * debian/copyright: Update for 4.1. + * debian/control, debian/control.m4, debian/rules.defs, debian/rules.conf: + Update for 4.1, add support for Obj-C++ and SSP. + * Fix generation of Ada docs in info format. + * Set Ada library version to 4.1. + * Drop gnat-3.3 as an alternative build dependency. + * Use fortran instead of f95 for the build files. + * Update build support for awt peer libs. + * Add packaging support for SSP library. + * Add packaging support for Obj-C++. + * Run the testsuite for -march=i686 on i386 and amd64 as well. + * Fix generation of Pascal docs in html format. + * Update config-ml patches to build libssp biarch. + * Disable libssp for hppa64 build. + * libgcj7-dev: Install jni_md.h. + * Disable gnat for powerpc, currently fails to build. + * Add biarch runtime lib packages for ssp, mudflap, ffi. + * Do not explicitely configure with --enable-java-gc=boehm, which is the + default. + * libjava-saxdriver-fix: Fix a problem in the Aelfred2 SAX parser. + * libstdc++6-4.0-dev: Depend on the libc-dev package. Ubuntu #18885. + * Build-depend on expect-tcl8.3 on all architectures. + * Build-depend on lib32z1-dev on amd64 and ppc64, drop build dependency on + amd64-libs. + * Disable ada on alpha mips mipsel powerpc s390, currently broken. + + -- Matthias Klose Wed, 19 Oct 2005 11:02:31 +0200 + +gcc-4.0 (4.0.2-3) unstable; urgency=low + + * Update to CVS 20051015, taken from the gcc-4_0-branch. + - gcc man page fixes (closes: #327254, #330099). + - PR java/19870, PR java/20338, PR java/21844, PR java/21540: + Remove Debian patches. + - Applied libjava-echo-fix patch. + - Fix PR target/24284, ICE (Segmentation fault) on sparc-linux. + Closes: #329840. + - Fix PR c++/23797, ICE on typename outside template. Closes: #325545. + - Fix PR c++/22551, ICE in tree_low_cst. Closes: #318932. + * libstdc++6: Tighten libstdc++ shlibs version to 4.0.2-3 (new symbol). + * Update generated Ada files. + * Fix logic to disable mudflap and Obj-C++ via the environment. + * Remove f77 build bits. + * gij-4.0: Remove /var/lib/gcj-4.0/classmap.db on purge (closes: #330800). + * Let gcj-4.0 depend on libgcj6-dev, instead of recommending it. This is + not necessary for byte-code compilations, but for compilations to native + code. For compilations to byte-code, use a better compiler like ecj + for now (found in the ecj-bootstrap package). + * Disable biarch setup in cross compilers (Josh Triplett). Closes: #333952. + * Fix with_libnof logic for cross-compilations (Josh Triplett). + Closes: #333951. + * Depend on binutils (>= 2.16.1cvs20050902-1) on the alpha architecture. + Closes: #333954. + * On i386, build-depend on libc6-dev-amd64. Closes: #329108. + * (Build-)depend on glibc 2.3.5-5. + + -- Matthias Klose Sun, 2 Oct 2005 14:25:54 +0200 + +gcc-4.0 (4.0.2-2) unstable; urgency=low + + * Update to CVS 20051001, taken from the gcc-4_0-branch. Includes the + changes between 4.0.2 RC3 and the final 4.0.2 release, missing from + the upstream tarball. Remove patches applied upstream (gcc-c-decl, + pr23182, pr23043, pr23367, pr23891, pr21418, pr24018). + * On ix86 architectures run the testsuite for -march=i686 as well. + * Build libffi on the Hurd (closes: #328705). + * Add big-endian arm (armeb) support (Lennert Buytenhek). Closes: #330730. + * Update libjava xml to classpath CVS HEAD 20050930 (Michael Koch). + * Reapply patch to make -mieee the default on alpha-linux. Closes: #330826. + * Add workaround not to make libmudflap _start/_end not small data on + mips/mipsel, taken from CVS HEAD. + * Don't build the nof libraries on powerpc. + * Number crunching time on m68k, reenable gfortran on m68k-linux-gnu. + + -- Matthias Klose Sat, 1 Oct 2005 15:42:10 +0200 + +gcc-4.0 (4.0.2-1) unstable; urgency=low + + * GCC 4.0.2 release. + * lib64stdc++6: Set priority to optional. + * Fix bug in StreamSerializer, seen with eclipse-3.1 (Ubuntu 12744). + Backport from CVS HEAD, Michael Koch. + * Apply java patches, proposed for the 4.0 branch: PR java/24018, + PR libgcj/23182, PR java/19870, PR java/21844, PR libgcj/23367, + PR java/20338. + * Update the expect/pty test to actually call expect directly, rather + than test for the existence of PTYs, since a working expect is what + we really care about, not random device files (Adam Conrad). + Closes: #329715. + * Add build dependencies on lib64z1-dev. + * gcc-c-decl.dpatch: Fix C global decl handling regression in 4.0.2 from + 4.0.1 + + -- Matthias Klose Thu, 29 Sep 2005 19:50:08 +0200 + +gcc-4.0 (4.0.1-9) unstable; urgency=low + + * Update to CVS 20050922, taken from the gcc-4_0-branch (4.0.2 RC3). + * Apply patches: + - Fix PR java/21418: Order of source files matters when compiling, + backported from mainline. + - Fix for PR 23043, backported form mainline. + - Proposed patch for #323016 (m68k only). Patch by Roman Zippel. + * libstdc++6: Tighten libstdc++ shlibs version to 4.0.1-9 (new symbol). + * Fail the build early, if the system doesn't have any pty devices + created in /dev. Needed for running the testsuite. + * Update hurd changes again (closes: #328973). + + -- Matthias Klose Thu, 22 Sep 2005 07:28:18 +0200 + +gcc-4.0 (4.0.1-8) unstable; urgency=medium + + * Update to CVS 20050917, taken from the gcc-4_0-branch. + - Fix FTBFS for boost, introduced in 4.0.1-7 (closes: #328684). + * Fix PR java/23891, eclipse bootstrap. + * Set priority of gcc-4.0-hppa64 package to standard. + * Bump standards version to 3.6.2. + * Fix java wrapper script, mishandles command line options with arguments. + Patch from Olly Betts. Closes: #296456. + * Bump epoch of the lib32gcc1 package to the same epoch as for the the + libgcc1 and lib64gcc1 packages. + * Fix some lintian warnings. + * Build libffi on the Hurd (closes: #328705). + * For biarch builds, disable the testsuite for the non-default architecture + for runtime libraries, which are not built by default (libjava). + * Add gsfonts-x11 to Build-Depends-Indep to avoid warnings from doxygen. + * Install Ada .ali files read-only. + + -- Matthias Klose Sat, 17 Sep 2005 10:35:23 +0200 + +gcc-4.0 (4.0.1-7) unstable; urgency=low + + * Update to CVS 20050913, taken from the gcc-4_0-branch. + - Fix PR c++/19004, ICE in uses_template_parms (closes: #284777). + - Fix PR rtl-optimization/23454, ICE in invert_exp_1 on sparc. + Closes: #321215. + - Fix PR libstdc++/23417, make bits/stl_{list,tree}.h -Weffc++ clean. + Closes: ##322170. + * Install 'altivec.h' on ppc64 (closes: #323945). + * Install locale data with the versioned package name (closes: #321591). + * Fix fastjar build without building libjava. + * On hppa, don't build using gcc-3.3 when ada is disabled. + * On m68k, don't build the stage1 compiler using -O. + + * Ludovic Brenta + - Allow the choice whether or not to build with NLS. + - Fix a typo whereby libffi was always enabled on i386. + + -- Matthias Klose Tue, 13 Sep 2005 23:23:11 +0200 + +gcc-4.0 (4.0.1-6) unstable; urgency=low + + * Update to CVS 20050821, taken from the gcc-4_0-branch. + - debian/patches/pr21562.dpatch: Removed, applied upstream. + - debian/patches/libjava-awt-name.dpatch: Updated. + - debian/patches/classpath-20050618.dpatch: Updated. + * Use all available CPU's for the check target, unless USE_NJOBS == no. + * debian/patches/biarch-include.dpatch: Include + /usr/local/include/-linux-gnu before including /usr/local/include. + * Fix biarch system include directories for the non-default architecture. + * Prefer gnat-4.0 over gnat-3.4 over gnat-3.3 as a build-dependency. + + -- Matthias Klose Thu, 18 Aug 2005 18:36:23 +0200 + +gcc-4.0 (4.0.1-5) unstable; urgency=low + + * Update to CVS 20050816, taken from the gcc-4_0-branch. + - Fix PR middle-end/23369, wrong code generation for funcptr comparison + on hppa. Closes: #321785. + - Fix PR fortran/23368 ICE with NAG routines (closes: #322912). + * Build-depend on libcairo2-dev (they say, that's the final package name ...) + * libgcj: Search /usr/lib/gcj-4.0 for dlopened libraries, place a copy + of the .la files in the libgcj6 package into this directory. + Closes: #322576. + * Tighten the dependencies between the compiler packages to the same + version and release. Use some substitution variables for control file + generation. + * Remove build dependencies for gpc. + * Don't use '/emul/ia32-linux' on ppc64 (closes: #322890). + * Synchronize with Ubuntu. + + -- Matthias Klose Tue, 16 Aug 2005 22:45:47 +0200 + +gcc-4.0 (4.0.1-4ubuntu1) breezy; urgency=low + + * Jeff Bailey + + Enable i386 biarch using biarch glibc (not yet enabled for unstable). + - debian/rules.d/binary-libgcc.mk: Make i386 lib64gcc1 depend on + libc6-amd64 + - debian/control.m4: Suggest libc6-amd64 rather than amd64-libs. + - debian/rules.conf: Build-Dep on libc6-dev-amd64 [i386] + Build-Dep on binutils >= 2.16.1-2ubuntu3 + - debian/rules2: Enable biarch build in Ubuntu. + + * Matthias Klose + + - Add shlibs file and dependency information for the lib32gcc1 package. + - debian/patches/gcc-textdomain.dpatch: Update (closes: #321591). + - Set priority of gcc-4.0-base and libstdc++6 packages to `required'. + Closes: #321016. + - libffi-hppa.dpatch: Remove, applied upstream. + + -- Matthias Klose Mon, 8 Aug 2005 19:39:02 +0200 + +gcc-4.0 (4.0.1-4) unstable; urgency=low + + * Enable the biarch compiler for powerpc (closes: #268023). + * Update to CVS 20050806, taken from the gcc-4_0-branch. + * Build depend on libcairo0.6.0-dev (closes: #321540). + * Fix Ada build on the hurd (closes: #321350). + * Update libffi for mips (Thiemo Seufer). Closes: #321100. + * Fix segfault on 64bit archs in the AWT Gtk peer library (Dan Frazier). + Closes: #320915. + * Add libXXgcc1 build dependencies for biarch builds. + + -- Matthias Klose Sun, 7 Aug 2005 07:01:59 +0000 + +gcc-4.0 (4.0.1-3) unstable; urgency=medium + + * Update to CVS 20050725, taken from the gcc-4_0-branch. + - Fix ICE with -O and -mno-ieee-fp/-ffast-math (closes: #319087). + * Synchronize with Ubuntu. + * Fix applying hurd specific patches for the hurd build (closes: #318443). + * Do not build-depend on libmpfr-dev on architectures, where fortran + is not built. + * Apply biarch include patch on ppc64 as well (closes: #318603). + * Correct libstdc++-dev package description (closes: #319082). + * debian/rules.defs: Replace DEB_TARGET_GNU_CPU with DEB_TARGET_ARCH_CPU. + * gcc-4.0-hppa64: Rename hppa64-linux-gcc to hppa64-linux-gnu-gcc. + Closes: #319818. + + -- Matthias Klose Mon, 25 Jul 2005 10:43:06 +0200 + +gcc-4.0 (4.0.1-2ubuntu3) breezy; urgency=low + + * Update to CVS 20050720, taken from the gcc-4_0-branch. + - Fix PR22278, volatile issues, seen when building xorg. + * Build against new libcairo1-dev (0.5.2). + + -- Matthias Klose Wed, 20 Jul 2005 12:29:50 +0200 + +gcc-4.0 (4.0.1-2ubuntu2) breezy; urgency=low + + * Acknowledge that i386 biarch builds still need to be fixed for glibc-2.3.5. + + -- Matthias Klose Tue, 19 Jul 2005 08:29:30 +0000 + +gcc-4.0 (4.0.1-2ubuntu1) breezy; urgency=low + + * Synchronize with Debian. + * Update to CVS 20050718, taken from the gcc-4_0-branch. + - Fix PR c++/22132 (closes: #318488), upcasting a const class pointer + to struct the class derives from generates wrong code. + * Build biarch runtime libraries for Fortran and ObjC. + * Apply proposed patch for PR22309 (crash with mt_allocator if libstdc++ + is dlclosed). Closes: #293466. + + -- Matthias Klose Mon, 18 Jul 2005 17:10:18 +0200 + +gcc-4.0 (4.0.1-2) unstable; urgency=low + + * Don't apply the patch to make -mieee the default on alpha-linux-gnu. + Causes the bootstrap to fail on alpha-linux-gnu. + + -- Matthias Klose Tue, 12 Jul 2005 00:14:12 +0200 + +gcc-4.0 (4.0.1-1) unstable; urgency=high + + * GCC 4.0.1 final release. See /usr/share/doc/gcc-4.0/NEWS.{gcc,html}. + * Build fastjar on mips/mipsel, fix fastjar build without building java. + * Disable the comparision check on unstable/ia64. adaint.o differs, + currently cannot be reproduced with glibc-2.3.5 and binutils-2.16.1. + * libffi/hppa: Fix handling of 3 and 5-7 byte struct returns. + * amd64: Fix libgcc symlinks to point to /usr/lib32, instead of /lib32. + * On powerpc, don't build with -j >1, apparently doesn't succeeds + on the Debian buildd. + * Apply revised patch to make -mieee the default on alpha-linux, + and add -mieee-disable switch to turn the default off (Tyson Whitehead). + * Disable multiarch-includes; redo biarch-includes to include the paths + for the non-default biarch, when called with -m32/-m64. + * Move new java headers from libstdc++-dev to libgcj-dev, add replaces + line. + * Update classpath patch to work with cairo-0.5.1. Patch provided by + Michael Koch. + * Further classpath updates for gnu.xml and javax.swing.text.html. + Patch provided by Michael Koch. + * Require binutils (>= 2.16.1) as a build dependency and a dependency. + * On i386, require amd64-libs-dev (>= 1.2). + * Update debian/NEWS.{html,gcc}. + + * Closing bug reports reported against older gcc versions (some of them + still present in Debian, but not anymore as the default compiler). + Usually, forwarded bug reports are linked to + http://gcc.gnu.org/PR + The upstream bug number usually can be found in the Debian reports. + + * Closed reports reported against gcc-3.3 and fixed in gcc-3.4: + - General: + + PR rtl-optimization/2960: Duplicate loop conditions even with -Os + Closes: #94701. + + PR optimization/3995: i386 optimisation: joining tests. + Closes: #105309. + + PR rtl-optimization/11635: Unnecessary store onto stack, more + curefully expand union cast (closes: #202016). + + PR target/7618: vararg disallowed in virtual function. Closes: #205404. + + Large array problem on 64 bit platforms (closes: #209152). + + Mark more strings as translatable (closes: #227129). + + PR gcc/14711: ICE when compiling a huge source file Closes: #234711. + + Better code generation for if(!p) return NULL;return p; + Closes: #242318. + + PR rtl-optimization/16152: Perl ftbfs on {ia64,arm,m68k}-linux. + Closes: #255801. + + ICE (segfault) while compiling Linux 2.6.9 (closes: #277206). + + Link error building memtest (closes: #281445). + - Ada: + + PR ada/12450: Constraint error for valid input (closes: #210844). + + PR ada/13620: miscompilation of array initializer with + -O3 -fprofile-arcs. Closes: #226244. + - C: + + PR c/6897: Code produced with -fPIC reserves EBX, but compiles + bad __asm__ anyway (closes: #73065). + + PR c/9209: On i386, gcc-3.0 allows $ in indentifiers but not the asm. + Closes: #121282. + + PR c/11943: Accepts invalid declaration "int x[2, 3];" in C99 mode. + Closes: #177303. + + PR c/11942: restrict keyword broken in C99 mode. Closes: #187091. + + PR other/11370: -Wunreachable-code gives false complaints. + Closes: #196600. + + PR c/11369: Too relaxed checking with -Wstrict-prototypes. + Closes: #197504. + + PR c/11445: False positive warning with -Wunreachable-code. + Closes: #200140. + + PR c/11459: -stdc=c90 -pedantic warns about C90's non long-long + support when in C99 mode. Closes: #200392. + + PR c/456: Handling of constant expressions. Closes: #225935. + + ICE on invalid #define with -traditional (closes: #242916). + + No warning when initializing a variable with itself, new option + -Winit-self (closes: #293957). + - C++: + + C++ parse error (closes: #42946). + + PR libstdc++/9073: Replacement for __STL_ASSERTIONS (libstdc++v3 + debug mode). Closes: #128993. + + Parse errors in nested constructor calls (closes: #138561). + + PR optimization/1823: -ftrapv aborts with pointer difference due to + division optimization. Closes: #169862. + + ICE on invalid code (closes: #176101). + + PR c++/10199: ICE handling method parametrized by template. + Closes: #185604. + + High memory usage building packages OpenOffice.org and MythTV. + Closes: #194345, #194513. + + Improved documentation of std::lower_bound (closes: #196380). + + ICE in regenerate_decl_from_template (closes: #197674). + + PR c++/11444: Function fails to propagate up class tree + (template-related). Closes: #198042. + + ICE when using namespaced typedef of primitive type as struct. + Closes: #198261. + + Bug using streambuf / iostream to read from a named pipe. + Closes: #216105. + + PR c++/11437: ICE in lookup_name_real (closes: #200011). + + Add large file support (LFS) in libstdc++ (closes: #220000). + + PR c++/13621: ICE compiling a statement expression returning type + string (closes: #224413). + + g++ doesn't find inherited inner class after template instantiation. + Closes: #227518. + + PR libstdc++/13928: Add whatis info in man pages generated by doxygen. + Closes: #229642. + + Missing symbol _M_setstate in libstdc++ (closes: #232709). + + Unable to parse declaration of inline constructor explicit + specialization (closes: #234709). + + ICE (segfault) on invalid C++ code (closes: #246031). + + ICE in lookup_tempate_function (closes: #262441). + + Undefined symbols in libstdc++, when using specials char_traits. + Closes: #266110. + + PR libstdc++/16011: Outputting numbers with ostream in the locale fr_BE + causes infinite recursion (closes: #270795). + + ICE in tree_low_cst (closes: #276291). + + ICE in in expand_call (closes: #283503). + + typeof operator is misparsed in a template function (closes: #288555). + + ICE in tree_low_cs (closes: #291374). + + Improve uninformative error messages (closes: #292961, #293076). + + ICE on array initialization (closes: #294560). + + Failure to build xine-lib with -finline-functions (closes: #306854). + - Java: + + Fix error finding files in subdirectories (closes: #195480). + + Implement java.text.CollationElementIterator lacks getOffset(). + Closes: #259789. + - Treelang: + + Pointer truncation on 64bit architectures (closes: #308367). + - Architecture specific: + - alpha + + PR debug/10695: ICE on alpha while building agistudio. + Closes: #192568. + + ICE when building fceu (closes: #228018, #252764). + - amd64 + + Miscompilation of Objective-C code (closes: #250174). + + g++ hangs compiling k3d on amd64 (closes: #285364). + - arm + + PR target/19008: gcc -O3 -fPIC produces wrong code via auto inlining. + Closes: #285238. + - i386 + + PR target/4106: i386 -fPIC asm ebx clobber no error. + Closes: #153472. + + PR target/10984: x86/sse2 ICEs on vector intrinsics. Closes: #166940. + + Wrong code generation on at least ix86 (closes: #275655). + - m68k + + PR target/9201: ICE compiling octave-2.1 (closes: #175478). + + ICE in verify_initial_elim_offsets (closes: #204407, #257012). + + g77 generates invalid assembly code (closes: #225621). + + ICE in verify_local_live_at_start (closes #245584). + - powerpc + + PR optimization/12828: -floop-optimize is unstable on PowerPC (float + to int conversion problem). Closes: #218219. + + PR target/13619: ICE building altivec code in ffmpeg. + Closes: #226148. + + PR target/20046: Miscompilation of bind 9.3.0. Closes: #292958. + - sparc + + ICE (segfault) while building atlas3 on sparc32 (closes: #249108). + + Wrong optimization on sparc32 when building linux kernel. + Closes: #254626. + + * Closed reports reported against gcc-3.3 or gcc-3.4 and fixed in gcc-4.0: + - General: + + PR rtl-optimization/6901: Optimizer improvement (removing unused + local variables). Closes: #67206. + + PR middle-end/179: Failure to detect use of unitialized variable + with -O -Wall. Closes: #117765. + + ICE building glibc's nptl on amd64 (closes: #260710, #307993). + + PR middle-end/17827: ICE in make_decl_rtl. Closes: #270854. + + PR middle-end/21709: ICE on compile-time complex NaN. Closes: #305344. + - Ada: + + PR ada/10889: Convention Fortran matrices mishandled in generics. + Closes: #192135. + + PR ada/13897: Implement tasking on powerpc. Closes: #225346. + - C: + + PR c/13072: Bogus warning with VLA in switch. Closes: #218803. + + PR c/13519: typeof(nonconst+const) is const. Closes: #208981. + + PR c/12867: Incorrect warning message (void format, should be void* + format). Closes: #217360. + + PR c/16066: PR 16066] i386 loop strength reduction bug. + Closes: #254659. + - C++: + + PR c++/13518: -Wnon-virtual-dtor doesn't always work. Closes: #212260. + + PR translation/16025: ICE with unsupported locale(closes: #242158). + + PR c++/15125: -Wformat doesn't warn for different types in fprintf. + Closes: #243507. + + PR c++/15214: Warn only if the dtor is non-private or the class has + friends. (closes: #246639). + + PR libstdc++/17218: Unknown subjects in generated libstdc++ manpages. + Closes: #262934. + + PR libstdc++/17223: Missing .so references in generated libstdc++ + manpages. Closes: #262956. + + libstdc++-doc: Improve man pages (closes: #280910). + + PR c++/19006: ICE in tree_low_cst. Closes: #285692. + + g++ does not check arguments to fprintf. Closes: #281847. + - Java: + + PR java/7304: gcj ICE (closes: #152501). + + PR libgcj/7305: Installation of headers not directly in /usr/include. + Closes: #195483. + + PR libgcj/11941: libgcj timezone handling (closes: #203212). + + PR java/14709: gcj fails to wait for its child processes on exec(). + Closes: #238432. + + PR libgcj/21703: gcj hangs when rapidly calling String.intern(). + Closes: #275547. + + SocketChannel.get(ByteBuffer) returns 0 at EOF. Closes: #281602. + + PR java/19711: gcj segfaults instead of reporting the ambiguous + expression. Closes: #286715. + + Static libgcj contains repeated archive members (closes: #298263). + - Architecture specific: + - alpha + + Unaligned accesses with ?-operator (closes: #301983). + - arm + + Compilation error of glibc-2.3.4 on arm (closes: #298508). + - m68k + + ICE in add_insn_before (closes: #248432). + - mips + + Fix o32 ABI breakage in gcc 3.3/3.4 (closes: #270620). + - powerpc + + ICE in extract_insn (closes: #311128). + + * Closing bug reports as wontfix: + - g++ defines _GNU_SOURCE when using the libstdc++ header files. + Behaviour did change since 3.0. Closes: #126703, #164872. + + -- Matthias Klose Sat, 9 Jul 2005 17:10:54 +0000 + +gcc-4.0 (4.0.0ds2-12) unstable; urgency=high + + * Update to CVS 20050701, taken from the gcc-4_0-branch. + * Apply proposed patch for MMAP configure fix; aka PR 19877. Backport + from mainline. + * Disable Fortran on m68k. Currently FTBFS. + * Split multiarch-include/lib patches. Update multiarch-include patch. + * Fix FTBFS of the hppa64-linux cross compiler. Don't add the + multiarch include dirs when cross compiling. + * Configure --with-java-home, as used by java-gcj-compat. + Closes: #315646. + * Make libgcj-dbg packages priority extra. + * Set the path of classmap.db to /var/lib/gcj-@gcc_version@. + * On m68k, do not create the default classmap.db in the gcj postinst. + See #312830. + * On amd64, install the 32bit libraries into /emul/ia32-linux/usr/lib. + Restore the /usr/lib32 symlink. + * On amd64, don't reference lib64, but instead lib (lib64 is a symlink + to lib). Closes: #293050. + * Remove references to build directories from the .la files. + * Make cpp-X.Y conflict with earlier versions of gcc-X.Y, g++-X.Y, gobjc-X.Y, + gcj-X.Y, gfortran-X.Y, gnat-X.Y, treelang-X.Y, if a path component in + the gcc library path changes (i.e. version or target alias). + * Disable Ada for sh3 sh3eb sh4 sh4eb. + * For gcj-4.0, add a conflict to libgcj4-dev and libgcj5-dev. + Closes: #316499. + + -- Matthias Klose Sat, 2 Jul 2005 11:04:35 +0200 + +gcc-4.0 (4.0.0ds1-11) unstable; urgency=low + + * debian/rules.defs: Disable Ada for alpha. + * debian/rules.conf: Fix typo in type-handling replacement code. + * Don't ship an empty libgcj6-dbg package. + + -- Matthias Klose Thu, 23 Jun 2005 09:03:21 +0200 + +gcc-4.0 (4.0.0ds1-10) unstable; urgency=medium + + * debian/patches/libstdc++-api-compat.dpatch: Apply proposed patch + to fix libstdc++ 3.4.5/4.0 compatibility. + * type-handling output became insane. Don't use it anymore. + * Drop the reference to the stl-manual package (closes: #314983). + * Disable java on GNU/kFreeBSD targets, requested by Robert Millan. + Closes: #315140. + * Terminate the acats-killer process, even if the build is aborted + by the user (closes: #314405). + * debian/rules.defs: Define DEB_TARGET_ARCH_{OS,CPU}. + * Start converting the use of DEB_*_GNU_* to DEB_*_ARCH_* in the build + files. + * Do not configure with --enable-gtk-cairo. Needs newer gtk. Drop + build dependency on libcairo-dev. + * Fix setting of the system header directory for the hurd (Michael Banck). + Closes: #315386. + * Fix FTBFS on hurd-i386: MAXPATHLEN issue (Michael Banck). Closes: #315384. + + -- Matthias Klose Wed, 22 Jun 2005 19:45:50 +0200 + +gcc-4.0 (4.0.0ds1-9ubuntu2) breezy; urgency=low + + * Fix version number in libgcj shlibs file. + + -- Matthias Klose Sun, 19 Jun 2005 10:34:02 +0200 + +gcc-4.0 (4.0.0ds1-9ubuntu1) breezy; urgency=low + + * Update to 4.0.1, release candidate 2. + * libstdc++ shlibs file: Require 4.0.0ds1-9ubuntu1 as minimum version. + * Rename libawt to libgcjawt to avoid conflicts with other + libawt implementations (backport from HEAD). + * Update classpath awt, swing and xml parser for HTML support in swing. + Taken from classpath CVS HEAD 2005-06-18. Patch provided by Michael Koch. + * Remove the libgcj-buffer-strategy path, part of the classpath update. + * libgcj shlibs file: Require 4.0.0ds1-9ubuntu1 as minimum version. + * Require cairo-0.5 as build dependency. + * gij-4.0: Provide java1-runtime. + * gij-4.0: Provide an rmiregistry alternative (using grmiregistry-4.0). + * gcj-4.0: Provide an rmic alternative (using grmic-4.0). + * libgcj6-dev conflicts with libgcj5-dev, libgcj4-dev, not libgcj6. + Closes: #312741. + * libmudflap-entry-point.dpatch: Correct name of entry point on mips/mipsel. + * Apply proposed patch for PR 18421 and PR 18719 (m68k only). + * Apply proposed path for PR 21562. + * Add build dependency on dpkg (>= 1.13.7). + * On linux systems, configure for -linux-gnu. + * Configure the hppa64 cross compiler to target hppa64-linux-gnu. + * (Build-)depend on binutils-2.16.1. + * libstdc{32,64}++6-4.0-dbg: Depend on libstdc++6-4.0-dev. + * gnat-4.0: only depend on libgnat, when a shared libgnat is built. + * gfortran-4.0: Depend on libgmp3c2 | libgmp3. + * On hppa, explicitely use gcc-3.3 as a build dependency in the case + that Ada is disabled. + * libmudflap: Always build the library for the non-default biarch + architecture, or else the test results show link failures. + + -- Matthias Klose Sat, 18 Jun 2005 00:42:55 +0000 + +gcc-4.0 (4.0.0-9) unstable; urgency=low + + * Upload to unstable. + + -- Matthias Klose Wed, 25 May 2005 19:02:20 +0200 + +gcc-4.0 (4.0.0-8ubuntu3) breezy; urgency=low + + * debian/control: Regenerate. + + -- Matthias Klose Sat, 4 Jun 2005 10:56:27 +0200 + +gcc-4.0 (4.0.0-8ubuntu2) breezy; urgency=low + + * Fix powerpc-config-ml patch. + + -- Matthias Klose Fri, 3 Jun 2005 15:47:52 +0200 + +gcc-4.0 (4.0.0-8ubuntu1) breezy; urgency=low + + * powerpc biarch support: + - Enable powerpc biarch support, build lib64gcc1 on powerpc. + - Add patch to disable libstdc++'s configure checking, if it can't run + 64bit binaries on 32bit kernels (Sven Luther). + - Apply the same patch to the other runtime librararies as well. + - Run the testsuite with -m64, if we can execute 64bit binaries. + - Add libc6-dev-ppc64 as build dependency for powerpc. + * 32bit gcj libs for amd64. + * debian/logwatch.sh: Don't remove logwatch pid file on exit (suggested + by Ryan Murray). + * Update to CVS 20050603, taken from the gcc-4_0-branch. + * g++-4.0 provides c++abi2-dev. + * Loosen dependencies on packages of architecture `all' to not break + binary only uploads. + * Build libgfortran for biarch as well, else the testsuite will fail. + + -- Matthias Klose Fri, 3 Jun 2005 13:38:19 +0200 + +gcc-4.0 (4.0.0-8) experimental; urgency=low + + * Synchronize with Ubuntu. + + -- Matthias Klose Mon, 23 May 2005 01:56:28 +0000 + +gcc-4.0 (4.0.0-7ubuntu7) breezy; urgency=low + + * Fix build failures for builds with disabled testsuite. + * Adjust debian/rules conditionals to work with all dpkg versions. + * Build separate lib32stdc6-4.0-dbg/lib64stdc6-4.0-dbg packages. + * Add the debugging symbols of the optimzed libstdc++ build in the + lib*stdc++6-dbg packages as well. + * Build a libgcj6-dbg package. + * Update to CVS 20050522, taken from the gcc-4_0-branch. + * Add Ada support for the ppc64 architecture (Andreas Jochens): + * debian/patches/ppc64-ada.dpatch + - Add gcc/ada/system-linux-ppc64.ads, which has been copied from + gcc/ada/system-linux-ppc.ads and changed to use 'Word_Size' 64 + instead of 32. + - gcc/ada/Makefile.in: Use gcc/ada/system-linux-ppc64.ads on powerpc64. + * debian/rules.patch + - Use ppc64-ada patch on ppc64. + * debian/rules.d/binary-ada.mk + Place the symlinks libgnat.so, libgnat-4.0.so, libgnarl.so, + libgnarl-4.0.so in '/usr/lib' instead of '/adalib'. + Closes: #308948. + * Add libc6-dev-i386 as an alternative build dependency for amd64. + Closes: #305690. + + -- Matthias Klose Sun, 22 May 2005 22:14:20 +0200 + +gcc-4.0 (4.0.0-7ubuntu6) breezy; urgency=low + + * Don't trust dpkg-architecture (1.13.4), it "hurds" ... + + -- Matthias Klose Wed, 18 May 2005 11:36:38 +0200 + +gcc-4.0 (4.0.0-7ubuntu5) breezy; urgency=low + + * libgcj6-dev: Don't provide libgcj-dev. + + -- Matthias Klose Wed, 18 May 2005 00:30:32 +0000 + +gcc-4.0 (4.0.0-7ubuntu4) breezy; urgency=low + + * Update to CVS 20050517, taken from the gcc-4_0-branch. + * Apply proposed patch for PR21293. + + -- Matthias Klose Tue, 17 May 2005 23:05:40 +0000 + +gcc-4.0 (4.0.0-7ubuntu2) breezy; urgency=low + + * Update to CVS 20050515, taken from the gcc-4_0-branch. + + -- Matthias Klose Sun, 15 May 2005 23:48:00 +0200 + +gcc-4.0 (4.0.0-7ubuntu1) breezy; urgency=low + + * Synchronize with Debian. + + -- Matthias Klose Mon, 9 May 2005 19:35:29 +0200 + +gcc-4.0 (4.0.0-7) experimental; urgency=low + + * Update to CVS 20050509, taken from the gcc-4_0-branch. + * Remove the note from the fastjar package description, stating, that + fastjar is incomplete compared to the "standard" jar utility. + * Fix typo in build depends. dpkg-checkbuilddeps doesn't like a comma + inside []. + * Tighten shlibs dependencies to require the current version. + + -- Matthias Klose Mon, 9 May 2005 19:02:03 +0200 + +gcc-4.0 (4.0.0-6) experimental; urgency=low + + * Update to CVS 20050508, taken from the gcc-4_0-branch. + + -- Matthias Klose Sun, 8 May 2005 14:08:28 +0200 + +gcc-4.0 (4.0.0-5ubuntu1) breezy; urgency=low + + * Temporarily disable the i386 biarch build. Remove the amd64-libs-dev + build dependency, add (build-)conflict (<= 1.1ubuntu1). + + -- Matthias Klose Sat, 7 May 2005 16:56:21 +0200 + +gcc-4.0 (4.0.0-5) breezy; urgency=low + + * gnat-3.3 and gnat-4.0 are alternative build dependencies (closes: #308002). + * Update to CVS 20050507, taken from the gcc-4_0-branch. + * gcj-4.0: Install gjnih. + * Add libgcj buffer strategy framework (Thomas Fitzsimmons), needed for OOo2. + Backport from 4.1. + * Fix all lintian errors and most of the warnings. + + -- Matthias Klose Sat, 7 May 2005 12:26:15 +0200 + +gcc-4.0 (4.0.0-4) breezy; urgency=low + + * Still prefer gnat-3.3 over gnat-4.0 as a build dependency. + + -- Matthias Klose Fri, 6 May 2005 22:30:43 +0200 + +gcc-4.0 (4.0.0-3) breezy; urgency=low + + * Update to CVS 20050506, taken from the gcc-4_0-branch. + * Update priority of java alternatives to 40. + * Move gcj-dbtool to gij package, move the default classmap.db to + /var/lib/gcj-4.0/classmap.db. Create it in the postinst. + * Fix gcc-4.0-hppa64 postinst (closes: #307762). + * Fix gcc-4.0-hppa64, gij-4.0 and gcj-4.0 postinst, to not ignore errors + from update-alternatives. + * Fix gcc-4.0-hppa64, fastjar, gij-4.0 and gcj-4.0 prerm, + to not ignore errors from update-alternatives. + + -- Matthias Klose Fri, 6 May 2005 17:50:58 +0200 + +gcc-4.0 (4.0.0-2) experimental; urgency=low + + * GCC 4.0.0 release. + * Update to CVS 20050503, taken from the gcc-4_0-branch. + * Add gnat-4.0 as an alternative build dependency (closes: #305690). + + -- Matthias Klose Tue, 3 May 2005 15:41:26 +0200 + +gcc-4.0 (4.0.0-1) experimental; urgency=low + + * GCC 4.0.0 release. + + -- Matthias Klose Sun, 24 Apr 2005 11:28:42 +0200 + +gcc-4.0 (4.0ds11-0pre11) breezy; urgency=low + + * CVS 20050413, taken from the gcc-4_0-branch. + * Add proposed patches for PR20126, PR20490, PR20929. + + -- Matthias Klose Wed, 13 Apr 2005 09:43:00 +0200 + +gcc-4.0 (4.0ds10-0pre10) experimental; urgency=low + + * gcc-4.0.0-20050410 release candidate 1, built from the prerelease tarball. + - C++ fix for "optimizer breaks function inlining". Closes: #302989. + * Append the GCC version to the fastjar/grepjar version string. + * Use short file names in the libstdc++ docs (closes: #301140). + * Fix libstdc++-dbg dependencies (closes: #303866). + + -- Matthias Klose Mon, 11 Apr 2005 13:16:01 +0200 + +gcc-4.0 (4.0ds9-0pre9) experimental; urgency=low + + * CVS 20050326, taken from the gcc-4_0-branch. + * Reenable Ada on ia64. + * Build libgnat on hppa, sparc, s390 again. + * ppc64 support (Andreas Jochens): + * debian/control.m4 + - Add libc6-dev-powerpc [ppc64] to the Build-Depends. + - Change the Description for lib32gcc1: s/ia32/32 bit Version/ + * debian/rules.defs + - Define 'biarch_ia32' for ppc64 to use the same 32 bit multilib + facilities as amd64. + * debian/rules.d/binary-gcc.mk + - Correct an error in the 'files_gcc' definition for biarch_ia32 + (replace '64' by '32'). + * debian/rules2 + - Do not use '--disable-multilib' on powerpc64-linux. + Use '--disable-nof --disable-softfloat' instead. + * debian/rules.d/binary-libstdcxx.mk + - Put the 32 bit libstdc++ files in '/usr/lib32'. + * debian/rules.patch + - Apply 'ppc64-biarch' patch on ppc64. + * debian/patches/ppc64-biarch.dpatch + - MULTILIB_OSDIRNAMES: Use /lib for native 64 bit libraries and + /lib32 for 32 bit libraries. + - Add multilib handling to src/config-ml.in (taken from + amd64-biarch.dpatch). + * Rename biarch_ia32 to biarch32, as suggsted by Andreas. + * Use /bin/dash on hppa. + * Reenable the build of the hppa64 compiler. + * Enable parallel builds by defaults (set environment variale USE_NJOBS=no + or USE_NJOBS= to modify the default, which is to use the + number of available processors). + + -- Matthias Klose Sat, 26 Mar 2005 19:07:30 +0100 + +gcc-4.0 (4.0ds8-0pre8) experimental; urgency=low + + * CVS 20050322, taken from the gcc-4_0-branch. + - Add proposed fix for PR19406. + * Configure --with-gtk-cairo only if version 0.3.0 is found. + * Split out gcc-4.0-locales package. Better chance of getting + bug reports in english language. + + -- Matthias Klose Tue, 22 Mar 2005 14:20:24 +0100 + +gcc-4.0 (4.0ds7-0pre7) experimental; urgency=low + + * CVS 20050304, taken from the gcc-4_0-branch. + * Build the treelang compiler. + + -- Matthias Klose Fri, 4 Mar 2005 21:29:56 +0100 + +gcc-4.0 (4.0ds6-0pre6ubuntu6) hoary; urgency=low + + * Fix lib32gcc1 symlink on amd64. Ubuntu #7099. + + -- Matthias Klose Thu, 3 Mar 2005 00:17:26 +0100 + +gcc-4.0 (4.0ds6-0pre6ubuntu5) hoary; urgency=low + + * Add patch from PR20160, avoid creating archives with components + that have duplicate basenames. + + -- Matthias Klose Wed, 2 Mar 2005 14:22:04 +0100 + +gcc-4.0 (4.0ds6-0pre6ubuntu4) hoary; urgency=low + + * CVS 20050301, taken from the gcc-4_0-branch. + Test builds on i386, amd64, powerpc, ia64, check libgcc_s.so.1. + * Add fastjar-4.0 binary and manpage. Some java packages append it + for all java related tools. + * Add libgcj6-src package for source code availability in IDE's. + * On hppa, disable the build of the hppa64 cross compiler, disable + java, disable running the testsuite (request by Lamont). + * On amd64, lib32gcc1 replaces ia32-libs.openoffice.org (<< 1ubuntu3). + * Build-Depend on libcairo1-dev, configure with --enable-gtk-cairo. + Work around libtool problems install libjawt. + Install jawt header files in libgcj6-dev. + * Add workaround for PR debug/19769. + + -- Matthias Klose Tue, 1 Mar 2005 11:26:19 +0100 + +gcc-4.0 (4.0ds5-0pre6ubuntu3) hoary; urgency=low + + * Drop libgmp3-dev (<< 4.1.4-3) as an alterntative build dependency. + + -- Matthias Klose Thu, 10 Feb 2005 15:16:27 +0100 + +gcc-4.0 (4.0ds5-0pre6ubuntu2) hoary; urgency=low + + * Disable Ada for powerpc. + + -- Matthias Klose Wed, 9 Feb 2005 16:47:07 +0100 + +gcc-4.0 (4.0ds5-0pre6ubuntu1) hoary; urgency=low + + * Avoid build dependency on type-handling. + * Install 32bit libs on amd64 in /lib32 and /usr/lib32. + + -- Matthias Klose Wed, 9 Feb 2005 08:27:21 +0100 + +gcc-4.0 (4.0ds5-0pre6) experimental; urgency=low + + * gcc-4.0 snapshot, taken from the HEAD branch CVS 20050208. + * Build-depend on graphviz (moved to main), remove the pregenerated + libstdc++ docs from the diff. + * Fix PR19162, libobjc build failure on arm-linux (closes: #291497). + + -- Matthias Klose Tue, 8 Feb 2005 11:47:31 +0000 + +gcc-4.0 (4.0ds4-0pre5) experimental; urgency=low + + * gcc-4.0 snapshot, taken from the HEAD branch CVS 20050125. + * Call the 4.0 gcx versions in the java wrappers (closes: #291075). + * Correctly install libgij (closes: #291077). + * libgcj6-dev: Add conflicts to other libgcj-dev packages (closes: #290950). + + -- Matthias Klose Mon, 24 Jan 2005 23:59:54 +0100 + +gcc-4.0 (4.0ds3-0pre4) experimental; urgency=low + + * gcc-4.0 snapshot, taken from the HEAD branch CVS 20050115. + * Update cross build patches (Nikita V. Youshchenko). + * Enable Ada on i386, amd64, mips, mipsel, powerpc, sparc, s390. + Doesn't yet bootstrap on alpha, hppa, ia64. + + -- Matthias Klose Sat, 15 Jan 2005 18:44:03 +0100 + +gcc-4.0 (4.0ds2-0pre3) experimental; urgency=low + + * gcc-4.0 snapshot, taken from the HEAD branch CVS 20041224. + + -- Matthias Klose Wed, 22 Dec 2004 00:31:44 +0100 + +gcc-4.0 (4.0ds1-0pre2) experimental; urgency=low + + * gcc-4.0 snapshot, taken from the HEAD branch CVS 20041205. + * Lot's of merges and updates from the gcc-3.4 packages. + + -- Matthias Klose Sat, 04 Dec 2004 12:14:51 +0100 + +gcc-4.0 (4.0ds0-0pre1) experimental; urgency=low + + * gcc-4.0 snapshot, taken from the HEAD branch CVS 20041114. + - Addresses many issues with the libstdc++ man pages (closes: #278549). + * Disable Ada on hppa, ia64, mips, mipsel, powerpc, s390 and sparc, at least + these are known to be broken at the time of the snapshot. + * Minor kbsd.gnu build fixes (Robert Millan). Closes: #273004. + * For amd64, add missing libstdc++ files to 'libstdc++6-dev' package. + (Andreas Jochens). Fixes: #274362. + * Update libffi-mips patch (closes: #274096). + * Updated i386-biarch patch. Don't build 64bit libstdc++, ICE. + * Update sparc biarch patch. + * Fix symlinks for gfortran manpage (closes: #278548). + * Update cross build patches (Nikita V. Youshchenko). + * Update Ada patches (Ludovic Brenta). + + -- Matthias Klose Sat, 13 Nov 2004 10:38:25 +0100 + +gcc-4.0 (4.0-0pre0) experimental; urgency=low + + * gcc-4.0 snapshot, taken from the HEAD branch CVS 20040912. + + * Matthias Klose + + - Integrate accumulated packaging patches from gcc-3.4. + - Rename libstdc++6-* packages to libstdc++6-4-* (closes: #261693). + - libffi4-dev: conflict with libffi3-dev (closes: #265939). + + * Robert Millan + + * control.m4: + - s/locale_no_archs !hurd-i386/locale_no_archs/g + (This is now handled in rules.defs. [1]) + - s/procps [check_no_archs]/procps [linux_gnu_archs]/g [2] + - Add type-handling to build-deps. [3] + * rules.conf: + - Don't require (>= $(libc_ver)) for libc0.1-dev. [4] + - Generate *_no_archs variables with type-handling and use them for + for m4's -D parameters. [3] + * rules.defs: + - use filter instead of findstring [1]. + - s/netbsd-elf-gnu/netbsdelf-gnu/g [5]. + - enable java for kfreebsd-gnu [6] + - enable ffi for kfreebsd-gnu and knetbsd-gnu [6] + - enable libgc for kfreebsd-gnu [6] + - enable checks for kfreebsd-gnu and knetbsd-gnu [7] + - enable locales for kfreebsd-gnu and gnu [1] [8]. + * Closes: #264025. + + -- Matthias Klose Sun, 12 Sep 2004 12:52:56 +0200 + +gcc-3.5 (3.5ds1-0pre1) experimental; urgency=low + + * gcc-3.5 snapshot, taken from the HEAD branch CVS 20040724. + * Install locale data with versioned package name (closes: #260497). + * Fix libgnat symlinks. + + -- Matthias Klose Sat, 24 Jul 2004 21:26:23 +0200 + +gcc-3.5 (3.5-0pre0) experimental; urgency=low + + * gcc-3.5 snapshot, taken from the HEAD branch CVS 20040718. + + -- Matthias Klose Sun, 18 Jul 2004 12:26:00 +0200 + +gcc-3.4 (3.4.1-1) experimental; urgency=low + + * gcc-3.4.1 final release. + - configured wth --enable-libstdcxx-allocator=mt. + * Fixes for generating cross compiler packages (Jeff Bailey). + + -- Matthias Klose Fri, 2 Jul 2004 22:49:05 +0200 + +gcc-3.4 (3.4.0-4) experimental; urgency=low + + * gcc-3.4.1 release candidate 1. + * Add logic to build biarch compiler on powerpc (disabled, needs lib64c). + * Don't build the libg2c0 package on mipsel-linux (no clear answer on + debian-mips, if the libg2c0's built by gcc-3.3 and gcc-3.4 are compatible + (post-sarge issue). + * Don't use gcc-2.95 as bootstrap compiler on m68k anymore. + + -- Matthias Klose Sat, 26 Jun 2004 22:40:20 +0200 + +gcc-3.4 (3.4.0-3) experimental; urgency=low + + * Update to gcc-3.4 CVS 20040613. + * On sparc, set the the build target to sparc64-linux, build with + switch defaulting to code generation for v7. To generate code for + sparc64, use the -m64 switch. + * Add missing doc-base files to -doc packages. + * Add portability patches and kbsd-gnu patch (Robert Millan). + Closes: #251293, #251294. + * Apply fixes for cross build (Nikita V. Youshchenko). + * Do not include the precompiled libstdc++ header files into the -dev + package (still experimental). Closes: #251707. + * Reflect renaming of Ada user's guide. + * Move AWT peer libraries for libgcj into it's own package (fixes: #247791). + + -- Matthias Klose Mon, 14 Jun 2004 00:03:18 +0200 + +gcc-3.4 (3.4.0-2) experimental; urgency=low + + * Update to gcc-3.4 CVS 20040516. + * Do not provide the /usr/hppa64-linux/include in the gcc-hppa64 package, + migrated to libc6-dev. Adjust dependencies. + * Integrate gpc test results into the GCC test summary. + * gnatchop calls gcc-3.4 (closes: #245438). + * debian/locale-gen.sh: Update for recent libstdc+++ testsuite. + * debian/copyright: Add libstdc++-v3's exception clause. + * Add libffi update for mips (Thiemo Seufer). + * Reference Debian specific bug reporting instructions. + * Update README.Bugs. + * Fix FTBFS for libstdc++-doc. + * Update libjava patch for hppa (Randolph Chung). + * Fix installation of ffitarget.h header file. + * On amd64-linux, configure --without-multilib, disable Ada. + + -- Matthias Klose Sun, 16 May 2004 07:53:39 +0200 + +gcc-3.4 (3.4.0-1) experimental; urgency=low + + * gcc-3.4.0 final release. + + * Why experimental? + - Do not interfer with packages currently built from gcc-3.3 sources, + i.e. libgcc1, libobjc1, libffi2, libffi2-dev, libg2c0. + - Biarch sparc compiler doesn't built yet. + - Use of configure flags affecting binary ABI's not yet determined. + - Several ABI bugs have been fixed. Unfortunately, these changes will break + binary compatibility with earlier releases on several architectures: + alpha, mips, sparc, + - hppa and m68k changed sjlj based exception handling to dwarf2 based + exception handling. + + See NEWS.html or http://gcc.gnu.org/gcc-3.4/changes.html for more + specific information. + + -- Matthias Klose Tue, 20 Apr 2004 20:54:56 +0200 + +gcc-3.4 (3.4ds3-0pre4) experimental; urgency=low + + * Update to gcc-3.4 CVS 20040403. + * Add gpc tarball, gpc patches for 3.4 (Waldek Hebisch). + * Reenable sparc-biarch patches (closes: #239856). + * Build the shared libgnat library, needed to fix FTBFS for some + Ada library packages (Ludovic Brenta). + Currently enabled for hppa, i386, ia64. + + -- Matthias Klose Sat, 3 Apr 2004 08:47:55 +0200 + +gcc-3.4 (3.4ds1-0pre2) experimental; urgency=low + + * Update to gcc-3.4 CVS 20040320. + * For libstdc++6-doc, add a conflict to libstdc++5-3.3-doc (closes: #236560). + * For libstdc++6-dbg, add a conflict to libstdc++5-3.3-dbg (closes: #236798). + * Reenable s390-biarch patches. + * Update the cross compiler build files (Nikita V. Youshchenko). + + -- Matthias Klose Sat, 20 Mar 2004 09:15:10 +0100 + +gcc-3.4 (3.4ds0-0pre1) experimental; urgency=low + + * Start gcc-3.4 packaging, get rid of the epoch for most of the + packages. + + -- Matthias Klose Sun, 22 Feb 2004 16:00:03 +0100 + +gcc-3.3 (1:3.3.3ds6-6) unstable; urgency=medium + + * Update to gcc-3_3-branch CVS 20040401. + - Fixed ICE in emit_move_insn_1 on legal code (closed: #223215). + - Fix PR 14755, miscompilation of loops with bitfield counter. + Closes: #241255. + - Fix PR 16040, crash in function initializing const data with + reinterpret_cast-ed pointer-to-member function crashes (closes: #238621). + - Remove patches integrated upstream. + * Reenable build of gpidump on powerpc and s390. + + -- Matthias Klose Thu, 1 Apr 2004 23:51:54 +0200 + +gcc-3.3 (1:3.3.3ds6-5) unstable; urgency=medium + + * Update to gcc-3_3-branch CVS 20040321. + - Fix PR target/13889 (ICE on valid code on m68k). + * Fix FTFBS on s390. Do not build gpc's gpidump on s390. + * Reenable gpc on arm. + + -- Matthias Klose Mon, 22 Mar 2004 07:37:26 +0100 + +gcc-3.3 (1:3.3.3ds6-4) unstable; urgency=low + + * Update to gcc-3_3-branch CVS 20040320. + - Revert patch for PR14640 (with this, at least mozilla-firefox was + miscompiled on x86 (closes: #238621). + * Update the gpc tarball (there were two releases with the same name ...). + * Reenable gpc on alpha and ia64. + + -- Matthias Klose Sat, 20 Mar 2004 07:39:24 +0100 + +gcc-3.3 (1:3.3.3ds5-3) unstable; urgency=low + + * Update to gcc-3_3-branch CVS 20040314. + - Fixes miscompilation with -O -funroll-loops on powerpc (closes: #229567). + - Fix ICE in dwarf-2 on code using altivec (closes: #203835). + * Update hurd-changes patch. + * Add libgcj4-dev as a recommendation for gcj (closes: #236547). + * debian/copyright: Added exemption to static linking of libgcc. + + * Phil Blundell: + - debian/patches/arm-ldm.dpatch, debian/patches/arm-gotoff.dpatch: Update. + + -- Matthias Klose Sun, 14 Mar 2004 09:56:06 +0100 + +gcc-3.3 (1:3.3.3ds5-2) unstable; urgency=low + + * Update to gcc-3_3-branch CVS 20040306. + - Fixes bootstrap comparision error on ia64. + - Allows ghc build with gcc-3.3. + - On amd64, don't imply 3DNow! for -m64 by default. + - Some arm specific changes + - Fix C++/13944: exception in constructor of a class to be thrown is not + caught. Closes: #228099. + * Enable the build of gcc-3.3-hppa64 on hppa. + Add symlinks for as and ld to point to hppa64-linux-{as,ld}. + * gcj-3.3 depends on g++-3.3, recommends gij-3.3. gij-3.3 suggests gcj-3.3. + * Fix libgc2c-pic compatibility links (closes: #234333). + The link will be removed for gcc-3.4. + * g77-3.3: Conflict with other g77-x.y packages. + * Tighten shlibs dependencies to latest released versions. + + * Phil Blundell: + - debian/patches/arm-233633.dpatch: New Fixes problems with half-word + loads on ARMv3 architecture. (Closes: #233633) + - debian/patches/arm-ldm.dpatch: New. Avoids inefficient epilogue for + leaf functions in PIC code on ARM. + + -- Matthias Klose Sat, 6 Mar 2004 10:57:14 +0100 + +gcc-3.3 (1:3.3.3ds5-1) unstable; urgency=medium + + * gcc-3.3.3 final release. + See /usr/share/doc/gcc-3.3/NEWS.{gcc,html}. + + -- Matthias Klose Mon, 16 Feb 2004 08:59:52 +0100 + +gcc-3.3 (1:3.3.3ds4-0pre4) unstable; urgency=low + + * Update to gcc-3.3.3 CVS 20040214 (2nd gcc-3.3.3 prerelease). + * Fix title of libstdc++'s html main index (closes: #196381). + * Move libg2c libraray files out of the gcc specific libdir to /usr/lib. + For g77-3.3 add conflicts to other g77 packages. Closes: #224848. + * Update the stack protector patch to 3.3-7, but don't apply it by default. + Closes: #230338. + * On arm, use arm6 as the cpu default (backport from mainline, PR12527). + * Add libffi and libjava support for hppa (Randolph Chung). Closes: #232615. + + -- Matthias Klose Sat, 14 Feb 2004 09:26:15 +0100 + +gcc-3.3 (1:3.3.3ds3-0pre3) unstable; urgency=low + + * Update to gcc-3.3.3 CVS 20040125. + - Fixed PR11350, undefined labels with -Os -fPIC (closes: #195911). + - Fixed PR11793, ICE in extract_insn, at recog.c (closes: #203835). + - Fixed PR13544, removed backport for PR12862. + - Integrated backport for PR12441. + * Fixed since 3.3: java: not implemented interface methods of abstract + classes not found (closes: #225438). + * Disable pascal on arm architecture (currently broken). + * Update the build files to build a cross compiler (Nikita V. Youshchenko). + See debian/README.cross in the source package. + * Apply revised patch to make -mieee the default on alpha-linux, + and add -mieee-disable switch to turn the default off (closes: #212912). + (Tyson Whitehead) + + -- Matthias Klose Sun, 25 Jan 2004 17:41:04 +0100 + +gcc-3.3 (1:3.3.3ds2-0pre2) unstable; urgency=medium + + * Update to gcc-3.3.3 CVS 20040110. + - Fixes compilation not terminating at -O1 on hppa (closes: #207516). + * Add backport to fix PR12441 (closes: #224576). + * Revert backport to 3.3 branch to fix PR12862, which introduced another + regression (PR13544). Closes: #225663. + * Tighten dependency of gnat-3.3 on gcc-3.3 (closes: #226273). + * Disable treelang build for cross compiler build. + * Disable pascal on alpha and ia64 architectures (currently broken). + + -- Matthias Klose Sat, 10 Jan 2004 12:33:59 +0100 + +gcc-3.3 (1:3.3.3ds1-0pre1) unstable; urgency=low + + * Update to gcc-3.3.3 CVS 20031229. + - Fixes bootstrap error on ia64-linux. + - Fix -pthread on mips{,el}-linux (closes: #224875). + - Fix -Wformat for C++ (closes: #217075). + * Backport from mainline: Preserve inline-ness when redeclaring + a function template (closes: #195264). + * Add missing intrinsics headers on ix86 (closes: #224593). + * Fix location of libg2c libdir in libg2c.la file (closes: #224848). + + -- Matthias Klose Mon, 29 Dec 2003 10:36:29 +0100 + +gcc-3.3 (1:3.3.3ds0-0pre0.1) unstable; urgency=high + + * NMU + * Fixed mips(el) spec file for -pthread: (Closes: #224875) + * [debian/patches/mips-pthread.dpatch] New. + * [debian/rules.patch] Added it to debian_patches. + + -- J.H.M. Dassen (Ray) Sat, 27 Dec 2003 15:51:47 +0100 + +gcc-3.3 (1:3.3.3ds0-0pre0) unstable; urgency=low + + * Update to gcc-3.3.3 CVS 20031206. + - Fixes ICE in verify_local_live_at_start (hppa). Closes: #201550. + - Fixes miscompilation of linux-2.6/sound/core/oss/rate.c. + Closes: #219949. + * Add missing unwind.h to gcc package (closes: #220846). + * Regenerate control file to fix build dependencies for m68k. + * More gpc only patches to fix test failures on m68k. + * Reenable gpc for the Hurd (closes: #189851). + + -- Matthias Klose Sat, 6 Dec 2003 10:29:07 +0100 + +gcc-3.3 (1:3.3.2ds5-4) unstable; urgency=low + + * Update libffi-dev package description (closes: #219508). + * For gij and libgcj fix dependency on the libstdc++ package, if + the latter isn't installed during the build. + * Apply patch to emit .note.GNU-stack section on linux arches + which by default need executable stack. + * Prefer gnat-3.3 over gnat-3.2 as a build dependency. + * Update the pascal tarball (different version released with the + same name). + * Add pascal patches to address various gpc testsuite failures. + On alpha and ia64, build gpc from the 20030830 version. Reenable + the build on m68k. + Remove the 20030507 gpc version from the tarball. + * Apply patch to build the shared ada libs and link the ada tools + against the shared libs. Not enabled by default, because gnat + and gnatlib are rebuilt during install. (Ludovic Brenta) + + -- Matthias Klose Sun, 9 Nov 2003 22:34:33 +0100 + +gcc-3.3 (1:3.3.2ds4-3) unstable; urgency=low + + * Fix rules to omit inclusion of gnatpsta in mips(el) gnat package. + + -- Matthias Klose Sun, 2 Nov 2003 14:29:59 +0100 + +gcc-3.3 (1:3.3.2ds4-2) unstable; urgency=medium + + * s390-ifcvt patch added. Fixes gcl miscompilation (closes: #217240). + (Gerhard Tonn) + * Fix an infinite loop in g++ compiling lufs, regression from 3.3.1. + * Fix a wrong code generation bug on alpha. + (Falk Hueffner) + * Update NEWS files. + * Add Falk Hueffner to the Debian GCC maintainers. + * Enable ada on mips and mipsel, but don't build the gnatpsta tool. + + -- Matthias Klose Wed, 29 Oct 2003 00:12:37 +0100 + +gcc-3.3 (1:3.3.2ds4-1) unstable; urgency=medium + + * Update to gcc-3.3.2. + * Update NEWS files. + * Miscompilation in the pari package at -O3 fixed (closes: #198172). + * On alpha-linux, revert -mieee as the default (Falk Hueffner). + Reopens: #212912. + * Add ia64-unwind patch (Jeff Bailey). + * Closed reports reported against gcc-2.96 (ia64), fixed at least in gcc-3.3: + - ICE in verify_local_live_at_start, at flow.c:2733 (closes: #135404). + - Compilation failure of stlport (closes: #135224). + - Infinite loop compiling cssc's pfile.cc with -O2 (closes: #115390). + - Added missing some string::compare() members (closes: #141199). + - header declares std::pow (closes: #161853). + - does have at() method (closes: #59776). + - Fixed error in stl_deque.h (closes: #69530). + - Fixed problem with bastring (closes: #75759, #96539). + - bad_alloc and std:: namespace problem (closes: #75120). + - Excessive warnings from headers with -Weffc++ (closes: #76827). + + -- Matthias Klose Fri, 17 Oct 2003 08:07:01 +0200 + +gcc-3.3 (1:3.3.2ds3-0pre5) unstable; urgency=low + + * Update to gcc-3.3.2 CVS 20031005. + - Fixes cpp inserting a spurious newline (closes: #210478, #210482). + - Fixes generation of unrecognizable insn compiling kernel source + on alpha (closes: #202762). + - Fixes ICE in add_abstract_origin_attribute (closes: #212406). + - Fixes forward declaration in libstdc++ (closes: #209386). + - Fixes ICE in in extract_insn, at recog.c on alpha (closes: #207564). + * Make libgcj-common architecture all (closes: #211909). + * Build depend on: flex-old | flex (<< 2.5.31). + * Fix spec linking libraries with -pthread on powerpc (closes: #211054). + * debian/patches/arm-gotoff.dpatch: fix two kinds of PIC lossage. + (Phil Blundell) + * debian/patches/arm-common.dpatch: fix excessive alignment of common + blocks causing binutils testsuite failures. + (Phil Blundell) + * Update priorities in debian/control to match the archive. + (Ryan Murray) + * s390-nonlocal-goto patch added. Fixes some pascal testcase failures. + (Gerhard Tonn) + * On alpha-linux, make -mieee default and add -mieee-disable switch + to turn default off (closes: #212912). + (Tyson Whitehead) + * Add gpc upstream patch for memory corruption fix. + + -- Matthias Klose Sun, 5 Oct 2003 19:53:49 +0200 + +gcc-3.3 (1:3.3.2ds2-0pre4) unstable; urgency=low + + * Add gcc-unsharing_lhs patch (closes: #210848) + + -- Ryan Murray Fri, 19 Sep 2003 22:51:19 -0600 + +gcc-3.3 (1:3.3.2ds2-0pre3) unstable; urgency=low + + * Update to gcc-3.3.2 CVS 20030908. + * PR11716 (Michael Eager, Dan Jacobowitz): + Make GCC think that the maximum length of a short branch is + 64K instead of 128K. It's a big hammer, but it works. + Closes: #207915. + * Downgrade gpc to 20030507 on alpha and ia64 (closes: #208717). + + -- Matthias Klose Mon, 8 Sep 2003 21:49:52 +0200 + +gcc-3.3 (1:3.3.2ds1-0pre2) unstable; urgency=low + + * Update to gcc-3.3.2 CVS 20030831. + - Fix java NullPointerException detection with 2.6 kernels. + Closes: #206377. + - Fix bug in C++ typedef handling (closes: #205402). + - Fix -Wunreachable-code giving false complaints (closes: #196600). + * Update to gpc-20030830. + * Don't include /usr/share/java/repository into the class path according + to the new version of th Debian Java policy (closes: #205643). + * Build-Depend/Depend on libgc-dev. + + -- Matthias Klose Sun, 31 Aug 2003 08:56:53 +0200 + +gcc-3.3 (1:3.3.2ds0-0pre1) unstable; urgency=low + + * Remove the build dependency on locales for now. + + -- Matthias Klose Fri, 15 Aug 2003 07:48:18 +0200 + +gcc-3.3 (1:3.3.2ds0-0pre0) unstable; urgency=medium + + * Update to gcc-3.3.2 CVS 20030812. + - Fixes generation of wrong code for XDM-AUTHORIZATION-1 key generation + and/or validation. Closes: #196090. + * Update NEWS files. + * Change ix86 default CPU type for code generation: + - i386-linux -> i486-linux + - i386-gnu -> i586-gnu + - i386-freebsd-gnu -> i486-freebsd-gnu + Use -march=i386 to target i386 CPUs. + + -- Matthias Klose Tue, 12 Aug 2003 10:31:28 +0200 + +gcc-3.3 (1:3.3.1ds3-1) unstable; urgency=low + + * gcc-3.3.1 (taken from CVS 20030805). + - C++: Fix declaration conflicts (closes: #203351). + - Fix ICE on ia64 (closes: #203840). + + -- Matthias Klose Tue, 5 Aug 2003 20:38:02 +0200 + +gcc-3.3 (1:3.3.1ds2-0rc2) unstable; urgency=low + + * Update to gcc-3.3.1 CVS 20030728. + - Fix ICE in extract_insn, at recog.c:2148 on m68k. + Closes: #177840, #180375, #190818. + - Fix ICE while building libquicktime on alpha (closes: #192576). + - Fix failure to deal with using and private inheritance (closes: #202696). + * On sparc, /usr/lib was added to the library search path. Fix it. + * Closed reports reported against gcc-3.2.x and fixed in gcc-3.3: + - Fix error building the gcl package on arm (closes: #199835). + + -- Matthias Klose Mon, 28 Jul 2003 20:39:07 +0200 + +gcc-3.3 (1:3.3.1ds1-0rc1) unstable; urgency=low + + * Update to gcc-3.3.1 CVS 20030722 (3.3.1 release candidate 1). + - Fix ICE in copy_to_mode_reg on 64-bit targets (closes: #189365). + - Remove documentation about multi-line strings (closes: #194391). + - Correctly document -falign-* parameters (closes: #198269). + - out-of-class specialization of a private nested template class. + Closes: #193830. + - Tighten shlibs dependency due to new symbols in libgcc. + * README.Debian for libg2c0, describing the need for g77-x.y when + working with the g2c header and library (closes: #189059). + * Call make with -j, if USE_NJOBS is set and non-empty + in the environment. + * Add another two m68k patches, partly replacing the workarounds provided + by Roman Zippel. + * Add the stack protector patch, but don't apply it by default. Edit + debian/rules.patch to apply it (closes: #171699, #189494). + * Remove wrong symlinks from gnat package (closes: #201882). + * Closed reports reported against gcc-2.95 and fixed in newer versions: + - SMP kernel compilation on alpha (closes: #134197, #146883). + - ICE on arm while building imagemagick (closes: #173475). + * Closed reports reported against gcc-3.2.x and fixed in gcc-3.3: + - Miscompilation of octave2.1 on hppa (closes: #192296, #193804). + + -- Matthias Klose Sun, 13 Jul 2003 10:26:30 +0200 + +gcc-3.3 (1:3.3.1ds0-0pre0) unstable; urgency=medium + + * Update to gcc-3.3.1 CVS 20030626. + - Fix ICE on arm compiling xfree86 (closes: #195424). + - Fix ICE on arm compiling fftw (closes: #186185). + - Fix ICE on arm in change_address_1, affecting a few packages. + Closes: #197099. + - Fix ICE in merge_assigned_reloads building Linux 2.4.2x sched.c. + Closes: #195237. + - Do not warn about failing to inline functions declared in system headers. + Closes: #193049. + - Fix ICE on mips{,el} in propagate_one_insn (closes: #194330, #196091). + - Fix ICE on m68k in reg_overlap_mentioned_p (closes: #194749). + - Build crtbeginT.o on m68k (closes: #197613). + * Fix g++ man page symlink (closes: #196271). + * mips/mipsel: Depend on binutils (>= 2.14.90.0.4). Closes: #196744. + * Disable treelang on powerpc (again). Closes: #196915. + * Pass -encoding in gcj-wrapper. + + -- Matthias Klose Fri, 27 Jun 2003 00:14:43 +0200 + +gcc-3.3 (1:3.3ds9-3) unstable; urgency=low + + * Closing more reports, fixed in 3.2/3.3: + - ICE building texmacs on m68k (closes: #177433). + - libstdc++: doesn't define trunc(...) (closes: #105285). + - libstdc++: setw is ignored for strings output (closes: #52382, #76645). + * Add build support to omit the manual pages and info docs from the + packages, disabled by default. Wait for a Debian statement, which can + be cited. Adresses: #193787. + * Reenable the m68k-const patch, don't run the g77 testsuite on m68k. + Addresses ICEs (#177840, #190818). + * Update arm-xscale patch. + * libstdc++: use __attribute__(__unknown__), instead of (unknown). + Closes: #195796. + * Build-Depend on glibc (>= 2.3.1) to prevent incorrect builds on woody. + Request from Adrian Bunk. + * Add treelang-update patch (Tim Josling), reenable treelang on powerpc. + * Add -{cpp,gcc,g++,gcj,g77} symlinks (addresses: #189466). + * Make sure not to build using binutils-2.14.90.0.[12]. + + -- Matthias Klose Mon, 2 Jun 2003 22:35:45 +0200 + +gcc-3.3 (1:3.3ds9-2) unstable; urgency=medium + + * Correct autoconf-related snafu in newly added ARM patches (Phil Blundell). + * Correct libgcc1 dependency (closes: #193689). + * Work around ldd/dpkg-shlibs failure on s390x. + + -- Matthias Klose Sun, 18 May 2003 09:40:15 +0200 + +gcc-3.3 (1:3.3ds9-1) unstable; urgency=low + + * gcc-3.3 final release. + See /usr/share/doc/gcc-3.3/NEWS.{gcc,html}. + * First merge of i386/x86-64 biarch support (Arnd Bergmann). + Disabled by default. Closes: #190066. + * New gpc-20030507 version. + * Upstream gpc update to fix netbsd build failure (closes: #191407). + * Add arm-xscale.dpatch, arm-10730.dpatch, arm-tune.dpatch, copied + from gcc-3.2 (Phil Blundell). + * Closing bug reports reported against older gcc versions (some of them + still present in Debian, but not anymore as the default compiler). + Usually, forwarded bug reports are linked to + http://gcc.gnu.org/PR + The upstream bug number usually can be found in the Debian reports. + + * Closed reports reported against gcc-3.1.x, gcc-3.2.x and fixed in gcc-3.3: + - General: + + GCC accepts multi-line strings without \ or " " &c (closes: #2910). + + -print-file-name sometimes fails (closes: #161615). + + ICE: reporting routines re-entered (closes: #179597, #180937). + + Misplaced paragraph in gcc documentation (closes: #179363). + + Error: suffix or operands invalid for `div' (closes: #150558). + + builtin memcmp() could be optimised (closes: #85535). + - Ada: + + Preelaborate, exceptions, and -gnatN (closes: #181679). + - C: + + Duplicate loop conditions even with -Os (closes: #94701). + + ICE (signal 11) (closes: #65686). + - C++: + + C++ error on virtual function which uses ... (closes: #165829). + + ICE when warning about cleanup nastiness in switch statements + (closes: #184108). + + Fails to compile virtual inheritance with variable number of + argument method (closes: #151357). + + xmmintrin.h broken for c++ (closes: #168310). + + Stack corruption with variable-length automatic arrays and virtual + destructors (closes: #188527). + + ICE on illegal code (closes: #184862). + + _attribute__((unused)) is ignored in C++ (closes: #45440). + + g++ handles &(void *)foo bizzarely (closes: #79225). + + ICE (with wrong code, though) (closes: #81122). + - Java: + + Broken zip file handling (closes: #180567). + - ObjC: + + @protocol forward definitions do not work (closes: #80468). + - Architecture specific: + - alpha + + va_start is off by one (closes: #186139). + + ICE while building kseg/ddd (closes: #184753). + + g++ -O2 optimization error (closes: #70743). + - arm + + ICE with -O2 in change_address_1 (closes: #180750). + + gcc optimization error with -O2, affecting bison (closes: #185903). + - hppa + + ICE in insn_default_length (closes: #186447). + - ia64 + + gcc-3.2 fails w/ optimization (closes: #178830). + - i386 + + unnecessary generation of instruction cwtl (closes: #95318). + + {athlon} ICE building mplayer (closes: #184800). + + {pentium4} ICE while compiling mozilla with -march=pentium4 + (closes: #187910). + + i386 optimisation: joining tests (closes: #105309). + - m68k + + ICE in instantiate_virtual_regs_1 (closes: #180493). + + gcc optimizer bug on m68k (closes: #64832). + - powerpc + + ICE in extract_insn, at recog.c:2175 building php3 (closes: #186299). + + ICE with -O -Wunreachable-code (closes: #189702). + - s390 + + Operand out of range at assembly time when using -O2 + (closes: #178596). + - sparc + + gcc-3.2 regression (wrong code) (closes: #176387). + + ICE in mem_loc_descriptor when optimizing (closes: #178909). + + ICE in gen_reg_rtx when optimizing (closes: #178965). + + Optimisation leads to unaligned access in memcpy (closes: #136659). + + * Closed reports reported against gcc-3.0 and fixed in gcc-3.2.x: + - General: + + Use mkstemp instead of mktemp (closed: #127802). + - Preprocessor: + + Fix redundant error message from cpp (closed: #100722). + - C: + + Optimization issue on ix86 (pointless moving) (closed: #97904). + + Miscompilation of allegro on ix86 (closed: #105741). + + Fix generation of ..ng references for static aliases (alpha-linux). + (closed: #108036). + + ICE compiling pari on hppa (closed: #111613). + + ICE on ia64 in instantiate_virtual_regs_1 (closed: #121668). + + ICE in c-typeck.c (closed: #123687). + + ICE in gen_subprogram_die on alpha (closed: #127890). + + SEGV in initialization of flexible char array member (closed: #131399). + + ICE on arm compiling lapack (closed: #135967). + + ICE in incomplete_type_error (closed: #140606). + + Fix -Wswitch (also part of -Wall) (closed: #140995). + + Wrong code in mke2fs on hppa (closed: #150232). + + sin(a) * sin(b) gives wrong result (closed: #164135). + - C++: + + Error in std library headers on arm (closed: #107633). + + ICE nr. 19970302 (closed: #119635). + + std::wcout does not perform encoding conversions (closed: #128026). + + SEGV, when compiling iostream.h with -fPIC (closed: #134315). + + Fixed segmentation fault in included code for (closed: #137017). + + Fix with exception handling and -O (closed: #144232). + + Fix octave-2.1 build failure on ia64 (closed: #144584). + + nonstandard overloads in num_get facet (closed: #155900). + + ICE in expand_end_loop with -O (closed: #158371). + - Fortran: + + Fix blas build failure on arm (closed: #137959). + - Java: + + Interface members are public by default (closed: #94974). + + Strange message with -fno-bounds-check in combination with -W. + (closed: #102353). + + Crash in FileWriter using IOException (closed: #116128). + + Fix ObjectInputStream.readObject() calling constructors. + (closed: #121636). + + gij: better error reporting on `class not found' (closed: #125649). + + Lockup during .java->.class compilation (closed: #141899). + + Compile breaks using temporary inner class instance (closed: #141900). + + Default constructor for inner class causes broken bytecode. + (closed: #141902). + + gij-3.2 linked against libgcc1 (closed: #165180). + + gij-wrapper understands -classpath parameter (closed: #146634). + + gij-3.2 doesn't ignore -jar when run as "java" (closed: #167673). + - ObjC: + + ICE on alpha (closed: #172353). + + * Closed reports reported against gcc-2.95 and fixed in newer versions: + - General: + + Undocumented option -pthread (closes: #165110). + + stdbool.h broken (closes: #167439). + + regparm/profiling breakage (closes: #20695). + + another gcc optimization error (closes: #51456). + + ICE in `output_fix_trunc' (closes: #55967). + + Fix "Unable to generate reloads for" (closes: #58219, #131890). + + gcc -c -MD x/y.c -o x/y.o leaves y.d in cwd (closes: #59232). + + Compiler error with -O2 (closes: #67631). + + ICE (unrecognizable insn) compiling php4 (closes: #83550, #84969). + + Another ICE (closes: #90666). + + man versus info inconsistency (-W and -Wall) (closes: #93708). + + ICE on invalid extended asm (closes: #136630). + + ICE in `emit_no_conflict_block' compiling perl (closes: #154599). + + ICE in `gen_tagged_type_instantiation_die'(closes: #166766). + + ICE on __builtin_memset(s, 0, -1) (closes: #170994). + + -Q option to gcc appears twice in the documentation (closes: #137382). + + New options for specifying targets:- -MQ and -MT (closes: #27878). + + Configure using --enable-nls (closes: #51651). + + gcc -dumpspecs undocumented (closes: #65406). + - Preprocessor: + + cpp fails to parse macros with varargs correctly(closes: #154767). + + __VA_ARGS__ stringification crashes preprocessor if __VA_ARGS__ is + empty (closes: #152709). + + gcc doesn't handle empty args in macro function if there is only + one arg(closes: #156450). + - C: + + Uncaught floating point exception causes ICE (closes: #33786). + + gcc -fpack-struct doesn't pack structs (closes: #64628). + + ICE in kernel (matroxfb) code (closes: #151196). + + gcc doesn't warn about unreachable code (closes: #158704). + + Fix docs for __builtin_return_address(closes: #165992). + + C99 symbols in limits.h not defined (closes: #168346). + + %zd printf spec generates warning, even in c9x mode (closes: #94891). + + Update GCC attribute syntax (closes: #12253, #43119). + - C++ & libstdc++-v3: + + template and virtual inheritance bug (closes: #152315). + + g++ has some troubles with nested templates (closes: #21255). + + vtable thunks implementation is broken (closes: #34876, #35477). + + ICE for templated friend (closes: #42662). + + ICE compiling mnemonic (closes: #42989). + + Deprecated: result naming doesn't work for functions defined in a + class (closes: #43170). + + volatile undefined ... (closes: #50529). + + ICE concerning templates (closes: #53698). + + Program compiled -O3 -malign-double segfaults in ofstream::~ofstream + (closes: #56867). + + __attribute__ ((constructor)) doesn't work with C++ (closes: #61806). + + Another ICE (closes: #65687). + + ICE in `const_hash' (closes: #72933). + + ICE on illegal code (closes: #83221). + + Wrong code with -O2 (closes: #83363). + + ICE on template class (closes: #85934). + + No warning for missing return in non-void member func (closes: #88260). + + Not a bug/fixed in libgcc1: libgcc.a symbols end up exported by + shared libraries (closes: #118670). + + ICE using nested templates (closes: #118781). + + Another ICE with templates (closes: #127489). + + More ICEs (closes: #140427, #141797). + + ICE when template declared after use(closes: #148603). + + template function default arguments are not handled (closes: #157292). + + Warning when including stl.h (closes: #162074). + + g++ -pedantic-errors -D_GNU_SOURCE cannot #include + (closes: #151671). + + c++ error message improvement suggestion (closes: #46181). + + Compilation error in stl_alloc.h with -fhonor-std (closes: #59005). + + libstdc++ has no method at() in stl_= (closes: #68963). + - Fortran: + + g77 crash (closes: #130415). + - ObjC: + + ICE: program cc1obj got fatal signal 11 (closes: #62309). + + Interface to garbage collector is undocumented. (closes: #68987). + - Architecture specific: + - alpha + + Can't compile with define gnu_source with stdio and curses + (closes: #97603). + + Header conflicts on alpha (closes: #134558). + + lapack-dev: cannot link on alpha (closes: #144602). + + ICE `fixup_var_refs_1' (closes: #43001). + + Mutt segv on viewing list of attachments (closes: #47981). + + ICE building open-amulet (closes: #48530). + + ICE compiling hatman (closes: #55291). + + dead code removal in switch() broken (closes: #142844). + - arm + + Miscompilation using -fPIC on arm (closes: #90363). + + infinite loop with -O on arm (closes: #151675). + - i386 + + ICE when using -mno-ieee-fp and -march=i686 (closes: #87540). + - m68k + + Optimization (-O2) broken on m68k (closes: #146006). + - mips + + g++ exception catching does not work... (closes: #105569). + + update-menus gets Bus Error (closes: #120333). + - mipsel + + aspell: triggers ICE on mipsel (closes: #128367). + - powerpc + + -O2 produces wrong code (gnuchess example) (closes: #131454). + - sparc + + Misleading documentation for -malign-{jump,loop,function}s + (closes: #114029). + + Sparc GCC issue with -mcpu=ultrasparc (closes: #172956). + + flightgear: build failure on sparc (closes: #88694). + + -- Matthias Klose Fri, 16 May 2003 07:13:57 +0200 + +gcc-3.3 (1:3.3ds8-0pre9) unstable; urgency=high + + * gcc-3.3 second prerelease. + - Fixing exception handling on s390 (urgency high). + * Reenabled gpc build (I had it disabled ...). Closes: #192347. + + -- Matthias Klose Fri, 9 May 2003 07:32:14 +0200 + +gcc-3.3 (1:3.3ds8-0pre8) unstable; urgency=low + + * gcc-3.3 prerelease. + - Fixes gcj ICE (closes: #189545). + * For libstdc++ use the i486 atomicity implementation, introduced with + 0pre6, left out in 0pre7 (closes: #191684). + * Add README.Debian for treelang (closes: #190812). + * Apply NetBSD changes (Joel Baker). Closes: #191551. + * New symbols in libgcc1, tighten the shlibs dependency. + * Disable testsuite run on mips/mipsel because of an outdated libc-dev + package. + * Do not build libffi with debug information, although configuring + with --enable-debug. + + -- Matthias Klose Tue, 6 May 2003 06:53:49 +0200 + +gcc-3.3 (1:3.3ds7-0pre7) unstable; urgency=low + + * gcc-3.3 prerelease taken from the gcc-3_3-branch (CVS 20030429). + * Revert upstream libstdc++ change (closes: #191145, #191147, #191148, + #191149, #149159, #149151, and other reports). + Sorry for not detecting this before the upload, seems to be + broken on i386 "only". + * hurd-i386: Use /usr/include, not /include. + * Disable gpc on hurd-i386 (closes: #189851). + * Disable building the debug version of libstdc++ on powerpc-linux + (fixes about 200 java test cases). + * Install libstdc++v3 man pages (closes: #127263). + + -- Matthias Klose Tue, 29 Apr 2003 23:28:44 +0200 + +gcc-3.3 (1:3.3ds6-0pre6) unstable; urgency=high + + * gcc-3.3 prerelease taken from the gcc-3_3-branch (CVS 20030426). + * libstdc++-doc: Fix index.html link (closes: #189424). + * Revert back to the i486 atomicity implementation, that was used + for gcc-3.2 as well. Reopens: #184446, #185662. Closes: #189983. + For this reason, tighten the libstdc++5 shlibs dependency. See + http://lists.debian.org/debian-devel/2003/debian-devel-200304/msg01895.html + Don't build the ix86 specfic libstdc++ libs anymore. + + -- Matthias Klose Sun, 27 Apr 2003 19:47:54 +0200 + +gcc-3.3 (1:3.3ds5-0pre5) unstable; urgency=low + + * gcc-3.3 prerelease taken from the gcc-3_3-branch (CVS 20030415). + * Disable treelang on powerpc. + * Disable gpc on m68k. + * Install locale data. Conflict with gcc-3.2 (<= 1:3.2.3-0pre8). + * Fix generated bits/atomicity.h (closes: #189183). + * Tighten libgcc1 shlibs dependency (new symbol _Unwind_Backtrace). + + -- Matthias Klose Wed, 16 Apr 2003 00:37:05 +0200 + +gcc-3.3 (1:3.3ds4-0pre4) unstable; urgency=low + + * gcc-3.3 prerelease taken from the gcc-3_3-branch (CVS 20030412). + * Avoid sparc64 dependencies for libgcc1 on sparc (Clint Adams). + * Make the default sparc 32bit target v8 instead of v7. This mainly + enables hardmul, which should speed up v8 and v9 systems by a large + margin (Ben Collins). + * Tighten binutils dependency for sparc. + * On i386, build libstdc++ optimized for i486 and above. The library + in /usr/lib is built for i386. Closes: #184446, #185662. + * Add gpc build (from gcc-snapshot package). + * debian/control: Include all packages, that _can_ be built from + this source package (except the cross packages). + * Add m68k patches: m68k-const, m68k-subreg, m68k-loop. + * Run the 3.3 testsuite a second time with the installed gcc-3.2 + to check for regressions (promised, only this time, and for the + final release ;). Add build dependencies (gobjc-3.2, g77-3.2, g++-3.2). + + -- Matthias Klose Sat, 12 Apr 2003 10:11:11 +0200 + +gcc-3.3 (1:3.3ds3-0pre3) unstable; urgency=low + + * gcc-3.3 prerelease taken from the gcc-3_3-branch (CVS 20030331). + * Reenable java on arm. + * Build-Depend on binutils-2.13.90.0.18-1.3 on m68k. Fixes all + bprob/gcov testsuite failures. + * Enable C++ build on arm. + * Enable the sparc64 build. + + -- Matthias Klose Mon, 31 Mar 2003 23:24:54 +0200 + +gcc-3.3 (1:3.3ds2-0pre2) unstable; urgency=low + + * gcc-3.3 prerelease taken from the gcc-3_3-branch (CVS 20030317). + * Disable building the gcc-3.3-nof package. + * Disable Ada on mips and mipsel. + * Remove the workaround to build Ada on powerpc. + * Add GNU Free documentation license to copyright file. + * Update the sparc64 build patches (Clint Adams). Not yet enabled. + * Disable C++ on arm (Not yet tested). + * Add fix for ICE on powerpc (see: #184684). + + -- Matthias Klose Sun, 16 Mar 2003 21:40:57 +0100 + +gcc-3.3 (1:3.3ds1-0pre1) unstable; urgency=low + + * gcc-3.3 prerelease taken from the gcc-3_3-branch (CVS 20030310). + * Add gccbug manpage. + * Don't build libgnat package (no shared library). + * Configure with --enable-sjlj-exceptions on hppa and m68k for + binary compatibility with libstdc++ built with gcc-3.2. + * Disable Java on arm-linux (never seen it sucessfully bootstrap). + * Install non-conflicting baseline README. + * multilib *.so and *.a moved to /usr/lib/gcc-lib/... , so that several + compiler versions can be installed concurrently. + * Remove libstdc++-incdir patch applied upstream. + * libstdc++ 64 bit development files now handled in -dev target. + (Gerhard Tonn) + * Drop build dependencies for gpc (tetex-bin, help2man, libncurses5-dev). + * Add libstdc++5-3.3-dev confict to libstdc++5-dev (<= 1:3.2.3-0pre3). + * Enable builds on m68k (all but C++ for the moment). gcc-3.3 bootstraps, + while gcc-3.2 doesn't. + + -- Matthias Klose Mon, 10 Mar 2003 23:41:00 +0100 + +gcc-3.3 (1:3.3ds0-0pre0) unstable; urgency=low + + * First gcc-3.3 package, built for s390 only. All other architectures + build the gcc-3.3-base package only. + To build the package on other architectures, edit debian/rules.defs + (macro no_dummy_archs). + * gcc-3.3 prerelease taken from the gcc-3_3-branch (CVS 20030301). + * Don't include the gcc locale files (would conflict with 3.2). + * Remove libffi-install-fix patch. + * Fix netbsd-i386 patches. + * Change priority of libstdc++5 and gcc-3.2-base to important. + * Install gcjh-wrapper for javah. + * gij suggests fastjar, gcj recommends fastjar. + * Allow builds using automake1.4 | automake (<< 1.5). + * Backport fix for to output more correct line numbers. + * Add help2man to build dependencies needed for some gpc man pages. + * gpc: Install binobj and gpidump binaries and man pages. + * Apply cross compilation patches submitted by Bastian Blank. + * Replace s390-biarch patch and copy s390-config-ml patch from 3.2 + (Gerhard Tonn). + * Configure using --enable-debug. + * Add infrastructure to only build a subset of binary packages. + * Rename libstdc++-{dev,dbg,pic,doc} packages. + * Build treelang compiler. + + -- Matthias Klose Sat, 1 Mar 2003 12:56:42 +0100 + +gcc-3.2 (1:3.2.3ds2-0pre3) unstable; urgency=low + + * gcc-3.2.3 prerelease (CVS 20030228) + - Fixes bootstrap failure on alpha-linux. + - Fixes ICE on m68k (closes: #177016). + * Build Pascal with -O1 on powerpc, disable Pascal on arm, m68k and + sparc (due to wrong code generation for fwrite in glibc, + see PR optimization/9279). + * Apply cross compilation patches submitted by Bastian Blank. + + -- Matthias Klose Fri, 28 Feb 2003 20:26:30 +0100 + +gcc-3.2 (1:3.2.3ds1-0pre2) unstable; urgency=medium + + * gcc-3.2.3 prerelease (CVS 20030221) + - Fixes ICE on hppa (closes: #181813). + * Patch for ffitest in s390-java.dpatch deleted, since already fixed + upstream. (Gerhard Tonn) + * Build crtbeginT.o on m68k-linux (closes: #179807). + * Install gcjh-wrapper for javah (closes: #180218). + * gij suggests fastjar, gcj recommends fastjar (closes: #179298). + * Allow builds using automake1.4 | automake (<< 1.5) (closes: #180048). + * Backport fix for to output more correct line numbers (closes: #153965). + * Add help2man to build dependencies needed for some gpc man pages. + * gpc: Install binobj and gpidump binaries and man pages. + * Disable gpc on arm due to wrong code generation for fwrite in + glibc (see PR optimization/9279). + + -- Matthias Klose Sat, 22 Feb 2003 19:58:20 +0100 + +gcc-3.2 (1:3.2.3ds0-0pre1) unstable; urgency=low + + * gcc-3.2.3 prerelease (CVS 20030210) + - Fixes long millicode calls on hppa (closes: #180520) + * New gpc-20030209 version. Remove gpc-update.dpatch and gpc-testsuite.dptch + as they are no longer needed. + * Fix netbsd-i386 patches (closes: #180129, #179931) + * m68k-bootstrap.dpatch: backport gcse.c changes from 3.3/MAIN to 3.2 + * Change priority of libstdc++5 and gcc-3.2-base to important. + + -- Ryan Murray Tue, 11 Feb 2003 06:18:09 -0700 + +gcc-3.2 (1:3.2.2ds8-1) unstable; urgency=low + + * gcc-3.2.2 release. + - Fixes ICE, regression from 2.95 (closes: #176117). + - Fixes ICE, regression from 2.95 (closes: #179161). + * libstdc++ for biarch installs now upstream to usr/lib64, + therefore mv usr/lib/64 usr/lib64 no longer necessary. (Gerhard Tonn) + + -- Ryan Murray Wed, 5 Feb 2003 01:35:29 -0700 + +gcc-3.2 (1:3.2.2ds7-0pre8) unstable; urgency=low + + * gcc-3.2.2 prerelease (CVS 20030130). + * update s390 libffi patch + * debian/control: add myself to uploaders and change libc12-dev depends to + libc-dev on i386 (closes: #179128) + * Build-Depend on procps so that ps is available for logwatch + + -- Ryan Murray Fri, 31 Jan 2003 04:00:15 -0700 + +gcc-3.2 (1:3.2.2ds6-0pre7) unstable; urgency=low + + * gcc-3.2.2 prerelease (CVS 20030128). + - Update needed for hppa. + - Fixes ICE on arm, regression from 2.95.x (closes: #168086). + - Can use default bison (1.875). + * Apply netbsd build patches (closes: #177674, #178328, #178325, + #178326, #178327). + * Run the logwatch script on "slow" architectures (arm, m68k) only. + * autoreconf.dpatch: Only update libtool.m4, which is newer conceptually + than libtool 1.4 (Ryan Murray). + * Apply autoreconf patch universally (Ryan Murray). + * More robust gij/gcj wrapper scripts, include /usr/lib/jni in default + JNI search path (Ben Burton). Closes: #167932. + * Build crtbeginT.o on m68k (closes: #177036). + * Fixed libc-dev source dependency (closes: #178602). + * Tighten shlib dependency to the current package version; should be + 1:3.2.2-1 for the final release (closes: #178867). + + -- Matthias Klose Tue, 28 Jan 2003 21:59:30 +0100 + +gcc-3.2 (1:3.2.2ds5-0pre6) unstable; urgency=low + + * gcc-3.2 snapshot taken from the gcc-3_2-branch (CVS 20030123). + * Build locales needed by the libstdc++ testsuite. + * Update config.{guess,sub} files from autotools-dev (closes: #177674). + * Disable Ada and Java on netbsd-i386 (closes: #177679). + * gnat: Add suggests for gnat-doc and ada-reference-manual. + + -- Matthias Klose Thu, 23 Jan 2003 22:16:53 +0100 + +gcc-3.2 (1:3.2.2ds4-0pre5.1) unstable; urgency=low + + * Readd build dependency `locales' on arm. locales is now installable + * Add autoreconf patch for mips{,el}. (closes: #176311) + + -- Ryan Murray Wed, 22 Jan 2003 14:31:14 -0800 + +gcc-3.2 (1:3.2.2ds4-0pre5) unstable; urgency=low + + * Remove build dependency `libc6-dev-sparc64 [sparc]' for now. + * Remove build dependency `locales' on arm. locales is uninstallable + on arm due to the missing glibc-2.3. + * Use bison-1.35. bison-1.875 causes an hard error on the reduce/reduce + conflict in objc-parse.y. + + -- Matthias Klose Fri, 10 Jan 2003 10:10:43 +0100 + +gcc-3.2 (1:3.2.2ds4-0pre4) unstable; urgency=low + + * Try building with gcc-2.95 on m68k-linux. Building gcc-3.2 with gcc-3.2 + does not work for me. m68k-linux doesn't look good at all ... + * Fix s390 build error. + * Add locales to build dependencies. A still unsolved issue is the + presence of the locales de_DE, en_PH, en_US, es_MX, fr_FR and it_IT, + or else some tests in the libstdc++ testsuite will fail. + * Put all -nof files in the -nof package (closes: #175253). + * Correctly exit logwatch script (closes: #175251). + * Install linker-map.gnu file for libstdc++_pic (closes: #175144). + * Install versioned gpcs docs only (closes: #173844). + * Include gpc test results in gpc package. + * Link local libstdc++ documentation to local source-level documentation. + * Clarify libstdc++ description (so version and library version). + Closes: #175799. + * Include library in libstdc++-dbg package (closes: #176005). + + -- Matthias Klose Wed, 8 Jan 2003 23:39:50 +0100 + +gcc-3.2 (1:3.2.2ds3-0pre3) unstable; urgency=low + + * gcc-3.2 snapshot taken from the gcc-3_2-branch (CVS 20021231). + - Fix loop count computation for preconditioned unrolled loops. + Closes: #162919. + - Fix xmmintrin.h (_MM_TRANSPOSE4_PS) CVS 20021027 (closes: #163647). + - Fix [PR 8601] strlen/template interaction causes ICE CVS 20021201. + Closes: #166143. + * Watch the log files, which are written during the testsuite runs and print + out a message, if there is still activity. No more buildd timeouts on arm + and m68k ... + * Remove gpc's reference to librx1g-dev package (closes: #172953). + * Remove trailing dots on package descriptions. + * Fix external reference to cpp.info in gcc.info (closes: #174598). + + -- Matthias Klose Tue, 31 Dec 2002 13:47:52 +0100 + +gcc-3.2 (1:3.2.2ds2-0pre2) unstable; urgency=medium + + * Friday, 13th upload, so what do you expect ... + * gcc-3.2 snapshot taken from the gcc-3_2-branch (CVS 20021212). + * Fix gnat build (autobuild maintainers: please revert back to gnat-3.2 + (<= 1:3.2.1ds6-1) for building gnat-3.2, if the build fails building + gnatlib and gnattools). + * Really disable sparc64 support. + + -- Matthias Klose Fri, 13 Dec 2002 00:26:37 +0100 + +gcc-3.2 (1:3.2.2ds1-0pre1) unstable; urgency=low + + * A candidate for the transition ... + * gcc-3.2 snapshot taken from the gcc-3_2-branch (CVS 20021210). + - doc/invoke.texi: Remove last reference to -a (closes: #171748). + * Disable sparc64 support. For now please use egcs64 to build sparc64 + kernels. + * Disable Pascal on the sparc architecture (doesn't bootstrap). + + -- Matthias Klose Tue, 10 Dec 2002 22:33:13 +0100 + +gcc-3.2 (1:3.2.2ds0-0pre0) unstable; urgency=low + + * gcc-3.2 snapshot taken from the gcc-3_2-branch (CVS 20021202). + - Should fix _Pragma expansion within macros (closes: #157416). + * New gpc-20021128 version. Run check using EXTRA_TEST_PFLAGS=-g0 + * Add tetex-bin to build dependencies (gpc needs it). Closes: #171203. + + -- Matthias Klose Tue, 3 Dec 2002 08:22:33 +0100 + +gcc-3.2 (1:3.2.1ds6-1) unstable; urgency=low + + * gcc-3.2.1 final release. + * Build gpc-20021111 for all architectures. hppa and i386 are + known to work. For the other architectures, send the usual FTBFS ... + WARNING: this gpc version is an alpha version, especially debug info + doesn't work well, so use -g0 for compiling. If you need a stable + gpc compiler, use gpc-2.95. + * Encode the gpc upstream version in the package name, the gpc release + date in the version number (requested by gpc upstream). + * Added libncurses5-dev and libgmp3-dev as build dependencies for the + gpc tests and runtime. + * Clean CVS files as well (closes: #169101). + * s390-biarch.dpatch added, backported from CVS (Gerhard Tonn). + * s390-config-ml.dpatch added, disables biarch for java, + libffi and boehm-gc on s390. They need a 64 bit runtime + during build which is not yet available on s390 (Gerhard Tonn). + * Biarch support for packaging adapted (Gerhard Tonn). + biarch variable added and with-sparc64 variable substituted in + most places by biarch. + dh_shlibdeps is applied only to 32 bit libraries on s390, since + ldd for 64 bit libraries don't work on 32 bit runtime. + Build dependency to libc6-dev-s390x added. + + -- Matthias Klose Wed, 20 Nov 2002 00:20:58 +0100 + +gcc-3.2 (1:3.2.1ds5-0pre6) unstable; urgency=medium + + * gcc-3.2.1 prerelease. + * Removed arm patch integrated upstream. + * Adjust gnat build dependency (closes: #167116). + * Always configure with --enable-clocale=gnu. The autobuilders do have + locales installed, but not generated the "de_DE" locale needed for + the autoconf test in libstdcc++-v3/aclocal.m4. + * libstdc++ documentaion: Don't compresss '*.txt' referenced by html pages. + + -- Matthias Klose Tue, 12 Nov 2002 07:19:44 +0100 + +gcc-3.2 (1:3.2.1ds4-0pre5) unstable; urgency=medium + + * gcc-3.2.1 snapshot (CVS 20021103). + * sparc64-build.dpatch: Updated. Lets sparc boostrap again. + * s390-loop.dpatch removed, already fixed upstream (Gerhard Tonn). + * bison.dpatch: Removed, patch submitted upstream. + * backport-java-6865.dpatch: Apply again during build. + * Tighten glibc dependency (closes: #166703). + + -- Matthias Klose Sun, 3 Nov 2002 12:22:02 +0100 + +gcc-3.2 (1:3.2.1ds3-0pre4) unstable; urgency=high + + * gcc-3.2.1 snapshot (CVS 20021020). + - Expansion of _Pragma within macros fixed (closes: #157416). + * FTBFS: With the switch to bison-1.50 (and 1.75), gcc-3.2 fails to build from + source on Debian unstable systems. This is fixed in gcc HEAD, but not on + the current release branch. + HELP NEEDED: + - check what is missing from the patches in debian/patches/bison.dpatch. + This is a backport of the bison related patches, but showing regressions + in the gcc testsuite, so it cannot be applied. + - build gcc using byacc (bootstrap currently fails using byacc). + - build bison-1.35 in it's own package (the current 1.35-3 package fails + to build form source). + - and finally ask upstream to backport the patch to the branch. It's not + helpful not beeing able to follow the stable branch. Maybe we should + just switch to gcc HEAD as BSD does ... + As a terrible workaround, build the sources from CVS first on a machine, + with bison-1.35 installed, then package the tarball, so the bison + generated files are not rebuilt. + + * re-add lost patch: configure with --enable-__cxa_atexit (closes: #163422), + Therefore urgency high. + * gcj-wrapper, gij-wrapper: Accept names starting with `.' (closes: #163172, + #164009). + * Point g++ manpage to correct g++ version (closes: #162843). + * Support for i386-freebsd-gnu (closes: #163883). + * s390-java.dpatch replaced with backport from cvs head (Gerhard Tonn). + * Disable the testsuite run on the Hurd (closes: #159650). + * s390-loop.dpatch added, fixes runtime problem (Gerhard Tonn). + * debian/patches/bison.dpatch: Backport for bison-1.75 compatibility. + Don't use it due to regressions. + * debian/patches/backport-java-6865.dpatch: Directly applied in the + included tarball because of bison problems. + * Make fixincludes priority optional, so linda can depend on it. + * Tighten binutils dependency. + + -- Matthias Klose Sun, 20 Oct 2002 10:52:49 +0200 + +gcc-3.2 (1:3.2.1ds2-0pre3) unstable; urgency=low + + * gcc-3.2.1 snapshot (CVS 20020923). + * Run the libstdc++ check-abi script. Results are put into the file + /usr/share/doc/libstdc++5/README.libstdc++-baseline in the libstdc++5-dev + package. This file contains a new baseline, if no baseline for this + architecture is included in the gcc sources. + * gcj-wrapper: Accept files starting with an underscore, accept + path names (closes: #160859, #161517). + * Explicitely call automake-1.4 when rebuilding Makefiles (closes: #161438). + * Let installed fixincludes script find files in /usr/lib/fixincludes. + * debian/rules.patch: Add .NOTPARALLEL as target, so that patches are + applied sequentially (closes: #159395). + + -- Matthias Klose Tue, 24 Sep 2002 07:36:56 +0200 + +gcc-3.2 (1:3.2.1ds1-0pre2) unstable; urgency=low + + * gcc-3.2.1 snapshot (CVS 20020913). Welcome back m68k in bootstrap land! + * Fix arm-tune.dpatch (closes: #159354). + * Don't overwrite LD_LIBRARY_PATH in build (closes: #158459). + * --disable-__cxa_atexit on NetBSD (closes: #159620). + * Reenable installation of message catalogs (disabled in 3.2-0pre2). + Closes: #160175. + * Ben Collins + - Re-enable sparc64 build. This time, it's part of the default compiler. + I have disabled 64/alt libraries as they are too much overhead. All + libraries build 64bit, but currently only libgcc/libstdc++ include the + 64bit libraries. + Closes: #160404. + * Depend on autoconf2.13, instead of autoconf. + * Phil Blundell + - debian/patches/arm-update.dpatch: Fix python2.2 build failure. + + -- Matthias Klose Sat, 7 Sep 2002 08:05:02 +0200 + +gcc-3.2 (1:3.2.1ds0-0pre1) unstable; urgency=medium + + * gcc-3.2.1 snapshot (CVS 20020829). + New g++ option -Wabi: + Warn when G++ generates code that is probably not compatible with the + vendor-neutral C++ ABI. Although an effort has been made to warn about + all such cases, there are probably some cases that are not warned about, + even though G++ is generating incompatible code. There may also be + cases where warnings are emitted even though the code that is generated + will be compatible. + The current version of the ABI is 102, defined by the __GXX_ABI_VERSION + macro. + * debian/NEWS.*: Updated. + * Fix libstdc++-dev dependency on libc-dev for the Hurd (closes: #157004). + * Add versioned expect build dependency. + * Tighten binutils dependency to 2.13.90.0.4. + * debian/patches/arm-tune.dpatch: Increase stack limit for configure. + * 3.2-0pre4 did build gnat-3.2 compilers for all architectures. Build-Depend + on gnat-3.2 now (closes: #156734). + * Remove bashism's in gcj-wrapper (closes: #157982). + * Add -cp and -classpath options to gij(1). Backport from HEAD (#146634). + * Add fastjar documentation. + + -- Matthias Klose Fri, 30 Aug 2002 10:35:00 +0200 + +gcc-3.2 (1:3.2ds0-0pre4) unstable; urgency=low + + * Correct build dependency on gnat-3.1. + + -- Matthias Klose Mon, 12 Aug 2002 01:21:58 +0200 + +gcc-3.2 (1:3.2ds0-0pre3) unstable; urgency=low + + * gcc-3.2 upstream prerelease. + * Disable all configure options, which are standard: + --enable-threads=posix --enable-long-long, --enable-clocale=gnu + + -- Matthias Klose Fri, 9 Aug 2002 21:59:08 +0200 + +gcc-3.2 (1:3.2ds0-0pre2) unstable; urgency=low + + * gcc-3.2 snapshot (CVS 20020802). + * Fix g++-include dir. + * Don't install the locale files (temporarily, until we don't build + gcc-3.1 anymore). + * New package libgcj-common to avoid conflict with classpath package. + + -- Matthias Klose Sat, 3 Aug 2002 09:08:34 +0200 + +gcc-3.2 (1:3.2ds0-0pre1) unstable; urgency=low + + * gcc-3.2 snapshot (CVS 20020729). + + -- Matthias Klose Mon, 29 Jul 2002 20:36:54 +0200 + +gcc-3.1 (1:3.1.1ds3-1) unstable; urgency=low + + * gcc-3.1.1 release. Following this release we will have a gcc-3.2 + release soon, which is gcc-3.1.1 plus some C++ ABI changes. Once + gcc-3.2 hits the archives, gcc-3.1.1 will go away. + * Don't build the sparc64 compiler. The packaging/patches are + currently broken. + * Add missing headers on m68k and powerpc. + * Install libgcc_s_nof on powerpc. + * Install libffi's copyright and doc files (closes: #152198). + * Remove dangling symlink (closes: #149002). + * libgcj3: Add a conflict to the classpath package (closes: #148664). + * README.C++: Fix URLs. + * libstdc++-dbg: Install into /usr/lib/debug, document it. + * backport-java-6865.dpatch: backport from HEAD. + * Fix typo in gcj docs (closes: #148890). + * Change libstdc++ include dir: /usr/include/c++/3.1. + * libstdc++-codecvt.dpatch: New patch (closes: #149776). + * Build libstdc++-pic package. + * Move 64bit libgcc in its own package libgcc1-64 (closes: #147249). + * Tighten glibc dependency. + + -- Matthias Klose Mon, 29 Jul 2002 00:34:49 +0200 + +gcc-3.1 (1:3.1.1ds2-0pre3) unstable; urgency=low + + * Updated to CVS 2002-06-06 (gcc-3_1-branch). + * Updated s390-java patch (Gerhard Tonn). + * Don't use -O in STAGE1_FLAGS on m68k. + * Fix `-classpath' option in gcj-wrapper script (closes: #150142). + * Remove g++-cxa-atexit patch, use --enable-__cxa_atexit configure option. + + -- Matthias Klose Wed, 3 Jul 2002 23:52:58 +0200 + +gcc-3.1 (1:3.1.1ds1-0pre2) unstable; urgency=low + + * Updated to CVS 2002-06-06 (gcc-3_1-branch), fixing an ObjC regression. + * Welcome m68k to bootstrap land (thanks to Andreas Schwab). + * Add javac wrapper for gcj-3.1 (Michael Koch). + * Remove dangling symlink in /usr/share/doc/gcc-3.1 (closes: #149002). + + -- Matthias Klose Fri, 7 Jun 2002 00:26:05 +0200 + +gcc-3.1 (1:3.1.1ds0-0pre1) unstable; urgency=low + + * Updated to CVS 2002-05-31 (gcc-3_1-branch). + * Change priorities from fastjar and gij-wrapper-3.1 from 30 to 31. + * Update arm-tune patch. + * Install xmmintrin.h header on i386 (closes: #148181). + * Install altivec.h header on powerpc. + * Call correct gij in gij-wrapper (closes: #148662, #148682). + + -- Matthias Klose Wed, 29 May 2002 22:47:40 +0200 + +gcc-3.1 (1:3.1ds2-2) unstable; urgency=low + + * Tighten binutils dependency. + * Fix libstdc include dir for multilibs (Dan Jacobowitz). + + -- Matthias Klose Tue, 21 May 2002 08:03:49 +0200 + +gcc-3.1 (1:3.1ds2-1) unstable; urgency=low + + * GCC 3.1 release. + * Ada cannot be built by the autobuilders for the first time. Do it by hand. + gnatgcc and gnatbind need to be in the PATH. + * Build with CC=gnatgcc, when building the Ada compiler. + * Hurd fixes. + * Don't build the sparc64 compiler; the hack isn't up to date and glibc + isn't converted to use /lib64 and /usr/lib64. + * m68k-linux shows bootstrap comparision failures. If you want to build + the compiler anyway and ignore the bootstrap comparision failure, edit + debian/rules.patch and uncomment the patch to ignore the failure. See + /usr/share/doc/gcc-3.1/BOOTSTRAP_COMPARISION_FAILURE for the differences. + + -- Matthias Klose Wed, 15 May 2002 09:53:00 +0200 + +gcc-3.1 (1:3.1ds1-0pre6) unstable; urgency=low + + * Build from the "final prerelease" tarball (gcc-3.1-20020508.tar.gz). + * Build gnat-3.1-doc package. + * Build fastjar package without building java packages. + * Hurd fixes. + * Updated sparc64-build patch. + * Add s390-ada patch (Gerhard Tonn). + * Undo the dwarf2 support for hppa from -0pre5. + + -- Matthias Klose Thu, 9 May 2002 17:21:09 +0200 + +gcc-3.1 (1:3.1ds0-0pre5) unstable; urgency=low + + * Use /usr/include/g++-v3-3.1 as C++ include dir. + * Update s390-java patch (Gerhard Tonn). + * Tighten binutils dependency (gas patch for m68k-linux). + * Use gnat-3.1 as the gnat package name (as found in gcc/ada/gnatvsn.ads). + * dwarf2 support hppa: a snapshot of the gcc/config/pa directory + from the trunk dated 2002-05-02. + + -- Matthias Klose Fri, 3 May 2002 22:51:37 +0200 + +gcc-3.1 (1:3.1ds0-0pre4) unstable; urgency=low + + * Use gnat-5.00w as the gnat package name (as found in gcc/ada/gnatvsn.ads). + * Don't build the shared libgnat library. It assumes an existing shared + libiberty library. + * Don't install the libgcjgc library. + + -- Matthias Klose Thu, 25 Apr 2002 08:48:04 +0200 + +gcc-3.1 (1:3.1ds0-0pre3) unstable; urgency=low + + * Build fastjar on all architectures. + * Update m68k patches. + * Update s390-java patch (Gerhard Tonn). + + -- Matthias Klose Sun, 14 Apr 2002 15:34:47 +0200 + +gcc-3.1 (1:3.1ds0-0pre2) unstable; urgency=low + + * Add Ada support. To successfully build, a working gnatbind and gcc + driver with Ada support is needed. + * Apply needed arm patches from 3.0.4. + + -- Matthias Klose Sat, 6 Apr 2002 13:17:08 +0200 + +gcc-3.1 (1:3.1ds0-0pre1) unstable; urgency=low + + * First try for gcc-3.1. + + -- Matthias Klose Mon, 1 Apr 2002 23:39:30 +0200 + +gcc-3.0 (1:3.0.4ds3-6) unstable; urgency=medium + + * Second try at fixing sparc build problems. + + -- Phil Blundell Sun, 24 Mar 2002 14:49:26 +0000 + +gcc-3.0 (1:3.0.4ds3-5) unstable; urgency=medium + + * Enable java on ARM. + * Create missing directory to fix sparc build. + + -- Phil Blundell Fri, 22 Mar 2002 20:21:59 +0000 + +gcc-3.0 (1:3.0.4ds3-4) unstable; urgency=low + + * Link with system zlib (closes: #136359). + + -- Matthias Klose Tue, 12 Mar 2002 20:47:59 +0100 + +gcc-3.0 (1:3.0.4ds3-3) unstable; urgency=low + + * Build libf2c (pic and non-pic) with -mieee on alpha-linux. + + -- Matthias Klose Sun, 10 Mar 2002 00:37:24 +0100 + +gcc-3.0 (1:3.0.4ds3-2) unstable; urgency=medium + + * Apply hppa-build patch (Randolph Chung). Closes: #136731. + * Make libgcc1 conflict/replace with libgcc1-sparc64. Closes: #135709. + * gij-3.0 provides the `java' command. Closes: #128947. + * Depend on binutils (>= 2.11.93.0.2-2), allows stripping of libgcj.a + again. Closes: #99307. + * Update README.cross pointing to the README of the toolchain-source + package. + + -- Matthias Klose Wed, 6 Mar 2002 21:53:34 +0100 + +gcc-3.0 (1:3.0.4ds3-1) unstable; urgency=low + + * Final gcc-3.0.4 release. + * debian/rules.d/binary-java.mk: Fix dormant typo, exposed by removing the + duplicate libgcj dependency and adding the gij-3.0 package. + Closes: #134005. + * New patch by Phil Blundell to fix scalapack build error on m68k. + + -- Matthias Klose Wed, 20 Feb 2002 23:59:43 +0100 + +gcc-3.0 (1:3.0.4ds2-0pre020210) unstable; urgency=low + + * Make the base package dependent on the binary-arch target. Closes: #133433. + * Get libstdc++ on arm woring (define _GNU_SOURCE). Closes: #133435. + + -- Matthias Klose Mon, 11 Feb 2002 20:31:12 +0100 + +gcc-3.0 (1:3.0.4ds2-0pre020209) unstable; urgency=high + + * Update to CVS sources (20020209 gcc-3_0-branch). + * Apply patch to fix bootstrap error on arm-linux (submitted upstream + by Phil Blundell). Closes: #130422. + * Make base package architecture any. + * Decouple versioned shlib dependencies from release number for + libobjc as well. + + -- Matthias Klose Sat, 9 Feb 2002 01:30:11 +0100 + +gcc-3.0 (1:3.0.4ds1-0pre020203) unstable; urgency=medium + + * One release critical bug outstanding: + - bootstrap error on arm. + * Update to CVS sources (20020203 gcc-3_0-branch). + * Fixed upstream: PR c/3504: Correct documentation of __alignof__. + Closes: #85445. + * Remove libgcc-powerpc patch, integrated upstream (closes: #131977). + * Tighten binutils build dependency (to address #126162). + * Move jv-convert to gcj package (closes: #131985). + + -- Matthias Klose Sun, 3 Feb 2002 14:47:14 +0100 + +gcc-3.0 (1:3.0.4ds0-0pre020127) unstable; urgency=low + + * Two release critical bugs outstanding: + - bootstrap error on arm. + - bus errors for C++ and java executables on sparc (see the testsuite + results). + * Update to CVS sources (20020125 gcc-3_0-branch). + * Enable java support for s390 architecture (patch from Gerhard Tonn). + * Updated NEWS file for 3.0.3. + * Disable building the gcc-sparc64, but build a multilibbed compiler + for sparc as the default. + * Disabled the subreg-byte patch for sparc (request from Ben Collins). + * Fixed reference to libgcc1 package in README (closes: #126218). + * Do recommend libc-dev, not depend on it. For low-end or embedded systems + the dependency on libc-dev can make the difference between + having enough or having too little space to build a kernel. + * README.cross: Updated by Hakan Ardo. + * Decouple versioned shlib dependencies from release number. Closes: #118391. + * Fix diversions for gcc-3.0-sparc64 package (closes: #128178), + unconditionally remove `sparc64-linux-gcc' alternative. + * g77/README.libg2c.Debian: New file mentioning `libg2c-pic'. The next + g77 version (3.1) does build a static and shared library (closes: #104250). + * Fix formatting errors in the synopsis of the java man pages. Maybe the + reason for #127571. Closes: #127571. + * fastjar: Fail for the (currently incorrect) -u option. Addresses: #116145. + Add alternative for `jar' using priority 30 (closes: #118648). + * jv-convert: Add --help option and man page. Backport from HEAD branch. + * libgcj2-dev: Remove duplicate dependency (closes: #127805). + * Giving up and make just another new package gij-X.Y with only the gij-X.Y + binary for policy conformance (closes: #127111). + * gij: Provides an alternative for `java' (priority 30) using a wrapper + script (Stephen Zander) (closes: #128974). Added simple manpage. + + -- Matthias Klose Sun, 27 Jan 2002 13:33:41 +0100 + +gcc-3.0 (1:3.0.3ds3-1) unstable; urgency=low + + * Final gcc-3.0.3 release. + * Do not compress .txt files in libstdc++ docs referenced from html + pages (closes: #124136). + * libstdc++-dev suggests libstdc++-doc. + * debian/patches/gcc-ia64-NaT.dpatch: Update (closes: #123685). + + -- Matthias Klose Fri, 21 Dec 2001 02:54:11 +0100 + +gcc-3.0 (1:3.0.3ds2-0pre011215) unstable; urgency=low + + * Update to CVS sources (011215). + * libstdc++ documentation updated upstream (closes: #123790). + * debian/patches/gcc-ia64-NaT.dpatch: Disable. Fixes bootstrap error + on ia64 (#123685). + + -- Matthias Klose Sat, 15 Dec 2001 14:43:21 +0100 + +gcc-3.0 (1:3.0.3ds1-0pre011210) unstable; urgency=medium + + * Update to CVS sources (011208). + * Supposed to fix powerpc build error (closes: #123155). + + -- Matthias Klose Thu, 13 Dec 2001 07:26:05 +0100 + +gcc-3.0 (1:3.0.3ds0-0pre011209) unstable; urgency=medium + + * Update to CVS sources (011208). Frozen for upstream 3.0.3 release. + * Apply contrib/PR3145.patch, a backport of Nathan Sidwell's patch to + fix PR c++/3145, the infamous "virtual inheritance" bug. This affected + especially KDE2 (eg. artsd). Franz Sirl + * cc1plus segfault in strength reduction fixed upstream. Closes: #122547. + * debian/patches/gcc-ia64-NaT.dpatch: Add patch to avoid a bug that can + cause miscompiled userapps to crash the kernel. Closes: #121924. + * Reenable shared libgcc for powerpc. Fixed upstream. + http://gcc.gnu.org/ml/gcc-patches/2001-11/msg00340.html + debian/patches/libgcc-powerpc.dpatch: New patch. + * Add upstream changelogs. + * Remove gij alternative. Move to gij package. + + -- Matthias Klose Sun, 9 Dec 2001 09:36:48 +0100 + +gcc-3.0 (1:3.0.2ds4-4) unstable; urgency=medium + + * Disable building of libffi on mips and mipsel. + (closes: #117503). + * Enable building of shared libgcc on s390 + (closes: #120452). + + -- Christopher C. Chimelis Sat, 1 Dec 2001 06:15:29 -0500 + +gcc-3.0 (1:3.0.2ds4-3) unstable; urgency=medium + + * Fix logic to build libffi without java (closes: #117503). + + -- Matthias Klose Sun, 4 Nov 2001 14:34:50 +0100 + +gcc-3.0 (1:3.0.2ds4-2) unstable; urgency=medium + + * Enable java for ia64 (Jeff Licquia). Closes: #116798. + * Allow building of libffi without gcj (Jeff Licquia). + New libffi packages for arm hurd-i386 mips mipsel, + still missing: hppa, s390. + * debian/NEWS.gcc: Add 3.0.2 release notes. + * debian/patches/hppa-align.dpatch: New patch from Alan Modra, + submitted by Randolph Tausq. + + -- Matthias Klose Thu, 25 Oct 2001 23:59:31 +0200 + +gcc-3.0 (1:3.0.2ds4-1) unstable; urgency=medium + + * Final gcc-3.0.2 release. The source tarball is not the released + tarball, but taken from CVS 011024). + * Remove patch for s390, included upstream. + + -- Matthias Klose Wed, 24 Oct 2001 00:49:40 +0200 + +gcc-3.0 (1:3.0.2ds3-0pre011014) unstable; urgency=low + + * Update to CVS sources (011014). Frozen for upstream 3.0.2 release. + Closes: #109351, #114099, #114216, #105741 (allegro3938). + * Added debian/patches/fastjar.dpatch, which makes fastjar extract + filenames correctly (previously, some had incorrect names on extract). + Closes: #113236. + * Priorities fixed in the past (closes: #94404). + + -- Matthias Klose Sun, 14 Oct 2001 13:19:43 +0200 + +gcc-3.0 (1:3.0.2ds2-0pre010923) unstable; urgency=low + + * Bootstraps on powerpc again (closes: #112777). + + -- Matthias Klose Sun, 23 Sep 2001 01:32:11 +0200 + +gcc-3.0 (1:3.0.2ds2-0pre010922) unstable; urgency=low + + * Update to CVS sources (010922). + * Fixed upstream (closes: #111801). #105569 on hppa. + * Update hppa patch (Matt Taggart). + * Fix libstdc++-dev package description (closes: #112758). + * debian/rules.d/binary-objc.mk: Fix build error (closes: #112462). + * Make gobjc-3.0 conflict with gcc-3.0-sparc64 (closes: #111772). + + -- Matthias Klose Sat, 22 Sep 2001 09:34:49 +0200 + +gcc-3.0 (1:3.0.2ds1-0pre010908) unstable; urgency=low + + * Update to CVS sources (010908). + * Update hppa patch (Matt Taggart). + * Depend on libgc6-dev, not libgc5-dev, which got obsolete (during + the freeze ...). However adds s390 support (closes: #110189). + * debian/patches/m68k-reload.dpatch: New patch (Roman Zippel). + Fixes #89023. + * debian/patches/gcc-sparc.dpatch: New patch ("David S. Miller"). + Fixes libstdc++ testsuite failures on sparc. + + -- Matthias Klose Sat, 8 Sep 2001 14:26:20 +0200 + +gcc-3.0 (1:3.0.2ds0-0pre010826) unstable; urgency=low + + * gcc-3.0-nof: Fix symlink to gcc-3.0-base doc directory. + * debian/patches/gcj-without-rpath: New patch. + * Remove self dependency on libgcj package. + * Handle diversions for upgrades from 3.0 and 3.0.1 -> 3.0.2 + in gcc-3.0-sparc64 package. + * Build libg2c.a with -fPIC -DPIC and name the result libg2c-pic.a. + Link with this library to avoid linking with non-pic code. + Use this library when building dynamically loadable objects (python + modules, gimp plugins, ...), which need to be linked against g2c or + a library which is linked against g2c (i.e. lapack). + Packages needing '-lg2c-pic' must have a build dependency on + 'g77-3.0 (>= 1:3.0.2-0pre010826). + + -- Matthias Klose Sun, 26 Aug 2001 13:59:03 +0200 + +gcc-3.0 (1:3.0.2ds0-0pre010825) unstable; urgency=low + + * Update to CVS sources (010825). + * Add libc6-dev-sparc64 to gcc-3.0-sparc64 and to sparc build dependencies. + * Remove conflicts on egcc package (closes: #109718). + * Fix gcc-3.0-nof dependency. + * s390 patches against gcc-3.0.1 (Gerhard Tonn). + * debian/control: Require binutils (>= 2.11.90.0.27) + + -- Matthias Klose Sat, 25 Aug 2001 10:59:15 +0200 + +gcc-3.0 (1:3.0.1ds3-1) unstable; urgency=low + + * Final gcc-3.0.1 release. + * Changed upstream: default of -flimit-inline is 600 (closes: #106716). + * Add fastjar man page (submitted by "The Missing Man Pages Project", + http://www.netmeister.org/misc/m2p2i/) (closes: #103051). + * Fixed in last upload as well: #105246. + * debian/patches/cpp-memory-leak.dpatch: New patch + * Disable installation of shared libgcc on s390 (Gerhard Tonn). + + -- Matthias Klose Mon, 20 Aug 2001 20:47:13 +0200 + +gcc-3.0 (1:3.0.1ds2-0pre010811) unstable; urgency=high + + * Update to CVS sources (010811). Includes s390 support. + * Add xlibs-dev to Build-Depends (libgcj). + * Enable java for powerpc, disable java for ia64. + * Enable ObjC garbage collection for all archs, which have a libgc5-dev + package. + * New patch libstdc++-codecvt (Michael Piefel) (closes: #104614). + * Don't strip static libgcj library (work around binutils bug #107812). + * Handle diversions for upgrade 3.0 -> 3.0.1 in gcc-3.0-sparc64 package + (closes: #107569). + + -- Matthias Klose Sat, 11 Aug 2001 20:42:15 +0200 + +gcc-3.0 (1:3.0.1ds1-0pre010801) unstable; urgency=high + + * Update to CVS sources (010801). (closes: #107012). + * Remove build dependency on non-free graphviz and include pregenerated + docs (closes: #107124). + * Fixed in 3.0.1 (closes: #99307). + * Updated m68k-updates patch (Roman Zippel). + * Another fix for ia64 packaging bits (Randolph Chung). + + -- Matthias Klose Tue, 31 Jul 2001 21:52:55 +0200 + +gcc-3.0 (1:3.0.1ds0-0pre010727) unstable; urgency=high + + * Update to CVS sources (010727). + * Add epoch to source version. Change '.dsx' to 'dsx', so that + 3.1.1ds0 gt 3.1ds7 (closes: #106538). + + -- Matthias Klose Sat, 28 Jul 2001 09:56:29 +0200 + +gcc-3.0 (3.0.1.ds0-0pre010723) unstable; urgency=high + + * ia64 packaging bits (Randolph Chung) (closes: #106252). + + -- Matthias Klose Mon, 23 Jul 2001 23:02:03 +0200 + +gcc-3.0 (3.0.1.ds0-0pre010721) unstable; urgency=high + + * Update to CVS sources (010721). + - Remove patches applied upstream: libstdc++-limits.dpatch, + objc-data-references + - Updated other patches. + * Fix gij alternative (closes: #103468, #103883). + * Patch to fix bootstrap on sparc (closes: #103568). + * Corrected (closes: #105371) and updated README.Debian. + * m68k patches for sucessful bootstrap (Roman Zippel). + * Add libstdc++v3 porting hints to README.Debian and README.C++. + * m68k md fix (#105622) (Roman Zippel). + * debian/rules2: Disable non-functional ulimit on Hurd (#105884). + * debian/control: Require binutils (>= 2.11.90.0.24) + * Java is enabled for alpha (closes: #87300). + + -- Matthias Klose Sun, 22 Jul 2001 08:24:04 +0200 + +gcc-3.0 (3.0.ds9-4) unstable; urgency=high + + * Move this version to testing ASAP. testing still has a prerelease + version with now incompatible ABI's. If sparc doesn't build, + then IMHO it's better to remove it from testing. + * debian/control.m4: Set uploaders field. Adjust description of + gcc-3.0 (binary) package (closes: #102271, #102620). + * Separate gij.1 in it's own pseudo man page (closes: #99523). + * debian/patches/java-manpages.dpatch: New patch. + * libgcj: Install unversioned gij. + + -- Matthias Klose Tue, 3 Jul 2001 07:38:08 +0200 + +gcc-3.0 (3.0.ds9-3) unstable; urgency=high + + * Reenable configuration with posix threads on i386 (lost in hurd-i386 + merge). + + -- Matthias Klose Sun, 24 Jun 2001 22:21:45 +0200 + +gcc-3.0 (3.0.ds9-2) unstable; urgency=medium + + * Move this version to testing ASAP. testing still has a prerelease + version with now incompatible ABI's. + * Add libgcc0 and libgcc300 to the build conflicts (#102041). + * debian/README.FIRST: Removed (#101534). + * Updated subreg-byte patch (doc files). + * Disable java for the Hurd, mips and mipsel (#101570). + * Patch for building on the Hurd (#101708) (Jeff Bailey ). + * Packaging fixes for the Hurd (#101711) (Jeff Bailey ). + * Include pregenerated doxygen (1.2.6) docs for libstdc++-v3 (#101557). + The current doxygen-1.2.8.1 segaults. + * C++: Enable -fuse-cxa-atexit by default (#101901). + * Correct mail address in gccbug (#101743). + * Make rules resumable after failure in binary-xxx targets (#101637). + + -- Matthias Klose Sun, 24 Jun 2001 16:04:53 +0200 + +gcc-3.0 (3.0.ds9-1) unstable; urgency=low + + * Final 3.0 release. + * Update libgcc version number (#100983, #100988, #101069, #101115, #101328). + * Updated hppa-build patch (Matt Taggart ). + * Disable java for hppa. + * Updated subreg-byte patch for sparc (Ben Collins). + + -- Matthias Klose Mon, 18 Jun 2001 18:26:04 +0200 + +gcc-3.0 (3.0.ds8-0pre010613) unstable; urgency=low + + * Update patches for recent (010613 23:13 +0200) CVS sources. + * Fix packaging bugs (#100459, #100447, #100483). + * Build-Depend on gawk, mawk doesn't work well with test_summary. + + -- Matthias Klose Wed, 13 Jun 2001 23:13:38 +0200 + +gcc-3.0 (3.0.ds7-0pre010609) unstable; urgency=low + + * Fix build dependency for the hurd (#99164). + * Update patches for recent (010609) CVS sources. + * Disable java on powerpc (link error in libjava). + * gcc-3.0-base.postinst: Don't prompt for non-interactive installs (#100110). + + -- Matthias Klose Sun, 10 Jun 2001 09:45:57 +0200 + +gcc-3.0 (3.0.ds6-0pre010526) unstable; urgency=high + + * Urgency "high" for replacing the gcc-3.0 snapshots in testing, which + now are incompatile due to the changed ABIs. + * Upstream begins tagging with "gcc-3_0_pre_2001mmdd". + * Tighten dependencies to install only binary packages derived from + one source (#98851). Tighten libc6-dev dependency to match libc6. + + -- Matthias Klose Sun, 27 May 2001 11:35:31 +0200 + +gcc-3.0 (3.0.ds6-0pre010525) unstable; urgency=low + + * ATTENTION: The ABI (exception handling) changed. No upgrade path from + earlier snapshots (you had been warned in the postinst ...) + Closing #93597, #94576, #96448, #96461. + You have to rebuild + * HELP is appreciated for scanning the Debian BTS and sending followups + to bug reports!!! + * Should we name debian gcc uploads? What about a "still seeking + g++ maintainer" upload? + * Fixed in gcc-3.0: #97030 + * Update patches for recent (010525) CVS sources. + * Make check depend on build target (fakeroot problmes). + * debian/rules.d/binary-libgcc.mk: new file, build first. + * Free memory detection on the hurd for running the testsuite. + * Update debhelper build dependency. + * libstdc++-doc: Include doxygen generated docs. + * Fix boring packaging bugs, too tired for appropriate changelogs ... + #93343, #96348, #96262, #97134, #97905, #96451, #95812, #93157 + * Fixed bugs: #87000. + + -- Matthias Klose Sat, 26 May 2001 23:10:42 +0200 + +gcc-3.0 (3.0.ds5-0pre010510) unstable; urgency=low + + * Update patches for recent (010506) CVS sources. + * New version of source, as of 2001-05-10 + * New version of gpc source, as of 2001-05-06 (disabled by default). + * Make gcc-3.0-sparc64 provide an alternative for sparc64-linux-gcc, + since it can build kernels just fine (it seems) + * Add hppa patch from Matt Taggart + * Fix objc info inclusion...now merged with gcc info + * Do not install the .la for libstdc++, since it confuses libtool linked + applications when libstdc++3-dev and libstdc++2.10-dev are both + installed (closes #97905). + * Fixed gcc-base and libgcc section/prio to match overrides + + -- Ben Collins Mon, 7 May 2001 00:08:52 +0200 + +gcc-3.0 (3.0.ds5-0pre010427) unstable; urgency=low + + * Fixed priority for fastjar from optional to extra + * New version of source, as of 2001-04-27 + * Fix description of libgcj-dev + * libffi-install: Make libffi installable + * Add libffi and libffi-dev packages. libffi is only enabled for java + targets right now. Perhaps more will be enabled later. + * Fixes to build cross compiler package (for avr) + (Hakan Ardo ). + * Better fixincludes description (#93157). + * Remove all remnants of libg++ + * Remove all hacks around libstdc++ version. Since we are strictly v3 now, + we can treat it like a normal shared lib, and not worry about all those + ABI changes. + * Remove all cruft control scripts. Note, debhelper will create scripts + that it needs to. It will do the doc link stuff and the ldconfig stuff + explicitly. + * Clean up the SONAME parsing stuff, make it a little more cleaner over + all the lib packages + * Make libffi install when built (IOW, whenever java is enabled). This + should obsolete the libffi package, which is old and broken + * Revert to normal sonames, except for ia64 (for now) + * Remove all references to dh_testversion, since they are deprecated for + Build-Depends + * Fix powerpc nof build + * Remove all references to the MULTILIB stuff, since the arches are + using specialized builds anyway (nof, softfloat). + * Added 64bit sparc64 package (gcc-3.0-sparc64, libgcc0-sparc64) + * Removed obsolete shlibs.local file + + -- Ben Collins Sun, 15 Apr 2001 21:33:15 -0400 + +gcc-3.0 (3.0.ds4-0pre010403) unstable; urgency=low + + * debian/README: Updated for gcc-3.0 + * debian/rules.patch: Added subreg-byte patch for sparc + * debian/rules.unpack: Update to current CVS for gcc tarball name + * debian/patches/subreg-byte.dpatch: sparc subreg-byte support + * debian/patches/gcc-rawhide.dpatch: Removed + debian/patches/gpc-2.95.dpatch: Removed + debian/patches/sparc32-rfi.dpatch: Removed + debian/patches/temporary.dpatch: Removed + * Moving to unstable now + * debian/patches/gcc-ppc-disable-shared-libgcc.dpatch: New patch, + disables shared libgcc for powerpc target, since it isn't compatible + with the EABI objects. + * Create $(with_shared_libgcc) var + * debian/rules.d/binary-gcc.mk: Use this new variable to determine if + the libgcc package actually has any files + + -- Ben Collins Tue, 3 Apr 2001 23:00:55 -0400 + +gcc-3.0 (3.0.ds2-0pre010223) experimental; urgency=low + + * New snapshot. Use distinct shared object names for shared libraries: + we don't know if binary API's still change until the final release. + * Versioned package names. + * debian/control.m4: New file. Add gcc-base, libgcc0, libobjc1, + libstdc++-doc, libgcj1, libgcj1-dev, fastjar, fixincludes packages. + Remove gcc-docs package. + * debian/gcov.1: Remove. + * debian/*: Remove 2.95.x support. Prepare for 3.0. + * debian/patches: Remove 2.95.x patches. + * Changed source package name. It's not allowed anymore to overwrite + source packages with different content. Introducing a 'debian source + element' (.ds), which is stripped again from the version number + for the binary packages. + * Fixed bugs and added functionality: + #26436, #27878, #33786, #34876, #35477, #42662, #46181, #42989, + #47981, #48530, #50529, #51227, #51456, #51651, #52382, #53698, + #55291, #55967, #56867, #58219, #59005, #59232, #59776, #64628, + #65687, #67631, #68632, #68963, #68987, #69530, #72933, #75120, + #75759, #76645, #76827, #83221, #87540 + * libgcj fixes: 42894, #51266, #68560, #71187, #79984 + + -- Matthias Klose Sat, 24 Feb 2001 13:41:11 +0100 + +gcc-2.95 (2.95.3-2.001222) experimental; urgency=low + + * New upstream version 2.95.3 experimental (CVS 20001222). + * debian/control.in: Versioned package names, removal of snapshot logic. + Remove fake gcc-docs package. + * Reserve -1 release numbers for woody. + * Updated to gpc-20001218. + + -- Matthias Klose Fri, 22 Dec 2000 19:53:03 +0100 + +gcc (2.95.2-20) unstable; urgency=low + + * Apply patch from gcc-2_95-branch; remove ulimit for make check. + + -- Matthias Klose Sun, 10 Dec 2000 17:01:13 +0100 + +gcc (2.95.2-19) unstable; urgency=low + + * Added testsuite-20001207 from current snapshots. We'll need results + for 2.95.2 to make sure there are no regressions against that release. + Dear build daemons and porters to other architectures, please send an + email to gcc-testresults@gcc.gnu.org. + You can do this by running "debian/rules mail-summary". + * Updated to gpc-20001206. + * Added S/390 patch prepared by Chu-yeon Park (#78983). + * debian/patches/libio.dpatch: Fix iostream doc (fixes #77647). + * debian/patches/gcc-doc.dpatch: Update URL (fixes #77542). + * debian/patches/gcc-reload1.dpatch Patch from the gcc-bug list which + fixes a problem in "long long" on i[345]86 (i686 was not affected). + + -- Matthias Klose Sat, 9 Dec 2000 12:30:32 +0100 + +gcc (2.95.2-18) unstable; urgency=low + + * debian/control.in: Fix syntax errors (fixes #76146, #76458). + Disable gpc on the hurd by request (#75686). + * debian/patches/arm-various.dpatch: Patches from Philip Blundell + for ARM arch (fixes #75801). + * debian/patches/gcc-alpha-mi-thunk.dpatch: Patches from Chris Chimelis + for alpha arch. + * debian/patches/g77-docs.dpatch: Adjust g77 docs (fixes #72594). + * Update gpc to gpc-20001118. + * Reenable gpc for alpha. + * debian/README.C++: Merge debian/README.libstdc++ and C++ FAQ information + provided by Matt Zimmermann. + * Build gcj only on architectures, where libgcj-2.95.1 can be built as well. + Probably needs some adjustments ... + * Conditionalize for chill, fortran, java, objc and chill. + + * NOT APPLIED: + debian/patches/libstdc++-bastring.dpatch: Apply fix (fixes #75759). + + -- Matthias Klose Sun, 19 Nov 2000 10:40:41 +0100 + +gcc (2.95.2-17) unstable; urgency=low + + * Disable gpc for alpha. + * Include gpc-cpp in gpc package (fixes #74492). + * Don't build gcc-docs compatibility package anymore. + + -- Matthias Klose Wed, 11 Oct 2000 06:16:53 +0200 + +gcc (2.95.2-16) unstable; urgency=low + + * Applied the emdebian/cross compiler patch and documentation + (Frank Smith ). + * Applied patch for avr target (Hakan Ardo ). + * debian/control.in: Add awk to Build-Depends. + Tighten libc6-dev dependency for libstdc++-dev (fixes #73031, + #72531, #72534). + * Disable libobjc_gc for m68k again (fixes #74380). + * debian/patches/arm-namespace.dpatch: Apply patch from Philip + Blundell to fix name space pollution on arm + (fixes #70937). + * Fix more warnings in STL headers (fixes #69352, #71943). + + -- Matthias Klose Mon, 9 Oct 2000 21:51:41 +0200 + +gcc (2.95.2-15) unstable; urgency=low + + * debian/control.in: Add libgc5-dev to build depends (fixes #67015). + * debian/rules.def: Build GC enabled ObjC runtime for sparc. + * Bug #58741 fixed (in some version since 2.95.2-5). + * debian/control.in: Recommend librx1g-dev, libgmp2-dev, libncurses5-dev + (unit dependencies). + * Patches from Marcus Brinkmann for the hurd (fixes #67763): + - debian/rules.defs: Disable objc_gc on hurd-i386. + Disable libg++ on GNU systems. + - debian/rules2: Set correct names of libstdc++/libg++ + libraries on GNU systems. + Write out correct shlibs and shlibs.local file content. + - Keep _G_config.h for the Hurd. + * Apply patch for ObjC linker warnings. + * Don't apply gcj backport patch for sparc. + * Apply libio compatability patch + * debian/glibcver.sh: generate appropriate version for glibc + * debian/rules.conf: for everything after glibc 2.1, we always append + "-glibc$(ver)" to the C++ libs for linux. + * Back down gpc to -13 version (-14 wont compile on anything but i386 + and m68k becuase of gpc). + * Remove extraneous and obsolete sparc64 patches/files from debian/* + + -- Ben Collins Thu, 21 Sep 2000 08:08:35 -0400 + +gcc-snapshot (20000901-2.2) experimental; urgency=low + + * New snapshot. + * debian/rules2: Move tradcpp0 to cpp package. + + -- Matthias Klose Sat, 2 Sep 2000 01:14:28 +0200 + +gcc-snapshot (20000802-2.1) experimental; urgency=low + + * New snapshot. + * debian/rules2: Fixes. tradcpp0 is in gcc package, not cpp. + + -- Matthias Klose Thu, 3 Aug 2000 07:40:05 +0200 + +gcc-snapshot (20000720-2) experimental; urgency=low + + * New snapshot. + * Enable libstdc++-v3. + * debian/rules2: Don't use -D for /usr/bin/install. + + -- Matthias Klose Thu, 20 Jul 2000 22:33:37 +0200 + +gcc (2.95.2-14) unstable; urgency=low + + * Update gpc patch. + + -- Matthias Klose Wed, 5 Jul 2000 20:51:16 +0200 + +gcc (2.95.2-13) frozen unstable; urgency=low + + * Update debian/README: document how to compile 2.0.xx kernels; don't + register gcc272 as an alternative for gcc (closes #62419). + Clarify compiler setup (closes #65548). + * debian/control.in: Make libstdc++-dev depend on current version of g++. + * Undo CVS update from release -8 (problems on alpha, #55263). + + -- Matthias Klose Mon, 19 Jun 2000 23:06:48 +0200 + +gcc (2.95.2-12) frozen unstable; urgency=low + + * debian/gpc.postinst: Correct typo introduced with -11 (fixes #64193). + * debian/patches/gcc-rs600.dpatch: ppc codegen fix (fixes #63933). + + -- Matthias Klose Sun, 21 May 2000 15:56:05 +0200 + +gcc (2.95.2-11) frozen unstable; urgency=medium + + * Upload to unstable again (fixes critical #63784). + * Fix doc-base files (fixes important #63810). + * gpc wasn't built in -10 (fixes #63977). + * Make /usr/bin/pc an alternative (fixes #63888). + * Add SYSCALLS.c.X to gcc package. + + -- Matthias Klose Sun, 14 May 2000 22:17:44 +0200 + +gcc (2.95.2-10) frozen; urgency=low + + * debian/control.in: make gcc conflict on any version of egcc + (slink to potato upgrade problem, fixes grave #62084). + * Build protoize programs, separate out in new package (fixes #59436, + #62911). + * Create dummy gcc-docs package for smooth update from slink (fixes #62537). + * Add doc-base support for all -doc packages (fixes #63380). + + -- Matthias Klose Mon, 1 May 2000 22:24:28 +0200 + +gcc (2.95.2-9) frozen unstable; urgency=low + + * Disable the sparc-bi-arch.dpatch (patch from Ben Collins, built + for sparc as NMU 8.1) (fixes critical #61529 and #61511). + "Seems that when you compile gcc 2.95.x for sparc64-linux and compile + sparc32 programs, the code is not the same as sparc-linux compile for + sparc32 (this is a bug, and is fixed in gcc 2.96 CVS)." + * debian/patches/gcj-vs-iconv.dpatch: Option '--encoding' for + encoding of input files. Patch from Tom Tromey + backported to 2.95.2 (fixes #42895). + Compile a Latin-1 encoded file with `gcj --encoding=Latin1 ...'. + * debian/control.in: gcc, g++ and gobjc suggest their corresponding + task packages (fixes #59623). + + -- Matthias Klose Sat, 8 Apr 2000 20:19:15 +0200 + +gcc (2.95.2-8) frozen unstable; urgency=low + + * Post-2.95.2 CVS updates of the gcc-2_95-branch until 20000313. + * debian/rules2: configure with --enable-java-gc=no for sparc. Fixes + gcj side of #60535. + * debian/rules.patch: Disable gcc-emit-rtl patch for all archs but + alpha. Disable g++-is-tree patch ("just for 2.95.1"). + * debian/README: Update for gcc-2.95. + + -- Matthias Klose Mon, 27 Mar 2000 00:03:16 +0200 + +gcc (2.95.2-7) frozen unstable; urgency=low + + * debian/patches/gcc-empty-struct-init.dpatch; Apply patch from + http://gcc.gnu.org/ml/gcc-patches/2000-02/msg00637.html. Fixes + compilation of 2.3.4x kernels. + * debian/patches/gcc-emit-rtl.dpatch: Apply patch from David Huggins-Daines + (backport from 2.96 CVS to fix #55263). + * debian/patches/gcc-pointer-arith.dpatch: Apply patch from Jim Kingdon + (backport from 2.96 CVS to fix #54951). + + -- Matthias Klose Thu, 2 Mar 2000 23:16:43 +0100 + +gcc (2.95.2-6) frozen unstable; urgency=low + + * Post-2.95.2 CVS updates of the gcc-2_95-branch until 20000220. + * Remove dangling symlink probably left over from libstdc++2.9 + package (fixes #53661). + * debian/patches/gcc-alpha-complex-float.dpatch: Fixed patch by + David Huggins-Daines (fixes #58486). + * debian/g++.{postinst,prerm}: Remove outdated g++FAQ registration + (fixes #58253). + * debian/control.in: gcc-doc replaces gcc-docs (fixes #58108). + * debian/rules2: Include some fixed headers (asm, bits, linux, ...). + * debian/patches/{gcc-alpha-ev5-fix,libstdc++-valarray}.dpatch: Remove. + Applied upstream. + * debian/patches/libstdc++-bastring.dpatch: Add patch from + sicard@bigruth.solsoft.fr (fixes #56715). + + -- Matthias Klose Sun, 20 Feb 2000 15:08:13 +0100 + +gcc (2.95.2-5) frozen unstable; urgency=low + + * Post-2.95.2 CVS updates of the gcc-2_95-branch until 20000116. + * Add more build dependencies (fixes #53204). + * debian/patches/gcc-alpha-complex-float.dpatch: Patch from + Joel Klecker to compile glibc correctly on alpha. + "Should fix the g77 problems too." + * debian/patches/{libio,libstdc++-wall2}.dpatch. Remove patches + applied upstream. + + -- Matthias Klose Sun, 16 Jan 2000 19:16:54 +0100 + +gcc (2.95.2-4) unstable; urgency=low + + * debian/patches/libio.dpatch: Patch from Martin v. Loewis. + (fixes: #35628). + * debian/patches/libstdc++-deque.dpatch: Patch from Martin v. Loewis. + (fixes: #52689). + * debian/control.in: Updated Build-Depends, removed outdated README.build. + Fixes #51246. + * Tighten dependencies to cpp (>= 2.95.2-4) (closes: #50294). + * debian/rules.patch: Really do not apply patches/gcj-backport.dpatch. + Fixes #51636. + * Apply updated sparc-bi-arch.dpatch from Ben Collins. + * libstdc++: Define wstring type, if __ENABLE_WSTRING is defined. Request + from the author of the War FTP Daemon for Linux ("Jarle Aase" + ). + * debain/g++.preinst: Remove dangling sysmlinks (fixes #52359). + + -- Matthias Klose Sun, 19 Dec 1999 21:53:48 +0100 + +gcc (2.95.2-3) unstable; urgency=low + + * debian/rules2: Don't install $(gcc_lib_dir)/include/asm; these are + headers fixed for glibc-1.x (closes: #49434). + * debian/patches/cpp-dos-newlines.dpatch: Keep CR's without + following LF (closes: #49186). + * Bug #37358 (internal compiler errors when building vdk_0.6.0-5) + fixed in gcc-2.95.? (closes: #37358). + * Apply patch gcc-alpha-ev5-fix from Richard Henderson + (should fix #48527 and #46963). + * debian/README.Bugs: Documented non bug #44554. + * Applied patch from Alexandre Oliva to fix gpc boostrap on alpha. + Reenabled gpc on all architectures. + * Post-2.95.2 CVS updates of the gcc-2_95-branch until 19991108. + * Explicitely generate postinst/prerm chunks for usr/doc transition. + debhelper currently doesn't handle generation for packages with + symlinked directories. + * debian/patches/libstdc++-wall3.dpatch: Fix warnings in stl_deque.h + and stl_rope.h (closes: #46444, #46720). + * debian/patches/gcj-backport.dpatch: Add file, don't apply (yet). + + -- Matthias Klose Wed, 10 Nov 1999 18:58:45 +0100 + +gcc (2.95.2-2) unstable; urgency=low + + * New gpc-19991030 snapshot. + * Post-2.95.2 CVS updates of the gcc-2_95-branch until 19991103. + * Reintegrated sparc patches (bcollins@debian.org), which were lost + in 2.95.2-1. + * debian/rules2: Only install $(gcc_lib_dir)/include/asm, when existing. + * debian/patches/gpc-2.95.{dpatch,diff}: updated patch to drop + initialization in stor-layout.c. + * debian/NEWS.gcc: Updated for gcc-2.95.2. + * debian/bugs/bug-...: Removed testcases for fixed bugs. + * debian/patches/...dpatch: Removed patches applied upstream. + * debian/{rules2,g++.postinst,g++.prerm}: Handle c++ alternative. + * debian/changelog: Merged gcc272, egcs and snapshot changelogs. + + -- Matthias Klose Tue, 2 Nov 1999 23:09:23 +0200 + +gcc (2.95.2-1.1) unstable; urgency=low + + * Most of the powerpc patches have been applied upstream. Remove all + but ppc-ice, ppc-andrew-dwarf-eh, and ppc-descriptions. + * mulilib-install.dpatch was definitely a bad idea. Fix it properly + by using install -D. + * Also, don't make directories before installing any more. Simplifies + rules a (tiny) bit. + * Do not build with LDFLAGS=-s. Everything gets stripped out anyway by + dh_strip -a -X_debug; so leave the binaries in the build tree with + debugging symbols for simplified debugging of the packages. + + -- Daniel Jacobowitz Sat, 30 Oct 1999 12:40:12 -0400 + +gcc (2.95.2-1) unstable; urgency=low + + * gcc-2.95.2 release (taken from the CVS archive). -fstrict-aliasing + is disabled upstream. + + -- Matthias Klose Mon, 25 Oct 1999 10:26:19 +0200 + +gcc (2.95.2-0pre4) unstable; urgency=low + + * Updated to cvs updates of the gcc-2_95-branch until 19991021. + * Updated gpc to gpc-19991018 snapshot (closes: #33037, #47453). + Enable gpc for all architectures ... + * Document gcc exit codes (closes: #43863). + * According to the bug submitter (Sergey V Kovalyov ) + the original source of these CERN librarties is outdated now. The latest + version of cernlibs compiles and works fine with slink (closes #31546). + * According to the bug submitter (Gergely Madarasz ), + the problem triggered on i386 cannot be reproduced with the current + jade and php3 versions anymore (closes: #35215). + * Replace corrupted m68k-pic.dpatch (from Roman Hodek and Andreas Schwab + and apply to + all architectures (closes: #48011). + * According to the bug submitter (Herbert Xu ) + this bug "probably has been fixed". Setting it to severity "fixed" + (fixes: #39616), will close it later ... + * debian/README.Bugs: Document throwing C++ exceptions "through" C + libraries (closes: #22769). + + -- Matthias Klose Fri, 22 Oct 1999 20:33:00 +0200 + +gcc (2.95.2-0pre3) unstable; urgency=low + + * Updated to cvs updates of the gcc-2_95-branch until 19991019. + * Apply NMU patches (closes: #46217). + * debian/control.in: Fix egcs64 conflict-dependency for sparc + architecture (closes: #47088). + * debian/rules2: dbg-packages share doc dir with lib packages + (closes #45067). + * debian/patches/gcj-debian-policy.dpatch: Patch from Stephane + Bortzmeyer to conform to Debian policy (closes: #44463). + * debian/bugs/bug-*: Added test cases for new bug reports. + * debian/patches/libstdc++-bastring.dpatch: Patch by Richard Kettlewell + (closes #46550). + * debian/rules.patch: Apply libstdc++-wall2 patch (closes #46609). + * debian/README: Fix typo (closes: #45253). + * debian/control.in: Remove primary/secondary distinction; + dbg-packages don't provide their normal counterparts (closes #45206). + * debian/rules.patch: gcc-combine patch applied upstream. + * debian/rules2: Only use mail if with_check is set (off by default). + * debian/rules.conf: Tighten binutils dependency to 2.9.5.0.12. + + -- Matthias Klose Tue, 19 Oct 1999 20:33:00 +0200 + +gcc (2.95.2-0pre2.0.2) unstable; urgency=HIGH (for m68k) + + * Binary-only NMU for m68k as quick fix for another bug; the patch + is in CVS already, too. + * Applied another patch by Andreas Schwab to fix %a5 restauration in + some cases. + + -- Roman Hodek Thu, 30 Sep 1999 16:09:15 +0200 + +gcc (2.95.2-0pre2.0.1) unstable; urgency=HIGH (for m68k) + + * Binary-only NMU for m68k as quick fix for serious bugs; the patches + are already checked into gcc CVS and should be in the next official + version, too. + * Applied two patches by Andreas Schwab to fix -fpic and loop optimization. + + -- Roman Hodek Mon, 27 Sep 1999 15:32:49 +0200 + +gcc (2.95.2-0pre2) unstable; urgency=low + + * Fixed in 2.95.2 (closes: #43478). + * Previous version had Pascal examples missing in doc directory. + + -- Matthias Klose Wed, 8 Sep 1999 22:18:17 +0200 + +gcc (2.95.2-0pre1) unstable; urgency=low + + * Updated to cvs updates of the gcc-2_95-branch until 19990828. + * Apply work around memory corruption (just for 2.95.1) by + Daniel Jacobowitz . + * debian/patches/libstdc++-wall2.dpatch: Patch from Franck Sicard + to fix some warnings (closes: #44670). + * debian/patches/libstdc++-valarray.dpatch: Patch from Hideaki Fujitani + to fix a bug in valarray_array.h. + * Applied NMU from Jim Pick minus the jump.c and fold-const.c patches + already in the gcc-2_95-branch (closes: #44690). + * Conform to debian-java policy (closes: #44463). + * Move docs to /usr/share/doc (closes: #44782). + * Remove debian/patches/gcc-align.dpatch applied upstream. + * debian/*.postinst: Call install-info only, when configuring. + * debian/*.{postinst,prerm}: Add #DEBHELPER# comments to handle + /usr/doc -> /usr/share/doc transition. + + -- Matthias Klose Wed, 8 Sep 1999 22:18:17 +0200 + +gcc (2.95.1-2.1) unstable; urgency=low + + * Non-maintainer upload. + * ARM platform no longer needs library-prefix patch. + * Updated patches from Philip Blundell. + + -- Jim Pick Wed, 8 Sep 1999 20:14:07 -0700 + +gcc (2.95.1-2) unstable; urgency=low + + * debian/gcc.{postinst,prerm}: gcc provides an alternative for + sparc64-linux-gcc. + * Applied patch from Ben Collins to enable bi-architecture (32/64) + support for sparc. + * Rebuild debian/control and debian/rules.parameters after unpacking. + * debian/rules2: binary-indep. Conditionalize on with_pascal. + + -- Matthias Klose Sat, 4 Sep 1999 13:47:30 +0200 + +gcc (2.95.1-1) unstable; urgency=low + + * Updated to release gcc-2.95.1 and cvs updates of the gcc-2_95-branch + until 19990828. + * debian/README.gcc: Updated NEWS file to include 2.95 and 2.95.1 news. + * debian/README.java: New file. + * debian/rules.defs: Disabled gpc for alpha, arm. Disabled ObjC-GC + for alpha. + * debian/rules [clean]: Remove debian/rules.parameters. + * debian/rules2 [binary-arch]: Call dh_shlibdeps with LD_LIBRARY_PATH set + to installation dir of libstdc++. Why isn't this the default? + * debian/control.in: *-dev packages do not longer conflict with + libg++272-dev package. + * Apply http://egcs.cygnus.com/ml/gcc-patches/1999-08/msg00599.html. + * Only define BAD_THROW_ALLOC, when using exceptions (fixes #43462). + * For ObjC (when configured with GC) recommend libgc4-dev, not libgc4. + * New version of 68060 build patch. + * debian/rules.conf: For m68k, depend on binutils version 2.9.1. + + -- Matthias Klose Sat, 28 Aug 1999 18:16:31 +0200 + +gcc (2.95.1-0pre2) unstable; urgency=medium + + * gpc is back again (fixes grave #43022). + * debian/patches/gpc-updates.dpatch: Patches sent to upstream authors. + * Work around the fatal dependtry assertion failure bug in dpkg (hint + from "Antti-Juhani Kaijanaho" , fixes important #43072). + + -- Matthias Klose Mon, 16 Aug 1999 19:34:14 +0200 + +gcc (2.95.1-0pre1) unstable; urgency=low + + * Updated to cvs 19990815 gcc-2_95-branch; included install docs and + FAQ from 2.95 release; upload source package as well. + * Source package contains tarballs only (gcc, libg++, installdocs). + * debian/rules: Splitted into debian/rules{,.unpack,.patch,.conf,2}. + * debian/gcc.postinst: s/any key/RETURN; warn only when upgrading from + pre 2.95 version; reference /usr/doc, not /usr/share/doc. + * Checked syntax for attributes of functions; checked for #35068; + checked for bad gmon.out files (at least with libc6 2.1.2-0pre5 and + binutils 2.9.1.0.25-2 the problem doesn't show up anymore). + * debian/patches/cpp-macro-doc.dpatch: Document macro varargs in cpp.texi. + * gcc is primary compiler for all platforms but m68k. Setting + severity of #22513 to fixed. + * debian/patches/gcc-default-arch.dpatch: New patch to enable generation + of i386 instruction as default (fixes #42743). + * debian/rules: Removed outdated gcc NEWS file (fixes #42742). + * debian/patches/libstdc++-out-of-mem.dpatch: Throw exception instead + of aborting when out of memory (fixes #42622). + * debian/patches/cpp-dos-newlines.dpatch: Handle ibackslashes after + DOS newlines (fixes #29240). + * Fixed in gcc-2.95.1: #43001. + * Bugs closed in this version: + Closes: #11525, #12253, #22513, #29240, #35068, #36182, #42584, #42585, + #42602, #42622, #42742 #42743, #43001, #43002. + + -- Matthias Klose Sun, 15 Aug 1999 10:31:50 +0200 + +gcc (2.95-3) unstable; urgency=high + + * Provide /lib/cpp again (fixes important bug #42524). + * Updated to cvs 19990805 gcc-2_95-branch. + * Build with the default scheduler. + * Apply install-multilib patch from Dan Jacobowitz. + * Apply revised cpp-A- patch from Dan Jacobowitz. + + -- Matthias Klose Fri, 6 Aug 1999 07:25:19 +0200 + +gcc (2.95-2) unstable; urgency=low + + * Remove /lib/cpp. This driver uses files from /usr/lib/gcc-lib anyway. + * The following bugs are fixed (compared to egcs-1.1.2). + Closes: #4429, #20889, #21122, #26369, #28417, #28261, #31416, #35261, + #35900, #35906, #38246, #38872, #39098, #39526, #40659, #40991, #41117, + #41290, #41302, #41313. + * The following by Joel Klecker: + - Adopt dpkg-architecture variables. + - Go back to SHELL = bash -e or it breaks where /bin/sh is not bash. + - Disabled the testsuite, it is not included in the gcc 2.95 release. + + -- Matthias Klose Sat, 31 Jul 1999 18:00:42 +0200 + +gcc (2.95-1) unstable; urgency=low + + * Update for official gcc-2.95 release. + * Built without gpc. + * debian/rules: Remove g++FAQ from rules, which is outdated. + For ix86, build for i386, not i486. + * Apply patch from Jim Pick for building multilib package on arm. + + -- Matthias Klose Sat, 31 Jul 1999 16:38:21 +0200 + +gcc (2.95-0pre10) unstable; urgency=low + + * Use ../builddir-gcc-$(VER) by default instead of ./builddir; upstream + strongly advises configuring outside of the source tree, and it makes + some things much easier. + * Add patch to prevent @local branches to weak symbols on powerpc (fixes + apt compilation). + * Add patch to make cpp -A- work as expected. + * Renamed debian/patches/ppc-library-prefix.dpatch to library-prefix.dpatch; + apply on all architectures. + * debian/control.in: Remove snapshot dependencies. + * debian/*.postinst: Reflect use of /usr/share/{info,man}. + + -- Daniel Jacobowitz Thu, 22 Jul 1999 19:27:12 -0400 + +gcc (2.95-0pre9) unstable; urgency=low + + * The following bugs are fixed (compared to egcs-1.1.2): #4429, #20889, + #21122, #26369, #28417, #28261, #35261, #38246, #38872, #39526, #40659, + #40991, #41117, #41290. + * Updated to CVS gcc-19990718 snapshot. + * debian/control.in: Removed references to egcs in descriptions. + Changed gcj's Recommends libgcj-dev to Depends. + * debian/rules: Apply ppc-library-prefix for alpha as well. + * debian/patches/arm-config.dpatch: Updated patch sent by Jim Pick. + + -- Matthias Klose Sun, 18 Jul 1999 12:21:07 +0200 + +gcc (2.95-0pre8) unstable; urgency=low + + * Updated CVS. + * debian/copyright: s%doc/copyright%share/common-licenses% + * debian/README.Bugs: s/egcs.cygnus.com/gcc.gnu.org/ s/egcs-bugs/gcc-bugs/ + * debian/patches/reporting.dpatch: Remake diff for current sources. + * debian/libstdc++-dev.postinst: It's /usr/share/info/iostream.info. + * debian/rules: Current dejagnu snapshot reports a framework version + of 1.3.1. + + -- Joel Klecker Sun, 18 Jul 1999 02:09:57 -0700 + +gcc-snapshot (19990714-0pre6) experimental; urgency=low + + * Updated to CVS gcc-19990714 snapshot. + * Applied ARM patch (#40515). + * Converted DOS style linefeeds in debian/patches/ppc-* files. + * debian/rules: Reflect change in gcc/version.c; use sh -e as shell: + for some obscure reason, bash -e doesn't work. + * Reflect version change for libstdc++ (2.10). Remove libg++-name + patch; libg++ now has version 2.8.1.3. Removed libc version from + the package name. + + -- Matthias Klose Wed, 14 Jul 1999 18:43:57 +0200 + +gcc-snapshot (19990625-0pre5.1) experimental; urgency=low + + * Non-maintainer upload. + * Added ARM specific patch. + + -- Jim Pick Tue, 29 Jun 1999 22:36:08 -0700 + +gcc-snapshot (19990625-0pre5) experimental; urgency=low + + * Updated to CVS gcc-19990625 snapshot. + + -- Matthias Klose Fri, 25 Jun 1999 16:11:53 +0200 + +gcc-snapshot (19990609-0pre4.1) experimental; urgency=low + + * Added and re-added a few last PPC patches. + + -- Daniel Jacobowitz Sat, 12 Jun 1999 16:48:01 -0500 + +gcc-snapshot (19990609-0pre4) experimental; urgency=low + + * Updated to CVS egcs-19990611 snapshot. + + -- Matthias Klose Fri, 11 Jun 1999 10:20:09 +0200 + +gcc-snapshot (19990609-0pre3) experimental; urgency=low + + * CVS gcc-19990609 snapshot. + * New gpc-19990607 snapshot. + + -- Matthias Klose Wed, 9 Jun 1999 19:40:44 +0200 + +gcc-snapshot (19990524-0pre1) experimental; urgency=low + + * egcs-19990524 snapshot. + * First snapshot of the gcc-2_95-branch. egcs-1.2 is renamed to gcc-2.95, + which is now the "official" successor to gcc-2.8.1. The full version + name is: gcc-2.95 19990521 (prerelease). + * debian/control.in: Changed maintainers to `Debian GCC maintainers'. + * Moved all version numbers to epoch 1. + * debian/rules: Major changes. The support for secondary compilers + was already removed for the egcs-1.2 snapshots. Many fixes by + Joel Klecker . + - Send mail to Debian maintainers for successful builds. + - Fix VER and VERNO sed expressions. + - Replace remaining GNUARCH occurrences. + * New gpc snapshot (but don't build). + * debian/patches/valarray.dpatch: Backport from libstdc++-v3. + * debian/gcc-doc.*: Info is now gcc.info* (Joel Klecker ). + * Use cpp driver provided by the package. + * New script c89 (fixes #28261). + + -- Matthias Klose Sat, 22 May 1999 16:10:36 +0200 + +egcs (1.1.2-2) unstable; urgency=low + + * Integrate NMU's for arm and sparc (fixes #37582, #36857). + * Apply patch for the Hurd (fixes #37753). + * Describe open bugs in TODO.Debian. Please have a look if you can help. + * Update README / math functions section (fixes #35906). + * Done by J.H.M. Dassen (Ray) : + - At Richard Braakman's request, made -dbg packages for libstdc++ + and libg++. + - Provide egcc(1) (fixes lintian error). + + -- Matthias Klose Sun, 16 May 1999 14:30:56 +0200 + +egcs-snapshot (19990502-1) experimental; urgency=low + + * New snapshot. + + -- Matthias Klose Thu, 6 May 1999 11:51:02 +0200 + +egcs-snapshot (19990418-2) experimental; urgency=low + + * Merged Rays changes to build debug packages. + + -- Matthias Klose Wed, 21 Apr 1999 16:54:56 +0200 + +egcs-snapshot (19990418-1) experimental; urgency=low + + * New snapshot. + * Disable cpplib. + + -- Matthias Klose Mon, 19 Apr 1999 11:32:19 +0200 + +egcs (1.1.2-1.2) unstable; urgency=low + + * NMU for arm + * Added arm-optimizer.dpatch with optimizer workaround for ARM + + -- Jim Pick Mon, 19 Apr 1999 06:17:13 -0700 + +egcs (1.1.2-1.1) unstable; urgency=low + + * NMU for sparc + * Included dpatch to modify the references to gcc/crtstuff.c so that + __register_frame_info is not a weak reference. This allows potato to + remain binary compatible with slink, while still retaining compatibility + with other sparc/egcs1.1.2 distributions. Diff in .dpatch format has + been sent to the maintainer with a note it may not be needed for 1.1.3. + + -- Ben Collins Tue, 27 Apr 1999 10:15:03 -0600 + +egcs (1.1.2-1) unstable; urgency=low + + * Final egcs-1.1.2 release built for potato as primary compiler + for all architectures except m68k. + + -- J.H.M. Dassen (Ray) Thu, 8 Apr 1999 13:14:29 +0200 + +egcs-snapshot (19990321-1) experimental; urgency=low + + * New snapshot. + * Disable gpc. + * debian/rules: Simplified (no secondary compiler, bumped all versions + to same epoch, libapi patch is included upstream). + * Separated out cpp documentation to cpp-doc package. + * Fixed in this version: #28417. + + -- Matthias Klose Tue, 23 Mar 1999 02:11:18 +0100 + +egcs (1.1.2-0slink2) stable; urgency=low + + * Applied H.J.Lu's egcs-19990315.linux patch. + * Install faq.html and egcs-1.1.2 announcment. + + -- Matthias Klose Tue, 23 Mar 1999 01:14:54 +0100 + +egcs (1.1.2-0slink1) stable; urgency=low + + * Final egcs-1.1.2 release; compiled with glibc-2.0 for slink on i386. + * debian/control.in: gcc provides egcc, when FIRST_PRIMARY defined. + * Fixes #30767, #32278, #34252, #34352. + * Don't build the libstdc++.so.2.9 library on architectures, which have + switched to glibc-2.1. + + -- Matthias Klose Wed, 17 Mar 1999 12:55:59 +0100 + +egcs (1.1.1.63-2.2) unstable; urgency=low + + * Non-maintainer upload. + * Incorporate patch from Joel Klecker to fix snapshot packages + by moving/removing the application of libapi. + * Disable the new libstdc++-dev-config and the postinst message in + glibc 2.1 versions. + + -- Daniel Jacobowitz Mon, 12 Mar 1999 14:16:02 -0500 + +egcs (1.1.1.63-2.1) unstable; urgency=low + + * Non-maintainer upload. + * Compile with glibc 2.1 release version. + * New upstream version egcs-1.1.2 pre3. + * Miscellaneous rules updates (see changelog.snapshot). + * New set of powerpc-related patches from Franz Sirl, + . + * Disable libgcc.dpatch (new solution implemented upstream). Remove it. + * Also pass $target to config.if. + * Enable Dwarf2 EH for powerpc. Bump the C++ binary version. No + loss in -backwards- compatibility as far as I can tell, so add a + compatibility symlink, and add to shlibs file. + * Add --no-backup-if-mismatch to the debian/patches/*.dpatch files, + to prevent bogus .orig's in diffs. + * Merged with (unreleased) 1.1.1.62-1 and 1.1.1.63-{1,2} packages from + Matthias Klose . + * Stop adding a backwards compatibility link for egcs-nof on powerpc. + To my knowledge, nothing uses it. Do add the libstdc++ API change + link, though. + + -- Daniel Jacobowitz Mon, 8 Mar 1999 14:24:01 -0500 + +egcs (1.1.1.63-2) stable; urgency=low + + * Provide a libstdc++ with a shared object name, which is compatible + to other distributions. Documented the change in README.Debian, + the libstdc++-2.9.postinst and the libstdc++-dev-config script. + + -- Matthias Klose Fri, 12 Mar 1999 00:36:20 +0100 + +egcs (1.1.1.63-1.1) unstable; urgency=low + + * Non-Maintainer release. + * Build against glibc 2.1. + * Make egcs the primary compiler on i386. + * Also confilct with egcc (<< FIRST_PRIMARY) + if FIRST_PRIMARY is defined. + (this tells dpkg that gcc completely obsoletes egcc) + * Remove hjl-12 patch again, HJL says it should not be + necessary with egcs 1.1.2. + (as per forwarded reply from Christopher Chimelis) + * Apply libapi patch in clean target before regenerating debian/control + and remove the patch afterward. Otherwise, the libstdc++ and libg++ + package names are generated wrong on a glibc 2.1 system. + + -- Joel Klecker Tue, 9 Mar 1999 15:31:02 -0800 + +egcs (1.1.1.63-1) unstable; urgency=low + + * New upstream version egcs-1.1.1-pre3. + * Applied improved libstdc++ warning patch from Rob Browning. + + -- Matthias Klose Tue, 9 Mar 1999 16:14:07 +0100 + +egcs (1.1.1.62-1) unstable; urgency=low + + * New upstream version egcs-1.1.1-pre2. + * New upstream version libg++-2.8.1.3. + * Readded ARM support + * Readded hjl-12 per request from Christopher C Chimelis + + + -- Matthias Klose Fri, 26 Feb 1999 09:54:01 +0100 + +egcs-snapshot (19990224-0.1) experimental; urgency=low + + * New snapshot. + * Add the ability to disable CPPLIB by setting CPPLIB=no in + the environment. + * Disable gpc for powerpc; I spent a long time getting it to + make correctly, and then it goes and ICEs. + + -- Daniel Jacobowitz Tue, 24 Feb 1999 23:34:12 -0500 + +egcs (1.1.1.61-1) unstable; urgency=low + + * New upstream version egcs-1.1.1-pre1. + * debian/control.in: Applied patch from bug report #32987. + * Split up H.J.Lu's hjl-19990115-linux patch into several small + chunks: libapi, arm-mips, libgcc, hjl-other. The changelog.Linux + aren't included in the separate chunks. Please refer to the + unmodified hjl-19990115-linux patch file in the egcs source pkg. + * Apply warning patch to fix the annoying spew you get if you try to + use ropes or deques with -Wall (which makes -Wall mostly useless for + spotting errors in your own code). Fixes #32996. + * debian/rules: Unapply patches in the exact reverse order they were + applied. + + -- Matthias Klose Sat, 20 Feb 1999 22:06:21 +0100 + +egcs (1.1.1-5) frozen unstable; urgency=medium + + * Move libgcc.map file to g++ package, where gcc is the secondary + compiler (fixes #32329, #32605, #32631). + * Prepare to rename libstdc++2.9 package for glibc-2.1 (fixes #32148). + * Apply NMU patch for arm architecure (fixes #32367). + * Don't apply hjl-12 patch for alpha architectures (requested by the + alpha developers, Christopher C Chimelis ). + * Call makeinfo with --no-validate to fix obscure build failure on alpha. + * Build gpc info files in doc subdirectory. + * Remove c++filt diversion (C++ name demangling patch is now in binutils, + fixes #30820 and #32502). + + -- Matthias Klose Sun, 31 Jan 1999 23:19:35 +0100 + +egcs (1.1.1-4.1) unstable; urgency=low + + * Non-maintainer upload. + * Pascal doesn't build for ARM. + + -- Jim Pick Sun, 24 Jan 1999 16:13:34 -0800 + +egcs (1.1.1-4) frozen unstable; urgency=high + + * Don't strip compiler libraries libgcc.a libobjc.a libg2c.a libgpc.a + * Move Pascal examples to the right place (fixes #32149, part 1). + * Add dependencies for switching from secondary to primary compiler, + if FIRST_PRIMARY is defined (fixes #32149, part 2). + + -- Matthias Klose Wed, 20 Jan 1999 16:51:30 +0100 + +egcs (1.1.1-3) frozen unstable; urgency=low + + * Updated with the H.J.Lu's hjl-19990115-linux patch (fixes the + __register_frame_info problems, mips and arm port included). + * Update gpc to 19990118 (beta release candidate). + * Strip static libraries (fixes #31247 and #31248). + * Changed maintainer address. + + -- Matthias Klose Tue, 19 Jan 1999 16:34:28 +0100 + +egcs (1.1.1-2) frozen unstable; urgency=low + + * Moved egcs-docs, g77-doc and gpc-doc packages to doc section. + * Downgraded Recommends: egcs-docs to Suggests: egcs-docs dependencies + (for archs, where egcs is the primary compiler). + * Add 'Suggests: stl-manual' dependency to libstdc++2.9-dev. + * Applied one more alpha patch: + ftp://ftp.yggdrasil.com/private/hjl/egcs/1.1.1/egcs-1.1.1.diff.12.gz + * Applied PPro optimization patch. + * Apply emit-rtl-nan patch. + * Upgraded to libg++-2.8.1.2a-19981218.tar.gz. + * Upgraded to gpc-19981218. + * Make symlinks for gobjc, libstdc++2.9-dev and libg++2.8.2 doc directories. + + -- Matthias Klose Wed, 23 Dec 1998 18:04:53 +0200 + +egcs-snapshot (19981211-1) experimental; urgency=low + + * New snapshot. + * Adapted gpc to egcs-2.92.x (BOOT_CFLAGS must include -g). + * New libg++-2.8.1.2a-19981209.tar.gz. + * debian/rules: new target mail-summary. + + -- Matthias Klose Fri, 11 Dec 1998 18:14:53 +0200 + +egcs (1.1.1-1) frozen unstable; urgency=high + + * Final egcs-1.1.1 release. + * The last version depended on a versioned libc6 again. + * Add lost dependency for libg++ on libstdc++. + * Added debian-libstdc++.sh script to generate a libstdc++ on a Linux + system, which doesn't use the libapi patch. + + -- Matthias Klose Wed, 2 Dec 1998 12:06:15 +0200 + +egcs (1.1.0.91.59-2) frozen unstable; urgency=high + + * Fixes bugs from libc6 2.0.7u-6 upload without dependency line + Conflicts: libstdc++-2.9 (<< 2.91.59): #30019, #30066, #30078. + * debian/copyright: Updated URLs. + * gcc --help now mentions /usr/doc/debian/bug-reporting.txt. + * Install README.Debian and include information about patches applied. + * Depend on unversioned libc6 on i386, such that libstdc++2.9 can be used + on a hamm system. + + -- Matthias Klose Fri, 27 Nov 1998 18:32:02 +0200 + +egcs (1.1.0.91.59-1) frozen unstable; urgency=low + + * This is egcs-1.1.1 prerelease #3, compiled with libc6 2.0.7u-6. + * Added dependency for libstdc++2.9-dev on g++ (fixes #29631). + * Package g77 provides f77 (fixes #29817). + * Already fixed in earlier egcs-1.1 releases: #2493, #25271, #10620. + * Bugs reported for gcc-2.7.x and fixed in the egcs version of gcc: + #2493, #4430, #4954, #5367, #6047, #10612, #12375, #20606, #24788, #26100. + * Upgraded libg++ to libg++-2.8.1.2a-19981114. + * Upgraded gpc to gpc-19981124. + * Close #25869: egcs and splay maintainers are unable to reproduce this + bug with the current Debian packages. Bug submitter doesn't respond. + * Close #25407: egcs maintainer cannot reproduce this bug with the current + Debian compiler. Bug submitter doesn't respond. + * Use debhelper 1.2.7 for building. + * Replace the libstdc++ and libg++ compatibility links with fake libraries. + + -- Matthias Klose Wed, 25 Nov 1998 12:11:42 +0200 + +egcs (1.1.0.91.58-5) frozen unstable; urgency=low + + * Applied patch to build on the m68060. + * Added c++filt and c++filt.1 to the g++ package. + * Updated gpc to gpc-981105; fixes some regressions compared to egcs-1.1. + * Separated out g77 and gpc doumentation to new packages g77-doc and gpc-doc. + * Closed bugs (#22158). + * Close #20248; on platforms where gas and gld are the default versions, + it makes no difference to configure with or without enable-ld. + * Close #24349. The bugs are in the amulet source. + See http://www.cs.cmu.edu/afs/cs/project/amulet/www/FAQ.html#GCC28x + * Rename gcc.info* files to egcs.info* (fixes #24088). + * Documented known bugs (and workarounds) in BUGS.Debian. + * Fixed demangling of C++ names (fixes #28787). + * Applied patch form aspell to libstdc++/stl/stl_rope.h. + * Updated from cvs 16 Nov 1998. + + -- Matthias Klose Tue, 17 Nov 1998 09:41:24 +0200 + +egcs-snapshot (19981115-2) experimental; urgency=low + + * New snapshot. Disabled gpc. + * New packages g77-doc and gpc-doc. + + -- Matthias Klose Mon, 16 Nov 1998 12:48:09 +0200 + +egcs (1.1.0.91.58-3) frozen unstable; urgency=low + + * Previous version installed in potato, not slink. + * Updated from cvs 3 Nov 1998. + + -- Matthias Klose Tue, 3 Nov 1998 18:34:44 +0200 + +egcs (1.1.0.91.58-2) unstable; urgency=low + + * [debian/rules]: added targets to apply and unapply patches. + * [debian/README.patches]: New file. + * Moved patches dir to debian/patches. debian/rules has to select + the patches to apply. + * Manual pages for genclass and gcov (fixes #5995, #20950, #22196). + * Apply egcs-1.1-reload patch needed for powerpc architecture. + * Fixed bugs (#17768, #20252, #25508, #27788). + * Reapplied alpha patch (#20875). + * Fixes first part of #22513, extended README.Debian (combining C & C++). + * Already fixed in earlier egcs-1.1 releases: #17963, #20252, #20524, + #20640, #22450, #24244, #24288, #28520. + + -- Matthias Klose Fri, 30 Oct 1998 13:41:45 +0200 + +egcs (1.1.0.91.58-1) experimental; urgency=low + + * New upstream version. That's the egcs-1.1.1 prerelease plus patches from + the cvs archive upto 29 Oct 1998. + * Merged files from the egcs and snapshot packages. + * Updated libg++ to libg++-2.8.1.2 (although the Debian package name is still + 2.8.2). + * Moved patches dir to patches-1.1. + * Dan Jacobowitz: + * This is a snapshot from the egcs_1_1_branch, with + libapi, reload, builtin-apply, and egcs patches from + the debian/patches/ dir applied, along with the egcs-gpc-patches + and gcc/p/diffs/gcc-egcs-2.91.55.diff. + * Conditionalize gcj and chill (since they aren't in this branch). + * Fake snapshots drop the -snap-main. + + -- Matthias Klose Thu, 29 Oct 1998 15:15:19 +0200 + +egcs-snapshot (1.1-19981019-5.1) experimental; urgency=low + + * This is a snapshot from the egcs_1_1_branch, with + libapi, reload, builtin-apply, and egcs patches from + the debian/patches/ dir applied, along with the egcs-gpc-patches + and gcc/p/diffs/gcc-egcs-2.91.55.diff. + * Conditionalize gcj and chill (since they aren't in this + branch). + * Fake snapshots drop the -snap-main. + + -- Daniel Jacobowitz Mon, 19 Oct 1998 22:19:23 -0400 + +egcs (1.1b-5) unstable; urgency=low + + * [debian/control.in] Fixed typo in dependencies (#28076, #28087, #28092). + + -- J.H.M. Dassen (Ray) Sun, 18 Oct 1998 22:56:51 +0200 + +egcs (1.1b-4) unstable; urgency=low + + * Strengthened g++ dependency on libstdc++_LIB_SO_-dev from + `Recommends' to `Depends'. + * Updated README.Debian for egcs-1.1. + * Updated TODO. + + -- Matthias Klose Thu, 15 Oct 1998 12:38:47 +0200 + +egcs-snapshot (19981005-0.1) experimental; urgency=low + + * Make libstdc++2.9-snap-main and libg++-snap-main provide + their mainstream equivalents and put those equivalents into + their shlibs file. + * Package gcj, the GNU Compiler for Java(TM). + + * New upstream version of egcs (The -regcs_latest_snapshot branch). + * Build without libg++ entirely. + * Leave out gpc for now - the internals are sufficiently different + that it does not trivially compile. + * Include an experimental reload patch for powerpc - this is, + in the words of its author, not release quality, but it allows + powerpc linuxthreads to function. + * On architectures where we are the primary compiler, let snapshots + build with --prefix=/usr and conflict with the stable versions. + * Package chill, a front end for the language Chill. + * Other applied patches from debian/patches/: egcs-patches and + builtin-apply-patch. + * Use reload.c revision 1.43 to avoid a nasty bug. + + -- Daniel Jacobowitz Wed, 7 Oct 1998 00:27:42 -0400 + +egcs (1.1b-3.1) unstable; urgency=low + + * NMU to fix the egcc -> gcc link once and for all + + -- Christopher C. Chimelis Tue, 22 Sep 1998 16:11:19 -0500 + +egcs (1.1b-3) unstable; urgency=low + + * Oops. The egcc -> gcc link on archs where gcc is egcc was broken. + Thanks to Chris Chimelis for pointing this out. + + -- J.H.M. Dassen (Ray) Mon, 21 Sep 1998 20:51:35 +0200 + +egcs (1.1b-2) unstable; urgency=low + + * New upstream spellfix release (Debian revision is 2 as the internal + version numbers didn't change). + * Added egcc -> gcc symlink on architectures where egcc is the primary C + compiler. Thus, maintainers of packages that require egcc, can now + simply use "egcc" without conditionals. + * Porters: we hope/plan to make egcs's gcc the default C compiler on all + platforms once the 2.2.x kernels are available. Please test this version + thoroughly, and give us a GO / NO GO for your architecture. + * Some symbols cpp used to predefine were removed upstream in order to clean + up the cpp namespace, but imake requires them for determining the proper + settings for LinuxMachineDefines (see /usr/X11R6/lib/X11/{Imake,linux}.cf), + thus we put them back. Thanks to Paul Slootman for reporting his imake + problems on Alpha. + * [gcc/config/alpha/linux.h] Added -D__alpha to CPP_PREDEFINES . + Thanks to Chris Chimelis for the alpha-only 1.1a-1.1 NMU which fixed + this already. + * [gcc/config/i386/linux.h] Added -D__i386__ to CPP_PREDEFINES . + * [gcc/config/sparc/linux.h] Has -Dsparc in CPP_PREDEFINES . + * [gcc/config/sparc/linux64.h] Has -Dsparc in CPP_PREDEFINES . + * [gcc/config/m68k/linux.h] Has -Dmc68000 in CPP_PREDEFINES . + * [gcc/config/rs6000/linux.h] Has -Dpowerpc in CPP_PREDEFINES . + * [gcc/config/arm/linux.h] Has -Darm in CPP_PREDEFINES . + * [gcc/config/i386/gnu.h] Has -Di386 in CPP_PREDEFINES . + * Small fixes and updates in README. + * Changes affecting the source package only: + * [gcc/Makefile.in, gcc/cp/Make-lang.in, gcc/p/Make-lang.in] + Daniel Jacobowitz: Ugly hacks of various kinds to make cplib2.txt get + properly regenerated with multilib. + * [debian/TODO] Created. + * [INSTALL/index.html] Fixed broken link. + + -- J.H.M. Dassen (Ray) Sun, 20 Sep 1998 14:05:15 +0200 + +egcs (1.1a-1) unstable; urgency=low + + * New upstream release. + * Added README.libstdc++ . + * Updated Standards-Version. + * Matthias: + * Downgraded gobjc dependency on egcs-docs from Recommends: to Suggests: . + * [libg++/Makefile.in] Patched not to rely on a `-f' flag of `ln'. + + -- J.H.M. Dassen (Ray) Wed, 2 Sep 1998 19:57:43 +0200 + +egcs (1.1-1) unstable; urgency=low + + * egcs-1.1 prerelease (from the last Debian package only the version file + changed). + * "Final" gpc Beta 2.1 gpc-19980830. + * Included libg++ and gpc in the .orig tarball. so that diffs are getting + smaller. + * debian/control.in: Changed maintainer address to galenh-egcs@debian.org. + * debian/copyright: Updated URLs. + + -- Matthias Klose Mon, 31 Aug 1998 12:43:13 +0200 + +egcs (1.0.99.56-0.1) unstable; urgency=low + + * New upstream snapshot 19980830 from CVS (called egcs-1.1 19980830). + * New libg++ snapshot 980828. + * Put all patches patches subdirectory; see patches/README in the source. + * debian/control.in: readded for libg++2.8.2-dev: + Replaces: libstdc++2.8-dev (<= 2.90.29-0.5) + * Renamed libg++2.9 package to libg++2.8.2. + * gcc/p/gpc-decl.c: Fix from Peter@Gerwinski.de; fixes optimization errors. + * patches/gpc-patch2: Fix from Peter@Gerwinski.de; fixes alpha errors. + * debian/rules: New configuration flag for building with and without + libstdc++api patch; untested without ... + + -- Matthias Klose Sun, 30 Aug 1998 12:04:22 +0200 + +egcs (1.0.99-0.6) unstable; urgency=low + + * PowerPC fixes. + * On powerpc, generate the -msoft-float libs and package them + as egcs-nof. + * Fix signed char error in gpc. + * Create a libg++.so.2.9 compatibility symlink. + + -- Daniel Jacobowitz Tue, 25 Aug 1998 11:44:09 -0400 + +egcs (1.0.99-0.5) unstable; urgency=low + + * New upstream snapshot 19980824. + * New gpc snapshot gpc-980822; reenabled gpc for alpha. + + -- Matthias Klose Tue, 25 Aug 1998 01:21:08 +0200 + +egcs (1.0.99-0.4) unstable; urgency=low + + * New upstream snapshot 19980819. Should build glibc 2.0.9x on PPC. + + -- Matthias Klose Wed, 19 Aug 1998 14:18:07 +0200 + +egcs (1.0.99-0.3) unstable; urgency=low + + * New upstream snapshot 19980816. + * debian/rules: build correct debian/control and debian/*.shlibs + * Enabled Haifa scheduler for ix86. + + -- Matthias Klose Mon, 17 Aug 1998 16:29:35 +0200 + +egcs (1.0.99-0.2) unstable; urgency=low + + * New upstream snapshot: egcs-19980812, minor changes only. + * Fixes for building on `primary' targets. + * Disabled gpc on `alpha' architecture. + * Uses debhelper 1.1.6 + * debian/control.in: Replace older snapshot versions in favor of newer + normal versions. + * debian/rules: Fixes building of binary-arch target only. + + -- Matthias Klose Thu, 13 Aug 1998 11:59:41 +0200 + +egcs (1.0.99-0.1) unstable; urgency=low + + * New upstream version: pre egcs-1.1 version. + * Many changes ... for details see debian/changelog.snapshot in the + source package. + * New packages libstdc++2.9 and libstdc++2.9-dev. + * New libg++ snapshot 980731: new packages libg++2.9 and libg++2.9-dev. + * New gpc snapshot gpc-980729: new package gpc. + * Uses debhelper 1.1 + + -- Matthias Klose Mon, 10 Aug 1998 13:00:27 +0200 + +egcs-snapshot (19980803-4) experimental; urgency=low + + * rebuilt debian/control. + + -- Matthias Klose Wed, 5 Aug 1998 08:51:47 +0200 + +egcs-snapshot (19980803-3) experimental; urgency=low + + * debian/rules: fix installation locations of NEWS, header and + `undocumented' files. + * man pages aren't compressed for the snapshot package. + + -- Matthias Klose Tue, 4 Aug 1998 17:34:31 +0200 + +egcs-snapshot (19980803-2) experimental; urgency=low + + * debian/rules: Uses debhelper. Old in debian/rules.old. + renamed postinst, prerm files for use with debhelper. + * debian/{libg++2.9,libstdc++2.9}/postinst: call ldconfig only, + when called for configure. + * egcs-docs is architecture independent package. + * new libg++ snapshot 980731. + * installed libstdc++ api patch (still buggy). + + -- Matthias Klose Mon, 3 Aug 1998 13:20:59 +0200 + +egcs-snapshot (19980729-1) experimental; urgency=low + + * New snapshot version 19980729 from CVS archive. + * New gpc snapshot gpc-980729. + * Let gcc/configure decide about using the Haifa scheduler. + * Remove -DDEBIAN. That was needed for the security improvements with + regard to the /tmp problem. egcs-1.1 chooses another approach. + * Save test-protocol and extract gpc errors to gpc-test-summary. + * Tighten binutils dependency to 2.9.1. + * debian/rules: new build-info target + * debian/{control.in,rules}: _SO_ and BINUTILSV substitution. + * debian/rules: add dependency for debian/control. + * debian/rules: remove bin/c++filt + * TODO: next version will use debhelper; the unorganized moving of + files becomes unmanageable ... + * TODO: g++ headers in stdc++ package? check! + + -- Matthias Klose Thu, 30 Jul 1998 12:10:20 +0200 + +egcs-snapshot (19980721-1) experimental; urgency=low + + * Unreleased. Infinite loops in executables made by gpc. + + -- Matthias Klose Wed, 22 Jul 1998 18:07:20 +0200 + +egcs-snapshot (19980715-1) experimental; urgency=low + + * New snapshot version from CVS archive. + * New gpc snapshot gpc-980715. + * New libg++ version libg++-2.8.2-980708. Changed versioning + schema for library. The major versions of libc, libstdc++ and the + g++ interface are coded in the library name. Use this new schema, + but provide a symlink to our previous schema, since the library + seems to be binary compatible. + * [debian/rules]: Fixed bug in build target, when bootstrap returns + with an error + + -- Matthias Klose Wed, 15 Jul 1998 10:55:05 +0200 + +egcs-snapshot (19980701-1) experimental; urgency=low + + * New snapshot version from CVS archive. + Two check programs in libg++ had to be manually killed to finish the + testsuite (tBag and tSet). + * New gpc snapshot gpc-980629. + * Incorporated debian/rules changes from egcs-1.0.3a-0.5 (but don't remove + gcc/cp/parse.c gcc/c-parse.c gcc/c-parse.y gcc/objc/objc-parse.c + gcc/objc/objc-parse.y, since these files are part of the release). + * Disable the -DMKTEMP_EACH_FILE -DHAVE_MKSTEMP -DDEBIAN flags for the + snapshot. egcs-1.1 will have another solution. + * Don't bootstrap the snapshot with -fno-force-mem. Internal compiler + error :-( + * libf2c.a and f2c.h have changed names to libg2c.a and g2c.h and + have moved again into the gcc-lib dir. They are installed under + libg2c.a and g2c.h. Is it necessary to provide links f2c -> g2c ? + * debian/rules: reflect change of build dir of libraries. + + -- Matthias Klose Wed, 2 Jul 1998 13:15:28 +0200 + +egcs-snapshot (19980628-0.1) experimental; urgency=low + + * New upstream snapshot version. + * Non-maintainer upload; Matthias appears to be absent currently. + * Updated shlibs. + * Merged changes from regular egcs: + * [debian/control] Tightened dependency on binutils to 2.8.1.0.23 or + newer, as according to INSTALL/SPECIFIC PowerPC (and possibly Sparc) + need this. + * [debian/rules] Clean up some generated files outside builddir, + so the .diff.gz becomes smaller. + * [debian/rules] Partial sync/update with the one for the regular egcs + version. + * [debian/rules] Make gcc/p/configure executable. + + -- J.H.M. Dassen (Ray) Wed, 1 Jul 1998 07:12:15 +0200 + +egcs (1.0.3a-0.6) frozen unstable; urgency=low + + * Some libg++ development files were in libstdc++2.8-dev rather than + libg++2.8-dev. Fixed this and dealt with upgrading from the earlier + versions (fixes #23908; this bug is not marked release-critical, but + is annoying and can be quite confusing for users. Therefore, I think + this fix should go in 2.0). + + -- J.H.M. Dassen (Ray) Tue, 30 Jun 1998 11:10:14 +0200 + +egcs (1.0.3a-0.5) frozen unstable; urgency=low + + * Fixed location of .hP files (Fixes #23448). + * [debian/rules] simplified extraction of the files for libg++2.8-dev. + + -- J.H.M. Dassen (Ray) Wed, 17 Jun 1998 09:33:41 +0200 + +egcs (1.0.3a-0.4) frozen unstable; urgency=low + + * [gcc/gcc.c] There is one call to choose_temp_base for determining the + tempdir to be used only; #ifdef HAVE_MKSTEMP delete the tempfile created + as a side effect. (fixes #23123 for egcs). + * [gcc/collect2.c] There's still a vulnerability here; I don't see how + I can fix it without leaving behind tempfiles though. + * [debian/control] Tightened dependency on binutils to 2.8.1.0.23 or + newer, as according to INSTALL/SPECIFIC PowerPC (and possibly Sparc) + need this. + * [debian/rules] Clean up some generated files outside builddir, so the + .diff.gz becomes smaller. + + -- J.H.M. Dassen (Ray) Sat, 13 Jun 1998 09:06:52 +0200 + +egcs-snapshot (19980608-1) experimental; urgency=low + + * New snapshot version. + + -- Matthias Klose Tue, 9 Jun 1998 14:07:44 +0200 + +egcs (1.0.3a-0.3) frozen unstable; urgency=high (security fixes) + + * [gcc/toplev.c] set flag_force_mem to 1 at optimisation level 3 or higher. + This works around #17768 which is considered release-critical. + * Changes by Matthias: + * [debian/README] Documentation of the compiler situation for Objective C. + * [debian/rules, debian/control.*] Generate control file from a master + file. + * [debian/rules] Updates for Pascal and Fortran parts; brings it in sync + with the one for the egcs snapshots. + * Use the recommended settings LDFLAGS=-s CFLAGS= BOOT_CFLAGS='-O2'. + * Really compile -DMKTEMP_EACH_FILE -DHAVE_MKSTEMP (really fixes #19453 + for egcs). + * [gcc/gcc.c] A couple of temp files weren't marked for deletion. + + -- J.H.M. Dassen (Ray) Sun, 31 May 1998 22:56:22 +0200 + +egcs (1.0.3a-0.2) frozen unstable; urgency=high (security fixes) + + * Security improvements with regard to the /tmp problem + (gcc opens predictably named files in TMPDIR which can be abused via + symlinks) (Fixes #19453 for egcs). + * Compile -DMKTEMP_EACH_FILE to ensure the %u name is generated randomly + every time; affects gcc/gcc.c . + * [gcc/choose-temp.c, libiberty/choose-temp.c]: use mktemp(3) if compiled + -DUSE_MKSTEMP . + * Security improvements: don't use the result of choose_temp_base in a + predictable fashion. + [gcc/gcc.c]: + * @c, @objective-c: use random name rather then tempbasename.i for + intermediate preprocessor output (%g.i -> %d%u). + * @c, @objective-c: use random name rather then tempbasename.s for + intermediate compiler output (%g.s -> %d%u). + * @c, @objective-c, @cpp-output, @assembler-with-cpp: switched + "as [-o output file] " to + "as [-o output file]". + * @c, @objective-c, @assembler-with-cpp: use previous random name + (cc1|cpp output) rather then tempbasename.s for intermediate assembler + input (%g.s -> %U) + [gcc/f/lang-specs.h]: + * @f77-cpp-input: use random name rather then tempbasename.i for + intermediate cpp output (%g.i -> %d%u). + * @f77-cpp-input: use previous random name (cpp output) rather than + tempbasename.i for f771 input (%g.i -> %U). + * @f77-cpp-input: switched + "as [-o output file] " to + "as [-o output file]". + * @f77-cpp-input: use random name rather then tempbasename.s for + intermediate compiler output (%g.s -> %d%u). + * @ratfor: use random name rather then tempbasename.i for + intermediate ratfor output (%g.f -> %d%u). + * @ratfor: use previous random name (ratfor output) rather than + tempbasename.i for f771 input (%g.f -> %U). + * @ratfor: use random name rather then tempbasename.s for + intermediate compiler output (%g.s -> %d%u). + * @ratfor: switched + "as [-o output file] " to + "as [-o output file]". + * @ratfor: use previous random name + (ratfor output) rather then tempbasename.s for intermediate assembler + input (%g.s -> %U). + * @f77: use random name rather then tempbasename.s for + intermediate ratfor output (%g.f -> %d%u). + * @ratfor: use previous random name (ratfor output) rather than + tempbasename.i for f771 input (%g.f -> %U). + * @ratfor: use random name rather then tempbasename.s for + intermediate compiler output (%g.s -> %d%u). + * @ratfor: switched + "as [-o output file] " to + "as [-o output file]". + * @ratfor: use previous random name + (ratfor output) rather then tempbasename.s for intermediate assembler + input (%g.s -> %U). + * @f77: use random name rather then tempbasename.s for + intermediate compiler output (%g.s -> %d%u). + * @f77: switched + "as [-o output file] " to + "as [-o output file]". + * @ratfor: use random name rather then tempbasename.s for + intermediate compiler output (%g.s -> %U). + * Run the testsuite (this requires the dejagnu package in experimental; + unfortunately, it is difficult to distinguish this version from the one + in frozen). + if possible, and log the results in warn_summary and bootstrap-summary. + * [gcc/choose-temp.c, libiberty/choose-temp.c]: s|returh|return| in + comment. + * Added notes on the Debian compiler setup [debian/README] to the + development packages. + * Matthias: + * [libg++/etc/lf/Makefile.in] Replaced "-ltermcap" by "-lncurses". + * [debian/rules] Updated so it can be used for both egcs releases and + snapshots easily; added support for the GNU Pascal Compiler gpc. + * [contrib/test_summary, contrib/warn_summary] Added from CVS. + * Run compiler checks and include results in /usr/doc/. + * Updates to the README. + * [debian/rules] Use assignments to speed up startup. + * [debian/rules] Show the important variables at the start of the build + process. + * [debian/control.secondary] Added a dependency of gobjc on egcc on + architectures where egcs provides the secondary compiler, as + /usr/bin/egcc is the compiler driver for gobjc. (Fixes #22829). + * [debian/control.*] Bumped Standards-Version; used shorter version + numbers in the dependency relationships (esthetic difference only); + fixed typo. + + -- J.H.M. Dassen (Ray) Tue, 26 May 1998 21:47:41 +0200 + +egcs-snapshot (19980525-1) experimental; urgency=low + + * New snapshot version. + + -- Matthias Klose Tue, 26 May 1998 18:04:06 +0200 + +egcs-snapshot (19980517-1) experimental; urgency=low + + * "Initial" release of the egcs-snapshot package; many debian/* files + derived from the egcs-1.0.3a-0.1 package (maintained by Galen Hazelwood + , NMU's by J.H.M. Dassen (Ray) ) + * The egcs-snapshot packages can coexist with the packages of the + egcs release. Package names have a '-ss' appended. + * All packages are installed in a separate tree (/usr/lib/egcs-ss following + the FHSS). + * Made all snapshot packages extra, all snapshot packages conflict + with correspondent egcs packages, which are newer than the snapshot. + * Included libg++-2.8.1-980505. + * Included GNU Pascal (gpc-980511). + * Haifa scheduler enabled for all snapshot packages. + * Run compiler checks and include results in /usr/doc/. + * Further information in /usr/doc//README.snapshot. + + -- Matthias Klose Wed, 20 May 1998 11:14:06 +0200 + +egcs (1.0.3a-0.1) frozen unstable; urgency=low + + * New upstream release egcs-2.90.29 980515 (egcs-1.0.3 release) + (we were using 1.0.3-prerelease). This includes the Haifa patches + we had since 1.0.3-0.2 and the gcc/objc/thr-posix.c patch we had + since 1.0.3-0.1; the differences with 1.0.3-prerelease + patches + we had is negligable. + * iostream info documentation was in the wrong package (libg++2.8-dev). + Now it's in libstdc++2.8-dev. (Thanks to Jens Rosenboom for bringing + this to my attention). As 1.0.3-0.3 didn't make it out of Incoming, + I'm not adding "Replaces:" for this; folks who had 1.0.3-0.3 installed + already know enough to use --force-overwrite. + * [gcc/objc/objc-act.c] Applied patch Matthias Klose supplied me with that + demangles Objective C method names in gcc error messages. + * Explicitly disable Haifa scheduling on Alpha, to make it easier to use + this package's diff with egcs snapshots, which may turn on Haifa + scheduling even though it is still unstable. (Requested by Chris Chimelis) + * Don't run "configure" again if builddir already exists (makes it faster + to restart builds in case one is hacking internals). Requested by + Johnnie Ingram. + * [gcc/gbl-ctors.h] Don't use extern declaration for atexit on glibc 2.1 + and higher (the prototype has probably changed; having the declaration + broke Sparc compiles). + * [debian/rules] Determine all version number automatically (from the + version string in gcc/version.c). + * [debian/copyright] Updated FTP locations; added text about libg++ (fixes + #22465). + + -- J.H.M. Dassen (Ray) Sat, 16 May 1998 17:41:44 +0200 + +egcs (1.0.3-0.3) frozen unstable; urgency=low + + * Made an "egcs-doc" package containing documentation for egcs (e)gcc, + g++, gobjc, so that administrators can choose whether to have this + documenation or the documentation that comes with the GNU gcc package. + Dependency on this is Recommends: on architectures where egcs provides + the primary C compiler; Suggests: on the others (where GNU gcc is still + the primary C compiler). + * Use the g++ FAQ from gcc/cp rather than libg++, as that version is more + up to date. + * Added iostream info documentation to libstdc++2.8-dev. + + -- J.H.M. Dassen (Ray) Wed, 13 May 1998 08:46:10 +0200 + +egcs (1.0.3-0.2) frozen unstable; urgency=low + + * Added libg++ that works with egcs, found at + ftp://ftp.yggdrasil.com/private/hjl/libg++-2.8.1-980505.tar.gz + (fixes #20587 (Severity: important)). + * The "libg++" and "libg++-dev" virtual packages now refer to the GNU + extensions. + * Added the g++ FAQ that comes with libg++ to the g++ package. + * libg++/Makefile.in: added $(srcdir) to rule for g++FAQ.info so that it + builds OK in builddir. + * Added -D__i386__ to the cpp predefines on intel. + * Patches Matthias supplied me with: + * Further 1.0.3 prerelease patches from CVS. + This includes patches to the Haifa scheduler. Alpha porters, please + check if this makes the Haifa scheduler OK again. + * Objective C patches from CVS. + + -- J.H.M. Dassen (Ray) Fri, 8 May 1998 14:43:20 +0200 + +egcs (1.0.3-0.1) frozen unstable; urgency=low (high for maintainers that use objc) + + * bug fixes only in new upstream version + * Applied patches from egcs CVS archive (egcs_1_03_prerelease) + (see gcc/ChangeLog in the egcs source package). + * libstdc++2.8-dev no longer Provides: libg++-dev (fixes #21153). + * libstdc++2.8-dev now Conflicts: libg++27-dev (bo), + libg++272-dev (hamm) [regular packages] rather than + Conflicts: libg++-dev [virtual package] to prepare the way for "libg++" + to be used as a virtual package for a new libg++ package (i.e. an up to + date one, which not longer contains libstdc++, but only the GNU + extensions) that is compatible with the egcs g++ packages. Such a package + isn't available yet. Joel Klecker tried building libg++2.8.1.1a within + egcs's libstdc++ setup, but it appears to need true gcc 2.8.1 . + * Filed Severity: important bugs against wxxt1-dev (#21707) because these + still depend on libg++-dev, which is removed in this version. + A fixed libsidplay1-dev has already been uploaded. + * libstdc++2.8 is now Section: base and Priority: required (as dselect is + linked against it). + * Disabled Haifa scheduling on Alpha again; Chris Chimelis reported + that this caused problems on some machines. + * [gcc/extend.texi] + ftp://maya.idiap.ch/pub/tmb/usenix88-lexic.ps.Z is no longer available; + use http://master.debian.org/~karlheg/Usenix88-lexic.pdf . + (fixes the egcs part of #20002). + * Updated Standards-Version. + * Changed chmod in debian/rules at Johnie Ingram's request. + * Rather than hardwire the Debian part of the packages' version number, + extract it from debian/changelog . + * Use gcc/objc/thr-posix.c from 980418 egcs snapshot to make objc work. + (Fixes #21192). + * Applied workaround for the GNUstep packages on sparc systems. + See README.sparc (on sparc packages only) in the doc directory. + This affects the other compilers as well. + * Already done in 1.0.2-0.7: the gobjc package now provides a virtual + package objc-compiler. + + -- J.H.M. Dassen (Ray) Tue, 28 Apr 1998 12:05:28 +0200 + +egcs (1.0.2-0.7) frozen unstable; urgency=low + + * Separated out Objective-C compiler. + * Applied patch from http://www.cygnus.com/ml/egcs/1998-Apr/0614.html + + -- Matthias Klose Fri, 17 Apr 1998 10:25:48 +0200 + +egcs (1.0.2-0.6) frozen unstable; urgency=low + + * Due to upstream changes (libg++ is now only the GNU specific C++ + classes, and is no longer maintained; libstdc++ contains the C++ + standard library, including STL), the virtual "libg++-dev" + package's meaning has become confusing. Therefore, new or updated + packages should no longer use the virtual "libg++-dev" package. + * Corrected g++'s Recommends to libstdc++2.8-dev (>=2.90.27-0.1). + The previous version had Recommends: libstdc++-dev (>=2.90.27-0.1) + which doesn't work, as libstc++-dev is a virtual package. + * Bumped Standards-Version. + + -- J.H.M. Dassen (Ray) Tue, 14 Apr 1998 11:52:08 +0200 + +egcs (1.0.2-0.5) frozen unstable; urgency=low (high for maintainers of packages that use libstdc++) + + * Modified shlibs file for libstdc++ to generate versioned dependencies, + as it is not link compatible with the 1.0.1-x versions in + project/experimental. (Fixes #20247, #20033) + Packages depending on libstd++ should be recompiled to fix their + dependencies. + * Strenghtened g++'s Recommends: libstdc++-dev to the 1.0.2 version or + newer. + * Fixed problems with the unknown(7) symlink for gcov. + * Reordering links now works. + + -- Adam Heath Sun, 12 Apr 1998 13:09:30 -0400 + +egcs (1.0.2-0.4) frozen unstable; urgency=low + + * Unreleased. This is the version Adam Heath received from me. + * Replaces: gcc (<= 2.7.2.3-3) so that the overlap with the older gcc + packages (including bo's gcc_2.7.2.1-8) is handled properly + (fixes #19931, #19672, #20217, #20593). + * Alpha architecture (fixes #20875): + * Patched gcc/config/alpha/linux.h for the gmon functions to operate + properly. + * Made egcs the primary C compiler. + * Enabled Hafia scheduling. + * Lintian-detected problems: + * E: libstdc++2.8: ldconfig-symlink-before-shlib-in-deb usr/lib/libstdc++.so.2.8 + * E: egcc: binary-without-manpage gcov + Reported as wishlist bug; added link to undocumented(7). + * W: libstdc++2.8: non-standard-executable-perm usr/lib/libstdc++.so.2.8.0 0555 + * E: libstdc++2.8: shlib-with-executable-bit usr/lib/libstdc++.so.2.8.0 0555 + + -- J.H.M. Dassen (Ray) Fri, 10 Apr 1998 14:46:46 +0200 + +egcs (1.0.2-0.3) frozen unstable; urgency=low + + * Really fixed dependencies. + + -- J.H.M. Dassen (Ray) Mon, 30 Mar 1998 11:30:26 +0200 + +egcs (1.0.2-0.2) frozen unstable; urgency=low + + * Fixed dependencies. + + -- J.H.M. Dassen (Ray) Sat, 28 Mar 1998 13:58:58 +0100 + +egcs (1.0.2-0.1) frozen unstable; urgency=low + + * New upstream version; it now has -Di386 in CPP_PREDEFINES. + * Only used the debian/* patches from 1.0.1-2; the rest of it appears + to be in 1.0.2 already. + + -- J.H.M. Dassen (Ray) Fri, 27 Mar 1998 11:47:14 +0100 + +egcs (1.0.1-2) unstable; urgency=low + + * Integrated pre-release 1.0.2 patches + * Split out g++ + * egcs may now provide either the primary or secondary C compiler + + -- Galen Hazelwood Sat, 14 Mar 1998 14:15:32 -0700 + +egcs (1.0.1-1) unstable; urgency=low + + * New upstream version + * egcs is now the standard Debian gcc! + * gcc now provides c-compiler (#15248 et al.) + * g77 now provides fortran77-compiler + * g77 dependencies now correct (#16991) + * /usr/doc/gcc/changelog.gz now has correct permissions (#16139) + + -- Galen Hazelwood Sat, 7 Feb 1998 19:22:30 -0700 + +egcs (1.0-1) experimental; urgency=low + + * First official release + + -- Galen Hazelwood Thu, 4 Dec 1997 16:30:11 -0700 + +egcs (970917-1) experimental; urgency=low + + * New upstream snapshot (There's a lot of stuff here as well, including + a new libstdc++, but it _still_ won't build...) + * eg77 driver now works properly + + -- Galen Hazelwood Wed, 17 Sep 1997 20:44:29 -0600 + +egcs (970904-1) experimental; urgency=low + + * New upstream snapshot + + -- Galen Hazelwood Sun, 7 Sep 1997 18:25:06 -0600 + +egcs (ss-970814-1) experimental; urgency=low + + * Initial packaging (of initial snapshot!) + + -- Galen Hazelwood Wed, 20 Aug 1997 00:36:28 +0000 + +gcc272 (2.7.2.3-12) unstable; urgency=low + + * Compiled on a glibc-2.0 based system. + * Reflect move of manpage to /usr/share in gcc.postinst as well. + * Moved gcc272-docs to section doc, priority optional. + + -- Matthias Klose Sat, 28 Aug 1999 13:42:13 +0200 + +gcc272 (2.7.2.3-11) unstable; urgency=low + + * Follow Debian policy for GNU system type (fixes #42657). + * config/i386/linux.h: Remove %[cpp_cpu] from CPP_SPEC. Stops gcc-2.95 + complaining about obsolete spec operators (using gcc -V 2.7.2.3). + Patch suggested by Zack Weinberg . + + -- Matthias Klose Sun, 15 Aug 1999 20:12:21 +0200 + +gcc272 (2.7.2.3-10) unstable; urgency=low + + * Renamed source package to gcc272. The egcs source package is renamed + to gcc, because it's now the "official" GNU C compiler. + * Changed maintainer address to "Debian GCC maintainers". + * Install info and man stuff to /usr/share. + + -- Matthias Klose Thu, 27 May 1999 12:29:23 +0200 + +gcc (2.7.2.3-9) unstable; urgency=low + + * debian/{postinst,prerm}-doc: handle gcc272.info, not gcc.info. + Fixes #36306. + + -- Matthias Klose Tue, 20 Apr 1999 07:32:58 +0200 + +gcc (2.7.2.3-8) unstable; urgency=low + + * Make gcc-2.7 the secondary compiler. Rename gcc package to gcc272. + On i386, sparc and m68k, this package is compiled against glibc2.0. + * The cpp package is built from the egcs source package. + + -- Matthias Klose Mon, 29 Mar 1999 22:48:50 +0200 + +gcc (2.7.2.3-7) frozen unstable; urgency=low + + * Separated out ObjC compiler to gobjc27 package. + * Changed maintainer address. + * Synchronized README.Debian with egcs-1.1.1-3. + + -- Matthias Klose Tue, 29 Dec 1998 19:05:26 +0100 + +gcc (2.7.2.3-6) frozen unstable; urgency=low + + * Link with -lc on i386, m68k, sparc, when building shared libraries + (fixes #25122). + + -- Matthias Klose Thu, 3 Dec 1998 12:12:12 +0200 + +gcc (2.7.2.3-5) frozen unstable; urgency=low + + * Updated maintainer info. + * Updated Standards-Version; made lintian-clean. + * gcc-docs can coexist with the latest egcs-docs, so added (<= version) to + the Conflicts. + * Updated the README and renamed it to README.Debian . + * Put a reference to /usr/doc/gcc/README.Debian in the info docs. + * Updated description of g++272 . + * Clean up generated info files, to keep the diff small. + + -- J.H.M. Dassen (Ray) Tue, 17 Nov 1998 20:05:59 +0100 + +gcc (2.7.2.3-4.8) frozen unstable; urgency=high + + * Non-maintainer release + * Fix type in extended description + * Removed wrong test in postinst + * Add preinst to clean up some stuff from an older gcc package properly + and stop man complaining about dangling symlinks + + -- Wichert Akkerman Fri, 17 Jul 1998 18:48:32 +0200 + +gcc (2.7.2.3-4.7) frozen unstable; urgency=high + + * Really fixed gcc-docs postinst (Fixes #23470), so that `gcc-docs' + becomes installable. + + -- J.H.M. Dassen (Ray) Mon, 15 Jun 1998 07:53:40 +0200 + +gcc (2.7.2.3-4.6) frozen unstable; urgency=high + + * [gcc.c] There is one call to choose_temp_base for determining the + tempdir to be used only; + #ifdef HAVE_MKSTEMP delete the tempfile created as a side effect. + (fixes #23123 for gcc). + * gcc-docs postinst was broken (due to a broken line) (fixes #23391, #23401). + * [debian/control] description for gcc-docs said `egcs' where it should have + said `gcc' (fixes #23396). + + -- J.H.M. Dassen (Ray) Thu, 11 Jun 1998 12:48:50 +0200 + +gcc (2.7.2.3-4.5) frozen unstable; urgency=high + + * The previous version left temporary files behind, as they were not + marked for deletion afterwards. + + -- J.H.M. Dassen (Ray) Sun, 31 May 1998 22:49:14 +0200 + +gcc (2.7.2.3-4.4) frozen unstable; urgency=high (security fixes) + + * Security improvements with regard to the /tmp problem + (gcc opens predictably named files in TMPDIR which can be abused via + symlinks) (Fixes #19453 for gcc): + * Compile -DMKTEMP_EACH_FILE to ensure the %u name is generated randomly + every time; affects gcc/gcc.c . + * [cp/g++.c, collect2.c, gcc.c] If compiled -DHAVE_MKSTEMP use mkstemp(3) + rather than mktemp(3). + * Security improvements: don't use the result of choose_temp_base in a + predictable fashion. + [gcc.c]: + * @c, @objective-c: use random name rather then tempbasename.i for + intermediate preprocessor output (%g.i -> %d%u). + * @c, @objective-c: use random name rather then tempbasename.s for + intermediate compiler output (%g.s -> %d%u). + * @c, @objective-c, @cpp-output, @assembler-with-cpp: switched + "as [-o output file] " to + "as [-o output file]". + * @c, @objective-c, @assembler-with-cpp: use previous random name + (cc1|cpp output) rather then tempbasename.s for intermediate assembler + input (%g.s -> %U) + [f/lang-specs.h]: + * @f77-cpp-input: use random name rather then tempbasename.i for + intermediate cpp output (%g.i -> %d%u). + * @f77-cpp-input: use previous random name (cpp output) rather than + tempbasename.i for f771 input (%g.i -> %U). + * @f77-cpp-input: switched + "as [-o output file] " to + "as [-o output file]". + * @f77-cpp-input: use random name rather then tempbasename.s for + intermediate compiler output (%g.s -> %d%u). + * @ratfor: use random name rather then tempbasename.i for + intermediate ratfor output (%g.f -> %d%u). + * @ratfor: use previous random name (ratfor output) rather than + tempbasename.i for f771 input (%g.f -> %U). + * @ratfor: use random name rather then tempbasename.s for + intermediate compiler output (%g.s -> %d%u). + * @ratfor: switched + "as [-o output file] " to + "as [-o output file]". + * @ratfor: use previous random name + (ratfor output) rather then tempbasename.s for intermediate assembler + input (%g.s -> %U). + * @f77: use random name rather then tempbasename.s for + intermediate ratfor output (%g.f -> %d%u). + * @ratfor: use previous random name (ratfor output) rather than + tempbasename.i for f771 input (%g.f -> %U). + * @ratfor: use random name rather then tempbasename.s for + intermediate compiler output (%g.s -> %d%u). + * @ratfor: switched + "as [-o output file] " to + "as [-o output file]". + * @ratfor: use previous random name + (ratfor output) rather then tempbasename.s for intermediate assembler + input (%g.s -> %U). + * @f77: use random name rather then tempbasename.s for + intermediate compiler output (%g.s -> %d%u). + * @f77: switched + "as [-o output file] " to + "as [-o output file]". + * @ratfor: use random name rather then tempbasename.s for + intermediate compiler output (%g.s -> %U). + + -- J.H.M. Dassen (Ray) Sat, 30 May 1998 17:27:03 +0200 + +gcc (2.7.2.3-4.3) frozen unstable; urgency=high + + * The "alpha" patches from -4 affected a lot more than alpha support, + and in all likeliness broke compilation of libc6 2.0.7pre3-1 + and 2.0.7pre1-4 . I removed them by selective application of the + diff between -4 and -4. (should fix #22292). + * Fixed reference to the trampolines paper (fixes #20002 for Debian; + this still needs to be forwarded). + * This is for frozen too. (obsoletes #22390 (request to move -4.2 to + frozen)). + * Split of gcc-docs package, so that the gcc can be succesfully installed + on systems that have egcs-docs installed. + * Added the README on the compiler situation that's already in the egcs + packages. + * Use the recommended settings LDFLAGS=-s CFLAGS= BOOT_CFLAGS='-O2'. + + -- J.H.M. Dassen (Ray) Thu, 28 May 1998 20:03:59 +0200 + +gcc (2.7.2.3-4.2) unstable; urgency=low + + * Still for unstable, as I have received no feedback about the g++272 + package yet. + * gcc now Provides: objc-compiler . + * Clean up /etc/alternatives/{g++,g++.1.gz} if they are dangling. + (fixes #19765, #20563) + + -- J.H.M. Dassen (Ray) Wed, 22 Apr 1998 12:40:45 +0200 + +gcc (2.7.2.3-4.1) unstable; urgency=low + + * Bumped Standards-Version. + * Forked off a g++272 package (e.g. for code that uses the GNU extensions + in libg++); for now this is in "unstable" only; feedback appreciated. + * Some cleanup (lintian): permissions, absolute link, gzip manpage. + + -- J.H.M. Dassen (Ray) Fri, 17 Apr 1998 13:05:25 +0200 + +gcc (2.7.2.3-4) unstable; urgency=low + + * Added alpha patches + * Only build C and objective-c compilers, split off g++ + + -- Galen Hazelwood Sun, 8 Mar 1998 21:16:39 -0700 + +gcc (2.7.2.3-3) unstable; urgency=low + + * Added patches for m68k + * Added patches for sparc (#13968) + + -- Galen Hazelwood Fri, 17 Oct 1997 18:25:21 -0600 + +gcc (2.7.2.3-2) unstable; urgency=low + + * Added g77 support (g77 0.5.21) + + -- Galen Hazelwood Wed, 10 Sep 1997 18:44:54 -0600 + +gcc (2.7.2.3-1) unstable; urgency=low + + * New upstream version + * Now using pristine source + * Removed misplaced paragraph in cpp.texi (#10877) + * Fix security bug for temporary files (#5298) + * Added Suggests: libg++-dev (#12335) + * Patched objc/thr-posix.c to support conditions (#12502) + + -- Galen Hazelwood Mon, 8 Sep 1997 12:20:07 -0600 + +gcc (2.7.2.2-7) unstable; urgency=low + + * Made cc and c++ managed through alternates mechanism (for egcs) + + -- Galen Hazelwood Tue, 19 Aug 1997 22:37:03 +0000 + +gcc (2.7.2.2-6) unstable; urgency=low + + * Tweaked Objective-C thread support (#11069) + + -- Galen Hazelwood Wed, 9 Jul 1997 11:56:57 -0600 + +gcc (2.7.2.2-5) unstable; urgency=low + + * More updated m68k patches + * Now conflicts with libc5-dev (#10006, #10112) + * More strict Depends: cpp, prevents version mismatch (#9954) + + -- Galen Hazelwood Thu, 19 Jun 1997 01:29:02 -0600 + +gcc (2.7.2.2-4) unstable; urgency=low + + * Moved to unstable + * Temporarily removed fortran support (waiting for new g77) + * Updated m68k patches + + -- Galen Hazelwood Fri, 9 May 1997 13:35:14 -0600 + +gcc (2.7.2.2-3) experimental; urgency=low + + * Built against libc6 (fixes bug #8511) + + -- Galen Hazelwood Fri, 4 Apr 1997 13:30:10 -0700 + +gcc (2.7.2.2-2) experimental; urgency=low + + * Fixed configure to build crt{begin,end}S.o on i386 + + -- Galen Hazelwood Tue, 11 Mar 1997 16:15:02 -0700 + +gcc (2.7.2.2-1) experimental; urgency=low + + * Built for use with libc6-dev (experimental purposes only!) + * Added m68k patches from Andreas Schwab + + -- Galen Hazelwood Fri, 7 Mar 1997 12:44:17 -0700 + +gcc (2.7.2.1-7) unstable; urgency=low + + * Patched to support g77 0.5.20 + + -- Galen Hazelwood Thu, 6 Mar 1997 22:20:23 -0700 + +gcc (2.7.2.1-6) unstable; urgency=low + + * Added (small) manpage for protoize/unprotoize (fixes bug #6904) + * Removed -lieee from specs file (fixes bug #7741) + * No longer builds aout-gcc + + -- Galen Hazelwood Mon, 3 Mar 1997 11:10:20 -0700 + +gcc (2.7.2.1-5) unstable; urgency=low + + * debian/control now lists cpp in section "interpreters" + * Re-added Objective-c patches for unstable + + -- Galen Hazelwood Wed, 22 Jan 1997 10:27:52 -0700 + +gcc (2.7.2.1-4) stable unstable; urgency=low + + * Changed original source file so dpkg-source -x works + * Removed Objective-c patches (unsafe for stable) + * Built against rex's libc, so fixes placed in -3 are available to + those still using rex + + -- Galen Hazelwood Tue, 21 Jan 1997 11:11:53 -0700 + +gcc (2.7.2.1-3) unstable; urgency=low + + * New (temporary) maintainer + * Updated to new standards and source format + * Integrated aout-gcc into gcc source package + * Demoted aout-gcc to Priority "extra" + * cpp package description more clear (fixes bug #5428) + * Removed cpp "Replaces: gcc" (fixes bug #5762) + * Minor fix to invoke.texi (fixes bug #2909) + * Added latest Objective-C patches for GNUstep people (fixes bug #4657) + + -- Galen Hazelwood Sun, 5 Jan 1997 09:57:36 -0700 --- gcc-4.5-4.5.2.orig/debian/README.cross +++ gcc-4.5-4.5.2/debian/README.cross @@ -0,0 +1,144 @@ +Building cross-compiler Debian packages +--------------------------------------- + +It is possible to build C and C++ cross compilers and support libraries +from gcc-4.0 source package. This document describes how to do so. +Cross-compiler build support is not perfect yet, please send fixes +and improvements to debian-gcc@lists.debian.org and +debian-embedded@lists.debian.org + +Before you start, you should probably check available pre-built +cross-toolchain debs. Available at http://www.emdebian.org + +Old patches could be reached at + http://zigzag.lvk.cs.msu.su/~nikita/debian/ + +If they are no longer there, you may check EmDebian web site at + http://www.emdebian.org/ +or ask debian-embedded@lists.debian.org for newer location. + +Please check http://bugs.debian.org/391445 if you are about building +gcc-4.3 or above. + +Most of them has been merged with gcc debian sources. + +0. What's wrong with toolchain-source approach + +Package toolchain-source contains sources for binutils and gcc, as well as +some support scripts to build cross-compiler packages. They seem to work. + +However, there is one fundamental problem with this approach. +Gcc package is actively maintained and frequently updated. These updates +do contain bug fixes and improvements, especially for non-x86 architectures. +Cross-compilers built using toolchain-source will not get those fixes unless +toolchain-source package is updated after each binutils and gcc update. +The later is not hapenning in real life. For example, toolchain-source +was upgraded from gcc-3.2 to gcc-3.3 half a year later than gcc-3.3 became +Debian default compiler. + +Keeping toolchain-source package up-to-date requires lots of work, and seems +to be a waste of time. It is much better to build cross-compilers directly +from gcc source package. + + +1. What is needed to build a cross-compiler from gcc-4.3 source + +1.1. dpkg-cross package + +Dpkg-cross package contains several tools to manage cross-compile environment. + +It can convert native debian library and lib-dev packages for the target +architecture to binary-all packages that keep libraries and headers under +/usr/$(TARGET)/. + +Also it contains helper tools for cross-compiling debian packages. Some of +these tools are used while building libgcc1 and libstdc++ library packages. +The resulting library packages follow the same convensions as library packages +converted by dpkg-cross. + +Currently, at least version 1.18 of dpkg-cross is needed for cross-gcc +package build. Version 1.32 of dpkg-cross is needed in order to build gcc-4.3. + +1.2. cross-binutils for the target + +You need cross-binutils for your target to build cross-compiler. +Binutils-multiarch package will not work because it does not provide cross- +assemblers. + +If you don't want to use pre-built cross-binutils packages, you may build +your own from binutils debian source package, using patches posted to +bug #231707. Please use the latest of patch versions available there. + +Alternatively, you may use toolchain-source package to build cross-binutils +(but in this case you will probably also want to use toolchain-source +to build cross-compiler itself). However, multilib'ed cross-compilers may +not build or work with these binutils. + +1.3. libc for target + +You also need libc library and development packages for the target +architecture installed. + +To get those, download linux-kernel-headers, libc6, and libc6-dev binary +debs for your target, convert those using dpkg-cross -b, and install +resulting -arch-cross debs. Consult dpkg-cross manual page for more +information. + +Building with/for alternative libc's is not supported yet (but this is in +TODO). + +Note that if you plan to use your cross-toolchain to develop kernel drivers +or similar low-level things, you will probably also need kernel headers +for the exact kernel version that your target hardware uses. + + +2. Building cross-compiler packages + +Get gcc-4.3 source package. + +Unpack it using dpkg-source -x, and cd to the package directory. + +Set GCC_TARGET environment variable to the target architectire name. Note +that currently you should use debian architecture name (i.e 'powerpc' or 'arm'), +not GNU system type (i.e. 'powerpc-linux' or 'arm-linux'). Setting GCC_TARGET +to GNU system type will cause cross-compiler build to fail. + +Instead of setting GCC_TARGET, target architecture name may be put into +debian/target file. If both GCC_TARGET is defined and debian/target file +exists, GCC_TARGET is used. + +Run debian/rules control. This will change debian/control file, +adjusting build-depends. By default, the packages will not depend on the +system -base package. A variable DEB_CROSS_INDEPENDENT has been merged with DEB_CROSS variable. + +You can then build with either + +$ GCC_TARGET=[arch] dpkg-buildpackage -rfakeroot + +3. Using crosshurd + +Jeff Bailey suggests alternate way to setup +environment to build cross-compiler, using 'crosshurd' package. +Crosshurd is like debootstrap but cross-arch, and works on the Hurd, +Linux and FreeBSD. (The name is historical). + +If you setup your environment with crosshurd, you will need to fix symlinks +in lib and usr/lib to be relative instead of absolute. For example: + +lrwxrwxrwx 1 root root 20 2004-05-06 23:02 libcom_err.so -> /lib/libcom_err.so.2 + +Needs to be changed to: + +lrwxrwxrwx 1 root root 20 2004-05-06 23:02 libcom_err.so -> ../../lib/libcom_err.so.2 + +Also, if you choose this method, set the environment variable 'with_sysroot' +to point to the ABSOLUTE PATH where the crosshurd was done. + +Note however that build-depends of cross-gcc and dependencies in generated +libgcc1 and libstdc++ packages assume that you use dpkg-cross to set up +your environment, and may be wrong or incomplete if you use alternate methods. +But probably you don't care. + +-- +Nikita V. Youshchenko - Jun 2004 +Hector Oron Martinez - Oct 2006 --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.kfreebsd-amd64 +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.kfreebsd-amd64 @@ -0,0 +1,5 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.10" +#include "libgfortran3.symbols.16" +#include "libgfortran3.symbols.64" --- gcc-4.5-4.5.2.orig/debian/libgfortran3.symbols.powerpc +++ gcc-4.5-4.5.2/debian/libgfortran3.symbols.powerpc @@ -0,0 +1,3 @@ +libgfortran.so.3 libgfortran3 #MINVER# +#include "libgfortran3.symbols.common" +#include "libgfortran3.symbols.16.powerpc" --- gcc-4.5-4.5.2.orig/debian/acats-killer.sh +++ gcc-4.5-4.5.2/debian/acats-killer.sh @@ -0,0 +1,62 @@ +#! /bin/sh + +# on ia64 systems, the acats hangs in unaligned memory accesses. +# kill these testcases. + +pidfile=acats-killer.pid + +usage() +{ + echo >&2 "usage: `basename $0` [-p ] " + exit 1 +} + +while [ $# -gt 0 ]; do + case $1 in + -p) + pidfile=$2 + shift + shift + ;; + -*) + usage + ;; + *) + break + esac +done + +[ $# -eq 2 ] || usage + +logfile=$1 +stopfile=$2 +interval=30 + +echo $$ > $pidfile + +while true; do + if [ -f "$stopfile" ]; then + echo "`basename $0`: finished." + rm -f $pidfile + exit 0 + fi + sleep $interval + if [ ! -f "$logfile" ]; then + continue + fi + pids=$(ps aux | awk '/testsuite\/ada\/acats\/tests/ { print $2 }') + if [ -n "$pids" ]; then + sleep $interval + pids2=$(ps aux | awk '/testsuite\/ada\/acats\/tests/ { print $2 }') + if [ "$pids" = "$pids2" ]; then + #echo kill: $pids + kill $pids + sleep 1 + pids2=$(ps aux | awk '/testsuite\/ada\/acats\/tests/ { print $2 }') + if [ "$pids" = "$pids2" ]; then + #echo kill -9: $pids + kill -9 $pids + fi + fi + fi +done --- gcc-4.5-4.5.2.orig/debian/protoize.1 +++ gcc-4.5-4.5.2/debian/protoize.1 @@ -0,0 +1,42 @@ +.TH PROTOIZE 1 +.\" NAME should be all caps, SECTION should be 1-8, maybe w/ subsection +.\" other parms are allowed: see man(7), man(1) +.SH NAME +protoize, unprotoize \- create/remove ANSI prototypes from C code +.SH SYNOPSIS +.B protoize +.I "[options] files ...." +.br +.B unprotoize +.I "[options] files ...." +.SH "DESCRIPTION" +This manual page documents briefly the +.BR protoize , +and +.B unprotoize +commands. +This manual page was written for the Debian GNU/Linux distribution +(but may be used by others), because the original program does not +have a manual page. +Instead, it has documentation in the GNU Info format; see below. +.PP +.B protoize +is an optional part of GNU C. You can use it to add prototypes to a +program, thus converting the program to ANSI C in one respect. The companion +program `unprotoize' does the reverse: it removes argument types from +any prototypes that are found. +.PP +When you run these programs, you must specify a set of source files +as command line arguments. +.SH OPTIONS +These programs are non-trivial to operate, and it is neither possible nor +desirable to properly summarize options in this man page. Read the info +documentation for more information. +.SH "SEE ALSO" +The programs are documented fully by +.IR "Gcc: The use and the internals of the GNU compiler", +available via the Info system. The documentation for protoize/unprotoize +can be found in the subsection "Invoking GCC", under "Running Protoize." +.SH AUTHOR +This manual page was written by Galen Hazelwood, +for the Debian GNU/Linux system. --- gcc-4.5-4.5.2.orig/debian/libstdc++6.symbols.mipsel +++ gcc-4.5-4.5.2/debian/libstdc++6.symbols.mipsel @@ -0,0 +1,7 @@ +libstdc++.so.6 libstdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" + __gxx_personality_v0@CXXABI_1.3 4.1.1 +#include "libstdc++6.symbols.excprop" +#include "libstdc++6.symbols.glibcxxmath" + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0 --- gcc-4.5-4.5.2.orig/debian/gnatprj.gpr +++ gcc-4.5-4.5.2/debian/gnatprj.gpr @@ -0,0 +1,32 @@ +-- Project file for use with GNAT +-- Copyright (c) 2005, 2008 Ludovic Brenta +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- This project file is designed to help build applications that use +-- GNAT project files. Here is an example of how to use this project file: +-- +-- with "gnatprj"; +-- project Example is +-- for Object_Dir use "obj"; +-- for Exec_Dir use "."; +-- for Main use ("example"); +-- end Example; + +with "gnatvsn.gpr"; +project Gnatprj is + for Library_Name use "gnatprj"; + for Library_Dir use "/usr/lib"; + for Library_Kind use "dynamic"; + for Source_Dirs use ("/usr/share/ada/adainclude/gnatprj"); + for Library_ALI_Dir use "/usr/lib/ada/adalib/gnatprj"; + for Externally_Built use "true"; +end Gnatprj; --- gcc-4.5-4.5.2.orig/debian/gcj-BV-jre-headless.postinst +++ gcc-4.5-4.5.2/debian/gcj-BV-jre-headless.postinst @@ -0,0 +1,48 @@ +#! /bin/sh -e + +prio=@java_priority@ + +update-alternatives --quiet \ + --install /usr/bin/java java /usr/bin/gij-@BV@ $prio \ + @GFDL@--slave /usr/share/man/man1/java.1.gz java.1.gz /usr/share/man/man1/gij-@BV@.1.gz + +update-alternatives --quiet \ + --install /usr/bin/rmiregistry rmiregistry /usr/bin/grmiregistry-@BV@ $prio \ + --slave /usr/share/man/man1/rmiregistry.1.gz rmiregistry.1.gz /usr/share/man/man1/grmiregistry-@BV@.1.gz + +update-alternatives --quiet \ + --install /usr/bin/keytool keytool /usr/bin/gkeytool-@BV@ $prio \ + --slave /usr/share/man/man1/keytool.1.gz keytool.1.gz /usr/share/man/man1/gkeytool-@BV@.1.gz + +update-alternatives --quiet \ + --install /usr/bin/orbd orbd /usr/bin/gorbd-@BV@ $prio \ + --slave /usr/share/man/man1/orbd.1.gz orbd.1.gz /usr/share/man/man1/gorbd-@BV@.1.gz + +update-alternatives --quiet \ + --install /usr/bin/rmid rmid /usr/bin/grmid-@BV@ $prio \ + --slave /usr/share/man/man1/rmid.1.gz rmid.1.gz /usr/share/man/man1/grmid-@BV@.1.gz + +case "$1" in +configure) + if [ ! -f /var/lib/gcj-@BV@/classmap.db ]; then + uname=$(uname -m) + mkdir -p /var/lib/gcj-@BV@ + if gcj-dbtool-@BV@ -n /var/lib/gcj-@BV@/classmap.db; then + case "$uname" in arm*|m68k|parisc*) + echo >&2 "gcj-dbtool succeeded unexpectedly" + esac + else + case "$uname" in + arm*|m68k|parisc*) + echo >&2 "ERROR: gcj-dbtool did fail; known problem on $uname";; + *) + exit 2 + esac + touch /var/lib/gcj-@BV@/classmap.db + fi + fi +esac + +#DEBHELPER# + +exit 0 --- gcc-4.5-4.5.2.orig/debian/lib32stdc++6.symbols.amd64 +++ gcc-4.5-4.5.2/debian/lib32stdc++6.symbols.amd64 @@ -0,0 +1,6 @@ +libstdc++.so.6 lib32stdc++6 #MINVER# +#include "libstdc++6.symbols.32bit" +#include "libstdc++6.symbols.excprop" + __gxx_personality_v0@CXXABI_1.3 4.1.1 + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 --- gcc-4.5-4.5.2.orig/debian/libgnatvsnBV.overrides +++ gcc-4.5-4.5.2/debian/libgnatvsnBV.overrides @@ -0,0 +1 @@ +libgnatvsn@BV@: missing-dependency-on-libc --- gcc-4.5-4.5.2.orig/debian/gcj-BV-jdk.overrides +++ gcc-4.5-4.5.2/debian/gcj-BV-jdk.overrides @@ -0,0 +1 @@ +gcj-@BV@-jdk binary: wrong-name-for-upstream-changelog --- gcc-4.5-4.5.2.orig/debian/lib64gcc1.symbols.powerpc +++ gcc-4.5-4.5.2/debian/lib64gcc1.symbols.powerpc @@ -0,0 +1,126 @@ +libgcc_s.so.1 lib64gcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4.4@GCC_3.4.4 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GLIBC_2.0@GLIBC_2.0 1:4.1.1 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __absvti2@GCC_3.4.4 1:4.1.1 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __addvti3@GCC_3.4.4 1:4.1.1 + __ashlti3@GCC_3.0 1:4.1.1 + __ashrti3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzti2@GCC_3.4 1:4.1.1 + __cmpti2@GCC_3.0 1:4.1.1 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzti2@GCC_3.4 1:4.1.1 + __deregister_frame@GLIBC_2.0 1:4.1.1 + __deregister_frame_info@GLIBC_2.0 1:4.1.1 + __deregister_frame_info_bases@GCC_3.0 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + __divtc3@GCC_4.0.0 1:4.1.1 + __divti3@GCC_3.0 1:4.1.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 1:4.1.1 + __ffsdi2@GCC_3.0 1:4.1.1 + __ffsti2@GCC_3.0 1:4.1.1 + __fixdfdi@GCC_3.0 1:4.1.1 + __fixdfti@GCC_3.0 1:4.1.1 + __fixsfdi@GCC_3.0 1:4.1.1 + __fixsfti@GCC_3.0 1:4.1.1 + __fixtfdi@GCC_3.0 1:4.1.1 + __fixtfti@GCC_3.0 1:4.1.1 + __fixunsdfdi@GCC_3.0 1:4.1.1 + __fixunsdfsi@GCC_3.0 1:4.1.1 + __fixunsdfti@GCC_3.0 1:4.1.1 + __fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfsi@GCC_3.0 1:4.1.1 + __fixunssfti@GCC_3.0 1:4.1.1 + __fixunstfdi@GCC_3.0 1:4.1.1 + __fixunstfti@GCC_3.0 1:4.1.1 + __floatdidf@GCC_3.0 1:4.1.1 + __floatdisf@GCC_3.0 1:4.1.1 + __floatditf@GCC_3.0 1:4.1.1 + __floattidf@GCC_3.0 1:4.1.1 + __floattisf@GCC_3.0 1:4.1.1 + __floattitf@GCC_3.0 1:4.1.1 + __floatundidf@GCC_4.2.0 1:4.2.1 + __floatundisf@GCC_4.2.0 1:4.2.1 + __floatunditf@GCC_4.2.0 1:4.2.1 + __floatuntidf@GCC_4.2.0 1:4.2.1 + __floatuntisf@GCC_4.2.0 1:4.2.1 + __floatuntitf@GCC_4.2.0 1:4.2.1 + __frame_state_for@GLIBC_2.0 1:4.1.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __gcc_qadd@GCC_3.4.4 1:4.1.1 + __gcc_qdiv@GCC_3.4.4 1:4.1.1 + __gcc_qmul@GCC_3.4.4 1:4.1.1 + __gcc_qsub@GCC_3.4.4 1:4.1.1 + __lshrti3@GCC_3.0 1:4.1.1 + __modti3@GCC_3.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_4.0.0 1:4.1.1 + __multi3@GCC_3.0 1:4.1.1 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __mulvti3@GCC_3.4.4 1:4.1.1 + __negti2@GCC_3.0 1:4.1.1 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __negvti2@GCC_3.4.4 1:4.1.1 + __paritydi2@GCC_3.4 1:4.1.1 + __parityti2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountti2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_4.0.0 1:4.1.1 + __register_frame@GLIBC_2.0 1:4.1.1 + __register_frame_info@GLIBC_2.0 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GLIBC_2.0 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GLIBC_2.0 1:4.1.1 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __subvti3@GCC_3.4.4 1:4.1.1 + __ucmpti2@GCC_3.0 1:4.1.1 + __udivmodti4@GCC_3.0 1:4.1.1 + __udivti3@GCC_3.0 1:4.1.1 + __umodti3@GCC_3.0 1:4.1.1 + _xlqadd@GCC_3.4 1:4.1.1 + _xlqdiv@GCC_3.4 1:4.1.1 + _xlqmul@GCC_3.4 1:4.1.1 + _xlqsub@GCC_3.4 1:4.1.1 --- gcc-4.5-4.5.2.orig/debian/libstdc++CXX-BV-doc.overrides +++ gcc-4.5-4.5.2/debian/libstdc++CXX-BV-doc.overrides @@ -0,0 +1,2 @@ +libstdc++@CXX@-@BV@-doc: hyphen-used-as-minus-sign +libstdc++@CXX@-@BV@-doc: manpage-has-bad-whatis-entry --- gcc-4.5-4.5.2.orig/debian/watch +++ gcc-4.5-4.5.2/debian/watch @@ -0,0 +1,2 @@ +version=2 +ftp://gcc.gnu.org/pub/gcc/releases/gcc-(4\.5[\d\.]*) debian uupdate --- gcc-4.5-4.5.2.orig/debian/libgcc1.symbols.i386 +++ gcc-4.5-4.5.2/debian/libgcc1.symbols.i386 @@ -0,0 +1,134 @@ +libgcc_s.so.1 libgcc1 #MINVER# + GCC_3.0@GCC_3.0 1:4.1.1 + GCC_3.3.1@GCC_3.3.1 1:4.1.1 + GCC_3.3@GCC_3.3 1:4.1.1 + GCC_3.4.2@GCC_3.4.2 1:4.1.1 + GCC_3.4@GCC_3.4 1:4.1.1 + GCC_4.0.0@GCC_4.0.0 1:4.1.1 + GCC_4.2.0@GCC_4.2.0 1:4.1.1 + GCC_4.3.0@GCC_4.3.0 1:4.3 + GCC_4.4.0@GCC_4.4.0 1:4.4.0 + GCC_4.5.0@GCC_4.5.0 1:4.5.0 + GLIBC_2.0@GLIBC_2.0 1:4.1.1 + _Unwind_Backtrace@GCC_3.3 1:4.1.1 + _Unwind_DeleteException@GCC_3.0 1:4.1.1 + _Unwind_FindEnclosingFunction@GCC_3.3 1:4.1.1 + _Unwind_Find_FDE@GCC_3.0 1:4.1.1 + _Unwind_ForcedUnwind@GCC_3.0 1:4.1.1 + _Unwind_GetCFA@GCC_3.3 1:4.1.1 + _Unwind_GetDataRelBase@GCC_3.0 1:4.1.1 + _Unwind_GetGR@GCC_3.0 1:4.1.1 + _Unwind_GetIP@GCC_3.0 1:4.1.1 + _Unwind_GetIPInfo@GCC_4.2.0 1:4.1.1 + _Unwind_GetLanguageSpecificData@GCC_3.0 1:4.1.1 + _Unwind_GetRegionStart@GCC_3.0 1:4.1.1 + _Unwind_GetTextRelBase@GCC_3.0 1:4.1.1 + _Unwind_RaiseException@GCC_3.0 1:4.1.1 + _Unwind_Resume@GCC_3.0 1:4.1.1 + _Unwind_Resume_or_Rethrow@GCC_3.3 1:4.1.1 + _Unwind_SetGR@GCC_3.0 1:4.1.1 + _Unwind_SetIP@GCC_3.0 1:4.1.1 + __absvdi2@GCC_3.0 1:4.1.1 + __absvsi2@GCC_3.0 1:4.1.1 + __addtf3@GCC_4.4.0 1:4.4.0 + __addvdi3@GCC_3.0 1:4.1.1 + __addvsi3@GCC_3.0 1:4.1.1 + __ashldi3@GCC_3.0 1:4.1.1 + __ashrdi3@GCC_3.0 1:4.1.1 + __bswapdi2@GCC_4.3.0 1:4.3 + __bswapsi2@GCC_4.3.0 1:4.3 + __clear_cache@GCC_3.0 1:4.1.1 + __clzdi2@GCC_3.4 1:4.1.1 + __clzsi2@GCC_3.4 1:4.1.1 + __cmpdi2@GCC_3.0 1:4.1.1 + __copysigntf3@GCC_4.4.0 1:4.4.0 + __ctzdi2@GCC_3.4 1:4.1.1 + __ctzsi2@GCC_3.4 1:4.1.1 + __deregister_frame@GLIBC_2.0 1:4.1.1 + __deregister_frame_info@GLIBC_2.0 1:4.1.1 + __deregister_frame_info_bases@GCC_3.0 1:4.1.1 + __divdc3@GCC_4.0.0 1:4.1.1 + __divdi3@GLIBC_2.0 1:4.1.1 + __divsc3@GCC_4.0.0 1:4.1.1 + __divtc3@GCC_4.4.0 1:4.4.0 + __divtf3@GCC_4.4.0 1:4.4.0 + __divxc3@GCC_4.0.0 1:4.1.1 + __emutls_get_address@GCC_4.3.0 1:4.3 + __emutls_register_common@GCC_4.3.0 1:4.3 + __enable_execute_stack@GCC_3.4.2 1:4.1.1 + __eqtf2@GCC_4.4.0 1:4.4.0 + __extenddftf2@GCC_4.4.0 1:4.4.0 + __extendsftf2@GCC_4.4.0 1:4.4.0 + __extendxftf2@GCC_4.5.0 1:4.5.0 + __fabstf2@GCC_4.4.0 1:4.4.0 + __ffsdi2@GCC_3.0 1:4.1.1 + __ffssi2@GCC_4.3.0 1:4.3 + __fixdfdi@GCC_3.0 1:4.1.1 + __fixsfdi@GCC_3.0 1:4.1.1 + __fixtfdi@GCC_4.4.0 1:4.4.0 + __fixtfsi@GCC_4.4.0 1:4.4.0 + __fixunsdfdi@GCC_3.0 1:4.1.1 + __fixunsdfsi@GCC_3.0 1:4.1.1 + __fixunssfdi@GCC_3.0 1:4.1.1 + __fixunssfsi@GCC_3.0 1:4.1.1 + __fixunstfdi@GCC_4.4.0 1:4.4.0 + __fixunstfsi@GCC_4.4.0 1:4.4.0 + __fixunsxfdi@GCC_3.0 1:4.1.1 + __fixunsxfsi@GCC_3.0 1:4.1.1 + __fixxfdi@GCC_3.0 1:4.1.1 + __floatdidf@GCC_3.0 1:4.1.1 + __floatdisf@GCC_3.0 1:4.1.1 + __floatditf@GCC_4.4.0 1:4.4.0 + __floatdixf@GCC_3.0 1:4.1.1 + __floatsitf@GCC_4.4.0 1:4.4.0 + __floatundidf@GCC_4.2.0 1:4.2.1 + __floatundisf@GCC_4.2.0 1:4.2.1 + __floatunditf@GCC_4.4.0 1:4.4.0 + __floatundixf@GCC_4.2.0 1:4.2.1 + __floatunsitf@GCC_4.4.0 1:4.4.0 + __frame_state_for@GLIBC_2.0 1:4.1.1 + __gcc_personality_v0@GCC_3.3.1 1:4.1.1 + __getf2@GCC_4.4.0 1:4.4.0 + __gttf2@GCC_4.4.0 1:4.4.0 + __letf2@GCC_4.4.0 1:4.4.0 + __lshrdi3@GCC_3.0 1:4.1.1 + __lttf2@GCC_4.4.0 1:4.4.0 + __moddi3@GLIBC_2.0 1:4.1.1 + __muldc3@GCC_4.0.0 1:4.1.1 + __muldi3@GCC_3.0 1:4.1.1 + __mulsc3@GCC_4.0.0 1:4.1.1 + __multc3@GCC_4.4.0 1:4.4.0 + __multf3@GCC_4.4.0 1:4.4.0 + __mulvdi3@GCC_3.0 1:4.1.1 + __mulvsi3@GCC_3.0 1:4.1.1 + __mulxc3@GCC_4.0.0 1:4.1.1 + __negdi2@GCC_3.0 1:4.1.1 + __negtf2@GCC_4.4.0 1:4.4.0 + __negvdi2@GCC_3.0 1:4.1.1 + __negvsi2@GCC_3.0 1:4.1.1 + __netf2@GCC_4.4.0 1:4.4.0 + __paritydi2@GCC_3.4 1:4.1.1 + __paritysi2@GCC_3.4 1:4.1.1 + __popcountdi2@GCC_3.4 1:4.1.1 + __popcountsi2@GCC_3.4 1:4.1.1 + __powidf2@GCC_4.0.0 1:4.1.1 + __powisf2@GCC_4.0.0 1:4.1.1 + __powitf2@GCC_4.4.0 1:4.4.0 + __powixf2@GCC_4.0.0 1:4.1.1 + __register_frame@GLIBC_2.0 1:4.1.1 + __register_frame_info@GLIBC_2.0 1:4.1.1 + __register_frame_info_bases@GCC_3.0 1:4.1.1 + __register_frame_info_table@GLIBC_2.0 1:4.1.1 + __register_frame_info_table_bases@GCC_3.0 1:4.1.1 + __register_frame_table@GLIBC_2.0 1:4.1.1 + __subtf3@GCC_4.4.0 1:4.4.0 + __subvdi3@GCC_3.0 1:4.1.1 + __subvsi3@GCC_3.0 1:4.1.1 + __trunctfdf2@GCC_4.4.0 1:4.4.0 + __trunctfsf2@GCC_4.4.0 1:4.4.0 + __trunctfxf2@GCC_4.4.0 1:4.4.0 + __ucmpdi2@GCC_3.0 1:4.1.1 + __udivdi3@GLIBC_2.0 1:4.1.1 + __udivmoddi4@GCC_3.0 1:4.1.1 + __umoddi3@GLIBC_2.0 1:4.1.1 + __unordtf2@GCC_4.4.0 1:4.4.0 --- gcc-4.5-4.5.2.orig/debian/lib64stdc++6.symbols.sparc +++ gcc-4.5-4.5.2/debian/lib64stdc++6.symbols.sparc @@ -0,0 +1,9 @@ +libstdc++.so.6 lib64stdc++6 #MINVER# +#include "libstdc++6.symbols.64bit" +#include "libstdc++6.symbols.excprop" + _ZN9__gnu_cxx12__atomic_addEPVli@GLIBCXX_3.4 4.1.1 + _ZN9__gnu_cxx18__exchange_and_addEPVli@GLIBCXX_3.4 4.1.1 +# FIXME: Currently no ldbl symbols in the 64bit libstdc++ on sparc. +# #include "libstdc++6.symbols.ldbl.64bit" + _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3 + _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3 --- gcc-4.5-4.5.2.orig/debian/README.C++ +++ gcc-4.5-4.5.2/debian/README.C++ @@ -0,0 +1,35 @@ +libstdc++ is an implementation of the Standard C++ Library, including the +Standard Template Library (i.e. as specified by ANSI and ISO). + +Some notes on porting applications from libstdc++-2.90 (or earlier versions) +to libstdc++-v3 can be found in the libstdc++6-4.3-doc package. After the +installation of the package, look at: + + file:///usr/share/doc/gcc-4.3-base/libstdc++/html/17_intro/porting-howto.html + +On Debian GNU/Linux you find additional documentation in the +libstdc++6-4.3-doc package. After installing these packages, +point your browser to + + file:///usr/share/doc/libstdc++6-4.3-doc/libstdc++/html/index.html + +Other documentation can be found: + + http://www.sgi.com/tech/stl/ + +with a good, recent, book on C++. + +A great deal of useful C++ documentation can be found in the C++ FAQ-Lite, +maintained by Marshall Cline . It can be found at the +mirror sites linked from the following URL (this was last updated on +2010/09/11): + + http://www.parashift.com/c++-faq/ + +or use some search engin site to find it, e.g.: + + http://www.google.com/search?q=c%2B%2B+faq+lite + +Be careful not to use outdated mirors. + +Please send updates to this list as bug report for the g++ package. --- gcc-4.5-4.5.2.orig/debian/gcj-BV-jre-headless.overrides +++ gcc-4.5-4.5.2/debian/gcj-BV-jre-headless.overrides @@ -0,0 +1,2 @@ +# pick up the exact version, in case another gcj version is installed +gcj-@BV@-jre-headless binary: binary-or-shlib-defines-rpath --- gcc-4.5-4.5.2.orig/debian/gcc-BV-doc.doc-base.gomp +++ gcc-4.5-4.5.2/debian/gcc-BV-doc.doc-base.gomp @@ -0,0 +1,15 @@ +Document: gcc-@BV@-gomp +Title: The GNU OpenMP Implementation (for GCC @BV@) +Author: Various +Abstract: This manual documents the usage of libgomp, the GNU implementation + of the OpenMP Application Programming Interface (API) for multi-platform + shared-memory parallel programming in C/C++ and Fortran. +Section: Programming + +Format: html +Index: /usr/share/doc/gcc-@BV@-base/libgomp.html +Files: /usr/share/doc/gcc-@BV@-base/libgomp.html + +Format: info +Index: /usr/share/info/libgomp-@BV@.info.gz +Files: /usr/share/info/libgomp-@BV@* --- gcc-4.5-4.5.2.orig/debian/libgomp1.symbols +++ gcc-4.5-4.5.2/debian/libgomp1.symbols @@ -0,0 +1,4 @@ +libgomp.so.1 libgomp1 #MINVER# +#include "libgomp1.symbols.common" + GOMP_atomic_end@GOMP_1.0 4.2.1 + GOMP_atomic_start@GOMP_1.0 4.2.1 --- gcc-4.5-4.5.2.orig/debian/libstdc++CXX.postinst +++ gcc-4.5-4.5.2/debian/libstdc++CXX.postinst @@ -0,0 +1,12 @@ +#! /bin/sh -e + +case "$1" in + configure) + docdir=/usr/share/doc/libstdc++@CXX@ + if [ -d $docdir ] && [ ! -h $docdir ]; then + rm -rf $docdir + ln -s gcc-@BV@-base $docdir + fi +esac + +#DEBHELPER# --- gcc-4.5-4.5.2.orig/debian/source/format +++ gcc-4.5-4.5.2/debian/source/format @@ -0,0 +1 @@ +1.0 --- gcc-4.5-4.5.2.orig/debian/patches/mudflap-nocheck.diff +++ gcc-4.5-4.5.2/debian/patches/mudflap-nocheck.diff @@ -0,0 +1,17 @@ +# DP: Disable running the libmudflap testsuite. Getting killed on alpha. + +--- + libmudflap/testsuite/Makefile.in | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +--- a/src/libmudflap/testsuite/Makefile.in ++++ b/src/libmudflap/testsuite/Makefile.in +@@ -246,6 +246,8 @@ CTAGS: + + + check-DEJAGNU: site.exp ++ @echo target $@ disabled for Debian build. ++check-DEJAGNU-disabled: site.exp + srcdir=`$(am__cd) $(srcdir) && pwd`; export srcdir; \ + EXPECT=$(EXPECT); export EXPECT; \ + runtest=$(RUNTEST); \ --- gcc-4.5-4.5.2.orig/debian/patches/config-ml.diff +++ gcc-4.5-4.5.2/debian/patches/config-ml.diff @@ -0,0 +1,79 @@ +# DP: disable some biarch libraries for biarch builds + +--- + config-ml.in | 45 ++++++++++++++++++++++++++++++++++++++++++++- + 1 files changed, 44 insertions(+), 1 deletions(-) + +--- a/src/config-ml.in ++++ b/src/config-ml.in +@@ -306,6 +306,11 @@ arm-*-*) + done + fi + ;; ++i[34567]86-*-*) ++ case " $multidirs " in ++ *" 64 "*) ac_configure_args="${ac_configure_args} --host=x86_64-linux-gnu" ++ esac ++ ;; + m68*-*-*) + if [ x$enable_softfloat = xno ] + then +@@ -477,9 +482,36 @@ powerpc*-*-* | rs6000*-*-*) + esac + done + fi ++ case " $multidirs " in ++ *" 64 "*) ac_configure_args="${ac_configure_args} --host=powerpc64-linux-gnu" ++ esac ++ ;; ++s390-*-*) ++ case " $multidirs " in ++ *" 64 "*) ac_configure_args="${ac_configure_args} --host=s390x-linux-gnu" ++ esac + ;; + esac + ++if [ -z "$biarch_multidir_names" ]; then ++ biarch_multidir_names="libiberty libstdc++-v3 libgfortran libmudflap libssp libffi libobjc libgomp" ++ echo "WARNING: biarch_multidir_names is unset. Use default value:" ++ echo " $biarch_multidir_names" ++fi ++ml_srcbase=`basename $ml_realsrcdir` ++old_multidirs="${multidirs}" ++multidirs="" ++for x in ${old_multidirs}; do ++ case " $x " in ++ " 32 "|" n32 "|" 64 " ) ++ case "$biarch_multidir_names" in ++ *"$ml_srcbase"*) multidirs="${multidirs} ${x}" ;; ++ esac ++ ;; ++ *) multidirs="${multidirs} ${x}" ;; ++ esac ++done ++ + # Remove extraneous blanks from multidirs. + # Tests like `if [ -n "$multidirs" ]' require it. + multidirs=`echo "$multidirs" | sed -e 's/^[ ][ ]*//' -e 's/[ ][ ]*$//' -e 's/[ ][ ]*/ /g'` +@@ -857,9 +889,20 @@ if [ -n "${multidirs}" ] && [ -z "${ml_norecursion}" ]; then + fi + fi + ++ ml_configure_args= ++ for arg in ${ac_configure_args} ++ do ++ case $arg in ++ *CC=*) ml_configure_args=${ml_config_env} ;; ++ *CXX=*) ml_configure_args=${ml_config_env} ;; ++ *GCJ=*) ml_configure_args=${ml_config_env} ;; ++ *) ;; ++ esac ++ done ++ + if eval ${ml_config_env} ${ml_config_shell} ${ml_recprog} \ + --with-multisubdir=${ml_dir} --with-multisrctop=${multisrctop} \ +- ${ac_configure_args} ${ml_config_env} ${ml_srcdiroption} ; then ++ ${ac_configure_args} ${ml_configure_args} ${ml_srcdiroption} ; then + true + else + exit 1 --- gcc-4.5-4.5.2.orig/debian/patches/note-gnu-stack.diff +++ gcc-4.5-4.5.2/debian/patches/note-gnu-stack.diff @@ -0,0 +1,170 @@ +# DP: Add .note.GNU-stack sections for gcc's crt files, libffi and boehm-gc +# DP: Taken from FC. + +gcc/ + +2004-09-20 Jakub Jelinek + + * config/rs6000/ppc-asm.h: Add .note.GNU-stack section also + on ppc64-linux. + + * config/ia64/lib1funcs.asm: Add .note.GNU-stack section on + ia64-linux. + * config/ia64/crtbegin.asm: Likewise. + * config/ia64/crtend.asm: Likewise. + * config/ia64/crti.asm: Likewise. + * config/ia64/crtn.asm: Likewise. + +2004-05-14 Jakub Jelinek + + * config/ia64/linux.h (TARGET_ASM_FILE_END): Define. + +boehm-gc/ + +2005-02-08 Jakub Jelinek + + * ia64_save_regs_in_stack.s: Moved to... + * ia64_save_regs_in_stack.S: ... this. Add .note.GNU-stack + on Linux. + +libffi/ + +2007-05-11 Daniel Jacobowitz + + * src/arm/sysv.S: Fix ARM comment marker. + +2005-02-08 Jakub Jelinek + + * src/alpha/osf.S: Add .note.GNU-stack on Linux. + * src/s390/sysv.S: Likewise. + * src/powerpc/linux64.S: Likewise. + * src/powerpc/linux64_closure.S: Likewise. + * src/powerpc/ppc_closure.S: Likewise. + * src/powerpc/sysv.S: Likewise. + * src/x86/unix64.S: Likewise. + * src/x86/sysv.S: Likewise. + * src/sparc/v8.S: Likewise. + * src/sparc/v9.S: Likewise. + * src/m68k/sysv.S: Likewise. + * src/ia64/unix.S: Likewise. + * src/arm/sysv.S: Likewise. + +--- + boehm-gc/ia64_save_regs_in_stack.s | 12 ------------ + gcc/config/ia64/crtbegin.asm | 4 ++++ + gcc/config/ia64/crtend.asm | 4 ++++ + gcc/config/ia64/crti.asm | 4 ++++ + gcc/config/ia64/crtn.asm | 4 ++++ + gcc/config/ia64/lib1funcs.asm | 4 ++++ + gcc/config/ia64/linux.h | 2 ++ + gcc/config/rs6000/ppc-asm.h | 2 +- + libffi/src/ia64/unix.S | 4 ++++ + libffi/src/powerpc/linux64.S | 4 ++++ + libffi/src/powerpc/linux64_closure.S | 4 ++++ + 11 files changed, 35 insertions(+), 13 deletions(-) + +--- a/src/boehm-gc/ia64_save_regs_in_stack.s ++++ b/src/boehm-gc/ia64_save_regs_in_stack.s +@@ -1,12 +0,0 @@ +- .text +- .align 16 +- .global GC_save_regs_in_stack +- .proc GC_save_regs_in_stack +-GC_save_regs_in_stack: +- .body +- flushrs +- ;; +- mov r8=ar.bsp +- br.ret.sptk.few rp +- .endp GC_save_regs_in_stack +- +--- a/src/boehm-gc/ia64_save_regs_in_stack.S ++++ b/src/boehm-gc/ia64_save_regs_in_stack.S +@@ -0,0 +1,15 @@ ++ .text ++ .align 16 ++ .global GC_save_regs_in_stack ++ .proc GC_save_regs_in_stack ++GC_save_regs_in_stack: ++ .body ++ flushrs ++ ;; ++ mov r8=ar.bsp ++ br.ret.sptk.few rp ++ .endp GC_save_regs_in_stack ++ ++#ifdef __linux__ ++ .section .note.GNU-stack,"",@progbits ++#endif +--- a/src/gcc/config/ia64/crtbegin.asm ++++ b/src/gcc/config/ia64/crtbegin.asm +@@ -255,3 +255,7 @@ __do_jv_register_classes: + .weak __cxa_finalize + #endif + .weak _Jv_RegisterClasses ++ ++#ifdef __linux__ ++.section .note.GNU-stack; .previous ++#endif +--- a/src/gcc/config/ia64/crtend.asm ++++ b/src/gcc/config/ia64/crtend.asm +@@ -122,3 +122,7 @@ __do_global_ctors_aux: + + br.ret.sptk.many rp + .endp __do_global_ctors_aux ++ ++#ifdef __linux__ ++.section .note.GNU-stack; .previous ++#endif +--- a/src/gcc/config/ia64/crti.asm ++++ b/src/gcc/config/ia64/crti.asm +@@ -62,3 +62,7 @@ _fini: + .body + + # end of crti.asm ++ ++#ifdef __linux__ ++.section .note.GNU-stack; .previous ++#endif +--- a/src/gcc/config/ia64/crtn.asm ++++ b/src/gcc/config/ia64/crtn.asm +@@ -52,3 +52,7 @@ + br.ret.sptk.many b0 + + # end of crtn.asm ++ ++#ifdef __linux__ ++.section .note.GNU-stack; .previous ++#endif +--- a/src/gcc/config/ia64/lib1funcs.asm ++++ b/src/gcc/config/ia64/lib1funcs.asm +@@ -796,3 +796,7 @@ __floattitf: + .endp __floattitf + #endif + #endif ++ ++#ifdef __linux__ ++.section .note.GNU-stack; .previous ++#endif +--- a/src/gcc/config/ia64/linux.h ++++ b/src/gcc/config/ia64/linux.h +@@ -5,6 +5,8 @@ + + #define TARGET_VERSION fprintf (stderr, " (IA-64) Linux"); + ++#define TARGET_ASM_FILE_END file_end_indicate_exec_stack ++ + /* This is for -profile to use -lc_p instead of -lc. */ + #undef CC1_SPEC + #define CC1_SPEC "%{profile:-p} %{G*}" +--- a/src/gcc/config/rs6000/ppc-asm.h ++++ b/src/gcc/config/rs6000/ppc-asm.h +@@ -172,7 +172,7 @@ GLUE(.L,name): \ + .size FUNC_NAME(name),GLUE(.L,name)-FUNC_NAME(name) + #endif + +-#if defined __linux__ && !defined __powerpc64__ ++#if defined __linux__ + .section .note.GNU-stack + .previous + #endif --- gcc-4.5-4.5.2.orig/debian/patches/rename-info-files.diff +++ gcc-4.5-4.5.2/debian/patches/rename-info-files.diff @@ -0,0 +1,546 @@ +# DP: Allow transformations on info file names. Reference the +# DP: transformed info file names in the texinfo files. + + +2004-02-17 Matthias Klose + +gcc/ChangeLog: + * Makefile.in: Allow transformations on info file names. + Define MAKEINFODEFS, macros to pass transformated info file + names to makeinfo. + * doc/cpp.texi: Use macros defined in MAKEINFODEFS for references. + * doc/cppinternals.texi: Likewise. + * doc/extend.texi: Likewise. + * doc/gcc.texi: Likewise. + * doc/gccint.texi: Likewise. + * doc/invoke.texi: Likewise. + * doc/libgcc.texi: Likewise. + * doc/makefile.texi: Likewise. + * doc/passes.texi: Likewise. + * doc/sourcebuild.texi: Likewise. + * doc/standards.texi: Likewise. + * doc/trouble.texi: Likewise. + +gcc/fortran/ChangeLog: + * Make-lang.in: Allow transformations on info file names. + Pass macros of transformated info file defined in MAKEINFODEFS + names to makeinfo. + * gfortran.texi: Use macros defined in MAKEINFODEFS for references. + +gcc/java/ChangeLog: + * Make-lang.in: Allow transformations on info file names. + Pass macros of transformated info file defined in MAKEINFODEFS + +--- a/src/gcc/doc/gcc.texi.orig 2009-07-18 ++++ b/src/gcc/doc/gcc.texi 2009-12-20 +@@ -65,8 +65,8 @@ + @ifnottex + @dircategory Software development + @direntry +-* gcc: (gcc). The GNU Compiler Collection. +-* g++: (gcc). The GNU C++ compiler. ++* @value{fngcc}: (@value{fngcc}). The GNU Compiler Collection. ++* @value{fngxx}: (@value{fngcc}). The GNU C++ compiler. + @end direntry + This file documents the use of the GNU compilers. + @sp 1 +@@ -126,7 +126,7 @@ + The internals of the GNU compilers, including how to port them to new + targets and some information about how to write front ends for new + languages, are documented in a separate manual. @xref{Top,, +-Introduction, gccint, GNU Compiler Collection (GCC) Internals}. ++Introduction, @value{fngccint}, GNU Compiler Collection (GCC) Internals}. + + @menu + * G++ and GCC:: You can compile C or C++ programs. +--- a/src/gcc/doc/install.texi.orig 2009-12-16 ++++ b/src/gcc/doc/install.texi 2009-12-20 +@@ -97,7 +97,7 @@ + @end ifinfo + @dircategory Software development + @direntry +-* gccinstall: (gccinstall). Installing the GNU Compiler Collection. ++* @value{fngccinstall}: (@value{fngccinstall}). Installing the GNU Compiler Collection. + @end direntry + + @c Part 3 Titlepage and Copyright +--- a/src/gcc/doc/gccint.texi.orig 2009-05-23 ++++ b/src/gcc/doc/gccint.texi 2009-12-20 +@@ -51,7 +51,7 @@ + @ifnottex + @dircategory Software development + @direntry +-* gccint: (gccint). Internals of the GNU Compiler Collection. ++* @value{fngccint}: (@value{fngccint}). Internals of the GNU Compiler Collection. + @end direntry + This file documents the internals of the GNU compilers. + @sp 1 +@@ -83,7 +83,7 @@ + @value{VERSION_PACKAGE} + @end ifset + version @value{version-GCC}. The use of the GNU compilers is documented in a +-separate manual. @xref{Top,, Introduction, gcc, Using the GNU ++separate manual. @xref{Top,, Introduction, @value{fngcc}, Using the GNU + Compiler Collection (GCC)}. + + This manual is mainly a reference manual rather than a tutorial. It +--- a/src/gcc/doc/cpp.texi.orig 2009-11-16 ++++ b/src/gcc/doc/cpp.texi 2009-12-20 +@@ -53,7 +53,7 @@ + @ifinfo + @dircategory Software development + @direntry +-* Cpp: (cpp). The GNU C preprocessor. ++* @value{fncpp}: (@value{fncpp}). The GNU C preprocessor. + @end direntry + @end ifinfo + +--- a/src/gcc/doc/extend.texi.orig 2009-12-16 ++++ b/src/gcc/doc/extend.texi 2009-12-20 +@@ -13048,7 +13048,7 @@ + test for the GNU compiler the same way as for C programs: check for a + predefined macro @code{__GNUC__}. You can also use @code{__GNUG__} to + test specifically for GNU C++ (@pxref{Common Predefined Macros,, +-Predefined Macros,cpp,The GNU C Preprocessor}). ++Predefined Macros,@value{fncpp},The GNU C Preprocessor}). + + @menu + * Volatiles:: What constitutes an access to a volatile object. +--- a/src/gcc/doc/standards.texi.orig 2009-09-22 ++++ b/src/gcc/doc/standards.texi 2009-12-20 +@@ -223,8 +223,8 @@ + GNAT Reference Manual}, for information on standard + conformance and compatibility of the Ada compiler. + +-@xref{Standards,,Standards, gfortran, The GNU Fortran Compiler}, for details ++@xref{Standards,,Standards, @value{fngfortran}, The GNU Fortran Compiler}, for details + of standards supported by GNU Fortran. + +-@xref{Compatibility,,Compatibility with the Java Platform, gcj, GNU gcj}, ++@xref{Compatibility,,Compatibility with the Java Platform, @value{fngcj}, GNU gcj}, + for details of compatibility between @command{gcj} and the Java Platform. +--- a/src/gcc/doc/cppinternals.texi.orig 2008-07-21 ++++ b/src/gcc/doc/cppinternals.texi 2009-12-20 +@@ -7,7 +7,7 @@ + @ifinfo + @dircategory Software development + @direntry +-* Cpplib: (cppinternals). Cpplib internals. ++* @value{fncppint}: (@value{fncppint}). Cpplib internals. + @end direntry + @end ifinfo + +--- a/src/gcc/doc/makefile.texi.orig 2009-02-21 ++++ b/src/gcc/doc/makefile.texi 2009-12-20 +@@ -140,7 +140,7 @@ + @item profiledbootstrap + Builds a compiler with profiling feedback information. For more + information, see +-@ref{Building,,Building with profile feedback,gccinstall,Installing GCC}. ++@ref{Building,,Building with profile feedback,@value{fngccinstall},Installing GCC}. + + @item restrap + Restart a bootstrap, so that everything that was not built with +--- a/src/gcc/doc/libgcc.texi.orig 2008-07-21 ++++ b/src/gcc/doc/libgcc.texi 2009-12-20 +@@ -24,7 +24,7 @@ + GCC will also generate calls to C library routines, such as + @code{memcpy} and @code{memset}, in some cases. The set of routines + that GCC may possibly use is documented in @ref{Other +-Builtins,,,gcc, Using the GNU Compiler Collection (GCC)}. ++Builtins,,,@value{fngcc}, Using the GNU Compiler Collection (GCC)}. + + These routines take arguments and return values of a specific machine + mode, not a specific C type. @xref{Machine Modes}, for an explanation +--- a/src/gcc/doc/invoke.texi.orig 2009-12-17 ++++ b/src/gcc/doc/invoke.texi 2009-12-20 +@@ -8644,7 +8644,7 @@ + @option{-nodefaultlibs} is @file{libgcc.a}, a library of internal subroutines + that GCC uses to overcome shortcomings of particular machines, or special + needs for some languages. +-(@xref{Interface,,Interfacing to GCC Output,gccint,GNU Compiler ++(@xref{Interface,,Interfacing to GCC Output,@value{fngccint},GNU Compiler + Collection (GCC) Internals}, + for more discussion of @file{libgcc.a}.) + In most cases, you need @file{libgcc.a} even when you want to avoid +@@ -8652,7 +8652,7 @@ + or @option{-nodefaultlibs} you should usually specify @option{-lgcc} as well. + This ensures that you have no unresolved references to internal GCC + library subroutines. (For example, @samp{__main}, used to ensure C++ +-constructors will be called; @pxref{Collect2,,@code{collect2}, gccint, ++constructors will be called; @pxref{Collect2,,@code{collect2}, @value{fngccint}, + GNU Compiler Collection (GCC) Internals}.) + + @item -pie +@@ -17524,7 +17524,7 @@ + @option{-B}, @option{-I} and @option{-L} (@pxref{Directory Options}). These + take precedence over places specified using environment variables, which + in turn take precedence over those specified by the configuration of GCC@. +-@xref{Driver,, Controlling the Compilation Driver @file{gcc}, gccint, ++@xref{Driver,, Controlling the Compilation Driver @file{gcc}, @value{fngccint}, + GNU Compiler Collection (GCC) Internals}. + + @table @env +@@ -17679,7 +17679,7 @@ + + A precompiled header file will be searched for when @code{#include} is + seen in the compilation. As it searches for the included file +-(@pxref{Search Path,,Search Path,cpp,The C Preprocessor}) the ++(@pxref{Search Path,,Search Path,@value{fncpp},The C Preprocessor}) the + compiler looks for a precompiled header in each directory just before it + looks for the include file in that directory. The name searched for is + the name specified in the @code{#include} with @samp{.gch} appended. If +--- a/src/gcc/doc/passes.texi.orig 2009-11-30 ++++ b/src/gcc/doc/passes.texi 2009-12-20 +@@ -201,7 +201,7 @@ + @item Mudflap declaration registration + + If mudflap (@pxref{Optimize Options,,-fmudflap -fmudflapth +--fmudflapir,gcc,Using the GNU Compiler Collection (GCC)}) is ++-fmudflapir,@value{fngcc},Using the GNU Compiler Collection (GCC)}) is + enabled, we generate code to register some variable declarations with + the mudflap runtime. Specifically, the runtime tracks the lifetimes of + those variable declarations that have their addresses taken, or whose +--- a/src/gcc/ada/gnat_rm.texi.orig 2009-11-30 ++++ b/src/gcc/ada/gnat_rm.texi 2009-12-20 +@@ -38,7 +38,7 @@ + + @dircategory GNU Ada tools + @direntry +-* GNAT Reference Manual: (gnat_rm). Reference Manual for GNU Ada tools. ++* GNAT Reference Manual: (gnat_rm-4.5). Reference Manual for GNU Ada tools. + @end direntry + + @titlepage +--- a/src/gcc/ada/gnat-style.texi.orig 2009-02-21 ++++ b/src/gcc/ada/gnat-style.texi 2009-12-20 +@@ -31,7 +31,7 @@ + + @dircategory Software development + @direntry +-* gnat-style: (gnat-style). GNAT Coding Style ++* gnat-style: (gnat-style-4.5). GNAT Coding Style + @end direntry + + @macro syntax{element} +--- a/src/gcc/java/Make-lang.in.orig 2009-09-15 ++++ b/src/gcc/java/Make-lang.in 2009-12-20 +@@ -127,11 +127,23 @@ + etags --include TAGS.sub --include ../TAGS.sub + + +-java.info: doc/gcj.info ++TEXI_GCJ_FILES = java/gcj.texi \ ++ $(gcc_docdir)/include/gpl.texi $(gcc_docdir)/include/funding.texi \ ++ $(gcc_docdir)/include/fdl.texi $(gcc_docdir)/include/gcc-common.texi gcc-vers.texi ++INFO_GCJ_NAME = $(shell echo gcj|sed '$(program_transform_name)') + +-java.srcinfo: doc/gcj.info ++java.info: doc/$(INFO_GCJ_NAME).info ++ ++java.srcinfo: doc/$(INFO_GCJ_NAME).info + -cp -p $^ $(srcdir)/doc + ++doc/$(INFO_GCJ_NAME).info: $(TEXI_GCJ_FILES) ++ if test "x$(BUILD_INFO)" = xinfo; then \ ++ rm -f $(@)*; \ ++ $(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) \ ++ -I$(gcc_docdir)/include -I$(srcdir)/f -o$@ $<; \ ++ fi ++ + java.dvi: doc/gcj.dvi + + JAVA_PDFFILES = doc/gcj.pdf +@@ -193,7 +205,7 @@ + -rm -rf $(DESTDIR)$(man1dir)/aot-compile$(man1ext) + -rm -rf $(DESTDIR)$(man1dir)/rebuild-gcj-db$(man1ext) + +-java.install-info: $(DESTDIR)$(infodir)/gcj.info ++java.install-info: $(DESTDIR)$(infodir)/$(INFO_GCJ_NAME).info + + java.install-pdf: $(JAVA_PDFFILES) + @$(NORMAL_INSTALL) +--- a/src/gcc/java/gcj.texi.orig 2009-08-13 ++++ b/src/gcc/java/gcj.texi 2009-12-20 +@@ -55,25 +55,25 @@ + @format + @dircategory Software development + @direntry +-* Gcj: (gcj). Ahead-of-time compiler for the Java language ++* @value{fngcj}: (@value{fngcj}). Ahead-of-time compiler for the Java language + @end direntry + + @dircategory Individual utilities + @direntry +-* jcf-dump: (gcj)Invoking jcf-dump. ++* jcf-dump: (@value{fngcj}) Invoking jcf-dump. + Print information about Java class files +-* gij: (gcj)Invoking gij. GNU interpreter for Java bytecode +-* gcj-dbtool: (gcj)Invoking gcj-dbtool. ++* gij: (@value{fngcj}) Invoking gij. GNU interpreter for Java bytecode ++* gcj-dbtool: (@value{fngcj}) Invoking gcj-dbtool. + Tool for manipulating class file databases. +-* jv-convert: (gcj)Invoking jv-convert. ++* jv-convert: (@value{fngcj}) Invoking jv-convert. + Convert file from one encoding to another +-* grmic: (gcj)Invoking grmic. ++* grmic: (@value{fngcj}) Invoking grmic. + Generate stubs for Remote Method Invocation. +-* gc-analyze: (gcj)Invoking gc-analyze. ++* gc-analyze: (@value{fngcj}) Invoking gc-analyze. + Analyze Garbage Collector (GC) memory dumps. +-* aot-compile: (gcj)Invoking aot-compile. ++* aot-compile: (@value{fngcj})Invoking aot-compile. + Compile bytecode to native and generate databases. +-* rebuild-gcj-db: (gcj)Invoking rebuild-gcj-db. ++* rebuild-gcj-db: (@value{fngcj})Invoking rebuild-gcj-db. + Merge the per-solib databases made by aot-compile + into one system-wide database. + @end direntry +@@ -159,7 +159,7 @@ + + As @command{gcj} is just another front end to @command{gcc}, it supports many + of the same options as gcc. @xref{Option Summary, , Option Summary, +-gcc, Using the GNU Compiler Collection (GCC)}. This manual only documents the ++@value{fngcc}, Using the GNU Compiler Collection (GCC)}. This manual only documents the + options specific to @command{gcj}. + + @c man end +--- a/src/gcc/fortran/gfortran.texi.orig 2009-12-17 ++++ b/src/gcc/fortran/gfortran.texi 2009-12-20 +@@ -101,7 +101,7 @@ + @ifinfo + @dircategory Software development + @direntry +-* gfortran: (gfortran). The GNU Fortran Compiler. ++* @value{fngfortran}: (@value{fngfortran}). The GNU Fortran Compiler. + @end direntry + This file documents the use and the internals of + the GNU Fortran compiler, (@command{gfortran}). +--- a/src/gcc/fortran/Make-lang.in.orig 2009-07-18 ++++ b/src/gcc/fortran/Make-lang.in 2009-12-20 +@@ -116,7 +116,8 @@ + cd $(srcdir)/fortran; etags -o TAGS.sub *.c *.h; \ + etags --include TAGS.sub --include ../TAGS.sub + +-fortran.info: doc/gfortran.info doc/gfc-internals.info ++INFO_FORTRAN_NAME = $(shell echo gfortran|sed '$(program_transform_name)') ++fortran.info: doc/$(INFO_FORTRAN_NAME).info + fortran.dvi: doc/gfortran.dvi doc/gfc-internals.dvi + fortran.html: $(build_htmldir)/gfortran/index.html + +@@ -165,10 +166,10 @@ + $(srcdir)/doc/include/gcc-common.texi \ + gcc-vers.texi + +-doc/gfortran.info: $(GFORTRAN_TEXI) ++doc/$(INFO_FORTRAN_NAME).info: $(GFORTRAN_TEXI) + if [ x$(BUILD_INFO) = xinfo ]; then \ + rm -f doc/gfortran.info-*; \ +- $(MAKEINFO) -I $(srcdir)/doc/include -I $(srcdir)/fortran \ ++ $(MAKEINFO) $(MAKEINFODEFS) -I $(srcdir)/doc/include -I $(srcdir)/fortran \ + -o $@ $<; \ + else true; fi + +@@ -236,7 +237,7 @@ + + fortran.install-plugin: + +-fortran.install-info: $(DESTDIR)$(infodir)/gfortran.info ++fortran.install-info: $(DESTDIR)$(infodir)/$(INFO_FORTRAN_NAME).info + + fortran.install-man: $(DESTDIR)$(man1dir)/$(GFORTRAN_INSTALL_NAME)$(man1ext) + +@@ -254,7 +255,7 @@ + rm -rf $(DESTDIR)$(bindir)/$(GFORTRAN_INSTALL_NAME)$(exeext); \ + rm -rf $(DESTDIR)$(man1dir)/$(GFORTRAN_INSTALL_NAME)$(man1ext); \ + rm -rf $(DESTDIR)$(bindir)/$(GFORTRAN_TARGET_INSTALL_NAME)$(exeext); \ +- rm -rf $(DESTDIR)$(infodir)/gfortran.info* ++ rm -rf $(DESTDIR)$(infodir)/$(INFO_FORTRAN_NAME).info* + + # + # Clean hooks: +--- a/src/gcc/Makefile.in.orig 2009-12-19 ++++ b/src/gcc/Makefile.in 2009-12-20 +@@ -3953,8 +3953,27 @@ + + doc: $(BUILD_INFO) $(GENERATED_MANPAGES) gccbug + +-INFOFILES = doc/cpp.info doc/gcc.info doc/gccint.info \ +- doc/gccinstall.info doc/cppinternals.info ++INFO_CPP_NAME = $(shell echo cpp|sed '$(program_transform_name)') ++INFO_GCC_NAME = $(shell echo gcc|sed '$(program_transform_name)') ++INFO_GXX_NAME = $(shell echo g++|sed '$(program_transform_name)') ++INFO_GCCINT_NAME = $(shell echo gccint|sed '$(program_transform_name)') ++INFO_GCCINSTALL_NAME = $(shell echo gccinstall|sed '$(program_transform_name)') ++INFO_CPPINT_NAME = $(shell echo cppinternals|sed '$(program_transform_name)') ++ ++INFO_FORTRAN_NAME = $(shell echo gfortran|sed '$(program_transform_name)') ++INFO_GCJ_NAME = $(shell echo gcj|sed '$(program_transform_name)') ++ ++INFOFILES = doc/$(INFO_CPP_NAME).info doc/$(INFO_GCC_NAME).info \ ++ doc/$(INFO_GCCINT_NAME).info \ ++ doc/$(INFO_GCCINSTALL_NAME).info doc/$(INFO_CPPINT_NAME).info ++ ++MAKEINFODEFS = -D 'fncpp $(INFO_CPP_NAME)' -D 'fngcc $(INFO_GCC_NAME)' \ ++ -D 'fngxx $(INFO_GXX_NAME)' \ ++ -D 'fngccint $(INFO_GCCINT_NAME)' \ ++ -D 'fngccinstall $(INFO_GCCINSTALL_NAME)' \ ++ -D 'fncppint $(INFO_CPPINT_NAME)' \ ++ -D 'fngfortran $(INFO_FORTRAN_NAME)' \ ++ -D 'fngcj $(INFO_GCJ_NAME)' + + info: $(INFOFILES) lang.info @GENINSRC@ srcinfo lang.srcinfo + +@@ -4004,21 +4023,41 @@ + # patterns. To use them, put each of the specific targets with its + # specific dependencies but no build commands. + +-doc/cpp.info: $(TEXI_CPP_FILES) +-doc/gcc.info: $(TEXI_GCC_FILES) +-doc/gccint.info: $(TEXI_GCCINT_FILES) +-doc/cppinternals.info: $(TEXI_CPPINT_FILES) +- ++# Generic entry to handle info files, which are not renamed (currently Ada) + doc/%.info: %.texi + if [ x$(BUILD_INFO) = xinfo ]; then \ + $(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \ + -I $(gcc_docdir)/include -o $@ $<; \ + fi + ++doc/$(INFO_CPP_NAME).info: $(TEXI_CPP_FILES) ++ if [ x$(BUILD_INFO) = xinfo ]; then \ ++ $(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \ ++ -I $(gcc_docdir)/include -o $@ $<; \ ++ fi ++ ++doc/$(INFO_GCC_NAME).info: $(TEXI_GCC_FILES) ++ if [ x$(BUILD_INFO) = xinfo ]; then \ ++ $(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \ ++ -I $(gcc_docdir)/include -o $@ $<; \ ++ fi ++ ++doc/$(INFO_GCCINT_NAME).info: $(TEXI_GCCINT_FILES) ++ if [ x$(BUILD_INFO) = xinfo ]; then \ ++ $(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \ ++ -I $(gcc_docdir)/include -o $@ $<; \ ++ fi ++ ++doc/$(INFO_CPPINT_NAME).info: $(TEXI_CPPINT_FILES) ++ if [ x$(BUILD_INFO) = xinfo ]; then \ ++ $(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \ ++ -I $(gcc_docdir)/include -o $@ $<; \ ++ fi ++ + # Duplicate entry to handle renaming of gccinstall.info +-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES) ++doc/$(INFO_GCCINSTALL_NAME).info: $(TEXI_GCCINSTALL_FILES) + if [ x$(BUILD_INFO) = xinfo ]; then \ +- $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \ ++ $(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \ + -I $(gcc_docdir)/include -o $@ $<; \ + fi + +@@ -4365,11 +4404,11 @@ + # $(INSTALL_DATA) might be a relative pathname, so we can't cd into srcdir + # to do the install. + install-info:: doc installdirs \ +- $(DESTDIR)$(infodir)/cpp.info \ +- $(DESTDIR)$(infodir)/gcc.info \ +- $(DESTDIR)$(infodir)/cppinternals.info \ +- $(DESTDIR)$(infodir)/gccinstall.info \ +- $(DESTDIR)$(infodir)/gccint.info \ ++ $(DESTDIR)$(infodir)/$(INFO_CPP_NAME).info \ ++ $(DESTDIR)$(infodir)/$(INFO_GCC_NAME).info \ ++ $(DESTDIR)$(infodir)/$(INFO_CPPINT_NAME).info \ ++ $(DESTDIR)$(infodir)/$(INFO_GCCINSTALL_NAME).info \ ++ $(DESTDIR)$(infodir)/$(INFO_GCCINT_NAME).info \ + lang.install-info + + $(DESTDIR)$(infodir)/%.info: doc/%.info installdirs +@@ -4561,8 +4600,11 @@ + -rm -rf $(DESTDIR)$(bindir)/$(GCOV_INSTALL_NAME)$(exeext) + -rm -rf $(DESTDIR)$(man1dir)/$(GCC_INSTALL_NAME)$(man1ext) + -rm -rf $(DESTDIR)$(man1dir)/cpp$(man1ext) +- -rm -f $(DESTDIR)$(infodir)/cpp.info* $(DESTDIR)$(infodir)/gcc.info* +- -rm -f $(DESTDIR)$(infodir)/cppinternals.info* $(DESTDIR)$(infodir)/gccint.info* ++ -rm -f $(DESTDIR)$(infodir)/$(INFO_CPP_NAME).info* ++ -rm -f $(DESTDIR)$(infodir)/$(INFO_GCC_NAME).info* ++ -rm -f $(DESTDIR)$(infodir)/$(INFO_CPPINT_NAME).info* ++ -rm -f $(DESTDIR)$(infodir)/$(INFO_GCCINT_NAME).info* ++ -rm -f $(DESTDIR)$(infodir)/$(INFO_GCCINSTALL_NAME).info* + # + # These targets are for the dejagnu testsuites. The file site.exp + # contains global variables that all the testsuites will use. +--- a/src/libgomp/libgomp.texi.orig 2008-11-08 ++++ b/src/libgomp/libgomp.texi 2009-12-20 +@@ -31,7 +31,7 @@ + @ifinfo + @dircategory GNU Libraries + @direntry +-* libgomp: (libgomp). GNU OpenMP runtime library ++* @value{fnlibgomp}: (@value{fnlibgomp}). GNU OpenMP runtime library + @end direntry + + This manual documents the GNU implementation of the OpenMP API for +--- a/src/libgomp/Makefile.am.orig 2009-09-11 ++++ b/src/libgomp/Makefile.am 2009-12-20 +@@ -85,16 +85,19 @@ + + all-local: $(STAMP_GENINSRC) + +-stamp-geninsrc: libgomp.info +- cp -p $(top_builddir)/libgomp.info $(srcdir)/libgomp.info ++INFO_LIBGOMP_NAME = $(shell echo libgomp|sed '$(program_transform_name)') ++stamp-geninsrc: $(INFO_LIBGOMP_NAME).info ++ cp -p $(top_builddir)/$(INFO_LIBGOMP_NAME).info $(srcdir)/libgomp.info + @touch $@ + +-libgomp.info: $(STAMP_BUILD_INFO) ++libgomp.info: $(INFO_LIBGOMP_NAME).info ++ cp $(INFO_LIBGOMP_NAME).info libgomp.info ++$(INFO_LIBGOMP_NAME).info: $(STAMP_BUILD_INFO) + + stamp-build-info: libgomp.texi +- $(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libgomp.info $(srcdir)/libgomp.texi ++ $(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -D 'fnlibgomp $(INFO_LIBGOMP_NAME)' -I $(srcdir) -o $(INFO_LIBGOMP_NAME).info $(srcdir)/libgomp.texi + @touch $@ + + +-CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) libgomp.info ++CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) $(INFO_LIBGOMP_NAME).info + MAINTAINERCLEANFILES = $(srcdir)/libgomp.info +--- a/src/libgomp/Makefile.in.orig 2009-12-07 ++++ b/src/libgomp/Makefile.in 2009-12-20 +@@ -375,7 +375,8 @@ + + # AM_CONDITIONAL on configure check ACX_CHECK_PROG_VER([MAKEINFO]) + @BUILD_INFO_TRUE@STAMP_BUILD_INFO = stamp-build-info +-CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) libgomp.info ++INFO_LIBGOMP_NAME = $(shell echo libgomp|sed '$(program_transform_name)') ++CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) $(INFO_LIBGOMP_NAME).info + MAINTAINERCLEANFILES = $(srcdir)/libgomp.info + all: config.h + $(MAKE) $(AM_MAKEFLAGS) all-recursive +@@ -1290,15 +1291,16 @@ + env.o: libgomp_f.h + + all-local: $(STAMP_GENINSRC) +- +-stamp-geninsrc: libgomp.info +- cp -p $(top_builddir)/libgomp.info $(srcdir)/libgomp.info ++stamp-geninsrc: $(INFO_LIBGOMP_NAME).info ++ cp -p $(top_builddir)/$(INFO_LIBGOMP_NAME).info $(srcdir)/libgomp.info + @touch $@ + +-libgomp.info: $(STAMP_BUILD_INFO) ++libgomp.info: $(INFO_LIBGOMP_NAME).info ++ [ "$(INFO_LIBGOMP_NAME).info" = libgomp.info ] || cp $(INFO_LIBGOMP_NAME).info libgomp.info ++$(INFO_LIBGOMP_NAME).info: $(STAMP_BUILD_INFO) + + stamp-build-info: libgomp.texi +- $(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libgomp.info $(srcdir)/libgomp.texi ++ $(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -D 'fnlibgomp $(INFO_LIBGOMP_NAME)' -I $(srcdir) -o $(INFO_LIBGOMP_NAME).info $(srcdir)/libgomp.texi + @touch $@ + + # Tell versions [3.59,3.63) of GNU make to not export all variables. --- gcc-4.5-4.5.2.orig/debian/patches/cross-fixes.diff +++ gcc-4.5-4.5.2/debian/patches/cross-fixes.diff @@ -0,0 +1,90 @@ +# DP: Fix the linker error when creating an xcc for ia64 + +--- + gcc/config/alpha/linux-unwind.h | 3 +++ + gcc/config/ia64/fde-glibc.c | 3 +++ + gcc/config/ia64/unwind-ia64.c | 3 ++- + gcc/unwind-compat.c | 2 ++ + gcc/unwind-generic.h | 2 ++ + 6 files changed, 14 insertions(+), 1 deletions(-) + +--- a/src/gcc/config/alpha/linux-unwind.h ++++ b/src/gcc/config/alpha/linux-unwind.h +@@ -29,6 +29,7 @@ Boston, MA 02110-1301, USA. */ + /* Do code reading to identify a signal frame, and set the frame + state data appropriately. See unwind-dw2.c for the structs. */ + ++#ifndef inhibit_libc + #include + #include + +@@ -80,3 +81,5 @@ alpha_fallback_frame_state (struct _Unwind_Context *context, + fs->retaddr_column = 64; + return _URC_NO_REASON; + } ++ ++#endif +--- a/src/gcc/config/ia64/fde-glibc.c ++++ b/src/gcc/config/ia64/fde-glibc.c +@@ -31,6 +31,7 @@ + #ifndef _GNU_SOURCE + #define _GNU_SOURCE 1 + #endif ++#ifndef inhibit_libc + #include "config.h" + #include + #include +@@ -162,3 +163,5 @@ _Unwind_FindTableEntry (void *pc, unsigned long *segment_base, + + return data.ret; + } ++ ++#endif +--- a/src/gcc/config/ia64/unwind-ia64.c ++++ b/src/gcc/config/ia64/unwind-ia64.c +@@ -27,6 +27,7 @@ + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + ++#ifndef inhibit_libc + #include "tconfig.h" + #include "tsystem.h" + #include "coretypes.h" +@@ -2417,3 +2417,4 @@ alias (_Unwind_SetIP); + #endif + + #endif ++#endif +--- a/src/gcc/unwind-compat.c ++++ b/src/gcc/unwind-compat.c +@@ -29,6 +29,7 @@ + 02110-1301, USA. */ + + #if defined (USE_GAS_SYMVER) && defined (USE_LIBUNWIND_EXCEPTIONS) ++#ifndef inhibit_libc + #include "tconfig.h" + #include "tsystem.h" + #include "unwind.h" +@@ -213,3 +214,4 @@ _Unwind_SetIP (struct _Unwind_Context *context, _Unwind_Ptr val) + } + symver (_Unwind_SetIP, GCC_3.0); + #endif ++#endif +--- a/src/gcc/unwind-generic.h ++++ b/src/gcc/unwind-generic.h +@@ -214,6 +214,7 @@ _Unwind_SjLj_Resume_or_Rethrow (struct _Unwind_Exception *); + compatible with the standard ABI for IA-64, we inline these. */ + + #ifdef __ia64__ ++#ifndef inhibit_libc + #include + + static inline _Unwind_Ptr +@@ -232,6 +233,7 @@ _Unwind_GetTextRelBase (struct _Unwind_Context *_C __attribute__ ((__unused__))) + + /* @@@ Retrieve the Backing Store Pointer of the given context. */ + extern _Unwind_Word _Unwind_GetBSP (struct _Unwind_Context *); ++#endif + #else + extern _Unwind_Ptr _Unwind_GetDataRelBase (struct _Unwind_Context *); + extern _Unwind_Ptr _Unwind_GetTextRelBase (struct _Unwind_Context *); --- gcc-4.5-4.5.2.orig/debian/patches/gcc-powerpc-nof.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-powerpc-nof.diff @@ -0,0 +1,24 @@ +# DP: Don't build nof multlib on powerpc. + +--- a/src/gcc/config/rs6000/t-linux64~ 2010-04-05 21:47:52.681086416 +0000 ++++ b/src/gcc/config/rs6000/t-linux64 2010-04-05 21:51:34.531670412 +0000 +@@ -31,13 +31,13 @@ + # it doesn't tell anything about the 32bit libraries on those systems. Set + # MULTILIB_OSDIRNAMES according to what is found on the target. + +-MULTILIB_OPTIONS = m64/m32 msoft-float +-MULTILIB_DIRNAMES = 64 32 nof ++MULTILIB_OPTIONS = m64/m32 ++MULTILIB_DIRNAMES = 64 32 + MULTILIB_EXTRA_OPTS = fPIC mstrict-align +-MULTILIB_EXCEPTIONS = m64/msoft-float +-MULTILIB_EXCLUSIONS = m64/!m32/msoft-float +-MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) nof +-MULTILIB_MATCHES = $(MULTILIB_MATCHES_FLOAT) ++MULTILIB_EXCEPTIONS = ++MULTILIB_EXCLUSIONS = ++MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) ++MULTILIB_MATCHES = + + softfp_wrap_start := '\#ifndef __powerpc64__' + softfp_wrap_end := '\#endif' --- gcc-4.5-4.5.2.orig/debian/patches/libjava-disable-static.diff +++ gcc-4.5-4.5.2/debian/patches/libjava-disable-static.diff @@ -0,0 +1,26 @@ +# DP: Disable building the static libjava. + +--- + Makefile.in | 4 ++-- + 1 files changed, 2 insertions(+), 2 deletions(-) + +--- a/src/Makefile.in ++++ b/src/Makefile.in +@@ -49463,7 +49463,7 @@ configure-target-libjava: + rm -f no-such-file || : ; \ + CONFIG_SITE=no-such-file $(SHELL) $${libsrcdir}/configure \ + $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \ +- --target=${target_alias} $${srcdiroption} \ ++ --target=${target_alias} --disable-static $${srcdiroption} \ + || exit 1 + @endif target-libjava + +@@ -50347,7 +50347,7 @@ configure-target-boehm-gc: + rm -f no-such-file || : ; \ + CONFIG_SITE=no-such-file $(SHELL) $${libsrcdir}/configure \ + $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \ +- --target=${target_alias} $${srcdiroption} \ ++ --target=${target_alias} --disable-static $${srcdiroption} \ + || exit 1 + @endif target-boehm-gc + --- gcc-4.5-4.5.2.orig/debian/patches/pr40521-sequel.diff +++ gcc-4.5-4.5.2/debian/patches/pr40521-sequel.diff @@ -0,0 +1,107 @@ +# DP: Sequel to PR40521 -- -g causes GCC to generate .eh_frame + +gcc/ +2010-03-31 Thomas Schwinge + Daniel Jacobowitz + + PR debug/40521 + * doc/tm.texi (DWARF2_UNWIND_INFO, TARGET_UNWIND_INFO): Improve. + * dwarf2out.c (NEED_UNWIND_TABLES): Define. + (dwarf2out_do_frame, dwarf2out_do_cfi_asm, dwarf2out_begin_prologue) + (dwarf2out_frame_finish, dwarf2out_assembly_start): Use it. + (dwarf2out_assembly_start): Correct logic for TARGET_UNWIND_INFO. + * config/arm/arm.h (DWARF2_UNWIND_INFO): Remove definition. + * config/arm/bpabi.h (DWARF2_UNWIND_INFO): Define to zero. + +--- a/src/gcc/dwarf2out.c.orig 2010-04-01 21:45:02.000000000 +0200 ++++ b/src/gcc/dwarf2out.c 2010-04-18 15:25:47.482337489 +0200 +@@ -124,6 +124,9 @@ + # endif + #endif + ++#define NEED_UNWIND_TABLES \ ++ (flag_unwind_tables || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS)) ++ + /* Map register numbers held in the call frame info that gcc has + collected using DWARF_FRAME_REGNUM to those that should be output in + .debug_frame and .eh_frame. */ +@@ -147,9 +150,7 @@ + || write_symbols == VMS_AND_DWARF2_DEBUG + || DWARF2_FRAME_INFO || saved_do_cfi_asm + #ifdef DWARF2_UNWIND_INFO +- || (DWARF2_UNWIND_INFO +- && (flag_unwind_tables +- || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS))) ++ || (DWARF2_UNWIND_INFO && NEED_UNWIND_TABLES) + #endif + ); + } +@@ -185,7 +186,7 @@ + #ifdef TARGET_UNWIND_INFO + return false; + #else +- if (USING_SJLJ_EXCEPTIONS || (!flag_unwind_tables && !flag_exceptions)) ++ if (!NEED_UNWIND_TABLES) + return false; + #endif + } +@@ -3905,8 +3906,7 @@ + /* ??? current_function_func_begin_label is also used by except.c + for call-site information. We must emit this label if it might + be used. */ +- if ((! flag_exceptions || USING_SJLJ_EXCEPTIONS) +- && ! dwarf2out_do_frame ()) ++ if (! NEED_UNWIND_TABLES && ! dwarf2out_do_frame ()) + return; + #else + if (! dwarf2out_do_frame ()) +@@ -4066,7 +4066,7 @@ + + #ifndef TARGET_UNWIND_INFO + /* Output another copy for the unwinder. */ +- if (! USING_SJLJ_EXCEPTIONS && (flag_unwind_tables || flag_exceptions)) ++ if (NEED_UNWIND_TABLES) + output_call_frame_info (1); + #endif + } +@@ -20700,10 +20700,15 @@ + { + if (HAVE_GAS_CFI_SECTIONS_DIRECTIVE && dwarf2out_do_cfi_asm ()) + { +-#ifndef TARGET_UNWIND_INFO +- if (USING_SJLJ_EXCEPTIONS || (!flag_unwind_tables && !flag_exceptions)) +-#endif ++#ifdef TARGET_UNWIND_INFO ++ /* We're only ever interested in .debug_frame. */ ++ fprintf (asm_out_file, "\t.cfi_sections\t.debug_frame\n"); ++#else ++ /* GAS defaults to emitting .eh_frame only, and .debug_frame is not ++ wanted in case that the former one is present. */ ++ if (! NEED_UNWIND_TABLES) + fprintf (asm_out_file, "\t.cfi_sections\t.debug_frame\n"); ++#endif + } + } + +--- a/src/gcc/config/arm/arm.h.orig 2009-12-23 17:36:40.000000000 +0100 ++++ b/src/gcc/config/arm/arm.h 2010-04-18 15:25:47.471085014 +0200 +@@ -918,9 +918,6 @@ + #define MUST_USE_SJLJ_EXCEPTIONS 1 + #endif + +-/* We can generate DWARF2 Unwind info, even though we don't use it. */ +-#define DWARF2_UNWIND_INFO 1 +- + /* Use r0 and r1 to pass exception handling information. */ + #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) + +--- a/src/gcc/config/arm/bpabi.h.orig 2009-11-20 18:37:30.000000000 +0100 ++++ b/src/gcc/config/arm/bpabi.h 2010-04-18 15:25:47.471085014 +0200 +@@ -26,6 +26,7 @@ + #define TARGET_BPABI (TARGET_AAPCS_BASED) + + /* BPABI targets use EABI frame unwinding tables. */ ++#define DWARF2_UNWIND_INFO 0 + #define TARGET_UNWIND_INFO 1 + + /* Section 4.1 of the AAPCS requires the use of VFP format. */ --- gcc-4.5-4.5.2.orig/debian/patches/testsuite-hardening-printf-types.diff +++ gcc-4.5-4.5.2/debian/patches/testsuite-hardening-printf-types.diff @@ -0,0 +1,662 @@ +#! /bin/sh -e + +# All lines beginning with `# DPATCH:' are a description of the patch. +# DP: Description: adjust/standardize printf types to avoid -Wformat warnings. +# DP: Author: Kees Cook +# DP: Ubuntu: https://bugs.launchpad.net/bugs/344502 + +dir= +if [ $# -eq 3 -a "$2" = '-d' ]; then + pdir="-d $3" + dir="$3/" +elif [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi +case "$1" in + -patch) + patch $pdir -f --no-backup-if-mismatch -p1 < $0 + #cd ${dir}gcc && autoconf + ;; + -unpatch) + patch $pdir -f --no-backup-if-mismatch -R -p1 < $0 + #rm ${dir}gcc/configure + ;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +esac +exit 0 + +diff -uNrp a/src/gcc/testsuite/g++.dg/ext/align1.C b/src/gcc/testsuite/g++.dg/ext/align1.C +--- a/src/gcc/testsuite/g++.dg/ext/align1.C 2002-02-06 08:18:33.000000000 -0800 ++++ b/src/gcc/testsuite/g++.dg/ext/align1.C 2009-03-17 13:40:03.000000000 -0700 +@@ -16,6 +16,7 @@ float f1 __attribute__ ((aligned)); + int + main (void) + { +- printf ("%d %d\n", __alignof (a1), __alignof (f1)); ++ // "%td" is not allowed by ISO C++, so use %p with a void * cast ++ printf ("%p %p\n", (void*)__alignof (a1), (void*)__alignof (f1)); + return (__alignof (a1) < __alignof (f1)); + } +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.law/operators28.C b/src/gcc/testsuite/g++.old-deja/g++.law/operators28.C +--- a/src/gcc/testsuite/g++.old-deja/g++.law/operators28.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.law/operators28.C 2009-03-17 13:40:03.000000000 -0700 +@@ -14,7 +14,8 @@ void* new_test::operator new(size_t sz, + { + void *p; + +- printf("%d %d %d\n", sz, count, type); ++ // ISO C++ does not support format size modifier "z", so use a cast ++ printf("%u %d %d\n", (unsigned int)sz, count, type); + + p = new char[sz * count]; + ((new_test *)p)->type = type; +diff -uNrp a/src/gcc/testsuite/gcc.dg/matrix/matrix-2.c b/src/gcc/testsuite/gcc.dg/matrix/matrix-2.c +--- a/src/gcc/testsuite/gcc.dg/matrix/matrix-2.c 2007-05-28 04:27:34.000000000 -0700 ++++ b/src/gcc/testsuite/gcc.dg/matrix/matrix-2.c 2009-03-17 17:10:34.000000000 -0700 +@@ -42,7 +42,7 @@ main (int argc, char **argv) + } + for (i = 0; i < ARCHnodes; i++) + for (j = 0; j < 3; j++) +- printf ("%x\n",vel[i][j]); ++ printf ("%p\n",vel[i][j]); + /*if (i!=1 || j!=1)*/ + /*if (i==1 && j==1) + continue; +@@ -83,14 +83,14 @@ mem_init (void) + for (j = 0; j < 3; j++) + { + vel[i][j] = (int *) malloc (ARCHnodes1 * sizeof (int)); +- printf ("%x %d %d\n",vel[i][j], ARCHnodes1, sizeof (int)); ++ printf ("%p %d %d\n",vel[i][j], ARCHnodes1, (int)sizeof (int)); + } + } + for (i = 0; i < ARCHnodes; i++) + { + for (j = 0; j < 3; j++) + { +- printf ("%x\n",vel[i][j]); ++ printf ("%p\n",vel[i][j]); + } + } + +@@ -99,7 +99,7 @@ mem_init (void) + { + for (j = 0; j < 3; j++) + { +- printf ("%x\n",vel[i][j]); ++ printf ("%p\n",vel[i][j]); + /*for (k = 0; k < ARCHnodes1; k++) + { + vel[i][j][k] = d; +diff -uNrp a/src/gcc/testsuite/gcc.dg/packed-vla.c b/src/gcc/testsuite/gcc.dg/packed-vla.c +--- a/src/gcc/testsuite/gcc.dg/packed-vla.c 2007-09-11 08:08:57.000000000 -0700 ++++ b/src/gcc/testsuite/gcc.dg/packed-vla.c 2009-03-17 17:00:46.000000000 -0700 +@@ -17,8 +17,8 @@ int func(int levels) + int b[4]; + } __attribute__ ((__packed__)) foo; + +- printf("foo %d\n", sizeof(foo)); +- printf("bar %d\n", sizeof(bar)); ++ printf("foo %d\n", (int)sizeof(foo)); ++ printf("bar %d\n", (int)sizeof(bar)); + + if (sizeof (foo) != sizeof (bar)) + abort (); +diff -uNrp a/src/gcc/testsuite/g++.dg/opt/alias2.C b/src/gcc/testsuite/g++.dg/opt/alias2.C +--- a/src/gcc/testsuite/g++.dg/opt/alias2.C 2005-04-25 11:28:55.000000000 -0700 ++++ b/src/gcc/testsuite/g++.dg/opt/alias2.C 2009-03-17 13:40:03.000000000 -0700 +@@ -30,14 +30,14 @@ public: + + + _Deque_base::~_Deque_base() { +- printf ("bb %x %x\n", this, *_M_start._M_node); ++ printf ("bb %p %x\n", this, *_M_start._M_node); + } + + void + _Deque_base::_M_initialize_map() + { + yy = 0x123; +- printf ("aa %x %x\n", this, yy); ++ printf ("aa %p %x\n", this, yy); + + _M_start._M_node = &yy; + _M_start._M_cur = yy; +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.abi/vbase1.C b/src/gcc/testsuite/g++.old-deja/g++.abi/vbase1.C +--- a/src/gcc/testsuite/g++.old-deja/g++.abi/vbase1.C 2003-07-01 05:01:44.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.abi/vbase1.C 2009-03-17 13:40:03.000000000 -0700 +@@ -33,7 +33,7 @@ struct VBase + void Offset () const + { + printf ("VBase\n"); +- printf (" VBase::member %d\n", &this->VBase::member - (int *)this); ++ printf (" VBase::member %d\n", (int)(&this->VBase::member - (int *)this)); + } + }; + +@@ -55,8 +55,8 @@ struct VDerived : virtual VBase + void Offset () const + { + printf ("VDerived\n"); +- printf (" VBase::member %d\n", &this->VBase::member - (int *)this); +- printf (" VDerived::member %d\n", &this->VDerived::member - (int *)this); ++ printf (" VBase::member %d\n", (int)(&this->VBase::member - (int *)this)); ++ printf (" VDerived::member %d\n", (int)(&this->VDerived::member - (int *)this)); + } + }; + struct B : virtual VBase +@@ -65,8 +65,8 @@ struct B : virtual VBase + void Offset () const + { + printf ("B\n"); +- printf (" VBase::member %d\n", &this->VBase::member - (int *)this); +- printf (" B::member %d\n", &this->B::member - (int *)this); ++ printf (" VBase::member %d\n", (int)(&this->VBase::member - (int *)this)); ++ printf (" B::member %d\n", (int)(&this->B::member - (int *)this)); + } + }; + struct MostDerived : B, virtual VDerived +@@ -75,10 +75,10 @@ struct MostDerived : B, virtual VDerived + void Offset () const + { + printf ("MostDerived\n"); +- printf (" VBase::member %d\n", &this->VBase::member - (int *)this); +- printf (" B::member %d\n", &this->B::member - (int *)this); +- printf (" VDerived::member %d\n", &this->VDerived::member - (int *)this); +- printf (" MostDerived::member %d\n", &this->MostDerived::member - (int *)this); ++ printf (" VBase::member %d\n", (int)(&this->VBase::member - (int *)this)); ++ printf (" B::member %d\n", (int)(&this->B::member - (int *)this)); ++ printf (" VDerived::member %d\n", (int)(&this->VDerived::member - (int *)this)); ++ printf (" MostDerived::member %d\n", (int)(&this->MostDerived::member - (int *)this)); + } + }; + +@@ -95,10 +95,10 @@ int main () + if (ctorVDerived != &dum.VDerived::member) + return 24; + +- printf (" VBase::member %d\n", &dum.VBase::member - this_); +- printf (" B::member %d\n", &dum.B::member - this_); +- printf (" VDerived::member %d\n", &dum.VDerived::member - this_); +- printf (" MostDerived::member %d\n", &dum.MostDerived::member - this_); ++ printf (" VBase::member %d\n", (int)(&dum.VBase::member - this_)); ++ printf (" B::member %d\n", (int)(&dum.B::member - this_)); ++ printf (" VDerived::member %d\n", (int)(&dum.VDerived::member - this_)); ++ printf (" MostDerived::member %d\n", (int)(&dum.MostDerived::member - this_)); + dum.MostDerived::Offset (); + dum.B::Offset (); + dum.VDerived::Offset (); +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.brendan/template8.C b/src/gcc/testsuite/g++.old-deja/g++.brendan/template8.C +--- a/src/gcc/testsuite/g++.old-deja/g++.brendan/template8.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.brendan/template8.C 2009-03-17 13:40:03.000000000 -0700 +@@ -15,6 +15,6 @@ int main(){ + + Double_alignt<20000> heap; + +- printf(" &heap.array[0] = %d, &heap.for_alignt = %d\n", &heap.array[0], &heap.for_alignt); ++ printf(" &heap.array[0] = %p, &heap.for_alignt = %p\n", (void*)&heap.array[0], (void*)&heap.for_alignt); + + } +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.eh/ptr1.C b/src/gcc/testsuite/g++.old-deja/g++.eh/ptr1.C +--- a/src/gcc/testsuite/g++.old-deja/g++.eh/ptr1.C 2007-03-22 12:44:09.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.eh/ptr1.C 2009-03-17 16:08:59.000000000 -0700 +@@ -16,7 +16,7 @@ int main() + } + + catch (E *&e) { +- printf ("address of e is 0x%lx\n", (__SIZE_TYPE__)e); ++ printf ("address of e is %p\n", (void *)e); + return !((__SIZE_TYPE__)e != 5 && e->x == 5); + } + return 2; +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.jason/access23.C b/src/gcc/testsuite/g++.old-deja/g++.jason/access23.C +--- a/src/gcc/testsuite/g++.old-deja/g++.jason/access23.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.jason/access23.C 2009-03-17 13:40:03.000000000 -0700 +@@ -42,19 +42,19 @@ public: + void DoSomething() { + PUB_A = 0; + Foo::A = 0; +- printf("%x\n",pX); ++ printf("%p\n",pX); + Foo::PUB.A = 0; +- printf("%x\n",PUB.pX); ++ printf("%p\n",PUB.pX); + B = 0; +- printf("%x\n",Foo::pY); ++ printf("%p\n",Foo::pY); + PRT_A = 0; + PRT.B = 0; +- printf("%x\n",Foo::PRT.pY); ++ printf("%p\n",Foo::PRT.pY); + PRV_A = 0; // { dg-error "" } + Foo::C = 0; // { dg-error "" } +- printf("%x\n",pZ); // { dg-error "" } ++ printf("%p\n",pZ); // { dg-error "" } + Foo::PRV.C = 0; // { dg-error "" } +- printf("%x\n",PRV.pZ); // { dg-error "" } ++ printf("%p\n",PRV.pZ); // { dg-error "" } + } + }; + +@@ -64,17 +64,17 @@ int main() + + a.PUB_A = 0; + a.A = 0; +- printf("%x\n",a.pX); ++ printf("%p\n",a.pX); + a.PRT_A = 0; // { dg-error "" } + a.B = 0; // { dg-error "" } +- printf("%x\n",a.pY); // { dg-error "" } ++ printf("%p\n",a.pY); // { dg-error "" } + a.PRV_A = 0; // { dg-error "" } + a.C = 0; // { dg-error "" } +- printf("%x\n",a.pZ); // { dg-error "" } ++ printf("%p\n",a.pZ); // { dg-error "" } + a.PUB.A = 0; +- printf("%x\n",a.PUB.pX); ++ printf("%p\n",a.PUB.pX); + a.PRT.B = 0; // { dg-error "" } +- printf("%x\n",a.PRT.pY); // { dg-error "" } ++ printf("%p\n",a.PRT.pY); // { dg-error "" } + a.PRV.C = 0; // { dg-error "" } +- printf("%x\n",a.PRV.pZ); // { dg-error "" } ++ printf("%p\n",a.PRV.pZ); // { dg-error "" } + } +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.law/cvt8.C b/src/gcc/testsuite/g++.old-deja/g++.law/cvt8.C +--- a/src/gcc/testsuite/g++.old-deja/g++.law/cvt8.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.law/cvt8.C 2009-03-17 13:40:03.000000000 -0700 +@@ -20,12 +20,12 @@ struct B { + B::operator const A&() const { + static A a; + a.i = i; +- printf("convert B to A at %x\n", &a); ++ printf("convert B to A at %p\n", (void*)&a); + return a; + } + + void f(A &a) { // { dg-error "" } in passing argument +- printf("A at %x is %d\n", &a, a.i); ++ printf("A at %p is %d\n", (void*)&a, a.i); + } + + int main() { +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.mike/net35.C b/src/gcc/testsuite/g++.old-deja/g++.mike/net35.C +--- a/src/gcc/testsuite/g++.old-deja/g++.mike/net35.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/net35.C 2009-03-17 13:40:03.000000000 -0700 +@@ -17,10 +17,10 @@ public: + + int main() { + C c; +- printf("&c.x = %x\n", &c.x); +- printf("&c.B1::x = %x\n", &c.B1::x); +- printf("&c.B2::x = %x\n", &c.B2::x); +- printf("&c.A::x = %x\n", &c.A::x); ++ printf("&c.x = %p\n", (void*)&c.x); ++ printf("&c.B1::x = %p\n", (void*)&c.B1::x); ++ printf("&c.B2::x = %p\n", (void*)&c.B2::x); ++ printf("&c.A::x = %p\n", (void*)&c.A::x); + if (&c.x != &c.B1::x + || &c.x != &c.B2::x + || &c.x != &c.A::x) +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.mike/offset1.C b/src/gcc/testsuite/g++.old-deja/g++.mike/offset1.C +--- a/src/gcc/testsuite/g++.old-deja/g++.mike/offset1.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/offset1.C 2009-03-17 13:40:03.000000000 -0700 +@@ -6,7 +6,7 @@ int fail = 0; + class Foo { + public: + virtual void setName() { +- printf("Foo at %x\n", this); ++ printf("Foo at %p\n", (void*)this); + if (vp != (void*)this) + fail = 1; + } +@@ -15,7 +15,7 @@ public: + class Bar : public Foo { + public: + virtual void init(int argc, char **argv) { +- printf("Bar's Foo at %x\n", (Foo*)this); ++ printf("Bar's Foo at %p\n", (void*)(Foo*)this); + vp = (void*)(Foo*)this; + setName(); + } +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.mike/p12306.C b/src/gcc/testsuite/g++.old-deja/g++.mike/p12306.C +--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p12306.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p12306.C 2009-03-17 13:40:03.000000000 -0700 +@@ -18,7 +18,7 @@ public: + if (ptr2 != &(*this).slist) + fail = 6; + +- if (0) printf("at %x %x\n", (RWSlistIterator*)this, &(*this).slist); ++ if (0) printf("at %p %p\n", (void*)(RWSlistIterator*)this, (void*)&(*this).slist); + } + }; + +@@ -54,14 +54,14 @@ Sim_Event_Manager::Sim_Event_Manager () + void Sim_Event_Manager::post_event () { + ptr1 = (RWSlistIterator*)&last_posted_event_position_; + ptr2 = &((RWSlistIterator*)&last_posted_event_position_)->slist; +- if (0) printf("at %x %x\n", (RWSlistIterator*)&last_posted_event_position_, +- &((RWSlistIterator*)&last_posted_event_position_)->slist); ++ if (0) printf("at %p %p\n", (void*)(RWSlistIterator*)&last_posted_event_position_, ++ (void*)&((RWSlistIterator*)&last_posted_event_position_)->slist); + if (ptr1 != (RWSlistIterator*)&last_posted_event_position_) + fail = 1; + if (ptr2 != &((RWSlistIterator&)last_posted_event_position_).slist) + fail = 2; +- if (0) printf("at %x ?%x\n", (RWSlistIterator*)&last_posted_event_position_, +- &((RWSlistIterator&)last_posted_event_position_).slist); ++ if (0) printf("at %p ?%p\n", (void*)(RWSlistIterator*)&last_posted_event_position_, ++ (void*)&((RWSlistIterator&)last_posted_event_position_).slist); + if (ptr1 != (RWSlistIterator*)&last_posted_event_position_) + fail = 3; + if (ptr2 != &((RWSlistIterator&)last_posted_event_position_).slist) +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.mike/p3579.C b/src/gcc/testsuite/g++.old-deja/g++.mike/p3579.C +--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p3579.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p3579.C 2009-03-17 13:40:03.000000000 -0700 +@@ -7,26 +7,26 @@ int num_x; + + class Y { + public: +- Y () { printf("Y() this: %x\n", this); } +- ~Y () { printf("~Y() this: %x\n", this); } ++ Y () { printf("Y() this: %p\n", (void*)this); } ++ ~Y () { printf("~Y() this: %p\n", (void*)this); } + }; + + class X { + public: + X () { + ++num_x; +- printf("X() this: %x\n", this); ++ printf("X() this: %p\n", (void*)this); + Y y; + *this = (X) y; + } + +- X (const Y & yy) { printf("X(const Y&) this: %x\n", this); ++num_x; } ++ X (const Y & yy) { printf("X(const Y&) this: %p\n", (void*)this); ++num_x; } + X & operator = (const X & xx) { +- printf("X.op=(X&) this: %x\n", this); ++ printf("X.op=(X&) this: %p\n", (void*)this); + return *this; + } + +- ~X () { printf("~X() this: %x\n", this); --num_x; } ++ ~X () { printf("~X() this: %p\n", (void*)this); --num_x; } + }; + + int main (int, char **) { +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.mike/p3708a.C b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708a.C +--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p3708a.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708a.C 2009-03-17 13:40:03.000000000 -0700 +@@ -38,7 +38,7 @@ public: + virtual void xx(int doit) { + --num; + if (ptr != this) +- printf("FAIL\n%x != %x\n", ptr, this); ++ printf("FAIL\n%p != %p\n", ptr, (void*)this); + printf ("C is destructed.\n"); + B::xx (0); + if (doit) A::xx (1); +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.mike/p3708b.C b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708b.C +--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p3708b.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708b.C 2009-03-17 13:40:03.000000000 -0700 +@@ -48,7 +48,7 @@ public: + virtual void xx(int doit) { + --num; + if (ptr != this) { +- printf("FAIL\n%x != %x\n", ptr, this); ++ printf("FAIL\n%p != %p\n", ptr, (void*)this); + exit(1); + } + printf ("D is destructed.\n"); +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.mike/p3708.C b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708.C +--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p3708.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708.C 2009-03-17 13:40:03.000000000 -0700 +@@ -38,7 +38,7 @@ public: + virtual void xx(int doit) { + --num; + if (ptr != this) +- printf("FAIL\n%x != %x\n", ptr, this); ++ printf("FAIL\n%p != %p\n", ptr, (void*)this); + printf ("C is destructed.\n"); + B::xx (0); + if (doit) A::xx (1); +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.mike/p646.C b/src/gcc/testsuite/g++.old-deja/g++.mike/p646.C +--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p646.C 2006-02-05 01:21:29.000000000 -0800 ++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p646.C 2009-03-17 13:40:03.000000000 -0700 +@@ -35,20 +35,20 @@ int foo::si = 0; + foo::foo () + { + si++; +- printf ("new foo @ 0x%x; now %d foos\n", this, si); ++ printf ("new foo @ %p; now %d foos\n", (void*)this, si); + } + + foo::foo (const foo &other) + { + si++; +- printf ("another foo @ 0x%x; now %d foos\n", this, si); ++ printf ("another foo @ %p; now %d foos\n", (void*)this, si); + *this = other; + } + + foo::~foo () + { + si--; +- printf ("deleted foo @ 0x%x; now %d foos\n", this, si); ++ printf ("deleted foo @ %p; now %d foos\n", (void*)this, si); + } + + int +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.mike/p710.C b/src/gcc/testsuite/g++.old-deja/g++.mike/p710.C +--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p710.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p710.C 2009-03-17 13:40:03.000000000 -0700 +@@ -30,7 +30,7 @@ class B + virtual ~B() {} + void operator delete(void*,size_t s) + { +- printf("B::delete() %d\n",s); ++ printf("B::delete() %u\n",(unsigned int)s); + } + void operator delete(void*){} + }; +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.mike/p789a.C b/src/gcc/testsuite/g++.old-deja/g++.mike/p789a.C +--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p789a.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p789a.C 2009-03-17 13:40:03.000000000 -0700 +@@ -13,10 +13,10 @@ struct foo + int x; + foo () { + x = count++; +- printf("this %d = %x\n", x, (void *)this); ++ printf("this %d = %p\n", x, (void *)this); + } + virtual ~foo () { +- printf("this %d = %x\n", x, (void *)this); ++ printf("this %d = %p\n", x, (void *)this); + --count; + } + }; +@@ -31,7 +31,7 @@ int main () + { + for (int j = 0; j < 3; j++) + { +- printf("&a[%d][%d] = %x\n", i, j, (void *)&array[i][j]); ++ printf("&a[%d][%d] = %p\n", i, j, (void *)&array[i][j]); + } + } + // The count should be nine, if not, fail the test. +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.mike/pmf2.C b/src/gcc/testsuite/g++.old-deja/g++.mike/pmf2.C +--- a/src/gcc/testsuite/g++.old-deja/g++.mike/pmf2.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/pmf2.C 2009-03-17 13:40:03.000000000 -0700 +@@ -42,7 +42,7 @@ B_table b; + bar jar; + + int main() { +- printf("ptr to B_table=%x, ptr to A_table=%x\n",&b,(A_table*)&b); ++ printf("ptr to B_table=%p, ptr to A_table=%p\n",(void*)&b,(void*)(A_table*)&b); + B_table::B_ti_fn z = &B_table::func1; + int j = 1; + jar.call_fn_fn1(j,(void *)&z); +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.mike/temp.C b/src/gcc/testsuite/g++.old-deja/g++.mike/temp.C +--- a/src/gcc/testsuite/g++.old-deja/g++.mike/temp.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/temp.C 2009-03-17 13:40:03.000000000 -0700 +@@ -7,11 +7,11 @@ class T { + public: + T() { + i = 1; +- printf("T() at %x\n", this); ++ printf("T() at %p\n", (void*)this); + } + T(const T& o) { + i = o.i; +- printf("T(const T&) at %x <-- %x\n", this, &o); ++ printf("T(const T&) at %p <-- %p\n", (void*)this, (void*)&o); + } + T operator +(const T& o) { + T r; +@@ -21,7 +21,7 @@ public: + operator int () { + return i; + } +- ~T() { printf("~T() at %x\n", this); } ++ ~T() { printf("~T() at %p\n", (void*)this); } + } s, b; + + int foo() { return getenv("TEST") == 0; } +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.other/temporary1.C b/src/gcc/testsuite/g++.old-deja/g++.other/temporary1.C +--- a/src/gcc/testsuite/g++.old-deja/g++.other/temporary1.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.other/temporary1.C 2009-03-17 16:09:42.000000000 -0700 +@@ -5,16 +5,16 @@ int c, d; + class Foo + { + public: +- Foo() { printf("Foo() 0x%08lx\n", (__SIZE_TYPE__)this); ++c; } +- Foo(Foo const &) { printf("Foo(Foo const &) 0x%08lx\n", (__SIZE_TYPE__)this); } +- ~Foo() { printf("~Foo() 0x%08lx\n", (__SIZE_TYPE__)this); ++d; } ++ Foo() { printf("Foo() %p\n", (void*)this); ++c; } ++ Foo(Foo const &) { printf("Foo(Foo const &) %p\n", (void*)this); } ++ ~Foo() { printf("~Foo() %p\n", (void*)this); ++d; } + }; + + // Bar creates constructs a temporary Foo() as a default + class Bar + { + public: +- Bar(Foo const & = Foo()) { printf("Bar(Foo const &) 0x%08lx\n", (__SIZE_TYPE__)this); } ++ Bar(Foo const & = Foo()) { printf("Bar(Foo const &) %p\n", (void*)this); } + }; + + void fakeRef(Bar *) +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.other/virtual8.C b/src/gcc/testsuite/g++.old-deja/g++.other/virtual8.C +--- a/src/gcc/testsuite/g++.old-deja/g++.other/virtual8.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.other/virtual8.C 2009-03-17 13:40:03.000000000 -0700 +@@ -4,7 +4,7 @@ extern "C" int printf (const char*, ...) + struct A + { + virtual void f () { +- printf ("%x\n", this); ++ printf ("%p\n", (void*)this); + } + }; + +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp23.C b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp23.C +--- a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp23.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp23.C 2009-03-17 13:40:03.000000000 -0700 +@@ -13,7 +13,7 @@ struct S + + template + void f(U u) +- { printf ("In S::f(U)\nsizeof(U) == %d\n", sizeof(u)); } ++ { printf ("In S::f(U)\nsizeof(U) == %d\n", (int)sizeof(u)); } + + int c[16]; + }; +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp24.C b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp24.C +--- a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp24.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp24.C 2009-03-17 13:40:03.000000000 -0700 +@@ -13,7 +13,7 @@ struct S + + template + void f(U u) +- { printf ("In S::f(U)\nsizeof(U) == %d\n", sizeof(u)); } ++ { printf ("In S::f(U)\nsizeof(U) == %d\n", (int)sizeof(u)); } + + int c[16]; + }; +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp25.C b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp25.C +--- a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp25.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp25.C 2009-03-17 13:40:03.000000000 -0700 +@@ -6,7 +6,7 @@ template + struct S + { + template +- void f(U u) { printf ("%d\n", sizeof (U)); } ++ void f(U u) { printf ("%d\n", (int)sizeof (U)); } + + int i[4]; + }; +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp26.C b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp26.C +--- a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp26.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp26.C 2009-03-17 13:40:03.000000000 -0700 +@@ -16,7 +16,7 @@ template + template + void S::f(U u) + { +- printf ("%d\n", sizeof (U)); ++ printf ("%d\n", (int)sizeof (U)); + } + + +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.pt/t39.C b/src/gcc/testsuite/g++.old-deja/g++.pt/t39.C +--- a/src/gcc/testsuite/g++.old-deja/g++.pt/t39.C 2006-02-05 01:21:29.000000000 -0800 ++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/t39.C 2009-03-17 13:40:03.000000000 -0700 +@@ -10,9 +10,9 @@ struct frob { + + template + void frob::print () { +- printf ("this = %08x\n", this); +- printf (" ptr = %08x\n", ptr); +- printf (" values = %x %x %x ...\n", ptr[0], ptr[1], ptr[2]); ++ printf ("this = %p\n", (void*)this); ++ printf (" ptr = %p\n", (void*)ptr); ++ printf (" values = %x %x %x ...\n", (int)ptr[0], (int)ptr[1], (int)ptr[2]); + } + + static int x[10]; +diff -uNrp a/src/gcc/testsuite/g++.old-deja/g++.robertl/eb17.C b/src/gcc/testsuite/g++.old-deja/g++.robertl/eb17.C +--- a/src/gcc/testsuite/g++.old-deja/g++.robertl/eb17.C 2003-04-30 19:02:59.000000000 -0700 ++++ b/src/gcc/testsuite/g++.old-deja/g++.robertl/eb17.C 2009-03-17 13:40:03.000000000 -0700 +@@ -44,15 +44,15 @@ int main() + A * a = new B; + B * b = dynamic_cast(a); + +- printf("%p\n",b); // (*2*) ++ printf("%p\n",(void*)b); // (*2*) + b->print(); + + a = b; +- printf("%p\n",a); ++ printf("%p\n",(void*)a); + a->print(); + + a = a->clone(); +- printf("%p\n",a); ++ printf("%p\n",(void*)a); + a->print(); // (*1*) + + return 0; +diff -uNrp a/src/gcc/testsuite/gcc.dg/pch/inline-4.c b/src/gcc/testsuite/gcc.dg/pch/inline-4.c +--- a/src/gcc/testsuite/gcc.dg/pch/inline-4.c 2009-03-20 09:08:02.000000000 -0700 ++++ b/src/gcc/testsuite/gcc.dg/pch/inline-4.c 2009-03-20 13:43:53.000000000 -0700 +@@ -1,6 +1,6 @@ + #include "inline-4.h" + extern int printf (const char *, ...); + int main(void) { +- printf (getstring()); ++ printf ("%s", getstring()); + return 0; + } --- gcc-4.5-4.5.2.orig/debian/patches/alpha-ieee-doc.diff +++ gcc-4.5-4.5.2/debian/patches/alpha-ieee-doc.diff @@ -0,0 +1,24 @@ +# DP: #212912 +# DP: on alpha-linux, make -mieee default and add -mieee-disable switch +# DP: to turn default off (doc patch) + +--- + gcc/doc/invoke.texi | 7 +++++++ + 1 files changed, 7 insertions(+), 0 deletions(-) + +--- a/src/gcc/doc/invoke.texi ++++ b/src/gcc/doc/invoke.texi +@@ -9980,6 +9980,13 @@ able to correctly support denormalized numbers and exceptional IEEE + values such as not-a-number and plus/minus infinity. Other Alpha + compilers call this option @option{-ieee_with_no_inexact}. + ++DEBIAN SPECIFIC: This option is on by default, unless ++@option{-ffinite-math-only} (which is part of the @option{-ffast-math} ++set) is specified, because the software functions in the GNU libc math ++libraries generate denormalized numbers, NaNs, and infs (all of which ++will cause a programs to SIGFPE when it attempts to use the results without ++@option{-mieee}). ++ + @item -mieee-with-inexact + @opindex mieee-with-inexact + This is like @option{-mieee} except the generated code also maintains --- gcc-4.5-4.5.2.orig/debian/patches/ada-gcc-name.diff +++ gcc-4.5-4.5.2/debian/patches/ada-gcc-name.diff @@ -0,0 +1,112 @@ +# DP: use gcc-4.4 instead of gcc as the command name. + +Index: b/src/gcc/ada/comperr.adb +=================================================================== +--- a/src/gcc/ada/comperr.adb ++++ b/src/gcc/ada/comperr.adb +@@ -356,7 +356,7 @@ + End_Line; + + Write_Str +- ("| Include the exact gcc or gnatmake command " & ++ ("| Include the exact gcc-4.4 or gnatmake command " & + "that you entered."); + End_Line; + +Index: b/src/gcc/ada/gnatlink.adb +=================================================================== +--- a/src/gcc/ada/gnatlink.adb ++++ b/src/gcc/ada/gnatlink.adb +@@ -137,7 +137,7 @@ + -- This table collects the arguments to be passed to compile the binder + -- generated file. + +- Gcc : String_Access := Program_Name ("gcc", "gnatlink"); ++ Gcc : String_Access := Program_Name ("gcc-4.4", "gnatlink"); + + Read_Mode : constant String := "r" & ASCII.NUL; + +@@ -1411,7 +1411,8 @@ + end if; + + Write_Line (" --GCC=comp Use comp as the compiler"); +- Write_Line (" --LINK=nam Use 'nam' for the linking rather than 'gcc'"); ++ Write_Line (" --LINK=nam Use 'nam' for the linking rather " & ++ "than 'gcc-4.4'"); + Write_Eol; + Write_Line (" [non-Ada-objects] list of non Ada object files"); + Write_Line (" [linker-options] other options for the linker"); +Index: b/src/gcc/ada/make.adb +=================================================================== +--- a/src/gcc/ada/make.adb ++++ b/src/gcc/ada/make.adb +@@ -670,7 +670,7 @@ + -- Compiler, Binder & Linker Data and Subprograms -- + ---------------------------------------------------- + +- Gcc : String_Access := Program_Name ("gcc", "gnatmake"); ++ Gcc : String_Access := Program_Name ("gcc-4.4", "gnatmake"); + Gnatbind : String_Access := Program_Name ("gnatbind", "gnatmake"); + Gnatlink : String_Access := Program_Name ("gnatlink", "gnatmake"); + -- Default compiler, binder, linker programs +Index: b/src/gcc/ada/gnatchop.adb +=================================================================== +--- a/src/gcc/ada/gnatchop.adb ++++ b/src/gcc/ada/gnatchop.adb +@@ -44,7 +44,7 @@ + Config_File_Name : constant String_Access := new String'("gnat.adc"); + -- The name of the file holding the GNAT configuration pragmas + +- Gcc : String_Access := new String'("gcc"); ++ Gcc : String_Access := new String'("gcc-4.4"); + -- May be modified by switch --GCC= + + Gcc_Set : Boolean := False; +Index: b/src/gcc/ada/mdll-utl.adb +=================================================================== +--- a/src/gcc/ada/mdll-utl.adb ++++ b/src/gcc/ada/mdll-utl.adb +@@ -39,7 +39,7 @@ + Dlltool_Name : constant String := "dlltool"; + Dlltool_Exec : OS_Lib.String_Access; + +- Gcc_Name : constant String := "gcc"; ++ Gcc_Name : constant String := "gcc-4.4"; + Gcc_Exec : OS_Lib.String_Access; + + Gnatbind_Name : constant String := "gnatbind"; +@@ -212,7 +212,7 @@ + end; + end if; + +- Print_Command ("gcc", Arguments (1 .. A)); ++ Print_Command ("gcc-4.4", Arguments (1 .. A)); + + OS_Lib.Spawn (Gcc_Exec.all, Arguments (1 .. A), Success); + +Index: b/src/gcc/ada/mlib-utl.adb +=================================================================== +--- a/src/gcc/ada/mlib-utl.adb ++++ b/src/gcc/ada/mlib-utl.adb +@@ -412,7 +412,7 @@ + if Driver_Name = No_Name then + if Gcc_Exec = null then + if Gcc_Name = null then +- Gcc_Name := Osint.Program_Name ("gcc", "gnatmake"); ++ Gcc_Name := Osint.Program_Name ("gcc-4.4", "gnatmake"); + end if; + + Gcc_Exec := Locate_Exec_On_Path (Gcc_Name.all); +Index: b/src/gcc/ada/prj-makr.adb +=================================================================== +--- a/src/gcc/ada/prj-makr.adb ++++ b/src/gcc/ada/prj-makr.adb +@@ -109,7 +109,7 @@ + + procedure Dup2 (Old_Fd, New_Fd : File_Descriptor); + +- Gcc : constant String := "gcc"; ++ Gcc : constant String := "gcc-4.4"; + Gcc_Path : String_Access := null; + + Non_Empty_Node : constant Project_Node_Id := 1; --- gcc-4.5-4.5.2.orig/debian/patches/no_fpr_in_libgcc.diff +++ gcc-4.5-4.5.2/debian/patches/no_fpr_in_libgcc.diff @@ -0,0 +1,55 @@ +# DP: It does not really harm by including them since nobody should use them +# DP: but gas does not wont to assmebly hard float since they are not +# DP: available on this cpu. Upstream did not respond. + +Index: gcc-4.4.5/src/gcc/config/rs6000/crtresfpr.asm +=================================================================== +--- gcc-4.4.5.orig/src/gcc/config/rs6000/crtresfpr.asm 2011-02-13 17:25:36.000000000 +0100 ++++ gcc-4.4.5/src/gcc/config/rs6000/crtresfpr.asm 2011-02-13 17:26:14.000000000 +0100 +@@ -33,6 +33,7 @@ + + /* On PowerPC64 Linux, these functions are provided by the linker. */ + #ifndef __powerpc64__ ++#ifndef __NO_FPRS__ + + /* Routines for restoring floating point registers, called by the compiler. */ + /* Called with r11 pointing to the stack header word of the caller of the */ +@@ -77,3 +78,4 @@ + FUNC_END(_restfpr_14) + + #endif ++#endif +Index: gcc-4.4.5/src/gcc/config/rs6000/crtresxfpr.asm +=================================================================== +--- gcc-4.4.5.orig/src/gcc/config/rs6000/crtresxfpr.asm 2011-02-13 17:25:36.000000000 +0100 ++++ gcc-4.4.5/src/gcc/config/rs6000/crtresxfpr.asm 2011-02-13 17:26:29.000000000 +0100 +@@ -33,6 +33,7 @@ + + /* On PowerPC64 Linux, these functions are provided by the linker. */ + #ifndef __powerpc64__ ++#ifndef __NO_FPRS__ + + /* Routines for restoring floating point registers, called by the compiler. */ + /* Called with r11 pointing to the stack header word of the caller of the */ +@@ -82,3 +83,4 @@ + FUNC_END(_restfpr_14_x) + + #endif ++#endif +Index: gcc-4.4.5/src/gcc/config/rs6000/crtsavfpr.asm +=================================================================== +--- gcc-4.4.5.orig/src/gcc/config/rs6000/crtsavfpr.asm 2011-02-13 17:25:36.000000000 +0100 ++++ gcc-4.4.5/src/gcc/config/rs6000/crtsavfpr.asm 2011-02-13 17:26:42.000000000 +0100 +@@ -33,6 +33,7 @@ + + /* On PowerPC64 Linux, these functions are provided by the linker. */ + #ifndef __powerpc64__ ++#ifndef __NO_FPRS__ + + /* Routines for saving floating point registers, called by the compiler. */ + /* Called with r11 pointing to the stack header word of the caller of the */ +@@ -77,3 +78,4 @@ + FUNC_END(_savefpr_14) + + #endif ++#endif --- gcc-4.5-4.5.2.orig/debian/patches/libobjc-gc.diff +++ gcc-4.5-4.5.2/debian/patches/libobjc-gc.diff @@ -0,0 +1,21 @@ +# DP: Avoid warning building GC enabled libobjc on amd64 + +--- a/src/libobjc/objects.c ++++ b/src/libobjc/objects.c +@@ -29,6 +29,7 @@ + + #if OBJC_WITH_GC + # include ++# include + #endif + + id __objc_object_alloc (Class); +@@ -47,7 +48,7 @@ + #if OBJC_WITH_GC + if (CLS_ISCLASS (class)) + new = (id) GC_malloc_explicitly_typed (class->instance_size, +- class->gc_object_type); ++ (GC_descr)class->gc_object_type); + #else + if (CLS_ISCLASS (class)) + new = (*_objc_object_alloc) (class); --- gcc-4.5-4.5.2.orig/debian/patches/ada-nobiarch-check.diff +++ gcc-4.5-4.5.2/debian/patches/ada-nobiarch-check.diff @@ -0,0 +1,20 @@ +# DP: For biarch builds, disable the gnat testsuite for the non-default +# architecture (no biarch support in gnat yet). + +Index: b/src/gcc/Makefile.in +=================================================================== +--- a/src/gcc/Makefile.in ++++ b/src/gcc/Makefile.in +@@ -4510,7 +4510,11 @@ + if [ -f $${rootme}/../expect/expect ] ; then \ + TCL_LIBRARY=`cd .. ; cd $${srcdir}/../tcl/library ; ${PWD_COMMAND}` ; \ + export TCL_LIBRARY ; fi ; \ +- $(RUNTEST) --tool $* $(RUNTESTFLAGS)) ++ if [ "$*" = gnat ]; then \ ++ runtestflags="`echo '$(RUNTESTFLAGS)' | sed 's/,-m[36][24]//;s/,-mabi=n32//'`"; \ ++ case "$$runtestflags" in *\\{\\}) runtestflags=; esac; \ ++ fi; \ ++ $(RUNTEST) --tool $* $$runtestflags) + + $(patsubst %,%-subtargets,$(filter-out $(lang_checks_parallelized),$(lang_checks))): check-%-subtargets: + @echo check-$* --- gcc-4.5-4.5.2.orig/debian/patches/gcc-plugindir-doc.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-plugindir-doc.diff @@ -0,0 +1,54 @@ +# DP: Search for plugins in a default plugin dir, backport from the trunk (docs). + +--- a/src/gcc/doc/plugins.texi~ 2010-04-02 21:54:46.000000000 +0200 ++++ b/src/gcc/doc/plugins.texi 2010-05-01 17:46:54.101086672 +0200 +@@ -22,6 +22,11 @@ + plugins as key-value pairs. Multiple plugins can be invoked by + specifying multiple @option{-fplugin} arguments. + ++A plugin can be simply given by its short name (no dots or ++slashes). When simply passing @option{-fplugin=NAME}, the plugin is ++loaded from the @file{plugin} directory, so @option{-fplugin=NAME} is ++the same as @option{-fplugin=`gcc -print-file-name=plugin`/NAME.so}, ++using backquote shell syntax to query the @file{plugin} directory. + + @section Plugin API + +@@ -407,6 +412,9 @@ + invoking @command{gcc -print-file-name=plugin} (replace if needed + @command{gcc} with the appropriate program path). + ++Inside plugins, this @code{plugin} directory name can be queried by ++calling @code{default_plugin_dir_name ()}. ++ + The following GNU Makefile excerpt shows how to build a simple plugin: + + @smallexample +--- a/src/gcc/doc/invoke.texi~ 2010-05-01 17:43:03.372338550 +0200 ++++ b/src/gcc/doc/invoke.texi 2010-05-01 17:46:05.673586259 +0200 +@@ -425,7 +425,8 @@ + + @item Directory Options + @xref{Directory Options,,Options for Directory Search}. +-@gccoptlist{-B@var{prefix} -I@var{dir} -iquote@var{dir} -L@var{dir} ++@gccoptlist{-B@var{prefix} -I@var{dir} -iplugindir=@var{dir} ++-iquote@var{dir} -L@var{dir} + -specs=@var{file} -I- --sysroot=@var{dir}} + + @item Target Options +@@ -8872,6 +8873,15 @@ + "@var{file}"}; they are not searched for @samp{#include <@var{file}>}, + otherwise just like @option{-I}. + ++@item -iplugindir=@var{dir} ++Set the directory to search for plugins which are passed ++by @option{-fplugin=@var{name}} instead of ++@option{-fplugin=@var{path}/@var{name}.so}. This option is not meant ++to be used by the user, but only passed by the driver. ++ ++NOTE: This is a backport for Debian/Ubuntu. Upstream versions of ++GCC 4.5 don't have this option. ++ + @item -L@var{dir} + @opindex L + Add directory @var{dir} to the list of directories to be searched --- gcc-4.5-4.5.2.orig/debian/patches/gcc-default-ssp-ppc64.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-default-ssp-ppc64.diff @@ -0,0 +1,194 @@ +# DP: Turn on -fstack-protector by default for C, C++, ObjC, ObjC++. +# DP: Build libgcc using -fno-stack-protector. + +--- + gcc/Makefile.in | 2 ++ + gcc/cp/lang-specs.h | 6 +++--- + gcc/doc/invoke.texi | 4 ++++ + gcc/gcc.c | 18 ++++++++++++++---- + gcc/objc/lang-specs.h | 10 +++++----- + gcc/objcp/lang-specs.h | 8 ++++---- + 6 files changed, 32 insertions(+), 16 deletions(-) + +--- a/src/gcc/gcc.c.orig ++++ b/src/gcc/gcc.c +@@ -752,6 +752,14 @@ + #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G" + #endif + ++#ifndef SSP_DEFAULT_SPEC ++#ifdef TARGET_LIBC_PROVIDES_SSP ++#define SSP_DEFAULT_SPEC "%{!fstack-protector-all:%{!fno-stack-protector:%{!ffreestanding:%{!nostdlib:-fstack-protector}}}}" ++#else ++#define SSP_DEFAULT_SPEC "" ++#endif ++#endif ++ + #ifndef LINK_SSP_SPEC + #ifdef TARGET_LIBC_PROVIDES_SSP + #define LINK_SSP_SPEC "%{fstack-protector:}" +@@ -837,6 +845,7 @@ + static const char *cc1plus_spec = CC1PLUS_SPEC; + static const char *link_gcc_c_sequence_spec = LINK_GCC_C_SEQUENCE_SPEC; + static const char *link_ssp_spec = LINK_SSP_SPEC; ++static const char *ssp_default_spec = SSP_DEFAULT_SPEC; + static const char *asm_spec = ASM_SPEC; + static const char *asm_final_spec = ASM_FINAL_SPEC; + static const char *link_spec = LINK_SPEC; +@@ -899,7 +908,7 @@ + "%(cpp_unique_options) %1 %{m*} %{std*&ansi&trigraphs} %{W*&pedantic*} %{w}\ + %{f*} %{g*:%{!g0:%{g*} %{!fno-working-directory:-fworking-directory}}} %{O*}\ + %{O1:%:if-env-unset(DEB_GCC_NO_O3 -O3)} %{O2:%:if-env-unset(DEB_GCC_NO_O3 -O3)}\ +- %{undef} %{save-temps*:-fpch-preprocess}"; ++ %{undef} %{save-temps*:-fpch-preprocess} %(ssp_default)"; + + /* This contains cpp options which are not passed when the preprocessor + output will be used by another program. */ +@@ -1091,15 +1100,15 @@ + %{save-temps*|traditional-cpp|no-integrated-cpp:%(trad_capable_cpp) \ + %(cpp_options) -o %{save-temps*:%b.i} %{!save-temps*:%g.i} \n\ + cc1 -fpreprocessed %{save-temps*:%b.i} %{!save-temps*:%g.i} \ +- %(cc1_options)}\ ++ %(cc1_options) %(ssp_default)}\ + %{!save-temps*:%{!traditional-cpp:%{!no-integrated-cpp:\ +- cc1 %(cpp_unique_options) %(cc1_options)}}}\ ++ cc1 %(cpp_unique_options) %(cc1_options) %(ssp_default)}}}\ + %{!fsyntax-only:%(invoke_as)}} \ + %{combine:\ + %{save-temps*|traditional-cpp|no-integrated-cpp:%(trad_capable_cpp) \ + %(cpp_options) -o %{save-temps*:%b.i} %{!save-temps*:%g.i}}\ + %{!save-temps*:%{!traditional-cpp:%{!no-integrated-cpp:\ +- cc1 %(cpp_unique_options) %(cc1_options)}}\ ++ cc1 %(cpp_unique_options) %(cc1_options) %(ssp_default)}}\ + %{!fsyntax-only:%(invoke_as)}}}}}}", 0, 1, 1}, + {"-", + "%{!E:%e-E or -x required when input is from standard input}\ +@@ -1122,7 +1131,7 @@ + %W{o*:--output-pch=%*}%V}}}}}}", 0, 0, 0}, + {".i", "@cpp-output", 0, 1, 0}, + {"@cpp-output", +- "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %(cc1_options) %{!fsyntax-only:%(invoke_as)}}}}", 0, 1, 0}, ++ "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %(cc1_options) %(ssp_default) %{!fsyntax-only:%(invoke_as)}}}}", 0, 1, 0}, + {".s", "@assembler", 0, 1, 0}, + {"@assembler", + "%{!M:%{!MM:%{!E:%{!S:as %(asm_debug) %(asm_options) %i %A }}}}", 0, 1, 0}, +@@ -1683,6 +1692,7 @@ + INIT_STATIC_SPEC ("cc1plus", &cc1plus_spec), + INIT_STATIC_SPEC ("link_gcc_c_sequence", &link_gcc_c_sequence_spec), + INIT_STATIC_SPEC ("link_ssp", &link_ssp_spec), ++ INIT_STATIC_SPEC ("ssp_default", &ssp_default_spec), + INIT_STATIC_SPEC ("endfile", &endfile_spec), + INIT_STATIC_SPEC ("link", &link_spec), + INIT_STATIC_SPEC ("lib", &lib_spec), +--- a/src/gcc/cp/lang-specs.h.orig ++++ b/src/gcc/cp/lang-specs.h +@@ -47,7 +47,7 @@ + %(cpp_options) %2 -o %{save-temps:%b.ii} %{!save-temps:%g.ii} \n}\ + cc1plus %{save-temps|no-integrated-cpp:-fpreprocessed %{save-temps:%b.ii} %{!save-temps:%g.ii}}\ + %{!save-temps:%{!no-integrated-cpp:%(cpp_unique_options)}}\ +- %(cc1_options) %2 %{+e1*}\ ++ %(cc1_options) %(ssp_default) %2 %{+e1*}\ + %{!fsyntax-only:-o %g.s %{!o*:--output-pch=%i.gch} %W{o*:--output-pch=%*}%V}}}}", + CPLUSPLUS_CPP_SPEC, 0, 0}, + {"@c++", +@@ -57,11 +57,11 @@ + %(cpp_options) %2 -o %{save-temps:%b.ii} %{!save-temps:%g.ii} \n}\ + cc1plus %{save-temps|no-integrated-cpp:-fpreprocessed %{save-temps:%b.ii} %{!save-temps:%g.ii}}\ + %{!save-temps:%{!no-integrated-cpp:%(cpp_unique_options)}}\ +- %(cc1_options) %2 %{+e1*}\ ++ %(cc1_options) %(ssp_default) %2 %{+e1*}\ + %{!fsyntax-only:%(invoke_as)}}}}", + CPLUSPLUS_CPP_SPEC, 0, 0}, + {".ii", "@c++-cpp-output", 0, 0, 0}, + {"@c++-cpp-output", + "%{!M:%{!MM:%{!E:\ +- cc1plus -fpreprocessed %i %(cc1_options) %2 %{+e*}\ ++ cc1plus -fpreprocessed %i %(cc1_options) %(ssp_default) %2 %{+e*}\ + %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, +--- a/src/gcc/params.def.orig ++++ b/src/gcc/params.def +@@ -616,7 +616,7 @@ + DEFPARAM (PARAM_SSP_BUFFER_SIZE, + "ssp-buffer-size", + "The lower bound for a buffer to be considered for stack smashing protection", +- 8, 1, 0) ++ 4, 1, 0) + + /* When we thread through a block we have to make copies of the + statements within the block. Clearly for large blocks the code +--- a/src/gcc/objc/lang-specs.h.orig ++++ b/src/gcc/objc/lang-specs.h +@@ -31,13 +31,13 @@ + %{traditional|ftraditional|traditional-cpp:\ + %eGNU Objective C no longer supports traditional compilation}\ + %{save-temps|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps:%b.mi} %{!save-temps:%g.mi} \n\ +- cc1obj -fpreprocessed -fno-section-anchors %{save-temps:%b.mi} %{!save-temps:%g.mi} %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}\ ++ cc1obj -fpreprocessed -fno-section-anchors %{save-temps:%b.mi} %{!save-temps:%g.mi} %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}}\ + %{!save-temps:%{!no-integrated-cpp:\ +- cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}}\ ++ cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}}}\ + %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, + {".mi", "@objc-cpp-output", 0, 0, 0}, + {"@objc-cpp-output", +- "%{!M:%{!MM:%{!E:cc1obj -fno-section-anchors -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ ++ "%{!M:%{!MM:%{!E:cc1obj -fno-section-anchors -fpreprocessed %i %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}\ + %{!fsyntax-only:%(invoke_as)}}}} \ + %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} ", 0, 0, 0}, + {"@objective-c-header", +@@ -48,11 +48,11 @@ + %{traditional|ftraditional|traditional-cpp:\ + %eGNU Objective C no longer supports traditional compilation}\ + %{save-temps|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps:%b.mi} %{!save-temps:%g.mi} \n\ +- cc1obj -fpreprocessed %b.mi %(cc1_options) -fno-section-anchors %{print-objc-runtime-info} %{gen-decls}\ ++ cc1obj -fpreprocessed %b.mi %(cc1_options) %(ssp_default) -fno-section-anchors %{print-objc-runtime-info} %{gen-decls}\ + -o %g.s %{!o*:--output-pch=%i.gch}\ + %W{o*:--output-pch=%*}%V}\ + %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \ + %{!save-temps:%{!no-integrated-cpp:\ +- cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ ++ cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}\ + -o %g.s %{!o*:--output-pch=%i.gch}\ + %W{o*:--output-pch=%*}%V}}}}}", 0, 0, 0}, +--- a/src/gcc/objcp/lang-specs.h.orig ++++ b/src/gcc/objcp/lang-specs.h +@@ -36,7 +36,7 @@ + %(cpp_options) %2 -o %{save-temps:%b.mii} %{!save-temps:%g.mii} \n}\ + cc1objplus %{save-temps|no-integrated-cpp:-fpreprocessed %{save-temps:%b.mii} %{!save-temps:%g.mii}}\ + %{!save-temps:%{!no-integrated-cpp:%(cpp_unique_options)}}\ +- %(cc1_options) %2 %{+e1*}\ ++ %(cc1_options) %(ssp_default) %2 %{+e1*}\ + -o %g.s %{!o*:--output-pch=%i.gch} %W{o*:--output-pch=%*}%V}}}", + CPLUSPLUS_CPP_SPEC, 0, 0}, + {"@objective-c++", +@@ -46,15 +46,15 @@ + %(cpp_options) %2 -o %{save-temps:%b.mii} %{!save-temps:%g.mii} \n}\ + cc1objplus %{save-temps|no-integrated-cpp:-fpreprocessed %{save-temps:%b.mii} %{!save-temps:%g.mii}}\ + %{!save-temps:%{!no-integrated-cpp:%(cpp_unique_options)}}\ +- %(cc1_options) %2 %{+e1*}\ ++ %(cc1_options) %(ssp_default) %2 %{+e1*}\ + %{!fsyntax-only:%(invoke_as)}}}}", + CPLUSPLUS_CPP_SPEC, 0, 0}, + {".mii", "@objective-c++-cpp-output", 0, 0, 0}, + {"@objective-c++-cpp-output", + "%{!M:%{!MM:%{!E:\ +- cc1objplus -fpreprocessed %i %(cc1_options) %2 %{+e*}\ ++ cc1objplus -fpreprocessed %i %(cc1_options) %(ssp_default) %2 %{+e*}\ + %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, + {"@objc++-cpp-output", + "%{!M:%{!MM:%{!E:\ +- cc1objplus -fpreprocessed %i %(cc1_options) %2 %{+e*}\ ++ cc1objplus -fpreprocessed %i %(cc1_options) %(ssp_default) %2 %{+e*}\ + %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, +--- a/src/gcc/doc/invoke.texi.orig ++++ b/src/gcc/doc/invoke.texi +@@ -7868,6 +7868,10 @@ + when a function is entered and then checked when the function exits. + If a guard check fails, an error message is printed and the program exits. + ++NOTE: In Ubuntu 6.10 and later versions this option is enabled by default ++for C, C++, ObjC, ObjC++, if none of @option{-fno-stack-protector}, ++@option{-nostdlib}, nor @option{-ffreestanding} are found. ++ + @item -fstack-protector-all + @opindex fstack-protector-all + Like @option{-fstack-protector} except that all functions are protected. --- gcc-4.5-4.5.2.orig/debian/patches/gcc-default-format-security.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-default-format-security.diff @@ -0,0 +1,54 @@ +# DP: Turn on -Wformat -Wformat-security by default for C, C++, ObjC, ObjC++. + +--- + gcc/c-common.c | 2 +- + gcc/c.opt | 2 +- + gcc/doc/invoke.texi | 8 ++++++++ + 3 files changed, 10 insertions(+), 2 deletions(-) + +--- a/src/gcc/c-common.c ++++ b/src/gcc/c-common.c +@@ -300,7 +300,7 @@ int warn_unknown_pragmas; /* Tri state variable. */ + /* Warn about format/argument anomalies in calls to formatted I/O functions + (*printf, *scanf, strftime, strfmon, etc.). */ + +-int warn_format; ++int warn_format = 1; + + /* Warn about using __null (as NULL in C++) as sentinel. For code compiled + with GCC this doesn't matter as __null is guaranteed to have the right +--- a/src/gcc/c.opt ++++ b/src/gcc/c.opt +@@ -236,7 +236,7 @@ C ObjC C++ ObjC++ Var(warn_format_contains_nul) Warning + Warn about format strings that contain NUL bytes + + Wformat-security +-C ObjC C++ ObjC++ Var(warn_format_security) Warning ++C ObjC C++ ObjC++ Var(warn_format_security) Init(1) Warning + Warn about possible security problems with format functions + + Wformat-y2k +--- a/src/gcc/doc/invoke.texi ++++ b/src/gcc/doc/invoke.texi +@@ -2864,6 +2864,9 @@ aspects of format checking, the options @option{-Wformat-y2k}, + @option{-Wformat-nonliteral}, @option{-Wformat-security}, and + @option{-Wformat=2} are available, but are not included in @option{-Wall}. + ++NOTE: In Ubuntu 8.10 and later versions this option is enabled by default ++for C, C++, ObjC, ObjC++. To disable, use @option{-Wformat=0}. ++ + @item -Wformat-y2k + @opindex Wformat-y2k + @opindex Wno-format-y2k +@@ -2917,6 +2920,11 @@ currently a subset of what @option{-Wformat-nonliteral} warns about, but + in future warnings may be added to @option{-Wformat-security} that are not + included in @option{-Wformat-nonliteral}.) + ++NOTE: In Ubuntu 8.10 and later versions this option is enabled by default ++for C, C++, ObjC, ObjC++. To disable, use @option{-Wno-format-security}, ++or disable all format warnings with @option{-Wformat=0}. To make format ++security warnings fatal, specify @option{-Werror=format-security}. ++ + @item -Wformat=2 + @opindex Wformat=2 + @opindex Wno-format=2 --- gcc-4.5-4.5.2.orig/debian/patches/ada-acats.diff +++ gcc-4.5-4.5.2/debian/patches/ada-acats.diff @@ -0,0 +1,179 @@ +# DP: - When running the ACATS, look for the gnat tools in their new +# DP: directory (build/gnattools), and for the shared libraries in +# DP: build/gcc/ada/rts-shared-zcx, build/libgnatvsn and build/libgnatprj. + +Index: b/src/gcc/testsuite/ada/acats/run_acats +=================================================================== +--- a/src/gcc/testsuite/ada/acats/run_acats ++++ b/src/gcc/testsuite/ada/acats/run_acats +@@ -5,51 +5,28 @@ + exit 1 + fi + +-# Set up environment to use the Ada compiler from the object tree +- +-host_gnatchop=`type gnatchop | awk '{print $3}'` +-host_gnatmake=`type gnatmake | awk '{print $3}'` +-ROOT=`${PWDCMD-pwd}` +-BASE=`cd $ROOT/../../..; ${PWDCMD-pwd}` ++echo '#!/bin/sh' > host_gnatchop ++echo exec /usr/bin/gnatchop '$*' >> host_gnatchop + +-PATH=$BASE:$ROOT:$PATH +-ADA_INCLUDE_PATH=$BASE/ada/rts +-LD_LIBRARY_PATH=$ADA_INCLUDE_PATH:$BASE:$LD_LIBRARY_PATH +-ADA_OBJECTS_PATH=$ADA_INCLUDE_PATH ++chmod +x host_gnatchop + +-if [ ! -d $ADA_INCLUDE_PATH ]; then +- echo gnatlib missing, exiting. +- exit 1 +-fi ++echo '#!/bin/sh' > host_gnatmake ++echo echo '$PATH' '$*' >> host_gnatmake ++echo exec /usr/bin/gnatmake '$*' >> host_gnatmake + +-if [ ! -f $BASE/gnatchop ]; then +- echo gnattools missing, exiting. +- exit 1 +-fi ++chmod +x host_gnatmake + +-if [ ! -f $BASE/gnatmake ]; then +- echo gnattools missing, exiting. +- exit 1 +-fi ++# Set up environment to use the Ada compiler from the object tree + ++ROOT=`${PWDCMD-pwd}` ++BASE=`cd $ROOT/../../..; ${PWDCMD-pwd}` ++PATH=$BASE:$ROOT:$PATH ++GNATTOOLS=`cd $BASE/../gnattools; ${PWDCMD-pwd}` ++LIBGNATVSN=`cd $BASE/../libgnatvsn; ${PWDCMD-pwd}` ++LIBGNATPRJ=`cd $BASE/../libgnatprj; ${PWDCMD-pwd}` + GCC_DRIVER="$BASE/xgcc" + GCC="$BASE/xgcc -B$BASE/" + export PATH ADA_INCLUDE_PATH ADA_OBJECTS_PATH GCC_DRIVER GCC LD_LIBRARY_PATH +- +-echo '#!/bin/sh' > host_gnatchop +-echo PATH=`dirname $host_gnatchop`:'$PATH' >> host_gnatchop +-echo unset ADA_INCLUDE_PATH ADA_OBJECTS_PATH GCC_EXEC_PREFIX >> host_gnatchop +-echo export PATH >> host_gnatchop +-echo exec gnatchop '"$@"' >> host_gnatchop +- +-chmod +x host_gnatchop +- +-echo '#!/bin/sh' > host_gnatmake +-echo PATH=`dirname $host_gnatmake`:'$PATH' >> host_gnatmake +-echo unset ADA_INCLUDE_PATH ADA_OBJECTS_PATH GCC_EXEC_PREFIX >> host_gnatmake +-echo export PATH >> host_gnatmake +-echo exec gnatmake '"$@"' >> host_gnatmake +- +-chmod +x host_gnatmake ++export GNATTOOLS LIBGNATVSN LIBGNATPRJ + + exec $testdir/run_all.sh ${1+"$@"} +Index: b/src/gcc/testsuite/ada/acats/run_all.sh +=================================================================== +--- a/src/gcc/testsuite/ada/acats/run_all.sh ++++ b/src/gcc/testsuite/ada/acats/run_all.sh +@@ -12,6 +12,10 @@ + gccflags="-O2" + gnatflags="-gnatws" + ++RTS=`cd $GNATTOOLS/../gcc/ada/rts-shared-zcx; ${PWDCMD-pwd}` ++LD_LIBRARY_PATH=$RTS:$LIBGNATVSN:$LIBGNATPRJ ++export LD_LIBRARY_PATH ++ + target_run () { + $* + } +@@ -48,15 +52,25 @@ + fi + + target_gnatchop () { +- gnatchop --GCC="$GCC_DRIVER" $* ++ display ADA_INCLUDE_PATH=$GNATTOOLS/../../src/gcc/ada $GNATTOOLS/gnatchop --GCC="$GCC_DRIVER" $* ++ ADA_INCLUDE_PATH=$GNATTOOLS/../../src/gcc/ada $GNATTOOLS/gnatchop --GCC="$GCC_DRIVER" $* + } + + target_gnatmake () { +- echo gnatmake --GCC=\"$GCC\" $gnatflags $gccflags $* -largs $EXTERNAL_OBJECTS --GCC=\"$GCC\" +- gnatmake --GCC="$GCC" $gnatflags $gccflags $* -largs $EXTERNAL_OBJECTS --GCC="$GCC" ++ RTS="$GNATTOOLS/../gcc/ada/rts-shared-zcx" ++ EXTERNAL_OBJECTS="$EXTERNAL_OBJECTS $RTS/adaint.o $RTS/sysdep.o $RTS/init.o" ++ display $GNATTOOLS/gnatmake -I- -I$RTS -I. \ ++ --GCC=\"$GCC\" --GNATBIND="$GNATTOOLS/gnatbind" \ ++ --GNATLINK="$GNATTOOLS/gnatlink" $gnatflags $gccflags $* \ ++ -bargs -static -largs $EXTERNAL_OBJECTS --GCC=\"$GCC -I- -I$RTS -I.\" ++ $GNATTOOLS/gnatmake -I- -I$RTS -I. \ ++ --GCC="$GCC" --GNATBIND="$GNATTOOLS/gnatbind" \ ++ --GNATLINK="$GNATTOOLS/gnatlink" $gnatflags $gccflags $* \ ++ -bargs -static -largs $EXTERNAL_OBJECTS --GCC="$GCC -I- -I$RTS -I." + } + + target_gcc () { ++ display $GCC $gccflags $* + $GCC $gccflags $* + } + +@@ -84,8 +98,8 @@ + display `$GCC -v 2>&1` + display host=`gcc -dumpmachine` + display target=$target +-display `type gnatmake` +-gnatls -v >> $dir/acats.log ++display `type $GNATTOOLS/gnatmake` ++$GNATTOOLS/gnatls -I- -I$RTS -v >> $dir/acats.log + display "" + + display " === acats support ===" +Index: b/src/gcc/testsuite/lib/gnat.exp +=================================================================== +--- a/src/gcc/testsuite/lib/gnat.exp ++++ b/src/gcc/testsuite/lib/gnat.exp +@@ -83,7 +83,6 @@ + global gluefile wrap_flags + global gnat_initialized + global GNAT_UNDER_TEST +- global GNAT_UNDER_TEST_ORIG + global TOOL_EXECUTABLE + global gnat_libgcc_s_path + global gnat_target_current +@@ -92,14 +91,7 @@ + + if { $gnat_initialized == 1 } { return } + +- if ![info exists GNAT_UNDER_TEST] then { +- if [info exists TOOL_EXECUTABLE] { +- set GNAT_UNDER_TEST "$TOOL_EXECUTABLE" +- } else { +- set GNAT_UNDER_TEST "[local_find_gnatmake]" +- } +- set GNAT_UNDER_TEST_ORIG "$GNAT_UNDER_TEST" +- } ++ set GNAT_UNDER_TEST "$rootme/../gnattools/gnatmake -I$rootme/ada/rts-shared-zcx --GCC=$rootme/xgcc --GNATBIND=$rootme/../gnattools/gnatbind --GNATLINK=$rootme/../gnattools/gnatlink -cargs -B$rootme -largs --GCC=$rootme/xgcc -B$rootme -margs" + + if ![info exists tmpdir] then { + set tmpdir /tmp +@@ -129,7 +121,6 @@ + global gluefile wrap_flags + global srcdir + global GNAT_UNDER_TEST +- global GNAT_UNDER_TEST_ORIG + global TOOL_OPTIONS + global ld_library_path + global gnat_libgcc_s_path +@@ -144,10 +135,10 @@ + } else { + set gnat_rts_opt "--RTS=[get_multilibs]/libada" + } +- set GNAT_UNDER_TEST "$GNAT_UNDER_TEST_ORIG $gnat_rts_opt" ++ set GNAT_UNDER_TEST "$GNAT_UNDER_TEST $gnat_rts_opt" + } + +- set ld_library_path ".:${gnat_libgcc_s_path}" ++ set ld_library_path ".:${gnat_libgcc_s_path}:${rootme}/ada/rts-shared-zcx:${rootme}/libgnatvsn:${rootme}/libgnatprj" + lappend options "compiler=$GNAT_UNDER_TEST -q -f" + lappend options "timeout=[timeout_value]" + --- gcc-4.5-4.5.2.orig/debian/patches/link-libs.diff +++ gcc-4.5-4.5.2/debian/patches/link-libs.diff @@ -0,0 +1,170 @@ +#DP: Link libraries with -01. + +--- + gcc/config/t-slibgcc-elf-ver | 1 + + libffi/Makefile.am | 2 +- + libffi/Makefile.in | 2 +- + libgfortran/Makefile.am | 2 +- + libgfortran/Makefile.in | 2 +- + libjava/Makefile.am | 2 +- + libjava/Makefile.in | 2 +- + libmudflap/Makefile.am | 4 ++-- + libmudflap/Makefile.in | 4 ++-- + libobjc/Makefile.in | 2 ++ + libstdc++-v3/src/Makefile.am | 1 + + libstdc++-v3/src/Makefile.in | 1 + + 12 files changed, 15 insertions(+), 10 deletions(-) + +--- a/src/gcc/config/t-slibgcc-elf-ver.orig 2009-09-10 ++++ b/src/gcc/config/t-slibgcc-elf-ver 2009-12-22 +@@ -35,6 +35,7 @@ + SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \ + -Wl,--soname=$(SHLIB_SONAME) \ + -Wl,--version-script=$(SHLIB_MAP) \ ++ -Wl,-O1 \ + -o $(SHLIB_DIR)/$(SHLIB_SONAME).tmp @multilib_flags@ \ + $(SHLIB_OBJS) $(SHLIB_LC) && \ + rm -f $(SHLIB_DIR)/$(SHLIB_SOLINK) && \ +--- a/src/libffi/Makefile.am.orig 2009-08-23 ++++ b/src/libffi/Makefile.am 2009-12-22 +@@ -164,7 +164,7 @@ + + LTLDFLAGS = $(shell $(SHELL) $(top_srcdir)/../libtool-ldflags $(LDFLAGS)) + +-libffi_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) ++libffi_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -Wl,-O1 + + AM_CPPFLAGS = -I. -I$(top_srcdir)/include -Iinclude -I$(top_srcdir)/src + AM_CCASFLAGS = $(AM_CPPFLAGS) +--- a/src/libffi/Makefile.in.orig 2009-12-07 ++++ b/src/libffi/Makefile.in 2009-12-22 +@@ -468,7 +468,7 @@ + nodist_libffi_convenience_la_SOURCES = $(nodist_libffi_la_SOURCES) + AM_CFLAGS = -Wall -g -fexceptions + LTLDFLAGS = $(shell $(SHELL) $(top_srcdir)/../libtool-ldflags $(LDFLAGS)) +-libffi_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) ++libffi_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -Wl,-O1 + AM_CPPFLAGS = -I. -I$(top_srcdir)/include -Iinclude -I$(top_srcdir)/src + AM_CCASFLAGS = $(AM_CPPFLAGS) + all: fficonfig.h +--- a/src/libgfortran/Makefile.am.orig 2009-12-01 ++++ b/src/libgfortran/Makefile.am 2009-12-22 +@@ -18,7 +18,7 @@ + + toolexeclib_LTLIBRARIES = libgfortran.la + libgfortran_la_LINK = $(LINK) $(libgfortran_la_LDFLAGS) +-libgfortran_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -lm $(extra_ldflags_libgfortran) $(version_arg) ++libgfortran_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -lm $(extra_ldflags_libgfortran) $(version_arg) -Wl,-O1 + + myexeclib_LTLIBRARIES = libgfortranbegin.la + myexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR) +--- a/src/libgfortran/Makefile.in.orig 2009-12-07 ++++ b/src/libgfortran/Makefile.in 2009-12-22 +@@ -976,7 +976,7 @@ + + toolexeclib_LTLIBRARIES = libgfortran.la + libgfortran_la_LINK = $(LINK) $(libgfortran_la_LDFLAGS) +-libgfortran_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -lm $(extra_ldflags_libgfortran) $(version_arg) ++libgfortran_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -lm $(extra_ldflags_libgfortran) $(version_arg) -Wl,-O1 + myexeclib_LTLIBRARIES = libgfortranbegin.la + myexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR) + libgfortranbegin_la_SOURCES = fmain.c +--- a/src/libjava/Makefile.am.orig 2009-12-21 ++++ b/src/libjava/Makefile.am 2009-12-22 +@@ -299,7 +299,7 @@ + GCJ_FOR_ECJX = @GCJ_FOR_ECJX@ + GCJ_FOR_ECJX_LINK = $(GCJ_FOR_ECJX) -o $@ + LIBLINK = $(LIBTOOL) --tag=CXX $(LIBTOOLFLAGS) --mode=link $(CXX) -L$(here) \ +- $(JC1FLAGS) $(LTLDFLAGS) $(extra_ldflags_libjava) $(extra_ldflags) -o $@ ++ $(JC1FLAGS) $(LTLDFLAGS) $(extra_ldflags_libjava) $(extra_ldflags) -Wl,-O1 -o $@ + CXXLINK = $(LIBTOOL) --tag=CXX $(LIBTOOLFLAGS) --mode=link $(CXXLD) \ + $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LTLDFLAGS) -o $@ + +--- a/src/libjava/Makefile.in.orig 2009-12-21 ++++ b/src/libjava/Makefile.in 2009-12-22 +@@ -1073,7 +1073,7 @@ + + GCJ_FOR_ECJX_LINK = $(GCJ_FOR_ECJX) -o $@ + LIBLINK = $(LIBTOOL) --tag=CXX $(LIBTOOLFLAGS) --mode=link $(CXX) -L$(here) \ +- $(JC1FLAGS) $(LTLDFLAGS) $(extra_ldflags_libjava) $(extra_ldflags) -o $@ ++ $(JC1FLAGS) $(LTLDFLAGS) $(extra_ldflags_libjava) $(extra_ldflags) -Wl,-O1 -o $@ + + CXXLINK = $(LIBTOOL) --tag=CXX $(LIBTOOLFLAGS) --mode=link $(CXXLD) \ + $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LTLDFLAGS) -o $@ +--- a/src/libmudflap/Makefile.am.orig 2009-08-23 ++++ b/src/libmudflap/Makefile.am 2009-12-22 +@@ -34,7 +34,7 @@ + mf-hooks2.c + libmudflap_la_LIBADD = + libmudflap_la_DEPENDENCIES = $(libmudflap_la_LIBADD) +-libmudflap_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` ++libmudflap_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` -Wl,-O1 + + + libmudflapth_la_SOURCES = \ +@@ -46,7 +46,7 @@ + libmudflapth_la_CFLAGS = -DLIBMUDFLAPTH + libmudflapth_la_LIBADD = + libmudflapth_la_DEPENDENCIES = $(libmudflapth_la_LIBADD) +-libmudflapth_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` ++libmudflapth_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` -Wl,-O1 + + + # XXX hack alert +--- a/src/libmudflap/Makefile.in.orig 2009-12-07 ++++ b/src/libmudflap/Makefile.in 2009-12-22 +@@ -320,7 +320,7 @@ + + libmudflap_la_LIBADD = + libmudflap_la_DEPENDENCIES = $(libmudflap_la_LIBADD) +-libmudflap_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` ++libmudflap_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` -Wl,-O1 + libmudflapth_la_SOURCES = \ + mf-runtime.c \ + mf-heuristics.c \ +@@ -331,7 +331,7 @@ + libmudflapth_la_CFLAGS = -DLIBMUDFLAPTH + libmudflapth_la_LIBADD = + libmudflapth_la_DEPENDENCIES = $(libmudflapth_la_LIBADD) +-libmudflapth_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` ++libmudflapth_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` -Wl,-O1 + + # XXX hack alert + # From libffi/Makefile.am +--- a/src/libobjc/Makefile.in.orig 2009-08-23 ++++ b/src/libobjc/Makefile.in 2009-12-22 +@@ -282,12 +282,14 @@ + libobjc$(libsuffix).la: $(OBJS) + $(LIBTOOL_LINK) $(CC) -o $@ $(OBJS) \ + -rpath $(toolexeclibdir) \ ++ -Wl,-O1 \ + -version-info $(LIBOBJC_VERSION) $(extra_ldflags_libobjc) \ + $(LTLDFLAGS) + + libobjc_gc$(libsuffix).la: $(OBJS_GC) + $(LIBTOOL_LINK) $(CC) -o $@ $(OBJS_GC) $(OBJC_BOEHM_GC_LIBS) \ + -rpath $(toolexeclibdir) \ ++ -Wl,-O1 \ + -version-info $(LIBOBJC_GC_VERSION) $(extra_ldflags_libobjc) \ + $(LTLDFLAGS) + +--- a/src/libstdc++-v3/src/Makefile.am.orig 2009-12-21 ++++ b/src/libstdc++-v3/src/Makefile.am 2009-12-22 +@@ -207,6 +207,7 @@ + $(top_builddir)/libsupc++/libsupc++convenience.la + + libstdc___la_LDFLAGS = \ ++ -Wl,-O1 \ + -version-info $(libtool_VERSION) ${version_arg} -lm + + libstdc___la_LINK = $(CXXLINK) $(libstdc___la_LDFLAGS) +--- a/src/libstdc++-v3/src/Makefile.in.orig 2009-12-21 ++++ b/src/libstdc++-v3/src/Makefile.in 2009-12-22 +@@ -444,6 +444,7 @@ + $(top_builddir)/libsupc++/libsupc++convenience.la + + libstdc___la_LDFLAGS = \ ++ -Wl,-O1 \ + -version-info $(libtool_VERSION) ${version_arg} -lm + + libstdc___la_LINK = $(CXXLINK) $(libstdc___la_LDFLAGS) --- gcc-4.5-4.5.2.orig/debian/patches/gcc-multiarch-linaro.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-multiarch-linaro.diff @@ -0,0 +1,355 @@ +# DP: Add multiarch support to GCC. +# DP: +# DP: Convert the multilib option to a target triplet, +# DP: add multiarch include directories and libraries path: +# DP: /usr/local/include/-linux-gnu +# DP: /usr/include/-linux-gnu +# DP: /usr/lib/-linux-gnu +# DP: to the system paths. + +2009-03-24 Arthur Loiret + + * configure.ac: Handle --enable-multiarch and --with-multiarch-defaults. + * config.gcc: Define MULTIARCH_DEFAULTS if multiarch is enabled. + * config.in [!USED_FOR_TARGET]: Undef ENABLE_MULTIARCH. + * gcc.c: include multiarch.h. + (set_multiarch_dir): New function. Adds the multiarch directories to + the library path. + [ENABLE_MULTIARCH]: Use it. + * cppdefault.c [LOCAL_INCLUDE_DIR, STANDARD_INCLUDE_DIR] Add an include + directory for multiarch directories. + * incpath.c: include multiarch.h + [ENABLE_MULTIARCH]: Add the multiarch directory to include directories. + * Makefile.in (MULTIARCH_H): New. Use it for incpath.o and gcc.o. + * multiarch.h: New file. +--- + gcc/Makefile.in | 7 ++-- + gcc/config.gcc | 9 +++++ + gcc/config.in | 4 ++ + gcc/configure.ac | 13 ++++++++ + gcc/cppdefault.c | 6 +++ + gcc/gcc.c | 41 ++++++++++++++++++++++++ + gcc/incpath.c | 28 ++++++++++++++++ + gcc/multiarch.h | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ + 8 files changed, 196 insertions(+), 3 deletions(-) + +--- a/src/gcc/config.gcc 2010-08-14 17:04:07.000000000 +0200 ++++ b/src/gcc/config.gcc 2010-08-14 17:07:02.064547238 +0200 +@@ -3560,3 +3560,12 @@ + target_cpu_default=$target_cpu_default2 + fi + fi ++ ++if test x${enable_multiarch} = xyes; then ++ multiarch_defaults=`echo ${target_noncanonical} | sed -e 's/unknown-//'` ++ multiarch_define="__`echo ${multiarch_defaults} | tr '-' '_'`__" ++ if test x${with_multiarch_defaults} != x; then ++ multiarch_defaults=${with_multiarch_defaults} ++ fi ++ tm_defines="${tm_defines} ${multiarch_define}=1 MULTIARCH_DEFAULTS=\\\"${multiarch_defaults}\\\"" ++fi +--- a/src/gcc/config.in 2010-08-14 17:04:04.000000000 +0200 ++++ b/src/gcc/config.in 2010-08-14 17:07:02.064547238 +0200 +@@ -185,6 +185,10 @@ + #undef ENABLE_WIN32_REGISTRY + #endif + ++/* Define if you want to use multiarch. */ ++#ifndef USED_FOR_TARGET ++#undef ENABLE_MULTIARCH ++#endif + + /* Define to the name of a file containing a list of extra machine modes for + this architecture. */ +--- a/src/gcc/configure.ac 2010-08-14 17:04:07.000000000 +0200 ++++ b/src/gcc/configure.ac 2010-08-14 17:07:02.064547238 +0200 +@@ -600,6 +600,19 @@ + [], [enable_multilib=yes]) + AC_SUBST(enable_multilib) + ++# Determine whether or not multiarch is enabled. ++AC_ARG_ENABLE(multiarch, ++[ --enable-multiarch enable multiarch support], ++[ ++ enable_multiarch=yes ++ AC_DEFINE(ENABLE_MULTIARCH, 1, ++ [Define if you want to use multiarch.]) ++],[]) ++AC_SUBST(enable_multiarch) ++ ++AC_ARG_WITH(multiarch-defaults, ++[ --with-multiarch-defaults set the default multiarch directory.],) ++ + # Enable __cxa_atexit for C++. + AC_ARG_ENABLE(__cxa_atexit, + [ --enable-__cxa_atexit enable __cxa_atexit for C++], +--- a/src/gcc/cppdefault.c 2007-07-26 10:37:01.000000000 +0200 ++++ b/src/gcc/cppdefault.c 2010-08-14 17:07:02.064547238 +0200 +@@ -60,6 +60,9 @@ + #endif + #ifdef LOCAL_INCLUDE_DIR + /* /usr/local/include comes before the fixincluded header files. */ ++# ifdef ENABLE_MULTIARCH ++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, ++# endif + { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 }, + #endif + #ifdef PREFIX_INCLUDE_DIR +@@ -95,6 +98,9 @@ + #endif + #ifdef STANDARD_INCLUDE_DIR + /* /usr/include comes dead last. */ ++# ifdef ENABLE_MULTIARCH ++ { STANDARD_INCLUDE_DIR, STANDARD_INCLUDE_COMPONENT, 0, 0, 1, 2 }, ++# endif + { STANDARD_INCLUDE_DIR, STANDARD_INCLUDE_COMPONENT, 0, 0, 1, 0 }, + #endif + { 0, 0, 0, 0, 0, 0 } +--- a/src/gcc/gcc.c 2010-08-14 17:04:07.000000000 +0200 ++++ b/src/gcc/gcc.c 2010-08-14 17:07:02.074547381 +0200 +@@ -72,6 +72,7 @@ + #include "system.h" + #include "coretypes.h" + #include "multilib.h" /* before tm.h */ ++#include "multiarch.h" + #include "tm.h" + #include + #if ! defined( SIGCHLD ) && defined( SIGCLD ) +@@ -376,6 +377,9 @@ + static int used_arg (const char *, int); + static int default_arg (const char *, int); + static void set_multilib_dir (void); ++#ifdef ENABLE_MULTIARCH ++static void set_multiarch_dir (void); ++#endif + static void print_multilib_info (void); + static void perror_with_name (const char *); + static void fatal_ice (const char *, ...) ATTRIBUTE_PRINTF_1 ATTRIBUTE_NORETURN; +@@ -7392,6 +7396,11 @@ + xputenv (XOBFINISH (&collect_obstack, char *)); + } + ++#ifdef ENABLE_MULTIARCH ++ /* Add the multiarch directories to libraries path. */ ++ set_multiarch_dir (); ++#endif ++ + /* Warn about any switches that no pass was interested in. */ + + for (i = 0; (int) i < n_switches; i++) +@@ -8553,6 +8562,27 @@ + multilib_os_dir = multilib_dir; + } + ++#ifdef ENABLE_MULTIARCH ++/* Add the multiarch directories to libraries path. This uses the converted ++ multiarch triplet from the multilib value. ++ For example, if the target supports -m32/-m64 as multilib option and ++ defaults to 64, it will add /usr/lib/$triplet_target64/lib to library ++ path if either -m64 or no multilib option at all is set. And it will ++ add /usr/lib/$triplet_target32 if -m32 is set. Triplets are defined in ++ multiarch.def. */ ++ ++static void ++set_multiarch_dir (void) ++{ ++ const char *path; ++ ++ path = concat (STANDARD_STARTFILE_PREFIX_2, MULTIARCH_DEFAULTS, ++ dir_separator_str, NULL); ++ add_prefix (&startfile_prefixes, path, NULL, ++ PREFIX_PRIORITY_LAST, 0, 1); ++} ++#endif ++ + /* Print out the multiple library subdirectory selection + information. This prints out a series of lines. Each line looks + like SUBDIRECTORY;@OPTION@OPTION, with as many options as is +--- a/src/gcc/incpath.c 2010-08-14 17:04:04.000000000 +0200 ++++ b/src/gcc/incpath.c 2010-08-14 17:07:02.074547381 +0200 +@@ -32,6 +32,7 @@ + #include "cppdefault.h" + #include "flags.h" + #include "toplev.h" ++#include "multiarch.h" + + /* Microsoft Windows does not natively support inodes. + VMS has non-numeric inodes. */ +@@ -134,6 +135,9 @@ + const struct default_include *p; + int relocated = cpp_relocated(); + size_t len; ++#ifdef ENABLE_MULTIARCH ++ const char *multiarch; ++#endif + + if (iprefix && (len = cpp_GCC_INCLUDE_DIR_len) != 0) + { +@@ -152,8 +156,20 @@ + if (!strncmp (p->fname, cpp_GCC_INCLUDE_DIR, len)) + { + char *str = concat (iprefix, p->fname + len, NULL); ++#ifdef ENABLE_MULTIARCH ++ if (p->multilib == 1 && imultilib) ++ str = concat (str, dir_separator_str, imultilib, NULL); ++ else if (p->multilib == 2) ++ { ++ multiarch = multilib_to_multiarch (imultilib); ++ if (!multiarch) ++ continue; ++ str = concat (str, dir_separator_str, multiarch, NULL); ++ } ++#else + if (p->multilib && imultilib) + str = concat (str, dir_separator_str, imultilib, NULL); ++#endif + add_path (str, SYSTEM, p->cxx_aware, false); + } + } +@@ -197,8 +213,20 @@ + else + str = update_path (p->fname, p->component); + ++#ifdef ENABLE_MULTIARCH ++ if (p->multilib == 1 && imultilib) ++ str = concat (str, dir_separator_str, imultilib, NULL); ++ else if (p->multilib == 2) ++ { ++ multiarch = multilib_to_multiarch (imultilib); ++ if (!multiarch) ++ continue; ++ str = concat (str, dir_separator_str, multiarch, NULL); ++ } ++#else + if (p->multilib && imultilib) + str = concat (str, dir_separator_str, imultilib, NULL); ++#endif + + add_path (str, SYSTEM, p->cxx_aware, false); + } +--- a/src/gcc/Makefile.in 2010-08-14 17:04:07.000000000 +0200 ++++ b/src/gcc/Makefile.in 2010-08-14 17:07:52.244547515 +0200 +@@ -859,6 +859,7 @@ + endif + + # Shorthand variables for dependency lists. ++MULTIARCH_H = multiarch.h + EXCEPT_H = except.h sbitmap.h vecprim.h + TOPLEV_H = toplev.h $(INPUT_H) bversion.h + TARGET_H = $(TM_H) target.h insn-modes.h +@@ -1967,7 +1968,7 @@ + + incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \ + intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \ +- $(MACHMODE_H) $(FLAGS_H) toplev.h ++ $(MACHMODE_H) $(FLAGS_H) toplev.h $(MULTIARCH_H) + + c-decl.o : c-decl.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) \ + $(RTL_H) $(C_TREE_H) $(GGC_H) $(TARGET_H) $(FLAGS_H) $(FUNCTION_H) output.h \ +@@ -2118,7 +2119,7 @@ + + gcc.o: gcc.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) intl.h multilib.h \ + Makefile $(lang_specs_files) specs.h prefix.h $(GCC_H) $(FLAGS_H) \ +- configargs.h $(OBSTACK_H) opts.h ++ configargs.h $(OBSTACK_H) opts.h $(MULTIARCH_H) + (SHLIB_LINK='$(SHLIB_LINK)'; \ + $(COMPILER) $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) \ + $(DRIVER_DEFINES) \ +--- a/src/gcc/multiarch.h 1970-01-01 01:00:00.000000000 +0100 ++++ b/src/gcc/multiarch.h 2010-08-14 17:07:02.074547381 +0200 +@@ -0,0 +1,95 @@ ++/* Header for multiarch handling (include directories, libraries path). ++ Copyright (C) 2009 Free Software Foundation, Inc. ++ Contributed by Arthur Loiret ++ ++This file is part of GCC. ++ ++GCC is free software; you can redistribute it and/or modify it under ++the terms of the GNU General Public License as published by the Free ++Software Foundation; either version 3, or (at your option) any later ++version. ++ ++GCC is distributed in the hope that it will be useful, but WITHOUT ANY ++WARRANTY; without even the implied warranty of MERCHANTABILITY or ++FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++for more details. ++ ++You should have received a copy of the GNU General Public License ++along with GCC; see the file COPYING3. If not see ++. */ ++ ++#ifndef GCC_MULTIARCH_H ++#define GCC_MULTIARCH_H ++ ++#include "tm.h" ++ ++struct multiarch_mapping ++{ ++ const char *const multilib; ++ const char *const multiarch; ++}; ++ ++const struct multiarch_mapping multiarch_mappings[] = { ++#ifdef ENABLE_MULTIARCH ++ { "", MULTIARCH_DEFAULTS }, ++# if defined(__x86_64_linux_gnu__) ++ { "32", "i386-linux-gnu" }, ++# endif ++# if defined(__i486_linux_gnu__) || defined(__i686_linux_gnu__) ++ { "64", "x86_64-linux-gnu" }, ++# endif ++# if defined(__powerpc64_linux_gnu__) ++ { "32", "powerpc-linux-gnu" }, ++# endif ++# if defined(__powerpc_linux_gnu__) ++ { "64", "powerpc64-linux-gnu" }, ++# endif ++# if defined(__sparc64_linux_gnu__) ++ { "32", "sparc-linux-gnu" }, ++# endif ++# if defined(__sparc_linux_gnu__) ++ { "64", "sparc64-linux-gnu" }, ++# endif ++# if defined(__s390x_linux_gnu__) ++ { "31", "s390-linux-gnu" }, ++# endif ++# if defined(__s390_linux_gnu__) ++ { "64", "s390x-linux-gnu" }, ++# endif ++# if defined(__mips_linux_gnu__) ++ { "n32", "mips64-linux-gnuabin32" }, ++ { "64", "mips64-linux-gnuabi64" }, ++# endif ++# if defined(__mipsel_linux_gnu__) ++ { "n32", "mips64el-linux-gnuabin32" }, ++ { "64", "mips64el-linux-gnuabi64" }, ++# endif ++# if defined(__x86_64_kfreebsd_gnu__) ++ { "32", "i386-kfreebsd-gnu" }, ++# endif ++# if defined(__sh4_linux_gnu__) ++ { "m4", "sh4-linux-gnu" }, ++ { "m4-nofpu", "sh4_nofpu-linux-gnu" }, ++# endif ++#endif /* ENABLE_MULTIARCH */ ++ { 0, 0 } ++}; ++ ++/* Convert the multilib option to the corresponding target triplet. ++ See multiarch.def and config.gcc for multilib/multiarch pairs. ++ When the default multilib is used, the corresponding multilib/multiarch ++ pair is { "", $target_tripplet }. */ ++static inline const char* ++multilib_to_multiarch (const char *imultilib) ++{ ++ const struct multiarch_mapping *p; ++ ++ for (p = multiarch_mappings; p->multiarch; p++) ++ { ++ if (!strcmp(p->multilib, imultilib ? imultilib : "")) ++ return p->multiarch; ++ } ++ return NULL; ++} ++ ++#endif /* GCC_MULTIARCH_H */ --- gcc-4.5-4.5.2.orig/debian/patches/gcc-default-ssp.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-default-ssp.diff @@ -0,0 +1,194 @@ +# DP: Turn on -fstack-protector by default for C, C++, ObjC, ObjC++. +# DP: Build libgcc using -fno-stack-protector. + +--- + gcc/Makefile.in | 2 ++ + gcc/cp/lang-specs.h | 6 +++--- + gcc/doc/invoke.texi | 4 ++++ + gcc/gcc.c | 18 ++++++++++++++---- + gcc/objc/lang-specs.h | 10 +++++----- + gcc/objcp/lang-specs.h | 8 ++++---- + 6 files changed, 32 insertions(+), 16 deletions(-) + +--- a/src/gcc/doc/invoke.texi.orig 2009-12-21 ++++ b/src/gcc/doc/invoke.texi 2009-12-21 +@@ -7853,6 +7853,10 @@ + when a function is entered and then checked when the function exits. + If a guard check fails, an error message is printed and the program exits. + ++NOTE: In Ubuntu 6.10 and later versions this option is enabled by default ++for C, C++, ObjC, ObjC++, if none of @option{-fno-stack-protector}, ++@option{-nostdlib}, nor @option{-ffreestanding} are found. ++ + @item -fstack-protector-all + @opindex fstack-protector-all + Like @option{-fstack-protector} except that all functions are protected. +--- a/src/gcc/objc/lang-specs.h.orig 2009-12-21 ++++ b/src/gcc/objc/lang-specs.h 2009-12-21 +@@ -31,13 +31,13 @@ + %{traditional|ftraditional|traditional-cpp:\ + %eGNU Objective C no longer supports traditional compilation}\ + %{save-temps|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps:%b.mi} %{!save-temps:%g.mi} \n\ +- cc1obj -fpreprocessed -fno-section-anchors %{save-temps:%b.mi} %{!save-temps:%g.mi} %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}\ ++ cc1obj -fpreprocessed -fno-section-anchors %{save-temps:%b.mi} %{!save-temps:%g.mi} %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}}\ + %{!save-temps:%{!no-integrated-cpp:\ +- cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}}\ ++ cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}}}\ + %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, + {".mi", "@objc-cpp-output", 0, 0, 0}, + {"@objc-cpp-output", +- "%{!M:%{!MM:%{!E:cc1obj -fno-section-anchors -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ ++ "%{!M:%{!MM:%{!E:cc1obj -fno-section-anchors -fpreprocessed %i %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}\ + %{!fsyntax-only:%(invoke_as)}}}} \ + %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} ", 0, 0, 0}, + {"@objective-c-header", +@@ -48,11 +48,11 @@ + %{traditional|ftraditional|traditional-cpp:\ + %eGNU Objective C no longer supports traditional compilation}\ + %{save-temps|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps:%b.mi} %{!save-temps:%g.mi} \n\ +- cc1obj -fpreprocessed %b.mi %(cc1_options) -fno-section-anchors %{print-objc-runtime-info} %{gen-decls}\ ++ cc1obj -fpreprocessed %b.mi %(cc1_options) %(ssp_default) -fno-section-anchors %{print-objc-runtime-info} %{gen-decls}\ + -o %g.s %{!o*:--output-pch=%i.gch}\ + %W{o*:--output-pch=%*}%V}\ + %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \ + %{!save-temps:%{!no-integrated-cpp:\ +- cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ ++ cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}\ + -o %g.s %{!o*:--output-pch=%i.gch}\ + %W{o*:--output-pch=%*}%V}}}}}", 0, 0, 0}, +--- a/src/gcc/objcp/lang-specs.h.orig 2009-03-24 ++++ b/src/gcc/objcp/lang-specs.h 2009-12-21 +@@ -36,7 +36,7 @@ + %(cpp_options) %2 -o %{save-temps:%b.mii} %{!save-temps:%g.mii} \n}\ + cc1objplus %{save-temps|no-integrated-cpp:-fpreprocessed %{save-temps:%b.mii} %{!save-temps:%g.mii}}\ + %{!save-temps:%{!no-integrated-cpp:%(cpp_unique_options)}}\ +- %(cc1_options) %2 %{+e1*}\ ++ %(cc1_options) %(ssp_default) %2 %{+e1*}\ + -o %g.s %{!o*:--output-pch=%i.gch} %W{o*:--output-pch=%*}%V}}}", + CPLUSPLUS_CPP_SPEC, 0, 0}, + {"@objective-c++", +@@ -46,15 +46,15 @@ + %(cpp_options) %2 -o %{save-temps:%b.mii} %{!save-temps:%g.mii} \n}\ + cc1objplus %{save-temps|no-integrated-cpp:-fpreprocessed %{save-temps:%b.mii} %{!save-temps:%g.mii}}\ + %{!save-temps:%{!no-integrated-cpp:%(cpp_unique_options)}}\ +- %(cc1_options) %2 %{+e1*}\ ++ %(cc1_options) %(ssp_default) %2 %{+e1*}\ + %{!fsyntax-only:%(invoke_as)}}}}", + CPLUSPLUS_CPP_SPEC, 0, 0}, + {".mii", "@objective-c++-cpp-output", 0, 0, 0}, + {"@objective-c++-cpp-output", + "%{!M:%{!MM:%{!E:\ +- cc1objplus -fpreprocessed %i %(cc1_options) %2 %{+e*}\ ++ cc1objplus -fpreprocessed %i %(cc1_options) %(ssp_default) %2 %{+e*}\ + %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, + {"@objc++-cpp-output", + "%{!M:%{!MM:%{!E:\ +- cc1objplus -fpreprocessed %i %(cc1_options) %2 %{+e*}\ ++ cc1objplus -fpreprocessed %i %(cc1_options) %(ssp_default) %2 %{+e*}\ + %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, +--- a/src/gcc/gcc.c.orig 2009-12-21 ++++ b/src/gcc/gcc.c 2009-12-21 +@@ -748,6 +748,14 @@ + #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G" + #endif + ++#ifndef SSP_DEFAULT_SPEC ++#ifdef TARGET_LIBC_PROVIDES_SSP ++#define SSP_DEFAULT_SPEC "%{!fstack-protector-all:%{!fno-stack-protector:%{!ffreestanding:%{!nostdlib:-fstack-protector}}}}" ++#else ++#define SSP_DEFAULT_SPEC "" ++#endif ++#endif ++ + #ifndef LINK_SSP_SPEC + #ifdef TARGET_LIBC_PROVIDES_SSP + #define LINK_SSP_SPEC "%{fstack-protector:}" +@@ -831,6 +839,7 @@ + static const char *cc1plus_spec = CC1PLUS_SPEC; + static const char *link_gcc_c_sequence_spec = LINK_GCC_C_SEQUENCE_SPEC; + static const char *link_ssp_spec = LINK_SSP_SPEC; ++static const char *ssp_default_spec = SSP_DEFAULT_SPEC; + static const char *asm_spec = ASM_SPEC; + static const char *asm_final_spec = ASM_FINAL_SPEC; + static const char *link_spec = LINK_SPEC; +@@ -891,7 +900,7 @@ + static const char *cpp_options = + "%(cpp_unique_options) %1 %{m*} %{std*&ansi&trigraphs} %{W*&pedantic*} %{w}\ + %{f*} %{g*:%{!g0:%{g*} %{!fno-working-directory:-fworking-directory}}} %{O*}\ +- %{undef} %{save-temps*:-fpch-preprocess}"; ++ %{undef} %{save-temps*:-fpch-preprocess} %(ssp_default)"; + + /* This contains cpp options which are not passed when the preprocessor + output will be used by another program. */ +@@ -1081,15 +1090,15 @@ + %{save-temps*|traditional-cpp|no-integrated-cpp:%(trad_capable_cpp) \ + %(cpp_options) -o %{save-temps*:%b.i} %{!save-temps*:%g.i} \n\ + cc1 -fpreprocessed %{save-temps*:%b.i} %{!save-temps*:%g.i} \ +- %(cc1_options)}\ ++ %(cc1_options) %(ssp_default)}\ + %{!save-temps*:%{!traditional-cpp:%{!no-integrated-cpp:\ +- cc1 %(cpp_unique_options) %(cc1_options)}}}\ ++ cc1 %(cpp_unique_options) %(cc1_options) %(ssp_default)}}}\ + %{!fsyntax-only:%(invoke_as)}} \ + %{combine:\ + %{save-temps*|traditional-cpp|no-integrated-cpp:%(trad_capable_cpp) \ + %(cpp_options) -o %{save-temps*:%b.i} %{!save-temps*:%g.i}}\ + %{!save-temps*:%{!traditional-cpp:%{!no-integrated-cpp:\ +- cc1 %(cpp_unique_options) %(cc1_options)}}\ ++ cc1 %(cpp_unique_options) %(cc1_options) %(ssp_default)}}\ + %{!fsyntax-only:%(invoke_as)}}}}}}", 0, 1, 1}, + {"-", + "%{!E:%e-E or -x required when input is from standard input}\ +@@ -1112,7 +1121,7 @@ + %W{o*:--output-pch=%*}%V}}}}}}", 0, 0, 0}, + {".i", "@cpp-output", 0, 1, 0}, + {"@cpp-output", +- "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %(cc1_options) %{!fsyntax-only:%(invoke_as)}}}}", 0, 1, 0}, ++ "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %(cc1_options) %(ssp_default) %{!fsyntax-only:%(invoke_as)}}}}", 0, 1, 0}, + {".s", "@assembler", 0, 1, 0}, + {"@assembler", + "%{!M:%{!MM:%{!E:%{!S:as %(asm_debug) %(asm_options) %i %A }}}}", 0, 1, 0}, +@@ -1672,6 +1681,7 @@ + INIT_STATIC_SPEC ("cc1plus", &cc1plus_spec), + INIT_STATIC_SPEC ("link_gcc_c_sequence", &link_gcc_c_sequence_spec), + INIT_STATIC_SPEC ("link_ssp", &link_ssp_spec), ++ INIT_STATIC_SPEC ("ssp_default", &ssp_default_spec), + INIT_STATIC_SPEC ("endfile", &endfile_spec), + INIT_STATIC_SPEC ("link", &link_spec), + INIT_STATIC_SPEC ("lib", &lib_spec), +--- a/src/gcc/cp/lang-specs.h.orig 2009-03-24 ++++ b/src/gcc/cp/lang-specs.h 2009-12-21 +@@ -47,7 +47,7 @@ + %(cpp_options) %2 -o %{save-temps:%b.ii} %{!save-temps:%g.ii} \n}\ + cc1plus %{save-temps|no-integrated-cpp:-fpreprocessed %{save-temps:%b.ii} %{!save-temps:%g.ii}}\ + %{!save-temps:%{!no-integrated-cpp:%(cpp_unique_options)}}\ +- %(cc1_options) %2 %{+e1*}\ ++ %(cc1_options) %(ssp_default) %2 %{+e1*}\ + %{!fsyntax-only:-o %g.s %{!o*:--output-pch=%i.gch} %W{o*:--output-pch=%*}%V}}}}", + CPLUSPLUS_CPP_SPEC, 0, 0}, + {"@c++", +@@ -57,11 +57,11 @@ + %(cpp_options) %2 -o %{save-temps:%b.ii} %{!save-temps:%g.ii} \n}\ + cc1plus %{save-temps|no-integrated-cpp:-fpreprocessed %{save-temps:%b.ii} %{!save-temps:%g.ii}}\ + %{!save-temps:%{!no-integrated-cpp:%(cpp_unique_options)}}\ +- %(cc1_options) %2 %{+e1*}\ ++ %(cc1_options) %(ssp_default) %2 %{+e1*}\ + %{!fsyntax-only:%(invoke_as)}}}}", + CPLUSPLUS_CPP_SPEC, 0, 0}, + {".ii", "@c++-cpp-output", 0, 0, 0}, + {"@c++-cpp-output", + "%{!M:%{!MM:%{!E:\ +- cc1plus -fpreprocessed %i %(cc1_options) %2 %{+e*}\ ++ cc1plus -fpreprocessed %i %(cc1_options) %(ssp_default) %2 %{+e*}\ + %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, +--- a/src/gcc/params.def.orig 2010-09-09 11:00:26.579149661 -0700 ++++ b/src/gcc/params.def 2010-09-09 11:00:37.968871185 -0700 +@@ -616,7 +616,7 @@ + DEFPARAM (PARAM_SSP_BUFFER_SIZE, + "ssp-buffer-size", + "The lower bound for a buffer to be considered for stack smashing protection", +- 8, 1, 0) ++ 4, 1, 0) + + /* When we thread through a block we have to make copies of the + statements within the block. Clearly for large blocks the code --- gcc-4.5-4.5.2.orig/debian/patches/gcc-textdomain.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-textdomain.diff @@ -0,0 +1,84 @@ +# DP: Set gettext's domain and textdomain to the versioned package name. + +--- a/src/gcc/intl.c.orig 2009-12-15 ++++ b/src/gcc/intl.c 2009-12-20 +@@ -57,8 +57,8 @@ + setlocale (LC_ALL, ""); + #endif + +- (void) bindtextdomain ("gcc", LOCALEDIR); +- (void) textdomain ("gcc"); ++ (void) bindtextdomain ("gcc-4.5", LOCALEDIR); ++ (void) textdomain ("gcc-4.5"); + + /* Opening quotation mark. */ + open_quote = _("`"); +--- a/src/gcc/Makefile.in.orig 2009-12-20 ++++ b/src/gcc/Makefile.in 2009-12-20 +@@ -4971,8 +4971,8 @@ + dir=$(localedir)/$$lang/LC_MESSAGES; \ + echo $(mkinstalldirs) $(DESTDIR)$$dir; \ + $(mkinstalldirs) $(DESTDIR)$$dir || exit 1; \ +- echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc.mo; \ +- $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc.mo; \ ++ echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc-4.5.mo; \ ++ $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc-4.5.mo; \ + done + + # Rule for regenerating the message template (gcc.pot). +--- a/src/libcpp/init.c.orig 2009-11-16 ++++ b/src/libcpp/init.c 2009-12-20 +@@ -133,7 +133,7 @@ + init_trigraph_map (); + + #ifdef ENABLE_NLS +- (void) bindtextdomain (PACKAGE, LOCALEDIR); ++ (void) bindtextdomain (PACKAGE PACKAGE_SUFFIX, LOCALEDIR); + #endif + } + } +--- a/src/libcpp/system.h.orig 2009-04-11 ++++ b/src/libcpp/system.h 2009-12-20 +@@ -259,7 +259,7 @@ + #endif + + #ifndef _ +-# define _(msgid) dgettext (PACKAGE, msgid) ++# define _(msgid) dgettext (PACKAGE PACKAGE_SUFFIX, msgid) + #endif + + #ifndef N_ +--- a/src/libcpp/Makefile.in.orig 2009-09-23 ++++ b/src/libcpp/Makefile.in 2009-12-20 +@@ -49,6 +49,7 @@ + LIBICONV = @LIBICONV@ + LIBINTL = @LIBINTL@ + PACKAGE = @PACKAGE@ ++PACKAGE_SUFFIX = -4.5 + RANLIB = @RANLIB@ + SHELL = @SHELL@ + USED_CATALOGS = @USED_CATALOGS@ +@@ -70,9 +71,10 @@ + + INCLUDES = -I$(srcdir) -I. -I$(srcdir)/../include @INCINTL@ \ + -I$(srcdir)/include ++DEBCPPFLAGS += -DPACKAGE_SUFFIX=\"$(strip $(PACKAGE_SUFFIX))\" + +-ALL_CFLAGS = $(CFLAGS) $(WARN_CFLAGS) $(INCLUDES) $(CPPFLAGS) +-ALL_CXXFLAGS = $(CXXFLAGS) $(WARN_CXXFLAGS) $(INCLUDES) $(CPPFLAGS) ++ALL_CFLAGS = $(CFLAGS) $(WARN_CFLAGS) $(INCLUDES) $(CPPFLAGS) $(DEBCPPFLAGS) ++ALL_CXXFLAGS = $(CXXFLAGS) $(WARN_CXXFLAGS) $(INCLUDES) $(CPPFLAGS) $(DEBCPPFLAGS) + + # The name of the compiler to use. + ENABLE_BUILD_WITH_CXX = @ENABLE_BUILD_WITH_CXX@ +@@ -168,8 +170,8 @@ + else continue; \ + fi; \ + dir=$(localedir)/$$lang/LC_MESSAGES; \ +- echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/$(PACKAGE).mo; \ +- $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/$(PACKAGE).mo; \ ++ echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/$(PACKAGE)$(PACKAGE_SUFFIX).mo; \ ++ $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/$(PACKAGE)$(PACKAGE_SUFFIX).mo; \ + done + + mostlyclean: --- gcc-4.5-4.5.2.orig/debian/patches/sparc-force-cpu.diff +++ gcc-4.5-4.5.2/debian/patches/sparc-force-cpu.diff @@ -0,0 +1,18 @@ +# DP: On sparc default to ultrasparc (v9a) in 32bit mode + +--- a/src/gcc/config.gcc~ 2009-10-18 03:09:56.000000000 +0200 ++++ b/src/gcc/config.gcc 2009-10-21 14:44:57.000000000 +0200 +@@ -3156,6 +3156,13 @@ + ;; + esac + ++ # setting this directly fails to build a biarch defaulting to 32bit ++ case "$target" in sparc*-*-linux*) ++ if test "$option" = cpu; then ++ val=ultrasparc ++ fi ++ esac ++ + if test "x$t" = x + then + t="{ \"$option\", \"$val\" }" --- gcc-4.5-4.5.2.orig/debian/patches/libgcc-no-ssp.diff +++ gcc-4.5-4.5.2/debian/patches/libgcc-no-ssp.diff @@ -0,0 +1,20 @@ +# DP: Build libgcc with -fno-stack-protector + +--- a/src/gcc/Makefile.in ++++ b/src/gcc/Makefile.in +@@ -646,6 +646,7 @@ + LIBGCC2_CFLAGS = -O2 $(LIBGCC2_INCLUDES) $(GCC_CFLAGS) $(TARGET_LIBGCC2_CFLAGS) \ + $(LIBGCC2_DEBUG_CFLAGS) $(GTHREAD_FLAGS) \ + -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED \ ++ -fno-stack-protector \ + $(INHIBIT_LIBC_CFLAGS) + + # Additional options to use when compiling libgcc2.a. +@@ -659,6 +660,7 @@ + CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \ + -finhibit-size-directive -fno-inline -fno-exceptions \ + -fno-zero-initialized-in-bss -fno-toplevel-reorder -fno-tree-vectorize \ ++ -fno-stack-protector \ + $(INHIBIT_LIBC_CFLAGS) + + # Additional sources to handle exceptions; overridden by targets as needed. --- gcc-4.5-4.5.2.orig/debian/patches/ignore-comp-fail.diff +++ gcc-4.5-4.5.2/debian/patches/ignore-comp-fail.diff @@ -0,0 +1,19 @@ +# DP: Ignore the bootstrap comparision failure + +--- + Makefile.in | 4 +++- + 1 files changed, 3 insertions(+), 1 deletions(-) + +--- a/src/Makefile.in ++++ b/src/Makefile.in +@@ -53636,7 +53636,9 @@ compare: + if [ -f .bad_compare ]; then \ + echo "Bootstrap comparison failure!"; \ + cat .bad_compare; \ +- exit 1; \ ++ echo ""; \ ++ echo "Ignore the comparision failure!"; \ ++ true; \ + else \ + echo Comparison successful.; \ + fi ; \ --- gcc-4.5-4.5.2.orig/debian/patches/armhf-triplet-backport.diff +++ gcc-4.5-4.5.2/debian/patches/armhf-triplet-backport.diff @@ -0,0 +1,120 @@ +# DP: add support for arm-linux-*eabi* triplets; useful for armhf + +Index: gcc-4.5-4.5.2/src/configure.ac +=================================================================== +--- gcc-4.5-4.5.2.orig/src/configure.ac 2011-03-18 19:10:48.804622758 +0000 ++++ gcc-4.5-4.5.2/src/configure.ac 2011-03-18 19:11:18.324622793 +0000 +@@ -592,7 +592,7 @@ + noconfigdirs="$noconfigdirs target-libffi target-qthreads" + libgloss_dir=arm + ;; +- arm*-*-linux-gnueabi) ++ arm*-*-linux-*eabi*) + noconfigdirs="$noconfigdirs target-qthreads" + case ${with_newlib} in + no) noconfigdirs="$noconfigdirs target-newlib target-libgloss" +Index: gcc-4.5-4.5.2/src/gcc/ada/gcc-interface/Makefile.in +=================================================================== +--- gcc-4.5-4.5.2.orig/src/gcc/ada/gcc-interface/Makefile.in 2011-03-18 19:11:37.296622753 +0000 ++++ gcc-4.5-4.5.2/src/gcc/ada/gcc-interface/Makefile.in 2011-03-18 19:11:52.964621827 +0000 +@@ -1857,7 +1857,7 @@ + LIBRARY_VERSION := $(LIB_VERSION) + endif + +-ifeq ($(strip $(filter-out arm% linux-gnueabi,$(arch) $(osys)-$(word 4,$(targ)))),) ++ifeq ($(strip $(filter-out arm%-linux,$(arch)-$(osys)) $(if $(findstring eabi,$(word 4,$(targ))),,$(word 4,$(targ)))),) + LIBGNAT_TARGET_PAIRS = \ + a-intnam.ads + // +Index: gcc-4.5-4.5.2/src/libstdc++-v3/testsuite/20_util/make_unsigned/requirements/typedefs-2.cc +=================================================================== +--- gcc-4.5-4.5.2.orig/src/libstdc++-v3/testsuite/20_util/make_unsigned/requirements/typedefs-2.cc 2011-03-18 19:16:31.144622761 +0000 ++++ gcc-4.5-4.5.2/src/libstdc++-v3/testsuite/20_util/make_unsigned/requirements/typedefs-2.cc 2011-03-18 19:16:41.420622950 +0000 +@@ -1,5 +1,5 @@ + // { dg-options "-std=gnu++0x -funsigned-char -fshort-enums" } +-// { dg-options "-std=gnu++0x -funsigned-char -fshort-enums -Wl,--no-enum-size-warning" { target arm*-*-linux*eabi } } ++// { dg-options "-std=gnu++0x -funsigned-char -fshort-enums -Wl,--no-enum-size-warning" { target arm*-*-linux-*eabi* } } + + // 2007-05-03 Benjamin Kosnik + // --- gcc-4.5-4.5.2.orig/debian/patches/gcc-default-fortify-source.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-default-fortify-source.diff @@ -0,0 +1,32 @@ +# DP: Turn on -D_FORTIFY_SOURCE=2 by default for C, C++, ObjC, ObjC++. + +--- + gcc/doc/invoke.texi | 6 ++++++ + gcc/gcc.c | 1 + + 2 files changed, 7 insertions(+), 0 deletions(-) + +--- a/src/gcc/doc/invoke.texi ++++ b/src/gcc/doc/invoke.texi +@@ -5415,6 +5415,12 @@ also turns on the following optimization flags: + Please note the warning under @option{-fgcse} about + invoking @option{-O2} on programs that use computed gotos. + ++NOTE: In Ubuntu 8.10 and later versions, @option{-D_FORTIFY_SOURCE=2} is ++set by default, and is activated when @option{-O} is set to 2 or higher. ++This enables additional compile-time and run-time checks for several libc ++functions. To disable, specify either @option{-U_FORTIFY_SOURCE} or ++@option{-D_FORTIFY_SOURCE=0}. ++ + @item -O3 + @opindex O3 + Optimize yet more. @option{-O3} turns on all optimizations specified +--- a/src/gcc/gcc.c ++++ b/src/gcc/gcc.c +@@ -810,6 +810,7 @@ static const char *cpp_unique_options = + %{H} %C %{D*&U*&A*} %{i*} %Z %i\ + %{fmudflap:-D_MUDFLAP -include mf-runtime.h}\ + %{fmudflapth:-D_MUDFLAP -D_MUDFLAPTH -include mf-runtime.h}\ ++ %{!D_FORTIFY_SOURCE:%{!D_FORTIFY_SOURCE=*:%{!U_FORTIFY_SOURCE:-D_FORTIFY_SOURCE=2}}}\ + %{E|M|MM:%W{o*}}"; + + /* This contains cpp options which are common with cc1_options and are passed --- gcc-4.5-4.5.2.orig/debian/patches/alpha-no-ev4-directive.diff +++ gcc-4.5-4.5.2/debian/patches/alpha-no-ev4-directive.diff @@ -0,0 +1,30 @@ +# DP: never emit .ev4 directive. + +--- + gcc/config/alpha/alpha.c | 7 +++---- + 1 files changed, 3 insertions(+), 4 deletions(-) + +--- a/src/gcc/config/alpha/alpha.c ++++ b/src/gcc/config/alpha/alpha.c +@@ -9421,7 +9421,7 @@ alpha_file_start (void) + fputs ("\t.set nomacro\n", asm_out_file); + if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX) + { +- const char *arch; ++ const char *arch = NULL; + + if (alpha_cpu == PROCESSOR_EV6 || TARGET_FIX || TARGET_CIX) + arch = "ev6"; +@@ -9431,10 +9431,9 @@ alpha_file_start (void) + arch = "ev56"; + else if (alpha_cpu == PROCESSOR_EV5) + arch = "ev5"; +- else +- arch = "ev4"; + +- fprintf (asm_out_file, "\t.arch %s\n", arch); ++ if (arch) ++ fprintf (asm_out_file, "\t.arch %s\n", arch); + } + } + #endif --- gcc-4.5-4.5.2.orig/debian/patches/s390-biarch.diff +++ gcc-4.5-4.5.2/debian/patches/s390-biarch.diff @@ -0,0 +1,24 @@ +# DP: Build a bi-arch compiler on s390-linux-gnu. +# DP: http://gcc.gnu.org/ml/gcc-patches/2009-03/msg01044.html + +2009-03-23 Arthur Loiret + + * config.gcc (s390-*-linux*): If 'enabled_targets' is 'all', build + a bi-arch compiler defaulting to 31-bit. In this case: + (tmake_file): Add s390/t-linux64. +--- + gcc/config.gcc | 3 +++ + 1 files changed, 3 insertions(+), 0 deletions(-) + +--- a/src/gcc/config.gcc 2009-12-08 12:55:09.000000000 +0100 ++++ b/src/gcc/config.gcc 2009-12-11 11:19:35.000000000 +0100 +@@ -2099,6 +2099,9 @@ + ;; + s390-*-linux*) + tm_file="s390/s390.h dbxelf.h elfos.h svr4.h linux.h glibc-stdint.h s390/linux.h" ++ if test x$enable_targets = xall; then ++ tmake_file="${tmake_file} s390/t-linux64" ++ fi + ;; + s390x-*-linux*) + tm_file="s390/s390x.h s390/s390.h dbxelf.h elfos.h svr4.h linux.h glibc-stdint.h s390/linux.h" --- gcc-4.5-4.5.2.orig/debian/patches/gcc-ice-hack-trunk.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-ice-hack-trunk.diff @@ -0,0 +1,315 @@ +# DP: Retry the build on an ice, save the calling options and preprocessed +# DP: source when the ice is reproducible. + +2004-01-23 Jakub Jelinek + + * system.h (ICE_EXIT_CODE): Define. + * gcc.c (execute): Don't free first string early, but at the end + of the function. Call retry_ice if compiler exited with + ICE_EXIT_CODE. + (retry_ice): New function. + * diagnostic.c (diagnostic_count_diagnostic, + diagnostic_action_after_output, error_recursion): Exit with + ICE_EXIT_CODE instead of FATAL_EXIT_CODE. + +--- + gcc/Makefile.in | 2 + + gcc/diagnostic.c | 2 +- + gcc/gcc.c | 236 +++++++++++++++++++++++++++++++++++++++++++++++++++++- + 3 files changed, 238 insertions(+), 2 deletions(-) + +#--- a/src/gcc/Makefile.in +#+++ b/src/gcc/Makefile.in +#@@ -181,6 +181,8 @@ SYSCALLS.c.X-warn = -Wno-strict-prototypes -Wno-error +# dfp.o-warn = -Wno-error +# # mips-tfile.c contains -Wcast-qual warnings. +# mips-tfile.o-warn = -Wno-error +#+# gcc-ice-hack +#+gcc.o-warn = -Wno-error +# +# # All warnings have to be shut off in stage1 if the compiler used then +# # isn't gcc; configure determines that. WARN_CFLAGS will be either +--- a/src/gcc/diagnostic.c ++++ b/src/gcc/diagnostic.c +@@ -195,7 +195,7 @@ diagnostic_action_after_output (diagnostic_context *context, + fnotice (stderr, "Please submit a full bug report,\n" + "with preprocessed source if appropriate.\n" + "See %s for instructions.\n", bug_report_url); +- exit (ICE_EXIT_CODE); ++ exit (FATAL_EXIT_CODE); + + case DK_FATAL: + if (context->abort_on_error) +--- a/src/gcc/gcc.c ++++ b/src/gcc/gcc.c +@@ -365,6 +365,9 @@ static void init_gcc_specs (struct obstack *, const char *, const char *, + #if defined(HAVE_TARGET_OBJECT_SUFFIX) || defined(HAVE_TARGET_EXECUTABLE_SUFFIX) + static const char *convert_filename (const char *, int, int); + #endif ++#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS)) ++static void retry_ice (const char *prog, const char **argv); ++#endif + + static const char *getenv_spec_function (int, const char **); + static const char *if_exists_spec_function (int, const char **); +@@ -3015,7 +3018,7 @@ execute (void) + } + } + +- if (string != commands[i].prog) ++ if (i && string != commands[i].prog) + free (CONST_CAST (char *, string)); + } + +@@ -3072,6 +3075,16 @@ See %s for instructions.", + else if (WIFEXITED (status) + && WEXITSTATUS (status) >= MIN_FATAL_STATUS) + { ++#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS)) ++ /* For ICEs in cc1, cc1obj, cc1plus see if it is ++ reproducible or not. */ ++ char *p; ++ if (WEXITSTATUS (status) == ICE_EXIT_CODE ++ && i == 0 ++ && (p = strrchr (commands[0].argv[0], DIR_SEPARATOR)) ++ && ! strncmp (p + 1, "cc1", 3)) ++ retry_ice (commands[0].prog, commands[0].argv); ++#endif + if (WEXITSTATUS (status) > greatest_status) + greatest_status = WEXITSTATUS (status); + ret_code = -1; +@@ -3092,6 +3105,9 @@ See %s for instructions.", + } + } + ++ if (commands[0].argv[0] != commands[0].prog) ++ free ((PTR) commands[0].argv[0]); ++ + return ret_code; + } + } +@@ -6108,6 +6124,224 @@ give_switch (int switchnum, int omit_first_word) + switches[switchnum].validated = 1; + } + ++#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS)) ++#define RETRY_ICE_ATTEMPTS 2 ++ ++static void ++retry_ice (const char *prog, const char **argv) ++{ ++ int nargs, out_arg = -1, quiet = 0, attempt; ++ int pid, retries, sleep_interval; ++ const char **new_argv; ++ char *temp_filenames[RETRY_ICE_ATTEMPTS * 2 + 2]; ++ ++ if (input_filename == NULL || ! strcmp (input_filename, "-")) ++ return; ++ ++ for (nargs = 0; argv[nargs] != NULL; ++nargs) ++ /* Only retry compiler ICEs, not preprocessor ones. */ ++ if (! strcmp (argv[nargs], "-E")) ++ return; ++ else if (argv[nargs][0] == '-' && argv[nargs][1] == 'o') ++ { ++ if (out_arg == -1) ++ out_arg = nargs; ++ else ++ return; ++ } ++ /* If the compiler is going to output any time information, ++ it might vary between invocations. */ ++ else if (! strcmp (argv[nargs], "-quiet")) ++ quiet = 1; ++ else if (! strcmp (argv[nargs], "-ftime-report")) ++ return; ++ ++ if (out_arg == -1 || !quiet) ++ return; ++ ++ memset (temp_filenames, '\0', sizeof (temp_filenames)); ++ new_argv = alloca ((nargs + 3) * sizeof (const char *)); ++ memcpy (new_argv, argv, (nargs + 1) * sizeof (const char *)); ++ new_argv[nargs++] = "-frandom-seed=0"; ++ new_argv[nargs] = NULL; ++ if (new_argv[out_arg][2] == '\0') ++ new_argv[out_arg + 1] = "-"; ++ else ++ new_argv[out_arg] = "-o-"; ++ ++ for (attempt = 0; attempt < RETRY_ICE_ATTEMPTS + 1; ++attempt) ++ { ++ int fd = -1; ++ int status; ++ ++ temp_filenames[attempt * 2] = make_temp_file (".out"); ++ temp_filenames[attempt * 2 + 1] = make_temp_file (".err"); ++ ++ if (attempt == RETRY_ICE_ATTEMPTS) ++ { ++ int i; ++ int fd1, fd2; ++ struct stat st1, st2; ++ size_t n, len; ++ char *buf; ++ ++ buf = xmalloc (8192); ++ ++ for (i = 0; i < 2; ++i) ++ { ++ fd1 = open (temp_filenames[i], O_RDONLY); ++ fd2 = open (temp_filenames[2 + i], O_RDONLY); ++ ++ if (fd1 < 0 || fd2 < 0) ++ { ++ i = -1; ++ close (fd1); ++ close (fd2); ++ break; ++ } ++ ++ if (fstat (fd1, &st1) < 0 || fstat (fd2, &st2) < 0) ++ { ++ i = -1; ++ close (fd1); ++ close (fd2); ++ break; ++ } ++ ++ if (st1.st_size != st2.st_size) ++ { ++ close (fd1); ++ close (fd2); ++ break; ++ } ++ ++ len = 0; ++ for (n = st1.st_size; n; n -= len) ++ { ++ len = n; ++ if (len > 4096) ++ len = 4096; ++ ++ if (read (fd1, buf, len) != (int) len ++ || read (fd2, buf + 4096, len) != (int) len) ++ { ++ i = -1; ++ break; ++ } ++ ++ if (memcmp (buf, buf + 4096, len) != 0) ++ break; ++ } ++ ++ close (fd1); ++ close (fd2); ++ ++ if (n) ++ break; ++ } ++ ++ free (buf); ++ if (i == -1) ++ break; ++ ++ if (i != 2) ++ { ++ fnotice (stderr, "The bug is not reproducible, so it is likely a hardware or OS problem.\n"); ++ break; ++ } ++ ++ fd = open (temp_filenames[attempt * 2], O_RDWR); ++ if (fd < 0) ++ break; ++ write (fd, "//", 2); ++ for (i = 0; i < nargs; i++) ++ { ++ write (fd, " ", 1); ++ write (fd, new_argv[i], strlen (new_argv[i])); ++ } ++ write (fd, "\n", 1); ++ new_argv[nargs] = "-E"; ++ new_argv[nargs + 1] = NULL; ++ } ++ ++ /* Fork a subprocess; wait and retry if it fails. */ ++ sleep_interval = 1; ++ pid = -1; ++ for (retries = 0; retries < 4; retries++) ++ { ++ pid = fork (); ++ if (pid >= 0) ++ break; ++ sleep (sleep_interval); ++ sleep_interval *= 2; ++ } ++ ++ if (pid < 0) ++ break; ++ else if (pid == 0) ++ { ++ if (attempt != RETRY_ICE_ATTEMPTS) ++ fd = open (temp_filenames[attempt * 2], O_RDWR); ++ if (fd < 0) ++ exit (-1); ++ if (fd != 1) ++ { ++ close (1); ++ dup (fd); ++ close (fd); ++ } ++ ++ fd = open (temp_filenames[attempt * 2 + 1], O_RDWR); ++ if (fd < 0) ++ exit (-1); ++ if (fd != 2) ++ { ++ close (2); ++ dup (fd); ++ close (fd); ++ } ++ ++ if (prog == new_argv[0]) ++ execvp (prog, (char *const *) new_argv); ++ else ++ execv (new_argv[0], (char *const *) new_argv); ++ exit (-1); ++ } ++ ++ if (waitpid (pid, &status, 0) < 0) ++ break; ++ ++ if (attempt < RETRY_ICE_ATTEMPTS ++ && (! WIFEXITED (status) || WEXITSTATUS (status) != ICE_EXIT_CODE)) ++ { ++ fnotice (stderr, "The bug is not reproducible, so it is likely a hardware or OS problem.\n"); ++ break; ++ } ++ else if (attempt == RETRY_ICE_ATTEMPTS) ++ { ++ close (fd); ++ if (WIFEXITED (status) ++ && WEXITSTATUS (status) == SUCCESS_EXIT_CODE) ++ { ++ fnotice (stderr, "Preprocessed source stored into %s file, please attach this to your bugreport.\n", ++ temp_filenames[attempt * 2]); ++ /* Make sure it is not deleted. */ ++ free (temp_filenames[attempt * 2]); ++ temp_filenames[attempt * 2] = NULL; ++ break; ++ } ++ } ++ } ++ ++ for (attempt = 0; attempt < RETRY_ICE_ATTEMPTS * 2 + 2; attempt++) ++ if (temp_filenames[attempt]) ++ { ++ unlink (temp_filenames[attempt]); ++ free (temp_filenames[attempt]); ++ } ++} ++#endif ++ + /* Search for a file named NAME trying various prefixes including the + user's -B prefix and some standard ones. + Return the absolute file name found. If nothing is found, return NAME. */ --- gcc-4.5-4.5.2.orig/debian/patches/gcc-linaro-updates.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-linaro-updates.diff @@ -0,0 +1,352 @@ +# DP: Post Linaro 4.5-2011.03-0 release changes (up to 20110313). + +--- a/src/ChangeLog.linaro ++++ b/src/ChangeLog.linaro +@@ -1,3 +1,48 @@ ++2011-03-10 Ramana Radhakrishnan ++ ++ LP:730440 ++ PR target/47668 ++ gcc/ ++ * config/arm/arm.md (arm_movtas_ze): Use 'L' instead of 'c'. ++ gcc/testsuite/ ++ * gcc.target/arm/pr47688.c: New. ++ ++2011-03-03 Richard Sandiford ++ ++ gcc/ ++ * ee.c (reg_use_p): Handle subregs of promoted vars. ++ ++2011-03-11 Andrew Stubbs ++ Michael Hope ++ Matthias Klose ++ ++ gcc/ ++ * function. (thread_prologue_and_epilogue_insns): Initialize ++ prologue_seq. ++ * opts.c (decode_options): Move flag_shrink_wrap to -O1. ++ ++2011-03-09 Bernd Schmidt ++ ++ Issue #10649 ++ gcc/ ++ * dwarf2out.c (dwarf2out_begin_epilogue): Accept simplejumps ++ as well as returnjumps. ++ * cfganal.c (set_edge_can_fallthru_flag): Revert previous change ++ that tried to keep epilogue blocks adjacent. ++ ++2011-02-03 Bernd Schmidt ++ ++ gcc/ ++ * function.c (prepare_shrink_wrap): New function. ++ (thread_prologue_and_epilogue_insns): Call it. ++ ++2011-03-03 Andrew Stubbs ++ ++ GCC Linaro 4.5-2011.03-0 released. ++ ++ gcc/ ++ * LINARO-VERSION: Update. ++ + 2011-02-11 Richard Sandiford + + gcc/ +--- a/src/gcc/cfganal.c ++++ b/src/gcc/cfganal.c +@@ -271,37 +271,6 @@ + EDGE_SUCC (bb, 0)->flags |= EDGE_CAN_FALLTHRU; + EDGE_SUCC (bb, 1)->flags |= EDGE_CAN_FALLTHRU; + } +- /* dwarf2out expects that a NOTE_INSN_EPILOGUE_BEGIN is always paired +- with a return or a sibcall. Ensure that this remains the case if +- they are in different basic blocks. */ +- FOR_EACH_BB (bb) +- { +- edge e; +- edge_iterator ei; +- rtx insn, end; +- +- end = BB_END (bb); +- FOR_BB_INSNS (bb, insn) +- if (GET_CODE (insn) == NOTE +- && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG +- && !(CALL_P (end) && SIBLING_CALL_P (end)) +- && !returnjump_p (end)) +- { +- basic_block other_bb = NULL; +- FOR_EACH_EDGE (e, ei, bb->succs) +- { +- if (e->flags & EDGE_FALLTHRU) +- other_bb = e->dest; +- else +- e->flags &= ~EDGE_CAN_FALLTHRU; +- } +- FOR_EACH_EDGE (e, ei, other_bb->preds) +- { +- if (!(e->flags & EDGE_FALLTHRU)) +- e->flags &= ~EDGE_CAN_FALLTHRU; +- } +- } +- } + } + + /* Find unreachable blocks. An unreachable block will have 0 in +--- a/src/gcc/config/arm/arm.md ++++ b/src/gcc/config/arm/arm.md +@@ -11133,13 +11133,15 @@ + [(set_attr "conds" "clob")] + ) + ++;; We only care about the lower 16 bits of the constant ++;; being inserted into the upper 16 bits of the register. + (define_insn "*arm_movtas_ze" + [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") + (const_int 16) + (const_int 16)) + (match_operand:SI 1 "const_int_operand" ""))] + "arm_arch_thumb2" +- "movt%?\t%0, %c1" ++ "movt%?\t%0, %L1" + [(set_attr "predicable" "yes") + (set_attr "length" "4")] + ) +--- a/src/gcc/dwarf2out.c ++++ b/src/gcc/dwarf2out.c +@@ -2782,10 +2782,10 @@ + dwarf2out_frame_debug_expr (insn, label); + } + +-/* Determine if we need to save and restore CFI information around this +- epilogue. If SIBCALL is true, then this is a sibcall epilogue. If +- we do need to save/restore, then emit the save now, and insert a +- NOTE_INSN_CFA_RESTORE_STATE at the appropriate place in the stream. */ ++/* Determine if we need to save and restore CFI information around ++ this epilogue. If we do need to save/restore, then emit the save ++ now, and insert a NOTE_INSN_CFA_RESTORE_STATE at the appropriate ++ place in the stream. */ + + void + dwarf2out_begin_epilogue (rtx insn) +@@ -2800,8 +2800,10 @@ + if (!INSN_P (i)) + continue; + +- /* Look for both regular and sibcalls to end the block. */ +- if (returnjump_p (i)) ++ /* Look for both regular and sibcalls to end the block. Various ++ optimization passes may cause us to jump to a common epilogue ++ tail, so we also accept simplejumps. */ ++ if (returnjump_p (i) || simplejump_p (i)) + break; + if (CALL_P (i) && SIBLING_CALL_P (i)) + break; +--- a/src/gcc/ee.c ++++ b/src/gcc/ee.c +@@ -209,7 +209,11 @@ + + *regno = REGNO (reg); + +- if (paradoxical_subreg_p (use)) ++ /* Non-paradoxical SUBREGs of promoted vars guarantee that the ++ upper (elided) bits of the inner register have a particular value. ++ For our purposes, such SUBREGs act as a full reference to the ++ inner register. */ ++ if (paradoxical_subreg_p (use) || SUBREG_PROMOTED_VAR_P (use)) + *size = GET_MODE_BITSIZE (GET_MODE (reg)); + else + *size = subreg_lsb (use) + GET_MODE_BITSIZE (GET_MODE (use)); +--- a/src/gcc/function.c ++++ b/src/gcc/function.c +@@ -5038,6 +5038,127 @@ + return true; + return false; + } ++ ++/* Look for sets of call-saved registers in the first block of the ++ function, and move them down into successor blocks if the register ++ is used only on one path. This exposes more opportunities for ++ shrink-wrapping. ++ These kinds of sets often occur when incoming argument registers are ++ moved to call-saved registers because their values are live across ++ one or more calls during the function. */ ++ ++static void ++prepare_shrink_wrap (basic_block entry_block) ++{ ++ rtx insn, curr; ++ FOR_BB_INSNS_SAFE (entry_block, insn, curr) ++ { ++ basic_block next_bb; ++ edge e, live_edge; ++ edge_iterator ei; ++ rtx set, scan; ++ unsigned destreg, srcreg; ++ ++ if (!NONDEBUG_INSN_P (insn)) ++ continue; ++ set = single_set (insn); ++ if (!set) ++ continue; ++ ++ if (!REG_P (SET_SRC (set)) || !REG_P (SET_DEST (set))) ++ continue; ++ srcreg = REGNO (SET_SRC (set)); ++ destreg = REGNO (SET_DEST (set)); ++ if (hard_regno_nregs[srcreg][GET_MODE (SET_SRC (set))] > 1 ++ || hard_regno_nregs[destreg][GET_MODE (SET_DEST (set))] > 1) ++ continue; ++ ++ next_bb = entry_block; ++ scan = insn; ++ ++ for (;;) ++ { ++ live_edge = NULL; ++ FOR_EACH_EDGE (e, ei, next_bb->succs) ++ { ++ if (REGNO_REG_SET_P (df_get_live_in (e->dest), destreg)) ++ { ++ if (live_edge) ++ { ++ live_edge = NULL; ++ break; ++ } ++ live_edge = e; ++ } ++ } ++ if (!live_edge) ++ break; ++ /* We can sometimes encounter dead code. Don't try to move it ++ into the exit block. */ ++ if (live_edge->dest == EXIT_BLOCK_PTR) ++ break; ++ if (EDGE_COUNT (live_edge->dest->preds) > 1) ++ break; ++ while (scan != BB_END (next_bb)) ++ { ++ scan = NEXT_INSN (scan); ++ if (NONDEBUG_INSN_P (scan)) ++ { ++ rtx link; ++ HARD_REG_SET set_regs; ++ ++ CLEAR_HARD_REG_SET (set_regs); ++ note_stores (PATTERN (scan), record_hard_reg_sets, ++ &set_regs); ++ if (CALL_P (scan)) ++ IOR_HARD_REG_SET (set_regs, call_used_reg_set); ++ for (link = REG_NOTES (scan); link; link = XEXP (link, 1)) ++ if (REG_NOTE_KIND (link) == REG_INC) ++ record_hard_reg_sets (XEXP (link, 0), NULL, &set_regs); ++ ++ if (TEST_HARD_REG_BIT (set_regs, srcreg) ++ || reg_referenced_p (SET_DEST (set), ++ PATTERN (scan))) ++ { ++ scan = NULL_RTX; ++ break; ++ } ++ if (CALL_P (scan)) ++ { ++ rtx link = CALL_INSN_FUNCTION_USAGE (scan); ++ while (link) ++ { ++ rtx tmp = XEXP (link, 0); ++ if (GET_CODE (tmp) == USE ++ && reg_referenced_p (SET_DEST (set), tmp)) ++ break; ++ link = XEXP (link, 1); ++ } ++ if (link) ++ { ++ scan = NULL_RTX; ++ break; ++ } ++ } ++ } ++ } ++ if (!scan) ++ break; ++ next_bb = live_edge->dest; ++ } ++ ++ if (next_bb != entry_block) ++ { ++ rtx after = BB_HEAD (next_bb); ++ while (!NOTE_P (after) ++ || NOTE_KIND (after) != NOTE_INSN_BASIC_BLOCK) ++ after = NEXT_INSN (after); ++ emit_insn_after (PATTERN (insn), after); ++ delete_insn (insn); ++ } ++ } ++} ++ + #endif + + #ifdef HAVE_return +@@ -5131,6 +5252,8 @@ + edge_iterator ei; + bitmap_head bb_flags; + ++ prologue_seq = NULL_RTX; ++ + df_analyze (); + + rtl_profile_for_bb (ENTRY_BLOCK_PTR); +@@ -5215,6 +5338,8 @@ + bitmap_head bb_antic_flags; + bitmap_head bb_on_list; + ++ prepare_shrink_wrap (entry_edge->dest); ++ + bitmap_initialize (&bb_antic_flags, &bitmap_default_obstack); + bitmap_initialize (&bb_on_list, &bitmap_default_obstack); + +--- a/src/gcc/opts.c ++++ b/src/gcc/opts.c +@@ -877,6 +877,7 @@ + flag_tree_copy_prop = opt1; + flag_tree_sink = opt1; + flag_tree_ch = opt1; ++ flag_shrink_wrap = opt1; + + /* -O2 optimizations. */ + opt2 = (optimize >= 2); +@@ -909,7 +910,6 @@ + flag_ipa_cp = opt2; + flag_ipa_sra = opt2; + flag_ee = opt2; +- flag_shrink_wrap = opt2; + + /* Track fields in field-sensitive alias analysis. */ + set_param_value ("max-fields-for-field-sensitive", +--- a/src/gcc/testsuite/gcc.target/arm/pr47688.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr47688.c +@@ -0,0 +1,26 @@ ++/* { dg-options "-mthumb -O2" } */ ++/* { dg-require-effective-target arm_thumb2_ok } */ ++/* { dg-final { scan-assembler-not "-32768" } } */ ++ ++typedef union ++{ ++ unsigned long int u_32_value; ++ struct ++ { ++ unsigned short int u_16_value_0; ++ unsigned short int u_16_value_1; ++ } u_16_values; ++} my_union; ++ ++ ++unsigned long int Test(const unsigned short int wXe) ++{ ++ my_union dwCalcVal; ++ ++ dwCalcVal.u_16_values.u_16_value_0=wXe; ++ dwCalcVal.u_16_values.u_16_value_1=0x8000u; ++ ++ dwCalcVal.u_32_value /=3; ++ ++ return (dwCalcVal.u_32_value); ++} --- gcc-4.5-4.5.2.orig/debian/patches/libstdc++-pic.diff +++ gcc-4.5-4.5.2/debian/patches/libstdc++-pic.diff @@ -0,0 +1,67 @@ +# DP: Build and install libstdc++_pic.a library. + +--- + libstdc++-v3/src/Makefile.am | 4 ++++ + libstdc++-v3/src/Makefile.in | 8 +++++++- + 2 files changed, 11 insertions(+), 1 deletions(-) + +--- a/src/libstdc++-v3/src/Makefile.am.orig 2009-11-30 15:46:45.000000000 +0000 ++++ b/src/libstdc++-v3/src/Makefile.am 2009-12-20 11:23:26.000000000 +0000 +@@ -364,6 +364,11 @@ + $(CXX) $(OPT_LDFLAGS) $(SECTION_LDFLAGS) $(AM_CXXFLAGS) $(LTLDFLAGS) -o $@ + + ++install-exec-local: ++ $(AR) cru libstdc++_pic.a .libs/*.o $(top_builddir)/libsupc++/*.o || touch libstdc++_pic.a ++ $(MKDIR_P) $(DESTDIR)$(toolexeclibdir) ++ $(INSTALL_DATA) libstdc++_pic.a $(DESTDIR)$(toolexeclibdir) ++ + # Added bits to build debug library. + if GLIBCXX_BUILD_DEBUG + all-local: build_debug +--- a/src/libstdc++-v3/src/Makefile.in.orig 2009-12-07 16:14:22.000000000 +0000 ++++ b/src/libstdc++-v3/src/Makefile.in 2009-12-20 11:26:04.000000000 +0000 +@@ -731,7 +731,7 @@ + + install-dvi-am: + +-install-exec-am: install-toolexeclibLTLIBRARIES ++install-exec-am: install-exec-local install-toolexeclibLTLIBRARIES + + install-html: install-html-am + +@@ -780,14 +780,14 @@ + distclean-libtool distclean-tags distdir dvi dvi-am html \ + html-am info info-am install install-am install-data \ + install-data-am install-data-local install-dvi install-dvi-am \ +- install-exec install-exec-am install-html install-html-am \ +- install-info install-info-am install-man install-pdf \ +- install-pdf-am install-ps install-ps-am install-strip \ +- install-toolexeclibLTLIBRARIES installcheck installcheck-am \ +- installdirs maintainer-clean maintainer-clean-generic \ +- mostlyclean mostlyclean-compile mostlyclean-generic \ +- mostlyclean-libtool pdf pdf-am ps ps-am tags uninstall \ +- uninstall-am uninstall-toolexeclibLTLIBRARIES ++ install-exec install-exec-am install-exec-local install-html \ ++ install-html-am install-info install-info-am install-man \ ++ install-pdf install-pdf-am install-ps install-ps-am \ ++ install-strip install-toolexeclibLTLIBRARIES installcheck \ ++ installcheck-am installdirs maintainer-clean \ ++ maintainer-clean-generic mostlyclean mostlyclean-compile \ ++ mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ ++ tags uninstall uninstall-am uninstall-toolexeclibLTLIBRARIES + + + # Symbol versioning for shared libraries. +@@ -947,6 +947,11 @@ + @GLIBCXX_LDBL_COMPAT_TRUE@compatibility-ldbl.o: compatibility-ldbl.cc + @GLIBCXX_LDBL_COMPAT_TRUE@ $(CXXCOMPILE) -mlong-double-64 -c $< + ++install-exec-local: ++ $(AR) cru libstdc++_pic.a .libs/*.o $(top_builddir)/libsupc++/*.o || touch libstdc++_pic.a ++ $(MKDIR_P) $(DESTDIR)$(toolexeclibdir) ++ $(INSTALL_DATA) libstdc++_pic.a $(DESTDIR)$(toolexeclibdir) ++ + # Added bits to build debug library. + @GLIBCXX_BUILD_DEBUG_TRUE@all-local: build_debug + @GLIBCXX_BUILD_DEBUG_TRUE@install-data-local: install_debug --- gcc-4.5-4.5.2.orig/debian/patches/libjava-armel-unwind.diff +++ gcc-4.5-4.5.2/debian/patches/libjava-armel-unwind.diff @@ -0,0 +1,19 @@ +# DP: On armel, apply kludge to fix unwinder infinitely looping 'til it runs out +# DP: of memory (http://gcc.gnu.org/ml/java/2008-06/msg00010.html). + +--- + libjava/stacktrace.cc | 3 +++ + 1 files changed, 3 insertions(+), 0 deletions(-) + +--- a/src/libjava/stacktrace.cc ++++ b/src/libjava/stacktrace.cc +@@ -115,6 +115,9 @@ _Jv_StackTrace::UnwindTraceFn (struct _Unwind_Context *context, void *state_ptr) + // Check if the trace buffer needs to be extended. + if (pos == state->length) + { ++ // http://gcc.gnu.org/ml/java/2008-06/msg00010.html ++ return _URC_END_OF_STACK; ++ + int newLength = state->length * 2; + void *newFrames = _Jv_AllocBytes (newLength * sizeof(_Jv_StackFrame)); + memcpy (newFrames, state->frames, state->length * sizeof(_Jv_StackFrame)); --- gcc-4.5-4.5.2.orig/debian/patches/gold-and-ld.diff +++ gcc-4.5-4.5.2/debian/patches/gold-and-ld.diff @@ -0,0 +1,615 @@ +# DP: Enable both gold and ld in a single toolchain. +# DP: New option -fuse-ld=ld.bfd, -fuse-ld=gold. + +Index: gcc/doc/invoke.texi +=================================================================== +--- a/src/gcc/doc/invoke.texi (revision ++++ b/src/gcc/doc/invoke.texi (working +@@ -390,7 +390,7 @@ + -funit-at-a-time -funroll-all-loops -funroll-loops @gol + -funsafe-loop-optimizations -funsafe-math-optimizations -funswitch-loops @gol + -fvariable-expansion-in-unroller -fvect-cost-model -fvpt -fweb @gol +--fwhole-program -fwhopr -fwpa -fuse-linker-plugin @gol ++-fwhole-program -fwhopr -fwpa -fuse-linker-plugin -fuse-ld @gol + --param @var{name}=@var{value} + -O -O0 -O1 -O2 -O3 -Os} + +@@ -7410,6 +7410,16 @@ + + Disabled by default. + ++@item -fuse-ld=gold ++Use the @command{gold} linker instead of the default linker. ++This option is only necessary if GCC has been configured with ++@option{--enable-gold=both} or @option{--enable-gold=both/ld}. ++ ++@item -fuse-ld=bfd ++Use the @command{ld.bfd} linker instead of the default linker. ++This option is only necessary if GCC has been configured with ++@option{--enable-gold=both/gold}. ++ + @item -fcprop-registers + @opindex fcprop-registers + After register allocation and post-register allocation instruction splitting, +Index: gcc/gcc.c +=================================================================== +--- a/src/gcc/gcc.c (revision ++++ b/src/gcc/gcc.c (working +@@ -790,6 +790,9 @@ + %{v:-plugin-opt=-v} \ + } \ + %{flto} %{fwhopr} %l " LINK_PIE_SPEC \ ++ "%{fuse-ld=gold:%{fuse-ld=bfd:%e-fuse-ld=gold and -fuse-ld=bfd may not be used together}} \ ++ %{fuse-ld=gold:-use-gold} \ ++ %{fuse-ld=bfd:-use-ld}" \ + "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\ + %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\ + %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\ +Index: gcc/opts.c +=================================================================== +--- a/src/gcc/opts.c (revision ++++ b/src/gcc/opts.c (working +@@ -2136,8 +2136,9 @@ + /* These are no-ops, preserved for backward compatibility. */ + break; + ++ case OPT_fuse_ld_: + case OPT_fuse_linker_plugin: +- /* No-op. Used by the driver and passed to us because it starts with f.*/ ++ /* No-op. Used by the driver and passed to us because it starts with f. */ + break; + + default: +Index: gcc/configure.ac +=================================================================== +--- a/src/gcc/configure.ac (revision ++++ b/src/gcc/configure.ac (working +@@ -1923,6 +1923,17 @@ + AC_PATH_PROG(gcc_cv_ld, $LD_FOR_TARGET) + fi]) + ++gcc_cv_ld_gold_srcdir=`echo $srcdir | sed -e 's,/gcc$,,'`/gold ++ ++AS_VAR_SET_IF(gcc_cv_gold,, [ ++if test -f $gcc_cv_ld_gold_srcdir/configure.ac \ ++ && test -f ../gold/Makefile \ ++ && test x$build = x$host; then ++ gcc_cv_gold=../gold/ld-new$build_exeext ++else ++ gcc_cv_gold='' ++fi]) ++ + ORIGINAL_PLUGIN_LD_FOR_TARGET=$gcc_cv_ld + PLUGIN_LD=`basename $gcc_cv_ld` + AC_ARG_WITH(plugin-ld, +@@ -1941,6 +1952,9 @@ + *) AC_CONFIG_FILES(collect-ld:exec-tool.in, [chmod +x collect-ld]) ;; + esac + ++ORIGINAL_GOLD_FOR_TARGET=$gcc_cv_gold ++AC_SUBST(ORIGINAL_GOLD_FOR_TARGET) ++ + AC_MSG_CHECKING(what linker to use) + if test "$gcc_cv_ld" = ../ld/ld-new$build_exeext; then + # Single tree build which includes ld. We want to prefer it +Index: gcc/exec-tool.in +=================================================================== +--- a/src/gcc/exec-tool.in (revision ++++ b/src/gcc/exec-tool.in (working +@@ -1,6 +1,6 @@ + #! /bin/sh + +-# Copyright (C) 2007, 2008 Free Software Foundation, Inc. ++# Copyright (C) 2007, 2008, 2010 Free Software Foundation, Inc. + # This file is part of GCC. + + # GCC is free software; you can redistribute it and/or modify +@@ -21,11 +21,13 @@ + + ORIGINAL_AS_FOR_TARGET="@ORIGINAL_AS_FOR_TARGET@" + ORIGINAL_LD_FOR_TARGET="@ORIGINAL_LD_FOR_TARGET@" ++ORIGINAL_GOLD_FOR_TARGET="@ORIGINAL_GOLD_FOR_TARGET@" + ORIGINAL_PLUGIN_LD_FOR_TARGET="@ORIGINAL_PLUGIN_LD_FOR_TARGET@" + ORIGINAL_NM_FOR_TARGET="@ORIGINAL_NM_FOR_TARGET@" + exeext=@host_exeext@ + fast_install=@enable_fast_install@ + objdir=@objdir@ ++version="1.1" + + invoked=`basename "$0"` + case "$invoked" in +@@ -34,54 +36,110 @@ + prog=as-new$exeext + dir=gas + ;; +- collect-ld) +- # when using a linker plugin, gcc will always pass '-plugin' as the +- # first option to the linker. +- if test x"$1" = "x-plugin"; then +- original=$ORIGINAL_PLUGIN_LD_FOR_TARGET +- else +- original=$ORIGINAL_LD_FOR_TARGET +- fi +- prog=ld-new$exeext +- dir=ld +- ;; + nm) + original=$ORIGINAL_NM_FOR_TARGET + prog=nm-new$exeext + dir=binutils + ;; ++ collect-ld) ++ prog=ld-new$exeext ++ # Look for the a command line option ++ # specifying the linker to be used. ++ case " $* " in ++ *\ -use-gold\ *) ++ original=$ORIGINAL_GOLD_FOR_TARGET ++ dir=gold ++ ;; ++ *\ -use-ld\ * | *\ -use-ld.bfd\ *) ++ original=$ORIGINAL_LD_FOR_TARGET ++ dir=ld ++ ;; ++ *\ -plugin\ *) ++ original=$ORIGINAL_PLUGIN_LD_FOR_TARGET ++ dir=ld ++ ;; ++ *) ++ original=$ORIGINAL_LD_FOR_TARGET ++ dir=ld ++ ;; ++ esac ++ ++ # If the selected linker has not been configured then ++ # try using the others, in the order PLUGIN-LD, LD, GOLD. ++ if test x"$original" = x; then ++ if test x"$ORIGINAL_PLUGIN_LD_FOR_TARGET" != x; then ++ original=$ORIGINAL_PLUGIN_LD_FOR_TARGET ++ dir=ld ++ elif test x"$ORIGINAL_LD_FOR_TARGET" != x; then ++ original=$ORIGINAL_LD_FOR_TARGET ++ dir=ld ++ elif test x"$ORIGINAL_GOLD_FOR_TARGET" != x; then ++ original=$ORIGINAL_GOLD_FOR_TARGET ++ dir=gold ++ # Otherwise do nothing - the case statement below ++ # will issue an error message for us. ++ fi ++ fi ++ ;; + esac + + case "$original" in + ../*) +- # compute absolute path of the location of this script ++ # Compute absolute path to the location of this script. + tdir=`dirname "$0"` + scriptdir=`cd "$tdir" && pwd` + + if test -x $scriptdir/../$dir/$prog; then +- test "$fast_install" = yes || exec $scriptdir/../$dir/$prog ${1+"$@"} ++ if test "$fast_install" = yes; then ++ # If libtool did everything it needs to do, there's a fast path. ++ lt_prog=$scriptdir/../$dir/$objdir/lt-$prog + +- # if libtool did everything it needs to do, there's a fast path +- lt_prog=$scriptdir/../$dir/$objdir/lt-$prog +- test -x $lt_prog && exec $lt_prog ${1+"$@"} +- +- # libtool has not relinked ld-new yet, but we cannot just use the +- # previous stage (because then the relinking would just never happen!). +- # So we take extra care to use prev-ld/ld-new *on recursive calls*. +- test x"$LT_RCU" = x"1" && exec $scriptdir/../prev-$dir/$prog ${1+"$@"} +- +- LT_RCU=1; export LT_RCU +- $scriptdir/../$dir/$prog ${1+"$@"} +- result=$? +- exit $result +- ++ if test -x $lt_prog; then ++ original=$lt_prog ++ else ++ # Libtool has not relinked ld-new yet, but we cannot just use the ++ # previous stage (because then the relinking would just never happen!). ++ # So we take extra care to use prev-ld/ld-new *on recursive calls*. ++ if test x"$LT_RCU" = x"1"; then ++ original=$scriptdir/../prev-$dir/$prog ++ else ++ LT_RCU=1; export LT_RCU ++ case " $* " in ++ *\ -v\ *) ++ echo "$invoked $version" ++ echo $scriptdir/../$dir/$prog $* ++ ;; ++ esac ++ $scriptdir/../$dir/$prog ${1+"$@"} ++ result=$? ++ exit $result ++ fi ++ fi ++ else ++ original=$scriptdir/../$dir/$prog ++ fi + else +- exec $scriptdir/../prev-$dir/$prog ${1+"$@"} ++ original=$scriptdir/../prev-$dir/$prog + fi + ;; +- *) +- exec "$original" ${1+"$@"} ++ "") ++ echo "$invoked: executable not configured" ++ exit 1 + ;; + esac + ++# If -v has been used then display our version number ++# and then echo the command we are about to invoke. ++case " $* " in ++ *\ -v\ *) ++ echo "$invoked $version" ++ echo $original $* ++ ;; ++esac + ++if test -x $original; then ++ exec "$original" ${1+"$@"} ++else ++ echo "$invoked: unable to locate executable: $original" ++ exit 1 ++fi +Index: gcc/common.opt +=================================================================== +--- a/src/gcc/common.opt (revision ++++ b/src/gcc/common.opt (working +@@ -1401,6 +1401,9 @@ + Common Report Var(flag_unwind_tables) Optimization + Just generate unwind tables for exception handling + ++fuse-ld= ++Common Joined Undocumented ++ + fuse-linker-plugin + Common Undocumented + +Index: gcc/collect2.c +=================================================================== +--- a/src/gcc/collect2.c (revision 157602) ++++ b/src/gcc/collect2.c (working copy) +@@ -1110,17 +1110,19 @@ + int + main (int argc, char **argv) + { +- static const char *const ld_suffix = "ld"; +- static const char *const plugin_ld_suffix = PLUGIN_LD; +- static const char *const real_ld_suffix = "real-ld"; ++ static const char *const ld_suffix = "ld"; ++ static const char *const gold_suffix = "gold"; ++ static const char *const bfd_ld_suffix = "ld.bfd"; ++ static const char *const plugin_ld_suffix = PLUGIN_LD; ++ static const char *const real_ld_suffix = "real-ld"; + static const char *const collect_ld_suffix = "collect-ld"; +- static const char *const nm_suffix = "nm"; +- static const char *const gnm_suffix = "gnm"; ++ static const char *const nm_suffix = "nm"; ++ static const char *const gnm_suffix = "gnm"; + #ifdef LDD_SUFFIX +- static const char *const ldd_suffix = LDD_SUFFIX; ++ static const char *const ldd_suffix = LDD_SUFFIX; + #endif +- static const char *const strip_suffix = "strip"; +- static const char *const gstrip_suffix = "gstrip"; ++ static const char *const strip_suffix = "strip"; ++ static const char *const gstrip_suffix = "gstrip"; + + #ifdef CROSS_DIRECTORY_STRUCTURE + /* If we look for a program in the compiler directories, we just use +@@ -1130,6 +1132,10 @@ + + const char *const full_ld_suffix = + concat(target_machine, "-", ld_suffix, NULL); ++ const char *const full_gold_suffix = ++ concat (target_machine, "-", gold_suffix, NULL); ++ const char *const full_bfd_ld_suffix = ++ concat (target_machine, "-", bfd_ld_suffix, NULL); + const char *const full_plugin_ld_suffix = + concat(target_machine, "-", plugin_ld_suffix, NULL); + const char *const full_nm_suffix = +@@ -1145,15 +1151,17 @@ + const char *const full_gstrip_suffix = + concat (target_machine, "-", gstrip_suffix, NULL); + #else +- const char *const full_ld_suffix = ld_suffix; ++ const char *const full_ld_suffix = ld_suffix; ++ const char *const full_gold_suffix = gold_suffix; ++ const char *const full_bfd_ld_suffix = bfd_ld_suffix; + const char *const full_plugin_ld_suffix = plugin_ld_suffix; +- const char *const full_nm_suffix = nm_suffix; +- const char *const full_gnm_suffix = gnm_suffix; ++ const char *const full_nm_suffix = nm_suffix; ++ const char *const full_gnm_suffix = gnm_suffix; + #ifdef LDD_SUFFIX +- const char *const full_ldd_suffix = ldd_suffix; ++ const char *const full_ldd_suffix = ldd_suffix; + #endif +- const char *const full_strip_suffix = strip_suffix; +- const char *const full_gstrip_suffix = gstrip_suffix; ++ const char *const full_strip_suffix = strip_suffix; ++ const char *const full_gstrip_suffix = gstrip_suffix; + #endif /* CROSS_DIRECTORY_STRUCTURE */ + + const char *arg; +@@ -1167,7 +1175,13 @@ + const char **c_ptr; + char **ld1_argv; + const char **ld1; +- bool use_plugin = false; ++ enum linker_select ++ { ++ DFLT_LINKER, ++ PLUGIN_LINKER, ++ GOLD_LINKER, ++ BFD_LINKER ++ } selected_linker = DFLT_LINKER; + + /* The kinds of symbols we will have to consider when scanning the + outcome of a first pass link. This is ALL to start with, then might +@@ -1184,7 +1198,6 @@ + int first_file; + int num_c_args; + char **old_argv; +- + bool use_verbose = false; + + old_argv = argv; +@@ -1240,22 +1253,29 @@ + { + if (! strcmp (argv[i], "-debug")) + debug = 1; +- else if (! strcmp (argv[i], "-flto") && ! use_plugin) ++ else if (! strcmp (argv[i], "-flto") ++ && selected_linker != PLUGIN_LINKER) + { + use_verbose = true; + lto_mode = LTO_MODE_LTO; + } +- else if (! strcmp (argv[i], "-fwhopr") && ! use_plugin) ++ else if (! strcmp (argv[i], "-fwhopr") ++ && selected_linker != PLUGIN_LINKER) + { + use_verbose = true; + lto_mode = LTO_MODE_WHOPR; + } + else if (! strcmp (argv[i], "-plugin")) + { +- use_plugin = true; ++ selected_linker = PLUGIN_LINKER; + use_verbose = true; + lto_mode = LTO_MODE_NONE; + } ++ else if (! strcmp (argv[i], "-use-gold")) ++ selected_linker = GOLD_LINKER; ++ else if (! strcmp (argv[i], "-use-ld")) ++ selected_linker = BFD_LINKER; ++ + #ifdef COLLECT_EXPORT_LIST + /* since -brtl, -bexport, -b64 are not position dependent + also check for them here */ +@@ -1335,36 +1355,109 @@ + /* Try to discover a valid linker/nm/strip to use. */ + + /* Maybe we know the right file to use (if not cross). */ +- ld_file_name = 0; ++ ld_file_name = NULL; + #ifdef DEFAULT_LINKER + if (access (DEFAULT_LINKER, X_OK) == 0) + ld_file_name = DEFAULT_LINKER; +- if (ld_file_name == 0) ++ if (ld_file_name == NULL) + #endif + #ifdef REAL_LD_FILE_NAME + ld_file_name = find_a_file (&path, REAL_LD_FILE_NAME); +- if (ld_file_name == 0) ++ if (ld_file_name == NULL) + #endif + /* Search the (target-specific) compiler dirs for ld'. */ + ld_file_name = find_a_file (&cpath, real_ld_suffix); + /* Likewise for `collect-ld'. */ +- if (ld_file_name == 0) ++ if (ld_file_name == NULL) + ld_file_name = find_a_file (&cpath, collect_ld_suffix); + /* Search the compiler directories for `ld'. We have protection against + recursive calls in find_a_file. */ +- if (ld_file_name == 0) +- ld_file_name = find_a_file (&cpath, +- use_plugin +- ? plugin_ld_suffix +- : ld_suffix); ++ if (ld_file_name == NULL) ++ switch (selected_linker) ++ { ++ default: ++ case DFLT_LINKER: ++ ld_file_name = find_a_file (&cpath, ld_suffix); ++ break; ++ case PLUGIN_LINKER: ++ ld_file_name = find_a_file (&cpath, plugin_ld_suffix); ++ break; ++ case GOLD_LINKER: ++ ld_file_name = find_a_file (&cpath, gold_suffix); ++ break; ++ case BFD_LINKER: ++ ld_file_name = find_a_file (&cpath, bfd_ld_suffix); ++ break; ++ } + /* Search the ordinary system bin directories + for `ld' (if native linking) or `TARGET-ld' (if cross). */ +- if (ld_file_name == 0) +- ld_file_name = find_a_file (&path, +- use_plugin +- ? full_plugin_ld_suffix +- : full_ld_suffix); ++ if (ld_file_name == NULL) ++ switch (selected_linker) ++ { ++ default: ++ case DFLT_LINKER: ++ ld_file_name = find_a_file (&path, full_ld_suffix); ++ break; ++ case PLUGIN_LINKER: ++ ld_file_name = find_a_file (&path, full_plugin_ld_suffix); ++ break; ++ case GOLD_LINKER: ++ ld_file_name = find_a_file (&path, full_gold_suffix); ++ break; ++ case BFD_LINKER: ++ ld_file_name = find_a_file (&path, full_bfd_ld_suffix); ++ break; ++ } ++ /* If we failed to find a plugin-capable linker, try the ordinary one. */ ++ if (ld_file_name == NULL && selected_linker == PLUGIN_LINKER) ++ ld_file_name = find_a_file (&cpath, ld_suffix); + ++ if ((vflag || debug) && ld_file_name == NULL) ++ { ++ struct prefix_list * p; ++ const char * s; ++ ++ notice ("collect2: warning: unable to find linker.\n"); ++ ++#ifdef DEFAULT_LINKER ++ notice (" Searched for this absolute executable:\n"); ++ notice (" %s\n", DEFAULT_LINKER); ++#endif ++ ++ notice (" Searched in these paths:\n"); ++ for (p = cpath.plist; p != NULL; p = p->next) ++ notice (" %s\n", p->prefix); ++ notice (" For these executables:\n"); ++ notice (" %s\n", real_ld_suffix); ++ notice (" %s\n", collect_ld_suffix); ++ switch (selected_linker) ++ { ++ default: ++ case DFLT_LINKER: s = ld_suffix; break; ++ case PLUGIN_LINKER: s = plugin_ld_suffix; break; ++ case GOLD_LINKER: s = gold_suffix; break; ++ case BFD_LINKER: s = bfd_ld_suffix; break; ++ } ++ notice (" %s\n", s); ++ ++ notice (" And searched in these paths:\n"); ++ for (p = path.plist; p != NULL; p = p->next) ++ notice (" %s\n", p->prefix); ++ notice (" For these executables:\n"); ++#ifdef REAL_LD_FILE_NAME ++ notice (" %s\n", REAL_LD_FILE_NAME); ++#endif ++ switch (selected_linker) ++ { ++ default: ++ case DFLT_LINKER: s = full_ld_suffix; break; ++ case PLUGIN_LINKER: s = full_plugin_ld_suffix; break; ++ case GOLD_LINKER: s = full_gold_suffix; break; ++ case BFD_LINKER: s = full_bfd_ld_suffix; break; ++ } ++ notice (" %s\n", s); ++ } ++ + #ifdef REAL_NM_FILE_NAME + nm_file_name = find_a_file (&path, REAL_NM_FILE_NAME); + if (nm_file_name == 0) +Index: configure.ac +=================================================================== +--- a/src/configure.ac (revision ++++ b/src/configure.ac (working +@@ -174,7 +174,7 @@ + # know that we are building the simulator. + # binutils, gas and ld appear in that order because it makes sense to run + # "make check" in that particular order. +-# If --enable-gold is used, "gold" will replace "ld". ++# If --enable-gold is used, "gold" may replace "ld". + host_tools="texinfo byacc flex bison binutils gas ld fixincludes gcc cgen sid sim gdb make patch prms send-pr gprof etc expect dejagnu ash bash bzip2 m4 autoconf automake libtool diff rcs fileutils shellutils time textutils wdiff find uudecode hello tar gzip indent recode release sed utils guile perl gawk findutils gettext zip fastjar gnattools" + + # libgcj represents the runtime libraries only used by gcj. +@@ -315,37 +315,57 @@ + esac + + # Handle --enable-gold. ++# --enable-gold Build only gold ++# --disable-gold [default] Build only ld ++# --enable-gold=both Build both gold and ld, ld is default ++# --enable-gold=both/ld Same ++# --enable-gold=both/gold Build both gold and ld, gold is default, ld is renamed ld.bfd + + AC_ARG_ENABLE(gold, +-[ --enable-gold use gold instead of ld], ++[ --enable-gold[[=ARG]] build gold [[ARG={both}[[/{gold,ld}]]]]], + ENABLE_GOLD=$enableval, + ENABLE_GOLD=no) +-if test "${ENABLE_GOLD}" = "yes"; then +- # Check for ELF target. +- is_elf=no +- case "${target}" in +- *-*-elf* | *-*-sysv4* | *-*-unixware* | *-*-eabi* | hppa*64*-*-hpux* \ +- | *-*-linux* | frv-*-uclinux* | *-*-irix5* | *-*-irix6* \ +- | *-*-netbsd* | *-*-openbsd* | *-*-freebsd* | *-*-solaris2* | *-*-nto*) ++ case "${ENABLE_GOLD}" in ++ yes|both|both/gold|both/ld) ++ # Check for ELF target. ++ is_elf=no ++ case "${target}" in ++ *-*-elf* | *-*-sysv4* | *-*-unixware* | *-*-eabi* | hppa*64*-*-hpux* \ ++ | *-*-linux* | frv-*-uclinux* | *-*-irix5* | *-*-irix6* \ ++ | *-*-netbsd* | *-*-openbsd* | *-*-freebsd* | *-*-solaris2* | *-*-nto*) ++ case "${target}" in ++ *-*-linux*aout* | *-*-linux*oldld*) ++ ;; ++ *) ++ is_elf=yes ++ ;; ++ esac ++ esac ++ ++ if test "$is_elf" = "yes"; then ++ # Check for target supported by gold. + case "${target}" in +- *-*-linux*aout* | *-*-linux*oldld*) ++ i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-*) ++ case "${ENABLE_GOLD}" in ++ both*) ++ configdirs="$configdirs gold" ++ ;; ++ *) ++ configdirs="`echo " ${configdirs} " | sed -e 's/ ld / gold /'`" ++ ;; ++ esac ++ ENABLE_GOLD=yes + ;; +- *) +- is_elf=yes +- ;; + esac ++ fi ++ ;; ++ no) ++ ;; ++ *) ++ AC_MSG_ERROR([invalid --enable-gold argument]) ++ ;; + esac + +- if test "$is_elf" = "yes"; then +- # Check for target supported by gold. +- case "${target}" in +- i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-*) +- configdirs="`echo " ${configdirs} " | sed -e 's/ ld / gold /'`" +- ;; +- esac +- fi +-fi +- + # Configure extra directories which are host specific + + case "${host}" in --- gcc-4.5-4.5.2.orig/debian/patches/gcc-linaro.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-linaro.diff @@ -0,0 +1,92822 @@ +# DP: Changes for the Linaro 4.5-2011.03-0 release. + +--- a/src/ChangeLog ++++ b/src/ChangeLog +@@ -1,3 +1,11 @@ ++2011-01-25 Richard Guenther ++ ++ Backport from mainline ++ 2010-05-05 Sebastian Pop ++ ++ * configure.ac: Allow all the versions greater than 0.10 of PPL. ++ * configure: Regenerated. ++ + 2010-12-16 Release Manager + + * GCC 4.5.2 released. +--- a/src/ChangeLog.linaro ++++ b/src/ChangeLog.linaro +@@ -0,0 +1,4279 @@ ++2011-02-11 Richard Sandiford ++ ++ gcc/ ++ * cse.c (count_reg_usage): Check side_effects_p. Remove the ++ separate check for volatile asms. ++ ++ gcc/testsuite/ ++ * gcc.dg/torture/volatile-pic-1.c: New test. ++ ++2011-02-02 Richard Sandiford ++ ++ gcc/ ++ Backport from mainline: ++ ++ 2011-01-23 Bernd Schmidt ++ Richard Sandiford ++ ++ PR rtl-optimization/47166 ++ * reload1.c (emit_reload_insns): Disable the spill_reg_store ++ mechanism for PRE_MODIFY and POST_MODIFY. ++ (inc_for_reload): For PRE_MODIFY, return the insn that sets the ++ reloadreg. ++ ++ gcc/testsuite/ ++ * gcc.c-torture/execute/postmod-1.c: New test. ++ ++2011-02-02 Richard Sandiford ++ ++ gcc/testsuite/ ++ PR target/47553 ++ * gcc.target/arm/neon-vld-1.c: New test. ++ gcc/ ++ PR target/47553 ++ * config/arm/predicates.md (neon_lane_number): Accept 0..15. ++ ++2011-02-02 Richard Sandiford ++ ++ ++ gcc/ ++ PR target/47551 ++ * config/arm/arm.c (coproc_secondary_reload_class): Handle ++ structure modes. Don't check neon_vector_mem_operand for ++ vector or structure modes. ++ ++ gcc/testsuite/ ++ PR target/47551 ++ * gcc.target/arm/neon-modes-2.c: New test. ++ ++2011-02-24 Chung-Lin Tang ++ ++ Backport from FSF mainline: ++ ++ 2010-08-10 Bernd Schmidt ++ ++ PR bootstrap/45177 ++ * config/arm/arm.c (multiple_operation_profitable_p): Move xscale ++ test here from arm_gen_load_multiple_1. ++ (arm_gen_load_multiple_1, arm_gen_store_multiple_1): Use ++ multiple_operation_profitable_p. ++ ++2011-01-11 Ramana Radhakrishnan ++ ++ * config/arm/t-arm: Fix up last commit. ++ ++2011-01-11 Ramana Radhakrishnan ++ ++ * config/arm/t-arm: Update MD_INCLUDES to include ++ all the files correctly. ++ * config/arm/arm.md: Update comments. ++ ++2011-02-28 Andrew Stubbs ++ ++ LP:709453 ++ ++ Revert: ++ ++ 2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ Jie Zhang ++ ++ Issue #7122 ++ ++ gcc/ ++ * config/arm/vfp.md (movdf_vfp): Add load double 0.0 case. ++ (thumb2_movdf_vfp): Likewise. Require that one of the operands be a ++ register. ++ * config/arm/constraints.md (D0): New constraint. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/neon-load-df0.c: New test. ++ ++2011-02-22 Andrew Stubbs ++ ++ Merge from FSF 4.5 branch r170352 (pre 4.5.3). ++ ++2011-02-08 Andrew Stubbs ++ ++ Backport from FSF mainline: ++ ++ 2010-06-30 H.J. Lu ++ ++ PR target/44721 ++ * config/i386/i386.md (peephole2 for arithmetic ops with memory): ++ Fix last commit. ++ ++ 2010-06-30 Richard Guenther ++ ++ PR target/44722 ++ * config/i386/i386.md (peephole2 for fix:SSEMODEI24): Guard ++ against oscillation with reverse peephole2. ++ ++ 2010-07-01 Bernd Schmidt ++ ++ PR target/44727 ++ * config/i386/i386.md (peephole2 for arithmetic ops with memory): ++ Make sure operand 0 dies. ++ ++2010-12-03 Yao Qi ++ ++ * config/arm/arm-ldmstm.ml: Rewrite ldm/stm RTL patterns to fix ++ regressions. ++ * config/arm/ldmstm.md: Regenreate. ++ ++2010-12-03 Yao Qi ++ ++ Backport from FSF mainline: ++ ++ 2010-08-02 Bernd Schmidt ++ ++ PR target/40457 ++ * config/arm/arm.h (arm_regs_in_sequence): Declare. ++ * config/arm/arm-protos.h (emit_ldm_seq, emit_stm_seq, ++ load_multiple_sequence, store_multiple_sequence): Delete ++ declarations. ++ (arm_gen_load_multiple, arm_gen_store_multiple): Adjust ++ declarations. ++ * config/arm/ldmstm.md: New file. ++ * config/arm/arm.c (arm_regs_in_sequence): New array. ++ (load_multiple_sequence): Now static. New args SAVED_ORDER, ++ CHECK_REGS. All callers changed. ++ If SAVED_ORDER is nonnull, copy the computed order into it. ++ If CHECK_REGS is false, don't sort REGS. Handle Thumb mode. ++ (store_multiple_sequence): Now static. New args NOPS_TOTAL, ++ SAVED_ORDER, REG_RTXS and CHECK_REGS. All callers changed. ++ If SAVED_ORDER is nonnull, copy the computed order into it. ++ If CHECK_REGS is false, don't sort REGS. Set up REG_RTXS just ++ like REGS. Handle Thumb mode. ++ (arm_gen_load_multiple_1): New function, broken out of ++ arm_gen_load_multiple. ++ (arm_gen_store_multiple_1): New function, broken out of ++ arm_gen_store_multiple. ++ (arm_gen_multiple_op): New function, with code from ++ arm_gen_load_multiple and arm_gen_store_multiple moved here. ++ (arm_gen_load_multiple, arm_gen_store_multiple): Now just ++ wrappers around arm_gen_multiple_op. Remove argument UP, all callers ++ changed. ++ (gen_ldm_seq, gen_stm_seq, gen_const_stm_seq): New functions. ++ * config/arm/predicates.md (commutative_binary_operator): New. ++ (load_multiple_operation, store_multiple_operation): Handle more ++ variants of these patterns with different starting offsets. Handle ++ Thumb-1. ++ * config/arm/arm.md: Include "ldmstm.md". ++ (ldmsi_postinc4, ldmsi_postinc4_thumb1, ldmsi_postinc3, ldmsi_postinc2, ++ ldmsi4, ldmsi3, ldmsi2, stmsi_postinc4, stmsi_postinc4_thumb1, ++ stmsi_postinc3, stmsi_postinc2, stmsi4, stmsi3, stmsi2 and related ++ peepholes): Delete. ++ * config/arm/ldmstm.md: New file. ++ * config/arm/arm-ldmstm.ml: New file. ++ ++ * config/arm/arm.c (arm_rtx_costs_1): Remove second clause from the ++ if statement which adds extra costs to frame-related expressions. ++ ++ 2010-05-06 Bernd Schmidt ++ ++ * config/arm/arm.h (MAX_LDM_STM_OPS): New macro. ++ * config/arm/arm.c (multiple_operation_profitable_p, ++ compute_offset_order): New static functions. ++ (load_multiple_sequence, store_multiple_sequence): Use them. ++ Replace constant 4 with MAX_LDM_STM_OPS. Compute order[0] from ++ memory offsets, not register numbers. ++ (emit_ldm_seq, emit_stm_seq): Replace constant 4 with MAX_LDM_STM_OPS. ++ ++ 2010-04-16 Bernd Schmidt ++ ++ * recog.h (struct recog_data): New field is_operator. ++ (struct insn_operand_data): New field is_operator. ++ * recog.c (extract_insn): Set recog_data.is_operator. ++ * genoutput.c (output_operand_data): Emit code to set the ++ is_operator field. ++ * reload.c (find_reloads): Use it rather than testing for an ++ empty constraint string. ++ ++2011-01-14 Bernd Schmidt ++ ++ gcc/ ++ * function.c (thread_prologue_and_epilogue_insns): Avoid uninitialized ++ variable. ++ ++2011-01-12 Bernd Schmidt ++ ++ gcc/ ++ * config/s390/s390.c (s390_emit_epilogue): Don't use gen_rtx_RETURN. ++ * config/rx/rx.c (gen_rx_rtsd_vector): Likewise. ++ * config/m68hc11/m68hc11.md (return): Likewise. ++ * config/cris/cris.c (cris_expand_return): Likewise. ++ * config/m68k/m68k.c (m68k_expand_epilogue): Likewise. ++ * config/picochip/picochip.c (picochip_expand_epilogue): Likewise. ++ * config/h8300/h8300.c (h8300_push_pop, h8300_expand_epilogue): ++ Likewise. ++ * config/v850/v850.c (expand_epilogue): Likewise. ++ * config/bfin/bfin.c (bfin_expand_call): Likewise. ++ ++2011-01-04 Catherine Moore ++ ++ gcc/ ++ * config/rs6000/rs6000.c (rs6000_make_savres_rtx): Change ++ gen_rtx_RETURN to ret_rtx. ++ (rs6000_emit_epilogue): Likewise. ++ (rs6000_output_mi_thunk): Likewise. ++ ++2011-01-03 Bernd Schmidt ++ ++ gcc/ ++ * doc/tm.texi (RETURN_ADDR_REGNUM): Document. ++ * doc/md.texi (simple_return): Document pattern. ++ (return): Add a sentence to clarify. ++ * doc/rtl.texi (simple_return): Document. ++ * doc/invoke.texi (Optimize Options): Document -fshrink-wrap. ++ * common.opt (fshrink-wrap): New. ++ * opts.c (decode_options): Set it for -O2 and above. ++ * gengenrtl.c (special_rtx): PC, CC0, RETURN and SIMPLE_RETURN ++ are special. ++ * rtl.h (ANY_RETURN_P): New macro. ++ (global_rtl_index): Add GR_RETURN and GR_SIMPLE_RETURN. ++ (ret_rtx, simple_return_rtx): New macros. ++ * genemit.c (gen_exp): RETURN and SIMPLE_RETURN have unique rtxs. ++ (gen_expand, gen_split): Use ANY_RETURN_P. ++ * rtl.c (copy_rtx): RETURN and SIMPLE_RETURN are shared. ++ * emit-rtl.c (verify_rtx_sharing): Likewise. ++ (skip_consecutive_labels): Return the argument if it is a return rtx. ++ (classify_insn): Handle both kinds of return. ++ (init_emit_regs): Create global rtl for ret_rtx and simple_return_rtx. ++ * df-scan.c (df_uses_record): Handle SIMPLE_RETURN. ++ * rtl.def (SIMPLE_RETURN): New. ++ * rtlanal.c (tablejump_p): Check JUMP_LABEL for returns. ++ * final.c (final_scan_insn): Recognize both kinds of return. ++ * reorg.c (function_return_label, function_simple_return_label): New ++ static variables. ++ (end_of_function_label): Remove. ++ (simplejump_or_return_p): New static function. ++ (find_end_label): Add a new arg, KIND. All callers changed. ++ Depending on KIND, look for a label suitable for return or ++ simple_return. ++ (make_return_insns): Make corresponding changes. ++ (get_jump_flags): Check JUMP_LABELs for returns. ++ (follow_jumps): Likewise. ++ (get_branch_condition): Check target for return patterns rather ++ than NULL. ++ (own_thread_p): Likewise for thread. ++ (steal_delay_list_from_target): Check JUMP_LABELs for returns. ++ Use simplejump_or_return_p. ++ (fill_simple_delay_slots): Likewise. ++ (optimize_skip): Likewise. ++ (fill_slots_from_thread): Likewise. ++ (relax_delay_slots): Likewise. ++ (dbr_schedule): Adjust handling of end_of_function_label for the ++ two new variables. ++ * ifcvt.c (find_if_case_1): Take care when redirecting jumps to the ++ exit block. ++ (dead_or_predicable): Change NEW_DEST arg to DEST_EDGE. All callers ++ changed. Ensure that the right label is passed to redirect_jump. ++ * jump.c (condjump_p, condjump_in_parallel_p, any_condjump_p, ++ returnjump_p): Handle SIMPLE_RETURNs. ++ (delete_related_insns): Check JUMP_LABEL for returns. ++ (redirect_target): New static function. ++ (redirect_exp_1): Use it. Handle any kind of return rtx as a label ++ rather than interpreting NULL as a return. ++ (redirect_jump_1): Assert that nlabel is not NULL. ++ (redirect_jump): Likewise. ++ (redirect_jump_2): Handle any kind of return rtx as a label rather ++ than interpreting NULL as a return. ++ * dwarf2out.c (compute_barrier_args_size_1): Check JUMP_LABEL for ++ returns. ++ * function.c (emit_return_into_block): Remove useless declaration. ++ (record_hard_reg_sets, frame_required_for_rtx, gen_return_pattern, ++ requires_stack_frame_p): New static functions. ++ (emit_return_into_block): New arg SIMPLE_P. All callers changed. ++ Generate either kind of return pattern and update the JUMP_LABEL. ++ (thread_prologue_and_epilogue_insns): Implement a form of ++ shrink-wrapping. Ensure JUMP_LABELs for return insns are set. ++ * print-rtl.c (print_rtx): Handle returns in JUMP_LABELs. ++ * cfglayout.c (fixup_reorder_chain): Ensure JUMP_LABELs for returns ++ remain correct. ++ * resource.c (find_dead_or_set_registers): Check JUMP_LABELs for ++ returns. ++ (mark_target_live_regs): Don't pass a return rtx to next_active_insn. ++ * basic-block.h (force_nonfallthru_and_redirect): Declare. ++ * sched-vis.c (print_pattern): Add case for SIMPLE_RETURN. ++ * cfgrtl.c (force_nonfallthru_and_redirect): No longer static. New arg ++ JUMP_LABEL. All callers changed. Use the label when generating ++ return insns. ++ ++ * config/i386/i386.md (returns, return_str, return_cond): New ++ code_iterator and corresponding code_attrs. ++ (return): Renamed from return and adapted. ++ (return_internal): Likewise for return_internal. ++ (return_internal_long): Likewise for return_internal_long. ++ (return_pop_internal): Likewise for return_pop_internal. ++ (return_indirect_internal): Likewise for ++ return_indirect_internal. ++ * config/i386/i386.c (ix86_expand_epilogue): Expand a simple_return as ++ the last insn. ++ (ix86_pad_returns): Handle both kinds of return rtx. ++ * config/arm/arm.c (use_simple_return_p): new function. ++ (is_jump_table): Handle returns in JUMP_LABELs. ++ (output_return_instruction): New arg SIMPLE. All callers changed. ++ Use it to determine which kind of return to generate. ++ (arm_final_prescan_insn): Handle both kinds of return. ++ * config/arm/arm.md (returns, return_str, return_simple_p, ++ return_cond): New code_iterator and corresponding code_attrs. ++ (return): Renamed from return and adapted. ++ (arm_return): Renamed from arm_return and adapted. ++ (cond_return): Renamed from cond_return and adapted. ++ (cond_return_inverted): Renamed from cond_return_inverted ++ and adapted. ++ (epilogue): Use ret_rtx instead of gen_rtx_RETURN. ++ * config/arm/thumb2.md (thumb2_return): Renamed from ++ thumb2_return and adapted. ++ * config/arm/arm.h (RETURN_ADDR_REGNUM): Define. ++ * config/arm/arm-protos.h (use_simple_return_p): Declare. ++ (output_return_instruction): Adjust declaration. ++ * config/mips/mips.c (mips_expand_epilogue): Generate a simple_return ++ as final insn. ++ * config/mips/mips.md (simple_return): New expander. ++ (*simple_return, simple_return_internal): New patterns. ++ * config/sh/sh.c (barrier_align): Handle return in a JUMP_LABEL. ++ (split_branches): Don't pass a null label to redirect_jump. ++ ++ From mainline: ++ * vec.h (FOR_EACH_VEC_ELT, FOR_EACH_VEC_ELT_REVERSE): New macros. ++ * haifa-sched.c (find_fallthru_edge_from): Rename from ++ find_fallthru_edge. All callers changed. ++ * sched-int.h (find_fallthru_edge_from): Rename declaration as well. ++ * basic-block.h (find_fallthru_edge): New inline function. ++ ++2010-02-04 Tom de Vries ++ ++ gcc/ ++ stmt.c (set_jump_prob): Fix assert condition. ++ ++2010-01-27 Tom de Vries ++ ++ gcc/ ++ stmt.c (rtx_seq_cost): Use insn_rtx_cost instead of rtx_cost. ++ ++2010-01-26 Tom de Vries ++ ++ gcc/ ++ * stmt.c (struct case_bit_test): Add rev_hi and rev_lo field. ++ * stmt.c (emit_case_bit_test_jump): New function. ++ * stmt.c (rtx_seq_cost): New function. ++ * stmt.c (choose_case_bit_test_expand_method): New function. ++ * stmt.c (set_bit): New function. ++ * stmt.c (emit_case_bit_test): Adjust comment. ++ * stmt.c (emit_case_bit_test): Set and update rev_hi and rev_lo fields. ++ * stmt.c (emit_case_bit_test): Use set_bit. ++ * stmt.c (emit_case_bit_test): Use choose_case_bit_test_expand_method. ++ * stmt.c (emit_case_bit_test): Use emit_case_bit_test_jump. ++ * testsuite/gcc.dg/switch-bittest.c: New test. ++ ++2010-01-25 Tom de Vries ++ ++ gcc/ ++ * stmt.c (emit_case_bit_tests): Change prototype. ++ * stmt.c (struct case_bit_test): Add prob field. ++ * stmt.c (get_label_prob): New function. ++ * stmt.c (set_jump_prob): New function. ++ * stmt.c (emit_case_bit_tests): Use get_label_prob. ++ * stmt.c (emit_case_bit_tests): Set prob field. ++ * stmt.c (emit_case_bit_tests): Use set_jump_prob. ++ * stmt.c (expand_case): Add new args to emit_case_bit_tests invocation. ++ * testsuite/gcc.dg/switch-prob.c: Add test. ++ ++2011-02-04 Andrew Stubbs ++ ++ gcc/ ++ * LINARO-VERSION: Bump version. ++ ++2011-02-04 Andrew Stubbs ++ ++ GCC Linaro 4.5-2011.02-0 released. ++ ++ gcc/ ++ * LINARO-VERSION: Update. ++ ++2011-02-04 Andrew Stubbs ++ ++ Revert: ++ ++ 2010-01-25 Tom de Vries ++ ++ gcc/ ++ * stmt.c (emit_case_bit_tests): Change prototype. ++ * stmt.c (struct case_bit_test): Add prob field. ++ * stmt.c (get_label_prob): New function. ++ * stmt.c (set_jump_prob): New function. ++ * stmt.c (emit_case_bit_tests): Use get_label_prob. ++ * stmt.c (emit_case_bit_tests): Set prob field. ++ * stmt.c (emit_case_bit_tests): Use set_jump_prob. ++ * stmt.c (expand_case): Add new args to emit_case_bit_tests invocation. ++ * testsuite/gcc.dg/switch-prob.c: Add test. ++ ++2010-01-25 Tom de Vries ++ ++ gcc/ ++ * stmt.c (emit_case_bit_tests): Change prototype. ++ * stmt.c (struct case_bit_test): Add prob field. ++ * stmt.c (get_label_prob): New function. ++ * stmt.c (set_jump_prob): New function. ++ * stmt.c (emit_case_bit_tests): Use get_label_prob. ++ * stmt.c (emit_case_bit_tests): Set prob field. ++ * stmt.c (emit_case_bit_tests): Use set_jump_prob. ++ * stmt.c (expand_case): Add new args to emit_case_bit_tests invocation. ++ * testsuite/gcc.dg/switch-prob.c: Add test. ++ ++2010-12-13 Tom de Vries ++ ++ gcc/ ++ * tree-if-switch-conversion.c: New pass. ++ * tree-pass.h (pass_if_to_switch): Declare. ++ * common.opt (ftree-if-to-switch-conversion): New switch. ++ * opts.c (decode_options): Set flag_tree_if_to_switch_conversion at -O2 ++ and higher. ++ * passes.c (init_optimization_passes): Use new pass. ++ * params.def (PARAM_IF_TO_SWITCH_THRESHOLD): New param. ++ * doc/invoke.texi (-ftree-if-to-switch-conversion) ++ (if-to-switch-threshold): New item. ++ * doc/invoke.texi (Optimization Options, option -O2): Add ++ -ftree-if-to-switch-conversion. ++ * Makefile.in (OBJS-common): Add tree-if-switch-conversion.o. ++ * Makefile.in (tree-if-switch-conversion.o): New rule. ++ ++2011-01-31 Ramana Radhakrishnan ++ ++ Backport from FSF 4.5 branch. ++ 2011-01-21 Ramana Radhakrishnan ++ ++ Backport from mainline. ++ 2010-09-08 Ramana Radhakrishnan ++ ++ PR target/44392 ++ * config/arm/arm.md (bswapsi2): Handle condition correctly ++ for armv6 and optimize_size. ++ ++2011-01-19 Ramana Radhakrishnan ++ ++ Backport from FSF mainline ++ ++ 2011-01-18 Ramana Radhakrishnan ++ ++ * config/arm/cortex-a9.md (cortex-a9-neon.md): Actually ++ include. ++ (cortex_a9_dp): Handle neon types correctly. ++ ++2011-01-18 Ulrich Weigand ++ ++ LP: #685352 ++ Backport from mainline: ++ ++ 2011-01-18 Jakub Jelinek ++ ++ gcc/ ++ PR rtl-optimization/47299 ++ * expr.c (expand_expr_real_2) : Don't use ++ subtarget. Use normal multiplication if both operands are ++ constants. ++ * expmed.c (expand_widening_mult): Don't try to optimize constant ++ multiplication if op0 has VOIDmode. Convert op1 constant to mode ++ before using it. ++ ++ gcc/testsuite/ ++ PR rtl-optimization/47299 ++ * gcc.c-torture/execute/pr47299.c: New test. ++ ++2011-01-10 Ken Werner ++ ++ LP: #681138 ++ Backport from mainline: ++ ++ gcc/ ++ * config/arm/sync.md (sync_clobber, sync_t2_reqd): New code attribute. ++ (arm_sync_old_si, arm_sync_old_): Use ++ the sync_clobber and sync_t2_reqd code attributes. ++ * config/arm/arm.c (arm_output_sync_loop): Reverse the operation if ++ the t2 argument is NULL. ++ ++2011-01-13 Andrew Stubbs ++ ++ gcc/ ++ * LINARO-VERSION: Bump version. ++ ++2011-01-13 Andrew Stubbs ++ ++ GCC Linaro 4.5-2011.01-1 released. ++ ++ gcc/ ++ * LINARO-VERSION: Update. ++ ++2011-01-13 Andrew Stubbs ++ ++ Revert: ++ ++ 2010-12-03 Yao Qi ++ ++ * config/arm/arm-ldmstm.ml: Rewrite ldm/stm RTL patterns to fix ++ regressions. ++ * config/arm/ldmstm.md: Regenreate. ++ ++ 2010-12-03 Yao Qi ++ ++ Backport from FSF mainline: ++ ++ 2010-08-02 Bernd Schmidt ++ ++ PR target/40457 ++ * config/arm/arm.h (arm_regs_in_sequence): Declare. ++ * config/arm/arm-protos.h (emit_ldm_seq, emit_stm_seq, ++ load_multiple_sequence, store_multiple_sequence): Delete ++ declarations. ++ (arm_gen_load_multiple, arm_gen_store_multiple): Adjust ++ declarations. ++ * config/arm/ldmstm.md: New file. ++ * config/arm/arm.c (arm_regs_in_sequence): New array. ++ (load_multiple_sequence): Now static. New args SAVED_ORDER, ++ CHECK_REGS. All callers changed. ++ If SAVED_ORDER is nonnull, copy the computed order into it. ++ If CHECK_REGS is false, don't sort REGS. Handle Thumb mode. ++ (store_multiple_sequence): Now static. New args NOPS_TOTAL, ++ SAVED_ORDER, REG_RTXS and CHECK_REGS. All callers changed. ++ If SAVED_ORDER is nonnull, copy the computed order into it. ++ If CHECK_REGS is false, don't sort REGS. Set up REG_RTXS just ++ like REGS. Handle Thumb mode. ++ (arm_gen_load_multiple_1): New function, broken out of ++ arm_gen_load_multiple. ++ (arm_gen_store_multiple_1): New function, broken out of ++ arm_gen_store_multiple. ++ (arm_gen_multiple_op): New function, with code from ++ arm_gen_load_multiple and arm_gen_store_multiple moved here. ++ (arm_gen_load_multiple, arm_gen_store_multiple): Now just ++ wrappers around arm_gen_multiple_op. Remove argument UP, all callers ++ changed. ++ (gen_ldm_seq, gen_stm_seq, gen_const_stm_seq): New functions. ++ * config/arm/predicates.md (commutative_binary_operator): New. ++ (load_multiple_operation, store_multiple_operation): Handle more ++ variants of these patterns with different starting offsets. Handle ++ Thumb-1. ++ * config/arm/arm.md: Include "ldmstm.md". ++ (ldmsi_postinc4, ldmsi_postinc4_thumb1, ldmsi_postinc3, ldmsi_postinc2, ++ ldmsi4, ldmsi3, ldmsi2, stmsi_postinc4, stmsi_postinc4_thumb1, ++ stmsi_postinc3, stmsi_postinc2, stmsi4, stmsi3, stmsi2 and related ++ peepholes): Delete. ++ * config/arm/ldmstm.md: New file. ++ * config/arm/arm-ldmstm.ml: New file. ++ ++ * config/arm/arm.c (arm_rtx_costs_1): Remove second clause from the ++ if statement which adds extra costs to frame-related expressions. ++ ++ 2010-05-06 Bernd Schmidt ++ ++ * config/arm/arm.h (MAX_LDM_STM_OPS): New macro. ++ * config/arm/arm.c (multiple_operation_profitable_p, ++ compute_offset_order): New static functions. ++ (load_multiple_sequence, store_multiple_sequence): Use them. ++ Replace constant 4 with MAX_LDM_STM_OPS. Compute order[0] from ++ memory offsets, not register numbers. ++ (emit_ldm_seq, emit_stm_seq): Replace constant 4 with MAX_LDM_STM_OPS. ++ ++ 2010-04-16 Bernd Schmidt ++ ++ * recog.h (struct recog_data): New field is_operator. ++ (struct insn_operand_data): New field is_operator. ++ * recog.c (extract_insn): Set recog_data.is_operator. ++ * genoutput.c (output_operand_data): Emit code to set the ++ is_operator field. ++ * reload.c (find_reloads): Use it rather than testing for an ++ empty constraint string. ++ ++ 2011-01-03 Bernd Schmidt ++ ++ gcc/ ++ * doc/tm.texi (RETURN_ADDR_REGNUM): Document. ++ * doc/md.texi (simple_return): Document pattern. ++ (return): Add a sentence to clarify. ++ * doc/rtl.texi (simple_return): Document. ++ * doc/invoke.texi (Optimize Options): Document -fshrink-wrap. ++ * common.opt (fshrink-wrap): New. ++ * opts.c (decode_options): Set it for -O2 and above. ++ * gengenrtl.c (special_rtx): PC, CC0, RETURN and SIMPLE_RETURN ++ are special. ++ * rtl.h (ANY_RETURN_P): New macro. ++ (global_rtl_index): Add GR_RETURN and GR_SIMPLE_RETURN. ++ (ret_rtx, simple_return_rtx): New macros. ++ * genemit.c (gen_exp): RETURN and SIMPLE_RETURN have unique rtxs. ++ (gen_expand, gen_split): Use ANY_RETURN_P. ++ * rtl.c (copy_rtx): RETURN and SIMPLE_RETURN are shared. ++ * emit-rtl.c (verify_rtx_sharing): Likewise. ++ (skip_consecutive_labels): Return the argument if it is a return rtx. ++ (classify_insn): Handle both kinds of return. ++ (init_emit_regs): Create global rtl for ret_rtx and simple_return_rtx. ++ * df-scan.c (df_uses_record): Handle SIMPLE_RETURN. ++ * rtl.def (SIMPLE_RETURN): New. ++ * rtlanal.c (tablejump_p): Check JUMP_LABEL for returns. ++ * final.c (final_scan_insn): Recognize both kinds of return. ++ * reorg.c (function_return_label, function_simple_return_label): New ++ static variables. ++ (end_of_function_label): Remove. ++ (simplejump_or_return_p): New static function. ++ (find_end_label): Add a new arg, KIND. All callers changed. ++ Depending on KIND, look for a label suitable for return or ++ simple_return. ++ (make_return_insns): Make corresponding changes. ++ (get_jump_flags): Check JUMP_LABELs for returns. ++ (follow_jumps): Likewise. ++ (get_branch_condition): Check target for return patterns rather ++ than NULL. ++ (own_thread_p): Likewise for thread. ++ (steal_delay_list_from_target): Check JUMP_LABELs for returns. ++ Use simplejump_or_return_p. ++ (fill_simple_delay_slots): Likewise. ++ (optimize_skip): Likewise. ++ (fill_slots_from_thread): Likewise. ++ (relax_delay_slots): Likewise. ++ (dbr_schedule): Adjust handling of end_of_function_label for the ++ two new variables. ++ * ifcvt.c (find_if_case_1): Take care when redirecting jumps to the ++ exit block. ++ (dead_or_predicable): Change NEW_DEST arg to DEST_EDGE. All callers ++ changed. Ensure that the right label is passed to redirect_jump. ++ * jump.c (condjump_p, condjump_in_parallel_p, any_condjump_p, ++ returnjump_p): Handle SIMPLE_RETURNs. ++ (delete_related_insns): Check JUMP_LABEL for returns. ++ (redirect_target): New static function. ++ (redirect_exp_1): Use it. Handle any kind of return rtx as a label ++ rather than interpreting NULL as a return. ++ (redirect_jump_1): Assert that nlabel is not NULL. ++ (redirect_jump): Likewise. ++ (redirect_jump_2): Handle any kind of return rtx as a label rather ++ than interpreting NULL as a return. ++ * dwarf2out.c (compute_barrier_args_size_1): Check JUMP_LABEL for ++ returns. ++ * function.c (emit_return_into_block): Remove useless declaration. ++ (record_hard_reg_sets, frame_required_for_rtx, gen_return_pattern, ++ requires_stack_frame_p): New static functions. ++ (emit_return_into_block): New arg SIMPLE_P. All callers changed. ++ Generate either kind of return pattern and update the JUMP_LABEL. ++ (thread_prologue_and_epilogue_insns): Implement a form of ++ shrink-wrapping. Ensure JUMP_LABELs for return insns are set. ++ * print-rtl.c (print_rtx): Handle returns in JUMP_LABELs. ++ * cfglayout.c (fixup_reorder_chain): Ensure JUMP_LABELs for returns ++ remain correct. ++ * resource.c (find_dead_or_set_registers): Check JUMP_LABELs for ++ returns. ++ (mark_target_live_regs): Don't pass a return rtx to next_active_insn. ++ * basic-block.h (force_nonfallthru_and_redirect): Declare. ++ * sched-vis.c (print_pattern): Add case for SIMPLE_RETURN. ++ * cfgrtl.c (force_nonfallthru_and_redirect): No longer static. New arg ++ JUMP_LABEL. All callers changed. Use the label when generating ++ return insns. ++ ++ * config/i386/i386.md (returns, return_str, return_cond): New ++ code_iterator and corresponding code_attrs. ++ (return): Renamed from return and adapted. ++ (return_internal): Likewise for return_internal. ++ (return_internal_long): Likewise for return_internal_long. ++ (return_pop_internal): Likewise for return_pop_internal. ++ (return_indirect_internal): Likewise for ++ return_indirect_internal. ++ * config/i386/i386.c (ix86_expand_epilogue): Expand a simple_return as ++ the last insn. ++ (ix86_pad_returns): Handle both kinds of return rtx. ++ * config/arm/arm.c (use_simple_return_p): new function. ++ (is_jump_table): Handle returns in JUMP_LABELs. ++ (output_return_instruction): New arg SIMPLE. All callers changed. ++ Use it to determine which kind of return to generate. ++ (arm_final_prescan_insn): Handle both kinds of return. ++ * config/arm/arm.md (returns, return_str, return_simple_p, ++ return_cond): New code_iterator and corresponding code_attrs. ++ (return): Renamed from return and adapted. ++ (arm_return): Renamed from arm_return and adapted. ++ (cond_return): Renamed from cond_return and adapted. ++ (cond_return_inverted): Renamed from cond_return_inverted ++ and adapted. ++ (epilogue): Use ret_rtx instead of gen_rtx_RETURN. ++ * config/arm/thumb2.md (thumb2_return): Renamed from ++ thumb2_return and adapted. ++ * config/arm/arm.h (RETURN_ADDR_REGNUM): Define. ++ * config/arm/arm-protos.h (use_simple_return_p): Declare. ++ (output_return_instruction): Adjust declaration. ++ * config/mips/mips.c (mips_expand_epilogue): Generate a simple_return ++ as final insn. ++ * config/mips/mips.md (simple_return): New expander. ++ (*simple_return, simple_return_internal): New patterns. ++ * config/sh/sh.c (barrier_align): Handle return in a JUMP_LABEL. ++ (split_branches): Don't pass a null label to redirect_jump. ++ ++ From mainline: ++ * vec.h (FOR_EACH_VEC_ELT, FOR_EACH_VEC_ELT_REVERSE): New macros. ++ * haifa-sched.c (find_fallthru_edge_from): Rename from ++ find_fallthru_edge. All callers changed. ++ * sched-int.h (find_fallthru_edge_from): Rename declaration as well. ++ * basic-block.h (find_fallthru_edge): New inline function. ++ ++2011-01-07 Andrew Stubbs ++ ++ gcc/ ++ * LINARO-VERSION: Bump version. ++ ++2011-01-07 Andrew Stubbs ++ ++ GCC Linaro 4.5-2011.01-0 released. ++ ++ gcc/ ++ * LINARO-VERSION: Update. ++ ++2011-01-06 Andrew Stubbs ++ ++ Merge from FSF 4.5 branch r167945 (4.5.2 release). ++ ++2010-12-03 Yao Qi ++ ++ * config/arm/arm-ldmstm.ml: Rewrite ldm/stm RTL patterns to fix ++ regressions. ++ * config/arm/ldmstm.md: Regenreate. ++ ++2010-12-03 Yao Qi ++ ++ Backport from FSF mainline: ++ ++ 2010-08-02 Bernd Schmidt ++ ++ PR target/40457 ++ * config/arm/arm.h (arm_regs_in_sequence): Declare. ++ * config/arm/arm-protos.h (emit_ldm_seq, emit_stm_seq, ++ load_multiple_sequence, store_multiple_sequence): Delete ++ declarations. ++ (arm_gen_load_multiple, arm_gen_store_multiple): Adjust ++ declarations. ++ * config/arm/ldmstm.md: New file. ++ * config/arm/arm.c (arm_regs_in_sequence): New array. ++ (load_multiple_sequence): Now static. New args SAVED_ORDER, ++ CHECK_REGS. All callers changed. ++ If SAVED_ORDER is nonnull, copy the computed order into it. ++ If CHECK_REGS is false, don't sort REGS. Handle Thumb mode. ++ (store_multiple_sequence): Now static. New args NOPS_TOTAL, ++ SAVED_ORDER, REG_RTXS and CHECK_REGS. All callers changed. ++ If SAVED_ORDER is nonnull, copy the computed order into it. ++ If CHECK_REGS is false, don't sort REGS. Set up REG_RTXS just ++ like REGS. Handle Thumb mode. ++ (arm_gen_load_multiple_1): New function, broken out of ++ arm_gen_load_multiple. ++ (arm_gen_store_multiple_1): New function, broken out of ++ arm_gen_store_multiple. ++ (arm_gen_multiple_op): New function, with code from ++ arm_gen_load_multiple and arm_gen_store_multiple moved here. ++ (arm_gen_load_multiple, arm_gen_store_multiple): Now just ++ wrappers around arm_gen_multiple_op. Remove argument UP, all callers ++ changed. ++ (gen_ldm_seq, gen_stm_seq, gen_const_stm_seq): New functions. ++ * config/arm/predicates.md (commutative_binary_operator): New. ++ (load_multiple_operation, store_multiple_operation): Handle more ++ variants of these patterns with different starting offsets. Handle ++ Thumb-1. ++ * config/arm/arm.md: Include "ldmstm.md". ++ (ldmsi_postinc4, ldmsi_postinc4_thumb1, ldmsi_postinc3, ldmsi_postinc2, ++ ldmsi4, ldmsi3, ldmsi2, stmsi_postinc4, stmsi_postinc4_thumb1, ++ stmsi_postinc3, stmsi_postinc2, stmsi4, stmsi3, stmsi2 and related ++ peepholes): Delete. ++ * config/arm/ldmstm.md: New file. ++ * config/arm/arm-ldmstm.ml: New file. ++ ++ * config/arm/arm.c (arm_rtx_costs_1): Remove second clause from the ++ if statement which adds extra costs to frame-related expressions. ++ ++ 2010-05-06 Bernd Schmidt ++ ++ * config/arm/arm.h (MAX_LDM_STM_OPS): New macro. ++ * config/arm/arm.c (multiple_operation_profitable_p, ++ compute_offset_order): New static functions. ++ (load_multiple_sequence, store_multiple_sequence): Use them. ++ Replace constant 4 with MAX_LDM_STM_OPS. Compute order[0] from ++ memory offsets, not register numbers. ++ (emit_ldm_seq, emit_stm_seq): Replace constant 4 with MAX_LDM_STM_OPS. ++ ++ 2010-04-16 Bernd Schmidt ++ ++ * recog.h (struct recog_data): New field is_operator. ++ (struct insn_operand_data): New field is_operator. ++ * recog.c (extract_insn): Set recog_data.is_operator. ++ * genoutput.c (output_operand_data): Emit code to set the ++ is_operator field. ++ * reload.c (find_reloads): Use it rather than testing for an ++ empty constraint string. ++ ++2011-01-03 Bernd Schmidt ++ ++ gcc/ ++ * doc/tm.texi (RETURN_ADDR_REGNUM): Document. ++ * doc/md.texi (simple_return): Document pattern. ++ (return): Add a sentence to clarify. ++ * doc/rtl.texi (simple_return): Document. ++ * doc/invoke.texi (Optimize Options): Document -fshrink-wrap. ++ * common.opt (fshrink-wrap): New. ++ * opts.c (decode_options): Set it for -O2 and above. ++ * gengenrtl.c (special_rtx): PC, CC0, RETURN and SIMPLE_RETURN ++ are special. ++ * rtl.h (ANY_RETURN_P): New macro. ++ (global_rtl_index): Add GR_RETURN and GR_SIMPLE_RETURN. ++ (ret_rtx, simple_return_rtx): New macros. ++ * genemit.c (gen_exp): RETURN and SIMPLE_RETURN have unique rtxs. ++ (gen_expand, gen_split): Use ANY_RETURN_P. ++ * rtl.c (copy_rtx): RETURN and SIMPLE_RETURN are shared. ++ * emit-rtl.c (verify_rtx_sharing): Likewise. ++ (skip_consecutive_labels): Return the argument if it is a return rtx. ++ (classify_insn): Handle both kinds of return. ++ (init_emit_regs): Create global rtl for ret_rtx and simple_return_rtx. ++ * df-scan.c (df_uses_record): Handle SIMPLE_RETURN. ++ * rtl.def (SIMPLE_RETURN): New. ++ * rtlanal.c (tablejump_p): Check JUMP_LABEL for returns. ++ * final.c (final_scan_insn): Recognize both kinds of return. ++ * reorg.c (function_return_label, function_simple_return_label): New ++ static variables. ++ (end_of_function_label): Remove. ++ (simplejump_or_return_p): New static function. ++ (find_end_label): Add a new arg, KIND. All callers changed. ++ Depending on KIND, look for a label suitable for return or ++ simple_return. ++ (make_return_insns): Make corresponding changes. ++ (get_jump_flags): Check JUMP_LABELs for returns. ++ (follow_jumps): Likewise. ++ (get_branch_condition): Check target for return patterns rather ++ than NULL. ++ (own_thread_p): Likewise for thread. ++ (steal_delay_list_from_target): Check JUMP_LABELs for returns. ++ Use simplejump_or_return_p. ++ (fill_simple_delay_slots): Likewise. ++ (optimize_skip): Likewise. ++ (fill_slots_from_thread): Likewise. ++ (relax_delay_slots): Likewise. ++ (dbr_schedule): Adjust handling of end_of_function_label for the ++ two new variables. ++ * ifcvt.c (find_if_case_1): Take care when redirecting jumps to the ++ exit block. ++ (dead_or_predicable): Change NEW_DEST arg to DEST_EDGE. All callers ++ changed. Ensure that the right label is passed to redirect_jump. ++ * jump.c (condjump_p, condjump_in_parallel_p, any_condjump_p, ++ returnjump_p): Handle SIMPLE_RETURNs. ++ (delete_related_insns): Check JUMP_LABEL for returns. ++ (redirect_target): New static function. ++ (redirect_exp_1): Use it. Handle any kind of return rtx as a label ++ rather than interpreting NULL as a return. ++ (redirect_jump_1): Assert that nlabel is not NULL. ++ (redirect_jump): Likewise. ++ (redirect_jump_2): Handle any kind of return rtx as a label rather ++ than interpreting NULL as a return. ++ * dwarf2out.c (compute_barrier_args_size_1): Check JUMP_LABEL for ++ returns. ++ * function.c (emit_return_into_block): Remove useless declaration. ++ (record_hard_reg_sets, frame_required_for_rtx, gen_return_pattern, ++ requires_stack_frame_p): New static functions. ++ (emit_return_into_block): New arg SIMPLE_P. All callers changed. ++ Generate either kind of return pattern and update the JUMP_LABEL. ++ (thread_prologue_and_epilogue_insns): Implement a form of ++ shrink-wrapping. Ensure JUMP_LABELs for return insns are set. ++ * print-rtl.c (print_rtx): Handle returns in JUMP_LABELs. ++ * cfglayout.c (fixup_reorder_chain): Ensure JUMP_LABELs for returns ++ remain correct. ++ * resource.c (find_dead_or_set_registers): Check JUMP_LABELs for ++ returns. ++ (mark_target_live_regs): Don't pass a return rtx to next_active_insn. ++ * basic-block.h (force_nonfallthru_and_redirect): Declare. ++ * sched-vis.c (print_pattern): Add case for SIMPLE_RETURN. ++ * cfgrtl.c (force_nonfallthru_and_redirect): No longer static. New arg ++ JUMP_LABEL. All callers changed. Use the label when generating ++ return insns. ++ ++ * config/i386/i386.md (returns, return_str, return_cond): New ++ code_iterator and corresponding code_attrs. ++ (return): Renamed from return and adapted. ++ (return_internal): Likewise for return_internal. ++ (return_internal_long): Likewise for return_internal_long. ++ (return_pop_internal): Likewise for return_pop_internal. ++ (return_indirect_internal): Likewise for ++ return_indirect_internal. ++ * config/i386/i386.c (ix86_expand_epilogue): Expand a simple_return as ++ the last insn. ++ (ix86_pad_returns): Handle both kinds of return rtx. ++ * config/arm/arm.c (use_simple_return_p): new function. ++ (is_jump_table): Handle returns in JUMP_LABELs. ++ (output_return_instruction): New arg SIMPLE. All callers changed. ++ Use it to determine which kind of return to generate. ++ (arm_final_prescan_insn): Handle both kinds of return. ++ * config/arm/arm.md (returns, return_str, return_simple_p, ++ return_cond): New code_iterator and corresponding code_attrs. ++ (return): Renamed from return and adapted. ++ (arm_return): Renamed from arm_return and adapted. ++ (cond_return): Renamed from cond_return and adapted. ++ (cond_return_inverted): Renamed from cond_return_inverted ++ and adapted. ++ (epilogue): Use ret_rtx instead of gen_rtx_RETURN. ++ * config/arm/thumb2.md (thumb2_return): Renamed from ++ thumb2_return and adapted. ++ * config/arm/arm.h (RETURN_ADDR_REGNUM): Define. ++ * config/arm/arm-protos.h (use_simple_return_p): Declare. ++ (output_return_instruction): Adjust declaration. ++ * config/mips/mips.c (mips_expand_epilogue): Generate a simple_return ++ as final insn. ++ * config/mips/mips.md (simple_return): New expander. ++ (*simple_return, simple_return_internal): New patterns. ++ * config/sh/sh.c (barrier_align): Handle return in a JUMP_LABEL. ++ (split_branches): Don't pass a null label to redirect_jump. ++ ++ From mainline: ++ * vec.h (FOR_EACH_VEC_ELT, FOR_EACH_VEC_ELT_REVERSE): New macros. ++ * haifa-sched.c (find_fallthru_edge_from): Rename from ++ find_fallthru_edge. All callers changed. ++ * sched-int.h (find_fallthru_edge_from): Rename declaration as well. ++ * basic-block.h (find_fallthru_edge): New inline function. ++ ++2010-12-21 Chung-Lin Tang ++ ++ Issue #10201 ++ ++ Backport from mainline: ++ ++ 2010-12-16 Chung-Lin Tang ++ ++ PR target/46883 ++ gcc/ ++ * config/arm/arm.md ++ (zero_extendhisi2 for register input splitter): Change ++ "register_operand" to "s_register_operand". ++ (zero_extendqisi2 for register input splitter): Same. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/pr46883.c: New testcase. ++ ++2010-12-18 Andrew Stubbs ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-12-17 Andrew Stubbs ++ ++ * config/arm/arm.md (maddhisi4, *maddhidi4): Use the canonical ++ operand order for plus. ++ Drop redundant % from constraints. ++ ++2010-12-17 Bernd Schmidt ++ ++ Issue #10208 ++ ++ gcc/ ++ * config/arm/arm.c (arm_select_cc_mode): Before calling ++ arm_select_dominance_cc_mode for AND or IOR operations, ensure ++ that op is NE or EQ. ++ ++ gcc/testsuite/ ++ * gcc.c-torture/compile/20101217-1.c: New test. ++ ++2010-12-14 Sandra Loosemore ++ ++ Backport from mainline: ++ ++ 2010-12-14 Jakub Jelinek ++ ++ PR tree-optimization/46909 ++ ++ gcc/ ++ * tree-ssa-ccp.c (and_var_with_comparison_1): Save partial ++ result even in the is_and case, if both partial results ++ are the same, return it. ++ (or_var_with_comparison_1): Use is_or predicate instead of ++ innercode == TRUTH_OR_EXPR test. Save partial result ++ even in the is_or case, if both partial results are the ++ same, return it. In the !is_or case when both partial ++ results are the same, return the partial result instead ++ of boolean_true_node. ++ ++ gcc/testsuite/ ++ * gcc.c-torture/execute/pr46909-1.c: New test. ++ * gcc.c-torture/execute/pr46909-2.c: New test. ++ * gcc.dg/pr46909.c: New test. ++ ++2010-12-22 Ulrich Weigand ++ ++ LP: #693425 ++ Backport from mainline: ++ ++ gcc/ ++ * config/spu/spu.md ("mov"): Use nonimmediate_operand ++ predicate for destination operand. ++ * config/spu/spu.c (spu_expand_mov): If move destination is an ++ invalid subreg, perform move in the subreg's inner mode instead. ++ ++2010-12-21 Ulrich Weigand ++ ++ LP: #662324 ++ Backport from mainline: ++ ++ 2010-12-17 Dodji Seketeli ++ ++ gcc/ ++ * dwarf2out.c (gen_type_die_with_usage): Do not try to emit debug ++ info for a redundant typedef that has DECL_ORIGINAL_TYPE set. Use ++ that underlying type instead. ++ ++ gcc/testsuite/ ++ * g++.dg/debug/dwarf2/self-ref-1.C: New test. ++ * g++.dg/debug/dwarf2/self-ref-2.C: Likewise. ++ ++2010-12-21 Ulrich Weigand ++ ++ LP: #617384 ++ Backport from mainline: ++ ++ gcc/ ++ * config/arm/arm.c (require_pic_register): Set INSN_LOCATOR for all ++ instructions injected into the prologue to prologue_locator. ++ ++2010-12-13 Chung-Lin Tang ++ ++ Backport from mainline: ++ ++ 2010-12-10 Jakub Jelinek ++ ++ PR rtl-optimization/46865 ++ ++ * rtl.c (rtx_equal_p_cb, rtx_equal_p): For last operand of ++ ASM_OPERANDS and ASM_INPUT if integers are different, ++ call locator_eq. ++ * jump.c (rtx_renumbered_equal_p): Likewise. ++ ++ gcc/testsuite/ ++ * gcc.target/i386/pr46865-1.c: New test. ++ * gcc.target/i386/pr46865-2.c: New test. ++ ++2010-12-14 Andrew Stubbs ++ ++ gcc/ ++ * DEV-PHASE: Revert to upstream state. ++ * REVISION: Delete file. ++ * configure: Regenerate. ++ * configure.ac (PKGVERSION): Set default to a custom ++ Linaro string. ++ * LINARO-VERSION: New file. ++ ++2010-12-10 Andrew Stubbs ++ ++ gcc/ ++ * REVISION: Bump version. ++ ++2010-12-10 Andrew Stubbs ++ ++ GCC Linaro 4.5-2010.12-0 released. ++ ++ gcc/ ++ * REVISION: Update. ++ ++2010-12-02 Bernd Schmidt ++ ++ Issue #10089 ++ ++ gcc/ ++ * expr.c (store_field): Avoid a direct store if the mode is larger ++ than the size of the bit field. ++ * stor-layout.c (layout_decl): If flag_strict_volatile_bitfields, ++ treat non-volatile bit fields like volatile ones. ++ * toplev.c (process_options): Disallow combination of ++ -fstrict-volatile-bitfields and ABI versions less than 2. ++ * config/arm/arm.c (arm_option_override): Don't enable ++ flag_strict_volatile_bitfields if the ABI version is less than 2. ++ * config/h8300/h8300.c (h8300_option_override): Likewise. ++ * config/rx/rx.c (rx_option_override): Likewise. ++ * config/m32c/m32c.c (m32c_option_override): Likewise. ++ * config/sh/sh.c (sh_option_override): Likewise. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/volatile-bitfields-4.c: New test. ++ * c-c++-common/abi-bf.c: New test. ++ ++2010-11-26 Tom de Vries ++ ++ gcc/ ++ * gcc/ee.c: New file. ++ * gcc/tree-pass.h (pass_ee): Declare. ++ * gcc/opts.c (decode_options): Set flag_ee at -O2. ++ * gcc/timevar.def (TV_EE): New timevar. ++ * gcc/common.opt (fextension-elimination): New option. ++ * gcc/Makefile.in (ee.o): New rule. ++ * gcc/passes.c (pass_ee): Add it. ++ * gcc/testsuite/gcc.dg/extend-4.c: New test. ++ * gcc/testsuite/gcc.dg/extend-1.c: New test. ++ * gcc/testsuite/gcc.dg/extend-2.c: New test. ++ * gcc/testsuite/gcc.dg/extend-2-64.c: New test. ++ * gcc/testsuite/gcc.dg/extend-3.c: New test. ++ ++2010-11-24 Maxim Kuvyrkov ++ ++ gcc/ ++ * loop-iv.c (get_biv_step): Workaround loop analysis ICE. ++ ++2010-11-25 Andrew Stubbs ++ ++ Backport from mainline: ++ ++ 2010-10-28 Andrew Stubbs ++ ++ gcc/ ++ * config/arm/arm.c (const_ok_for_arm): Support 0xXY00XY00 pattern ++ constants in thumb2. ++ ++2010-11-24 Chung-Lin Tang ++ ++ 2010-07-08 Ramana Radhakrishnan ++ ++ PR bootstrap/44768 ++ ++ * cfgexpand.c (estimated_stack_frame_size): Make self-contained ++ with respect to current_function_decl. Pass decl of the function. ++ * tree-inline.h (estimated_stack_frame_size): Adjust prototype. ++ * ipa-inline.c (compute_inline_parameters): Pass decl to ++ estimated_stack_frame_size. ++ ++2010-11-16 Chung-Lin Tang ++ ++ 2010-07-21 Richard Henderson ++ ++ gcc/ ++ * config/i386/i386.c (setup_incoming_varargs_64): Emit a simple ++ comparison for avoiding xmm register saves. Emit the xmm register ++ saves explicitly. ++ * config/i386/i386.md (UNSPEC_SSE_PROLOGUE_SAVE): Remove. ++ (UNSPEC_SSE_PROLOGUE_SAVE_LOW): Remove. ++ (sse_prologue_save, sse_prologue_save_insn1, sse_prologue_save_insn): ++ Remove patterns and the associated splitters. ++ ++ 2010-07-22 Richard Henderson ++ ++ gcc/ ++ PR target/45027 ++ * config/i386/i386.c (setup_incoming_varargs_64): Force the use ++ of V4SFmode for the SSE saves; increase stack alignment if needed. ++ ++2010-11-16 Chung-Lin Tang ++ ++ Re-merge, backport from mainline: ++ ++ 2010-07-15 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (last_label_ruid, first_index_reg, last_index_reg): ++ New static variables. ++ (reload_combine_recognize_pattern): New static function, broken out ++ of reload_combine. ++ (reload_combine): Use it. Only initialize first_index_reg and ++ last_index_reg once. ++ ++ 2010-07-17 Bernd Schmidt ++ ++ PR target/42235 ++ gcc/ ++ * postreload.c (reload_cse_move2add): Return bool, true if anything. ++ changed. All callers changed. ++ (move2add_use_add2_insn): Likewise. ++ (move2add_use_add3_insn): Likewise. ++ (reload_cse_regs): If reload_cse_move2add changed anything, rerun ++ reload_combine. ++ (RELOAD_COMBINE_MAX_USES): Bump to 16. ++ (last_jump_ruid): New static variable. ++ (struct reg_use): New members CONTAINING_MEM and RUID. ++ (reg_state): New members ALL_OFFSETS_MATCH and REAL_STORE_RUID. ++ (reload_combine_split_one_ruid, reload_combine_split_ruids, ++ reload_combine_purge_insn_uses, reload_combine_closest_single_use ++ reload_combine_purge_reg_uses_after_ruid, ++ reload_combine_recognize_const_pattern): New static functions. ++ (reload_combine_recognize_pattern): Verify that ALL_OFFSETS_MATCH ++ is true for our reg and that we have available index regs. ++ (reload_combine_note_use): New args RUID and CONTAINING_MEM. All ++ callers changed. Use them to initialize fields in struct reg_use. ++ (reload_combine): Initialize last_jump_ruid. Be careful when to ++ take PREV_INSN of the scanned insn. Update REAL_STORE_RUID fields. ++ Call reload_combine_recognize_const_pattern. ++ (reload_combine_note_store): Update REAL_STORE_RUID field. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/pr42235.c: New test. ++ ++ 2010-07-19 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (reload_combine_closest_single_use): Ignore the ++ number of uses for DEBUG_INSNs. ++ (fixup_debug_insns): New static function. ++ (reload_combine_recognize_const_pattern): Use it. Don't let the ++ main loop be affected by DEBUG_INSNs. ++ Really disallow moving adds past a jump insn. ++ (reload_combine_recognize_pattern): Don't update use_ruid here. ++ (reload_combine_note_use): Do it here. ++ (reload_combine): Use control_flow_insn_p rather than JUMP_P. ++ ++ 2010-07-20 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (fixup_debug_insns): Remove arg REGNO. New args ++ FROM and TO. All callers changed. Don't look for tracked uses, ++ just scan the RTL for DEBUG_INSNs and substitute. ++ (reload_combine_recognize_pattern): Call fixup_debug_insns. ++ (reload_combine): Ignore DEBUG_INSNs. ++ ++ 2010-07-22 Bernd Schmidt ++ ++ PR bootstrap/44970 ++ PR middle-end/45009 ++ gcc/ ++ * postreload.c: Include "target.h". ++ (reload_combine_closest_single_use): Don't take DEBUG_INSNs ++ into account. ++ (fixup_debug_insns): Don't copy the rtx. ++ (reload_combine_recognize_const_pattern): DEBUG_INSNs can't have uses. ++ Don't copy when replacing. Call fixup_debug_insns in the case where ++ we merged one add with another. ++ (reload_combine_recognize_pattern): Fail if there aren't any uses. ++ Try harder to determine whether we're picking a valid index register. ++ Don't set store_ruid for an insn we're going to scan in the ++ next iteration. ++ (reload_combine): Remove unused code. ++ (reload_combine_note_use): When updating use information for ++ an old insn, ignore a use that occurs after store_ruid. ++ * Makefile.in (postreload.o): Update dependencies. ++ ++ 2010-07-27 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (reload_combine_recognize_const_pattern): Move test ++ for limiting the insn movement to the right scope. ++ ++ 2010-07-27 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (try_replace_in_use): New static function. ++ (reload_combine_recognize_const_pattern): Use it here. Allow ++ substituting into a final add insn, and substituting into a memory ++ reference in an insn that sets the reg. ++ ++2010-11-26 Andrew Stubbs ++ ++ Merge from FSF 4.5 branch r167157 (pre 4.5.2). ++ ++2010-11-24 Richard Sandiford ++ ++ Launchpad #618684 ++ ++ Backport from mainline: ++ ++ 2010-04-10 Bernd Schmidt ++ ++ * reload1.c (eliminate_regs_in_insn): Don't restore an operand ++ if doing so would replace the entire pattern. ++ ++2010-11-24 Maxim Kuvyrkov ++ ++ gcc/ ++ * combine.c (subst, combine_simlify_rtx): Add new argument, use it ++ to track processing of conditionals. Update all callers. ++ (try_combine, simplify_if_then_else): Update. ++ ++2010-11-08 Yao Qi ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-08-02 Bernd Schmidt ++ ++ * config/arm/arm.c (arm_rtx_costs_1): Remove second clause from the ++ if statement which adds extra costs to frame-related ++ expressions. ++ ++2010-11-3 Chung-Lin Tang ++ ++ Backport from mainline: ++ ++ 2010-11-02 Chung-Lin Tang ++ ++ gcc/ ++ * Makefile.in (LIBGCC2_CFLAGS): Add -fno-stack-protector, to ++ explicitly disable stack protection when building libgcc. ++ (CRTSTUFF_CFLAGS): Same, for crtbegin/end. ++ ++2010-10-29 Julian Brown ++ ++ Launchpad #629671 ++ ++ gcc/ ++ * config/arm/arm.h (REG_CLASS_CONTENTS): Remove soft frame pointer ++ from CORE_REGS and GENERAL_REGS classes. ++ * config/arm/arm.md (*thumb1_movsi_insn): Ignore all parts of final ++ constraint for register preferencing. ++ ++2010-11-03 Nathan Froyd ++ ++ Issue #10002 ++ ++ gcc/ ++ * config/arm/arm.c (arm_legitimate_index_p): Split ++ VALID_NEON_QREG_MODE and VALID_NEON_DREG_MODE cases. Permit ++ slightly larger constants in the latter case. ++ (thumb2_legitimate_index_p): Likewise. ++ ++2010-11-09 Michael Hope ++ ++ gcc/ ++ * REVISION: Bump version. ++ ++2010-11-09 Michael Hope ++ ++ GCC Linaro 4.5-2010.11-1 released. ++ ++ gcc/ ++ * REVISION: Update. ++ ++2010-11-09 Michael Hope ++ ++ Revert: ++ ++ Backport from mainline: ++ ++ 2010-07-15 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (last_label_ruid, first_index_reg, last_index_reg): ++ New static variables. ++ (reload_combine_recognize_pattern): New static function, broken out ++ of reload_combine. ++ (reload_combine): Use it. Only initialize first_index_reg and ++ last_index_reg once. ++ ++ 2010-07-17 Bernd Schmidt ++ ++ PR target/42235 ++ gcc/ ++ * postreload.c (reload_cse_move2add): Return bool, true if anything. ++ changed. All callers changed. ++ (move2add_use_add2_insn): Likewise. ++ (move2add_use_add3_insn): Likewise. ++ (reload_cse_regs): If reload_cse_move2add changed anything, rerun ++ reload_combine. ++ (RELOAD_COMBINE_MAX_USES): Bump to 16. ++ (last_jump_ruid): New static variable. ++ (struct reg_use): New members CONTAINING_MEM and RUID. ++ (reg_state): New members ALL_OFFSETS_MATCH and REAL_STORE_RUID. ++ (reload_combine_split_one_ruid, reload_combine_split_ruids, ++ reload_combine_purge_insn_uses, reload_combine_closest_single_use ++ reload_combine_purge_reg_uses_after_ruid, ++ reload_combine_recognize_const_pattern): New static functions. ++ (reload_combine_recognize_pattern): Verify that ALL_OFFSETS_MATCH ++ is true for our reg and that we have available index regs. ++ (reload_combine_note_use): New args RUID and CONTAINING_MEM. All ++ callers changed. Use them to initialize fields in struct reg_use. ++ (reload_combine): Initialize last_jump_ruid. Be careful when to ++ take PREV_INSN of the scanned insn. Update REAL_STORE_RUID fields. ++ Call reload_combine_recognize_const_pattern. ++ (reload_combine_note_store): Update REAL_STORE_RUID field. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/pr42235.c: New test. ++ ++ 2010-07-19 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (reload_combine_closest_single_use): Ignore the ++ number of uses for DEBUG_INSNs. ++ (fixup_debug_insns): New static function. ++ (reload_combine_recognize_const_pattern): Use it. Don't let the ++ main loop be affected by DEBUG_INSNs. ++ Really disallow moving adds past a jump insn. ++ (reload_combine_recognize_pattern): Don't update use_ruid here. ++ (reload_combine_note_use): Do it here. ++ (reload_combine): Use control_flow_insn_p rather than JUMP_P. ++ ++ 2010-07-20 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (fixup_debug_insns): Remove arg REGNO. New args ++ FROM and TO. All callers changed. Don't look for tracked uses, ++ just scan the RTL for DEBUG_INSNs and substitute. ++ (reload_combine_recognize_pattern): Call fixup_debug_insns. ++ (reload_combine): Ignore DEBUG_INSNs. ++ ++ 2010-07-22 Bernd Schmidt ++ ++ PR bootstrap/44970 ++ PR middle-end/45009 ++ gcc/ ++ * postreload.c: Include "target.h". ++ (reload_combine_closest_single_use): Don't take DEBUG_INSNs ++ into account. ++ (fixup_debug_insns): Don't copy the rtx. ++ (reload_combine_recognize_const_pattern): DEBUG_INSNs can't have uses. ++ Don't copy when replacing. Call fixup_debug_insns in the case where ++ we merged one add with another. ++ (reload_combine_recognize_pattern): Fail if there aren't any uses. ++ Try harder to determine whether we're picking a valid index register. ++ Don't set store_ruid for an insn we're going to scan in the ++ next iteration. ++ (reload_combine): Remove unused code. ++ (reload_combine_note_use): When updating use information for ++ an old insn, ignore a use that occurs after store_ruid. ++ * Makefile.in (postreload.o): Update dependencies. ++ ++ 2010-07-27 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (reload_combine_recognize_const_pattern): Move test ++ for limiting the insn movement to the right scope. ++ ++ 2010-07-27 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (try_replace_in_use): New static function. ++ (reload_combine_recognize_const_pattern): Use it here. Allow ++ substituting into a final add insn, and substituting into a memory ++ reference in an insn that sets the reg. ++ ++2010-11-05 Andrew Stubbs ++ ++ gcc/ ++ * REVISION: Bump version. ++ ++2010-11-05 Andrew Stubbs ++ ++ GCC Linaro 4.5-2010.11-0 released. ++ ++ gcc/ ++ * REVISION: Update. ++ ++2010-10-26 Jie Zhang ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-10-26 Jie Zhang ++ ++ * doc/invoke.texi: Improve documentation of ++ -fstrict-volatile-bitfields. ++ ++2010-10-26 Jie Zhang ++ ++ Issue #1259 ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-10-26 Jie Zhang ++ ++ * stor-layout.c (layout_decl): Use the field's type to ++ determine the mode and keep DECL_BIT_FIELD for a volatile ++ bit-field. ++ * config/arm/arm.c (arm_override_options): Default to ++ -fstrict-volatile-bitfields. ++ ++ gcc/testsuite/ ++ 2010-10-26 Jie Zhang ++ ++ * gcc.target/arm/volatile-bitfields-1.c: New test. ++ * gcc.target/arm/volatile-bitfields-2.c: New test. ++ * gcc.target/arm/volatile-bitfields-3.c: New test. ++ ++2010-10-25 Jie Zhang ++ ++ Issue #1259 ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-10-22 Jie Zhang ++ ++ * expr.c (emit_group_load_1): Update calls to extract_bit_field. ++ (copy_blkmode_from_reg): Likewise. ++ (read_complex_part): Likewise. ++ (expand_expr_real_1): Calculate packedp and pass it to ++ extract_bit_field. ++ * expr.h (extract_bit_field): Update declaration. ++ * calls.c (store_unaligned_arguments_into_pseudos): Update call ++ to extract_bit_field. ++ * expmed.c (extract_fixed_bit_field): Update calls to ++ extract_fixed_bit_field. ++ (store_split_bit_field): Likewise. ++ (extract_bit_field_1): Add new argument packedp. ++ (extract_bit_field): Add new argument packedp. ++ (extract_fixed_bit_field): Add new argument packedp and let ++ packed attribute override volatile. ++ * stmt.c (expand_return): Update call to extract_bit_field. ++ ++ 2010-10-15 Jie Zhang ++ ++ * doc/invoke.texi: Add -fstrict-volatile-bitfields to ++ Option Summary and Index. ++ ++ 2010-07-13 DJ Delorie ++ ++ * config/h8300/h8300.c (h8300_init_once): Default to ++ -fstrict_volatile_bitfields. ++ ++ * config/sh/sh.c (sh_override_options): Default to ++ -fstrict_volatile_bitfields. ++ ++ * config/rx/rx.c (rx_option_override): New. ++ ++ * config/m32c/m32c.c (m32c_override_options): Default to ++ -fstrict_volatile_bitfields. ++ ++ 2010-06-16 DJ Delorie ++ ++ * common.opt (-fstrict-volatile-bitfields): new. ++ * doc/invoke.texi: Document it. ++ * fold-const.c (optimize_bit_field_compare): For volatile ++ bitfields, use the field's type to determine the mode, not the ++ field's size. ++ * expr.c (expand_assignment): Likewise. ++ (get_inner_reference): Likewise. ++ (expand_expr_real_1): Likewise. ++ * expmed.c (store_fixed_bit_field): Likewise. ++ (extract_bit_field_1): Likewise. ++ (extract_fixed_bit_field): Likewise. ++ ++ gcc/testsuite/ ++ 2010-08-19 Uros Bizjak ++ ++ PR testsuite/45324 ++ * gcc.target/i386/volatile-bitfields-1.c: Also scan movb. ++ ++ 2010-06-16 DJ Delorie ++ ++ * gcc.target/i386/volatile-bitfields-1.c: New. ++ * gcc.target/i386/volatile-bitfields-2.c: New. ++ ++2010-10-25 Jie Zhang ++ ++ Issue #9812 ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-10-25 Jie Zhang ++ * combine.c (try_combine): If insns need to be kept around, ++ check that they can be copied in the merged instruction. ++ ++ gcc/testsuite/ ++ 2010-10-25 Jie Zhang ++ * g++.dg/opt/combine.c: New test. ++ ++2010-10-23 Joseph Myers ++ ++ Backport from FSF: ++ ++ gcc/ ++ 2010-10-14 Joseph Myers ++ ++ PR c/45969 ++ * c-typeck.c (build_binary_op): Don't try to compute a semantic ++ type with excess precision for boolean operations. ++ ++ gcc/testsuite/ ++ 2010-10-14 Joseph Myers ++ ++ PR c/45969 ++ * gcc.c-torture/compile/pr45969-1.c: New test. ++ ++2010-10-20 Nathan Froyd ++ ++ Issue #9781 ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-10-20 Nathan Froyd ++ ++ * ifcvt.c (noce_emit_cmove): If both of the values are SUBREGs, try ++ emitting the conditional move in the inner mode of the SUBREG. ++ ++2010-10-18 Kazu Hirata ++ ++ Issue #9720 ++ Backport from mainline: ++ gcc/ ++ 2010-10-07 Tejas Belagod ++ * config/arm/neon.md (neon_unpack_): Add 'w' to ++ constraint, add register specifier in instruction template. ++ (neon_vec_pack_trunc_): Likewise. ++ (neon_vec_mult_): Add register specifier to ++ instruction template. ++ ++2010-10-22 Julian Brown ++ ++ Backport from mainline: ++ ++ 2010-10-18 Marcus Shawcroft ++ ++ gcc/testsuite/ ++ * gcc.target/arm/synchronize.c: Permit dmb or mcr in assembler scan. ++ ++2010-10-14 Julian Brown ++ ++ Backport from mainline: ++ ++ 2010-08-18 Marcus Shawcroft ++ ++ gcc/ ++ * config/arm/arm-protos.h (arm_expand_sync): New. ++ (arm_output_memory_barrier, arm_output_sync_insn): New. ++ (arm_sync_loop_insns): New. ++ * config/arm/arm.c (FL_ARCH7): New. ++ (FL_FOR_ARCH7): Include FL_ARCH7. ++ (arm_arch7): New. ++ (arm_print_operand): Support %C markup. ++ (arm_legitimize_sync_memory): New. ++ (arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New. ++ (arm_process_output_memory_barrier, arm_output_memory_barrier): New. ++ (arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New. ++ (arm_output_op2, arm_output_op3, arm_output_sync_loop): New. ++ (arm_get_sync_operand, FETCH_SYNC_OPERAND): New. ++ (arm_process_output_sync_insn, arm_output_sync_insn): New. ++ (arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New. ++ * config/arm/arm.h (struct arm_sync_generator): New. ++ (TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New. ++ (TARGET_HAVE_MEMORY_BARRIER): New. ++ (TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New. ++ * config/arm/arm.md: Include sync.md. ++ (UNSPEC_MEMORY_BARRIER): New. ++ (VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New. ++ (VUNSPEC_SYNC_OP):New. ++ (VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New. ++ (sync_result, sync_memory, sync_required_value): New attributes. ++ (sync_new_value, sync_t1, sync_t2): Likewise. ++ (sync_release_barrier, sync_op): Likewise. ++ (length): Add logic to length attribute defintion to call ++ arm_sync_loop_insns when appropriate. ++ * config/arm/sync.md: New file. ++ ++ 2010-09-02 Marcus Shawcroft ++ ++ gcc/ ++ * config/arm/predicates.md (arm_sync_memory_operand): New. ++ * config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate ++ to arm_sync_memory_operand and constraint to Q. ++ (arm_sync_compare_and_swap): Likewise. ++ (arm_sync_compare_and_swap): Likewise. ++ (arm_sync_lock_test_and_setsi): Likewise. ++ (arm_sync_lock_test_and_set): Likewise. ++ (arm_sync_new_si): Likewise. ++ (arm_sync_new_nandsi): Likewise. ++ (arm_sync_new_): Likewise. ++ (arm_sync_new_nand): Likewise. ++ (arm_sync_old_si): Likewise. ++ (arm_sync_old_nandsi): Likewise. ++ (arm_sync_old_): Likewise. ++ (arm_sync_old_nand): Likewise. ++ ++ 2010-09-13 Marcus Shawcroft ++ ++ gcc/ ++ * config/arm/arm.md: (define_attr "conds"): Update comment. ++ * config/arm/sync.md (arm_sync_compare_and_swapsi): Change ++ conds attribute to clob. ++ (arm_sync_compare_and_swapsi): Likewise. ++ (arm_sync_compare_and_swap): Likewise. ++ (arm_sync_lock_test_and_setsi): Likewise. ++ (arm_sync_lock_test_and_set): Likewise. ++ (arm_sync_new_si): Likewise. ++ (arm_sync_new_nandsi): Likewise. ++ (arm_sync_new_): Likewise. ++ (arm_sync_new_nand): Likewise. ++ (arm_sync_old_si): Likewise. ++ (arm_sync_old_nandsi): Likewise. ++ (arm_sync_old_): Likewise. ++ (arm_sync_old_nand): Likewise. ++ ++ 2010-09-13 Marcus Shawcroft ++ ++ gcc/testsuite/ ++ * gcc.target/arm/sync-1.c: New. ++ ++2010-10-20 Yao Qi ++ ++ Merge from Sourcery G++ to fix LP:660021 ++ 2010-10-18 Paul Brook ++ ++ * tree-vect-stmts.c (supportable_widening_operation): Check if wide ++ vector type exists. ++ ++2010-10-15 Jie Zhang ++ ++ Backport from mainline: ++ ++ gcc/testsuite/ ++ 2010-10-15 Jie Zhang ++ ++ * lib/lto.exp (lto-link-and-maybe-run): Use the default linker ++ script when relocatable linking. ++ ++2010-10-15 Chung-Lin Tang ++ ++ Backport from mainline: ++ ++ 2010-10-15 Chung-Lin Tang ++ ++ gcc/ ++ * ifcvt.c (find_active_insn_before): New function. ++ (find_active_insn_after): New function. ++ (cond_exec_process_if_block): Use new functions to replace ++ prev_active_insn() and next_active_insn(). ++ ++ gcc/testsuite/ ++ * gcc.dg/20101010-1.c: New testcase. ++ ++2010-10-13 Chung-Lin Tang ++ ++ Issue #8615 ++ ++ Backport from mainline: ++ ++ 2010-10-12 Chung-Lin Tang ++ ++ gcc/ ++ * config/arm/arm.h (ARM_EXPAND_ALIGNMENT): Rename from ++ DATA_ALIGNMENT and add COND parameter. Update comments above. ++ (DATA_ALIGNMENT): Use ARM_EXPAND_ALIGNMENT, with !optimize_size. ++ (LOCAL_ALIGNMENT): Use ARM_EXPAND_ALIGNMENT, with ++ !flag_conserve_stack. ++ ++2010-10-15 Yao Qi ++ ++ Backport from mainline: ++ ++ 2010-10-14 Yao Qi ++ ++ gcc/ ++ PR target/45447 ++ * config/arm/arm.c (arm_build_builtin_va_list): Assign ++ va_list_name to TYPE_STUB_DECL (va_list_type). ++ ++ gcc/testsuite/ ++ PR target/45447 ++ * gcc.target/arm/pr45447.c: New test. ++ ++2010-10-13 Chung-Lin Tang ++ ++ Backport from mainline: ++ ++ 2010-04-20 James E. Wilson ++ ++ gcc/ ++ PR rtl-optimization/43520 ++ * ira-lives.c (ira_implicitly_set_insn_hard_regs): Exclude classes with ++ zero available registers. ++ ++2010-10-09 Jie Zhang ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-06-03 Paul Brook ++ * config/arm/arm.c (FL_TUNE): Define. ++ (arm_default_cpu, arm_cpu_select): Remove. ++ (all_cores): Populate core field. ++ (arm_selected_arch, arm_selected_cpu, arm_selected_tune): New. ++ (arm_find_cpu): New function. ++ (arm_handle_option): Lookup cpu/architecture names. ++ (arm_override_options): Cleanup mcpu/march/mtune handling. ++ (arm_file_start): Ditto. ++ ++2010-10-08 Jie Zhang ++ ++ * config/arm/arm.c (arm_override_options): Disable ++ -fsched-interblock for Cortex-M4. ++ ++2010-10-06 Julian Brown ++ ++ gcc/testsuite/ ++ * gcc.dg/Warray-bounds-3.c: Add -fno-unroll-loops for ARM. ++ * gcc.dg/vect/vect.exp: Likewise, for all vect tests. ++ ++2010-09-30 Jie Zhang ++ ++ gcc/testsuite/ ++ * gcc.target/arm/neon-thumb2-move.c: Add ++ dg-require-effective-target arm_thumb2_ok. ++ ++2010-10-01 Julian Brown ++ ++ Revert: ++ ++ Backport from FSF: ++ ++ gcc/ ++ 2010-08-18 Marcus Shawcroft ++ * config/arm/arm-protos.h (arm_expand_sync): New. ++ (arm_output_memory_barrier, arm_output_sync_insn): New. ++ (arm_sync_loop_insns): New. ++ * config/arm/arm.c (FL_ARCH7): New. ++ (FL_FOR_ARCH7): Include FL_ARCH7. ++ (arm_arch7): New. ++ (arm_print_operand): Support %C markup. ++ (arm_legitimize_sync_memory): New. ++ (arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New. ++ (arm_process_output_memory_barrier, arm_output_memory_barrier): New. ++ (arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New. ++ (arm_output_op2, arm_output_op3, arm_output_sync_loop): New. ++ (arm_get_sync_operand, FETCH_SYNC_OPERAND): New. ++ (arm_process_output_sync_insn, arm_output_sync_insn): New. ++ (arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New. ++ * config/arm/arm.h (struct arm_sync_generator): New. ++ (TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New. ++ (TARGET_HAVE_MEMORY_BARRIER): New. ++ (TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New. ++ * config/arm/arm.md: Include sync.md. ++ (UNSPEC_MEMORY_BARRIER): New. ++ (VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New. ++ (VUNSPEC_SYNC_OP):New. ++ (VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New. ++ (sync_result, sync_memory, sync_required_value): New attributes. ++ (sync_new_value, sync_t1, sync_t2): Likewise. ++ (sync_release_barrier, sync_op): Likewise. ++ (length): Add logic to length attribute defintion to call ++ arm_sync_loop_insns when appropriate. ++ * config/arm/sync.md: New file. ++ ++ gcc/ ++ 2010-09-02 Marcus Shawcroft ++ * config/arm/predicates.md (arm_sync_memory_operand): New. ++ * config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate ++ to arm_sync_memory_operand and constraint to Q. ++ (arm_sync_compare_and_swap): Likewise. ++ (arm_sync_compare_and_swap): Likewise. ++ (arm_sync_lock_test_and_setsi): Likewise. ++ (arm_sync_lock_test_and_set): Likewise. ++ (arm_sync_new_si): Likewise. ++ (arm_sync_new_nandsi): Likewise. ++ (arm_sync_new_): Likewise. ++ (arm_sync_new_nand): Likewise. ++ (arm_sync_old_si): Likewise. ++ (arm_sync_old_nandsi): Likewise. ++ (arm_sync_old_): Likewise. ++ (arm_sync_old_nand): Likewise. ++ ++2010-09-30 Jie Zhang ++ ++ gcc/testsuite/ ++ ++ * c-c++-common/uninit-17.c: Adjust warning message. ++ ++ Backport from mainline: ++ ++ 2010-07-30 Xinliang David Li ++ PR tree-optimization/45121 ++ * c-c++-common/uninit-17.c: Add -fno-ivops option. ++ ++2010-09-28 Jie Zhang ++ ++ Backport from mainline: ++ ++ gcc/testsuite/ ++ 2010-09-28 Jie Zhang ++ * gcc.dg/Wcxx-compat-12.c: Add -fno-short-enums. ++ ++2010-09-22 Chung-Lin Tang ++ ++ Backport from mainline: ++ ++ 2010-09-22 Chung-Lin Tang ++ ++ gcc/ ++ * postreload.c (move2add_note_store): Add reg_symbol_ref[] checks ++ to update conditions. Fix reg_mode[] check. ++ ++2010-09-20 Jie Zhang ++ ++ Issue #9019 ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-09-20 Jie Zhang ++ * config/arm/arm.c (arm_address_offset_is_imm): New. ++ (arm_early_store_addr_dep): New. ++ (arm_early_load_addr_dep): New. ++ * config/arm/arm-protos.h (arm_early_store_addr_dep): Declare. ++ (arm_early_load_addr_dep): Declare. ++ (arm_address_offset_is_imm): Declare. ++ * config/arm/cortex-m4.md: New file. ++ * config/arm/cortex-m4-fpu.md: New file. ++ * config/arm/arm.md: Include cortex-m4.md and cortex-m4-fpu.md. ++ (attr generic_sched): Exclude cortexm4. ++ (attr generic_vfp): Exclude cortexm4. ++ ++2010-09-20 Jie Zhang ++ ++ Issue #5256 ++ ++ libstdc++-v3/ ++ ++ Backport from mainline: ++ ++ 2010-05-21 Joseph Myers ++ * acinclude.m4 (GLIBCXX_ENABLE_CLOCALE): Use GNU locale model for ++ glibc 2.3 and later, but not uClibc, without an execution test. ++ * configure: Regenerate. ++ * doc/xml/manual/configure.xml, doc/xml/manual/prerequisites.xml, ++ doc/xml/faq.xml: Update. ++ ++2010-09-17 Chung-Lin Tang ++ ++ Backport from mainline: ++ ++ 2010-07-15 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (last_label_ruid, first_index_reg, last_index_reg): ++ New static variables. ++ (reload_combine_recognize_pattern): New static function, broken out ++ of reload_combine. ++ (reload_combine): Use it. Only initialize first_index_reg and ++ last_index_reg once. ++ ++ 2010-07-17 Bernd Schmidt ++ ++ PR target/42235 ++ gcc/ ++ * postreload.c (reload_cse_move2add): Return bool, true if anything. ++ changed. All callers changed. ++ (move2add_use_add2_insn): Likewise. ++ (move2add_use_add3_insn): Likewise. ++ (reload_cse_regs): If reload_cse_move2add changed anything, rerun ++ reload_combine. ++ (RELOAD_COMBINE_MAX_USES): Bump to 16. ++ (last_jump_ruid): New static variable. ++ (struct reg_use): New members CONTAINING_MEM and RUID. ++ (reg_state): New members ALL_OFFSETS_MATCH and REAL_STORE_RUID. ++ (reload_combine_split_one_ruid, reload_combine_split_ruids, ++ reload_combine_purge_insn_uses, reload_combine_closest_single_use ++ reload_combine_purge_reg_uses_after_ruid, ++ reload_combine_recognize_const_pattern): New static functions. ++ (reload_combine_recognize_pattern): Verify that ALL_OFFSETS_MATCH ++ is true for our reg and that we have available index regs. ++ (reload_combine_note_use): New args RUID and CONTAINING_MEM. All ++ callers changed. Use them to initialize fields in struct reg_use. ++ (reload_combine): Initialize last_jump_ruid. Be careful when to ++ take PREV_INSN of the scanned insn. Update REAL_STORE_RUID fields. ++ Call reload_combine_recognize_const_pattern. ++ (reload_combine_note_store): Update REAL_STORE_RUID field. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/pr42235.c: New test. ++ ++ 2010-07-19 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (reload_combine_closest_single_use): Ignore the ++ number of uses for DEBUG_INSNs. ++ (fixup_debug_insns): New static function. ++ (reload_combine_recognize_const_pattern): Use it. Don't let the ++ main loop be affected by DEBUG_INSNs. ++ Really disallow moving adds past a jump insn. ++ (reload_combine_recognize_pattern): Don't update use_ruid here. ++ (reload_combine_note_use): Do it here. ++ (reload_combine): Use control_flow_insn_p rather than JUMP_P. ++ ++ 2010-07-20 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (fixup_debug_insns): Remove arg REGNO. New args ++ FROM and TO. All callers changed. Don't look for tracked uses, ++ just scan the RTL for DEBUG_INSNs and substitute. ++ (reload_combine_recognize_pattern): Call fixup_debug_insns. ++ (reload_combine): Ignore DEBUG_INSNs. ++ ++ 2010-07-22 Bernd Schmidt ++ ++ PR bootstrap/44970 ++ PR middle-end/45009 ++ gcc/ ++ * postreload.c: Include "target.h". ++ (reload_combine_closest_single_use): Don't take DEBUG_INSNs ++ into account. ++ (fixup_debug_insns): Don't copy the rtx. ++ (reload_combine_recognize_const_pattern): DEBUG_INSNs can't have uses. ++ Don't copy when replacing. Call fixup_debug_insns in the case where ++ we merged one add with another. ++ (reload_combine_recognize_pattern): Fail if there aren't any uses. ++ Try harder to determine whether we're picking a valid index register. ++ Don't set store_ruid for an insn we're going to scan in the ++ next iteration. ++ (reload_combine): Remove unused code. ++ (reload_combine_note_use): When updating use information for ++ an old insn, ignore a use that occurs after store_ruid. ++ * Makefile.in (postreload.o): Update dependencies. ++ ++ 2010-07-27 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (reload_combine_recognize_const_pattern): Move test ++ for limiting the insn movement to the right scope. ++ ++ 2010-07-27 Bernd Schmidt ++ ++ gcc/ ++ * postreload.c (try_replace_in_use): New static function. ++ (reload_combine_recognize_const_pattern): Use it here. Allow ++ substituting into a final add insn, and substituting into a memory ++ reference in an insn that sets the reg. ++ ++2010-10-12 Michael Hope ++ ++ gcc/ ++ * REVISION: Bump version. ++ ++2010-10-12 Michael Hope ++ ++ GCC Linaro 4.5-2010.10-0 released. ++ ++ gcc/ ++ * REVISION: Update. ++ ++2010-10-04 Michael Hope ++ ++ Merge from FSF 4.5 branch r164911 (pre 4.5.2) ++ ++2010-09-21 Yao Qi ++ ++ Backport from FSF to fix ICE found in LP:635409: ++ ++ 2010-07-07 Bernd Schmidt ++ ++ gcc/ ++ PR rtl-optimization/44787 ++ * config/arm/arm.md (arith_shiftsi): Allow stack pointer in operand 2. ++ * config/arm/thumb2.md (thumb2_arith_shiftsi): Likewise. ++ ++ gcc/testsuite/ ++ PR rtl-optimization/44787 ++ * gcc.c-torture/compile/pr44788.c: New test. ++ * gcc.target/arm/pr44788.c: New test. ++ ++2010-09-16 Andrew Stubbs ++ ++ Backport from FSF: ++ ++ 2010-09-01 Ramana Radhakrishnan ++ ++ * config/arm/neon-schedgen.ml (core): New type. ++ (allCores): List of supported cores. ++ (availability_table): Add supported cores. ++ (collate_bypasses): Accept core as a parameter. ++ (worst_case_latencies_and_bypasses): Accept core as a ++ parameter. ++ (emit_insn_reservations): Accept core as a parameter. ++ Use tuneStr and coreStr to get tune attribute and prefix ++ for functional units. ++ (emit_bypasses): Accept core name and use it. ++ (calculate_per_core_availability_table): New. ++ (filter_core): New. ++ (calculate_core_availability_table): New. ++ (main): Use calculate_core_availablity_table. ++ * config/arm/cortex-a8-neon.md: Update copyright year. ++ Regenerated from ml file and merged in. ++ (neon_mrrc, neon_mrc): Rename to cortex_a8_neon_mrrc and ++ cortex_a8_neon_mrc. ++ ++ 2010-09-10 Ramana Radhakrishnan ++ ++ * config/arm/neon-schedgen.ml (allCores): Add support for ++ Cortex-A9. ++ * config/arm/cortex-a9-neon.md: New and partially generated. ++ * config/arm/cortex-a9.md (cortex_a9_dp): Adjust for Neon. ++ ++2010-09-15 Chung-Lin Tang ++ ++ Issue #9441 ++ ++ Backport from mainline: ++ ++ 2010-06-25 Bernd Schmidt ++ ++ With large parts from Jim Wilson: ++ PR target/43902 ++ ++ gcc/ ++ * tree-pretty-print.c (dump_generic_node, op_code_prio): Add ++ WIDEN_MULT_PLUS_EXPR and WIDEN_MULT_MINUS_EXPR. ++ * optabs.c (optab_for_tree_code): Likewise. ++ (expand_widen_pattern_expr): Likewise. ++ * tree-ssa-math-opts.c (convert_mult_to_widen): New function, broken ++ out of execute_optimize_widening_mul. ++ (convert_plusminus_to_widen): New function. ++ (execute_optimize_widening_mul): Use the two new functions. ++ * expr.c (expand_expr_real_2): Add support for GIMPLE_TERNARY_RHS. ++ Remove code to generate widening multiply-accumulate. Add support ++ for WIDEN_MULT_PLUS_EXPR and WIDEN_MULT_MINUS_EXPR. ++ * gimple-pretty-print.c (dump_ternary_rhs): New function. ++ (dump_gimple_assign): Call it when appropriate. ++ * tree.def (WIDEN_MULT_PLUS_EXPR, WIDEN_MULT_MINUS_EXPR): New codes. ++ * cfgexpand.c (gimple_assign_rhs_to_tree): Likewise. ++ (expand_gimple_stmt_1): Likewise. ++ (expand_debug_expr): Support WIDEN_MULT_PLUS_EXPR and ++ WIDEN_MULT_MINUS_EXPR. ++ * tree-ssa-operands.c (get_expr_operands): Likewise. ++ * tree-inline.c (estimate_operator_cost): Likewise. ++ * gimple.c (extract_ops_from_tree_1): Renamed from ++ extract_ops_from_tree. Add new arg for a third operand; fill it. ++ (gimple_build_assign_stat): Support operations with three operands. ++ (gimple_build_assign_with_ops_stat): Likewise. ++ (gimple_assign_set_rhs_from_tree): Likewise. ++ (gimple_assign_set_rhs_with_ops_1): Renamed from ++ gimple_assign_set_rhs_with_ops. Add new arg for a third operand. ++ (get_gimple_rhs_num_ops): Support GIMPLE_TERNARY_RHS. ++ (get_gimple_rhs_num_ops): Handle WIDEN_MULT_PLUS_EXPR and ++ WIDEN_MULT_MINUS_EXPR. ++ * gimple.h (enum gimple_rhs_class): Add GIMPLE_TERNARY_RHS. ++ (extract_ops_from_tree_1): Adjust declaration. ++ (gimple_assign_set_rhs_with_ops_1): Likewise. ++ (gimple_build_assign_with_ops): Pass NULL for last operand. ++ (gimple_build_assign_with_ops3): New macro. ++ (gimple_assign_rhs3, gimple_assign_rhs3_ptr, gimple_assign_set_rhs3, ++ gimple_assign_set_rhs_with_ops, extract_ops_from_tree): New inline ++ functions. ++ * tree-cfg.c (verify_gimple_assign_ternary): New static function. ++ (verify_gimple_assign): Call it. ++ * doc/gimple.texi (Manipulating operands): Document GIMPLE_TERNARY_RHS. ++ (Tuple specific accessors, subsection GIMPLE_ASSIGN): Document new ++ functions for dealing with three-operand statements. ++ * tree.c (commutative_ternary_tree_code): New function. ++ * tree.h (commutative_ternary_tree_code): Declare it. ++ * tree-vrp.c (gimple_assign_nonnegative_warnv_p): Return false for ++ ternary statements. ++ (gimple_assign_nonzero_warnv_p): Likewise. ++ * tree-ssa-sccvn.c (stmt_has_constants): Handle GIMPLE_TERNARY_RHS. ++ * tree-ssa-ccp.c (get_rhs_assign_op_for_ccp): New static function. ++ (ccp_fold): Use it. Handle GIMPLE_TERNARY_RHS. ++ * tree-ssa-dom.c (enum expr_kind): Add EXPR_TERNARY. ++ (struct hashtable_expr): New member ternary in the union. ++ (initialize_hash_element): Handle GIMPLE_TERNARY_RHS. ++ (hashable_expr_equal_p): Fix indentation. Handle EXPR_TERNARY. ++ (iterative_hash_hashable_expr): Likewise. ++ (print_expr_hash_elt): Handle EXPR_TERNARY. ++ * gimple-fold.c (fold_gimple_assign): Handle GIMPLE_TERNARY_RHS. ++ * tree-ssa-threadedge.c (fold_assignment_stmt): Remove useless break ++ statements. Handle GIMPLE_TERNARY_RHS. ++ ++ From Jim Wilson: ++ gcc/testsuite/ ++ * gcc.target/mips/madd-9.c: New test. ++ ++ 2010-06-29 Bernd Schmidt ++ ++ PR target/43902 ++ gcc/ ++ * config/arm/arm.md (maddsidi4, umaddsidi4): New expanders. ++ (maddhisi4): Renamed from mulhisi3addsi. Operands renumbered. ++ (maddhidi4): Likewise. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/wmul-1.c: Test for smlabb instead of smulbb. ++ * gcc.target/arm/wmul-3.c: New test. ++ * gcc.target/arm/wmul-4.c: New test. ++ ++ 2010-07-22 Richard Sandiford ++ ++ gcc/ ++ * tree-ssa-math-opts.c (is_widening_mult_rhs_p): New function. ++ (is_widening_mult_p): Likewise. ++ (convert_to_widen): Use them. ++ (convert_plusminus_to_widen): Likewise. Handle fixed-point types as ++ well as integer ones. ++ ++ 2010-07-31 Richard Sandiford ++ ++ gcc/ ++ * tree-ssa-math-opts.c (convert_plusminus_to_widen): Fix type ++ used in the call to optab_for_tree_code. Fix the second ++ is_widening_mult_p call. Check that both unwidened operands ++ have the same sign. ++ ++2010-09-15 Jie Zhang ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-09-15 Jie Zhang ++ * config/arm/vfp.md (cmpsf_trap_vfp): Change type from ++ fcmpd to fcmps. ++ ++2010-09-13 Chung-Lin Tang ++ ++ Backport from mainline: ++ ++ 2010-09-12 Bernd Schmidt ++ ++ gcc/ ++ * config/arm/arm.md (arm_ashldi3_1bit, arm_ashrdi3_1bit, ++ arm_lshrdi3_1bit): Put earlyclobber on the right alternative. ++ ++2010-09-10 Nathan Froyd ++ ++ Issue #9120 ++ ++ gcc/ ++ * gimple.c (is_gimple_min_invariant): Check for constant INDIRECT_REFs. ++ ++2010-09-08 Tom de Vries ++ ++ gcc/ ++ * gcc/emit-rtl.c (set_mem_attributes_minus_bitpos): Set MEM_READONLY_P ++ for static const strings. ++ * gcc/testsuite/gcc.dg/memcpy-3.c: New test. ++ ++2010-09-13 Andrew Stubbs ++ ++ gcc/ ++ * REVISION: Bump version. ++ ++2010-09-13 Andrew Stubbs ++ ++ GCC Linaro 4.5-2010.09-1 released. ++ ++ gcc/ ++ * REVISION: Update. ++ ++2010-09-13 Andrew Stubbs ++ ++ Backport from FSF: ++ ++ 2010-09-13 Marcus Shawcroft ++ ++ * config/arm/arm.md: (define_attr "conds"): Update comment. ++ * config/arm/sync.md (arm_sync_compare_and_swapsi): Change ++ conds attribute to clob. ++ (arm_sync_compare_and_swapsi): Likewise. ++ (arm_sync_compare_and_swap): Likewise. ++ (arm_sync_lock_test_and_setsi): Likewise. ++ (arm_sync_lock_test_and_set): Likewise. ++ (arm_sync_new_si): Likewise. ++ (arm_sync_new_nandsi): Likewise. ++ (arm_sync_new_): Likewise. ++ (arm_sync_new_nand): Likewise. ++ (arm_sync_old_si): Likewise. ++ (arm_sync_old_nandsi): Likewise. ++ (arm_sync_old_): Likewise. ++ (arm_sync_old_nand): Likewise. ++ ++ 2010-09-13 Marcus Shawcroft ++ ++ * gcc.target/arm/sync-1.c: New. ++ ++2010-09-10 Andrew Stubbs ++ ++ gcc/ ++ * REVISION: Bump version. ++ ++2010-09-10 Andrew Stubbs ++ ++ GCC Linaro 4.5-2010.09-0 released. ++ ++ gcc/ ++ * REVISION: Update. ++ ++2010-09-09 Andrew Stubbs ++ ++ 2010-09-02 Marcus Shawcroft ++ * config/arm/predicates.md (arm_sync_memory_operand): New. ++ * config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate ++ to arm_sync_memory_operand and constraint to Q. ++ (arm_sync_compare_and_swap): Likewise. ++ (arm_sync_compare_and_swap): Likewise. ++ (arm_sync_lock_test_and_setsi): Likewise. ++ (arm_sync_lock_test_and_set): Likewise. ++ (arm_sync_new_si): Likewise. ++ (arm_sync_new_nandsi): Likewise. ++ (arm_sync_new_): Likewise. ++ (arm_sync_new_nand): Likewise. ++ (arm_sync_old_si): Likewise. ++ (arm_sync_old_nandsi): Likewise. ++ (arm_sync_old_): Likewise. ++ (arm_sync_old_nand): Likewise. ++ ++2010-09-09 Andrew Stubbs ++ ++ Backport from mainline: ++ ++ 2010-08-18 Marcus Shawcroft ++ * config/arm/arm-protos.h (arm_expand_sync): New. ++ (arm_output_memory_barrier, arm_output_sync_insn): New. ++ (arm_sync_loop_insns): New. ++ * config/arm/arm.c (FL_ARCH7): New. ++ (FL_FOR_ARCH7): Include FL_ARCH7. ++ (arm_arch7): New. ++ (arm_print_operand): Support %C markup. ++ (arm_legitimize_sync_memory): New. ++ (arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New. ++ (arm_process_output_memory_barrier, arm_output_memory_barrier): New. ++ (arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New. ++ (arm_output_op2, arm_output_op3, arm_output_sync_loop): New. ++ (arm_get_sync_operand, FETCH_SYNC_OPERAND): New. ++ (arm_process_output_sync_insn, arm_output_sync_insn): New. ++ (arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New. ++ * config/arm/arm.h (struct arm_sync_generator): New. ++ (TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New. ++ (TARGET_HAVE_MEMORY_BARRIER): New. ++ (TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New. ++ * config/arm/arm.md: Include sync.md. ++ (UNSPEC_MEMORY_BARRIER): New. ++ (VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New. ++ (VUNSPEC_SYNC_OP):New. ++ (VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New. ++ (sync_result, sync_memory, sync_required_value): New attributes. ++ (sync_new_value, sync_t1, sync_t2): Likewise. ++ (sync_release_barrier, sync_op): Likewise. ++ (length): Add logic to length attribute defintion to call ++ arm_sync_loop_insns when appropriate. ++ * config/arm/sync.md: New file. ++ ++2010-09-09 Andrew Stubbs ++ ++ Backport from mainline: ++ ++ 2010-08-25 Tejas Belagod ++ * config/arm/iterators.md (VU, SE, V_widen_l): New. ++ (V_unpack, US): New. ++ * config/arm/neon.md (vec_unpack_hi_): Expansion for ++ vmovl. ++ (vec_unpack_lo_): Likewise. ++ (neon_vec_unpack_hi_): Instruction pattern for vmovl. ++ (neon_vec_unpack_lo_): Likewise. ++ (vec_widen_mult_lo_): Expansion for vmull. ++ (vec_widen_mult_hi_): Likewise. ++ (neon_vec_mult_lo_"): Instruction pattern for vmull. ++ (neon_vec_mult_hi_"): Likewise. ++ (neon_unpack_): Widening move intermediate step for ++ vectorizing without -mvectorize-with-neon-quad. ++ (neon_vec_mult_): Widening multiply intermediate step ++ for vectorizing without -mvectorize-with-neon-quad. ++ * config/arm/predicates.md (vect_par_constant_high): Check for ++ high-half lanes of a vector. ++ (vect_par_constant_low): Check for low-half lanes of a vector. ++ ++ 2010-08-25 Tejas Belagod ++ * lib/target-supports.exp (check_effective_target_vect_unpack): ++ Set vect_unpack supported flag to true for neon. ++ ++2010-09-07 Andrew Stubbs ++ ++ Backport from gcc-patches: ++ http://gcc.gnu.org/ml/gcc-patches/2010-06/msg00658.html ++ ++ gcc/ ++ 2010-06-07 Matthias Klose ++ PR bootstrap/43847 ++ * configure.ac (--enable-plugin): Enhance for cross builds. ++ * configure: Regenerate. ++ ++2010-09-06 Mark Mitchell ++ ++ Issue #9022 ++ ++ Backport from mainline: ++ 2010-09-05 Mark Mitchell ++ * doc/invoke.texi: Document -Wdouble-promotion. ++ * c-typeck.c (convert_arguments): Check for implicit conversions ++ from float to double. ++ (do_warn_double_promotion): New function. ++ (build_conditional_expr): Use it. ++ (build_binary_op): Likewise. ++ * c.opt (Wdouble-promotion): New. ++ 2010-09-05 Mark Mitchell ++ * gcc.dg/Wdouble-promotion.c: New. ++ 2010-09-06 Mark Mitchell ++ gcc/ ++ * c-common.h (do_warn_double_promotion): Declare. ++ * c-common.c (do_warn_double_promotion): Define. ++ * c-typeck.c (do_warn_double_promotion): Remove. ++ * doc/invoke.texi (-Wdouble-promotion): Note available for C++ and ++ Objective-C++ too. ++ gcc/cp/ ++ * typeck.c (cp_build_binary_op): Call do_warn_double_promotion. ++ * call.c (build_conditional_expr): Likewise. ++ (convert_arg_to_ellipsis): Likewise. ++ gcc/testsuite/ ++ * g++.dg/warn/Wdouble-promotion.C: New. ++ ++2010-08-31 Chung-Lin Tang ++ ++ Backport from mainline: ++ ++ 2010-04-14 Bernd Schmidt ++ ++ PR target/21803 ++ gcc/ ++ * ifcvt.c (cond_exec_process_if_block): Look for identical sequences ++ at the start and end of the then/else blocks, and omit them from the ++ conversion. ++ * cfgcleanup.c (flow_find_cross_jump): No longer static. Remove MODE ++ argument; all callers changed. Pass zero to old_insns_match_p instead. ++ (flow_find_head_matching_sequence): New function. ++ (old_insns_match_p): Check REG_EH_REGION notes for calls. ++ * basic-block.h (flow_find_cross_jump, ++ flow_find_head_matching_sequence): Declare functions. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/pr42496.c: New test. ++ ++ 2010-04-22 Bernd Schmidt ++ ++ PR middle-end/29274 ++ gcc/ ++ * tree-pass.h (pass_optimize_widening_mul): Declare. ++ * tree-ssa-math-opts.c (execute_optimize_widening_mul, ++ gate_optimize_widening_mul): New static functions. ++ (pass_optimize_widening_mul): New. ++ * expr.c (expand_expr_real_2) : New case. ++ : Remove support for widening multiplies. ++ * tree.def (WIDEN_MULT_EXPR): Tweak comment. ++ * cfgexpand.c (expand_debug_expr) : Use ++ simplify_gen_unary rather than directly building extensions. ++ * tree-cfg.c (verify_gimple_assign_binary): Add tests for ++ WIDEN_MULT_EXPR. ++ * expmed.c (expand_widening_mult): New function. ++ * passes.c (init_optimization_passes): Add pass_optimize_widening_mul. ++ * optabs.h (expand_widening_mult): Declare. ++ ++ gcc/testsuite/ ++ * gcc.target/i386/wmul-1.c: New test. ++ * gcc.target/i386/wmul-2.c: New test. ++ * gcc.target/bfin/wmul-1.c: New test. ++ * gcc.target/bfin/wmul-2.c: New test. ++ * gcc.target/arm/wmul-1.c: New test. ++ * gcc.target/arm/wmul-2.c: New test. ++ ++ 2010-04-24 Bernd Schmidt ++ ++ PR tree-optimization/41442 ++ gcc/ ++ * fold-const.c (merge_truthop_with_opposite_arm): New function. ++ (fold_binary_loc): Call it. ++ ++ gcc/testsuite/ ++ * gcc.target/i386/pr41442.c: New test. ++ ++ 2010-04-29 Bernd Schmidt ++ ++ PR target/42895 ++ gcc/ ++ * doc/tm.texi (ADJUST_REG_ALLOC_ORDER): Renamed from ++ ORDER_REGS_FOR_LOCAL_ALLOC. All instances of this macro changed. ++ (HONOR_REG_ALLOC_ORDER): Describe new macro. ++ * ira.c (setup_alloc_regs): Use ADJUST_REG_ALLOC_ORDER if defined. ++ * ira-color.c (assign_hard_reg): Take prologue/epilogue costs into ++ account only if HONOR_REG_ALLOC_ORDER is not defined. ++ * config/arm/arm.h (HONOR_REG_ALLOC_ORDER): Define. ++ * system.h (ORDER_REGS_FOR_LOCAL_ALLOC): Poison. ++ ++ 2010-05-04 Mikael Pettersson ++ ++ PR bootstrap/43964 ++ gcc/ ++ * ira-color.c (assign_hard_reg): Declare rclass and add_cost ++ only if HONOR_REG_ALLOC_ORDER is not defined. ++ ++ 2010-06-04 Bernd Schmidt ++ ++ PR rtl-optimization/39871 ++ PR rtl-optimization/40615 ++ PR rtl-optimization/42500 ++ PR rtl-optimization/42502 ++ gcc/ ++ * ira.c (init_reg_equiv_memory_loc: New function. ++ (ira): Call it twice. ++ * reload.h (calculate_elim_costs_all_insns): Declare. ++ * ira-costs.c: Include "reload.h". ++ (regno_equiv_gains): New static variable. ++ (init_costs): Allocate it. ++ (finish_costs): Free it. ++ (ira_costs): Call calculate_elim_costs_all_insns. ++ (find_costs_and_classes): Take estimated elimination costs ++ into account. ++ (ira_adjust_equiv_reg_cost): New function. ++ * ira.h (ira_adjust_equiv_reg_cost): Declare it. ++ * reload1.c (init_eliminable_invariants, free_reg_equiv, ++ elimination_costs_in_insn, note_reg_elim_costly): New static functions. ++ (elim_bb): New static variable. ++ (reload): Move code out of here into init_eliminable_invariants and ++ free_reg_equiv. Call them. ++ (calculate_elim_costs_all_insns): New function. ++ (eliminate_regs_1): Declare. Add extra arg FOR_COSTS; ++ all callers changed. If FOR_COSTS is true, don't call alter_reg, ++ but call note_reg_elim_costly if we turned a valid memory address ++ into an invalid one. ++ * Makefile.in (ira-costs.o): Depend on reload.h. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/eliminate.c: New test. ++ ++ 2010-06-09 Bernd Schmidt ++ ++ gcc/ ++ * config/arm/arm.c (thumb2_reorg): New function. ++ (arm_reorg): Call it. ++ * config/arm/thumb2.md (define_peephole2 for flag clobbering ++ arithmetic operations): Delete. ++ ++ 2010-06-12 Bernd Schmidt ++ ++ gcc/ ++ * config/arm/arm.c (thumb2_reorg): Fix errors in previous change. ++ ++ 2010-06-17 Bernd Schmidt ++ ++ PR rtl-optimization/39871 ++ gcc/ ++ * reload1.c (init_eliminable_invariants): For flag_pic, disable ++ equivalences only for constants that aren't LEGITIMATE_PIC_OPERAND_P. ++ (function_invariant_p): Rule out a plus of frame or arg pointer with ++ a SYMBOL_REF. ++ * ira.c (find_reg_equiv_invariant_const): Likewise. ++ ++ 2010-06-18 Eric Botcazou ++ ++ PR rtl-optimization/40900 ++ gcc/ ++ * expr.c (expand_expr_real_1) : Fix long line. Save the ++ original expression for later reuse. ++ : Use promote_function_mode to compute the signedness ++ of the promoted RTL for a SSA_NAME on the LHS of a call statement. ++ ++ 2010-06-18 Bernd Schmidt ++ gcc/testsuite/ ++ * gcc.target/arm/pr40900.c: New test. ++ ++ 2010-06-30 Bernd Schmidt ++ ++ PR tree-optimization/39799 ++ gcc/ ++ * tree-inline.c (remap_ssa_name): Initialize variable only if ++ SSA_NAME_OCCURS_IN_ABNORMAL_PHI. ++ * tree-ssa.c (warn_uninit): Avoid emitting an unnecessary message. ++ ++ gcc/testsuite/ ++ * c-c++-common/uninit-17.c: New test. ++ ++ 2010-07-25 Eric Botcazou ++ ++ PR target/44484 ++ gcc/ ++ * config/sparc/predicates.md (memory_reg_operand): Delete. ++ * config/sparc/sync.md (sync_compare_and_swap): Minor tweaks. ++ (*sync_compare_and_swap): Encode the address form in the pattern. ++ (*sync_compare_and_swapdi_v8plus): Likewise. ++ ++2010-08-29 Chung-Lin Tang ++ ++ Backport from mainline: ++ ++ 2010-04-16 Bernd Schmidt ++ ++ PR target/41514 ++ gcc/ ++ * config/arm/arm.md (cbranchsi4_insn): Renamed from "*cbranchsi4_insn". ++ If the previous insn is a cbranchsi4_insn with the same arguments, ++ omit the compare instruction. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/thumb-comparisons.c: New test. ++ ++ gcc/ ++ * config/arm/arm.md (addsi3_cbranch): If destination is a high ++ register, inputs must be low registers and we need a low register ++ scratch. Handle alternative 2 like alternative 3. ++ ++ PR target/40603 ++ gcc/ ++ * config/arm/arm.md (cbranchqi4): New pattern. ++ * config/arm/predicates.md (const0_operand, ++ cbranchqi4_comparison_operator): New predicates. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/thumb-cbranchqi.c: New test. ++ ++ 2010-04-27 Bernd Schmidt ++ ++ PR target/40657 ++ gcc/ ++ * config/arm/arm.c (thumb1_extra_regs_pushed): New function. ++ (thumb1_expand_prologue, thumb1_output_function_prologue): Call it ++ here to determine which regs to push and how much stack to reserve. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/thumb-stackframe.c: New test. ++ ++ 2010-07-02 Bernd Schmidt ++ ++ PR target/42835 ++ gcc/ ++ * config/arm/arm-modes.def (CC_NOTB): New mode. ++ * config/arm/arm.c (get_arm_condition_code): Handle it. ++ * config/arm/thumb2.md (thumb2_compare_scc): Delete pattern. ++ * config/arm/arm.md (subsi3_compare0_c): New pattern. ++ (compare_scc): Now a define_and_split. Add a number of extra ++ splitters before it. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/pr42835.c: New test. ++ ++ PR target/42172 ++ gcc/ ++ * config/arm/arm.c (thumb1_rtx_costs): Improve support for SIGN_EXTEND ++ and ZERO_EXTEND. ++ (arm_rtx_costs_1): Likewise. ++ (arm_size_rtx_costs): Use arm_rtx_costs_1 for these codes. ++ * config/arm/arm.md (is_arch6): New attribute. ++ (zero_extendhisi2, zero_extendqisi2, extendhisi2, ++ extendqisi2): Tighten the code somewhat, avoiding invalid ++ RTL to occur in the expander patterns. ++ (thumb1_zero_extendhisi2): Merge with thumb1_zero_extendhisi2_v6. ++ (thumb1_zero_extendhisi2_v6): Delete. ++ (thumb1_extendhisi2): Merge with thumb1_extendhisi2_v6. ++ (thumb1_extendhisi2_v6): Delete. ++ (thumb1_extendqisi2): Merge with thumb1_extendhisi2_v6. ++ (thumb1_extendqisi2_v6): Delete. ++ (zero_extendhisi2 for register input splitter): New. ++ (zero_extendqisi2 for register input splitter): New. ++ (thumb1_extendhisi2 for register input splitter): New. ++ (extendhisi2 for register input splitter): New. ++ (extendqisi2 for register input splitter): New. ++ (TARGET_THUMB1 extendqisi2 for memory input splitter): New. ++ (arm_zero_extendhisi2): Allow nonimmediate_operand for operand 1, ++ and add support for a register alternative requiring a split. ++ (thumb1_zero_extendqisi2): Likewise. ++ (arm_zero_extendqisi2): Likewise. ++ (arm_extendhisi2): Likewise. ++ (arm_extendqisi2): Likewise. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/pr42172-1.c: New test. ++ ++ 2010-07-05 Bernd Schmidt ++ ++ * config/arm/arm.c (get_arm_condition_code): Remove CC_NOTBmode case. ++ * arm-modes.def (CC_NOTB): Don't define. ++ * config/arm/arm.md (arm_adddi3): Generate canonical RTL. ++ (adddi_sesidi_di, adddi_zesidi_di): Likewise. ++ (LTUGEU): New code_iterator. ++ (cnb, optab): New corresponding code_attrs. ++ (addsi3_carryin_): Renamed from addsi3_carryin. Change pattern ++ to canonical form. Operands 1 and 2 are commutative. Parametrize ++ using LTUGEU. ++ (addsi3_carryin_shift_): Likewise. ++ (addsi3_carryin_alt2_): Renamed from addsi3_carryin_alt2. ++ Operands 1 and 2 are commutative. Parametrize using LTUGEU. ++ (addsi3_carryin_alt1, addsi3_carryin_alt3): Remove. ++ (subsi3_compare): Renamed from subsi3_compare0_c. Change CC_NOTB to ++ CC. ++ (arm_subsi3_insn): Allow constants for operand 0. ++ (compare_scc peephole for eq case): New. ++ (compare_scc splitters): Change CC_NOTB to CC. ++ ++ 2010-07-09 Bernd Schmidt ++ ++ PR target/40657 ++ gcc/ ++ * config/arm/arm.c (thumb1_extra_regs_pushed): New arg FOR_PROLOGUE. ++ All callers changed. ++ Handle the case when we're called for the epilogue. ++ (thumb_unexpanded_epilogue): Use it. ++ (thumb1_expand_epilogue): Likewise. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/pr40657-1.c: New test. ++ * gcc.target/arm/pr40657-2.c: New test. ++ * gcc.c-torture/execute/pr40657.c: New test. ++ ++ gcc/ ++ * config/arm/arm.md (addsi3_cbranch): Switch alternatives 0 and 1. ++ ++ * config/arm/arm.md (Thumb-1 ldrsb peephole): New. ++ ++ * config/arm/arm.md (cbranchqi4): Fix array size. ++ (addsi3_cbranch): Also andle alternative 2 like alternative 3 when ++ calculating length. ++ ++2010-08-27 Paul Brook ++ ++ gcc/ ++ * config/arm/thumb2.md (thumb_andsi_not_shiftsi_si, ++ thumb2_notsi_shiftsi, thumb2_notsi_shiftsi_compare0, ++ thumb2_not_shiftsi_compare0_scratch, thumb2_cmpsi_shiftsi, ++ thumb2_cmpsi_shiftsi_swp, thumb2_cmpsi_neg_shiftsi, ++ thumb2_arith_shiftsi, thumb2_arith_shiftsi_compare0, ++ thumb2_arith_shiftsi_compare0_scratch, thumb2_sub_shiftsi, ++ thumb2_sub_shiftsi_compare0, thumb2_sub_shiftsi_compare0_scratch): ++ Use const_shift_count predicate for "M" constraints. ++ * config/arm/predicates.md (const_shift_operand): Remove. ++ (const_shift_count): New. ++ ++ gcc/testsuite/ ++ * gcc.dg/long-long-shift-1.c: New test. ++ ++2010-08-26 Paul Brook ++ ++ Merge from Sourcery G++ 4.3/4.4: ++ Issue #1510 ++ 2007-04-27 Paul Brook ++ gcc/ ++ * cse.c (cse_process_notes): Make sure PLUS are canonical. ++ ++2010-08-26 Paul Brook ++ ++ Merge from Sourcery G++ 4.3/4.4: ++ 2007-03-30 Paul Brook ++ gcc/ ++ * calls.c (store_one_arg): Check alignment of mode used for save. ++ ++2010-08-26 Maciej Rozycki ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2009-02-17 Andrew Jenner ++ Maciej Rozycki ++ ++ gcc/ ++ * unwind.inc (_Unwind_RaiseException): Use return value of ++ uw_init_context. ++ * unwind-dw2.c (uw_init_context): Make macro an expression instead of ++ a statement. ++ (uw_init_context_1): Add return value. ++ * unwind-sjlj.c (uw_init_context): Add return value. ++ ++2010-08-26 Andrew Stubbs ++ ++ Merge from Ubuntu GCC: ++ ++ GCC bugzilla PR objc/41848. ++ ++ gcc/ ++ * objc/lang-specs.h: Work around ObjC and -fsection-anchors. ++ ++ gcc/testsuite/ ++ * objc/execute/forward-1.x: Update for ARM. ++ ++2010-08-25 Andrew Stubbs ++ ++ Backport from FSF: ++ ++ 2010-08-25 Julian Brown ++ ++ * config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5. ++ * config/arm/arm.md (generic_sched): No for Cortex-A5. ++ (generic_vfp): Likewise. ++ (cortex-a5.md): Include. ++ * config/arm/cortex-a5.md: New. ++ ++2010-08-25 Andrew Stubbs ++ ++ Revert: ++ ++ 2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-04-11 Julian Brown ++ ++ Issue #7326 ++ ++ gcc/ ++ * config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5. ++ * config/arm/arm.md (generic_sched): No for Cortex-A5. ++ (generic_vfp): Likewise. ++ (cortex-a5.md): Include. ++ * config/arm/cortex-a5.md: New. ++ ++2010-08-24 Andrew Stubbs ++ ++ Backport from FSF: ++ ++ 2010-08-07 Ramana Radhakrishnan ++ ++ * config/arm/cortex-a9.md: Rewrite VFP Pipeline description. ++ * config/arm/arm.c (arm_xscale_tune): Initialize sched_adjust_cost. ++ (arm_fastmul_tune,arm_slowmul_tune, arm_9e_tune): Likewise. ++ (arm_adjust_cost): Split into xscale_sched_adjust_cost and a ++ generic part. ++ (cortex_a9_sched_adjust_cost): New function. ++ (xscale_sched_adjust_cost): New function. ++ * config/arm/arm-protos.h (struct tune_params): New field ++ sched_adjust_cost. ++ * config/arm/arm-cores.def: Adjust costs for cortex-a9. ++ ++ 2010-04-17 Richard Earnshaw ++ ++ * arm-protos.h (tune_params): New structure. ++ * arm.c (current_tune): New variable. ++ (arm_constant_limit): Delete. ++ (struct processors): Add pointer to the tune parameters. ++ (arm_slowmul_tune): New tuning option. ++ (arm_fastmul_tune, arm_xscale_tune, arm_9e_tune): Likewise. ++ (all_cores): Adjust to pick up the tuning model. ++ (arm_constant_limit): New function. ++ (arm_override_options): Select the appropriate tuning model. Delete ++ initialization of arm_const_limit. ++ (arm_split_constant): Use the new constant-limit model. ++ (arm_rtx_costs): Pick up the current tuning model. ++ * arm.md (is_strongarm, is_xscale): Delete. ++ * arm-generic.md (load_ldsched_x, load_ldsched): Test explicitly ++ for Xscale variant architectures. ++ (mult_ldsched_strongarm, mult_ldsched): Similarly for StrongARM. ++ ++2010-08-23 Andrew Stubbs ++ ++ Backport from FSF: ++ ++ 2010-08-07 Marcus Shawcroft ++ ++ gcc/ ++ * config/arm/linux-atomic.c (SUBWORD_VAL_CAS): Instantiate with ++ 'unsigned short' and 'unsigned char' instead of 'short' and 'char'. ++ (SUBWORD_BOOL_CAS): Likewise. ++ (SUBWORD_SYNC_OP): Likewise. ++ (SUBWORD_TEST_AND_SET): Likewise. ++ (FETCH_AND_OP_WORD): Parenthesise INF_OP ++ (SUBWORD_SYNC_OP): Likewise. ++ (OP_AND_FETCH_WORD): Likewise. ++ ++ gcc/testsuite/ ++ * lib/target-supports.exp: (check_effective_target_sync_int_long): ++ Add arm*-*-linux-gnueabi. ++ (check_effective_target_sync_char_short): Likewise. ++ ++2010-08-20 Jie Zhang ++ ++ Merged from Sourcery G++ 4.4: ++ ++ gcc/ ++ 2009-05-29 Julian Brown ++ Merged from Sourcery G++ 4.3: ++ * config/arm/arm.md (movsi): Don't split symbol refs here. ++ (define_split): New. ++ ++2010-08-18 Julian Brown ++ ++ Issue #9222 ++ ++ gcc/ ++ * config/arm/neon.md (UNSPEC_VCLE, UNSPEC_VCLT): New constants for ++ unspecs. ++ (vcond, vcondu): New expanders. ++ (neon_vceq, neon_vcge, neon_vcgt): Support ++ comparisons with zero. ++ (neon_vcle, neon_vclt): New patterns. ++ * config/arm/constraints.md (Dz): New constraint. ++ ++2010-08-18 Jie Zhang ++ ++ Backport from mainline: ++ ++ gcc/testsuite/ ++ 2010-08-18 Jie Zhang ++ * gcc.dg/builtin-apply2.c (STACK_ARGUMENTS_SIZE): Define to ++ 20 if __ARM_PCS is defined otherwise 64. ++ (bar): Use STACK_ARGUMENTS_SIZE for the third argument ++ instead of hard coded 64. ++ ++2010-08-13 Jie Zhang ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-08-13 Jie Zhang ++ * config/arm/arm.md (cstoredf4): Only valid when ++ !TARGET_VFP_SINGLE. ++ ++2010-08-12 Jie Zhang ++ ++ Backport from mainline: ++ ++ gcc/testsuite/ ++ 2010-08-12 Jie Zhang ++ * gcc.dg/graphite/interchange-9.c (M): Define to be 111. ++ (N): Likewise. ++ (main): Adjust accordingly. ++ ++2010-08-05 Julian Brown ++ ++ Backport from mainline (candidate patch): ++ ++ gcc/ ++ * expr.c (expand_assignment): Add assertion to prevent emitting null ++ rtx for movmisalign pattern. ++ (expand_expr_real_1): Likewise. ++ * config/arm/arm.c (arm_builtin_support_vector_misalignment): New. ++ (TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): New. Use above. ++ (arm_vector_alignment_reachable): New. ++ (TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE): New. Use above. ++ (neon_vector_mem_operand): Disallow PRE_DEC for misaligned loads. ++ (arm_print_operand): Include alignment qualifier in %A. ++ * config/arm/neon.md (UNSPEC_MISALIGNED_ACCESS): New constant. ++ (movmisalign): New expander. ++ (movmisalign_neon_store, movmisalign_neon_load): New ++ insn patterns. ++ ++ gcc/testsuite/ ++ * gcc.dg/vect/vect-42.c: Use vect_element_align instead of ++ vect_hw_misalign. ++ * gcc.dg/vect/vect-60.c: Likewise. ++ * gcc.dg/vect/vect-56.c: Likewise. ++ * gcc.dg/vect/vect-93.c: Likewise. ++ * gcc.dg/vect/no-scevccp-outer-8.c: Likewise. ++ * gcc.dg/vect/vect-95.c: Likewise. ++ * gcc.dg/vect/vect-96.c: Likewise. ++ * gcc.dg/vect/vect-outer-5.c: Use quad-word vectors when available. ++ * gcc.dg/vect/slp-25.c: Likewise. ++ * gcc.dg/vect/slp-3.c: Likewise. ++ * gcc.dg/vect/vect-multitypes-1.c: Likewise. ++ * gcc.dg/vect/no-vfa-pr29145.c: Likewise. ++ * gcc.dg/vect/vect-multitypes-4.c: Likewise. Use vect_element_align. ++ * gcc.dg/vect/vect-109.c: Likewise. ++ * gcc.dg/vect/vect-peel-1.c: Likewise. ++ * gcc.dg/vect/vect-peel-2.c: Likewise. ++ * lib/target-supports.exp ++ (check_effective_target_arm_vect_no_misalign): New. ++ (check_effective_target_vect_no_align): Use above. ++ (check_effective_target_vect_element_align): New. ++ (add_options_for_quad_vectors): New. ++ ++2010-08-05 Jie Zhang ++ ++ Issue #7257 ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-08-05 Jie Zhang ++ PR tree-optimization/45144 ++ * tree-sra.c (type_consists_of_records_p): Return false ++ if the record contains bit-field. ++ ++ gcc/testsuite/ ++ 2010-08-05 Jie Zhang ++ PR tree-optimization/45144 ++ * gcc.dg/tree-ssa/pr45144.c: New test. ++ ++2010-08-04 Mark Mitchell ++ ++ Backport from mainline: ++ ++ gcc/testsuite/ ++ 2010-08-04 Daniel Gutson ++ * g++.dg/warn/miss-format-1.C: Update line number. ++ ++2010-08-04 Julian Brown ++ ++ gcc/ ++ * config/arm/neon-testgen.ml (regexps): Allow any characters ++ in comments after assembly instructions. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/neon/vfp-shift-a2t2.c: Allow any characters in ++ comments after assembly instructions. ++ * gcc.target/arm/neon/v*.c: Regenerate. ++ ++2010-07-28 Maxim Kuvyrkov ++ ++ Backport code hoisting improvements from mainline: ++ ++ 2010-07-28 Jakub Jelinek ++ PR debug/45105 ++ * gcc.dg/pr45105.c: New test. ++ ++ 2010-07-28 Jakub Jelinek ++ PR debug/45105 ++ * gcse.c (hoist_code): Use FOR_BB_INSNS macro. ++ ++ 2010-07-28 Maxim Kuvyrkov ++ PR rtl-optimization/45107 ++ * gcc.dg/pr45107.c: New test. ++ ++ 2010-07-28 Maxim Kuvyrkov ++ PR rtl-optimization/45107 ++ * gcse.c (hash_scan_set): Use max_distance for gcse-las. ++ ++ 2010-07-28 Maxim Kuvyrkov ++ PR rtl-optimization/45101 ++ * gcc.dg/pr45101.c: New test. ++ ++ 2010-07-28 Maxim Kuvyrkov ++ PR rtl-optimization/45101 ++ * gcse.c (hash_scan_set): Fix argument ordering of insert_expr_in_table ++ for gcse-las. ++ ++ 2010-07-27 Maxim Kuvyrkov ++ PR rtl-optimization/40956 ++ PR target/42495 ++ PR middle-end/42574 ++ * gcc.target/arm/pr40956.c, gcc.target/arm/pr42495.c, ++ * gcc.target/arm/pr42574.c: Add tests. ++ ++ 2010-07-27 Maxim Kuvyrkov ++ * config/arm/arm.c (params.h): Include. ++ (arm_override_options): Tune gcse-unrestricted-cost. ++ * config/arm/t-arm (arm.o): Define dependencies. ++ ++ 2010-07-27 Maxim Kuvyrkov ++ PR target/42495 ++ PR middle-end/42574 ++ * basic-block.h (get_dominated_to_depth): Declare. ++ * dominance.c (get_dominated_to_depth): New function, use ++ get_all_dominated_blocks as a base. ++ (get_all_dominated_blocks): Use get_dominated_to_depth. ++ * gcse.c (occr_t, VEC (occr_t, heap)): Define. ++ (hoist_exprs): Remove. ++ (alloc_code_hoist_mem, free_code_hoist_mem): Update. ++ (compute_code_hoist_vbeinout): Add debug print outs. ++ (hoist_code): Partially rewrite, simplify. Use get_dominated_to_depth. ++ * params.def (PARAM_MAX_HOIST_DEPTH): New parameter to avoid ++ quadratic behavior. ++ * params.h (MAX_HOIST_DEPTH): New macro. ++ * doc/invoke.texi (max-hoist-depth): Document. ++ ++ 2010-07-27 Maxim Kuvyrkov ++ PR rtl-optimization/40956 ++ * config/arm/arm.c (thumb1_size_rtx_costs): Fix cost of simple ++ constants. ++ ++ 2010-07-27 Maxim Kuvyrkov ++ PR target/42495 ++ PR middle-end/42574 ++ * config/arm/arm.c (legitimize_pic_address): Use ++ gen_calculate_pic_address pattern to emit calculation of PIC address. ++ (will_be_in_index_register): New function. ++ (arm_legitimate_address_outer_p, thumb2_legitimate_address_p,) ++ (thumb1_legitimate_address_p): Use it provided !strict_p. ++ * config/arm/arm.md (calculate_pic_address): New expand and split. ++ ++ 2010-07-27 Maxim Kuvyrkov ++ PR target/42495 ++ PR middle-end/42574 ++ * config/arm/arm.c (thumb1_size_rtx_costs): Add cost for "J" constants. ++ * config/arm/arm.md (define_split "J", define_split "K"): Make ++ IRA/reload friendly. ++ ++ 2010-07-27 Maxim Kuvyrkov ++ * gcse.c (insert_insn_end_basic_block): Update signature, remove ++ unused checks. ++ (pre_edge_insert, hoist_code): Update. ++ ++ 2010-07-27 Maxim Kuvyrkov ++ PR target/42495 ++ PR middle-end/42574 ++ * gcse.c (hoist_expr_reaches_here_p): Remove excessive check. ++ ++ 2010-07-27 Maxim Kuvyrkov ++ * gcse.c (hoist_code): Generate new pseudo for every new set insn. ++ ++ 2010-07-27 Maxim Kuvyrkov ++ PR rtl-optimization/40956 ++ PR target/42495 ++ PR middle-end/42574 ++ * gcse.c (compute_code_hoist_vbeinout): Consider more expressions ++ for hoisting. ++ (hoist_code): Count occurences in current block too. ++ ++ 2010-07-27 Maxim Kuvyrkov ++ * gcse.c (struct expr:max_distance): New field. ++ (doing_code_hoisting_p): New static variable. ++ (want_to_gcse_p): Change signature. Allow constrained hoisting of ++ simple expressions, don't change behavior for PRE. Set max_distance. ++ (insert_expr_in_table): Set new max_distance field. ++ (hash_scan_set): Update. ++ (hoist_expr_reaches_here_p): Stop search after max_distance ++ instructions. ++ (find_occr_in_bb): New static function. Use it in ... ++ (hoist_code): Calculate sizes of basic block before any changes are ++ done. Pass max_distance to hoist_expr_reaches_here_p. ++ (one_code_hoisting_pass): Set doing_code_hoisting_p. ++ * params.def (PARAM_GCSE_COST_DISTANCE_RATIO,) ++ (PARAM_GCSE_UNRESTRICTED_COST): New parameters. ++ * params.h (GCSE_COST_DISTANCE_RATIO, GCSE_UNRESTRICTED_COST): New ++ macros. ++ * doc/invoke.texi (gcse-cost-distance-ratio, gcse-unrestricted-cost): ++ Document. ++ ++ 2010-07-27 Jeff Law ++ Maxim Kuvyrkov ++ * gcse.c (compute_transpout, transpout): Remove, move logic ++ to prune_expressions. ++ (compute_pre_data): Move pruning of trapping expressions ... ++ (prune_expressions): ... here. New static function. ++ (compute_code_hoist_data): Use it. ++ (alloc_code_hoist_mem, free_code_hoist_mem, hoist_code): Update. ++ ++ 2010-07-27 Maxim Kuvyrkov ++ * dbgcnt.def (hoist_insn): New debug counter. ++ * gcse.c (hoist_code): Use it. ++ ++2010-07-28 Julian Brown ++ ++ Backport from FSF mainline: ++ ++ gcc/ ++ * config/arm/thumb2.md (*thumb2_movdf_soft_insn): Fix alternatives ++ for pool ranges. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-06-14 Paul Brook ++ ++ Issue #8879 ++ gcc/ ++ * config/arm/arm.c (use_vfp_abi): Add sorry() for Thumb-1 ++ hard-float ABI. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-06-12 Jie Zhang ++ ++ gcc/ ++ * config/arm/vfp.md (arm_movsi_vfp): Set neon_type correctly ++ for neon_ldr and neon_str instructions. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-04-11 Julian Brown ++ ++ Issue #7326 ++ ++ gcc/ ++ * config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5. ++ * config/arm/arm.md (generic_sched): No for Cortex-A5. ++ (generic_vfp): Likewise. ++ (cortex-a5.md): Include. ++ * config/arm/cortex-a5.md: New. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-04-12 Andrew Stubbs ++ ++ Issue #7178 ++ ++ gcc/ ++ * config/arm/arm.c (arm_init_libfuncs): Change __gnu_f2h_ieee to ++ __aeabi_f2h, __gnu_f2h_alternative to __aeabi_f2h_alt, __gnu_h2f_ieee ++ to __aeabi_h2f, and __gnu_h2f_alternative to __aeabi_h2f_alt. ++ * config/arm/fp16.c (__gnu_f2h_internal): Change return type to ++ unsigned int. Change 'sign' variable likewise. ++ (__gnu_h2f_internal): Set to static inline. ++ Change return type to unsigned int. Change 'sign' variable likewise. ++ (ALIAS): New define. ++ (__gnu_f2h_ieee): Change unsigned short to unsigned int. ++ (__gnu_h2f_ieee): Likewise. ++ (__gnu_f2h_alternative): Likewise. ++ (__gnu_h2f_alternative): Likewise. ++ (__aeabi_f2h, __aeabi_h2f): New aliases. ++ (__aeabi_f2h_alt, __aeabi_h2f_alt): Likewise. ++ * config/arm/sfp-machine.h (__extendhfsf2): Set to __aeabi_h2f. ++ (__truncsfhf2): Set to __aeabi_f2h. ++ ++ gcc/testsuite/ ++ * g++.dg/ext/arm-fp16/arm-fp16-ops-5.C: Check for __aeabi_h2f ++ and __aeabi_f2h. ++ * g++.dg/ext/arm-fp16/arm-fp16-ops-6.C: Likewise. ++ * gcc.dg/torture/arm-fp16-ops-5.c: Likewise. ++ * gcc.dg/torture/arm-fp16-ops-6.c: Likewise. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ Richard Earnshaw ++ ++ gcc/ ++ * doc/tm.texi (OVERLAPPING_REGISTER_NAMES): Document new macro. ++ * output.h (decode_reg_name_and_count): Declare. ++ * varasm.c (decode_reg_name_and_count): New function. ++ (decode_reg_name): Reimplement using decode_reg_name_and_count. ++ * reginfo.c (fix_register): Use decode_reg_name_and_count and ++ iterate over all regs used. ++ * stmt.c (expand_asm_operands): Likewise. ++ * config/arm/aout.h (OVERLAPPING_REGISTER_NAMES): Define. ++ (ADDITIONAL_REGISTER_NAMES): Remove aliases that overlap ++ multiple machine registers. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-04-08 Bernd Schmidt ++ ++ Issue #6952 ++ ++ gcc/ ++ * ira-costs.c (record_reg_classes): Ignore alternatives that are ++ not enabled. ++ * config/arm/vfp.md (arm_movdi_vfp): Enable only when not tuning ++ for Cortex-A8. ++ (arm_movdi_vfp_cortexa8): New pattern. ++ * config/arm/neon.md (adddi3_neon, subdi3_neon, anddi3_neon, ++ iordi3_neon, xordi3_neon): Add alternatives to discourage Neon ++ instructions when tuning for Cortex-A8. Set attribute "alt_tune". ++ * config/arm/arm.md (define_attr "alt_tune", define_attr "enabled"): ++ New. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-04-07 Thomas Schwinge ++ Daniel Jacobowitz ++ ++ Issue #6715 ++ ++ PR debug/40521 ++ ++ gcc/ ++ * dwarf2out.c (NEED_UNWIND_TABLES): Define. ++ (dwarf2out_do_frame, dwarf2out_do_cfi_asm, dwarf2out_begin_prologue) ++ (dwarf2out_frame_finish, dwarf2out_assembly_start): Use it. ++ (dwarf2out_assembly_start): Correct logic for TARGET_UNWIND_INFO. ++ * config/arm/arm.h (DWARF2_UNWIND_INFO): Remove definition. ++ * config/arm/bpabi.h (DWARF2_UNWIND_INFO): Define to zero. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ Jie Zhang ++ ++ Issue #7122 ++ ++ gcc/ ++ * config/arm/arm.c (arm_rtx_costs_1): Adjust cost for ++ CONST_VECTOR. ++ (arm_size_rtx_costs): Likewise. ++ (thumb2_size_rtx_costs): Likewise. ++ (neon_valid_immediate): Add a case for double 0.0. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/neon-vdup-1.c: New test case. ++ * gcc.target/arm/neon-vdup-2.c: New test case. ++ * gcc.target/arm/neon-vdup-3.c: New test case. ++ * gcc.target/arm/neon-vdup-4.c: New test case. ++ * gcc.target/arm/neon-vdup-5.c: New test case. ++ * gcc.target/arm/neon-vdup-6.c: New test case. ++ * gcc.target/arm/neon-vdup-7.c: New test case. ++ * gcc.target/arm/neon-vdup-8.c: New test case. ++ * gcc.target/arm/neon-vdup-9.c: New test case. ++ * gcc.target/arm/neon-vdup-10.c: New test case. ++ * gcc.target/arm/neon-vdup-11.c: New test case. ++ * gcc.target/arm/neon-vdup-12.c: New test case. ++ * gcc.target/arm/neon-vdup-13.c: New test case. ++ * gcc.target/arm/neon-vdup-14.c: New test case. ++ * gcc.target/arm/neon-vdup-15.c: New test case. ++ * gcc.target/arm/neon-vdup-16.c: New test case. ++ * gcc.target/arm/neon-vdup-17.c: New test case. ++ * gcc.target/arm/neon-vdup-18.c: New test case. ++ * gcc.target/arm/neon-vdup-19.c: New test case. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ Jie Zhang ++ ++ Issue #7122 ++ ++ gcc/ ++ * config/arm/vfp.md (movdf_vfp): Add load double 0.0 case. ++ (thumb2_movdf_vfp): Likewise. Require that one of the operands be a ++ register. ++ * config/arm/constraints.md (D0): New constraint. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/neon-load-df0.c: New test. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-02-23 Julian Brown ++ ++ gcc/ ++ * config/arm/arm.c (thumb2_size_rtx_costs): New. ++ (arm_rtx_costs): Call above for Thumb-2. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-02-23 Julian Brown ++ ++ gcc/ ++ * calls.c (precompute_register_parameters): Avoid generating a ++ register move if optimizing for size. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-02-15 Julian Brown ++ ++ Issue #7486 ++ ++ gcc/ ++ * config/arm/arm.c (arm_libcall_uses_aapcs_base) ++ (arm_init_cumulative_args): Use correct ABI for double-precision ++ helper functions in hard-float mode if only single-precision ++ arithmetic is supported in hardware. ++ ++2010-07-26 Julian Brown ++ ++ Backport from FSF mainline: ++ ++ Julian Brown ++ Mark Mitchell ++ ++ gcc/ ++ * config/arm/arm.c (arm_function_ok_for_sibcall): Only forbid ++ sibling calls for Thumb-1. ++ * config/arm/arm.h (USE_RETURN_INSN): Enable for Thumb-2. ++ * config/arm/arm.md (*call_symbol, *call_value_symbol): Use for ++ Thumb-2. ++ (*call_insn, *call_value_insn): Don't use for Thumb-2. ++ (sibcall, sibcall_value, *sibcall_insn, *sibcall_value_insn): Use ++ for Thumb-2. ++ (return): New expander. ++ (*arm_return): New name for ARM return insn. ++ * config/arm/thumb2.md (*thumb2_return): New insn pattern. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-02-04 Daniel Jacobowitz ++ ++ Issue #7197 - backtrace() through throw() ++ ++ libstdc++-v3/ ++ * libsupc++/eh_personality.cc (PERSONALITY_FUNCTION): For ++ ARM EABI, skip handlers for _US_VIRTUAL_UNWIND_FRAME ++ | _US_FORCE_UNWIND. ++ ++2010-07-26 Julian Brown ++ ++ Backport from FSF mainline: ++ ++ 2010-02-03 Daniel Gutson ++ ++ Issue #6472 ++ ++ gcc/ ++ * config/arm/lib1funcs.asm (__ARM_ARCH__): __ARM_ARCH_7EM__ ++ added to the preprocessor condition. ++ ++2010-07-26 Julian Brown ++ ++ Backport from FSF mainline: ++ ++ gcc/ ++ * config/arm/thumb2.md (*thumb2_addsi3_compare0): New. ++ (*thumb2_addsi3_compare0_scratch): New. ++ * config/arm/constraints.md (Pv): New. ++ * config/arm/arm.md (*addsi3_compare0): Remove FIXME comment. Use ++ for ARM mode only. ++ (*addsi3_compare0_scratch): Likewise. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-05-25 Julian Brown ++ ++ gcc/ ++ * config/arm/arm.c (arm_tune_cortex_a5): New. ++ (arm_override_options): Set above. Set max_insns_skipped to 1 for ++ Cortex-A5. ++ * config/arm/arm.h (arm_tune_cortex_a5): Add declaration. ++ (BRANCH_COST): Set to zero for Cortex-A5 unless optimising for ++ size. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2009-08-26 Julian Brown ++ ++ gcc/config/arm/ ++ * uclinux-eabi.h (LINK_GCC_C_SEQUENCE_SPEC): Override definition ++ for uclinux. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2009-08-26 Kazu Hirata ++ ++ Issue #6089 ++ gcc/ ++ * config/arm/arm.c (arm_rtx_costs_1): Don't special case for ++ Thumb-2 in the MINUS case. ++ ++2010-07-26 Julian Brown ++ ++ Backport from FSF mainline: ++ ++ gcc/ ++ * gengtype-lex.l: Add HARD_REG_SET. ++ * expr.c (expand_expr_real_1): Record writes to hard registers. ++ * function.h (rtl_data): Add asm_clobbers. ++ * ira.c (compute_regs_asm_clobbered): Use crtl->asm_clobbers. ++ (ira_setup_eliminable_regset): Remove regs_asm_clobbered. ++ Use crtl->asm_clobbers. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/frame-pointer-1.c: New test. ++ * gcc.target/i386/pr9771-1.c: Move code out of main to allow frame ++ pointer elimination. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2009-06-23 Kazu Hirata ++ ++ Issue #4613 ++ gcc/ ++ * config/arm/arm.c (arm_rtx_costs_1): Teach that the cost of MLS ++ is the same as its underlying multiplication. ++ * config/arm/arm.md (two splitters): New. ++ * config/arm/predicates.md (binary_operator): New. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2008-09-08 Daniel Jacobowitz ++ ++ gcc/ ++ * config/arm/unwind-arm.c (__gnu_unwind_pr_common): Correct test ++ for barrier handlers. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ gcc/ ++ * config/arm/arm.c (arm_override_options): Override alignments if ++ tuning for Cortex-A8. ++ (create_fix_barrier, arm_reorg): If aligning to jumps or loops, ++ make labels have a size. ++ * config/arm/arm.md (VUNSPEC_ALIGN16, VUNSPEC_ALIGN32): New constants. ++ (align_16, align_32): New patterns. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ Mark Shinwell ++ ++ gcc/ ++ * config/arm/vfp.md (*arm_movsi_vfp, *thumb2_movsi_vfp) ++ (*arm_movdi_vfp, *thumb2_movdi_vfp, *movsf_vfp, *thumb2_movsf_vfp) ++ (*movdf_vfp, *thumb2_movdf_vfp, *movsfcc_vfp, *thumb2_movsfcc_vfp) ++ (*movdfcc_vfp, *thumb2_movdfcc_vfp): Add neon_type. ++ * config/arm/arm.md (neon_type): Update comment. ++ ++2010-08-10 Andrew Stubbs ++ ++ gcc/ ++ * REVISION: Bump version. ++ ++2010-08-10 Andrew Stubbs ++ ++ GCC Linaro 4.5-2010.08-1 released. ++ ++ gcc/ ++ *REVISION: Update. ++ ++2010-08-06 Yao Qi ++ ++ LP: #612011 ++ gcc/ ++ * config/arm/arm.c (output_move_double): Fix typo generating ++ instructions ('ldr'->'str'). ++ ++ gcc/testsuite/ ++ * gcc.target/arm/pr45094.c: New test. ++ ++2010-08-02 Ulrich Weigand ++ ++ LP: #604874 ++ Backport from mainline: ++ ++ gcc/cp/ ++ PR c++/45112 ++ * decl.c (duplicate_decls): Merge DECL_USER_ALIGN and DECL_PACKED. ++ ++ gcc/testsuite/ ++ PR c++/45112 ++ * testsuite/g++.dg/pr45112.C: New test. ++ ++2010-08-10 Andrew Stubbs ++ ++ Merge from FSF GCC 4.5.1. ++ ++2010-08-06 Andrew Stubbs ++ ++ gcc/ ++ * REVISION: Bump version. ++ ++2010-08-06 Andrew Stubbs ++ ++ GCC Linaro 4.5-2010.08-0 released. ++ ++ gcc/ ++ * REVISION: New file. ++ * DEV-PHASE: Set to "Linaro". ++ ++2010-07-26 Julian Brown ++ ++ Backport from FSF mainline: ++ ++ Mark Shinwell ++ Julian Brown ++ ++ gcc/ ++ * config/arm/thumb2.md (thumb2_movsi_insn): Split ldr and str ++ alternatives according to use of high and low regs. ++ * config/arm/vfp.md (thumb2_movsi_vfp): Likewise. ++ * config/arm/arm.h (CONDITIONAL_REGISTER_USAGE): Use high regs when ++ optimizing for size on Thumb-2. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ http://gcc.gnu.org/ml/gcc-patches/2006-03/msg00038.html ++ ++ * g++.dg/other/armv7m-1.C: New. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ http://gcc.gnu.org/ml/gcc-patches/2006-04/msg00811.html ++ ++ Kazu Hirata ++ ++ gcc/testsuite/ ++ * gcc.target/arm/vfp-ldmdbd.c, gcc.target/arm/vfp-ldmdbs.c, ++ gcc.target/arm/vfp-ldmiad.c, gcc.target/arm/vfp-ldmias.c, ++ gcc.target/arm/vfp-stmdbd.c, gcc.target/arm/vfp-stmdbs.c, ++ gcc.target/arm/vfp-stmiad.c, gcc.target/arm/vfp-stmias.c: New. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ Julian Brown ++ Mark Shinwell ++ ++ gcc/ ++ * regrename.c (addresses.h): Move include of addresses.h after ++ include of flags.h. ++ * recog.c: Likewise. ++ * regcprop.c: Likewise. ++ * config/arm/arm.h (CLASS_LIKELY_SPILLED_P): Check against ++ LO_REGS only for Thumb-1. ++ (MODE_BASE_REG_CLASS): Restrict base registers to those which can ++ be used in short instructions when optimising for size on Thumb-2. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ Vladimir Prus ++ Julian Brown ++ ++ gcc/ ++ * config/arm/arm.c (arm_override_options): Warn if mlow-irq-latency is ++ specified in Thumb mode. ++ (load_multiple_sequence): Return 0 if low irq latency is requested. ++ (store_multiple_sequence): Likewise. ++ (arm_gen_load_multiple): Load registers one-by-one if low irq latency ++ is requested. ++ (arm_gen_store_multiple): Likewise. ++ (vfp_output_fldmd): When low_irq_latency is non zero, pop each ++ register separately. ++ (vfp_emit_fstmd): When low_irq_latency is non zero, save each register ++ separately. ++ (arm_get_vfp_saved_size): Adjust saved register size calculation for ++ the above changes. ++ (print_pop_reg_by_ldr): New. ++ (arm_output_epilogue): Use print_pop_reg_by_ldr when low irq latency ++ is requested. ++ (emit_multi_reg_push): Push registers separately if low irq latency ++ is requested. ++ * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Set __low_irq_latency__. ++ (low_irq_latency): Define. ++ (USE_RETURN_INSN): Don't use return insn when low irq latency is ++ requested. ++ * config/arm/lib1funcs.asm (do_pop, do_push): Define as variadic ++ macros. When __low_irq_latency__ is defined, push and pop registers ++ individually. ++ (div0): Use correct punctuation. ++ * config/arm/ieee754-df.S: Adjust syntax of using do_push. ++ * config/arm/ieee754-sf.S: Likewise. ++ * config/arm/bpabi.S: Likewise. ++ * config/arm/arm.opt (mlow-irq-latency): New option. ++ * config/arm/predicates.md (load_multiple_operation): Return false is ++ low irq latency is requested. ++ (store_multiple_operation): Likewise. ++ * config/arm/arm.md (movmemqi): Don't use it if low irq latency is ++ requested. ++ * doc/invoke.texi (-mlow-irq-latency): Add documentation. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2007-06-06 Joseph Myers ++ ++ gcc/ ++ * config/arm/arm.h (VALID_IWMMXT_REG_MODE): Allow SImode. ++ (ARM_LEGITIMIZE_RELOAD_ADDRESS): Reduce range allowed for SImode ++ offsets with iWMMXt. ++ * config/arm/arm.c (arm_hard_regno_mode_ok): Update for change to ++ VALID_IWMMXT_REG_MODE. ++ ++2010-07-26 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2007-07-05 Mark Shinwell ++ ++ gcc/ ++ * config/arm/arm.h (BRANCH_COST): Set to 1 when optimizing for size ++ on Thumb-2. ++ ++2010-08-05 Andrew Stubbs ++ ++ gcc/testsuite/ ++ * gcc.dg/vect/vect-shift-2.c: Revert all previous changes. ++ * gcc.dg/vect/vect-shift-4.c: New file. ++ ++ 2010-07-20 Yao Qi ++ ++ Merge from Sourcery G++ 4.4: ++ 2009-06-16 Daniel Jacobowitz ++ ++ Merge from Sourcery G++ 4.3: ++ 2008-12-03 Daniel Jacobowitz ++ ++ gcc/testsuite/ ++ * gcc.dg/vect/vect-shift-2.c, gcc.dg/vect/vect-shift-3.c: New. ++ * lib/target-supports.exp (check_effective_target_vect_shift_char): New ++ function. ++ ++2010-07-24 Sandra Loosemore ++ ++ Backport from mainline: ++ ++ 2010-04-10 Wei Guozhi ++ ++ PR target/42601 ++ gcc/ ++ * config/arm/arm.c (arm_pic_static_addr): New function. ++ (legitimize_pic_address): Call arm_pic_static_addr when it detects ++ a static symbol. ++ (arm_output_addr_const_extra): Output expression for new pattern. ++ * config/arm/arm.md (UNSPEC_SYMBOL_OFFSET): New unspec symbol. ++ ++ 2010-07-22 Sandra Loosemore ++ ++ PR tree-optimization/39839 ++ gcc/testsuite/ ++ * gcc.target/arm/pr39839.c: New test case. ++ ++2010-07-24 Jie Zhang ++ ++ Issue #9079 ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-07-23 Jie Zhang ++ PR target/44290 ++ * attribs.c (decl_attributes): Insert "noinline" and "noclone" ++ if "naked". ++ * tree-sra.c (ipa_sra_preliminary_function_checks): Return ++ false if ! tree_versionable_function_p. ++ ++ gcc/testsuite/ ++ 2010-07-23 Jie Zhang ++ PR target/44290 ++ * gcc.dg/pr44290-1.c: New test. ++ * gcc.dg/pr44290-2.c: New test. ++ ++2010-07-22 Maxim Kuvyrkov ++ ++ Backport from FSF GCC 4.5 branch to fix PR45015: ++ ++ 2010-07-22 Jakub Jelinek ++ PR debug/45015 ++ * var-tracking.c (adjust_mems): Ignore ASM_OPERANDS with non-zero ++ ASM_OPERANDS_OUTPUT_IDX. ++ (adjust_insn): For inline asm with multiple sets ensure first ++ ASM_OPERANDS vectors are used by all following ASM_OPERANDS in ++ the insn. ++ ++ 2010-07-22 Jakub Jelinek ++ PR debug/45015 ++ * gcc.target/m68k/pr45015.c: New test. ++ ++2010-07-20 Yao Qi ++ ++ Merge from Sourcery G++ 4.4: ++ 2010-06-07 Kazu Hirata ++ ++ Issue #8535 ++ ++ Backport from mainline: ++ gcc/ ++ 2010-06-07 Kazu Hirata ++ PR rtl-optimization/44404 ++ * auto-inc-dec.c (find_inc): Use reg_overlap_mentioned_p instead ++ of count_occurrences to see if it's safe to modify mem_insn.insn. ++ ++ gcc/testsuite/ ++ 2010-06-07 Kazu Hirata ++ PR rtl-optimization/44404 ++ * gcc.dg/pr44404.c: New. ++ ++2010-08-03 Chung-Lin Tang ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-07-28 Chung-Lin Tang ++ * config/arm/arm.c (arm_pcs_default): Remove static. ++ * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_PCS or ++ __ARM_PCS_VFP to indicate soft/hard-float calling convention. ++ (arm_pcs_default): Declare. ++ ++2010-07-16 Jie Zhang ++ ++ Issue #7688 ++ ++ Backport from mainline: ++ ++ gcc/ ++ 2010-07-12 Jie Zhang ++ * postreload.c (reg_symbol_ref[]): New. ++ (move2add_use_add2_insn): New. ++ (move2add_use_add3_insn): New. ++ (reload_cse_move2add): Handle SYMBOL + OFFSET case. ++ (move2add_note_store): Likewise. ++ ++2010-07-15 Yao Qi ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-02-25 Maxim Kuvyrkov ++ ++ gcc/ ++ * tree.c (initializer_zerop): Handle STRING_CST. ++ ++2010-07-15 Sandra Loosemore ++ ++ Backport from mainline: ++ ++ 2010-06-09 Sandra Loosemore ++ ++ gcc/ ++ * tree-ssa-loop-ivopts.c (adjust_setup_cost): New function. ++ (get_computation_cost_at): Use it. ++ (determine_use_iv_cost_condition): Likewise. ++ (determine_iv_cost): Likewise. ++ ++ 2010-07-05 Sandra Loosemore ++ ++ PR middle-end/42505 ++ ++ gcc/ ++ * tree-ssa-loop-ivopts.c (determine_set_costs): Delete obsolete ++ comments about cost model. ++ (try_add_cand_for): Add second strategy for choosing initial set ++ based on original IVs, controlled by ORIGINALP argument. ++ (get_initial_solution): Add ORIGINALP argument. ++ (find_optimal_iv_set_1): New function, split from find_optimal_iv_set. ++ (find_optimal_iv_set): Try two different strategies for choosing ++ the IV set, and return the one with lower cost. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/pr42505.c: New test case. ++ ++ 2010-07-10 Sandra Loosemore ++ ++ PR middle-end/42505 ++ ++ gcc/ ++ * tree-inline.c (estimate_num_insns): Refactor builtin complexity ++ lookup code into.... ++ * builtins.c (is_simple_builtin, is_inexpensive_builtin): ...these ++ new functions. ++ * tree.h (is_simple_builtin, is_inexpensive_builtin): Declare. ++ * cfgloopanal.c (target_clobbered_regs): Define. ++ (init_set_costs): Initialize target_clobbered_regs. ++ (estimate_reg_pressure_cost): Add call_p argument. When true, ++ adjust the number of available registers to exclude the ++ call-clobbered registers. ++ * cfgloop.h (target_clobbered_regs): Declare. ++ (estimate_reg_pressure_cost): Adjust declaration. ++ * tree-ssa-loop-ivopts.c (struct ivopts_data): Add body_includes_call. ++ (ivopts_global_cost_for_size): Pass it to estimate_reg_pressure_cost. ++ (determine_set_costs): Dump target_clobbered_regs. ++ (loop_body_includes_call): New function. ++ (tree_ssa_iv_optimize_loop): Use it to initialize new field. ++ * loop-invariant.c (gain_for_invariant): Adjust arguments to pass ++ call_p flag through. ++ (best_gain_for_invariant): Likewise. ++ (find_invariants_to_move): Likewise. ++ (move_single_loop_invariants): Likewise, using already-computed ++ has_call field. ++ ++2010-07-15 Jie Zhang ++ ++ Issue #8497, #8893 ++ ++ Backport from mainline (originally from Sourcery G++ 4.4): ++ ++ gcc/ ++ 2010-07-12 Jie Zhang ++ * config/arm/arm.c (arm_get_frame_offsets): Don't use r3 to ++ align the stack when it's going to be saved. ++ ++ gcc/testsuite/ ++ 2010-07-12 Jie Zhang ++ * gcc.target/arm/interrupt-1.c: New test. ++ * gcc.target/arm/interrupt-2.c: New test. ++ ++2010-07-15 Jie Zhang ++ ++ Backport from mainline (originally from Sourcery G++ 4.4): ++ ++ gcc/ ++ 2010-07-07 Jie Zhang ++ * genautomata.c (output_automata_list_min_issue_delay_code): ++ Correctly decompress min_issue_delay. ++ ++2010-07-15 Jie Zhang ++ ++ Issue #8980 ++ ++ Backport from mainline (originally from Sourcery G++ 4.4): ++ ++ gcc/ ++ 2010-07-03 Jie Zhang ++ * config/arm/vfp.md (*push_multi_vfp): Use vfp_register_operand ++ as predicate for operand 1 and remove its constraint. ++ * config/arm/predicates.md (vfp_register_operand): New. ++ * config/arm/arm.md (*push_multi): Remove the constraint of ++ operand 1. ++ (*push_fp_multi): Likewise. ++ ++2010-07-15 Jie Zhang ++ ++ Backport from mainline (originally from Sourcery G++ 4.4): ++ ++ gcc/cp/ ++ 2010-04-07 Jie Zhang ++ ++ PR c++/42556 ++ * typeck2.c (split_nonconstant_init_1): Drop empty CONSTRUCTOR ++ when all of its elements are non-constant and have been split out. ++ ++ gcc/testsuite/ ++ 2010-04-07 Jie Zhang ++ ++ PR c++/42556 ++ * g++.dg/init/pr42556.C: New test. ++ ++2010-07-12 Yao Qi ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2009-10-06 Paul Brook ++ Issue #3869 ++ gcc/ ++ * target.h (gcc_target): Add warn_func_result. ++ * target-def.h (TARGET_WARN_FUNC_RESULT): Define and use. ++ * tree-cfg.h (execute_warn_function_return): Use ++ targetm.warn_func_result. ++ * config/arm/arm.c (TARGET_WARN_FUNC_RESULT): Define. ++ (arm_warn_func_result): New function. ++ ++ gcc/testuite/ ++ * gcc.target/arm/naked-3.c: New test. ++ ++2010-07-10 Sandra Loosemore ++ ++ Backport from mainline: ++ ++ 2010-05-08 Sandra Loosemore ++ ++ PR middle-end/28685 ++ ++ gcc/ ++ * tree-ssa-reassoc.c (eliminate_redundant_comparison): New function. ++ (optimize_ops_list): Call it. ++ ++ gcc/testsuite/ ++ * gcc.dg/pr28685-1.c: New file. ++ ++ 2010-06-08 Sandra Loosemore ++ ++ PR tree-optimization/39874 ++ PR middle-end/28685 ++ ++ gcc/ ++ * gimple.h (maybe_fold_and_comparisons, maybe_fold_or_comparisons): ++ Declare. ++ * gimple-fold.c (canonicalize_bool, same_bool_comparison_p, ++ same_bool_result_p): New. ++ (and_var_with_comparison, and_var_with_comparison_1, ++ and_comparisons_1, and_comparisons, maybe_fold_and_comparisons): New. ++ (or_var_with_comparison, or_var_with_comparison_1, ++ or_comparisons_1, or_comparisons, maybe_fold_or_comparisons): New. ++ * tree-ssa-reassoc.c (eliminate_redundant_comparison): Use ++ maybe_fold_and_comparisons or maybe_fold_or_comparisons instead ++ of combine_comparisons. ++ * tree-ssa-ifcombine.c (ifcombine_ifandif, ifcombine_iforif): Likewise. ++ ++ gcc/testsuite/ ++ * gcc.dg/pr39874.c: New file. ++ ++2010-07-10 Yao Qi ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2009-09-02 Daniel Jacobowitz ++ ++ libgcc/ ++ * shared-object.mk (c_flags-$(base)$(objext)): New. ++ ($(base)$(objext)): Use above. ++ ($(base)_s$(objext)): Likewise. ++ * static-object.mk (c_flags-$(base)$(objext)): New. ++ ($(base)$(objext)): Use above. ++ ++2010-07-10 Yao Qi ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2009-05-28 Julian Brown ++ ++ Merged from Sourcery G++ 4.3: ++ ++ libgcc/ ++ * config.host (arm*-*-linux*, arm*-*-uclinux*, arm*-*-eabi*) ++ (arm*-*-symbianelf): Add arm/t-divmod-ef to tmake_file. ++ * Makefile.in (LIB2_DIVMOD_EXCEPTION_FLAGS): Set to previous ++ default if not set by a target-specific Makefile fragment. ++ (lib2-divmod-o, lib2-divmod-s-o): Use above. ++ * config/arm/t-divmod-ef: New. ++ ++2010-07-09 Sandra Loosemore ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2009-05-21 Sandra Loosemore ++ ++ Merge from Sourcery G++ 4.3: ++ ++ 2009-04-04 Sandra Loosemore ++ ++ Issue #5104 ++ PR tree-optimization/39604 ++ ++ gcc/testsuite ++ * g++.dg/tree-ssa/sink-1.C: New. ++ ++ gcc/ ++ * tree_ssa-sink.c (sink_code_in_bb): Do not sink statements out ++ of a lexical block containing variable definitions. ++ ++2010-07-09 Sandra Loosemore ++ ++ Backport from mainline (originally on Sourcery G++ 4.4): ++ ++ 2010-07-02 Julian Brown ++ Sandra Loosemore ++ ++ PR target/43703 ++ ++ gcc/ ++ * config/arm/vec-common.md (add3, sub3, smin3) ++ (smax3): Disable for NEON float modes when ++ flag_unsafe_math_optimizations is false. ++ * config/arm/neon.md (*add3_neon, *sub3_neon) ++ (*mul3_neon) ++ (mul3add_neon, mul3negadd_neon) ++ (reduc_splus_, reduc_smin_, reduc_smax_): Disable ++ for NEON float modes when flag_unsafe_math_optimizations is false. ++ (quad_halves_v4sf): Only enable if flag_unsafe_math_optimizations ++ is true. ++ * doc/invoke.texi (ARM Options): Add note about floating point ++ vectorization requiring -funsafe-math-optimizations. ++ ++ gcc/testsuite/ ++ * gcc.dg/vect/vect.exp: Add -ffast-math for NEON. ++ * gcc.dg/vect/vect-reduc-6.c: Add XFAIL for NEON. ++ ++2010-07-08 Sandra Loosemore ++ ++ Backport from upstream (originally from Sourcery G++ 4.4): ++ ++ 2010-07-02 Daniel Jacobowitz ++ Julian Brown ++ Sandra Loosemore ++ ++ gcc/ ++ * config/arm/arm.c (arm_canonicalize_comparison): Canonicalize DImode ++ comparisons. Adjust to take both operands. ++ (arm_select_cc_mode): Handle DImode comparisons. ++ (arm_gen_compare_reg): Generate a scratch register for DImode ++ comparisons which require one. Use xor for Thumb equality checks. ++ (arm_const_double_by_immediates): New. ++ (arm_print_operand): Allow 'Q' and 'R' for constants. ++ (get_arm_condition_code): Handle new CC_CZmode and CC_NCVmode. ++ * config/arm/arm.h (CANONICALIZE_COMPARISON): Always use ++ arm_canonicalize_comparison. ++ * config/arm/arm-modes.def: Add CC_CZmode and CC_NCVmode. ++ * config/arm/arm-protos.h (arm_canonicalize_comparison): Update ++ prototype. ++ (arm_const_double_by_immediates): Declare. ++ * config/arm/constraints.md (Di): New constraint. ++ * config/arm/predicates.md (arm_immediate_di_operand) ++ (arm_di_operand, cmpdi_operand): New. ++ * config/arm/arm.md (cbranchdi4): Handle non-Cirrus also. ++ (*arm_cmpdi_insn, *arm_cmpdi_unsigned) ++ (*arm_cmpdi_zero, *thumb_cmpdi_zero): New insns. ++ (cstoredi4): Handle non-Cirrus also. ++ ++ gcc/testsuite/ ++ * gcc.c-torture/execute/20100416-1.c: New test case. ++ ++2010-07-08 Sandra Loosemore ++ ++ Backport from upstream (originally from Sourcery G++ 4.4): ++ ++ 2010-07-02 Sandra Loosemore ++ ++ gcc/ ++ * config/arm/neon.md (vec_extractv2di): Correct error in register ++ numbering to reconcile with neon_vget_lanev2di. ++ ++ 2010-07-02 Sandra Loosemore ++ ++ gcc/ ++ * config/arm/arm.c (neon_vdup_constant): Expand into canonical RTL ++ instead of an unspec. ++ (neon_expand_vector_init): Likewise. ++ * config/arm/neon.md (UNSPEC_VCOMBINE): Delete. ++ (UNSPEC_VDUP_LANE): Delete. ++ (UNSPEC VDUP_N): Delete. ++ (UNSPEC_VGET_HIGH): Delete. ++ (UNSPEC_VGET_LANE): Delete. ++ (UNSPEC_VGET_LOW): Delete. ++ (UNSPEC_VMVN): Delete. ++ (UNSPEC_VSET_LANE): Delete. ++ (V_double_vector_mode): New. ++ (vec_set_internal): Make code emitted match that for the ++ corresponding intrinsics. ++ (vec_setv2di_internal): Likewise. ++ (neon_vget_lanedi): Rewrite to expand into emit_move_insn. ++ (neon_vget_lanev2di): Rewrite to expand into vec_extractv2di. ++ (neon_vset_lane): Combine double and quad patterns and ++ expand into vec_set_internal instead of UNSPEC_VSET_LANE. ++ (neon_vset_lanedi): Rewrite to expand into emit_move_insn. ++ (neon_vdup_n): Rewrite RTL without unspec. ++ (neon_vdup_ndi): Rewrite as define_expand and use emit_move_insn. ++ (neon_vdup_nv2di): Rewrite RTL without unspec and merge with ++ with neon_vdup_lanev2di, adjusting the pattern from the latter ++ to be predicable for consistency. ++ (neon_vdup_lane_internal): New. ++ (neon_vdup_lane): Turn into a define_expand and rewrite ++ to avoid using an unspec. ++ (neon_vdup_lanedi): Rewrite RTL pattern to avoid unspec. ++ (neon_vdup_lanev2di): Turn into a define_expand. ++ (neon_vcombine): Rewrite pattern to eliminate UNPSEC_VCOMBINE. ++ (neon_vget_high): Replace with.... ++ (neon_vget_highv16qi): New pattern using canonical RTL. ++ (neon_vget_highv8hi): Likewise. ++ (neon_vget_highv4si): Likewise. ++ (neon_vget_highv4sf): Likewise. ++ (neon_vget_highv2di): Likewise. ++ (neon_vget_low): Replace with.... ++ (neon_vget_lowv16qi): New pattern using canonical RTL. ++ (neon_vget_lowv8hi): Likewise. ++ (neon_vget_lowv4si): Likewise. ++ (neon_vget_lowv4sf): Likewise. ++ (neon_vget_lowv2di): Likewise. ++ ++ * config/arm/neon.ml (Vget_lane): Add No_op attribute to suppress ++ test for this emitting vmov. ++ (Vset_lane): Likewise. ++ (Vdup_n): Likewise. ++ (Vmov_n): Likewise. ++ ++ * doc/arm-neon-intrinsics.texi: Regenerated. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/neon/vdup_ns64.c: Regenerated. ++ * gcc.target/arm/neon/vdup_nu64.c: Regenerated. ++ * gcc.target/arm/neon/vdupQ_ns64.c: Regenerated. ++ * gcc.target/arm/neon/vdupQ_nu64.c: Regenerated. ++ * gcc.target/arm/neon/vmov_ns64.c: Regenerated. ++ * gcc.target/arm/neon/vmov_nu64.c: Regenerated. ++ * gcc.target/arm/neon/vmovQ_ns64.c: Regenerated. ++ * gcc.target/arm/neon/vmovQ_nu64.c: Regenerated. ++ * gcc.target/arm/neon/vget_lanes64.c: Regenerated. ++ * gcc.target/arm/neon/vget_laneu64.c: Regenerated. ++ * gcc.target/arm/neon/vset_lanes64.c: Regenerated. ++ * gcc.target/arm/neon/vset_laneu64.c: Regenerated. ++ * gcc.target/arm/neon-vdup_ns64.c: New. ++ * gcc.target/arm/neon-vdup_nu64.c: New. ++ * gcc.target/arm/neon-vdupQ_ns64.c: New. ++ * gcc.target/arm/neon-vdupQ_nu64.c: New. ++ * gcc.target/arm/neon-vdupQ_lanes64.c: New. ++ * gcc.target/arm/neon-vdupQ_laneu64.c: New. ++ * gcc.target/arm/neon-vmov_ns64.c: New. ++ * gcc.target/arm/neon-vmov_nu64.c: New. ++ * gcc.target/arm/neon-vmovQ_ns64.c: New. ++ * gcc.target/arm/neon-vmovQ_nu64.c: New. ++ * gcc.target/arm/neon-vget_lanes64.c: New. ++ * gcc.target/arm/neon-vget_laneu64.c: New. ++ * gcc.target/arm/neon-vset_lanes64.c: New. ++ * gcc.target/arm/neon-vset_laneu64.c: New. ++ ++ 2010-07-02 Sandra Loosemore ++ Julian Brown ++ ++ gcc/ ++ * config/arm/neon.md (UNSPEC_VABA): Delete. ++ (UNSPEC_VABAL): Delete. ++ (UNSPEC_VABS): Delete. ++ (UNSPEC_VMUL_N): Delete. ++ (adddi3_neon): New. ++ (subdi3_neon): New. ++ (mul3add_neon): Make the pattern named. ++ (mul3negadd_neon): Likewise. ++ (neon_vadd): Replace with define_expand, and move the remaining ++ unspec parts... ++ (neon_vadd_unspec): ...to this. ++ (neon_vmla, neon_vmla_unspec): Likewise. ++ (neon_vlms, neon_vmls_unspec): Likewise. ++ (neon_vsub, neon_vsub_unspec): Likewise. ++ (neon_vaba): Rewrite in terms of vabd. ++ (neon_vabal): Rewrite in terms of vabdl. ++ (neon_vabs): Rewrite without unspec. ++ * config/arm/arm.md (*arm_adddi3): Disable for TARGET_NEON. ++ (*arm_subdi3): Likewise. ++ * config/arm/neon.ml (Vadd, Vsub): Split out 64-bit variants and add ++ No_op attribute to disable assembly output checks. ++ * config/arm/arm_neon.h: Regenerated. ++ * doc/arm-neon-intrinsics.texi: Regenerated. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/neon/vadds64.c: Regenerated. ++ * gcc.target/arm/neon/vaddu64.c: Regenerated. ++ * gcc.target/arm/neon/vsubs64.c: Regenerated. ++ * gcc.target/arm/neon/vsubu64.c: Regenerated. ++ * gcc.target/arm/neon-vmla-1.c: Add -ffast-math to options. ++ * gcc.target/arm/neon-vmls-1.c: Likewise. ++ * gcc.target/arm/neon-vsubs64.c: New execution test. ++ * gcc.target/arm/neon-vsubu64.c: New execution test. ++ * gcc.target/arm/neon-vadds64.c: New execution test. ++ * gcc.target/arm/neon-vaddu64.c: New execution test. ++ ++2010-07-07 Sandra Loosemore ++ ++ Merge from Sourcery G++ 4.4: ++ ++ 2010-03-08 Paul Brook ++ ++ gcc/ ++ * doc/invoke.texi: Document ARM -mcpu=cortex-m4. ++ * config/arm/arm.c (all_architectures): Change v7e-m default to ++ cortexm4. ++ * config/arm/arm-cores.def: Add cortex-m4. ++ * config/arm/arm-tune.md: Regenerate. ++ ++2010-07-07 Sandra Loosemore ++ ++ Backport from mainline (originally from Sourcery G++ 4.4): ++ ++ 2010-05-24 Daniel Jacobowitz ++ Sandra Loosemore ++ ++ gcc/ ++ * config/arm/neon-testgen.ml: Use dg-add-options arm_neon. ++ * doc/sourcebuild.texi (Effective-Target Keywords): Update arm_neon_ok ++ description. Add arm_neon_fp16_ok. ++ (Add Options): Add arm_neon and arm_neon_fp16. ++ ++ gcc/testsuite/ ++ * gcc.target/arm/neon/: Regenerated test cases. ++ ++ * gcc.target/arm/neon/polytypes.c, ++ gcc.target/arm/neon-vmla-1.c, gcc.target/arm/neon-vmls-1.c, ++ gcc.target/arm/neon-cond-1.c, gcc.target/arm/neon/vfp-shift-a2t2.c, ++ gcc.target/arm/neon-thumb2-move.c, gcc.dg/torture/arm-fp16-ops-8.c, ++ gcc.dg/torture/arm-fp16-ops-7.c, g++.dg/ext/arm-fp16/arm-fp16-ops-7.C, ++ g++.dg/ext/arm-fp16/arm-fp16-ops-8.C, g++.dg/abi/mangle-neon.C: Use ++ dg-add-options arm_neon. ++ ++ * gcc.target/arm/fp16-compile-vcvt.c, gcc.dg/torture/arm-fp16-ops-5.c, ++ gcc.dg/torture/arm-fp16-ops-6.c, g++.dg/ext/arm-fp16/arm-fp16-ops-5.C, ++ g++.dg/ext/arm-fp16/arm-fp16-ops-6.C: Use dg-add-options arm_neon_fp16 ++ and arm_neon_fp16_ok. ++ ++ * gcc.dg/vect/vect.exp, g++.dg/vect/vect.exp, ++ gfortran.dg/vect/vect.exp: Use add_options_for_arm_neon. ++ ++ * lib/target-supports.exp (add_options_for_arm_neon): New. ++ (check_effective_target_arm_neon_ok_nocache): New, from ++ check_effective_target_arm_neon_ok. Check multiple possibilities. ++ (check_effective_target_arm_neon_ok): Use ++ check_effective_target_arm_neon_ok_nocache. ++ (add_options_for_arm_neon_fp16) ++ (check_effective_target_arm_neon_fp16_ok) ++ check_effective_target_arm_neon_fp16_ok_nocache): New. ++ (check_effective_target_arm_neon_hw): Use add_options_for_arm_neon. ++ ++2010-06-28 Julian Brown ++ ++ Merge from Sourcery G++ 4.4: ++ ++ Daniel Jacobowitz ++ Joseph Myers ++ ++ gcc/ ++ * doc/invoke.texi (-Wno-poison-system-directories): Document. ++ * gcc.c (LINK_COMMAND_SPEC): Pass --no-poison-system-directories ++ if -Wno-poison-system-directories and --error-poison-system-directories ++ if -Werror=poison-system-directories to linker. ++ * incpath.c: Include flags.h. Include toplev.h. ++ (merge_include_chains): If ENABLE_POISON_SYSTEM_DIRECTORIES defined ++ and flag_poison_system_directories is true, warn for use of ++ /usr/include, /usr/local/include or /usr/X11R6/include. ++ * Makefile.in (incpath.o): Depend on $(FLAGS_H) and toplev.h. ++ * common.opt (--Wno-poison-system-directories): New. ++ * configure.ac (--enable-poison-system-directories): New option. ++ * configure: Regenerate. ++ * config.in: Regenerate. +--- a/src/configure ++++ b/src/configure +@@ -5780,8 +5780,6 @@ + + + # Check for PPL +-ppl_major_version=0 +-ppl_minor_version=10 + ppllibs=" -lppl_c -lppl -lgmpxx" + pplinc= + +@@ -5838,8 +5836,8 @@ + if test "x$with_ppl" != "xno" -a "${ENABLE_PPL_CHECK}" = "yes"; then + saved_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS $pplinc $gmpinc" +- { $as_echo "$as_me:${as_lineno-$LINENO}: checking for version $ppl_major_version.$ppl_minor_version of PPL" >&5 +-$as_echo_n "checking for version $ppl_major_version.$ppl_minor_version of PPL... " >&6; } ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking for version 0.10 (or later revision) of PPL" >&5 ++$as_echo_n "checking for version 0.10 (or later revision) of PPL... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext + /* end confdefs.h. */ + #include "ppl_c.h" +@@ -5847,7 +5845,7 @@ + main () + { + +- #if PPL_VERSION_MAJOR != $ppl_major_version || PPL_VERSION_MINOR != $ppl_minor_version ++ #if PPL_VERSION_MAJOR != 0 || PPL_VERSION_MINOR < 10 + choke me + #endif + +--- a/src/configure.ac ++++ b/src/configure.ac +@@ -1510,8 +1510,6 @@ + AC_SUBST(poststage1_ldflags) + + # Check for PPL +-ppl_major_version=0 +-ppl_minor_version=10 + ppllibs=" -lppl_c -lppl -lgmpxx" + pplinc= + +@@ -1552,9 +1550,9 @@ + if test "x$with_ppl" != "xno" -a "${ENABLE_PPL_CHECK}" = "yes"; then + saved_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS $pplinc $gmpinc" +- AC_MSG_CHECKING([for version $ppl_major_version.$ppl_minor_version of PPL]) ++ AC_MSG_CHECKING([for version 0.10 (or later revision) of PPL]) + AC_TRY_COMPILE([#include "ppl_c.h"],[ +- #if PPL_VERSION_MAJOR != $ppl_major_version || PPL_VERSION_MINOR != $ppl_minor_version ++ #if PPL_VERSION_MAJOR != 0 || PPL_VERSION_MINOR < 10 + choke me + #endif + ], [AC_MSG_RESULT([yes])], [AC_MSG_RESULT([no]); ppllibs= ; pplinc= ; with_ppl=no ]) +--- a/src/gcc/ChangeLog ++++ b/src/gcc/ChangeLog +@@ -1,3 +1,677 @@ ++2011-02-18 John David Anglin ++ ++ * config.gcc (hppa[12]*-*-hpux11*): Set extra_parts. ++ * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock, ++ pthread_mutex_unlock, pthread_once): Reinstate pthread stubs. ++ * config/pa/t-pa-hpux11: Add rules to build pthread stubs. ++ * config/pa/t-pa64: Likewise. ++ * config/pa/pa-hpux11.h (LINK_GCC_C_SEQUENCE_SPEC): Define. ++ ++2011-02-17 Uros Bizjak ++ ++ PR target/43653 ++ * config/i386/i386.c (ix86_secondary_reload): Handle SSE ++ input reload with PLUS RTX. ++ ++2011-02-15 Rainer Orth ++ ++ PR pch/14940 ++ * config/alpha/host-osf.c: New file. ++ * config/alpha/x-osf: New file. ++ * config.host (alpha*-dec-osf*): Use it. ++ ++2011-02-15 Tijl Coosemans ++ ++ * config/i386/freebsd.h (SUBTARGET32_DEFAULT_CPU): Add. ++ Update copyright years. ++ ++2011-02-11 Bernd Schmidt ++ ++ PR rtl-optimization/47166 ++ * reload1.c (emit_reload_insns): Disable the spill_reg_store ++ mechanism for PRE_MODIFY and POST_MODIFY. ++ (inc_for_reload): For PRE_MODIFY, return the insn that sets the ++ reloadreg. ++ ++2011-02-10 John David Anglin ++ ++ Backport from mainline: ++ 2011-02-07 John David Anglin ++ ++ * config.gcc (hppa[12]*-*-hpux11*): Don't set extra_parts. ++ * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock, ++ pthread_mutex_unlock): Remove. ++ * config/pa/t-pa-hpux11: Remove rules to build pthread stubs. ++ * config/pa/t-pa64: Likewise. ++ * config/pa/pa64-hpux.h (LIB_SPEC): In static links, link against ++ shared libc if not linking against libpthread. ++ * config/pa/pa-hpux11.h (LIB_SPEC): Likewise. ++ ++2011-02-03 Michael Meissner ++ ++ Backport from mainline: ++ 2011-02-02 Michael Meissner ++ ++ PR target/47272 ++ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): ++ Document using vector double with the load/store builtins, and ++ that the load/store builtins always use Altivec instructions. ++ ++ * config/rs6000/vector.md (vector_altivec_load_): New insns ++ to use altivec memory instructions, even on VSX. ++ (vector_altivec_store_): Ditto. ++ ++ * config/rs6000/rs6000-protos.h (rs6000_address_for_altivec): New ++ function. ++ ++ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add ++ V2DF, V2DI support to load/store overloaded builtins. ++ ++ * config/rs6000/rs6000-builtin.def (ALTIVEC_BUILTIN_*): Add ++ altivec load/store builtins for V2DF/V2DI types. ++ ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't ++ set avoid indexed addresses on power6 if -maltivec. ++ (altivec_expand_ld_builtin): Add V2DF, V2DI support, use ++ vector_altivec_load/vector_altivec_store builtins. ++ (altivec_expand_st_builtin): Ditto. ++ (altivec_expand_builtin): Add VSX memory builtins. ++ (rs6000_init_builtins): Add V2DI types to internal types. ++ (altivec_init_builtins): Add support for V2DF/V2DI altivec ++ load/store builtins. ++ (rs6000_address_for_altivec): Insure memory address is appropriate ++ for Altivec. ++ ++ * config/rs6000/vsx.md (vsx_load_): New expanders for ++ vec_vsx_ld and vec_vsx_st. ++ (vsx_store_): Ditto. ++ ++ * config/rs6000/rs6000.h (RS6000_BTI_long_long): New type ++ variables to hold long long types for VSX vector memory builtins. ++ (RS6000_BTI_unsigned_long_long): Ditto. ++ (long_long_integer_type_internal_node): Ditti. ++ (long_long_unsigned_type_internal_node): Ditti. ++ ++ * config/rs6000/altivec.md (UNSPEC_LVX): New UNSPEC. ++ (altivec_lvx_): Make altivec_lvx use a mode iterator. ++ (altivec_stvx_): Make altivec_stvx use a mode iterator. ++ ++ * config/rs6000/altivec.h (vec_vsx_ld): Define VSX memory builtin ++ short cuts. ++ (vec_vsx_st): Ditto. ++ ++ Backport from mainline: ++ 2011-02-01 Michael Meissner ++ ++ PR target/47580 ++ * config/rs6000/vsx.md (vsx_float2): Use ++ gpc_reg_operand instead of vsx_register_operand to match rs6000.md ++ generator functions. ++ (vsx_floatuns2): Ditto. ++ (vsx_fix_trunc2): Ditto. ++ (vsx_fixuns_trunc2): Ditto. ++ ++2011-02-02 Nick Clifton ++ ++ Import these patches from the mainline: ++ 2011-01-31 Nick Clifton ++ ++ * config/rx/rx.c (rx_get_stack_layout): Only save call clobbered ++ registers inside interrupt handlers if the handler is not a leaf ++ function. ++ ++ 2011-01-25 Nick Clifton ++ ++ * config/rx/rx.h (LIBCALL_VALUE): Do not promote complex types. ++ * config/rx/rx.c (rx_function_value): Likewise. ++ (rx_promote_function_mode): Likewise. ++ (gen_safe_add): Place an outsized immediate value inside an UNSPEC ++ in order to make it legitimate. ++ * config/rx/rx.md (adddi3_internal): If the second operand is a ++ MEM make sure that the first operand is the same as the result ++ register. ++ (addsi3_unspec): Delete. ++ (subdi3): Do not accept immediate operands. ++ (subdi3_internal): Likewise. ++ ++ 2011-01-24 Richard Henderson ++ ++ * config/rx/predicates.md (rx_fp_comparison_operator): Don't accept ++ compound unordered comparisons. ++ * config/rx/rx.c (rx_split_fp_compare): Remove. ++ * config/rx/rx-protos.h: Update. ++ * config/rx/rx.md (gcc_conds, rx_conds): Remove. ++ (cbranchsf4): Don't call rx_split_fp_compare. ++ (*cbranchsf4): Use rx_split_cbranch. ++ (*cmpsf): Don't accept "i" constraint. ++ (*conditional_branch): Only valid after reload. ++ (cstoresf4): Merge expander with insn. Don't call ++ rx_split_fp_compare. ++ ++ 2011-01-22 Nick Clifton ++ ++ * config/rx/rx.md (cstoresf4): Pass comparison operator to ++ rx_split_fp_compare. ++ ++ 2011-01-22 Nick Clifton ++ ++ * config/rx/rx.md (UNSPEC_CONST): New. ++ (deallocate_and_return): Wrap the amount popped off the stack in ++ an UNSPEC_CONST in order to stop it being rejected by ++ -mmax-constant-size. ++ (pop_and_return): Add a "(return)" rtx. ++ (call): Drop the immediate operand. ++ (call_internal): Likewise. ++ (call_value): Likewise. ++ (call_value_internal): Likewise. ++ (sibcall_internal): Likewise. ++ (sibcall_value_internal): Likewise. ++ (sibcall): Likewise. Generate an explicit call using ++ sibcall_internal. ++ (sibcall_value): Likewise. ++ (mov<>): FAIL if a constant operand is not legitimate. ++ (addsi3_unpsec): New pattern. ++ ++ * config/rx/rx.c (rx_print_operand_address): Handle UNPSEC ++ CONSTs. ++ (ok_for_max_constant): New function. ++ (gen_safe_add): New function. ++ (rx_expand_prologue): Use gen_safe_add. ++ (rx_expand_epilogue): Likewise. ++ (rx_is_legitimate_constant): Use ok_for_max_constant. Handle ++ UNSPEC CONSTs. ++ ++ 2011-01-17 Richard Henderson ++ ++ * config/rx/predicates.md (rx_constshift_operand): Use match_test. ++ (rx_restricted_mem_operand): New. ++ (rx_shift_operand): Use register_operand. ++ (rx_source_operand, rx_compare_operand): Likewise. ++ * config/rx/rx.md (addsi3_flags): New expander. ++ (adddi3): Rewrite as expander. ++ (adc_internal, *adc_flags, adddi3_internal): New patterns. ++ (subsi3_flags): New expander. ++ (subdi3): Rewrite as expander. ++ (sbb_internal, *sbb_flags, subdi3_internal): New patterns. ++ ++ * config/rx/rx.c (RX_BUILTIN_SAT): Remove. ++ (rx_init_builtins): Remove sat builtin. ++ (rx_expand_builtin): Likewise. ++ * config/rx/rx.md (ssaddsi3): New. ++ (*sat): Rename from sat. Represent the CC_REG input. ++ ++ * config/rx/predicates.md (rshift_operator): New. ++ * config/rx/rx.c (rx_expand_insv): Remove. ++ * config/rx/rx-protos.h: Update. ++ * config/rx/rx.md (*bitset): Rename from bitset. Swap the ashift ++ operand to the canonical position. ++ (*bitset_in_memory, *bitinvert, *bitinvert_in_memory): Similarly. ++ (*bitclr, *bitclr_in_memory): Similarly. ++ (*insv_imm, rx_insv_reg, *insv_cond, *bmcc, *insv_cond_lt): New. ++ (insv): Retain the zero_extract in the expansion. ++ ++ * config/rx/rx.md (bswapsi2): Use = not + for output reload. ++ (bswaphi2, bitinvert, revw): Likewise. ++ ++ * config/rx/rx.c (gen_rx_store_vector): Use VOIDmode for gen_rtx_SET. ++ (gen_rx_rtsd_vector, gen_rx_popm_vector): Likewise. ++ * config/rx/rx.md (pop_and_return): Use VOIDmode for SET. ++ (stack_push, stack_pushm, stack_pop, stack_popm): Likewise. ++ (bitset, bitset_in_memory): Likewise. ++ (bitinvert, bitinvert_in_memory): Likewise. ++ (bitclr, bitclr_in_memory): Likewise. ++ (insv, sync_lock_test_and_setsi, movstr, rx_movstr): Likewise. ++ (rx_strend, rx_cmpstrn): Likewise. ++ (rx_setmem): Likewise. Make the source BLKmode to match the dest. ++ (bitop peep2 patterns): Remove. ++ ++ * config/rx/rx.c (rx_match_ccmode): New. ++ * config/rx/rx-protos.h: Update. ++ * config/rx/rx.md (abssi2): Clobber, don't set flags. ++ (addsi3, adddi3, andsi3, negsi2, one_cmplsi2, iorsi3): Likewise. ++ (rotlsi3, rotrsi3, ashrsi3, lshrsi3, ashlsi3): Likewise. ++ (subsi3, subdi3, xorsi3, addsf3, divsf3, mulsf3, subsf3): Likewise. ++ (fix_truncsfsi2, floatsisf2): Likewise. ++ (*abssi2_flags, *addsi3_flags, *andsi3_flags, *negsi2_flags): New. ++ (*one_cmplsi2_flags, *iorsi3_flags, *rotlsi3_flags): New. ++ (*rotrsi3_flags, *ashrsi3_flags, *lshrsi3_flags, *ashlsi3_flags): New. ++ (*subsi3_flags, *xorsi3_flags): New. ++ ++ * config/rx/rx.md (cstoresf4, *cstoresf4): New patterns. ++ ++ * config/rx/rx.c (rx_print_operand): Remove workaround for ++ unsplit comparison operations. ++ ++ * config/rx/rx.md (movsicc): Split after reload. ++ (*movsicc): Merge *movsieq and *movsine via match_operator. ++ (*stcc): New pattern. ++ ++ * config/rx/rx.c (rx_float_compare_mode): Remove. ++ * config/rx/rx.h (rx_float_compare_mode): Remove. ++ * config/rx/rx.md (cstoresi4): Split after reload. ++ (*sccc): New pattern. ++ ++ * config/rx/predicates.md (label_ref_operand): New. ++ (rx_z_comparison_operator): New. ++ (rx_zs_comparison_operator): New. ++ (rx_fp_comparison_operator): New. ++ * config/rx/rx.c (rx_print_operand) [B]: Examine comparison modes. ++ Validate that the flags are set properly for the comparison. ++ (rx_gen_cond_branch_template): Remove. ++ (rx_cc_modes_compatible): Remove. ++ (mode_from_flags): New. ++ (flags_from_code): Rename from flags_needed_for_conditional. ++ (rx_cc_modes_compatible): Re-write in terms of flags_from_mode. ++ (rx_select_cc_mode): Likewise. ++ (rx_split_fp_compare): New. ++ (rx_split_cbranch): New. ++ * config/rx/rx.md (most_cond, zs_cond): Remove iterators. ++ (*cbranchsi4): Use match_operator and rx_split_cbranch. ++ (*cbranchsf4): Similarly. ++ (*cbranchsi4_tst): Rename from *tstbranchsi4_. Use ++ match_operator and rx_split_cbranch. ++ (*cbranchsi4_tst_ext): Combine *tstbranchsi4m_eq and ++ tstbranchsi4m_ne. Use match_operator and rx_split_cbranch. ++ (*cmpsi): Rename from cmpsi. ++ (*tstsi): Rename from tstsi. ++ (*cmpsf): Rename from cmpsf; use CC_Fmode. ++ (*conditional_branch): Rename from conditional_branch. ++ (*reveresed_conditional_branch): Remove. ++ (b): Remove expander. ++ * config/rx/rx-protos.h: Update. ++ ++ * config/rx/rx.c (rx_compare_redundant): Remove. ++ * config/rx/rx.md (cmpsi): Don't use it. ++ * config/rx/rx-protos.h: Update. ++ ++ * config/rx/rx-modes.def (CC_F): New mode. ++ * config/rx/rx.c (rx_select_cc_mode): New. ++ * config/rx/rx.h (SELECT_CC_MODE): Use it. ++ * config/rx/rx-protos.h: Update. ++ ++2011-02-01 Richard Guenther ++ ++ PR tree-optimization/47541 ++ * tree-ssa-structalias.c (push_fields_onto_fieldstack): Make ++ sure to have a field at offset zero. ++ ++2011-01-31 Nathan Froyd ++ ++ Backport from mainline: ++ 2010-12-30 Nathan Froyd ++ ++ PR target/44606 ++ * reload1.c (choose_reload_regs): Don't look for equivalences for ++ output reloads of constant loads. ++ ++2011-01-30 Gerald Pfeifer ++ ++ * doc/install.texi (hppa-hp-hpux10): Remove references to HP ++ support sites. ++ ++2011-01-30 Gerald Pfeifer ++ ++ * doc/install.texi: Update copyright years. ++ ++2011-01-30 Gerald Pfeifer ++ ++ * doc/install.texi (Binaries): Remove outdated reference for ++ Motorola 68HC11/68HC12 downloads. ++ ++2011-01-30 Gerald Pfeifer ++ ++ * doc/extend.texi (Thread-Local): Adjust reference to Ulrich ++ Drepper's paper. ++ ++2011-01-29 John David Anglin ++ ++ Backport from mainline: ++ 2010-08-22 John David Anglin ++ ++ PR boehm-gc/34544 ++ * gthr-posix.h (__gthread_active_init): Delete. ++ (__gthread_active_p): Do activity check here. ++ Don't include errno.h on hppa-hpux. Update comment. ++ * gthr-posix95.h (__gthread_active_init): Delete. ++ (__gthread_active_p): Do activity check here. ++ Don't include errno.h on hppa-hpux. Update comment. ++ * config.gcc (hppa[12]*-*-hpux11*): Define extra_parts. ++ * config/pa/pa64-hpux.h (LIB_SPEC): When -static is specified, only ++ add -lpthread when -mt or -pthread is specified. ++ * config/pa/pa-hpux11.h (LIB_SPEC): likewise. ++ (LINK_GCC_C_SEQUENCE_SPEC): Define. ++ * config/pa/t-pa-hpux11 (LIBGCCSTUB_OBJS): Define. ++ (stublib.c, pthread_default_stacksize_np-stub.o, ++ pthread_mutex_lock-stub.o, pthread_mutex_unlock-stub.o, ++ $(T)libgcc_stub.a): Add methods. ++ * config/pa/t-pa64 (LIBGCCSTUB_OBJS): Add pthread stubs. ++ (stublib.c, pthread_default_stacksize_np-stub.o, ++ pthread_mutex_lock-stub.o, pthread_mutex_unlock-stub.o): Add methods. ++ * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock, ++ pthread_mutex_unlock): New stubs. ++ ++2011-01-26 Eric Botcazou ++ ++ PR rtl-optimization/44469 ++ * cfgcleanup.c (try_optimize_cfg): Iterate in CFG layout mode too ++ after removing trivially dead basic blocks. ++ ++2011-01-25 Richard Guenther ++ ++ PR tree-optimization/47411 ++ Backport from mainline ++ 2010-06-30 Michael Matz ++ ++ PR bootstrap/44699 ++ * tree-vrp.c (vrp_finalize): Deal with changing num_ssa_names. ++ ++2011-01-21 Ramana Radhakrishnan ++ ++ Backport from mainline. ++ 2010-09-08 Ramana Radhakrishnan ++ ++ PR target/44392 ++ * config/arm/arm.md (bswapsi2): Handle condition correctly ++ for armv6 and optimize_size. ++ ++2011-01-21 Richard Guenther ++ ++ PR tree-optimization/47365 ++ * tree-ssa-sccvn.h (vn_lookup_kind): Declare. ++ (vn_reference_lookup_pieces): Adjust. ++ (vn_reference_lookup): Likewise. ++ * tree-ssa-sccvn.c (vn_walk_kind): New static global. ++ (vn_reference_lookup_3): Only look through kills if in ++ VN_WALKREWRITE mode. ++ (vn_reference_lookup_pieces): Adjust. ++ (vn_reference_lookup): Likewise. ++ (visit_reference_op_load): Likewise. ++ (visit_reference_op_store): Likewise. ++ * tree-ssa-pre.c (phi_translate_1): Use VN_WALK mode. ++ (compute_avail): Likewise. ++ (eliminate): Likewise. ++ ++2011-01-20 Richard Guenther ++ ++ PR tree-optimization/47167 ++ * tree-ssa-copyrename.c (copy_rename_partition_coalesce): ++ Revert previous change, only avoid enumeral type changes. ++ ++2011-01-17 H.J. Lu ++ ++ Backport from mainline ++ 2011-01-17 H.J. Lu ++ ++ PR target/47318 ++ * config/i386/avxintrin.h (_mm_maskload_pd): Change mask to ++ __m128i. ++ (_mm_maskstore_pd): Likewise. ++ (_mm_maskload_ps): Likewise. ++ (_mm_maskstore_ps): Likewise. ++ (_mm256_maskload_pd): Change mask to __m256i. ++ (_mm256_maskstore_pd): Likewise. ++ (_mm256_maskload_ps): Likewise. ++ (_mm256_maskstore_ps): Likewise. ++ ++ * config/i386/i386-builtin-types.def: Updated. ++ (ix86_expand_special_args_builtin): Likewise. ++ ++ * config/i386/i386.c (bdesc_special_args): Update ++ __builtin_ia32_maskloadpd, __builtin_ia32_maskloadps, ++ __builtin_ia32_maskloadpd256, __builtin_ia32_maskloadps256, ++ __builtin_ia32_maskstorepd, __builtin_ia32_maskstoreps, ++ __builtin_ia32_maskstorepd256 and __builtin_ia32_maskstoreps256. ++ ++ * config/i386/sse.md (avx_maskload): ++ Use on mask register. ++ (avx_maskstore): Likewise. ++ ++2011-01-17 Olivier Hainque ++ Michael Haubenwallner ++ Eric Botcazou ++ ++ PR target/46655 ++ * xcoffout.c (ASM_OUTPUT_LINE): Output line only if positive, and only ++ if <= USHRT_MAX in 32-bit mode. ++ ++2011-01-17 Richard Guenther ++ ++ Backport from mainline ++ PR tree-optimization/47286 ++ * tree-ssa-structalias.c (new_var_info): Register variables ++ are global. ++ ++ PR tree-optimization/44592 ++ * tree-ssa-ccp.c (gimplify_and_update_call_from_tree): Copy ++ from trunk. ++ ++2011-01-16 Jakub Jelinek ++ ++ Backport from mainline ++ 2011-01-07 Jakub Jelinek ++ ++ PR target/47201 ++ * config/i386/i386.c (ix86_delegitimize_address): If ++ simplify_gen_subreg fails, return orig_x. ++ ++ 2011-01-06 Jakub Jelinek ++ ++ PR c/47150 ++ * c-convert.c (convert): When converting a complex expression ++ other than COMPLEX_EXPR to a different complex type, ensure ++ c_save_expr is called instead of save_expr, unless in_late_binary_op. ++ * c-typeck.c (convert_for_assignment): Set in_late_binary_op also ++ when converting COMPLEX_TYPE. ++ ++ 2010-12-21 Jakub Jelinek ++ ++ PR target/46880 ++ * config/i386/sse.md (sse2_loadlpd, sse2_movsd): Fix shufpd source ++ operand. ++ ++ PR middle-end/45852 ++ * expr.c (store_expr): Ignore alt_rtl if equal to target, ++ but has side-effects. ++ ++ 2010-12-16 Jakub Jelinek ++ ++ PR tree-optimization/43655 ++ * tree-ssa-ter.c (is_replaceable_p): Don't use ++ gimple_references_memory_p for -O0, instead check for load ++ by looking at rhs. ++ ++ PR debug/46893 ++ * cfgexpand.c (expand_debug_expr): If GET_MODE (op0) is VOIDmode, ++ use TYPE_MODE (TREE_TYPE (tem)) instead of mode1. ++ ++ 2010-12-10 Jakub Jelinek ++ ++ PR rtl-optimization/46804 ++ * regmove.c (optimize_reg_copy_3): Look for REG_EQUAL note ++ on the setter of src_reg rather than on insn. If it is ++ equal to the setter's original SET_SRC, replace it with its ++ zero or sign extension instead of dropping it. ++ ++ PR rtl-optimization/46865 ++ * rtl.c (rtx_equal_p_cb, rtx_equal_p): For last operand of ++ ASM_OPERANDS and ASM_INPUT if integers are different, ++ call locator_eq. ++ * jump.c (rtx_renumbered_equal_p): Likewise. ++ ++ PR tree-optimization/46864 ++ * tree-ssa-loop-im.c (loop_suitable_for_sm): Return false even ++ when there are EDGE_EH exit edges. ++ ++ 2010-12-09 Jakub Jelinek ++ ++ PR target/41082 ++ * config/rs6000/rs6000.c (rs6000_expand_vector_extract): Use stvx ++ instead of stve*x. ++ (altivec_expand_stv_builtin): For op0 use mode of operand 1 instead ++ of operand 0. ++ * config/rs6000/altivec.md (VI_scalar): New mode attr. ++ (altivec_stvex, *altivec_stvesfx): Use scalar instead of ++ vector mode for operand 0, put operand 1 into UNSPEC. ++ ++2011-01-13 Nick Clifton ++ ++ Import this fix from the mainline: ++ 2010-10-19 Nick Clifton ++ ++ * config/rx/rx.c (rx_function_value): Small integer types are ++ promoted to SImode. ++ (rx_promote_function_mode): New function. ++ (TARGET_PROMOTE_FUNCTION_MODE): Define. ++ ++2011-01-07 Rainer Orth ++ ++ Backport from mainline: ++ 2011-01-06 Rainer Orth ++ ++ PR target/43309 ++ * config/i386/i386.c (legitimize_tls_address) ++ : Handle TARGET_64BIT && TARGET_SUN_TLS. ++ * config/i386/i386.md (UNSPEC_TLS_IE_SUN): Declare. ++ (tls_initial_exec_64_sun): New pattern. ++ ++2011-01-03 Eric Botcazou ++ ++ Backport from mainline ++ 2010-12-30 Eric Botcazou ++ ++ PR target/47038 ++ * config/sparc/sparc.c (sparc_file_end): Call resolve_unique_section ++ on the GOT helper if USE_HIDDEN_LINKONCE. ++ ++ 2010-12-02 Eric Botcazou ++ ++ PR target/46685 ++ * config/sparc/sparc.c (can_use_mov_pic_label_ref): New predicate. ++ (sparc_expand_move): Call it to decide whether to emit the special ++ mov{si,di}_pic_label_ref patterns. ++ (sparc_legitimize_pic_address): Call it to decide whether to emit ++ the regular PIC sequence for labels. Fix long line. ++ (sparc_file_end): Set is_thunk for the PIC helper. ++ ++2010-12-30 John David Anglin ++ ++ * config/pa/pa.md: Add ",*" condition to 64-bit add/subtract boolean ++ patterns. ++ ++2010-12-27 Yao Qi ++ ++ Backport from mainline: ++ 2010-10-14 Yao Qi ++ ++ PR target/45447 ++ * config/arm/arm.c (arm_build_builtin_va_list): Assign ++ va_list_name to TYPE_STUB_DECL (va_list_type). ++ ++2010-12-23 Sebastian Pop ++ Richard Guenther ++ ++ PR tree-optimization/46758 ++ * graphite-sese-to-poly.c (scan_tree_for_params_right_scev): Use ++ tree_int_to_gmp instead of int_cst_value. ++ (scan_tree_for_params_int): Same. ++ (scan_tree_for_params): Same. ++ (pdr_add_data_dimensions): Use ppl_set_inhomogeneous_tree. ++ ++2010-12-23 Sebastian Pop ++ ++ Backport from mainline ++ Fix PR45758: reset scevs before Graphite. ++ 2010-09-24 Sebastian Pop ++ ++ PR tree-optimization/45552 ++ * graphite.c (graphite_initialize): Call scev_reset. ++ ++2010-12-23 Sebastian Pop ++ ++ PR tree-optimization/43023 ++ * tree-data-ref.c (mem_write_stride_of_same_size_as_unit_type_p): ++ Removed. ++ (stores_zero_from_loop): Call stmt_stores_zero. ++ (stmt_with_adjacent_zero_store_dr_p): New. ++ * tree-data-ref.h (stmt_with_adjacent_zero_store_dr_p): Declared. ++ (stride_of_unit_type_p): New. ++ * tree-loop-distribution.c (generate_memset_zero): Do not return a ++ boolean. Call gcc_assert on stride_of_unit_type_p. ++ (generate_builtin): Call stmt_stores_zero. ++ (rdg_flag_all_uses): Removed. ++ (rdg_flag_similar_memory_accesses): Removed. ++ (build_rdg_partition_for_component): Removed parameter ++ other_stores. Removed call to rdg_flag_similar_memory_accesses. ++ (can_generate_builtin): New. ++ (similar_memory_accesses): New. ++ (fuse_partitions_with_similar_memory_accesses): New. ++ (rdg_build_partitions): Call ++ fuse_partitions_with_similar_memory_accesses. ++ ++2010-12-21 Martin Jambor ++ ++ Backport from mainline: ++ 2010-12-09 Martin Jambor ++ ++ PR middle-end/46734 ++ * tree-sra.c (splice_param_accesses): Check that there are not ++ multiple ADDRESSABLE types. ++ ++2010-12-19 John David Anglin ++ ++ Backport from mainline: ++ 2010-12-18 John David Anglin ++ ++ PR target/46915 ++ * config/pa/pa.c (branch_to_delay_slot_p): Use next_active_insn instead ++ of next_real_insn. Search forward checking for both ASM_INPUT and ++ ASM_OPERANDS asms until exit condition is found. ++ (branch_needs_nop_p): Likewise. ++ (use_skip_p): New function. ++ (output_cbranch): Use use_skip_p. ++ (output_bb, output_bvb): Likewise. ++ ++2010-12-19 Eric Botcazou ++ ++ PR target/46729 ++ * config/sparc/sparc.h (GLOBAL_OFFSET_TABLE_REGNUM): New macro. ++ (PIC_OFFSET_TABLE_REGNUM): Rewrite in terms of above macro. ++ * config/sparc/sparc.c (pic_helper_needed): Delete. ++ (global_offset_table): Likewise. ++ (pic_helper_symbol): Rename to... ++ (got_helper_rtx): ...this. ++ (global_offset_table_rtx): New global variable. ++ (sparc_got_symbol): Likewise. ++ (sparc_got): New static function. ++ (check_pic): Use local variable and call sparc_got. ++ (sparc_tls_symbol): Initialize to NULL_RTX. ++ (sparc_tls_got): In non-PIC mode, reload the GOT register for Sun TLS ++ and 32-bit ABI and copy the GOT symbol to a new register otherwise. ++ (get_pc_thunk_name): Rename local variable. ++ (gen_load_pcrel_sym): New wrapper around load_pcrel_sym{si,di}. ++ (load_pic_register): Rename to... ++ (load_got_register): ...this. Adjust and call gen_load_pcrel_sym. ++ (sparc_expand_prologue): Do not test flag_pic. ++ (sparc_output_mi_thunk): Use pic_offset_table_rtx directly. ++ (sparc_file_end): Test got_helper_rtx instead of pic_helper_needed. ++ Rename local variable and do not call get_pc_thunk_name again. ++ * config/sparc/sparc.md (load_pcrel_sym): Add operand #3. ++ ++2010-12-18 Alexandre Oliva ++ ++ PR debug/46756 ++ * jump.c (mark_all_labels): Skip debug insns. ++ ++2010-12-18 Alexandre Oliva ++ ++ PR debug/46782 ++ * cfgcleanup.c (try_forward_edges): Skip debug insns. ++ ++2010-12-16 Eric Botcazou ++ ++ * tree-ssa-sccvn.c (vn_reference_lookup_3): Always punt if the call to ++ get_ref_base_and_extent returns -1 as the max size. ++ + 2010-12-16 Release Manager + + * GCC 4.5.2 released. +@@ -106,7 +785,7 @@ + + Backport from mainline: + 2010-09-15 Olivier Hainque +- Jose Ruiz ++ Jose Ruiz + + * config/alpha/osf.h (MD_UNWIND_SUPPORT): Define. + * config/alpha/osf-unwind.h: New file. +--- a/src/gcc/DATESTAMP ++++ b/src/gcc/DATESTAMP +@@ -1 +1 @@ +-20101216 ++20110221 +--- a/src/gcc/LINARO-VERSION ++++ b/src/gcc/LINARO-VERSION +@@ -0,0 +1 @@ ++4.5-2011.02-dev1 +--- a/src/gcc/Makefile.in ++++ b/src/gcc/Makefile.in +@@ -646,6 +646,7 @@ + LIBGCC2_CFLAGS = -O2 $(LIBGCC2_INCLUDES) $(GCC_CFLAGS) $(TARGET_LIBGCC2_CFLAGS) \ + $(LIBGCC2_DEBUG_CFLAGS) $(GTHREAD_FLAGS) \ + -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED \ ++ -fno-stack-protector \ + $(INHIBIT_LIBC_CFLAGS) + + # Additional options to use when compiling libgcc2.a. +@@ -659,6 +660,7 @@ + CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \ + -finhibit-size-directive -fno-inline -fno-exceptions \ + -fno-zero-initialized-in-bss -fno-toplevel-reorder -fno-tree-vectorize \ ++ -fno-stack-protector \ + $(INHIBIT_LIBC_CFLAGS) + + # Additional sources to handle exceptions; overridden by targets as needed. +@@ -1192,6 +1194,7 @@ + dse.o \ + dwarf2asm.o \ + dwarf2out.o \ ++ ee.o \ + ebitmap.o \ + emit-rtl.o \ + et-forest.o \ +@@ -1347,6 +1350,7 @@ + tree-profile.o \ + tree-scalar-evolution.o \ + tree-sra.o \ ++ tree-if-switch-conversion.o \ + tree-switch-conversion.o \ + tree-ssa-address.o \ + tree-ssa-alias.o \ +@@ -1965,7 +1969,7 @@ + + incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \ + intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \ +- $(MACHMODE_H) ++ $(MACHMODE_H) $(FLAGS_H) toplev.h + + c-decl.o : c-decl.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) \ + $(RTL_H) $(C_TREE_H) $(GGC_H) $(TARGET_H) $(FLAGS_H) $(FUNCTION_H) output.h \ +@@ -2963,6 +2967,11 @@ + web.o : web.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \ + hard-reg-set.h $(FLAGS_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \ + $(DF_H) $(OBSTACK_H) $(TIMEVAR_H) $(TREE_PASS_H) ++ee.o : ee.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \ ++ hard-reg-set.h $(FLAGS_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h \ ++ $(DF_H) $(TIMEVAR_H) tree-pass.h $(RECOG_H) $(EXPR_H) \ ++ $(REGS_H) $(TREE_H) $(TM_P_H) insn-config.h $(INSN_ATTR_H) $(TOPLEV_H) $(DIAGNOSTIC_CORE_H) \ ++ $(TARGET_H) $(OPTABS_H) insn-codes.h rtlhooks-def.h $(PARAMS_H) $(CGRAPH_H) + gcse.o : gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \ + $(REGS_H) hard-reg-set.h $(FLAGS_H) $(REAL_H) insn-config.h $(GGC_H) \ + $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \ +@@ -3001,6 +3010,11 @@ + $(TM_H) $(TREE_H) $(GIMPLE_H) $(CGRAPH_H) $(TREE_FLOW_H) $(IPA_PROP_H) \ + $(DIAGNOSTIC_H) statistics.h $(TREE_DUMP_H) $(TIMEVAR_H) $(PARAMS_H) \ + $(TARGET_H) $(FLAGS_H) $(EXPR_H) $(TREE_INLINE_H) ++tree-if-switch-conversion.o : tree-if-switch-conversion.c $(CONFIG_H) \ ++ $(SYSTEM_H) $(TREE_H) $(TM_P_H) $(TREE_FLOW_H) $(DIAGNOSTIC_H) \ ++ $(TREE_INLINE_H) $(TIMEVAR_H) $(TM_H) coretypes.h $(TREE_DUMP_H) \ ++ $(GIMPLE_H) $(TREE_PASS_H) $(FLAGS_H) $(EXPR_H) $(BASIC_BLOCK_H) output.h \ ++ $(GGC_H) $(OBSTACK_H) $(PARAMS_H) $(CPPLIB_H) $(PARAMS_H) + tree-switch-conversion.o : tree-switch-conversion.c $(CONFIG_H) $(SYSTEM_H) \ + $(TREE_H) $(TM_P_H) $(TREE_FLOW_H) $(DIAGNOSTIC_H) $(TREE_INLINE_H) \ + $(TIMEVAR_H) $(TM_H) coretypes.h $(TREE_DUMP_H) $(GIMPLE_H) \ +@@ -3155,7 +3169,7 @@ + $(RTL_H) $(REAL_H) $(FLAGS_H) $(EXPR_H) $(OPTABS_H) reload.h $(REGS_H) \ + hard-reg-set.h insn-config.h $(BASIC_BLOCK_H) $(RECOG_H) output.h \ + $(FUNCTION_H) $(TOPLEV_H) cselib.h $(TM_P_H) $(EXCEPT_H) $(TREE_H) $(MACHMODE_H) \ +- $(OBSTACK_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H) ++ $(OBSTACK_H) $(TARGET_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H) + postreload-gcse.o : postreload-gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ + $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) insn-config.h \ + $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \ +@@ -3193,7 +3207,7 @@ + ira-costs.o: ira-costs.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ + hard-reg-set.h $(RTL_H) $(EXPR_H) $(TM_P_H) $(FLAGS_H) $(BASIC_BLOCK_H) \ + $(REGS_H) addresses.h insn-config.h $(RECOG_H) $(TOPLEV_H) $(TARGET_H) \ +- $(PARAMS_H) $(IRA_INT_H) ++ $(PARAMS_H) $(IRA_INT_H) reload.h + ira-conflicts.o: ira-conflicts.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ + $(TARGET_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) \ + insn-config.h $(RECOG_H) $(BASIC_BLOCK_H) $(TOPLEV_H) $(TM_P_H) $(PARAMS_H) \ +--- a/src/gcc/ada/ChangeLog ++++ b/src/gcc/ada/ChangeLog +@@ -1,3 +1,18 @@ ++2011-02-12 Gerald Pfeifer ++ ++ * gnat_ugn.texi (Compiling Different Versions of Ada): Update ++ link to "Ada Issues". ++ ++2011-02-08 Eric Botcazou ++ ++ * gcc-interface/Makefile.in (x86-64 darwin): Handle multilibs. ++ ++2011-01-04 Eric Botcazou ++ ++ * gcc-interface/trans.c (Subprogram_Body_to_gnu): Evaluate the ++ expressions of the parameter cache within the statement group of ++ the CICO mechanism. ++ + 2010-12-16 Release Manager + + * GCC 4.5.2 released. +--- a/src/gcc/ada/gcc-interface/Makefile.in ++++ b/src/gcc/ada/gcc-interface/Makefile.in +@@ -2143,11 +2143,17 @@ + s-taprop.adblanguage->parm_attr_cache; ++ if (cache) ++ { ++ struct parm_attr_d *pa; ++ int i; ++ ++ start_stmt_group (); ++ ++ for (i = 0; VEC_iterate (parm_attr, cache, i, pa); i++) ++ { ++ if (pa->first) ++ add_stmt_with_node (pa->first, gnat_node); ++ if (pa->last) ++ add_stmt_with_node (pa->last, gnat_node); ++ if (pa->length) ++ add_stmt_with_node (pa->length, gnat_node); ++ } ++ ++ add_stmt (gnu_result); ++ gnu_result = end_stmt_group (); ++ } ++ + /* If we are dealing with a return from an Ada procedure with parameters + passed by copy-in/copy-out, we need to return a record containing the + final values of these parameters. If the list contains only one entry, +@@ -2341,30 +2366,6 @@ + + pop_stack (&gnu_return_label_stack); + +- /* If we populated the parameter attributes cache, we need to make sure +- that the cached expressions are evaluated on all possible paths. */ +- cache = DECL_STRUCT_FUNCTION (gnu_subprog_decl)->language->parm_attr_cache; +- if (cache) +- { +- struct parm_attr_d *pa; +- int i; +- +- start_stmt_group (); +- +- for (i = 0; VEC_iterate (parm_attr, cache, i, pa); i++) +- { +- if (pa->first) +- add_stmt_with_node (pa->first, gnat_node); +- if (pa->last) +- add_stmt_with_node (pa->last, gnat_node); +- if (pa->length) +- add_stmt_with_node (pa->length, gnat_node); +- } +- +- add_stmt (gnu_result); +- gnu_result = end_stmt_group (); +- } +- + /* Set the end location. */ + Sloc_to_locus + ((Present (End_Label (Handled_Statement_Sequence (gnat_node))) +--- a/src/gcc/attribs.c ++++ b/src/gcc/attribs.c +@@ -278,6 +278,19 @@ + TREE_VALUE (cur_attr) = chainon (opts, TREE_VALUE (cur_attr)); + } + ++ /* A "naked" function attribute implies "noinline" and "noclone" for ++ those targets that support it. */ ++ if (TREE_CODE (*node) == FUNCTION_DECL ++ && lookup_attribute_spec (get_identifier ("naked")) ++ && lookup_attribute ("naked", attributes) != NULL) ++ { ++ if (lookup_attribute ("noinline", attributes) == NULL) ++ attributes = tree_cons (get_identifier ("noinline"), NULL, attributes); ++ ++ if (lookup_attribute ("noclone", attributes) == NULL) ++ attributes = tree_cons (get_identifier ("noclone"), NULL, attributes); ++ } ++ + targetm.insert_attributes (*node, &attributes); + + for (a = attributes; a; a = TREE_CHAIN (a)) +--- a/src/gcc/auto-inc-dec.c ++++ b/src/gcc/auto-inc-dec.c +@@ -1068,7 +1068,7 @@ + /* For the post_add to work, the result_reg of the inc must not be + used in the mem insn since this will become the new index + register. */ +- if (count_occurrences (PATTERN (mem_insn.insn), inc_insn.reg_res, 1) != 0) ++ if (reg_overlap_mentioned_p (inc_insn.reg_res, PATTERN (mem_insn.insn))) + { + if (dump_file) + fprintf (dump_file, "base reg replacement failure.\n"); +--- a/src/gcc/basic-block.h ++++ b/src/gcc/basic-block.h +@@ -884,6 +884,7 @@ + + /* In cfgrtl.c */ + extern basic_block force_nonfallthru (edge); ++extern basic_block force_nonfallthru_and_redirect (edge, basic_block, rtx); + extern rtx block_label (basic_block); + extern bool purge_all_dead_edges (void); + extern bool purge_dead_edges (basic_block); +@@ -894,6 +895,10 @@ + + /* In cfgcleanup.c. */ + extern bool cleanup_cfg (int); ++extern int flow_find_cross_jump (basic_block, basic_block, rtx *, rtx *); ++extern int flow_find_head_matching_sequence (basic_block, basic_block, ++ rtx *, rtx *, int); ++ + extern bool delete_unreachable_blocks (void); + + extern bool mark_dfs_back_edges (void); +@@ -932,6 +937,8 @@ + extern VEC (basic_block, heap) *get_dominated_by_region (enum cdi_direction, + basic_block *, + unsigned); ++extern VEC (basic_block, heap) *get_dominated_to_depth (enum cdi_direction, ++ basic_block, int); + extern VEC (basic_block, heap) *get_all_dominated_blocks (enum cdi_direction, + basic_block); + extern void add_to_dominance_info (enum cdi_direction, basic_block); +@@ -998,6 +1005,20 @@ + return false; + } + ++/* Return the fallthru edge in EDGES if it exists, NULL otherwise. */ ++static inline edge ++find_fallthru_edge (VEC(edge,gc) *edges) ++{ ++ edge e; ++ edge_iterator ei; ++ ++ FOR_EACH_EDGE (e, ei, edges) ++ if (e->flags & EDGE_FALLTHRU) ++ break; ++ ++ return e; ++} ++ + /* In cfgloopmanip.c. */ + extern edge mfb_kj_edge; + extern bool mfb_keep_just (edge); +--- a/src/gcc/builtins.c ++++ b/src/gcc/builtins.c +@@ -13666,3 +13666,123 @@ + break; + } + } ++ ++/* Return true if DECL is a builtin that expands to a constant or similarly ++ simple code. */ ++bool ++is_simple_builtin (tree decl) ++{ ++ if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL) ++ switch (DECL_FUNCTION_CODE (decl)) ++ { ++ /* Builtins that expand to constants. */ ++ case BUILT_IN_CONSTANT_P: ++ case BUILT_IN_EXPECT: ++ case BUILT_IN_OBJECT_SIZE: ++ case BUILT_IN_UNREACHABLE: ++ /* Simple register moves or loads from stack. */ ++ case BUILT_IN_RETURN_ADDRESS: ++ case BUILT_IN_EXTRACT_RETURN_ADDR: ++ case BUILT_IN_FROB_RETURN_ADDR: ++ case BUILT_IN_RETURN: ++ case BUILT_IN_AGGREGATE_INCOMING_ADDRESS: ++ case BUILT_IN_FRAME_ADDRESS: ++ case BUILT_IN_VA_END: ++ case BUILT_IN_STACK_SAVE: ++ case BUILT_IN_STACK_RESTORE: ++ /* Exception state returns or moves registers around. */ ++ case BUILT_IN_EH_FILTER: ++ case BUILT_IN_EH_POINTER: ++ case BUILT_IN_EH_COPY_VALUES: ++ return true; ++ ++ default: ++ return false; ++ } ++ ++ return false; ++} ++ ++/* Return true if DECL is a builtin that is not expensive, i.e., they are ++ most probably expanded inline into reasonably simple code. This is a ++ superset of is_simple_builtin. */ ++bool ++is_inexpensive_builtin (tree decl) ++{ ++ if (!decl) ++ return false; ++ else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_MD) ++ return true; ++ else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL) ++ switch (DECL_FUNCTION_CODE (decl)) ++ { ++ case BUILT_IN_ABS: ++ case BUILT_IN_ALLOCA: ++ case BUILT_IN_BSWAP32: ++ case BUILT_IN_BSWAP64: ++ case BUILT_IN_CLZ: ++ case BUILT_IN_CLZIMAX: ++ case BUILT_IN_CLZL: ++ case BUILT_IN_CLZLL: ++ case BUILT_IN_CTZ: ++ case BUILT_IN_CTZIMAX: ++ case BUILT_IN_CTZL: ++ case BUILT_IN_CTZLL: ++ case BUILT_IN_FFS: ++ case BUILT_IN_FFSIMAX: ++ case BUILT_IN_FFSL: ++ case BUILT_IN_FFSLL: ++ case BUILT_IN_IMAXABS: ++ case BUILT_IN_FINITE: ++ case BUILT_IN_FINITEF: ++ case BUILT_IN_FINITEL: ++ case BUILT_IN_FINITED32: ++ case BUILT_IN_FINITED64: ++ case BUILT_IN_FINITED128: ++ case BUILT_IN_FPCLASSIFY: ++ case BUILT_IN_ISFINITE: ++ case BUILT_IN_ISINF_SIGN: ++ case BUILT_IN_ISINF: ++ case BUILT_IN_ISINFF: ++ case BUILT_IN_ISINFL: ++ case BUILT_IN_ISINFD32: ++ case BUILT_IN_ISINFD64: ++ case BUILT_IN_ISINFD128: ++ case BUILT_IN_ISNAN: ++ case BUILT_IN_ISNANF: ++ case BUILT_IN_ISNANL: ++ case BUILT_IN_ISNAND32: ++ case BUILT_IN_ISNAND64: ++ case BUILT_IN_ISNAND128: ++ case BUILT_IN_ISNORMAL: ++ case BUILT_IN_ISGREATER: ++ case BUILT_IN_ISGREATEREQUAL: ++ case BUILT_IN_ISLESS: ++ case BUILT_IN_ISLESSEQUAL: ++ case BUILT_IN_ISLESSGREATER: ++ case BUILT_IN_ISUNORDERED: ++ case BUILT_IN_VA_ARG_PACK: ++ case BUILT_IN_VA_ARG_PACK_LEN: ++ case BUILT_IN_VA_COPY: ++ case BUILT_IN_TRAP: ++ case BUILT_IN_SAVEREGS: ++ case BUILT_IN_POPCOUNTL: ++ case BUILT_IN_POPCOUNTLL: ++ case BUILT_IN_POPCOUNTIMAX: ++ case BUILT_IN_POPCOUNT: ++ case BUILT_IN_PARITYL: ++ case BUILT_IN_PARITYLL: ++ case BUILT_IN_PARITYIMAX: ++ case BUILT_IN_PARITY: ++ case BUILT_IN_LABS: ++ case BUILT_IN_LLABS: ++ case BUILT_IN_PREFETCH: ++ return true; ++ ++ default: ++ return is_simple_builtin (decl); ++ } ++ ++ return false; ++} ++ +--- a/src/gcc/c-common.c ++++ b/src/gcc/c-common.c +@@ -9196,6 +9196,40 @@ + } + } + ++/* RESULT_TYPE is the result of converting TYPE1 and TYPE2 to a common ++ type via c_common_type. If -Wdouble-promotion is in use, and the ++ conditions for warning have been met, issue a warning. GMSGID is ++ the warning message. It must have two %T specifiers for the type ++ that was converted (generally "float") and the type to which it was ++ converted (generally "double), respectively. LOC is the location ++ to which the awrning should refer. */ ++ ++void ++do_warn_double_promotion (tree result_type, tree type1, tree type2, ++ const char *gmsgid, location_t loc) ++{ ++ tree source_type; ++ ++ if (!warn_double_promotion) ++ return; ++ /* If the conversion will not occur at run-time, there is no need to ++ warn about it. */ ++ if (c_inhibit_evaluation_warnings) ++ return; ++ if (TYPE_MAIN_VARIANT (result_type) != double_type_node ++ && TYPE_MAIN_VARIANT (result_type) != complex_double_type_node) ++ return; ++ if (TYPE_MAIN_VARIANT (type1) == float_type_node ++ || TYPE_MAIN_VARIANT (type1) == complex_float_type_node) ++ source_type = type1; ++ else if (TYPE_MAIN_VARIANT (type2) == float_type_node ++ || TYPE_MAIN_VARIANT (type2) == complex_float_type_node) ++ source_type = type2; ++ else ++ return; ++ warning_at (loc, OPT_Wdouble_promotion, gmsgid, source_type, result_type); ++} ++ + /* Setup a TYPE_DECL node as a typedef representation. + + X is a TYPE_DECL for a typedef statement. Create a brand new +--- a/src/gcc/c-common.h ++++ b/src/gcc/c-common.h +@@ -1057,6 +1057,8 @@ + tree op0, tree op1, + tree result_type, + enum tree_code resultcode); ++extern void do_warn_double_promotion (tree, tree, tree, const char *, ++ location_t); + extern void set_underlying_type (tree x); + extern bool is_typedef_decl (tree x); + extern VEC(tree,gc) *make_tree_vector (void); +--- a/src/gcc/c-convert.c ++++ b/src/gcc/c-convert.c +@@ -131,6 +131,32 @@ + goto maybe_fold; + + case COMPLEX_TYPE: ++ /* If converting from COMPLEX_TYPE to a different COMPLEX_TYPE ++ and e is not COMPLEX_EXPR, convert_to_complex uses save_expr, ++ but for the C FE c_save_expr needs to be called instead. */ ++ if (TREE_CODE (TREE_TYPE (e)) == COMPLEX_TYPE) ++ { ++ tree subtype = TREE_TYPE (type); ++ tree elt_type = TREE_TYPE (TREE_TYPE (e)); ++ ++ if (TYPE_MAIN_VARIANT (elt_type) != TYPE_MAIN_VARIANT (subtype) ++ && TREE_CODE (e) != COMPLEX_EXPR) ++ { ++ if (in_late_binary_op) ++ e = save_expr (e); ++ else ++ e = c_save_expr (e); ++ ret ++ = fold_build2 (COMPLEX_EXPR, type, ++ convert (subtype, ++ fold_build1 (REALPART_EXPR, ++ elt_type, e)), ++ convert (subtype, ++ fold_build1 (IMAGPART_EXPR, ++ elt_type, e))); ++ goto maybe_fold; ++ } ++ } + ret = convert_to_complex (type, e); + goto maybe_fold; + +--- a/src/gcc/c-typeck.c ++++ b/src/gcc/c-typeck.c +@@ -3005,8 +3005,15 @@ + if (type_generic) + parmval = val; + else +- /* Convert `float' to `double'. */ +- parmval = convert (double_type_node, val); ++ { ++ /* Convert `float' to `double'. */ ++ if (warn_double_promotion && !c_inhibit_evaluation_warnings) ++ warning (OPT_Wdouble_promotion, ++ "implicit conversion from %qT to %qT when passing " ++ "argument to function", ++ valtype, double_type_node); ++ parmval = convert (double_type_node, val); ++ } + } + else if (excess_precision && !type_generic) + /* A "double" argument with excess precision being passed +@@ -4029,6 +4036,10 @@ + || code2 == COMPLEX_TYPE)) + { + result_type = c_common_type (type1, type2); ++ do_warn_double_promotion (result_type, type1, type2, ++ "implicit conversion from %qT to %qT to " ++ "match other result of conditional", ++ colon_loc); + + /* If -Wsign-compare, warn here if type1 and type2 have + different signedness. We'll promote the signed to unsigned +@@ -5025,10 +5036,10 @@ + { + tree ret; + bool save = in_late_binary_op; +- if (codel == BOOLEAN_TYPE) ++ if (codel == BOOLEAN_TYPE || codel == COMPLEX_TYPE) + in_late_binary_op = true; + ret = convert_and_check (type, orig_rhs); +- if (codel == BOOLEAN_TYPE) ++ if (codel == BOOLEAN_TYPE || codel == COMPLEX_TYPE) + in_late_binary_op = save; + return ret; + } +@@ -9605,6 +9616,11 @@ + if (shorten || common || short_compare) + { + result_type = c_common_type (type0, type1); ++ do_warn_double_promotion (result_type, type0, type1, ++ "implicit conversion from %qT to %qT " ++ "to match other operand of binary " ++ "expression", ++ location); + if (result_type == error_mark_node) + return error_mark_node; + } +--- a/src/gcc/c.opt ++++ b/src/gcc/c.opt +@@ -265,6 +265,10 @@ + Wimplicit + C ObjC C++ ObjC++ Warning + ++Wdouble-promotion ++C ObjC C++ ObjC++ Var(warn_double_promotion) Warning ++Warn about implicit conversions from \"float\" to \"double\" ++ + Wimplicit-function-declaration + C ObjC Var(warn_implicit_function_declaration) Init(-1) Warning + Warn about implicit function declarations +--- a/src/gcc/calls.c ++++ b/src/gcc/calls.c +@@ -703,7 +703,9 @@ + + For small register classes, also do this if this call uses + register parameters. This is to avoid reload conflicts while +- loading the parameters registers. */ ++ loading the parameters registers. ++ ++ Avoid creating the extra move if optimizing for size. */ + + else if ((! (REG_P (args[i].value) + || (GET_CODE (args[i].value) == SUBREG +@@ -711,6 +713,7 @@ + && args[i].mode != BLKmode + && rtx_cost (args[i].value, SET, optimize_insn_for_speed_p ()) + > COSTS_N_INSNS (1) ++ && !optimize_size + && ((SMALL_REGISTER_CLASSES && *reg_parm_seen) + || optimize)) + args[i].value = copy_to_mode_reg (args[i].mode, args[i].value); +@@ -875,7 +878,7 @@ + int bitsize = MIN (bytes * BITS_PER_UNIT, BITS_PER_WORD); + + args[i].aligned_regs[j] = reg; +- word = extract_bit_field (word, bitsize, 0, 1, NULL_RTX, ++ word = extract_bit_field (word, bitsize, 0, 1, false, NULL_RTX, + word_mode, word_mode); + + /* There is no need to restrict this code to loading items +@@ -4045,8 +4048,17 @@ + /* We need to make a save area. */ + unsigned int size = arg->locate.size.constant * BITS_PER_UNIT; + enum machine_mode save_mode = mode_for_size (size, MODE_INT, 1); +- rtx adr = memory_address (save_mode, XEXP (arg->stack_slot, 0)); +- rtx stack_area = gen_rtx_MEM (save_mode, adr); ++ rtx adr; ++ rtx stack_area; ++ ++ /* We can only use save_mode if the arg is sufficiently ++ aligned. */ ++ if (STRICT_ALIGNMENT ++ && GET_MODE_ALIGNMENT (save_mode) > arg->locate.boundary) ++ save_mode = BLKmode; ++ ++ adr = memory_address (save_mode, XEXP (arg->stack_slot, 0)); ++ stack_area = gen_rtx_MEM (save_mode, adr); + + if (save_mode == BLKmode) + { +--- a/src/gcc/cfganal.c ++++ b/src/gcc/cfganal.c +@@ -271,6 +271,37 @@ + EDGE_SUCC (bb, 0)->flags |= EDGE_CAN_FALLTHRU; + EDGE_SUCC (bb, 1)->flags |= EDGE_CAN_FALLTHRU; + } ++ /* dwarf2out expects that a NOTE_INSN_EPILOGUE_BEGIN is always paired ++ with a return or a sibcall. Ensure that this remains the case if ++ they are in different basic blocks. */ ++ FOR_EACH_BB (bb) ++ { ++ edge e; ++ edge_iterator ei; ++ rtx insn, end; ++ ++ end = BB_END (bb); ++ FOR_BB_INSNS (bb, insn) ++ if (GET_CODE (insn) == NOTE ++ && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG ++ && !(CALL_P (end) && SIBLING_CALL_P (end)) ++ && !returnjump_p (end)) ++ { ++ basic_block other_bb = NULL; ++ FOR_EACH_EDGE (e, ei, bb->succs) ++ { ++ if (e->flags & EDGE_FALLTHRU) ++ other_bb = e->dest; ++ else ++ e->flags &= ~EDGE_CAN_FALLTHRU; ++ } ++ FOR_EACH_EDGE (e, ei, other_bb->preds) ++ { ++ if (!(e->flags & EDGE_FALLTHRU)) ++ e->flags &= ~EDGE_CAN_FALLTHRU; ++ } ++ } ++ } + } + + /* Find unreachable blocks. An unreachable block will have 0 in +--- a/src/gcc/cfgcleanup.c ++++ b/src/gcc/cfgcleanup.c +@@ -68,7 +68,6 @@ + static bool try_crossjump_to_edge (int, edge, edge); + static bool try_crossjump_bb (int, basic_block); + static bool outgoing_edges_match (int, basic_block, basic_block); +-static int flow_find_cross_jump (int, basic_block, basic_block, rtx *, rtx *); + static bool old_insns_match_p (int, rtx, rtx); + + static void merge_blocks_move_predecessor_nojumps (basic_block, basic_block); +@@ -482,15 +481,20 @@ + /* When not optimizing, ensure that edges or forwarder + blocks with different locus are not optimized out. */ + int locus = single_succ_edge (target)->goto_locus; ++ rtx last ; + + if (locus && goto_locus && !locator_eq (locus, goto_locus)) + counter = n_basic_blocks; + else if (locus) + goto_locus = locus; + +- if (INSN_P (BB_END (target))) ++ last = BB_END (target); ++ if (DEBUG_INSN_P (last)) ++ last = prev_nondebug_insn (last); ++ ++ if (last && INSN_P (last)) + { +- locus = INSN_LOCATOR (BB_END (target)); ++ locus = INSN_LOCATOR (last); + + if (locus && goto_locus + && !locator_eq (locus, goto_locus)) +@@ -972,13 +976,27 @@ + be filled that clobbers a parameter expected by the subroutine. + + ??? We take the simple route for now and assume that if they're +- equal, they were constructed identically. */ ++ equal, they were constructed identically. ++ ++ Also check for identical exception regions. */ + +- if (CALL_P (i1) +- && (!rtx_equal_p (CALL_INSN_FUNCTION_USAGE (i1), ++ if (CALL_P (i1)) ++ { ++ /* Ensure the same EH region. */ ++ rtx n1 = find_reg_note (i1, REG_EH_REGION, 0); ++ rtx n2 = find_reg_note (i2, REG_EH_REGION, 0); ++ ++ if (!n1 && n2) ++ return false; ++ ++ if (n1 && (!n2 || XEXP (n1, 0) != XEXP (n2, 0))) ++ return false; ++ ++ if (!rtx_equal_p (CALL_INSN_FUNCTION_USAGE (i1), + CALL_INSN_FUNCTION_USAGE (i2)) +- || SIBLING_CALL_P (i1) != SIBLING_CALL_P (i2))) +- return false; ++ || SIBLING_CALL_P (i1) != SIBLING_CALL_P (i2)) ++ return false; ++ } + + #ifdef STACK_REGS + /* If cross_jump_death_matters is not 0, the insn's mode +@@ -1017,6 +1035,29 @@ + return false; + } + ++/* When comparing insns I1 and I2 in flow_find_cross_jump or ++ flow_find_head_matching_sequence, ensure the notes match. */ ++ ++static void ++merge_notes (rtx i1, rtx i2) ++{ ++ /* If the merged insns have different REG_EQUAL notes, then ++ remove them. */ ++ rtx equiv1 = find_reg_equal_equiv_note (i1); ++ rtx equiv2 = find_reg_equal_equiv_note (i2); ++ ++ if (equiv1 && !equiv2) ++ remove_note (i1, equiv1); ++ else if (!equiv1 && equiv2) ++ remove_note (i2, equiv2); ++ else if (equiv1 && equiv2 ++ && !rtx_equal_p (XEXP (equiv1, 0), XEXP (equiv2, 0))) ++ { ++ remove_note (i1, equiv1); ++ remove_note (i2, equiv2); ++ } ++} ++ + /* Look through the insns at the end of BB1 and BB2 and find the longest + sequence that are equivalent. Store the first insns for that sequence + in *F1 and *F2 and return the sequence length. +@@ -1024,9 +1065,8 @@ + To simplify callers of this function, if the blocks match exactly, + store the head of the blocks in *F1 and *F2. */ + +-static int +-flow_find_cross_jump (int mode ATTRIBUTE_UNUSED, basic_block bb1, +- basic_block bb2, rtx *f1, rtx *f2) ++int ++flow_find_cross_jump (basic_block bb1, basic_block bb2, rtx *f1, rtx *f2) + { + rtx i1, i2, last1, last2, afterlast1, afterlast2; + int ninsns = 0; +@@ -1066,7 +1106,7 @@ + if (i1 == BB_HEAD (bb1) || i2 == BB_HEAD (bb2)) + break; + +- if (!old_insns_match_p (mode, i1, i2)) ++ if (!old_insns_match_p (0, i1, i2)) + break; + + merge_memattrs (i1, i2); +@@ -1074,21 +1114,7 @@ + /* Don't begin a cross-jump with a NOTE insn. */ + if (INSN_P (i1)) + { +- /* If the merged insns have different REG_EQUAL notes, then +- remove them. */ +- rtx equiv1 = find_reg_equal_equiv_note (i1); +- rtx equiv2 = find_reg_equal_equiv_note (i2); +- +- if (equiv1 && !equiv2) +- remove_note (i1, equiv1); +- else if (!equiv1 && equiv2) +- remove_note (i2, equiv2); +- else if (equiv1 && equiv2 +- && !rtx_equal_p (XEXP (equiv1, 0), XEXP (equiv2, 0))) +- { +- remove_note (i1, equiv1); +- remove_note (i2, equiv2); +- } ++ merge_notes (i1, i2); + + afterlast1 = last1, afterlast2 = last2; + last1 = i1, last2 = i2; +@@ -1130,6 +1156,97 @@ + return ninsns; + } + ++/* Like flow_find_cross_jump, except start looking for a matching sequence from ++ the head of the two blocks. Do not include jumps at the end. ++ If STOP_AFTER is nonzero, stop after finding that many matching ++ instructions. */ ++ ++int ++flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1, ++ rtx *f2, int stop_after) ++{ ++ rtx i1, i2, last1, last2, beforelast1, beforelast2; ++ int ninsns = 0; ++ edge e; ++ edge_iterator ei; ++ int nehedges1 = 0, nehedges2 = 0; ++ ++ FOR_EACH_EDGE (e, ei, bb1->succs) ++ if (e->flags & EDGE_EH) ++ nehedges1++; ++ FOR_EACH_EDGE (e, ei, bb2->succs) ++ if (e->flags & EDGE_EH) ++ nehedges2++; ++ ++ i1 = BB_HEAD (bb1); ++ i2 = BB_HEAD (bb2); ++ last1 = beforelast1 = last2 = beforelast2 = NULL_RTX; ++ ++ while (true) ++ { ++ ++ /* Ignore notes. */ ++ while (!NONDEBUG_INSN_P (i1) && i1 != BB_END (bb1)) ++ i1 = NEXT_INSN (i1); ++ ++ while (!NONDEBUG_INSN_P (i2) && i2 != BB_END (bb2)) ++ i2 = NEXT_INSN (i2); ++ ++ if (NOTE_P (i1) || NOTE_P (i2) ++ || JUMP_P (i1) || JUMP_P (i2)) ++ break; ++ ++ /* A sanity check to make sure we're not merging insns with different ++ effects on EH. If only one of them ends a basic block, it shouldn't ++ have an EH edge; if both end a basic block, there should be the same ++ number of EH edges. */ ++ if ((i1 == BB_END (bb1) && i2 != BB_END (bb2) ++ && nehedges1 > 0) ++ || (i2 == BB_END (bb2) && i1 != BB_END (bb1) ++ && nehedges2 > 0) ++ || (i1 == BB_END (bb1) && i2 == BB_END (bb2) ++ && nehedges1 != nehedges2)) ++ break; ++ ++ if (!old_insns_match_p (0, i1, i2)) ++ break; ++ ++ merge_memattrs (i1, i2); ++ ++ /* Don't begin a cross-jump with a NOTE insn. */ ++ if (INSN_P (i1)) ++ { ++ merge_notes (i1, i2); ++ ++ beforelast1 = last1, beforelast2 = last2; ++ last1 = i1, last2 = i2; ++ ninsns++; ++ } ++ ++ if (i1 == BB_END (bb1) || i2 == BB_END (bb2) ++ || (stop_after > 0 && ninsns == stop_after)) ++ break; ++ ++ i1 = NEXT_INSN (i1); ++ i2 = NEXT_INSN (i2); ++ } ++ ++#ifdef HAVE_cc0 ++ /* Don't allow a compare to be shared by cross-jumping unless the insn ++ after the compare is also shared. */ ++ if (ninsns && reg_mentioned_p (cc0_rtx, last1) && sets_cc0_p (last1)) ++ last1 = beforelast1, last2 = beforelast2, ninsns--; ++#endif ++ ++ if (ninsns) ++ { ++ *f1 = last1; ++ *f2 = last2; ++ } ++ ++ return ninsns; ++} ++ + /* Return true iff outgoing edges of BB1 and BB2 match, together with + the branch instruction. This means that if we commonize the control + flow before end of the basic block, the semantic remains unchanged. +@@ -1498,7 +1615,7 @@ + return false; + + /* ... and part the second. */ +- nmatch = flow_find_cross_jump (mode, src1, src2, &newpos1, &newpos2); ++ nmatch = flow_find_cross_jump (src1, src2, &newpos1, &newpos2); + + /* Don't proceed with the crossjump unless we found a sufficient number + of matching instructions or the 'from' block was totally matched +@@ -1923,8 +2040,7 @@ + } + } + delete_basic_block (b); +- if (!(mode & CLEANUP_CFGLAYOUT)) +- changed = true; ++ changed = true; + /* Avoid trying to remove ENTRY_BLOCK_PTR. */ + b = (c == ENTRY_BLOCK_PTR ? c->next_bb : c); + continue; +--- a/src/gcc/cfgexpand.c ++++ b/src/gcc/cfgexpand.c +@@ -64,7 +64,13 @@ + + grhs_class = get_gimple_rhs_class (gimple_expr_code (stmt)); + +- if (grhs_class == GIMPLE_BINARY_RHS) ++ if (grhs_class == GIMPLE_TERNARY_RHS) ++ t = build3 (gimple_assign_rhs_code (stmt), ++ TREE_TYPE (gimple_assign_lhs (stmt)), ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), ++ gimple_assign_rhs3 (stmt)); ++ else if (grhs_class == GIMPLE_BINARY_RHS) + t = build2 (gimple_assign_rhs_code (stmt), + TREE_TYPE (gimple_assign_lhs (stmt)), + gimple_assign_rhs1 (stmt), +@@ -1242,8 +1248,8 @@ + stack_vars_alloc = stack_vars_num = 0; + } + +-/* Make a fair guess for the size of the stack frame of the current +- function. This doesn't have to be exact, the result is only used ++/* Make a fair guess for the size of the stack frame of the decl ++ passed. This doesn't have to be exact, the result is only used + in the inline heuristics. So we don't want to run the full stack + var packing algorithm (which is quadratic in the number of stack + vars). Instead, we calculate the total size of all stack vars. +@@ -1251,11 +1257,14 @@ + vars doesn't happen very often. */ + + HOST_WIDE_INT +-estimated_stack_frame_size (void) ++estimated_stack_frame_size (tree decl) + { + HOST_WIDE_INT size = 0; + size_t i; + tree t, outer_block = DECL_INITIAL (current_function_decl); ++ tree old_cur_fun_decl = current_function_decl; ++ current_function_decl = decl; ++ push_cfun (DECL_STRUCT_FUNCTION (decl)); + + init_vars_expansion (); + +@@ -1278,7 +1287,8 @@ + size += account_stack_vars (); + fini_vars_expansion (); + } +- ++ pop_cfun (); ++ current_function_decl = old_cur_fun_decl; + return size; + } + +@@ -1893,6 +1903,9 @@ + ops.type = TREE_TYPE (lhs); + switch (get_gimple_rhs_class (gimple_expr_code (stmt))) + { ++ case GIMPLE_TERNARY_RHS: ++ ops.op2 = gimple_assign_rhs3 (stmt); ++ /* Fallthru */ + case GIMPLE_BINARY_RHS: + ops.op1 = gimple_assign_rhs2 (stmt); + /* Fallthru */ +@@ -2243,6 +2256,8 @@ + { + case COND_EXPR: + case DOT_PROD_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: + goto ternary; + + case TRUTH_ANDIF_EXPR: +@@ -2578,7 +2593,7 @@ + enum machine_mode opmode = GET_MODE (op0); + + if (opmode == VOIDmode) +- opmode = mode1; ++ opmode = TYPE_MODE (TREE_TYPE (tem)); + + /* This condition may hold if we're expanding the address + right past the end of an array that turned out not to +@@ -2599,7 +2614,8 @@ + ? SIGN_EXTRACT + : ZERO_EXTRACT, mode, + GET_MODE (op0) != VOIDmode +- ? GET_MODE (op0) : mode1, ++ ? GET_MODE (op0) ++ : TYPE_MODE (TREE_TYPE (tem)), + op0, GEN_INT (bitsize), GEN_INT (bitpos)); + } + +@@ -3029,18 +3045,27 @@ + return NULL; + + case WIDEN_MULT_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: + if (SCALAR_INT_MODE_P (GET_MODE (op0)) + && SCALAR_INT_MODE_P (mode)) + { ++ enum machine_mode inner_mode = GET_MODE (op0); + if (TYPE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 0)))) +- op0 = gen_rtx_ZERO_EXTEND (mode, op0); ++ op0 = simplify_gen_unary (ZERO_EXTEND, mode, op0, inner_mode); + else +- op0 = gen_rtx_SIGN_EXTEND (mode, op0); ++ op0 = simplify_gen_unary (SIGN_EXTEND, mode, op0, inner_mode); + if (TYPE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 1)))) +- op1 = gen_rtx_ZERO_EXTEND (mode, op1); ++ op1 = simplify_gen_unary (ZERO_EXTEND, mode, op1, inner_mode); + else +- op1 = gen_rtx_SIGN_EXTEND (mode, op1); +- return gen_rtx_MULT (mode, op0, op1); ++ op1 = simplify_gen_unary (SIGN_EXTEND, mode, op1, inner_mode); ++ op0 = gen_rtx_MULT (mode, op0, op1); ++ if (TREE_CODE (exp) == WIDEN_MULT_EXPR) ++ return op0; ++ else if (TREE_CODE (exp) == WIDEN_MULT_PLUS_EXPR) ++ return gen_rtx_PLUS (mode, op0, op2); ++ else ++ return gen_rtx_MINUS (mode, op2, op0); + } + return NULL; + +--- a/src/gcc/cfglayout.c ++++ b/src/gcc/cfglayout.c +@@ -766,6 +766,7 @@ + { + edge e_fall, e_taken, e; + rtx bb_end_insn; ++ rtx ret_label = NULL_RTX; + basic_block nb; + edge_iterator ei; + +@@ -785,6 +786,7 @@ + bb_end_insn = BB_END (bb); + if (JUMP_P (bb_end_insn)) + { ++ ret_label = JUMP_LABEL (bb_end_insn); + if (any_condjump_p (bb_end_insn)) + { + /* This might happen if the conditional jump has side +@@ -899,7 +901,7 @@ + } + + /* We got here if we need to add a new jump insn. */ +- nb = force_nonfallthru (e_fall); ++ nb = force_nonfallthru_and_redirect (e_fall, e_fall->dest, ret_label); + if (nb) + { + nb->il.rtl->visited = 1; +@@ -1118,24 +1120,30 @@ + bool + cfg_layout_can_duplicate_bb_p (const_basic_block bb) + { ++ rtx insn; ++ + /* Do not attempt to duplicate tablejumps, as we need to unshare + the dispatch table. This is difficult to do, as the instructions + computing jump destination may be hoisted outside the basic block. */ + if (tablejump_p (BB_END (bb), NULL, NULL)) + return false; + +- /* Do not duplicate blocks containing insns that can't be copied. */ +- if (targetm.cannot_copy_insn_p) ++ insn = BB_HEAD (bb); ++ while (1) + { +- rtx insn = BB_HEAD (bb); +- while (1) +- { +- if (INSN_P (insn) && targetm.cannot_copy_insn_p (insn)) +- return false; +- if (insn == BB_END (bb)) +- break; +- insn = NEXT_INSN (insn); +- } ++ /* Do not duplicate blocks containing insns that can't be copied. */ ++ if (INSN_P (insn) && targetm.cannot_copy_insn_p ++ && targetm.cannot_copy_insn_p (insn)) ++ return false; ++ /* dwarf2out expects that these notes are always paired with a ++ returnjump or sibling call. */ ++ if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG ++ && !returnjump_p (BB_END (bb)) ++ && (!CALL_P (BB_END (bb)) || !SIBLING_CALL_P (BB_END (bb)))) ++ return false; ++ if (insn == BB_END (bb)) ++ break; ++ insn = NEXT_INSN (insn); + } + + return true; +@@ -1180,6 +1188,9 @@ + break; + } + copy = emit_copy_of_insn_after (insn, get_last_insn ()); ++ if (JUMP_P (insn) && JUMP_LABEL (insn) != NULL_RTX ++ && ANY_RETURN_P (JUMP_LABEL (insn))) ++ JUMP_LABEL (copy) = JUMP_LABEL (insn); + maybe_copy_epilogue_insn (insn, copy); + break; + +--- a/src/gcc/cfgloop.h ++++ b/src/gcc/cfgloop.h +@@ -622,13 +622,14 @@ + /* The properties of the target. */ + + extern unsigned target_avail_regs; ++extern unsigned target_clobbered_regs; + extern unsigned target_res_regs; + extern unsigned target_reg_cost [2]; + extern unsigned target_spill_cost [2]; + + /* Register pressure estimation for induction variable optimizations & loop + invariant motion. */ +-extern unsigned estimate_reg_pressure_cost (unsigned, unsigned, bool); ++extern unsigned estimate_reg_pressure_cost (unsigned, unsigned, bool, bool); + extern void init_set_costs (void); + + /* Loop optimizer initialization. */ +--- a/src/gcc/cfgloopanal.c ++++ b/src/gcc/cfgloopanal.c +@@ -320,6 +320,8 @@ + /* The properties of the target. */ + + unsigned target_avail_regs; /* Number of available registers. */ ++unsigned target_clobbered_regs; /* Number of available registers that are ++ call-clobbered. */ + unsigned target_res_regs; /* Number of registers reserved for temporary + expressions. */ + unsigned target_reg_cost[2]; /* The cost for register when there still +@@ -342,10 +344,15 @@ + unsigned i; + + target_avail_regs = 0; ++ target_clobbered_regs = 0; + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i) + && !fixed_regs[i]) +- target_avail_regs++; ++ { ++ target_avail_regs++; ++ if (call_used_regs[i]) ++ target_clobbered_regs++; ++ } + + target_res_regs = 3; + +@@ -379,20 +386,29 @@ + + /* Estimates cost of increased register pressure caused by making N_NEW new + registers live around the loop. N_OLD is the number of registers live +- around the loop. */ ++ around the loop. If CALL_P is true, also take into account that ++ call-used registers may be clobbered in the loop body, reducing the ++ number of available registers before we spill. */ + + unsigned +-estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed) ++estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed, ++ bool call_p) + { + unsigned cost; + unsigned regs_needed = n_new + n_old; ++ unsigned available_regs = target_avail_regs; ++ ++ /* If there is a call in the loop body, the call-clobbered registers ++ are not available for loop invariants. */ ++ if (call_p) ++ available_regs = available_regs - target_clobbered_regs; + + /* If we have enough registers, we should use them and not restrict + the transformations unnecessarily. */ +- if (regs_needed + target_res_regs <= target_avail_regs) ++ if (regs_needed + target_res_regs <= available_regs) + return 0; + +- if (regs_needed <= target_avail_regs) ++ if (regs_needed <= available_regs) + /* If we are close to running out of registers, try to preserve + them. */ + cost = target_reg_cost [speed] * n_new; +--- a/src/gcc/cfgrtl.c ++++ b/src/gcc/cfgrtl.c +@@ -1107,10 +1107,13 @@ + } + + /* Like force_nonfallthru below, but additionally performs redirection +- Used by redirect_edge_and_branch_force. */ ++ Used by redirect_edge_and_branch_force. JUMP_LABEL is used only ++ when redirecting to the EXIT_BLOCK, it is either a return or a ++ simple_return rtx indicating which kind of returnjump to create. ++ It should be NULL otherwise. */ + +-static basic_block +-force_nonfallthru_and_redirect (edge e, basic_block target) ++basic_block ++force_nonfallthru_and_redirect (edge e, basic_block target, rtx jump_label) + { + basic_block jump_block, new_bb = NULL, src = e->src; + rtx note; +@@ -1242,11 +1245,25 @@ + e->flags &= ~EDGE_FALLTHRU; + if (target == EXIT_BLOCK_PTR) + { ++ if (jump_label == ret_rtx) ++ { + #ifdef HAVE_return +- emit_jump_insn_after_setloc (gen_return (), BB_END (jump_block), loc); ++ emit_jump_insn_after_setloc (gen_return (), BB_END (jump_block), ++ loc); ++#else ++ gcc_unreachable (); ++#endif ++ } ++ else ++ { ++ gcc_assert (jump_label == simple_return_rtx); ++#ifdef HAVE_simple_return ++ emit_jump_insn_after_setloc (gen_simple_return (), ++ BB_END (jump_block), loc); + #else +- gcc_unreachable (); ++ gcc_unreachable (); + #endif ++ } + } + else + { +@@ -1273,7 +1290,7 @@ + basic_block + force_nonfallthru (edge e) + { +- return force_nonfallthru_and_redirect (e, e->dest); ++ return force_nonfallthru_and_redirect (e, e->dest, NULL_RTX); + } + + /* Redirect edge even at the expense of creating new jump insn or +@@ -1290,7 +1307,7 @@ + /* In case the edge redirection failed, try to force it to be non-fallthru + and redirect newly created simplejump. */ + df_set_bb_dirty (e->src); +- return force_nonfallthru_and_redirect (e, target); ++ return force_nonfallthru_and_redirect (e, target, NULL_RTX); + } + + /* The given edge should potentially be a fallthru edge. If that is in +--- a/src/gcc/combine.c ++++ b/src/gcc/combine.c +@@ -392,8 +392,8 @@ + static void undo_all (void); + static void undo_commit (void); + static rtx *find_split_point (rtx *, rtx); +-static rtx subst (rtx, rtx, rtx, int, int); +-static rtx combine_simplify_rtx (rtx, enum machine_mode, int); ++static rtx subst (rtx, rtx, rtx, int, int, int); ++static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int); + static rtx simplify_if_then_else (rtx); + static rtx simplify_set (rtx); + static rtx simplify_logical (rtx); +@@ -2827,6 +2827,17 @@ + = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) + : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); + ++ /* We are about to copy insns for the case where they need to be kept ++ around. Check that they can be copied in the merged instruction. */ ++ ++ if (targetm.cannot_copy_insn_p ++ && ((added_sets_2 && targetm.cannot_copy_insn_p (i2)) ++ || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1)))) ++ { ++ undo_all (); ++ return 0; ++ } ++ + /* If the set in I2 needs to be kept around, we must make a copy of + PATTERN (I2), so that when we substitute I1SRC for I1DEST in + PATTERN (I2), we are only substituting for the original I1DEST, not into +@@ -2951,12 +2962,12 @@ + if (i1) + { + subst_low_luid = DF_INSN_LUID (i1); +- i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); ++ i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0); + } + else + { + subst_low_luid = DF_INSN_LUID (i2); +- i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); ++ i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0); + } + } + +@@ -2967,7 +2978,7 @@ + to avoid self-referential rtl. */ + + subst_low_luid = DF_INSN_LUID (i2); +- newpat = subst (PATTERN (i3), i2dest, i2src, 0, ++ newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0, + ! i1_feeds_i3 && i1dest_in_i1src); + substed_i2 = 1; + +@@ -2998,7 +3009,7 @@ + + n_occurrences = 0; + subst_low_luid = DF_INSN_LUID (i1); +- newpat = subst (newpat, i1dest, i1src, 0, 0); ++ newpat = subst (newpat, i1dest, i1src, 0, 0, 0); + substed_i1 = 1; + } + +@@ -3060,7 +3071,7 @@ + else + /* See comment where i2pat is assigned. */ + XVECEXP (newpat, 0, --total_sets) +- = subst (i2pat, i1dest, i1src, 0, 0); ++ = subst (i2pat, i1dest, i1src, 0, 0, 0); + } + } + +@@ -4612,11 +4623,13 @@ + + IN_DEST is nonzero if we are processing the SET_DEST of a SET. + ++ IN_COND is nonzero if we are on top level of the condition. ++ + UNIQUE_COPY is nonzero if each substitution must be unique. We do this + by copying if `n_occurrences' is nonzero. */ + + static rtx +-subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy) ++subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy) + { + enum rtx_code code = GET_CODE (x); + enum machine_mode op0_mode = VOIDmode; +@@ -4677,7 +4690,7 @@ + && GET_CODE (XVECEXP (x, 0, 0)) == SET + && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) + { +- new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy); ++ new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy); + + /* If this substitution failed, this whole thing fails. */ + if (GET_CODE (new_rtx) == CLOBBER +@@ -4694,7 +4707,7 @@ + && GET_CODE (dest) != CC0 + && GET_CODE (dest) != PC) + { +- new_rtx = subst (dest, from, to, 0, unique_copy); ++ new_rtx = subst (dest, from, to, 0, 0, unique_copy); + + /* If this substitution failed, this whole thing fails. */ + if (GET_CODE (new_rtx) == CLOBBER +@@ -4740,8 +4753,8 @@ + } + else + { +- new_rtx = subst (XVECEXP (x, i, j), from, to, 0, +- unique_copy); ++ new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0, ++ unique_copy); + + /* If this substitution failed, this whole thing + fails. */ +@@ -4818,7 +4831,9 @@ + && (code == SUBREG || code == STRICT_LOW_PART + || code == ZERO_EXTRACT)) + || code == SET) +- && i == 0), unique_copy); ++ && i == 0), ++ code == IF_THEN_ELSE && i == 0, ++ unique_copy); + + /* If we found that we will have to reject this combination, + indicate that by returning the CLOBBER ourselves, rather than +@@ -4875,7 +4890,7 @@ + /* If X is sufficiently simple, don't bother trying to do anything + with it. */ + if (code != CONST_INT && code != REG && code != CLOBBER) +- x = combine_simplify_rtx (x, op0_mode, in_dest); ++ x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond); + + if (GET_CODE (x) == code) + break; +@@ -4895,10 +4910,12 @@ + expression. + + OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero +- if we are inside a SET_DEST. */ ++ if we are inside a SET_DEST. IN_COND is nonzero if we are on the top level ++ of a condition. */ + + static rtx +-combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest) ++combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest, ++ int in_cond) + { + enum rtx_code code = GET_CODE (x); + enum machine_mode mode = GET_MODE (x); +@@ -4953,8 +4970,8 @@ + false arms to store-flag values. Be careful to use copy_rtx + here since true_rtx or false_rtx might share RTL with x as a + result of the if_then_else_cond call above. */ +- true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0); +- false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0); ++ true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0); ++ false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0); + + /* If true_rtx and false_rtx are not general_operands, an if_then_else + is unlikely to be simpler. */ +@@ -5298,7 +5315,7 @@ + { + /* Try to simplify the expression further. */ + rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); +- temp = combine_simplify_rtx (tor, mode, in_dest); ++ temp = combine_simplify_rtx (tor, mode, in_dest, 0); + + /* If we could, great. If not, do not go ahead with the IOR + replacement, since PLUS appears in many special purpose +@@ -5391,7 +5408,16 @@ + ZERO_EXTRACT is indeed appropriate, it will be placed back by + the call to make_compound_operation in the SET case. */ + +- if (STORE_FLAG_VALUE == 1 ++ if (in_cond) ++ /* Don't apply below optimizations if the caller would ++ prefer a comparison rather than a value. ++ E.g., for the condition in an IF_THEN_ELSE most targets need ++ an explicit comparison. */ ++ { ++ ; ++ } ++ ++ else if (STORE_FLAG_VALUE == 1 + && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT + && op1 == const0_rtx + && mode == GET_MODE (op0) +@@ -5635,11 +5661,11 @@ + if (reg_mentioned_p (from, true_rtx)) + true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, + from, true_val), +- pc_rtx, pc_rtx, 0, 0); ++ pc_rtx, pc_rtx, 0, 0, 0); + if (reg_mentioned_p (from, false_rtx)) + false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, + from, false_val), +- pc_rtx, pc_rtx, 0, 0); ++ pc_rtx, pc_rtx, 0, 0, 0); + + SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); + SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); +@@ -5856,11 +5882,11 @@ + { + temp = subst (simplify_gen_relational (true_code, m, VOIDmode, + cond_op0, cond_op1), +- pc_rtx, pc_rtx, 0, 0); ++ pc_rtx, pc_rtx, 0, 0, 0); + temp = simplify_gen_binary (MULT, m, temp, + simplify_gen_binary (MULT, m, c1, + const_true_rtx)); +- temp = subst (temp, pc_rtx, pc_rtx, 0, 0); ++ temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0); + temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp); + + if (extend_op != UNKNOWN) +--- a/src/gcc/common.opt ++++ b/src/gcc/common.opt +@@ -152,6 +152,10 @@ + Common Var(warn_padded) Warning + Warn when padding is required to align structure members + ++Wpoison-system-directories ++Common Var(flag_poison_system_directories) Init(1) ++Warn for -I and -L options using system directories if cross compiling ++ + Wshadow + Common Var(warn_shadow) Warning + Warn when one local variable shadows another +@@ -492,6 +496,10 @@ + Common Report Var(flag_early_inlining) Init(1) Optimization + Perform early inlining + ++fextension-elimination ++Common Report Var(flag_ee) Init(0) Optimization ++Perform extension elimination ++ + feliminate-dwarf2-dups + Common Report Var(flag_eliminate_dwarf2_dups) + Perform DWARF2 duplicate elimination +@@ -609,6 +617,10 @@ + Common Report Var(flag_loop_block) Optimization + Enable Loop Blocking transformation + ++fstrict-volatile-bitfields ++Common Report Var(flag_strict_volatile_bitfields) Init(-1) ++Force bitfield accesses to match their type width ++ + fguess-branch-probability + Common Report Var(flag_guess_branch_prob) Optimization + Enable guessing of branch probabilities +@@ -1135,6 +1147,11 @@ + Common C ObjC C++ ObjC++ Report Var(flag_show_column) Init(1) + Show column numbers in diagnostics, when available. Default on + ++fshrink-wrap ++Common Report Var(flag_shrink_wrap) Optimization ++Emit function prologues only before parts of the function that need it, ++rather than at the top of the function. ++ + fsignaling-nans + Common Report Var(flag_signaling_nans) Optimization + Disable optimizations observable by IEEE signaling NaNs +@@ -1273,6 +1290,10 @@ + Common Report Var(flag_tree_switch_conversion) Optimization + Perform conversions of switch initializations. + ++ftree-if-to-switch-conversion ++Common Report Var(flag_tree_if_to_switch_conversion) Optimization ++Perform conversions of chains of ifs into switches. ++ + ftree-dce + Common Report Var(flag_tree_dce) Optimization + Enable SSA dead code elimination optimization on trees +--- a/src/gcc/config/alpha/host-osf.c ++++ b/src/gcc/config/alpha/host-osf.c +@@ -0,0 +1,147 @@ ++/* Tru64 UNIX host-specific hook definitions. ++ Copyright (C) 2011 Free Software Foundation, Inc. ++ ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published ++ by the Free Software Foundation; either version 3, or (at your ++ option) any later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with GCC; see the file COPYING3. If not see ++ . */ ++ ++#include "config.h" ++#include "system.h" ++#include "coretypes.h" ++#include ++/* Inhibit inclusion of , unnecessary and errors out due to ++ use of poisoned bcmp, bcopy. */ ++#define _SYS_MOUNT_H_ ++#include ++#include "hosthooks.h" ++#include "hosthooks-def.h" ++ ++ ++#undef HOST_HOOKS_GT_PCH_GET_ADDRESS ++#define HOST_HOOKS_GT_PCH_GET_ADDRESS osf_gt_pch_get_address ++#undef HOST_HOOKS_GT_PCH_USE_ADDRESS ++#define HOST_HOOKS_GT_PCH_USE_ADDRESS osf_gt_pch_use_address ++ ++/* The mmap ADDR parameter may be ignored without MAP_FIXED set. Before we ++ give up, check existing mappings with ioctl(PIOCMAP) to see if the space ++ is really free. */ ++ ++static void * ++mmap_fixed (void *addr, size_t len, int prot, int flags, int fd, off_t off) ++{ ++ void *base; ++ ++ base = mmap ((caddr_t) addr, len, prot, flags, fd, off); ++ ++ if (base != addr) ++ { ++ /* PID_MAX is SHRT_MAX on Tru64 UNIX V4.0, but INT_MAX on V5.1. ++ Allow for both. "/proc/" + INT_MAX + '\0'. */ ++ char pname[6+10+1]; ++ int procfd, nmap; ++ prmap_t *pmap; ++ int i, overlap = 0; ++ ++ if (base != (void *) MAP_FAILED) ++ munmap ((caddr_t) base, len); ++ ++ /* Check if there's any mapping overlapping [addr, addr+len). */ ++ ++ snprintf (pname, sizeof (pname), "/proc/%d", getpid ()); ++ procfd = open (pname, O_RDONLY); ++ if (procfd == -1) ++ return ((void *) MAP_FAILED); ++ if (ioctl (procfd, PIOCNMAP, &nmap) == -1) ++ return ((void *) MAP_FAILED); ++ pmap = (prmap_t *) xmalloc (sizeof (*pmap) * (nmap+1)); ++ if (ioctl (procfd, PIOCMAP, pmap) == -1) ++ return ((void *) MAP_FAILED); ++ ++ /* It seems like pmap[] is sorted by address, but can we rely on ++ that? */ ++ for (i = 0; i < nmap; i++) ++ { ++ uintptr_t map_start = (uintptr_t) pmap[i].pr_vaddr; ++ uintptr_t map_end = map_start + pmap[i].pr_size; ++ ++ if ((uintptr_t) addr < map_end ++ && (uintptr_t) addr+len > map_start) ++ { ++ overlap = 1; ++ break; ++ } ++ } ++ free (pmap); ++ close (procfd); ++ ++ if (!overlap) ++ base = mmap ((caddr_t) addr, len, prot, flags | MAP_FIXED, fd, off); ++ else ++ base = mmap ((caddr_t) addr, len, prot, flags, fd, off); ++ } ++ ++ return base; ++} ++ ++/* For various ports, try to guess a fixed spot in the vm space that's ++ probably free. Take the middle between start of text segment and ++ dynamic loader space. See and Tru64 UNIX ++ Assembly Language Programmer's Guide, p.6-18, Figure 6-3: Default Layout ++ of Memory (User Program View). */ ++#define TRY_EMPTY_VM_SPACE 0x20050000000 ++ ++/* Determine a location where we might be able to reliably allocate ++ SIZE bytes. FD is the PCH file, though we should return with the ++ file unmapped. */ ++ ++static void * ++osf_gt_pch_get_address (size_t size, int fd) ++{ ++ void *addr; ++ ++ addr = mmap_fixed ((caddr_t) TRY_EMPTY_VM_SPACE, size, ++ PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); ++ ++ /* If we failed the map, that means there's *no* free space. */ ++ if (addr == (void *) MAP_FAILED) ++ return NULL; ++ /* Unmap the area before returning. */ ++ munmap ((caddr_t) addr, size); ++ ++ return addr; ++} ++ ++/* Map SIZE bytes of FD+OFFSET at BASE. Return 1 if we succeeded at ++ mapping the data at BASE, -1 if we couldn't. */ ++ ++static int ++osf_gt_pch_use_address (void *base, size_t size, int fd, size_t offset) ++{ ++ void *addr; ++ ++ /* We're called with size == 0 if we're not planning to load a PCH ++ file at all. This allows the hook to free any static space that ++ we might have allocated at link time. */ ++ if (size == 0) ++ return -1; ++ ++ addr = mmap_fixed ((caddr_t) base, size, ++ PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, offset); ++ ++ return addr == base ? 1 : -1; ++} ++ ++ ++const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER; +--- a/src/gcc/config/alpha/x-osf ++++ b/src/gcc/config/alpha/x-osf +@@ -0,0 +1,4 @@ ++host-osf.o : $(srcdir)/config/alpha/host-osf.c $(CONFIG_H) $(SYSTEM_H) \ ++ coretypes.h hosthooks.h hosthooks-def.h $(HOOKS_H) ++ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ ++ $(srcdir)/config/alpha/host-osf.c +--- a/src/gcc/config/arm/aout.h ++++ b/src/gcc/config/arm/aout.h +@@ -163,31 +163,45 @@ + {"mvdx12", 39}, \ + {"mvdx13", 40}, \ + {"mvdx14", 41}, \ +- {"mvdx15", 42}, \ +- {"d0", 63}, {"q0", 63}, \ +- {"d1", 65}, \ +- {"d2", 67}, {"q1", 67}, \ +- {"d3", 69}, \ +- {"d4", 71}, {"q2", 71}, \ +- {"d5", 73}, \ +- {"d6", 75}, {"q3", 75}, \ +- {"d7", 77}, \ +- {"d8", 79}, {"q4", 79}, \ +- {"d9", 81}, \ +- {"d10", 83}, {"q5", 83}, \ +- {"d11", 85}, \ +- {"d12", 87}, {"q6", 87}, \ +- {"d13", 89}, \ +- {"d14", 91}, {"q7", 91}, \ +- {"d15", 93}, \ +- {"q8", 95}, \ +- {"q9", 99}, \ +- {"q10", 103}, \ +- {"q11", 107}, \ +- {"q12", 111}, \ +- {"q13", 115}, \ +- {"q14", 119}, \ +- {"q15", 123} \ ++ {"mvdx15", 42} \ ++} ++#endif ++ ++#ifndef OVERLAPPING_REGISTER_NAMES ++#define OVERLAPPING_REGISTER_NAMES \ ++{ \ ++ {"d0", 63, 2}, \ ++ {"d1", 65, 2}, \ ++ {"d2", 67, 2}, \ ++ {"d3", 69, 2}, \ ++ {"d4", 71, 2}, \ ++ {"d5", 73, 2}, \ ++ {"d6", 75, 2}, \ ++ {"d7", 77, 2}, \ ++ {"d8", 79, 2}, \ ++ {"d9", 81, 2}, \ ++ {"d10", 83, 2}, \ ++ {"d11", 85, 2}, \ ++ {"d12", 87, 2}, \ ++ {"d13", 89, 2}, \ ++ {"d14", 91, 2}, \ ++ {"d15", 93, 2}, \ ++ {"q0", 63, 4}, \ ++ {"q1", 67, 4}, \ ++ {"q2", 71, 4}, \ ++ {"q3", 75, 4}, \ ++ {"q4", 79, 4}, \ ++ {"q5", 83, 4}, \ ++ {"q6", 87, 4}, \ ++ {"q7", 91, 4}, \ ++ {"q8", 95, 4}, \ ++ {"q9", 99, 4}, \ ++ {"q10", 103, 4}, \ ++ {"q11", 107, 4}, \ ++ {"q12", 111, 4}, \ ++ {"q13", 115, 4}, \ ++ {"q14", 119, 4}, \ ++ {"q15", 123, 4} \ + } + #endif + +--- a/src/gcc/config/arm/arm-cores.def ++++ b/src/gcc/config/arm/arm-cores.def +@@ -120,9 +120,10 @@ + ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, 9e) + ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, 9e) + ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e) +-ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, 9e) ++ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) + ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e) + ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e) ++ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, 9e) + ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e) + ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e) + ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, 9e) +--- a/src/gcc/config/arm/arm-generic.md ++++ b/src/gcc/config/arm/arm-generic.md +@@ -104,14 +104,14 @@ + (and (eq_attr "generic_sched" "yes") + (and (eq_attr "ldsched" "yes") + (and (eq_attr "type" "load_byte,load1") +- (eq_attr "is_xscale" "yes")))) ++ (eq_attr "tune" "xscale,iwmmxt,iwmmxt2")))) + "core") + + (define_insn_reservation "load_ldsched" 2 + (and (eq_attr "generic_sched" "yes") + (and (eq_attr "ldsched" "yes") + (and (eq_attr "type" "load_byte,load1") +- (eq_attr "is_xscale" "no")))) ++ (eq_attr "tune" "!xscale,iwmmxt,iwmmxt2")))) + "core") + + (define_insn_reservation "load_or_store" 2 +@@ -128,14 +128,16 @@ + (define_insn_reservation "mult_ldsched_strongarm" 3 + (and (eq_attr "generic_sched" "yes") + (and (eq_attr "ldsched" "yes") +- (and (eq_attr "is_strongarm" "yes") ++ (and (eq_attr "tune" ++ "strongarm,strongarm110,strongarm1100,strongarm1110") + (eq_attr "type" "mult")))) + "core*2") + + (define_insn_reservation "mult_ldsched" 4 + (and (eq_attr "generic_sched" "yes") + (and (eq_attr "ldsched" "yes") +- (and (eq_attr "is_strongarm" "no") ++ (and (eq_attr "tune" ++ "!strongarm,strongarm110,strongarm1100,strongarm1110") + (eq_attr "type" "mult")))) + "core*4") + +--- a/src/gcc/config/arm/arm-ldmstm.ml ++++ b/src/gcc/config/arm/arm-ldmstm.ml +@@ -0,0 +1,333 @@ ++(* Auto-generate ARM ldm/stm patterns ++ Copyright (C) 2010 Free Software Foundation, Inc. ++ Contributed by CodeSourcery. ++ ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it under ++ the terms of the GNU General Public License as published by the Free ++ Software Foundation; either version 3, or (at your option) any later ++ version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ANY ++ WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with GCC; see the file COPYING3. If not see ++ . ++ ++ This is an O'Caml program. The O'Caml compiler is available from: ++ ++ http://caml.inria.fr/ ++ ++ Or from your favourite OS's friendly packaging system. Tested with version ++ 3.09.2, though other versions will probably work too. ++ ++ Run with: ++ ocaml arm-ldmstm.ml >/path/to/gcc/config/arm/ldmstm.ml ++*) ++ ++type amode = IA | IB | DA | DB ++ ++type optype = IN | OUT | INOUT ++ ++let rec string_of_addrmode addrmode = ++ match addrmode with ++ IA -> "ia" | IB -> "ib" | DA -> "da" | DB -> "db" ++ ++let rec initial_offset addrmode nregs = ++ match addrmode with ++ IA -> 0 ++ | IB -> 4 ++ | DA -> -4 * nregs + 4 ++ | DB -> -4 * nregs ++ ++let rec final_offset addrmode nregs = ++ match addrmode with ++ IA -> nregs * 4 ++ | IB -> nregs * 4 ++ | DA -> -4 * nregs ++ | DB -> -4 * nregs ++ ++let constr thumb = ++ if thumb then "l" else "rk" ++ ++let inout_constr op_type = ++ match op_type with ++ OUT -> "=" ++ | INOUT -> "+&" ++ | IN -> "" ++ ++let destreg nregs first op_type thumb = ++ if not first then ++ Printf.sprintf "(match_dup %d)" (nregs) ++ else ++ Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")") ++ (nregs) (inout_constr op_type) (constr thumb) ++ ++let write_ldm_set thumb nregs offset opnr first = ++ let indent = " " in ++ Printf.printf "%s" (if first then " [" else indent); ++ Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr; ++ Printf.printf "%s (mem:SI " indent; ++ begin if offset != 0 then Printf.printf "(plus:SI " end; ++ Printf.printf "%s" (destreg nregs first IN thumb); ++ begin if offset != 0 then Printf.printf "\n%s (const_int %d))" indent offset end; ++ Printf.printf "))" ++ ++let write_stm_set thumb nregs offset opnr first = ++ let indent = " " in ++ Printf.printf "%s" (if first then " [" else indent); ++ Printf.printf "(set (mem:SI "; ++ begin if offset != 0 then Printf.printf "(plus:SI " end; ++ Printf.printf "%s" (destreg nregs first IN thumb); ++ begin if offset != 0 then Printf.printf " (const_int %d))" offset end; ++ Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr ++ ++let write_ldm_peep_set extra_indent nregs opnr first = ++ let indent = " " ^ extra_indent in ++ Printf.printf "%s" (if first then extra_indent ^ " [" else indent); ++ Printf.printf "(set (match_operand:SI %d \"s_register_operand\" \"\")\n" opnr; ++ Printf.printf "%s (match_operand:SI %d \"memory_operand\" \"\"))" indent (nregs + opnr) ++ ++let write_stm_peep_set extra_indent nregs opnr first = ++ let indent = " " ^ extra_indent in ++ Printf.printf "%s" (if first then extra_indent ^ " [" else indent); ++ Printf.printf "(set (match_operand:SI %d \"memory_operand\" \"\")\n" (nregs + opnr); ++ Printf.printf "%s (match_operand:SI %d \"s_register_operand\" \"\"))" indent opnr ++ ++let write_any_load optype nregs opnr first = ++ let indent = " " in ++ Printf.printf "%s" (if first then " [" else indent); ++ Printf.printf "(set (match_operand:SI %d \"s_register_operand\" \"\")\n" opnr; ++ Printf.printf "%s (match_operand:SI %d \"%s\" \"\"))" indent (nregs * 2 + opnr) optype ++ ++let write_const_store nregs opnr first = ++ let indent = " " in ++ Printf.printf "%s(set (match_operand:SI %d \"memory_operand\" \"\")\n" indent (nregs + opnr); ++ Printf.printf "%s (match_dup %d))" indent opnr ++ ++let write_const_stm_peep_set nregs opnr first = ++ write_any_load "const_int_operand" nregs opnr first; ++ Printf.printf "\n"; ++ write_const_store nregs opnr false ++ ++ ++let rec write_pat_sets func opnr offset first n_left = ++ func offset opnr first; ++ begin ++ if n_left > 1 then begin ++ Printf.printf "\n"; ++ write_pat_sets func (opnr + 1) (offset + 4) false (n_left - 1); ++ end else ++ Printf.printf "]" ++ end ++ ++let rec write_peep_sets func opnr first n_left = ++ func opnr first; ++ begin ++ if n_left > 1 then begin ++ Printf.printf "\n"; ++ write_peep_sets func (opnr + 1) false (n_left - 1); ++ end ++ end ++ ++let can_thumb addrmode update is_store = ++ match addrmode, update, is_store with ++ (* Thumb1 mode only supports IA with update. However, for LDMIA, ++ if the address register also appears in the list of loaded ++ registers, the loaded value is stored, hence the RTL pattern ++ to describe such an insn does not have an update. We check ++ in the match_parallel predicate that the condition described ++ above is met. *) ++ IA, _, false -> true ++ | IA, true, true -> true ++ | _ -> false ++ ++let target addrmode thumb = ++ match addrmode, thumb with ++ IA, true -> "TARGET_THUMB1" ++ | IA, false -> "TARGET_32BIT" ++ | DB, false -> "TARGET_32BIT" ++ | _, false -> "TARGET_ARM" ++ ++let write_pattern_1 name ls addrmode nregs write_set_fn update thumb = ++ let astr = string_of_addrmode addrmode in ++ Printf.printf "(define_insn \"*%s%s%d_%s%s\"\n" ++ (if thumb then "thumb_" else "") name nregs astr ++ (if update then "_update" else ""); ++ Printf.printf " [(match_parallel 0 \"%s_multiple_operation\"\n" ls; ++ begin ++ if update then begin ++ Printf.printf " [(set %s\n (plus:SI " ++ (destreg 1 true OUT thumb); (*destreg 2 true IN thumb*) ++ Printf.printf "(match_operand:SI 2 \"s_register_operand\" \"1\")"; ++ Printf.printf " (const_int %d)))\n" ++ (final_offset addrmode nregs) ++ end ++ end; ++ write_pat_sets ++ (write_set_fn thumb (if update then 2 else 1)) (if update then 3 else 2) ++ (initial_offset addrmode nregs) ++ (not update) nregs; ++ Printf.printf ")]\n \"%s && XVECLEN (operands[0], 0) == %d\"\n" ++ (target addrmode thumb) ++ (if update then nregs + 1 else nregs); ++ Printf.printf " \"%s%%(%s%%)\\t%%%d%s, {" ++ name astr (1) (if update then "!" else ""); ++ for n = 1 to nregs; do ++ Printf.printf "%%%d%s" (n+(if update then 2 else 1)) (if n < nregs then ", " else "") ++ done; ++ Printf.printf "}\"\n"; ++ Printf.printf " [(set_attr \"type\" \"%s%d\")" ls nregs; ++ begin if not thumb then ++ Printf.printf "\n (set_attr \"predicable\" \"yes\")"; ++ end; ++ Printf.printf "])\n\n" ++ ++let write_ldm_pattern addrmode nregs update = ++ write_pattern_1 "ldm" "load" addrmode nregs write_ldm_set update false; ++ begin if can_thumb addrmode update false then ++ write_pattern_1 "ldm" "load" addrmode nregs write_ldm_set update true; ++ end ++ ++let write_stm_pattern addrmode nregs update = ++ write_pattern_1 "stm" "store" addrmode nregs write_stm_set update false; ++ begin if can_thumb addrmode update true then ++ write_pattern_1 "stm" "store" addrmode nregs write_stm_set update true; ++ end ++ ++let write_ldm_commutative_peephole thumb = ++ let nregs = 2 in ++ Printf.printf "(define_peephole2\n"; ++ write_peep_sets (write_ldm_peep_set "" nregs) 0 true nregs; ++ let indent = " " in ++ if thumb then begin ++ Printf.printf "\n%s(set (match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2); ++ Printf.printf "%s (match_operator:SI %d \"commutative_binary_operator\"\n" indent (nregs * 2 + 1); ++ Printf.printf "%s [(match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2 + 2); ++ Printf.printf "%s (match_operand:SI %d \"s_register_operand\" \"\")]))]\n" indent (nregs * 2 + 3) ++ end else begin ++ Printf.printf "\n%s(parallel\n" indent; ++ Printf.printf "%s [(set (match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2); ++ Printf.printf "%s (match_operator:SI %d \"commutative_binary_operator\"\n" indent (nregs * 2 + 1); ++ Printf.printf "%s [(match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2 + 2); ++ Printf.printf "%s (match_operand:SI %d \"s_register_operand\" \"\")]))\n" indent (nregs * 2 + 3); ++ Printf.printf "%s (clobber (reg:CC CC_REGNUM))])]\n" indent ++ end; ++ Printf.printf " \"(((operands[%d] == operands[0] && operands[%d] == operands[1])\n" (nregs * 2 + 2) (nregs * 2 + 3); ++ Printf.printf " || (operands[%d] == operands[0] && operands[%d] == operands[1]))\n" (nregs * 2 + 3) (nregs * 2 + 2); ++ Printf.printf " && peep2_reg_dead_p (%d, operands[0]) && peep2_reg_dead_p (%d, operands[1]))\"\n" (nregs + 1) (nregs + 1); ++ begin ++ if thumb then ++ Printf.printf " [(set (match_dup %d) (match_op_dup %d [(match_dup %d) (match_dup %d)]))]\n" ++ (nregs * 2) (nregs * 2 + 1) (nregs * 2 + 2) (nregs * 2 + 3) ++ else begin ++ Printf.printf " [(parallel\n"; ++ Printf.printf " [(set (match_dup %d) (match_op_dup %d [(match_dup %d) (match_dup %d)]))\n" ++ (nregs * 2) (nregs * 2 + 1) (nregs * 2 + 2) (nregs * 2 + 3); ++ Printf.printf " (clobber (reg:CC CC_REGNUM))])]\n" ++ end ++ end; ++ Printf.printf "{\n if (!gen_ldm_seq (operands, %d, true))\n FAIL;\n" nregs; ++ Printf.printf "})\n\n" ++ ++let write_ldm_peephole nregs = ++ Printf.printf "(define_peephole2\n"; ++ write_peep_sets (write_ldm_peep_set "" nregs) 0 true nregs; ++ Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; ++ Printf.printf " if (gen_ldm_seq (operands, %d, false))\n DONE;\n else\n FAIL;\n})\n\n" nregs ++ ++let write_ldm_peephole_b nregs = ++ if nregs > 2 then begin ++ Printf.printf "(define_peephole2\n"; ++ write_ldm_peep_set "" nregs 0 true; ++ Printf.printf "\n (parallel\n"; ++ write_peep_sets (write_ldm_peep_set " " nregs) 1 true (nregs - 1); ++ Printf.printf "])]\n \"\"\n [(const_int 0)]\n{\n"; ++ Printf.printf " if (gen_ldm_seq (operands, %d, false))\n DONE;\n else\n FAIL;\n})\n\n" nregs ++ end ++ ++let write_stm_peephole nregs = ++ Printf.printf "(define_peephole2\n"; ++ write_peep_sets (write_stm_peep_set "" nregs) 0 true nregs; ++ Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; ++ Printf.printf " if (gen_stm_seq (operands, %d))\n DONE;\n else\n FAIL;\n})\n\n" nregs ++ ++let write_stm_peephole_b nregs = ++ if nregs > 2 then begin ++ Printf.printf "(define_peephole2\n"; ++ write_stm_peep_set "" nregs 0 true; ++ Printf.printf "\n (parallel\n"; ++ write_peep_sets (write_stm_peep_set "" nregs) 1 true (nregs - 1); ++ Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; ++ Printf.printf " if (gen_stm_seq (operands, %d))\n DONE;\n else\n FAIL;\n})\n\n" nregs ++ end ++ ++let write_const_stm_peephole_a nregs = ++ Printf.printf "(define_peephole2\n"; ++ write_peep_sets (write_const_stm_peep_set nregs) 0 true nregs; ++ Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; ++ Printf.printf " if (gen_const_stm_seq (operands, %d))\n DONE;\n else\n FAIL;\n})\n\n" nregs ++ ++let write_const_stm_peephole_b nregs = ++ Printf.printf "(define_peephole2\n"; ++ write_peep_sets (write_any_load "const_int_operand" nregs) 0 true nregs; ++ Printf.printf "\n"; ++ write_peep_sets (write_const_store nregs) 0 false nregs; ++ Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; ++ Printf.printf " if (gen_const_stm_seq (operands, %d))\n DONE;\n else\n FAIL;\n})\n\n" nregs ++ ++let patterns () = ++ let addrmodes = [ IA; IB; DA; DB ] in ++ let sizes = [ 4; 3; 2] in ++ List.iter ++ (fun n -> ++ List.iter ++ (fun addrmode -> ++ write_ldm_pattern addrmode n false; ++ write_ldm_pattern addrmode n true; ++ write_stm_pattern addrmode n false; ++ write_stm_pattern addrmode n true) ++ addrmodes; ++ write_ldm_peephole n; ++ write_ldm_peephole_b n; ++ write_const_stm_peephole_a n; ++ write_const_stm_peephole_b n; ++ write_stm_peephole n;) ++ sizes; ++ write_ldm_commutative_peephole false; ++ write_ldm_commutative_peephole true ++ ++let print_lines = List.iter (fun s -> Format.printf "%s@\n" s) ++ ++(* Do it. *) ++ ++let _ = ++ print_lines [ ++"/* ARM ldm/stm instruction patterns. This file was automatically generated"; ++" using arm-ldmstm.ml. Please do not edit manually."; ++""; ++" Copyright (C) 2010 Free Software Foundation, Inc."; ++" Contributed by CodeSourcery."; ++""; ++" This file is part of GCC."; ++""; ++" GCC is free software; you can redistribute it and/or modify it"; ++" under the terms of the GNU General Public License as published"; ++" by the Free Software Foundation; either version 3, or (at your"; ++" option) any later version."; ++""; ++" GCC is distributed in the hope that it will be useful, but WITHOUT"; ++" ANY WARRANTY; without even the implied warranty of MERCHANTABILITY"; ++" or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public"; ++" License for more details."; ++""; ++" You should have received a copy of the GNU General Public License and"; ++" a copy of the GCC Runtime Library Exception along with this program;"; ++" see the files COPYING3 and COPYING.RUNTIME respectively. If not, see"; ++" . */"; ++""]; ++ patterns (); +--- a/src/gcc/config/arm/arm-modes.def ++++ b/src/gcc/config/arm/arm-modes.def +@@ -34,11 +34,19 @@ + CCFPmode should be used with floating equalities. + CC_NOOVmode should be used with SImode integer equalities. + CC_Zmode should be used if only the Z flag is set correctly ++ CC_Cmode should be used if only the C flag is set correctly, after an ++ addition. + CC_Nmode should be used if only the N (sign) flag is set correctly ++ CC_CZmode should be used if only the C and Z flags are correct ++ (used for DImode unsigned comparisons). ++ CC_NCVmode should be used if only the N, C, and V flags are correct ++ (used for DImode signed comparisons). + CCmode should be used otherwise. */ + + CC_MODE (CC_NOOV); + CC_MODE (CC_Z); ++CC_MODE (CC_CZ); ++CC_MODE (CC_NCV); + CC_MODE (CC_SWP); + CC_MODE (CCFP); + CC_MODE (CCFPE); +--- a/src/gcc/config/arm/arm-protos.h ++++ b/src/gcc/config/arm/arm-protos.h +@@ -26,6 +26,7 @@ + extern void arm_override_options (void); + extern void arm_optimization_options (int, int); + extern int use_return_insn (int, rtx); ++extern bool use_simple_return_p (void); + extern enum reg_class arm_regno_class (int); + extern void arm_load_pic_register (unsigned long); + extern int arm_volatile_func (void); +@@ -49,8 +50,7 @@ + extern int const_ok_for_arm (HOST_WIDE_INT); + extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx, + HOST_WIDE_INT, rtx, rtx, int); +-extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, enum machine_mode, +- rtx *); ++extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *); + extern int legitimate_pic_operand_p (rtx); + extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx); + extern rtx legitimize_tls_address (rtx, rtx); +@@ -88,6 +88,8 @@ + extern int neon_vector_mem_operand (rtx, int); + extern int neon_struct_mem_operand (rtx); + extern int arm_no_early_store_addr_dep (rtx, rtx); ++extern int arm_early_store_addr_dep (rtx, rtx); ++extern int arm_early_load_addr_dep (rtx, rtx); + extern int arm_no_early_alu_shift_dep (rtx, rtx); + extern int arm_no_early_alu_shift_value_dep (rtx, rtx); + extern int arm_no_early_mul_dep (rtx, rtx); +@@ -98,14 +100,11 @@ + extern int label_mentioned_p (rtx); + extern RTX_CODE minmax_code (rtx); + extern int adjacent_mem_locations (rtx, rtx); +-extern int load_multiple_sequence (rtx *, int, int *, int *, HOST_WIDE_INT *); +-extern const char *emit_ldm_seq (rtx *, int); +-extern int store_multiple_sequence (rtx *, int, int *, int *, HOST_WIDE_INT *); +-extern const char * emit_stm_seq (rtx *, int); +-extern rtx arm_gen_load_multiple (int, int, rtx, int, int, +- rtx, HOST_WIDE_INT *); +-extern rtx arm_gen_store_multiple (int, int, rtx, int, int, +- rtx, HOST_WIDE_INT *); ++extern bool gen_ldm_seq (rtx *, int, bool); ++extern bool gen_stm_seq (rtx *, int); ++extern bool gen_const_stm_seq (rtx *, int); ++extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); ++extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); + extern int arm_gen_movmemqi (rtx *); + extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx); + extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx, +@@ -116,6 +115,7 @@ + extern void arm_reload_out_hi (rtx *); + extern int arm_const_double_inline_cost (rtx); + extern bool arm_const_double_by_parts (rtx); ++extern bool arm_const_double_by_immediates (rtx); + extern const char *fp_immediate_constant (rtx); + extern void arm_emit_call_insn (rtx, rtx); + extern const char *output_call (rtx *); +@@ -131,10 +131,11 @@ + extern const char *output_move_vfp (rtx *operands); + extern const char *output_move_neon (rtx *operands); + extern int arm_attr_length_move_neon (rtx); ++extern int arm_address_offset_is_imm (rtx); + extern const char *output_add_immediate (rtx *); + extern const char *arithmetic_instr (rtx, int); + extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int); +-extern const char *output_return_instruction (rtx, int, int); ++extern const char *output_return_instruction (rtx, bool, bool, bool); + extern void arm_poke_function_name (FILE *, const char *); + extern void arm_print_operand (FILE *, rtx, int); + extern void arm_print_operand_address (FILE *, rtx); +@@ -148,6 +149,11 @@ + extern void arm_set_return_address (rtx, rtx); + extern int arm_eliminable_register (rtx); + extern const char *arm_output_shift(rtx *, int); ++extern void arm_expand_sync (enum machine_mode, struct arm_sync_generator *, ++ rtx, rtx, rtx, rtx); ++extern const char *arm_output_memory_barrier (rtx *); ++extern const char *arm_output_sync_insn (rtx, rtx *); ++extern unsigned int arm_sync_loop_insns (rtx , rtx *); + + extern bool arm_output_addr_const_extra (FILE *, rtx); + +@@ -214,4 +220,17 @@ + + extern void arm_order_regs_for_local_alloc (void); + ++#ifdef RTX_CODE ++/* This needs to be here because we need RTX_CODE and similar. */ ++ ++struct tune_params ++{ ++ bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool); ++ bool (*sched_adjust_cost) (rtx, rtx, rtx, int *); ++ int constant_limit; ++}; ++ ++extern const struct tune_params *current_tune; ++#endif /* RTX_CODE */ ++ + #endif /* ! GCC_ARM_PROTOS_H */ +--- a/src/gcc/config/arm/arm-tune.md ++++ b/src/gcc/config/arm/arm-tune.md +@@ -1,5 +1,5 @@ + ;; -*- buffer-read-only: t -*- + ;; Generated automatically by gentune.sh from arm-cores.def + (define_attr "tune" +- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1,cortexm0" ++ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0" + (const (symbol_ref "((enum attr_tune) arm_tune)"))) +--- a/src/gcc/config/arm/arm.c ++++ b/src/gcc/config/arm/arm.c +@@ -56,6 +56,7 @@ + #include "df.h" + #include "intl.h" + #include "libfuncs.h" ++#include "params.h" + + /* Forward definitions of types. */ + typedef struct minipool_node Mnode; +@@ -141,6 +142,7 @@ + static bool arm_have_conditional_execution (void); + static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool); + static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); ++static bool thumb2_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); + static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); + static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); + static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); +@@ -214,6 +216,7 @@ + static int arm_issue_rate (void); + static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; + static bool arm_allocate_stack_slots_for_args (void); ++static bool arm_warn_func_result (void); + static const char *arm_invalid_parameter_type (const_tree t); + static const char *arm_invalid_return_type (const_tree t); + static tree arm_promoted_type (const_tree t); +@@ -224,6 +227,14 @@ + static void arm_asm_trampoline_template (FILE *); + static void arm_trampoline_init (rtx, tree, rtx); + static rtx arm_trampoline_adjust_address (rtx); ++static rtx arm_pic_static_addr (rtx orig, rtx reg); ++static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *); ++static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *); ++static bool arm_vector_alignment_reachable (const_tree type, bool is_packed); ++static bool arm_builtin_support_vector_misalignment (enum machine_mode mode, ++ const_tree type, ++ int misalignment, ++ bool is_packed); + + + /* Table of machine attributes. */ +@@ -378,6 +389,9 @@ + #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS + #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address + ++#undef TARGET_WARN_FUNC_RESULT ++#define TARGET_WARN_FUNC_RESULT arm_warn_func_result ++ + #undef TARGET_DEFAULT_SHORT_ENUMS + #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums + +@@ -507,6 +521,14 @@ + #undef TARGET_CAN_ELIMINATE + #define TARGET_CAN_ELIMINATE arm_can_eliminate + ++#undef TARGET_VECTOR_ALIGNMENT_REACHABLE ++#define TARGET_VECTOR_ALIGNMENT_REACHABLE \ ++ arm_vector_alignment_reachable ++ ++#undef TARGET_SUPPORT_VECTOR_MISALIGNMENT ++#define TARGET_SUPPORT_VECTOR_MISALIGNMENT \ ++ arm_builtin_support_vector_misalignment ++ + struct gcc_target targetm = TARGET_INITIALIZER; + + /* Obstack for minipool constant handling. */ +@@ -525,8 +547,8 @@ + /* The processor for which instructions should be scheduled. */ + enum processor_type arm_tune = arm_none; + +-/* The default processor used if not overridden by commandline. */ +-static enum processor_type arm_default_cpu = arm_none; ++/* The current tuning set. */ ++const struct tune_params *current_tune; + + /* Which floating point hardware to schedule for. */ + int arm_fpu_attr; +@@ -580,9 +602,14 @@ + #define FL_NEON (1 << 20) /* Neon instructions. */ + #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M + architecture. */ ++#define FL_ARCH7 (1 << 22) /* Architecture 7. */ + + #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ + ++/* Flags that only effect tuning, not available instructions. */ ++#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ ++ | FL_CO_PROC) ++ + #define FL_FOR_ARCH2 FL_NOTM + #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) + #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) +@@ -600,7 +627,7 @@ + #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K + #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) + #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) +-#define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM) ++#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) + #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) + #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) + #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) +@@ -638,6 +665,9 @@ + /* Nonzero if this chip supports the ARM 6K extensions. */ + int arm_arch6k = 0; + ++/* Nonzero if this chip supports the ARM 7 extensions. */ ++int arm_arch7 = 0; ++ + /* Nonzero if instructions not present in the 'M' profile can be used. */ + int arm_arch_notm = 0; + +@@ -666,6 +696,9 @@ + This typically means an ARM6 or ARM7 with MMU or MPU. */ + int arm_tune_wbuf = 0; + ++/* Nonzero if tuning for Cortex-A5. */ ++int arm_tune_cortex_a5 = 0; ++ + /* Nonzero if tuning for Cortex-A9. */ + int arm_tune_cortex_a9 = 0; + +@@ -697,10 +730,7 @@ + the next function. */ + static int after_arm_reorg = 0; + +-/* The maximum number of insns to be used when loading a constant. */ +-static int arm_constant_limit = 3; +- +-static enum arm_pcs arm_pcs_default; ++enum arm_pcs arm_pcs_default; + + /* For an explanation of these variables, see final_prescan_insn below. */ + int arm_ccfsm_state; +@@ -723,6 +753,12 @@ + "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" + }; + ++/* The register numbers in sequence, for passing to arm_gen_load_multiple. */ ++int arm_regs_in_sequence[] = ++{ ++ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 ++}; ++ + #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl") + #define streq(string1, string2) (strcmp (string1, string2) == 0) + +@@ -738,16 +774,52 @@ + enum processor_type core; + const char *arch; + const unsigned long flags; +- bool (* rtx_costs) (rtx, enum rtx_code, enum rtx_code, int *, bool); ++ const struct tune_params *const tune; ++}; ++ ++const struct tune_params arm_slowmul_tune = ++{ ++ arm_slowmul_rtx_costs, ++ NULL, ++ 3 ++}; ++ ++const struct tune_params arm_fastmul_tune = ++{ ++ arm_fastmul_rtx_costs, ++ NULL, ++ 1 + }; + ++const struct tune_params arm_xscale_tune = ++{ ++ arm_xscale_rtx_costs, ++ xscale_sched_adjust_cost, ++ 2 ++}; ++ ++const struct tune_params arm_9e_tune = ++{ ++ arm_9e_rtx_costs, ++ NULL, ++ 1 ++}; ++ ++const struct tune_params arm_cortex_a9_tune = ++{ ++ arm_9e_rtx_costs, ++ cortex_a9_sched_adjust_cost, ++ 1 ++}; ++ ++ + /* Not all of these give usefully different compilation alternatives, + but there is no simple way of generalizing them. */ + static const struct processors all_cores[] = + { + /* ARM Cores */ + #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ +- {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs}, ++ {NAME, IDENT, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune}, + #include "arm-cores.def" + #undef ARM_CORE + {NULL, arm_none, NULL, 0, NULL} +@@ -756,7 +828,7 @@ + static const struct processors all_architectures[] = + { + /* ARM Architectures */ +- /* We don't specify rtx_costs here as it will be figured out ++ /* We don't specify tuning costs here as it will be figured out + from the core. */ + + {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, +@@ -782,36 +854,19 @@ + {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL}, + {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL}, + {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL}, +- {"armv7e-m", cortexm3, "7EM", FL_CO_PROC | FL_FOR_ARCH7EM, NULL}, ++ {"armv7e-m", cortexm4, "7EM", FL_CO_PROC | FL_FOR_ARCH7EM, NULL}, + {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, + {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, + {"iwmmxt2", iwmmxt2, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, + {NULL, arm_none, NULL, 0 , NULL} + }; + +-struct arm_cpu_select +-{ +- const char * string; +- const char * name; +- const struct processors * processors; +-}; +- +-/* This is a magic structure. The 'string' field is magically filled in +- with a pointer to the value specified by the user on the command line +- assuming that the user has specified such a value. */ +- +-static struct arm_cpu_select arm_select[] = +-{ +- /* string name processors */ +- { NULL, "-mcpu=", all_cores }, +- { NULL, "-march=", all_architectures }, +- { NULL, "-mtune=", all_cores } +-}; + +-/* Defines representing the indexes into the above table. */ +-#define ARM_OPT_SET_CPU 0 +-#define ARM_OPT_SET_ARCH 1 +-#define ARM_OPT_SET_TUNE 2 ++/* These are populated as commandline arguments are processed, or NULL ++ if not specified. */ ++static const struct processors *arm_selected_arch; ++static const struct processors *arm_selected_cpu; ++static const struct processors *arm_selected_tune; + + /* The name of the preprocessor macro to define for this architecture. */ + +@@ -905,6 +960,13 @@ + TLS_LE32 + }; + ++/* The maximum number of insns to be used when loading a constant. */ ++inline static int ++arm_constant_limit (bool size_p) ++{ ++ return size_p ? 1 : current_tune->constant_limit; ++} ++ + /* Emit an insn that's a simple single-set. Both the operands must be known + to be valid. */ + inline static rtx +@@ -1045,12 +1107,12 @@ + /* Conversions. */ + set_conv_libfunc (trunc_optab, HFmode, SFmode, + (arm_fp16_format == ARM_FP16_FORMAT_IEEE +- ? "__gnu_f2h_ieee" +- : "__gnu_f2h_alternative")); ++ ? "__aeabi_f2h" ++ : "__aeabi_f2h_alt")); + set_conv_libfunc (sext_optab, SFmode, HFmode, + (arm_fp16_format == ARM_FP16_FORMAT_IEEE +- ? "__gnu_h2f_ieee" +- : "__gnu_h2f_alternative")); ++ ? "__aeabi_h2f" ++ : "__aeabi_h2f_alt")); + + /* Arithmetic. */ + set_optab_libfunc (add_optab, HFmode, NULL); +@@ -1114,6 +1176,7 @@ + va_list_type); + DECL_ARTIFICIAL (va_list_name) = 1; + TYPE_NAME (va_list_type) = va_list_name; ++ TYPE_STUB_DECL (va_list_type) = va_list_name; + /* Create the __ap field. */ + ap_field = build_decl (BUILTINS_LOCATION, + FIELD_DECL, +@@ -1166,6 +1229,24 @@ + return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); + } + ++/* Lookup NAME in SEL. */ ++ ++static const struct processors * ++arm_find_cpu (const char *name, const struct processors *sel, const char *desc) ++{ ++ if (!(name && *name)) ++ return NULL; ++ ++ for (; sel->name != NULL; sel++) ++ { ++ if (streq (name, sel->name)) ++ return sel; ++ } ++ ++ error ("bad value (%s) for %s switch", name, desc); ++ return NULL; ++} ++ + /* Implement TARGET_HANDLE_OPTION. */ + + static bool +@@ -1174,11 +1255,11 @@ + switch (code) + { + case OPT_march_: +- arm_select[1].string = arg; ++ arm_selected_arch = arm_find_cpu(arg, all_architectures, "-march"); + return true; + + case OPT_mcpu_: +- arm_select[0].string = arg; ++ arm_selected_cpu = arm_find_cpu(arg, all_cores, "-mcpu"); + return true; + + case OPT_mhard_float: +@@ -1190,7 +1271,7 @@ + return true; + + case OPT_mtune_: +- arm_select[2].string = arg; ++ arm_selected_tune = arm_find_cpu(arg, all_cores, "-mtune"); + return true; + + default: +@@ -1290,88 +1371,52 @@ + arm_override_options (void) + { + unsigned i; +- enum processor_type target_arch_cpu = arm_none; +- enum processor_type selected_cpu = arm_none; + +- /* Set up the flags based on the cpu/architecture selected by the user. */ +- for (i = ARRAY_SIZE (arm_select); i--;) ++ if (arm_selected_arch) + { +- struct arm_cpu_select * ptr = arm_select + i; +- +- if (ptr->string != NULL && ptr->string[0] != '\0') +- { +- const struct processors * sel; +- +- for (sel = ptr->processors; sel->name != NULL; sel++) +- if (streq (ptr->string, sel->name)) +- { +- /* Set the architecture define. */ +- if (i != ARM_OPT_SET_TUNE) +- sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); +- +- /* Determine the processor core for which we should +- tune code-generation. */ +- if (/* -mcpu= is a sensible default. */ +- i == ARM_OPT_SET_CPU +- /* -mtune= overrides -mcpu= and -march=. */ +- || i == ARM_OPT_SET_TUNE) +- arm_tune = (enum processor_type) (sel - ptr->processors); +- +- /* Remember the CPU associated with this architecture. +- If no other option is used to set the CPU type, +- we'll use this to guess the most suitable tuning +- options. */ +- if (i == ARM_OPT_SET_ARCH) +- target_arch_cpu = sel->core; +- +- if (i == ARM_OPT_SET_CPU) +- selected_cpu = (enum processor_type) (sel - ptr->processors); +- +- if (i != ARM_OPT_SET_TUNE) +- { +- /* If we have been given an architecture and a processor +- make sure that they are compatible. We only generate +- a warning though, and we prefer the CPU over the +- architecture. */ +- if (insn_flags != 0 && (insn_flags ^ sel->flags)) +- warning (0, "switch -mcpu=%s conflicts with -march= switch", +- ptr->string); +- +- insn_flags = sel->flags; +- } +- +- break; +- } ++ if (arm_selected_cpu) ++ { ++ /* Check for conflict between mcpu and march */ ++ if ((arm_selected_cpu->flags ^ arm_selected_arch->flags) & ~FL_TUNE) ++ { ++ warning (0, "switch -mcpu=%s conflicts with -march=%s switch", ++ arm_selected_cpu->name, arm_selected_arch->name); ++ /* -march wins for code generation. ++ -mcpu wins for default tuning. */ ++ if (!arm_selected_tune) ++ arm_selected_tune = arm_selected_cpu; + +- if (sel->name == NULL) +- error ("bad value (%s) for %s switch", ptr->string, ptr->name); +- } ++ arm_selected_cpu = arm_selected_arch; ++ } ++ else ++ /* -mcpu wins. */ ++ arm_selected_arch = NULL; ++ } ++ else ++ /* Pick a CPU based on the architecture. */ ++ arm_selected_cpu = arm_selected_arch; + } + +- /* Guess the tuning options from the architecture if necessary. */ +- if (arm_tune == arm_none) +- arm_tune = target_arch_cpu; +- + /* If the user did not specify a processor, choose one for them. */ +- if (insn_flags == 0) ++ if (!arm_selected_cpu) + { + const struct processors * sel; + unsigned int sought; + +- selected_cpu = (enum processor_type) TARGET_CPU_DEFAULT; +- if (selected_cpu == arm_none) ++ arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT]; ++ if (!arm_selected_cpu->name) + { + #ifdef SUBTARGET_CPU_DEFAULT + /* Use the subtarget default CPU if none was specified by + configure. */ +- selected_cpu = (enum processor_type) SUBTARGET_CPU_DEFAULT; ++ arm_selected_cpu = &all_cores[SUBTARGET_CPU_DEFAULT]; + #endif + /* Default to ARM6. */ +- if (selected_cpu == arm_none) +- selected_cpu = arm6; ++ if (arm_selected_cpu->name) ++ arm_selected_cpu = &all_cores[arm6]; + } +- sel = &all_cores[selected_cpu]; + ++ sel = arm_selected_cpu; + insn_flags = sel->flags; + + /* Now check to see if the user has specified some command line +@@ -1432,19 +1477,31 @@ + sel = best_fit; + } + +- insn_flags = sel->flags; ++ arm_selected_cpu = sel; + } +- sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); +- arm_default_cpu = (enum processor_type) (sel - all_cores); +- if (arm_tune == arm_none) +- arm_tune = arm_default_cpu; + } + +- /* The processor for which we should tune should now have been +- chosen. */ +- gcc_assert (arm_tune != arm_none); ++ gcc_assert (arm_selected_cpu); ++ /* The selected cpu may be an architecture, so lookup tuning by core ID. */ ++ if (!arm_selected_tune) ++ arm_selected_tune = &all_cores[arm_selected_cpu->core]; + +- tune_flags = all_cores[(int)arm_tune].flags; ++ sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_selected_cpu->arch); ++ insn_flags = arm_selected_cpu->flags; ++ ++ arm_tune = arm_selected_tune->core; ++ tune_flags = arm_selected_tune->flags; ++ current_tune = arm_selected_tune->tune; ++ ++ if (arm_tune == cortexa8 && optimize >= 3) ++ { ++ /* These alignments were experimentally determined to improve SPECint ++ performance on SPECCPU 2000. */ ++ if (align_functions <= 0) ++ align_functions = 16; ++ if (align_jumps <= 0) ++ align_jumps = 16; ++ } + + if (target_fp16_format_name) + { +@@ -1555,6 +1612,7 @@ + arm_arch6 = (insn_flags & FL_ARCH6) != 0; + arm_arch6k = (insn_flags & FL_ARCH6K) != 0; + arm_arch_notm = (insn_flags & FL_NOTM) != 0; ++ arm_arch7 = (insn_flags & FL_ARCH7) != 0; + arm_arch7em = (insn_flags & FL_ARCH7EM) != 0; + arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; + arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; +@@ -1567,6 +1625,7 @@ + arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; + arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; + arm_arch_hwdiv = (insn_flags & FL_DIV) != 0; ++ arm_tune_cortex_a5 = (arm_tune == cortexa5) != 0; + arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; + + /* If we are not using the default (ARM mode) section anchor offset +@@ -1827,12 +1886,16 @@ + /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */ + if (fix_cm3_ldrd == 2) + { +- if (selected_cpu == cortexm3) ++ if (arm_selected_cpu->core == cortexm3) + fix_cm3_ldrd = 1; + else + fix_cm3_ldrd = 0; + } + ++ /* Disable -fsched-interblock for Cortex-M4. */ ++ if (arm_selected_tune->core == cortexm4) ++ flag_schedule_interblock = 0; ++ + if (TARGET_THUMB1 && flag_schedule_insns) + { + /* Don't warn since it's on by default in -O2. */ +@@ -1841,30 +1904,21 @@ + + if (optimize_size) + { +- arm_constant_limit = 1; +- + /* If optimizing for size, bump the number of instructions that we + are prepared to conditionally execute (even on a StrongARM). */ + max_insns_skipped = 6; + } + else + { +- /* For processors with load scheduling, it never costs more than +- 2 cycles to load a constant, and the load scheduler may well +- reduce that to 1. */ +- if (arm_ld_sched) +- arm_constant_limit = 1; +- +- /* On XScale the longer latency of a load makes it more difficult +- to achieve a good schedule, so it's faster to synthesize +- constants that can be done in two insns. */ +- if (arm_tune_xscale) +- arm_constant_limit = 2; +- + /* StrongARM has early execution of branches, so a sequence + that is worth skipping is shorter. */ + if (arm_tune_strongarm) + max_insns_skipped = 3; ++ ++ /* Branches can be dual-issued on Cortex-A5, so conditional execution is ++ less appealing. */ ++ if (arm_tune_cortex_a5) ++ max_insns_skipped = 1; + } + + /* Hot/Cold partitioning is not currently supported, since we can't +@@ -1877,8 +1931,28 @@ + flag_reorder_blocks = 1; + } + ++ if (!PARAM_SET_P (PARAM_GCSE_UNRESTRICTED_COST) ++ && flag_pic) ++ /* Hoisting PIC address calculations more aggressively provides a small, ++ but measurable, size reduction for PIC code. Therefore, we decrease ++ the bar for unrestricted expression hoisting to the cost of PIC address ++ calculation, which is 2 instructions. */ ++ set_param_value ("gcse-unrestricted-cost", 2); ++ ++ /* ARM EABI defaults to strict volatile bitfields. */ ++ if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0 ++ && abi_version_at_least(2)) ++ flag_strict_volatile_bitfields = 1; ++ + /* Register global variables with the garbage collector. */ + arm_add_gc_roots (); ++ ++ if (low_irq_latency && TARGET_THUMB) ++ { ++ warning (0, ++ "-mlow-irq-latency has no effect when compiling for Thumb"); ++ low_irq_latency = 0; ++ } + } + + static void +@@ -2008,6 +2082,14 @@ + return !IS_NAKED (arm_current_func_type ()); + } + ++static bool ++arm_warn_func_result (void) ++{ ++ /* Naked functions are implemented entirely in assembly, including the ++ return sequence, so suppress warnings about this. */ ++ return !IS_NAKED (arm_current_func_type ()); ++} ++ + + /* Output assembler code for a block containing the constant parts + of a trampoline, leaving space for the variable parts. +@@ -2087,6 +2169,18 @@ + return addr; + } + ++/* Return true if we should try to use a simple_return insn, i.e. perform ++ shrink-wrapping if possible. This is the case if we need to emit a ++ prologue, which we can test by looking at the offsets. */ ++bool ++use_simple_return_p (void) ++{ ++ arm_stack_offsets *offsets; ++ ++ offsets = arm_get_frame_offsets (); ++ return offsets->outgoing_args != 0; ++} ++ + /* Return 1 if it is possible to return using a single instruction. + If SIBLING is non-null, this is a test for a return before a sibling + call. SIBLING is the call insn, so we can examine its register usage. */ +@@ -2265,11 +2359,17 @@ + { + HOST_WIDE_INT v; + +- /* Allow repeated pattern. */ ++ /* Allow repeated patterns 0x00XY00XY or 0xXYXYXYXY. */ + v = i & 0xff; + v |= v << 16; + if (i == v || i == (v | (v << 8))) + return TRUE; ++ ++ /* Allow repeated pattern 0xXY00XY00. */ ++ v = i & 0xff00; ++ v |= v << 16; ++ if (i == v) ++ return TRUE; + } + + return FALSE; +@@ -2361,7 +2461,8 @@ + && !cond + && (arm_gen_constant (code, mode, NULL_RTX, val, target, source, + 1, 0) +- > arm_constant_limit + (code != SET))) ++ > (arm_constant_limit (optimize_function_for_size_p (cfun)) ++ + (code != SET)))) + { + if (code == SET) + { +@@ -3190,13 +3291,82 @@ + immediate value easier to load. */ + + enum rtx_code +-arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode, +- rtx * op1) ++arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1) + { +- unsigned HOST_WIDE_INT i = INTVAL (*op1); +- unsigned HOST_WIDE_INT maxval; ++ enum machine_mode mode; ++ unsigned HOST_WIDE_INT i, maxval; ++ ++ mode = GET_MODE (*op0); ++ if (mode == VOIDmode) ++ mode = GET_MODE (*op1); ++ + maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1; + ++ /* For DImode, we have GE/LT/GEU/LTU comparisons. In ARM mode ++ we can also use cmp/cmpeq for GTU/LEU. GT/LE must be either ++ reversed or (for constant OP1) adjusted to GE/LT. Similarly ++ for GTU/LEU in Thumb mode. */ ++ if (mode == DImode) ++ { ++ rtx tem; ++ ++ /* To keep things simple, always use the Cirrus cfcmp64 if it is ++ available. */ ++ if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ return code; ++ ++ if (code == GT || code == LE ++ || (!TARGET_ARM && (code == GTU || code == LEU))) ++ { ++ /* Missing comparison. First try to use an available ++ comparison. */ ++ if (GET_CODE (*op1) == CONST_INT) ++ { ++ i = INTVAL (*op1); ++ switch (code) ++ { ++ case GT: ++ case LE: ++ if (i != maxval ++ && arm_const_double_by_immediates (GEN_INT (i + 1))) ++ { ++ *op1 = GEN_INT (i + 1); ++ return code == GT ? GE : LT; ++ } ++ break; ++ case GTU: ++ case LEU: ++ if (i != ~((unsigned HOST_WIDE_INT) 0) ++ && arm_const_double_by_immediates (GEN_INT (i + 1))) ++ { ++ *op1 = GEN_INT (i + 1); ++ return code == GTU ? GEU : LTU; ++ } ++ break; ++ default: ++ gcc_unreachable (); ++ } ++ } ++ ++ /* If that did not work, reverse the condition. */ ++ tem = *op0; ++ *op0 = *op1; ++ *op1 = tem; ++ return swap_condition (code); ++ } ++ ++ return code; ++ } ++ ++ /* Comparisons smaller than DImode. Only adjust comparisons against ++ an out-of-range constant. */ ++ if (GET_CODE (*op1) != CONST_INT ++ || const_ok_for_arm (INTVAL (*op1)) ++ || const_ok_for_arm (- INTVAL (*op1))) ++ return code; ++ ++ i = INTVAL (*op1); ++ + switch (code) + { + case EQ: +@@ -3345,6 +3515,28 @@ + convert_optab_libfunc (sfix_optab, DImode, SFmode)); + add_libcall (libcall_htab, + convert_optab_libfunc (ufix_optab, DImode, SFmode)); ++ ++ /* Values from double-precision helper functions are returned in core ++ registers if the selected core only supports single-precision ++ arithmetic, even if we are using the hard-float ABI. */ ++ if (TARGET_VFP) ++ { ++ add_libcall (libcall_htab, optab_libfunc (add_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (sdiv_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (smul_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (neg_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (sub_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (eq_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (lt_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (le_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (ge_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (gt_optab, DFmode)); ++ add_libcall (libcall_htab, optab_libfunc (unord_optab, DFmode)); ++ add_libcall (libcall_htab, ++ convert_optab_libfunc (sext_optab, DFmode, SFmode)); ++ add_libcall (libcall_htab, ++ convert_optab_libfunc (trunc_optab, SFmode, DFmode)); ++ } + } + + return libcall && htab_find (libcall_htab, libcall) != NULL; +@@ -3838,7 +4030,18 @@ + use_vfp_abi (enum arm_pcs pcs_variant, bool is_double) + { + if (pcs_variant == ARM_PCS_AAPCS_VFP) +- return true; ++ { ++ static bool seen_thumb1_vfp = false; ++ ++ if (TARGET_THUMB1 && !seen_thumb1_vfp) ++ { ++ sorry ("Thumb-1 hard-float VFP ABI"); ++ /* sorry() is not immediately fatal, so only display this once. */ ++ seen_thumb1_vfp = true; ++ } ++ ++ return true; ++ } + + if (pcs_variant != ARM_PCS_AAPCS_LOCAL) + return false; +@@ -4298,6 +4501,31 @@ + if (arm_libcall_uses_aapcs_base (libname)) + pcum->pcs_variant = ARM_PCS_AAPCS; + ++ /* We must pass arguments to double-precision helper functions in core ++ registers if we only have hardware support for single-precision ++ arithmetic, even if we are using the hard-float ABI. */ ++ if (TARGET_VFP ++ && (rtx_equal_p (libname, optab_libfunc (add_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (sdiv_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (smul_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (neg_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (sub_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (eq_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (lt_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (le_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (ge_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (gt_optab, DFmode)) ++ || rtx_equal_p (libname, optab_libfunc (unord_optab, DFmode)) ++ || rtx_equal_p (libname, convert_optab_libfunc (sext_optab, ++ DFmode, SFmode)) ++ || rtx_equal_p (libname, convert_optab_libfunc (trunc_optab, ++ SFmode, DFmode)) ++ || rtx_equal_p (libname, convert_optab_libfunc (sfix_optab, ++ SImode, DFmode)) ++ || rtx_equal_p (libname, convert_optab_libfunc (ufix_optab, ++ SImode, DFmode)))) ++ pcum->pcs_variant = ARM_PCS_AAPCS; ++ + pcum->aapcs_ncrn = pcum->aapcs_next_ncrn = 0; + pcum->aapcs_reg = NULL_RTX; + pcum->aapcs_partial = 0; +@@ -4778,8 +5006,8 @@ + return false; + + /* Never tailcall something for which we have no decl, or if we +- are in Thumb mode. */ +- if (decl == NULL || TARGET_THUMB) ++ are generating code for Thumb-1. */ ++ if (decl == NULL || TARGET_THUMB1) + return false; + + /* The PIC register is live on entry to VxWorks PLT entries, so we +@@ -4870,7 +5098,7 @@ + } + else + { +- rtx seq; ++ rtx seq, insn; + + if (!cfun->machine->pic_reg) + cfun->machine->pic_reg = gen_reg_rtx (Pmode); +@@ -4887,6 +5115,11 @@ + + seq = get_insns (); + end_sequence (); ++ ++ for (insn = seq; insn; insn = NEXT_INSN (insn)) ++ if (INSN_P (insn)) ++ INSN_LOCATOR (insn) = prologue_locator; ++ + /* We can be called during expansion of PHI nodes, where + we can't yet emit instructions directly in the final + insn stream. Queue the insns on the entry edge, they will +@@ -4903,31 +5136,14 @@ + if (GET_CODE (orig) == SYMBOL_REF + || GET_CODE (orig) == LABEL_REF) + { +- rtx pic_ref, address; + rtx insn; +- int subregs = 0; +- +- /* If this function doesn't have a pic register, create one now. */ +- require_pic_register (); + + if (reg == 0) + { + gcc_assert (can_create_pseudo_p ()); + reg = gen_reg_rtx (Pmode); +- +- subregs = 1; + } + +- if (subregs) +- address = gen_reg_rtx (Pmode); +- else +- address = reg; +- +- if (TARGET_32BIT) +- emit_insn (gen_pic_load_addr_32bit (address, orig)); +- else /* TARGET_THUMB1 */ +- emit_insn (gen_pic_load_addr_thumb1 (address, orig)); +- + /* VxWorks does not impose a fixed gap between segments; the run-time + gap can be different from the object-file gap. We therefore can't + use GOTOFF unless we are absolutely sure that the symbol is in the +@@ -4939,15 +5155,25 @@ + SYMBOL_REF_LOCAL_P (orig))) + && NEED_GOT_RELOC + && !TARGET_VXWORKS_RTP) +- pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address); ++ insn = arm_pic_static_addr (orig, reg); + else + { +- pic_ref = gen_const_mem (Pmode, +- gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, +- address)); +- } ++ rtx pat; ++ rtx mem; ++ ++ /* If this function doesn't have a pic register, create one now. */ ++ require_pic_register (); ++ ++ pat = gen_calculate_pic_address (reg, cfun->machine->pic_reg, orig); ++ ++ /* Make the MEM as close to a constant as possible. */ ++ mem = SET_SRC (pat); ++ gcc_assert (MEM_P (mem) && !MEM_VOLATILE_P (mem)); ++ MEM_READONLY_P (mem) = 1; ++ MEM_NOTRAP_P (mem) = 1; + +- insn = emit_move_insn (reg, pic_ref); ++ insn = emit_insn (pat); ++ } + + /* Put a REG_EQUAL note on this insn, so that it can be optimized + by loop. */ +@@ -5155,6 +5381,43 @@ + emit_use (pic_reg); + } + ++/* Generate code to load the address of a static var when flag_pic is set. */ ++static rtx ++arm_pic_static_addr (rtx orig, rtx reg) ++{ ++ rtx l1, labelno, offset_rtx, insn; ++ ++ gcc_assert (flag_pic); ++ ++ /* We use an UNSPEC rather than a LABEL_REF because this label ++ never appears in the code stream. */ ++ labelno = GEN_INT (pic_labelno++); ++ l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); ++ l1 = gen_rtx_CONST (VOIDmode, l1); ++ ++ /* On the ARM the PC register contains 'dot + 8' at the time of the ++ addition, on the Thumb it is 'dot + 4'. */ ++ offset_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4); ++ offset_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, orig, offset_rtx), ++ UNSPEC_SYMBOL_OFFSET); ++ offset_rtx = gen_rtx_CONST (Pmode, offset_rtx); ++ ++ if (TARGET_32BIT) ++ { ++ emit_insn (gen_pic_load_addr_32bit (reg, offset_rtx)); ++ if (TARGET_ARM) ++ insn = emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); ++ else ++ insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); ++ } ++ else /* TARGET_THUMB1 */ ++ { ++ emit_insn (gen_pic_load_addr_thumb1 (reg, offset_rtx)); ++ insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); ++ } ++ ++ return insn; ++} + + /* Return nonzero if X is valid as an ARM state addressing register. */ + static int +@@ -5189,6 +5452,15 @@ + return FALSE; + } + ++/* Return true if X will surely end up in an index register after next ++ splitting pass. */ ++static bool ++will_be_in_index_register (const_rtx x) ++{ ++ /* arm.md: calculate_pic_address will split this into a register. */ ++ return GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_SYM; ++} ++ + /* Return nonzero if X is a valid ARM state address operand. */ + int + arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer, +@@ -5246,8 +5518,9 @@ + rtx xop1 = XEXP (x, 1); + + return ((arm_address_register_rtx_p (xop0, strict_p) +- && GET_CODE(xop1) == CONST_INT +- && arm_legitimate_index_p (mode, xop1, outer, strict_p)) ++ && ((GET_CODE(xop1) == CONST_INT ++ && arm_legitimate_index_p (mode, xop1, outer, strict_p)) ++ || (!strict_p && will_be_in_index_register (xop1)))) + || (arm_address_register_rtx_p (xop1, strict_p) + && arm_legitimate_index_p (mode, xop0, outer, strict_p))); + } +@@ -5333,7 +5606,8 @@ + rtx xop1 = XEXP (x, 1); + + return ((arm_address_register_rtx_p (xop0, strict_p) +- && thumb2_legitimate_index_p (mode, xop1, strict_p)) ++ && (thumb2_legitimate_index_p (mode, xop1, strict_p) ++ || (!strict_p && will_be_in_index_register (xop1)))) + || (arm_address_register_rtx_p (xop1, strict_p) + && thumb2_legitimate_index_p (mode, xop0, strict_p))); + } +@@ -5367,13 +5641,25 @@ + && INTVAL (index) > -1024 + && (INTVAL (index) & 3) == 0); + +- if (TARGET_NEON +- && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) ++ /* For quad modes, we restrict the constant offset to be slightly less ++ than what the instruction format permits. We do this because for ++ quad mode moves, we will actually decompose them into two separate ++ double-mode reads or writes. INDEX must therefore be a valid ++ (double-mode) offset and so should INDEX+8. */ ++ if (TARGET_NEON && VALID_NEON_QREG_MODE (mode)) + return (code == CONST_INT + && INTVAL (index) < 1016 + && INTVAL (index) > -1024 + && (INTVAL (index) & 3) == 0); + ++ /* We have no such constraint on double mode offsets, so we permit the ++ full range of the instruction format. */ ++ if (TARGET_NEON && VALID_NEON_DREG_MODE (mode)) ++ return (code == CONST_INT ++ && INTVAL (index) < 1024 ++ && INTVAL (index) > -1024 ++ && (INTVAL (index) & 3) == 0); ++ + if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) + return (code == CONST_INT + && INTVAL (index) < 1024 +@@ -5487,13 +5773,25 @@ + && (INTVAL (index) & 3) == 0); + } + +- if (TARGET_NEON +- && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) ++ /* For quad modes, we restrict the constant offset to be slightly less ++ than what the instruction format permits. We do this because for ++ quad mode moves, we will actually decompose them into two separate ++ double-mode reads or writes. INDEX must therefore be a valid ++ (double-mode) offset and so should INDEX+8. */ ++ if (TARGET_NEON && VALID_NEON_QREG_MODE (mode)) + return (code == CONST_INT + && INTVAL (index) < 1016 + && INTVAL (index) > -1024 + && (INTVAL (index) & 3) == 0); + ++ /* We have no such constraint on double mode offsets, so we permit the ++ full range of the instruction format. */ ++ if (TARGET_NEON && VALID_NEON_DREG_MODE (mode)) ++ return (code == CONST_INT ++ && INTVAL (index) < 1024 ++ && INTVAL (index) > -1024 ++ && (INTVAL (index) & 3) == 0); ++ + if (arm_address_register_rtx_p (index, strict_p) + && (GET_MODE_SIZE (mode) <= 4)) + return 1; +@@ -5636,7 +5934,8 @@ + && XEXP (x, 0) != frame_pointer_rtx + && XEXP (x, 1) != frame_pointer_rtx + && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) +- && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p)) ++ && (thumb1_index_register_rtx_p (XEXP (x, 1), strict_p) ++ || (!strict_p && will_be_in_index_register (XEXP (x, 1))))) + return 1; + + /* REG+const has 5-7 bit offset for non-SP registers. */ +@@ -6179,6 +6478,7 @@ + thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) + { + enum machine_mode mode = GET_MODE (x); ++ int total; + + switch (code) + { +@@ -6215,12 +6515,16 @@ + + case CONST_INT: + if (outer == SET) +- { +- if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) +- return 0; +- if (thumb_shiftable_const (INTVAL (x))) +- return COSTS_N_INSNS (2); +- return COSTS_N_INSNS (3); ++ { ++ if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) ++ return COSTS_N_INSNS (1); ++ /* See split "TARGET_THUMB1 && satisfies_constraint_J". */ ++ if (INTVAL (x) >= -255 && INTVAL (x) <= -1) ++ return COSTS_N_INSNS (2); ++ /* See split "TARGET_THUMB1 && satisfies_constraint_K". */ ++ if (thumb_shiftable_const (INTVAL (x))) ++ return COSTS_N_INSNS (2); ++ return COSTS_N_INSNS (3); + } + else if ((outer == PLUS || outer == COMPARE) + && INTVAL (x) < 256 && INTVAL (x) > -256) +@@ -6277,24 +6581,20 @@ + return 14; + return 2; + ++ case SIGN_EXTEND: + case ZERO_EXTEND: +- /* XXX still guessing. */ +- switch (GET_MODE (XEXP (x, 0))) +- { +- case QImode: +- return (1 + (mode == DImode ? 4 : 0) +- + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); +- +- case HImode: +- return (4 + (mode == DImode ? 4 : 0) +- + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); ++ total = mode == DImode ? COSTS_N_INSNS (1) : 0; ++ total += thumb1_rtx_costs (XEXP (x, 0), GET_CODE (XEXP (x, 0)), code); + +- case SImode: +- return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); ++ if (mode == SImode) ++ return total; + +- default: +- return 99; +- } ++ if (arm_arch6) ++ return total + COSTS_N_INSNS (1); ++ ++ /* Assume a two-shift sequence. Increase the cost slightly so ++ we prefer actual shifts over an extend operation. */ ++ return total + 1 + COSTS_N_INSNS (2); + + default: + return 99; +@@ -6364,23 +6664,6 @@ + return true; + + case MINUS: +- if (TARGET_THUMB2) +- { +- if (GET_MODE_CLASS (mode) == MODE_FLOAT) +- { +- if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) +- *total = COSTS_N_INSNS (1); +- else +- *total = COSTS_N_INSNS (20); +- } +- else +- *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); +- /* Thumb2 does not have RSB, so all arguments must be +- registers (subtracting a constant is canonicalized as +- addition of the negated constant). */ +- return false; +- } +- + if (mode == DImode) + { + *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); +@@ -6474,6 +6757,19 @@ + return true; + } + ++ /* MLS is just as expensive as its underlying multiplication. ++ Exclude a shift by a constant, which is expressed as a ++ multiplication. */ ++ if (TARGET_32BIT && arm_arch_thumb2 ++ && GET_CODE (XEXP (x, 1)) == MULT ++ && ! (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT ++ && ((INTVAL (XEXP (XEXP (x, 1), 1)) & ++ (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0))) ++ { ++ /* The cost comes from the cost of the multiply. */ ++ return false; ++ } ++ + /* Fall through */ + + case PLUS: +@@ -6539,12 +6835,10 @@ + since then they might not be moved outside of loops. As a compromise + we allow integration with ops that have a constant as their second + operand. */ +- if ((REG_OR_SUBREG_REG (XEXP (x, 0)) +- && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) +- && GET_CODE (XEXP (x, 1)) != CONST_INT) +- || (REG_OR_SUBREG_REG (XEXP (x, 0)) +- && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) +- *total = 4; ++ if (REG_OR_SUBREG_REG (XEXP (x, 0)) ++ && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) ++ && GET_CODE (XEXP (x, 1)) != CONST_INT) ++ *total = COSTS_N_INSNS (1); + + if (mode == DImode) + { +@@ -6782,44 +7076,39 @@ + return false; + + case SIGN_EXTEND: +- if (GET_MODE_CLASS (mode) == MODE_INT) +- { +- *total = 0; +- if (mode == DImode) +- *total += COSTS_N_INSNS (1); +- +- if (GET_MODE (XEXP (x, 0)) != SImode) +- { +- if (arm_arch6) +- { +- if (GET_CODE (XEXP (x, 0)) != MEM) +- *total += COSTS_N_INSNS (1); +- } +- else if (!arm_arch4 || GET_CODE (XEXP (x, 0)) != MEM) +- *total += COSTS_N_INSNS (2); +- } +- +- return false; +- } +- +- /* Fall through */ + case ZERO_EXTEND: + *total = 0; + if (GET_MODE_CLASS (mode) == MODE_INT) + { ++ rtx op = XEXP (x, 0); ++ enum machine_mode opmode = GET_MODE (op); ++ + if (mode == DImode) + *total += COSTS_N_INSNS (1); + +- if (GET_MODE (XEXP (x, 0)) != SImode) ++ if (opmode != SImode) + { +- if (arm_arch6) ++ if (MEM_P (op)) + { +- if (GET_CODE (XEXP (x, 0)) != MEM) +- *total += COSTS_N_INSNS (1); ++ /* If !arm_arch4, we use one of the extendhisi2_mem ++ or movhi_bytes patterns for HImode. For a QImode ++ sign extension, we first zero-extend from memory ++ and then perform a shift sequence. */ ++ if (!arm_arch4 && (opmode != QImode || code == SIGN_EXTEND)) ++ *total += COSTS_N_INSNS (2); + } +- else if (!arm_arch4 || GET_CODE (XEXP (x, 0)) != MEM) +- *total += COSTS_N_INSNS (GET_MODE (XEXP (x, 0)) == QImode ? +- 1 : 2); ++ else if (arm_arch6) ++ *total += COSTS_N_INSNS (1); ++ ++ /* We don't have the necessary insn, so we need to perform some ++ other operation. */ ++ else if (TARGET_ARM && code == ZERO_EXTEND && mode == QImode) ++ /* An and with constant 255. */ ++ *total += COSTS_N_INSNS (1); ++ else ++ /* A shift sequence. Increase costs slightly to avoid ++ combining two shifts into an extend operation. */ ++ *total += COSTS_N_INSNS (2) + 1; + } + + return false; +@@ -6878,6 +7167,17 @@ + *total = COSTS_N_INSNS (4); + return true; + ++ case CONST_VECTOR: ++ if (TARGET_NEON ++ && TARGET_HARD_FLOAT ++ && outer == SET ++ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) ++ && neon_immediate_valid_for_move (x, mode, NULL, NULL)) ++ *total = COSTS_N_INSNS (1); ++ else ++ *total = COSTS_N_INSNS (4); ++ return true; ++ + default: + *total = COSTS_N_INSNS (4); + return false; +@@ -6905,6 +7205,12 @@ + a single register, otherwise it costs one insn per word. */ + if (REG_P (XEXP (x, 0))) + *total = COSTS_N_INSNS (1); ++ else if (flag_pic ++ && GET_CODE (XEXP (x, 0)) == PLUS ++ && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) ++ /* This will be split into two instructions. ++ See arm.md:calculate_pic_address. */ ++ *total = COSTS_N_INSNS (2); + else + *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); + return true; +@@ -7052,41 +7358,8 @@ + return false; + + case SIGN_EXTEND: +- *total = 0; +- if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4) +- { +- if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) +- *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); +- } +- if (mode == DImode) +- *total += COSTS_N_INSNS (1); +- return false; +- + case ZERO_EXTEND: +- *total = 0; +- if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) +- { +- switch (GET_MODE (XEXP (x, 0))) +- { +- case QImode: +- *total += COSTS_N_INSNS (1); +- break; +- +- case HImode: +- *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); +- +- case SImode: +- break; +- +- default: +- *total += COSTS_N_INSNS (2); +- } +- } +- +- if (mode == DImode) +- *total += COSTS_N_INSNS (1); +- +- return false; ++ return arm_rtx_costs_1 (x, outer_code, total, 0); + + case CONST_INT: + if (const_ok_for_arm (INTVAL (x))) +@@ -7118,10 +7391,21 @@ + *total = COSTS_N_INSNS (4); + return true; + +- case HIGH: +- case LO_SUM: +- /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the +- cost of these slightly. */ ++ case CONST_VECTOR: ++ if (TARGET_NEON ++ && TARGET_HARD_FLOAT ++ && outer_code == SET ++ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) ++ && neon_immediate_valid_for_move (x, mode, NULL, NULL)) ++ *total = COSTS_N_INSNS (1); ++ else ++ *total = COSTS_N_INSNS (4); ++ return true; ++ ++ case HIGH: ++ case LO_SUM: ++ /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the ++ cost of these slightly. */ + *total = COSTS_N_INSNS (1) + 1; + return true; + +@@ -7134,18 +7418,387 @@ + } + } + ++static bool ++thumb2_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ++ int *total) ++{ ++ /* Attempt to give a lower cost to RTXs which can optimistically be ++ represented as short insns, assuming that the right conditions will hold ++ later (e.g. low registers will be chosen if a short insn requires them). ++ ++ Note that we don't make wide insns cost twice as much as narrow insns, ++ because we can't prove that a particular RTX will actually use a narrow ++ insn, because not enough information is available (e.g., we don't know ++ which hard registers pseudos will be assigned). Consider these to be ++ "expected" sizes/weightings. ++ ++ (COSTS_NARROW_INSNS has the same weight as COSTS_N_INSNS.) */ ++ ++#define COSTS_NARROW_INSNS(N) ((N) * 4) ++#define COSTS_WIDE_INSNS(N) ((N) * 6) ++#define THUMB2_LIBCALL_COST COSTS_WIDE_INSNS (2) ++ enum machine_mode mode = GET_MODE (x); ++ ++ switch (code) ++ { ++ case MEM: ++ if (REG_P (XEXP (x, 0))) ++ { ++ /* Hopefully this will use a narrow ldm/stm insn. */ ++ *total = COSTS_NARROW_INSNS (1); ++ return true; ++ } ++ else if ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF ++ && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))) ++ || reg_mentioned_p (virtual_stack_vars_rtx, XEXP (x, 0)) ++ || reg_mentioned_p (stack_pointer_rtx, XEXP (x, 0))) ++ { ++ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)); ++ return true; ++ } ++ else if (GET_CODE (XEXP (x, 0)) == PLUS) ++ { ++ rtx plus = XEXP (x, 0); ++ ++ if (GET_CODE (XEXP (plus, 1)) == CONST_INT) ++ { ++ HOST_WIDE_INT cst = INTVAL (XEXP (plus, 1)); ++ ++ if (cst >= 0 && cst < 256) ++ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)); ++ else ++ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); ++ ++ *total += rtx_cost (XEXP (plus, 0), code, false); ++ ++ return true; ++ } ++ } ++ ++ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)); ++ return false; ++ ++ case DIV: ++ case MOD: ++ case UDIV: ++ case UMOD: ++ if (arm_arch_hwdiv) ++ *total = COSTS_WIDE_INSNS (1); ++ else ++ *total = THUMB2_LIBCALL_COST; ++ return false; ++ ++ case ROTATE: ++ if (mode == SImode && REG_P (XEXP (x, 1))) ++ { ++ *total = COSTS_WIDE_INSNS (1) + COSTS_NARROW_INSNS (1) ++ + rtx_cost (XEXP (x, 0), code, false); ++ return true; ++ } ++ /* Fall through */ ++ ++ case ASHIFT: ++ case LSHIFTRT: ++ case ASHIFTRT: ++ if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) ++ { ++ *total = COSTS_WIDE_INSNS (3) + rtx_cost (XEXP (x, 0), code, false); ++ return true; ++ } ++ else if (mode == SImode) ++ { ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ } ++ ++ /* Needs a libcall. */ ++ *total = THUMB2_LIBCALL_COST; ++ return false; ++ ++ case ROTATERT: ++ if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) ++ { ++ *total = COSTS_WIDE_INSNS (3) + rtx_cost (XEXP (x, 0), code, false); ++ return true; ++ } ++ else if (mode == SImode) ++ { ++ if (GET_CODE (XEXP (x, 1)) == CONST_INT) ++ *total = COSTS_WIDE_INSNS (1) + rtx_cost (XEXP (x, 0), code, false); ++ else ++ *total = COSTS_NARROW_INSNS (1) ++ + rtx_cost (XEXP (x, 0), code, false); ++ return true; ++ } ++ ++ /* Needs a libcall. */ ++ *total = THUMB2_LIBCALL_COST; ++ return false; ++ ++ case MINUS: ++ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT ++ && (mode == SFmode || !TARGET_VFP_SINGLE)) ++ { ++ *total = COSTS_WIDE_INSNS (1); ++ return false; ++ } ++ ++ if (mode == SImode) ++ { ++ enum rtx_code subcode0 = GET_CODE (XEXP (x, 0)); ++ enum rtx_code subcode1 = GET_CODE (XEXP (x, 1)); ++ ++ if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT ++ || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT ++ || subcode1 == ROTATE || subcode1 == ROTATERT ++ || subcode1 == ASHIFT || subcode1 == LSHIFTRT ++ || subcode1 == ASHIFTRT) ++ { ++ /* It's just the cost of the two operands. */ ++ *total = 0; ++ return false; ++ } ++ ++ if (subcode1 == CONST_INT) ++ { ++ HOST_WIDE_INT cst = INTVAL (XEXP (x, 1)); ++ ++ if (cst >= 0 && cst < 256) ++ *total = COSTS_NARROW_INSNS (1); ++ else ++ *total = COSTS_WIDE_INSNS (1); ++ ++ *total += rtx_cost (XEXP (x, 0), code, false); ++ ++ return true; ++ } ++ ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ } ++ ++ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); ++ return false; ++ ++ case PLUS: ++ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT ++ && (mode == SFmode || !TARGET_VFP_SINGLE)) ++ { ++ *total = COSTS_WIDE_INSNS (1); ++ return false; ++ } ++ ++ /* Fall through */ ++ case AND: case XOR: case IOR: ++ if (mode == SImode) ++ { ++ enum rtx_code subcode = GET_CODE (XEXP (x, 0)); ++ ++ if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT ++ || subcode == LSHIFTRT || subcode == ASHIFTRT ++ || (code == AND && subcode == NOT)) ++ { ++ /* It's just the cost of the two operands. */ ++ *total = 0; ++ return false; ++ } ++ ++ if (code == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) ++ { ++ HOST_WIDE_INT cst = INTVAL (XEXP (x, 1)); ++ ++ if ((reg_mentioned_p (virtual_stack_vars_rtx, XEXP (x, 0)) ++ || reg_mentioned_p (stack_pointer_rtx, XEXP (x, 0))) ++ && cst > -512 && cst < 1024) ++ /* Only approximately correct, depending on destination ++ register. */ ++ *total = COSTS_NARROW_INSNS (1); ++ else if (cst > -256 && cst < 256) ++ *total = COSTS_NARROW_INSNS (1); ++ else ++ *total = COSTS_WIDE_INSNS (1); ++ ++ *total += rtx_cost (XEXP (x, 0), code, false); ++ ++ return true; ++ } ++ ++ if (subcode == MULT ++ && power_of_two_operand (XEXP (XEXP (x, 0), 1), mode)) ++ { ++ *total = COSTS_WIDE_INSNS (1) ++ + rtx_cost (XEXP (x, 1), code, false); ++ return true; ++ } ++ } ++ ++ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)); ++ return false; ++ ++ case MULT: ++ if (mode == SImode && GET_CODE (XEXP (x, 1)) != CONST_INT) ++ { ++ /* Might be using muls. */ ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ } ++ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); ++ return false; ++ ++ case NEG: ++ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT ++ && (mode == SFmode || !TARGET_VFP_SINGLE)) ++ { ++ *total = COSTS_WIDE_INSNS (1); ++ return false; ++ } ++ ++ /* Fall through */ ++ case NOT: ++ if (mode == SImode) ++ { ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ } ++ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); ++ return false; ++ ++ case IF_THEN_ELSE: ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ ++ case COMPARE: ++ if (cc_register (XEXP (x, 0), VOIDmode)) ++ *total = 0; ++ else ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ ++ case ABS: ++ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT ++ && (mode == SFmode || !TARGET_VFP_SINGLE)) ++ *total = COSTS_WIDE_INSNS (1); ++ else ++ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)) * 2; ++ return false; ++ ++ case SIGN_EXTEND: ++ if (GET_MODE_SIZE (mode) <= 4) ++ *total = GET_CODE (XEXP (x, 0)) == MEM ? 0 : COSTS_NARROW_INSNS (1); ++ else ++ *total = COSTS_NARROW_INSNS (1) ++ + COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); ++ return false; ++ ++ case ZERO_EXTEND: ++ if (GET_MODE_SIZE (mode) > 4) ++ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode) - 1); ++ else if (GET_CODE (XEXP (x, 0)) == MEM) ++ *total = 0; ++ else ++ *total = COSTS_NARROW_INSNS (1); ++ return false; ++ ++ case CONST_INT: ++ { ++ HOST_WIDE_INT cst = INTVAL (x); ++ ++ switch (outer_code) ++ { ++ case PLUS: ++ if (cst > -256 && cst < 256) ++ *total = 0; ++ else ++ /* See note about optabs below. */ ++ *total = COSTS_N_INSNS (1); ++ return true; ++ ++ case MINUS: ++ case COMPARE: ++ if (cst >= 0 && cst < 256) ++ *total = 0; ++ else ++ /* See note about optabs below. */ ++ *total = COSTS_N_INSNS (1); ++ return true; ++ ++ case ASHIFT: ++ case ASHIFTRT: ++ case LSHIFTRT: ++ *total = 0; ++ return true; ++ ++ default: ++ /* Constants are compared explicitly against COSTS_N_INSNS (1) in ++ optabs.c, creating an alternative, larger code sequence for more ++ expensive constants). So, it doesn't pay to make some constants ++ cost more than this. */ ++ *total = COSTS_N_INSNS (1); ++ } ++ return true; ++ } ++ ++ case CONST: ++ case LABEL_REF: ++ case SYMBOL_REF: ++ *total = COSTS_WIDE_INSNS (2); ++ return true; ++ ++ case CONST_DOUBLE: ++ *total = COSTS_WIDE_INSNS (4); ++ return true; ++ ++ case CONST_VECTOR: ++ if (TARGET_NEON ++ && TARGET_HARD_FLOAT ++ && outer_code == SET ++ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) ++ && neon_immediate_valid_for_move (x, mode, NULL, NULL)) ++ *total = COSTS_WIDE_INSNS (1); ++ else ++ *total = COSTS_WIDE_INSNS (4); ++ return true; ++ ++ case HIGH: ++ case LO_SUM: ++ /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the ++ cost of these slightly. */ ++ *total = COSTS_WIDE_INSNS (1) + 1; ++ return true; ++ ++ default: ++ if (mode != VOIDmode) ++ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); ++ else ++ /* A guess (inherited from arm_size_rtx_costs). */ ++ *total = COSTS_WIDE_INSNS (4); ++ return false; ++ } ++ ++ return true; ++#undef THUMB2_LIBCALL_COST ++#undef COSTS_WIDE_INSNS ++#undef COSTS_NARROW_INSNS ++} ++ + /* RTX costs when optimizing for size. */ + static bool + arm_rtx_costs (rtx x, int code, int outer_code, int *total, + bool speed) + { + if (!speed) +- return arm_size_rtx_costs (x, (enum rtx_code) code, +- (enum rtx_code) outer_code, total); ++ { ++ if (TARGET_THUMB2) ++ return thumb2_size_rtx_costs (x, (enum rtx_code) code, ++ (enum rtx_code) outer_code, total); ++ else ++ return arm_size_rtx_costs (x, (enum rtx_code) code, ++ (enum rtx_code) outer_code, total); ++ } + else +- return all_cores[(int)arm_tune].rtx_costs (x, (enum rtx_code) code, +- (enum rtx_code) outer_code, +- total, speed); ++ return current_tune->rtx_costs (x, (enum rtx_code) code, ++ (enum rtx_code) outer_code, ++ total, speed); + } + + /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not +@@ -7290,7 +7943,8 @@ + so it can be ignored. */ + + static bool +-arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, int *total, bool speed) ++arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ++ int *total, bool speed) + { + enum machine_mode mode = GET_MODE (x); + +@@ -7491,15 +8145,13 @@ + return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x); + } + +-static int +-arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) ++/* Adjust cost hook for XScale. */ ++static bool ++xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) + { +- rtx i_pat, d_pat; +- + /* Some true dependencies can have a higher cost depending + on precisely how certain input operands are used. */ +- if (arm_tune_xscale +- && REG_NOTE_KIND (link) == 0 ++ if (REG_NOTE_KIND (link) == 0 + && recog_memoized (insn) >= 0 + && recog_memoized (dep) >= 0) + { +@@ -7533,10 +8185,106 @@ + + if (reg_overlap_mentioned_p (recog_data.operand[opno], + shifted_operand)) +- return 2; ++ { ++ *cost = 2; ++ return false; ++ } + } + } + } ++ return true; ++} ++ ++/* Adjust cost hook for Cortex A9. */ ++static bool ++cortex_a9_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) ++{ ++ switch (REG_NOTE_KIND (link)) ++ { ++ case REG_DEP_ANTI: ++ *cost = 0; ++ return false; ++ ++ case REG_DEP_TRUE: ++ case REG_DEP_OUTPUT: ++ if (recog_memoized (insn) >= 0 ++ && recog_memoized (dep) >= 0) ++ { ++ if (GET_CODE (PATTERN (insn)) == SET) ++ { ++ if (GET_MODE_CLASS ++ (GET_MODE (SET_DEST (PATTERN (insn)))) == MODE_FLOAT ++ || GET_MODE_CLASS ++ (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT) ++ { ++ enum attr_type attr_type_insn = get_attr_type (insn); ++ enum attr_type attr_type_dep = get_attr_type (dep); ++ ++ /* By default all dependencies of the form ++ s0 = s0 s1 ++ s0 = s0 s2 ++ have an extra latency of 1 cycle because ++ of the input and output dependency in this ++ case. However this gets modeled as an true ++ dependency and hence all these checks. */ ++ if (REG_P (SET_DEST (PATTERN (insn))) ++ && REG_P (SET_DEST (PATTERN (dep))) ++ && reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)), ++ SET_DEST (PATTERN (dep)))) ++ { ++ /* FMACS is a special case where the dependant ++ instruction can be issued 3 cycles before ++ the normal latency in case of an output ++ dependency. */ ++ if ((attr_type_insn == TYPE_FMACS ++ || attr_type_insn == TYPE_FMACD) ++ && (attr_type_dep == TYPE_FMACS ++ || attr_type_dep == TYPE_FMACD)) ++ { ++ if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) ++ *cost = insn_default_latency (dep) - 3; ++ else ++ *cost = insn_default_latency (dep); ++ return false; ++ } ++ else ++ { ++ if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) ++ *cost = insn_default_latency (dep) + 1; ++ else ++ *cost = insn_default_latency (dep); ++ } ++ return false; ++ } ++ } ++ } ++ } ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ return true; ++} ++ ++/* This function implements the target macro TARGET_SCHED_ADJUST_COST. ++ It corrects the value of COST based on the relationship between ++ INSN and DEP through the dependence LINK. It returns the new ++ value. There is a per-core adjust_cost hook to adjust scheduler costs ++ and the per-core hook can choose to completely override the generic ++ adjust_cost function. Only put bits of code into arm_adjust_cost that ++ are common across all cores. */ ++static int ++arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) ++{ ++ rtx i_pat, d_pat; ++ ++ if (current_tune->sched_adjust_cost != NULL) ++ { ++ if (!current_tune->sched_adjust_cost (insn, link, dep, &cost)) ++ return cost; ++ } + + /* XXX This is not strictly true for the FPA. */ + if (REG_NOTE_KIND (link) == REG_DEP_ANTI +@@ -7559,7 +8307,8 @@ + constant pool are cached, and that others will miss. This is a + hack. */ + +- if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem)) ++ if ((GET_CODE (src_mem) == SYMBOL_REF ++ && CONSTANT_POOL_ADDRESS_P (src_mem)) + || reg_mentioned_p (stack_pointer_rtx, src_mem) + || reg_mentioned_p (frame_pointer_rtx, src_mem) + || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) +@@ -7774,11 +8523,14 @@ + vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd + eeeeeeee ffffffff gggggggg hhhhhhhh + vmov f32 18 aBbbbbbc defgh000 00000000 00000000 ++ vmov f32 19 00000000 00000000 00000000 00000000 + + For case 18, B = !b. Representable values are exactly those accepted by + vfp3_const_double_index, but are output as floating-point numbers rather + than indices. + ++ For case 19, we will change it to vmov.i32 when assembling. ++ + Variants 0-5 (inclusive) may also be used as immediates for the second + operand of VORR/VBIC instructions. + +@@ -7821,7 +8573,7 @@ + rtx el0 = CONST_VECTOR_ELT (op, 0); + REAL_VALUE_TYPE r0; + +- if (!vfp3_const_double_rtx (el0)) ++ if (!vfp3_const_double_rtx (el0) && el0 != CONST0_RTX (GET_MODE (el0))) + return -1; + + REAL_VALUE_FROM_CONST_DOUBLE (r0, el0); +@@ -7843,7 +8595,10 @@ + if (elementwidth) + *elementwidth = 0; + +- return 18; ++ if (el0 == CONST0_RTX (GET_MODE (el0))) ++ return 19; ++ else ++ return 18; + } + + /* Splat vector constant out into a byte vector. */ +@@ -8110,8 +8865,7 @@ + load. */ + + x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0)); +- return gen_rtx_UNSPEC (mode, gen_rtvec (1, x), +- UNSPEC_VDUP_N); ++ return gen_rtx_VEC_DUPLICATE (mode, x); + } + + /* Generate code to load VALS, which is a PARALLEL containing only +@@ -8207,8 +8961,7 @@ + { + x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0)); + emit_insn (gen_rtx_SET (VOIDmode, target, +- gen_rtx_UNSPEC (mode, gen_rtvec (1, x), +- UNSPEC_VDUP_N))); ++ gen_rtx_VEC_DUPLICATE (mode, x))); + return; + } + +@@ -8217,7 +8970,7 @@ + if (n_var == 1) + { + rtx copy = copy_rtx (vals); +- rtvec ops; ++ rtx index = GEN_INT (one_var); + + /* Load constant part of vector, substitute neighboring value for + varying element. */ +@@ -8226,9 +8979,38 @@ + + /* Insert variable. */ + x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var)); +- ops = gen_rtvec (3, x, target, GEN_INT (one_var)); +- emit_insn (gen_rtx_SET (VOIDmode, target, +- gen_rtx_UNSPEC (mode, ops, UNSPEC_VSET_LANE))); ++ switch (mode) ++ { ++ case V8QImode: ++ emit_insn (gen_neon_vset_lanev8qi (target, x, target, index)); ++ break; ++ case V16QImode: ++ emit_insn (gen_neon_vset_lanev16qi (target, x, target, index)); ++ break; ++ case V4HImode: ++ emit_insn (gen_neon_vset_lanev4hi (target, x, target, index)); ++ break; ++ case V8HImode: ++ emit_insn (gen_neon_vset_lanev8hi (target, x, target, index)); ++ break; ++ case V2SImode: ++ emit_insn (gen_neon_vset_lanev2si (target, x, target, index)); ++ break; ++ case V4SImode: ++ emit_insn (gen_neon_vset_lanev4si (target, x, target, index)); ++ break; ++ case V2SFmode: ++ emit_insn (gen_neon_vset_lanev2sf (target, x, target, index)); ++ break; ++ case V4SFmode: ++ emit_insn (gen_neon_vset_lanev4sf (target, x, target, index)); ++ break; ++ case V2DImode: ++ emit_insn (gen_neon_vset_lanev2di (target, x, target, index)); ++ break; ++ default: ++ gcc_unreachable (); ++ } + return; + } + +@@ -8436,7 +9218,8 @@ + return arm_address_register_rtx_p (ind, 0); + + /* Allow post-increment with Neon registers. */ +- if (type != 1 && (GET_CODE (ind) == POST_INC || GET_CODE (ind) == PRE_DEC)) ++ if ((type != 1 && GET_CODE (ind) == POST_INC) ++ || (type == 0 && GET_CODE (ind) == PRE_DEC)) + return arm_address_register_rtx_p (XEXP (ind, 0), 0); + + /* FIXME: vld1 allows register post-modify. */ +@@ -8520,11 +9303,14 @@ + return GENERAL_REGS; + } + ++ /* The neon move patterns handle all legitimate vector and struct ++ addresses. */ + if (TARGET_NEON ++ && MEM_P (x) + && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT +- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) +- && neon_vector_mem_operand (x, 0)) +- return NO_REGS; ++ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT ++ || VALID_NEON_STRUCT_MODE (mode))) ++ return NO_REGS; + + if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) + return NO_REGS; +@@ -8903,21 +9689,155 @@ + return 0; + } + +-int +-load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, +- HOST_WIDE_INT *load_offset) ++ ++/* Return true iff it would be profitable to turn a sequence of NOPS loads ++ or stores (depending on IS_STORE) into a load-multiple or store-multiple ++ instruction. ADD_OFFSET is nonzero if the base address register needs ++ to be modified with an add instruction before we can use it. */ ++ ++static bool ++multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED, ++ int nops, HOST_WIDE_INT add_offset) ++ { ++ /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm ++ if the offset isn't small enough. The reason 2 ldrs are faster ++ is because these ARMs are able to do more than one cache access ++ in a single cycle. The ARM9 and StrongARM have Harvard caches, ++ whilst the ARM8 has a double bandwidth cache. This means that ++ these cores can do both an instruction fetch and a data fetch in ++ a single cycle, so the trick of calculating the address into a ++ scratch register (one of the result regs) and then doing a load ++ multiple actually becomes slower (and no smaller in code size). ++ That is the transformation ++ ++ ldr rd1, [rbase + offset] ++ ldr rd2, [rbase + offset + 4] ++ ++ to ++ ++ add rd1, rbase, offset ++ ldmia rd1, {rd1, rd2} ++ ++ produces worse code -- '3 cycles + any stalls on rd2' instead of ++ '2 cycles + any stalls on rd2'. On ARMs with only one cache ++ access per cycle, the first sequence could never complete in less ++ than 6 cycles, whereas the ldm sequence would only take 5 and ++ would make better use of sequential accesses if not hitting the ++ cache. ++ ++ We cheat here and test 'arm_ld_sched' which we currently know to ++ only be true for the ARM8, ARM9 and StrongARM. If this ever ++ changes, then the test below needs to be reworked. */ ++ if (nops == 2 && arm_ld_sched && add_offset != 0) ++ return false; ++ ++ /* XScale has load-store double instructions, but they have stricter ++ alignment requirements than load-store multiple, so we cannot ++ use them. ++ ++ For XScale ldm requires 2 + NREGS cycles to complete and blocks ++ the pipeline until completion. ++ ++ NREGS CYCLES ++ 1 3 ++ 2 4 ++ 3 5 ++ 4 6 ++ ++ An ldr instruction takes 1-3 cycles, but does not block the ++ pipeline. ++ ++ NREGS CYCLES ++ 1 1-3 ++ 2 2-6 ++ 3 3-9 ++ 4 4-12 ++ ++ Best case ldr will always win. However, the more ldr instructions ++ we issue, the less likely we are to be able to schedule them well. ++ Using ldr instructions also increases code size. ++ ++ As a compromise, we use ldr for counts of 1 or 2 regs, and ldm ++ for counts of 3 or 4 regs. */ ++ if (nops <= 2 && arm_tune_xscale && !optimize_size) ++ return false; ++ return true; ++} ++ ++/* Subroutine of load_multiple_sequence and store_multiple_sequence. ++ Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute ++ an array ORDER which describes the sequence to use when accessing the ++ offsets that produces an ascending order. In this sequence, each ++ offset must be larger by exactly 4 than the previous one. ORDER[0] ++ must have been filled in with the lowest offset by the caller. ++ If UNSORTED_REGS is nonnull, it is an array of register numbers that ++ we use to verify that ORDER produces an ascending order of registers. ++ Return true if it was possible to construct such an order, false if ++ not. */ ++ ++static bool ++compute_offset_order (int nops, HOST_WIDE_INT *unsorted_offsets, int *order, ++ int *unsorted_regs) + { +- int unsorted_regs[4]; +- HOST_WIDE_INT unsorted_offsets[4]; +- int order[4]; +- int base_reg = -1; + int i; ++ for (i = 1; i < nops; i++) ++ { ++ int j; + +- /* Can only handle 2, 3, or 4 insns at present, +- though could be easily extended if required. */ +- gcc_assert (nops >= 2 && nops <= 4); ++ order[i] = order[i - 1]; ++ for (j = 0; j < nops; j++) ++ if (unsorted_offsets[j] == unsorted_offsets[order[i - 1]] + 4) ++ { ++ /* We must find exactly one offset that is higher than the ++ previous one by 4. */ ++ if (order[i] != order[i - 1]) ++ return false; ++ order[i] = j; ++ } ++ if (order[i] == order[i - 1]) ++ return false; ++ /* The register numbers must be ascending. */ ++ if (unsorted_regs != NULL ++ && unsorted_regs[order[i]] <= unsorted_regs[order[i - 1]]) ++ return false; ++ } ++ return true; ++} ++ ++/* Used to determine in a peephole whether a sequence of load ++ instructions can be changed into a load-multiple instruction. ++ NOPS is the number of separate load instructions we are examining. The ++ first NOPS entries in OPERANDS are the destination registers, the ++ next NOPS entries are memory operands. If this function is ++ successful, *BASE is set to the common base register of the memory ++ accesses; *LOAD_OFFSET is set to the first memory location's offset ++ from that base register. ++ REGS is an array filled in with the destination register numbers. ++ SAVED_ORDER (if nonnull), is an array filled in with an order that maps ++ insn numbers to to an ascending order of stores. If CHECK_REGS is true, ++ the sequence of registers in REGS matches the loads from ascending memory ++ locations, and the function verifies that the register numbers are ++ themselves ascending. If CHECK_REGS is false, the register numbers ++ are stored in the order they are found in the operands. */ ++static int ++load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, ++ int *base, HOST_WIDE_INT *load_offset, bool check_regs) ++{ ++ int unsorted_regs[MAX_LDM_STM_OPS]; ++ HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS]; ++ int order[MAX_LDM_STM_OPS]; ++ rtx base_reg_rtx = NULL; ++ int base_reg = -1; ++ int i, ldm_case; + +- memset (order, 0, 4 * sizeof (int)); ++ if (low_irq_latency) ++ return 0; ++ ++ /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be ++ easily extended if required. */ ++ gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS); ++ ++ memset (order, 0, MAX_LDM_STM_OPS * sizeof (int)); + + /* Loop over the operands and check that the memory references are + suitable (i.e. immediate offsets from the same base register). At +@@ -8955,32 +9875,30 @@ + if (i == 0) + { + base_reg = REGNO (reg); +- unsorted_regs[0] = (GET_CODE (operands[i]) == REG +- ? REGNO (operands[i]) +- : REGNO (SUBREG_REG (operands[i]))); +- order[0] = 0; +- } +- else +- { +- if (base_reg != (int) REGNO (reg)) +- /* Not addressed from the same base register. */ ++ base_reg_rtx = reg; ++ if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM) + return 0; +- +- unsorted_regs[i] = (GET_CODE (operands[i]) == REG +- ? REGNO (operands[i]) +- : REGNO (SUBREG_REG (operands[i]))); +- if (unsorted_regs[i] < unsorted_regs[order[0]]) +- order[0] = i; + } ++ else if (base_reg != (int) REGNO (reg)) ++ /* Not addressed from the same base register. */ ++ return 0; ++ ++ unsorted_regs[i] = (GET_CODE (operands[i]) == REG ++ ? REGNO (operands[i]) ++ : REGNO (SUBREG_REG (operands[i]))); + + /* If it isn't an integer register, or if it overwrites the + base register but isn't the last insn in the list, then + we can't do this. */ +- if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 ++ if (unsorted_regs[i] < 0 ++ || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) ++ || unsorted_regs[i] > 14 + || (i != nops - 1 && unsorted_regs[i] == base_reg)) + return 0; + + unsorted_offsets[i] = INTVAL (offset); ++ if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) ++ order[0] = i; + } + else + /* Not a suitable memory address. */ +@@ -8989,164 +9907,90 @@ + + /* All the useful information has now been extracted from the + operands into unsorted_regs and unsorted_offsets; additionally, +- order[0] has been set to the lowest numbered register in the +- list. Sort the registers into order, and check that the memory +- offsets are ascending and adjacent. */ +- +- for (i = 1; i < nops; i++) +- { +- int j; +- +- order[i] = order[i - 1]; +- for (j = 0; j < nops; j++) +- if (unsorted_regs[j] > unsorted_regs[order[i - 1]] +- && (order[i] == order[i - 1] +- || unsorted_regs[j] < unsorted_regs[order[i]])) +- order[i] = j; +- +- /* Have we found a suitable register? if not, one must be used more +- than once. */ +- if (order[i] == order[i - 1]) +- return 0; ++ order[0] has been set to the lowest offset in the list. Sort ++ the offsets into order, verifying that they are adjacent, and ++ check that the register numbers are ascending. */ ++ if (!compute_offset_order (nops, unsorted_offsets, order, ++ check_regs ? unsorted_regs : NULL)) ++ return 0; + +- /* Is the memory address adjacent and ascending? */ +- if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) +- return 0; +- } ++ if (saved_order) ++ memcpy (saved_order, order, sizeof order); + + if (base) + { + *base = base_reg; + + for (i = 0; i < nops; i++) +- regs[i] = unsorted_regs[order[i]]; ++ regs[i] = unsorted_regs[check_regs ? order[i] : i]; + + *load_offset = unsorted_offsets[order[0]]; + } + +- if (unsorted_offsets[order[0]] == 0) +- return 1; /* ldmia */ +- +- if (TARGET_ARM && unsorted_offsets[order[0]] == 4) +- return 2; /* ldmib */ +- +- if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) +- return 3; /* ldmda */ +- +- if (unsorted_offsets[order[nops - 1]] == -4) +- return 4; /* ldmdb */ +- +- /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm +- if the offset isn't small enough. The reason 2 ldrs are faster +- is because these ARMs are able to do more than one cache access +- in a single cycle. The ARM9 and StrongARM have Harvard caches, +- whilst the ARM8 has a double bandwidth cache. This means that +- these cores can do both an instruction fetch and a data fetch in +- a single cycle, so the trick of calculating the address into a +- scratch register (one of the result regs) and then doing a load +- multiple actually becomes slower (and no smaller in code size). +- That is the transformation +- +- ldr rd1, [rbase + offset] +- ldr rd2, [rbase + offset + 4] +- +- to +- +- add rd1, rbase, offset +- ldmia rd1, {rd1, rd2} +- +- produces worse code -- '3 cycles + any stalls on rd2' instead of +- '2 cycles + any stalls on rd2'. On ARMs with only one cache +- access per cycle, the first sequence could never complete in less +- than 6 cycles, whereas the ldm sequence would only take 5 and +- would make better use of sequential accesses if not hitting the +- cache. +- +- We cheat here and test 'arm_ld_sched' which we currently know to +- only be true for the ARM8, ARM9 and StrongARM. If this ever +- changes, then the test below needs to be reworked. */ +- if (nops == 2 && arm_ld_sched) ++ if (TARGET_THUMB1 ++ && !peep2_reg_dead_p (nops, base_reg_rtx)) + return 0; + +- /* Can't do it without setting up the offset, only do this if it takes +- no more than one insn. */ +- return (const_ok_for_arm (unsorted_offsets[order[0]]) +- || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; +-} +- +-const char * +-emit_ldm_seq (rtx *operands, int nops) +-{ +- int regs[4]; +- int base_reg; +- HOST_WIDE_INT offset; +- char buf[100]; +- int i; +- +- switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) +- { +- case 1: +- strcpy (buf, "ldm%(ia%)\t"); +- break; +- +- case 2: +- strcpy (buf, "ldm%(ib%)\t"); +- break; +- +- case 3: +- strcpy (buf, "ldm%(da%)\t"); +- break; +- +- case 4: +- strcpy (buf, "ldm%(db%)\t"); +- break; +- +- case 5: +- if (offset >= 0) +- sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, +- reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], +- (long) offset); +- else +- sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, +- reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], +- (long) -offset); +- output_asm_insn (buf, operands); +- base_reg = regs[0]; +- strcpy (buf, "ldm%(ia%)\t"); +- break; +- +- default: +- gcc_unreachable (); +- } +- +- sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, +- reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); +- +- for (i = 1; i < nops; i++) +- sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, +- reg_names[regs[i]]); ++ if (unsorted_offsets[order[0]] == 0) ++ ldm_case = 1; /* ldmia */ ++ else if (TARGET_ARM && unsorted_offsets[order[0]] == 4) ++ ldm_case = 2; /* ldmib */ ++ else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) ++ ldm_case = 3; /* ldmda */ ++ else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4) ++ ldm_case = 4; /* ldmdb */ ++ else if (const_ok_for_arm (unsorted_offsets[order[0]]) ++ || const_ok_for_arm (-unsorted_offsets[order[0]])) ++ ldm_case = 5; ++ else ++ return 0; + +- strcat (buf, "}\t%@ phole ldm"); ++ if (!multiple_operation_profitable_p (false, nops, ++ ldm_case == 5 ++ ? unsorted_offsets[order[0]] : 0)) ++ return 0; + +- output_asm_insn (buf, operands); +- return ""; ++ return ldm_case; + } + +-int +-store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, +- HOST_WIDE_INT * load_offset) +-{ +- int unsorted_regs[4]; +- HOST_WIDE_INT unsorted_offsets[4]; +- int order[4]; ++/* Used to determine in a peephole whether a sequence of store instructions can ++ be changed into a store-multiple instruction. ++ NOPS is the number of separate store instructions we are examining. ++ NOPS_TOTAL is the total number of instructions recognized by the peephole ++ pattern. ++ The first NOPS entries in OPERANDS are the source registers, the next ++ NOPS entries are memory operands. If this function is successful, *BASE is ++ set to the common base register of the memory accesses; *LOAD_OFFSET is set ++ to the first memory location's offset from that base register. REGS is an ++ array filled in with the source register numbers, REG_RTXS (if nonnull) is ++ likewise filled with the corresponding rtx's. ++ SAVED_ORDER (if nonnull), is an array filled in with an order that maps insn ++ numbers to to an ascending order of stores. ++ If CHECK_REGS is true, the sequence of registers in *REGS matches the stores ++ from ascending memory locations, and the function verifies that the register ++ numbers are themselves ascending. If CHECK_REGS is false, the register ++ numbers are stored in the order they are found in the operands. */ ++static int ++store_multiple_sequence (rtx *operands, int nops, int nops_total, ++ int *regs, rtx *reg_rtxs, int *saved_order, int *base, ++ HOST_WIDE_INT *load_offset, bool check_regs) ++{ ++ int unsorted_regs[MAX_LDM_STM_OPS]; ++ rtx unsorted_reg_rtxs[MAX_LDM_STM_OPS]; ++ HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS]; ++ int order[MAX_LDM_STM_OPS]; + int base_reg = -1; +- int i; ++ rtx base_reg_rtx = NULL; ++ int i, stm_case; ++ ++ if (low_irq_latency) ++ return 0; + +- /* Can only handle 2, 3, or 4 insns at present, though could be easily +- extended if required. */ +- gcc_assert (nops >= 2 && nops <= 4); ++ /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be ++ easily extended if required. */ ++ gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS); + +- memset (order, 0, 4 * sizeof (int)); ++ memset (order, 0, MAX_LDM_STM_OPS * sizeof (int)); + + /* Loop over the operands and check that the memory references are + suitable (i.e. immediate offsets from the same base register). At +@@ -9181,32 +10025,32 @@ + && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) + == CONST_INT))) + { ++ unsorted_reg_rtxs[i] = (GET_CODE (operands[i]) == REG ++ ? operands[i] : SUBREG_REG (operands[i])); ++ unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]); ++ + if (i == 0) + { + base_reg = REGNO (reg); +- unsorted_regs[0] = (GET_CODE (operands[i]) == REG +- ? REGNO (operands[i]) +- : REGNO (SUBREG_REG (operands[i]))); +- order[0] = 0; +- } +- else +- { +- if (base_reg != (int) REGNO (reg)) +- /* Not addressed from the same base register. */ ++ base_reg_rtx = reg; ++ if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM) + return 0; +- +- unsorted_regs[i] = (GET_CODE (operands[i]) == REG +- ? REGNO (operands[i]) +- : REGNO (SUBREG_REG (operands[i]))); +- if (unsorted_regs[i] < unsorted_regs[order[0]]) +- order[0] = i; + } ++ else if (base_reg != (int) REGNO (reg)) ++ /* Not addressed from the same base register. */ ++ return 0; + + /* If it isn't an integer register, then we can't do this. */ +- if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) ++ if (unsorted_regs[i] < 0 ++ || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) ++ || (TARGET_THUMB2 && unsorted_regs[i] == base_reg) ++ || (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM) ++ || unsorted_regs[i] > 14) + return 0; + + unsorted_offsets[i] = INTVAL (offset); ++ if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) ++ order[0] = i; + } + else + /* Not a suitable memory address. */ +@@ -9215,253 +10059,450 @@ + + /* All the useful information has now been extracted from the + operands into unsorted_regs and unsorted_offsets; additionally, +- order[0] has been set to the lowest numbered register in the +- list. Sort the registers into order, and check that the memory +- offsets are ascending and adjacent. */ +- +- for (i = 1; i < nops; i++) +- { +- int j; ++ order[0] has been set to the lowest offset in the list. Sort ++ the offsets into order, verifying that they are adjacent, and ++ check that the register numbers are ascending. */ ++ if (!compute_offset_order (nops, unsorted_offsets, order, ++ check_regs ? unsorted_regs : NULL)) ++ return 0; + +- order[i] = order[i - 1]; +- for (j = 0; j < nops; j++) +- if (unsorted_regs[j] > unsorted_regs[order[i - 1]] +- && (order[i] == order[i - 1] +- || unsorted_regs[j] < unsorted_regs[order[i]])) +- order[i] = j; +- +- /* Have we found a suitable register? if not, one must be used more +- than once. */ +- if (order[i] == order[i - 1]) +- return 0; +- +- /* Is the memory address adjacent and ascending? */ +- if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) +- return 0; +- } ++ if (saved_order) ++ memcpy (saved_order, order, sizeof order); + + if (base) + { + *base = base_reg; + + for (i = 0; i < nops; i++) +- regs[i] = unsorted_regs[order[i]]; ++ { ++ regs[i] = unsorted_regs[check_regs ? order[i] : i]; ++ if (reg_rtxs) ++ reg_rtxs[i] = unsorted_reg_rtxs[check_regs ? order[i] : i]; ++ } + + *load_offset = unsorted_offsets[order[0]]; + } + ++ if (TARGET_THUMB1 ++ && !peep2_reg_dead_p (nops_total, base_reg_rtx)) ++ return 0; ++ + if (unsorted_offsets[order[0]] == 0) +- return 1; /* stmia */ ++ stm_case = 1; /* stmia */ ++ else if (TARGET_ARM && unsorted_offsets[order[0]] == 4) ++ stm_case = 2; /* stmib */ ++ else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) ++ stm_case = 3; /* stmda */ ++ else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4) ++ stm_case = 4; /* stmdb */ ++ else ++ return 0; + +- if (unsorted_offsets[order[0]] == 4) +- return 2; /* stmib */ ++ if (!multiple_operation_profitable_p (false, nops, 0)) ++ return 0; ++ ++ return stm_case; ++} ++ ++/* Routines for use in generating RTL. */ + +- if (unsorted_offsets[order[nops - 1]] == 0) +- return 3; /* stmda */ ++/* Generate a load-multiple instruction. COUNT is the number of loads in ++ the instruction; REGS and MEMS are arrays containing the operands. ++ BASEREG is the base register to be used in addressing the memory operands. ++ WBACK_OFFSET is nonzero if the instruction should update the base ++ register. */ + +- if (unsorted_offsets[order[nops - 1]] == -4) +- return 4; /* stmdb */ ++static rtx ++arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, ++ HOST_WIDE_INT wback_offset) ++{ ++ int i = 0, j; ++ rtx result; + +- return 0; ++ if (low_irq_latency || !multiple_operation_profitable_p (false, count, 0)) ++ { ++ rtx seq; ++ ++ start_sequence (); ++ ++ for (i = 0; i < count; i++) ++ emit_move_insn (gen_rtx_REG (SImode, regs[i]), mems[i]); ++ ++ if (wback_offset != 0) ++ emit_move_insn (basereg, plus_constant (basereg, wback_offset)); ++ ++ seq = get_insns (); ++ end_sequence (); ++ ++ return seq; ++ } ++ ++ result = gen_rtx_PARALLEL (VOIDmode, ++ rtvec_alloc (count + (wback_offset != 0 ? 1 : 0))); ++ if (wback_offset != 0) ++ { ++ XVECEXP (result, 0, 0) ++ = gen_rtx_SET (VOIDmode, basereg, ++ plus_constant (basereg, wback_offset)); ++ i = 1; ++ count++; ++ } ++ ++ for (j = 0; i < count; i++, j++) ++ XVECEXP (result, 0, i) ++ = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regs[j]), mems[j]); ++ ++ return result; + } + +-const char * +-emit_stm_seq (rtx *operands, int nops) ++/* Generate a store-multiple instruction. COUNT is the number of stores in ++ the instruction; REGS and MEMS are arrays containing the operands. ++ BASEREG is the base register to be used in addressing the memory operands. ++ WBACK_OFFSET is nonzero if the instruction should update the base ++ register. */ ++ ++static rtx ++arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, ++ HOST_WIDE_INT wback_offset) + { +- int regs[4]; +- int base_reg; +- HOST_WIDE_INT offset; +- char buf[100]; +- int i; ++ int i = 0, j; ++ rtx result; + +- switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) ++ if (GET_CODE (basereg) == PLUS) ++ basereg = XEXP (basereg, 0); ++ ++ if (low_irq_latency || !multiple_operation_profitable_p (false, count, 0)) + { +- case 1: +- strcpy (buf, "stm%(ia%)\t"); +- break; ++ rtx seq; + +- case 2: +- strcpy (buf, "stm%(ib%)\t"); +- break; ++ start_sequence (); + +- case 3: +- strcpy (buf, "stm%(da%)\t"); +- break; ++ for (i = 0; i < count; i++) ++ emit_move_insn (mems[i], gen_rtx_REG (SImode, regs[i])); + +- case 4: +- strcpy (buf, "stm%(db%)\t"); +- break; ++ if (wback_offset != 0) ++ emit_move_insn (basereg, plus_constant (basereg, wback_offset)); + +- default: +- gcc_unreachable (); ++ seq = get_insns (); ++ end_sequence (); ++ ++ return seq; + } + +- sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, +- reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); ++ result = gen_rtx_PARALLEL (VOIDmode, ++ rtvec_alloc (count + (wback_offset != 0 ? 1 : 0))); ++ if (wback_offset != 0) ++ { ++ XVECEXP (result, 0, 0) ++ = gen_rtx_SET (VOIDmode, basereg, ++ plus_constant (basereg, wback_offset)); ++ i = 1; ++ count++; ++ } + +- for (i = 1; i < nops; i++) +- sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, +- reg_names[regs[i]]); ++ for (j = 0; i < count; i++, j++) ++ XVECEXP (result, 0, i) ++ = gen_rtx_SET (VOIDmode, mems[j], gen_rtx_REG (SImode, regs[j])); + +- strcat (buf, "}\t%@ phole stm"); ++ return result; ++} + +- output_asm_insn (buf, operands); +- return ""; ++/* Generate either a load-multiple or a store-multiple instruction. This ++ function can be used in situations where we can start with a single MEM ++ rtx and adjust its address upwards. ++ COUNT is the number of operations in the instruction, not counting a ++ possible update of the base register. REGS is an array containing the ++ register operands. ++ BASEREG is the base register to be used in addressing the memory operands, ++ which are constructed from BASEMEM. ++ WRITE_BACK specifies whether the generated instruction should include an ++ update of the base register. ++ OFFSETP is used to pass an offset to and from this function; this offset ++ is not used when constructing the address (instead BASEMEM should have an ++ appropriate offset in its address), it is used only for setting ++ MEM_OFFSET. It is updated only if WRITE_BACK is true.*/ ++ ++static rtx ++arm_gen_multiple_op (bool is_load, int *regs, int count, rtx basereg, ++ bool write_back, rtx basemem, HOST_WIDE_INT *offsetp) ++{ ++ rtx mems[MAX_LDM_STM_OPS]; ++ HOST_WIDE_INT offset = *offsetp; ++ int i; ++ ++ gcc_assert (count <= MAX_LDM_STM_OPS); ++ ++ if (GET_CODE (basereg) == PLUS) ++ basereg = XEXP (basereg, 0); ++ ++ for (i = 0; i < count; i++) ++ { ++ rtx addr = plus_constant (basereg, i * 4); ++ mems[i] = adjust_automodify_address_nv (basemem, SImode, addr, offset); ++ offset += 4; ++ } ++ ++ if (write_back) ++ *offsetp = offset; ++ ++ if (is_load) ++ return arm_gen_load_multiple_1 (count, regs, mems, basereg, ++ write_back ? 4 * count : 0); ++ else ++ return arm_gen_store_multiple_1 (count, regs, mems, basereg, ++ write_back ? 4 * count : 0); + } +- +-/* Routines for use in generating RTL. */ + + rtx +-arm_gen_load_multiple (int base_regno, int count, rtx from, int up, +- int write_back, rtx basemem, HOST_WIDE_INT *offsetp) ++arm_gen_load_multiple (int *regs, int count, rtx basereg, int write_back, ++ rtx basemem, HOST_WIDE_INT *offsetp) + { +- HOST_WIDE_INT offset = *offsetp; +- int i = 0, j; +- rtx result; +- int sign = up ? 1 : -1; +- rtx mem, addr; ++ return arm_gen_multiple_op (TRUE, regs, count, basereg, write_back, basemem, ++ offsetp); ++} + +- /* XScale has load-store double instructions, but they have stricter +- alignment requirements than load-store multiple, so we cannot +- use them. ++rtx ++arm_gen_store_multiple (int *regs, int count, rtx basereg, int write_back, ++ rtx basemem, HOST_WIDE_INT *offsetp) ++{ ++ return arm_gen_multiple_op (FALSE, regs, count, basereg, write_back, basemem, ++ offsetp); ++} + +- For XScale ldm requires 2 + NREGS cycles to complete and blocks +- the pipeline until completion. ++/* Called from a peephole2 expander to turn a sequence of loads into an ++ LDM instruction. OPERANDS are the operands found by the peephole matcher; ++ NOPS indicates how many separate loads we are trying to combine. SORT_REGS ++ is true if we can reorder the registers because they are used commutatively ++ subsequently. ++ Returns true iff we could generate a new instruction. */ + +- NREGS CYCLES +- 1 3 +- 2 4 +- 3 5 +- 4 6 ++bool ++gen_ldm_seq (rtx *operands, int nops, bool sort_regs) ++{ ++ int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; ++ rtx mems[MAX_LDM_STM_OPS]; ++ int i, j, base_reg; ++ rtx base_reg_rtx; ++ HOST_WIDE_INT offset; ++ int write_back = FALSE; ++ int ldm_case; ++ rtx addr; + +- An ldr instruction takes 1-3 cycles, but does not block the +- pipeline. ++ ldm_case = load_multiple_sequence (operands, nops, regs, mem_order, ++ &base_reg, &offset, !sort_regs); + +- NREGS CYCLES +- 1 1-3 +- 2 2-6 +- 3 3-9 +- 4 4-12 ++ if (ldm_case == 0) ++ return false; + +- Best case ldr will always win. However, the more ldr instructions +- we issue, the less likely we are to be able to schedule them well. +- Using ldr instructions also increases code size. ++ if (sort_regs) ++ for (i = 0; i < nops - 1; i++) ++ for (j = i + 1; j < nops; j++) ++ if (regs[i] > regs[j]) ++ { ++ int t = regs[i]; ++ regs[i] = regs[j]; ++ regs[j] = t; ++ } ++ base_reg_rtx = gen_rtx_REG (Pmode, base_reg); + +- As a compromise, we use ldr for counts of 1 or 2 regs, and ldm +- for counts of 3 or 4 regs. */ +- if (arm_tune_xscale && count <= 2 && ! optimize_size) ++ if (TARGET_THUMB1) + { +- rtx seq; +- +- start_sequence (); ++ gcc_assert (peep2_reg_dead_p (nops, base_reg_rtx)); ++ gcc_assert (ldm_case == 1 || ldm_case == 5); ++ write_back = TRUE; ++ } + +- for (i = 0; i < count; i++) ++ if (ldm_case == 5) ++ { ++ rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG (SImode, regs[0]); ++ emit_insn (gen_addsi3 (newbase, base_reg_rtx, GEN_INT (offset))); ++ offset = 0; ++ if (!TARGET_THUMB1) + { +- addr = plus_constant (from, i * 4 * sign); +- mem = adjust_automodify_address (basemem, SImode, addr, offset); +- emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); +- offset += 4 * sign; ++ base_reg = regs[0]; ++ base_reg_rtx = newbase; + } ++ } + +- if (write_back) +- { +- emit_move_insn (from, plus_constant (from, count * 4 * sign)); +- *offsetp = offset; +- } ++ for (i = 0; i < nops; i++) ++ { ++ addr = plus_constant (base_reg_rtx, offset + i * 4); ++ mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], ++ SImode, addr, 0); ++ } ++ emit_insn (arm_gen_load_multiple_1 (nops, regs, mems, base_reg_rtx, ++ write_back ? offset + i * 4 : 0)); ++ return true; ++} + +- seq = get_insns (); +- end_sequence (); ++/* Called from a peephole2 expander to turn a sequence of stores into an ++ STM instruction. OPERANDS are the operands found by the peephole matcher; ++ NOPS indicates how many separate stores we are trying to combine. ++ Returns true iff we could generate a new instruction. */ + +- return seq; +- } ++bool ++gen_stm_seq (rtx *operands, int nops) ++{ ++ int i; ++ int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; ++ rtx mems[MAX_LDM_STM_OPS]; ++ int base_reg; ++ rtx base_reg_rtx; ++ HOST_WIDE_INT offset; ++ int write_back = FALSE; ++ int stm_case; ++ rtx addr; ++ bool base_reg_dies; ++ ++ stm_case = store_multiple_sequence (operands, nops, nops, regs, NULL, ++ mem_order, &base_reg, &offset, true); ++ ++ if (stm_case == 0) ++ return false; ++ ++ base_reg_rtx = gen_rtx_REG (Pmode, base_reg); + +- result = gen_rtx_PARALLEL (VOIDmode, +- rtvec_alloc (count + (write_back ? 1 : 0))); +- if (write_back) ++ base_reg_dies = peep2_reg_dead_p (nops, base_reg_rtx); ++ if (TARGET_THUMB1) + { +- XVECEXP (result, 0, 0) +- = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign)); +- i = 1; +- count++; ++ gcc_assert (base_reg_dies); ++ write_back = TRUE; + } + +- for (j = 0; i < count; i++, j++) ++ if (stm_case == 5) + { +- addr = plus_constant (from, j * 4 * sign); +- mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); +- XVECEXP (result, 0, i) +- = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); +- offset += 4 * sign; ++ gcc_assert (base_reg_dies); ++ emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset))); ++ offset = 0; + } + +- if (write_back) +- *offsetp = offset; ++ addr = plus_constant (base_reg_rtx, offset); + +- return result; ++ for (i = 0; i < nops; i++) ++ { ++ addr = plus_constant (base_reg_rtx, offset + i * 4); ++ mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], ++ SImode, addr, 0); ++ } ++ emit_insn (arm_gen_store_multiple_1 (nops, regs, mems, base_reg_rtx, ++ write_back ? offset + i * 4 : 0)); ++ return true; + } + +-rtx +-arm_gen_store_multiple (int base_regno, int count, rtx to, int up, +- int write_back, rtx basemem, HOST_WIDE_INT *offsetp) ++/* Called from a peephole2 expander to turn a sequence of stores that are ++ preceded by constant loads into an STM instruction. OPERANDS are the ++ operands found by the peephole matcher; NOPS indicates how many ++ separate stores we are trying to combine; there are 2 * NOPS ++ instructions in the peephole. ++ Returns true iff we could generate a new instruction. */ ++ ++bool ++gen_const_stm_seq (rtx *operands, int nops) + { +- HOST_WIDE_INT offset = *offsetp; +- int i = 0, j; +- rtx result; +- int sign = up ? 1 : -1; +- rtx mem, addr; ++ int regs[MAX_LDM_STM_OPS], sorted_regs[MAX_LDM_STM_OPS]; ++ int reg_order[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; ++ rtx reg_rtxs[MAX_LDM_STM_OPS], orig_reg_rtxs[MAX_LDM_STM_OPS]; ++ rtx mems[MAX_LDM_STM_OPS]; ++ int base_reg; ++ rtx base_reg_rtx; ++ HOST_WIDE_INT offset; ++ int write_back = FALSE; ++ int stm_case; ++ rtx addr; ++ bool base_reg_dies; ++ int i, j; ++ HARD_REG_SET allocated; + +- /* See arm_gen_load_multiple for discussion of +- the pros/cons of ldm/stm usage for XScale. */ +- if (arm_tune_xscale && count <= 2 && ! optimize_size) +- { +- rtx seq; ++ stm_case = store_multiple_sequence (operands, nops, 2 * nops, regs, reg_rtxs, ++ mem_order, &base_reg, &offset, false); + +- start_sequence (); ++ if (stm_case == 0) ++ return false; + +- for (i = 0; i < count; i++) +- { +- addr = plus_constant (to, i * 4 * sign); +- mem = adjust_automodify_address (basemem, SImode, addr, offset); +- emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); +- offset += 4 * sign; +- } ++ memcpy (orig_reg_rtxs, reg_rtxs, sizeof orig_reg_rtxs); + +- if (write_back) +- { +- emit_move_insn (to, plus_constant (to, count * 4 * sign)); +- *offsetp = offset; +- } ++ /* If the same register is used more than once, try to find a free ++ register. */ ++ CLEAR_HARD_REG_SET (allocated); ++ for (i = 0; i < nops; i++) ++ { ++ for (j = i + 1; j < nops; j++) ++ if (regs[i] == regs[j]) ++ { ++ rtx t = peep2_find_free_register (0, nops * 2, ++ TARGET_THUMB1 ? "l" : "r", ++ SImode, &allocated); ++ if (t == NULL_RTX) ++ return false; ++ reg_rtxs[i] = t; ++ regs[i] = REGNO (t); ++ } ++ } + +- seq = get_insns (); +- end_sequence (); ++ /* Compute an ordering that maps the register numbers to an ascending ++ sequence. */ ++ reg_order[0] = 0; ++ for (i = 0; i < nops; i++) ++ if (regs[i] < regs[reg_order[0]]) ++ reg_order[0] = i; + +- return seq; ++ for (i = 1; i < nops; i++) ++ { ++ int this_order = reg_order[i - 1]; ++ for (j = 0; j < nops; j++) ++ if (regs[j] > regs[reg_order[i - 1]] ++ && (this_order == reg_order[i - 1] ++ || regs[j] < regs[this_order])) ++ this_order = j; ++ reg_order[i] = this_order; + } + +- result = gen_rtx_PARALLEL (VOIDmode, +- rtvec_alloc (count + (write_back ? 1 : 0))); +- if (write_back) ++ /* Ensure that registers that must be live after the instruction end ++ up with the correct value. */ ++ for (i = 0; i < nops; i++) + { +- XVECEXP (result, 0, 0) +- = gen_rtx_SET (VOIDmode, to, +- plus_constant (to, count * 4 * sign)); +- i = 1; +- count++; ++ int this_order = reg_order[i]; ++ if ((this_order != mem_order[i] ++ || orig_reg_rtxs[this_order] != reg_rtxs[this_order]) ++ && !peep2_reg_dead_p (nops * 2, orig_reg_rtxs[this_order])) ++ return false; + } + +- for (j = 0; i < count; i++, j++) ++ /* Load the constants. */ ++ for (i = 0; i < nops; i++) + { +- addr = plus_constant (to, j * 4 * sign); +- mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); +- XVECEXP (result, 0, i) +- = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); +- offset += 4 * sign; ++ rtx op = operands[2 * nops + mem_order[i]]; ++ sorted_regs[i] = regs[reg_order[i]]; ++ emit_move_insn (reg_rtxs[reg_order[i]], op); + } + +- if (write_back) +- *offsetp = offset; ++ base_reg_rtx = gen_rtx_REG (Pmode, base_reg); + +- return result; ++ base_reg_dies = peep2_reg_dead_p (nops * 2, base_reg_rtx); ++ if (TARGET_THUMB1) ++ { ++ gcc_assert (base_reg_dies); ++ write_back = TRUE; ++ } ++ ++ if (stm_case == 5) ++ { ++ gcc_assert (base_reg_dies); ++ emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset))); ++ offset = 0; ++ } ++ ++ addr = plus_constant (base_reg_rtx, offset); ++ ++ for (i = 0; i < nops; i++) ++ { ++ addr = plus_constant (base_reg_rtx, offset + i * 4); ++ mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], ++ SImode, addr, 0); ++ } ++ emit_insn (arm_gen_store_multiple_1 (nops, sorted_regs, mems, base_reg_rtx, ++ write_back ? offset + i * 4 : 0)); ++ return true; + } + + int +@@ -9497,20 +10538,21 @@ + for (i = 0; in_words_to_go >= 2; i+=4) + { + if (in_words_to_go > 4) +- emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, +- srcbase, &srcoffset)); ++ emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, src, ++ TRUE, srcbase, &srcoffset)); + else +- emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, +- FALSE, srcbase, &srcoffset)); ++ emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, in_words_to_go, ++ src, FALSE, srcbase, ++ &srcoffset)); + + if (out_words_to_go) + { + if (out_words_to_go > 4) +- emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, +- dstbase, &dstoffset)); ++ emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, dst, ++ TRUE, dstbase, &dstoffset)); + else if (out_words_to_go != 1) +- emit_insn (arm_gen_store_multiple (0, out_words_to_go, +- dst, TRUE, ++ emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, ++ out_words_to_go, dst, + (last_bytes == 0 + ? FALSE : TRUE), + dstbase, &dstoffset)); +@@ -9838,12 +10880,14 @@ + + /* Alternate canonicalizations of the above. These are somewhat cleaner. */ + if (GET_CODE (x) == AND ++ && (op == EQ || op == NE) + && COMPARISON_P (XEXP (x, 0)) + && COMPARISON_P (XEXP (x, 1))) + return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), + DOM_CC_X_AND_Y); + + if (GET_CODE (x) == IOR ++ && (op == EQ || op == NE) + && COMPARISON_P (XEXP (x, 0)) + && COMPARISON_P (XEXP (x, 1))) + return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), +@@ -9885,6 +10929,55 @@ + && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) + return CC_Cmode; + ++ if (GET_MODE (x) == DImode || GET_MODE (y) == DImode) ++ { ++ /* To keep things simple, always use the Cirrus cfcmp64 if it is ++ available. */ ++ if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ return CCmode; ++ ++ switch (op) ++ { ++ case EQ: ++ case NE: ++ /* A DImode comparison against zero can be implemented by ++ or'ing the two halves together. */ ++ if (y == const0_rtx) ++ return CC_Zmode; ++ ++ /* We can do an equality test in three Thumb instructions. */ ++ if (!TARGET_ARM) ++ return CC_Zmode; ++ ++ /* FALLTHROUGH */ ++ ++ case LTU: ++ case LEU: ++ case GTU: ++ case GEU: ++ /* DImode unsigned comparisons can be implemented by cmp + ++ cmpeq without a scratch register. Not worth doing in ++ Thumb-2. */ ++ if (TARGET_ARM) ++ return CC_CZmode; ++ ++ /* FALLTHROUGH */ ++ ++ case LT: ++ case LE: ++ case GT: ++ case GE: ++ /* DImode signed and unsigned comparisons can be implemented ++ by cmp + sbcs with a scratch register, but that does not ++ set the Z flag - we must reverse GT/LE/GTU/LEU. */ ++ gcc_assert (op != EQ && op != NE); ++ return CC_NCVmode; ++ ++ default: ++ gcc_unreachable (); ++ } ++ } ++ + return CCmode; + } + +@@ -9894,10 +10987,39 @@ + rtx + arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) + { +- enum machine_mode mode = SELECT_CC_MODE (code, x, y); +- rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); ++ enum machine_mode mode; ++ rtx cc_reg; ++ int dimode_comparison = GET_MODE (x) == DImode || GET_MODE (y) == DImode; + +- emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); ++ /* We might have X as a constant, Y as a register because of the predicates ++ used for cmpdi. If so, force X to a register here. */ ++ if (dimode_comparison && !REG_P (x)) ++ x = force_reg (DImode, x); ++ ++ mode = SELECT_CC_MODE (code, x, y); ++ cc_reg = gen_rtx_REG (mode, CC_REGNUM); ++ ++ if (dimode_comparison ++ && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ && mode != CC_CZmode) ++ { ++ rtx clobber, set; ++ ++ /* To compare two non-zero values for equality, XOR them and ++ then compare against zero. Not used for ARM mode; there ++ CC_CZmode is cheaper. */ ++ if (mode == CC_Zmode && y != const0_rtx) ++ { ++ x = expand_binop (DImode, xor_optab, x, y, NULL_RTX, 0, OPTAB_WIDEN); ++ y = const0_rtx; ++ } ++ /* A scratch register is required. */ ++ clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)); ++ set = gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)); ++ emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); ++ } ++ else ++ emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); + + return cc_reg; + } +@@ -10433,6 +11555,7 @@ + + if (GET_CODE (insn) == JUMP_INSN + && JUMP_LABEL (insn) != NULL ++ && !ANY_RETURN_P (JUMP_LABEL (insn)) + && ((table = next_real_insn (JUMP_LABEL (insn))) + == next_real_insn (insn)) + && table != NULL +@@ -11032,7 +12155,10 @@ + gcc_assert (GET_CODE (from) != BARRIER); + + /* Count the length of this insn. */ +- count += get_attr_length (from); ++ if (LABEL_P (from) && (align_jumps > 0 || align_loops > 0)) ++ count += MAX (align_jumps, align_loops); ++ else ++ count += get_attr_length (from); + + /* If there is a jump table, add its length. */ + tmp = is_jump_table (from); +@@ -11226,6 +12352,34 @@ + return false; + } + ++/* Return true if it is possible to inline both the high and low parts ++ of a 64-bit constant into 32-bit data processing instructions. */ ++bool ++arm_const_double_by_immediates (rtx val) ++{ ++ enum machine_mode mode = GET_MODE (val); ++ rtx part; ++ ++ if (mode == VOIDmode) ++ mode = DImode; ++ ++ part = gen_highpart_mode (SImode, mode, val); ++ ++ gcc_assert (GET_CODE (part) == CONST_INT); ++ ++ if (!const_ok_for_arm (INTVAL (part))) ++ return false; ++ ++ part = gen_lowpart (SImode, val); ++ ++ gcc_assert (GET_CODE (part) == CONST_INT); ++ ++ if (!const_ok_for_arm (INTVAL (part))) ++ return false; ++ ++ return true; ++} ++ + /* Scan INSN and note any of its operands that need fixing. + If DO_PUSHES is false we do not actually push any of the fixups + needed. The function returns TRUE if any fixups were needed/pushed. +@@ -11299,6 +12453,60 @@ + return result; + } + ++/* Convert instructions to their cc-clobbering variant if possible, since ++ that allows us to use smaller encodings. */ ++ ++static void ++thumb2_reorg (void) ++{ ++ basic_block bb; ++ regset_head live; ++ ++ INIT_REG_SET (&live); ++ ++ /* We are freeing block_for_insn in the toplev to keep compatibility ++ with old MDEP_REORGS that are not CFG based. Recompute it now. */ ++ compute_bb_for_insn (); ++ df_analyze (); ++ ++ FOR_EACH_BB (bb) ++ { ++ rtx insn; ++ COPY_REG_SET (&live, DF_LR_OUT (bb)); ++ df_simulate_initialize_backwards (bb, &live); ++ FOR_BB_INSNS_REVERSE (bb, insn) ++ { ++ if (NONJUMP_INSN_P (insn) ++ && !REGNO_REG_SET_P (&live, CC_REGNUM)) ++ { ++ rtx pat = PATTERN (insn); ++ if (GET_CODE (pat) == SET ++ && low_register_operand (XEXP (pat, 0), SImode) ++ && thumb_16bit_operator (XEXP (pat, 1), SImode) ++ && low_register_operand (XEXP (XEXP (pat, 1), 0), SImode) ++ && low_register_operand (XEXP (XEXP (pat, 1), 1), SImode)) ++ { ++ rtx dst = XEXP (pat, 0); ++ rtx src = XEXP (pat, 1); ++ rtx op0 = XEXP (src, 0); ++ if (rtx_equal_p (dst, op0) ++ || GET_CODE (src) == PLUS || GET_CODE (src) == MINUS) ++ { ++ rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM); ++ rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg); ++ rtvec vec = gen_rtvec (2, pat, clobber); ++ PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); ++ INSN_CODE (insn) = -1; ++ } ++ } ++ } ++ if (NONDEBUG_INSN_P (insn)) ++ df_simulate_one_insn_backwards (bb, insn, &live); ++ } ++ } ++ CLEAR_REG_SET (&live); ++} ++ + /* Gcc puts the pool in the wrong place for ARM, since we can only + load addresses a limited distance around the pc. We do some + special munging to move the constant pool values to the correct +@@ -11310,6 +12518,9 @@ + HOST_WIDE_INT address = 0; + Mfix * fix; + ++ if (TARGET_THUMB2) ++ thumb2_reorg (); ++ + minipool_fix_head = minipool_fix_tail = NULL; + + /* The first insn must always be a note, or the code below won't +@@ -11344,6 +12555,8 @@ + insn = table; + } + } ++ else if (LABEL_P (insn) && (align_jumps > 0 || align_loops > 0)) ++ address += MAX (align_jumps, align_loops); + } + + fix = minipool_fix_head; +@@ -11549,6 +12762,21 @@ + vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count) + { + int i; ++ int offset; ++ ++ if (low_irq_latency) ++ { ++ /* Output a sequence of FLDD instructions. */ ++ offset = 0; ++ for (i = reg; i < reg + count; ++i, offset += 8) ++ { ++ fputc ('\t', stream); ++ asm_fprintf (stream, "fldd\td%d, [%r,#%d]\n", i, base, offset); ++ } ++ asm_fprintf (stream, "\tadd\tsp, sp, #%d\n", count * 8); ++ return; ++ } ++ + + /* Workaround ARM10 VFPr1 bug. */ + if (count == 2 && !arm_arch6) +@@ -11619,6 +12847,56 @@ + rtx tmp, reg; + int i; + ++ if (low_irq_latency) ++ { ++ int saved_size; ++ rtx sp_insn; ++ ++ if (!count) ++ return 0; ++ ++ saved_size = count * GET_MODE_SIZE (DFmode); ++ ++ /* Since fstd does not have postdecrement addressing mode, ++ we first decrement stack pointer and then use base+offset ++ stores for VFP registers. The ARM EABI unwind information ++ can't easily describe base+offset loads, so we attach ++ a note for the effects of the whole block in the first insn, ++ and avoid marking the subsequent instructions ++ with RTX_FRAME_RELATED_P. */ ++ sp_insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, ++ GEN_INT (-saved_size)); ++ sp_insn = emit_insn (sp_insn); ++ RTX_FRAME_RELATED_P (sp_insn) = 1; ++ ++ dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); ++ XVECEXP (dwarf, 0, 0) = ++ gen_rtx_SET (VOIDmode, stack_pointer_rtx, ++ plus_constant (stack_pointer_rtx, -saved_size)); ++ ++ /* push double VFP registers to stack */ ++ for (i = 0; i < count; ++i ) ++ { ++ rtx reg; ++ rtx mem; ++ rtx addr; ++ rtx insn; ++ reg = gen_rtx_REG (DFmode, base_reg + 2*i); ++ addr = (i == 0) ? stack_pointer_rtx ++ : gen_rtx_PLUS (SImode, stack_pointer_rtx, ++ GEN_INT (i * GET_MODE_SIZE (DFmode))); ++ mem = gen_frame_mem (DFmode, addr); ++ insn = emit_move_insn (mem, reg); ++ XVECEXP (dwarf, 0, i+1) = ++ gen_rtx_SET (VOIDmode, mem, reg); ++ } ++ ++ REG_NOTES (sp_insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, ++ REG_NOTES (sp_insn)); ++ ++ return saved_size; ++ } ++ + /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two + register pairs are stored by a store multiple insn. We avoid this + by pushing an extra pair. */ +@@ -12182,13 +13460,13 @@ + { + if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) + { +- output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); +- output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); ++ output_asm_insn ("str%?\t%0, [%1, %2]!", otherops); ++ output_asm_insn ("str%?\t%H0, [%1, #4]", otherops); + } + else + { +- output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); +- output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); ++ output_asm_insn ("str%?\t%H0, [%1, #4]", otherops); ++ output_asm_insn ("str%?\t%0, [%1], %2", otherops); + } + } + else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) +@@ -12548,6 +13826,34 @@ + return 4; + } + ++/* Return nonzero if the offset in the address is an immediate. Otherwise, ++ return zero. */ ++ ++int ++arm_address_offset_is_imm (rtx insn) ++{ ++ rtx mem, addr; ++ ++ extract_insn_cached (insn); ++ ++ if (REG_P (recog_data.operand[0])) ++ return 0; ++ ++ mem = recog_data.operand[0]; ++ ++ gcc_assert (MEM_P (mem)); ++ ++ addr = XEXP (mem, 0); ++ ++ if (GET_CODE (addr) == REG ++ || (GET_CODE (addr) == PLUS ++ && GET_CODE (XEXP (addr, 0)) == REG ++ && GET_CODE (XEXP (addr, 1)) == CONST_INT)) ++ return 1; ++ else ++ return 0; ++} ++ + /* Output an ADD r, s, #n where n may be too big for one instruction. + If adding zero to one register, output nothing. */ + const char * +@@ -13111,7 +14417,7 @@ + if (count > 0) + { + /* Workaround ARM10 VFPr1 bug. */ +- if (count == 2 && !arm_arch6) ++ if (count == 2 && !arm_arch6 && !low_irq_latency) + count++; + saved += count * 8; + } +@@ -13134,7 +14440,7 @@ + /* Generate a function exit sequence. If REALLY_RETURN is false, then do + everything bar the final return instruction. */ + const char * +-output_return_instruction (rtx operand, int really_return, int reverse) ++output_return_instruction (rtx operand, bool really_return, bool reverse, bool simple) + { + char conditional[10]; + char instr[100]; +@@ -13172,10 +14478,15 @@ + + sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); + +- cfun->machine->return_used_this_function = 1; ++ if (simple) ++ live_regs_mask = 0; ++ else ++ { ++ cfun->machine->return_used_this_function = 1; + +- offsets = arm_get_frame_offsets (); +- live_regs_mask = offsets->saved_regs_mask; ++ offsets = arm_get_frame_offsets (); ++ live_regs_mask = offsets->saved_regs_mask; ++ } + + if (live_regs_mask) + { +@@ -13449,6 +14760,41 @@ + + } + ++/* Generate to STREAM a code sequence that pops registers identified ++ in REGS_MASK from SP. SP is incremented as the result. ++*/ ++static void ++print_pop_reg_by_ldr (FILE *stream, int regs_mask, int rfe) ++{ ++ int reg; ++ ++ gcc_assert (! (regs_mask & (1 << SP_REGNUM))); ++ ++ for (reg = 0; reg < PC_REGNUM; ++reg) ++ if (regs_mask & (1 << reg)) ++ asm_fprintf (stream, "\tldr\t%r, [%r], #4\n", ++ reg, SP_REGNUM); ++ ++ if (regs_mask & (1 << PC_REGNUM)) ++ { ++ if (rfe) ++ /* When returning from exception, we need to ++ copy SPSR to CPSR. There are two ways to do ++ that: the ldm instruction with "^" suffix, ++ and movs instruction. The latter would ++ require that we load from stack to some ++ scratch register, and then move to PC. ++ Therefore, we'd need extra instruction and ++ have to make sure we actually have a spare ++ register. Using ldm with a single register ++ is simler. */ ++ asm_fprintf (stream, "\tldm\tsp!, {pc}^\n"); ++ else ++ asm_fprintf (stream, "\tldr\t%r, [%r], #4\n", ++ PC_REGNUM, SP_REGNUM); ++ } ++} ++ + const char * + arm_output_epilogue (rtx sibling) + { +@@ -13823,22 +15169,19 @@ + to load use the LDR instruction - it is faster. For Thumb-2 + always use pop and the assembler will pick the best instruction.*/ + if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM) +- && !IS_INTERRUPT(func_type)) ++ && !IS_INTERRUPT (func_type)) + { + asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); + } + else if (saved_regs_mask) + { +- if (saved_regs_mask & (1 << SP_REGNUM)) +- /* Note - write back to the stack register is not enabled +- (i.e. "ldmfd sp!..."). We know that the stack pointer is +- in the list of registers and if we add writeback the +- instruction becomes UNPREDICTABLE. */ +- print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, +- rfe); +- else if (TARGET_ARM) +- print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask, +- rfe); ++ gcc_assert ( ! (saved_regs_mask & (1 << SP_REGNUM))); ++ if (TARGET_ARM) ++ if (low_irq_latency) ++ print_pop_reg_by_ldr (f, saved_regs_mask, rfe); ++ else ++ print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask, ++ rfe); + else + print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0); + } +@@ -13959,6 +15302,32 @@ + + gcc_assert (num_regs && num_regs <= 16); + ++ if (low_irq_latency) ++ { ++ rtx insn = 0; ++ ++ /* Emit a series of ldr instructions rather rather than a single ldm. */ ++ /* TODO: Use ldrd where possible. */ ++ gcc_assert (! (mask & (1 << SP_REGNUM))); ++ ++ for (i = LAST_ARM_REGNUM; i >= 0; --i) ++ { ++ if (mask & (1 << i)) ++ ++ { ++ rtx reg, where, mem; ++ ++ reg = gen_rtx_REG (SImode, i); ++ where = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); ++ mem = gen_rtx_MEM (SImode, where); ++ insn = emit_move_insn (mem, reg); ++ RTX_FRAME_RELATED_P (insn) = 1; ++ } ++ } ++ ++ return insn; ++ } ++ + /* We don't record the PC in the dwarf frame information. */ + num_dwarf_regs = num_regs; + if (mask & (1 << PC_REGNUM)) +@@ -15122,8 +16491,18 @@ + the value being loaded is big-wordian or little-wordian. The + order of the two register loads can matter however, if the address + of the memory location is actually held in one of the registers +- being overwritten by the load. */ ++ being overwritten by the load. ++ ++ The 'Q' and 'R' constraints are also available for 64-bit ++ constants. */ + case 'Q': ++ if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) ++ { ++ rtx part = gen_lowpart (SImode, x); ++ fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part)); ++ return; ++ } ++ + if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + { + output_operand_lossage ("invalid operand for code '%c'", code); +@@ -15134,6 +16513,18 @@ + return; + + case 'R': ++ if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) ++ { ++ enum machine_mode mode = GET_MODE (x); ++ rtx part; ++ ++ if (mode == VOIDmode) ++ mode = DImode; ++ part = gen_highpart_mode (SImode, mode, x); ++ fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part)); ++ return; ++ } ++ + if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + { + output_operand_lossage ("invalid operand for code '%c'", code); +@@ -15456,6 +16847,8 @@ + { + rtx addr; + bool postinc = FALSE; ++ unsigned align, modesize, align_bits; ++ + gcc_assert (GET_CODE (x) == MEM); + addr = XEXP (x, 0); + if (GET_CODE (addr) == POST_INC) +@@ -15463,12 +16856,45 @@ + postinc = 1; + addr = XEXP (addr, 0); + } +- asm_fprintf (stream, "[%r]", REGNO (addr)); ++ asm_fprintf (stream, "[%r", REGNO (addr)); ++ ++ /* We know the alignment of this access, so we can emit a hint in the ++ instruction (for some alignments) as an aid to the memory subsystem ++ of the target. */ ++ align = MEM_ALIGN (x) >> 3; ++ modesize = GET_MODE_SIZE (GET_MODE (x)); ++ ++ /* Only certain alignment specifiers are supported by the hardware. */ ++ if (modesize == 16 && (align % 32) == 0) ++ align_bits = 256; ++ else if ((modesize == 8 || modesize == 16) && (align % 16) == 0) ++ align_bits = 128; ++ else if ((align % 8) == 0) ++ align_bits = 64; ++ else ++ align_bits = 0; ++ ++ if (align_bits != 0) ++ asm_fprintf (stream, ", :%d", align_bits); ++ ++ asm_fprintf (stream, "]"); ++ + if (postinc) + fputs("!", stream); + } + return; + ++ case 'C': ++ { ++ rtx addr; ++ ++ gcc_assert (GET_CODE (x) == MEM); ++ addr = XEXP (x, 0); ++ gcc_assert (GET_CODE (addr) == REG); ++ asm_fprintf (stream, "[%r]", REGNO (addr)); ++ } ++ return; ++ + /* Translate an S register number into a D register number and element index. */ + case 'y': + { +@@ -15818,13 +17244,35 @@ + default: gcc_unreachable (); + } + +- case CC_Cmode: ++ case CC_Cmode: ++ switch (comp_code) ++ { ++ case LTU: return ARM_CS; ++ case GEU: return ARM_CC; ++ default: gcc_unreachable (); ++ } ++ ++ case CC_CZmode: ++ switch (comp_code) ++ { ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case GEU: return ARM_CS; ++ case GTU: return ARM_HI; ++ case LEU: return ARM_LS; ++ case LTU: return ARM_CC; ++ default: gcc_unreachable (); ++ } ++ ++ case CC_NCVmode: + switch (comp_code) +- { +- case LTU: return ARM_CS; +- case GEU: return ARM_CC; +- default: gcc_unreachable (); +- } ++ { ++ case GE: return ARM_GE; ++ case LT: return ARM_LT; ++ case GEU: return ARM_CS; ++ case LTU: return ARM_CC; ++ default: gcc_unreachable (); ++ } + + case CCmode: + switch (comp_code) +@@ -15937,6 +17385,7 @@ + + /* If we start with a return insn, we only succeed if we find another one. */ + int seeking_return = 0; ++ enum rtx_code return_code = UNKNOWN; + + /* START_INSN will hold the insn from where we start looking. This is the + first insn after the following code_label if REVERSE is true. */ +@@ -15975,7 +17424,7 @@ + else + return; + } +- else if (GET_CODE (body) == RETURN) ++ else if (ANY_RETURN_P (body)) + { + start_insn = next_nonnote_insn (start_insn); + if (GET_CODE (start_insn) == BARRIER) +@@ -15986,6 +17435,7 @@ + { + reverse = TRUE; + seeking_return = 1; ++ return_code = GET_CODE (body); + } + else + return; +@@ -16026,11 +17476,15 @@ + label = XEXP (XEXP (SET_SRC (body), 2), 0); + then_not_else = FALSE; + } +- else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) +- seeking_return = 1; +- else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) ++ else if (ANY_RETURN_P (XEXP (SET_SRC (body), 1))) ++ { ++ seeking_return = 1; ++ return_code = GET_CODE (XEXP (SET_SRC (body), 1)); ++ } ++ else if (ANY_RETURN_P (XEXP (SET_SRC (body), 2))) + { + seeking_return = 1; ++ return_code = GET_CODE (XEXP (SET_SRC (body), 2)); + then_not_else = FALSE; + } + else +@@ -16131,8 +17585,7 @@ + && !use_return_insn (TRUE, NULL) + && !optimize_size) + fail = TRUE; +- else if (GET_CODE (scanbody) == RETURN +- && seeking_return) ++ else if (GET_CODE (scanbody) == return_code) + { + arm_ccfsm_state = 2; + succeed = TRUE; +@@ -16299,7 +17752,7 @@ + return mode == SImode; + + if (IS_IWMMXT_REGNUM (regno)) +- return VALID_IWMMXT_REG_MODE (mode); ++ return VALID_IWMMXT_REG_MODE (mode) && mode != SImode; + } + + /* We allow almost any value to be stored in the general registers. +@@ -19027,6 +20480,81 @@ + #endif + } + ++/* Given the stack offsets and register mask in OFFSETS, decide how ++ many additional registers to push instead of subtracting a constant ++ from SP. For epilogues the principle is the same except we use pop. ++ FOR_PROLOGUE indicates which we're generating. */ ++static int ++thumb1_extra_regs_pushed (arm_stack_offsets *offsets, bool for_prologue) ++{ ++ HOST_WIDE_INT amount; ++ unsigned long live_regs_mask = offsets->saved_regs_mask; ++ /* Extract a mask of the ones we can give to the Thumb's push/pop ++ instruction. */ ++ unsigned long l_mask = live_regs_mask & (for_prologue ? 0x40ff : 0xff); ++ /* Then count how many other high registers will need to be pushed. */ ++ unsigned long high_regs_pushed = bit_count (live_regs_mask & 0x0f00); ++ int n_free, reg_base; ++ ++ if (!for_prologue && frame_pointer_needed) ++ amount = offsets->locals_base - offsets->saved_regs; ++ else ++ amount = offsets->outgoing_args - offsets->saved_regs; ++ ++ /* If the stack frame size is 512 exactly, we can save one load ++ instruction, which should make this a win even when optimizing ++ for speed. */ ++ if (!optimize_size && amount != 512) ++ return 0; ++ ++ /* Can't do this if there are high registers to push. */ ++ if (high_regs_pushed != 0) ++ return 0; ++ ++ /* Shouldn't do it in the prologue if no registers would normally ++ be pushed at all. In the epilogue, also allow it if we'll have ++ a pop insn for the PC. */ ++ if (l_mask == 0 ++ && (for_prologue ++ || TARGET_BACKTRACE ++ || (live_regs_mask & 1 << LR_REGNUM) == 0 ++ || TARGET_INTERWORK ++ || crtl->args.pretend_args_size != 0)) ++ return 0; ++ ++ /* Don't do this if thumb_expand_prologue wants to emit instructions ++ between the push and the stack frame allocation. */ ++ if (for_prologue ++ && ((flag_pic && arm_pic_register != INVALID_REGNUM) ++ || (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0))) ++ return 0; ++ ++ reg_base = 0; ++ n_free = 0; ++ if (!for_prologue) ++ { ++ reg_base = arm_size_return_regs () / UNITS_PER_WORD; ++ live_regs_mask >>= reg_base; ++ } ++ ++ while (reg_base + n_free < 8 && !(live_regs_mask & 1) ++ && (for_prologue || call_used_regs[reg_base + n_free])) ++ { ++ live_regs_mask >>= 1; ++ n_free++; ++ } ++ ++ if (n_free == 0) ++ return 0; ++ gcc_assert (amount / 4 * 4 == amount); ++ ++ if (amount >= 512 && (amount - n_free * 4) < 512) ++ return (amount - 508) / 4; ++ if (amount <= n_free * 4) ++ return amount / 4; ++ return 0; ++} ++ + /* The bits which aren't usefully expanded as rtl. */ + const char * + thumb_unexpanded_epilogue (void) +@@ -19035,6 +20563,7 @@ + int regno; + unsigned long live_regs_mask = 0; + int high_regs_pushed = 0; ++ int extra_pop; + int had_to_push_lr; + int size; + +@@ -19054,6 +20583,13 @@ + the register is used to hold a return value. */ + size = arm_size_return_regs (); + ++ extra_pop = thumb1_extra_regs_pushed (offsets, false); ++ if (extra_pop > 0) ++ { ++ unsigned long extra_mask = (1 << extra_pop) - 1; ++ live_regs_mask |= extra_mask << (size / UNITS_PER_WORD); ++ } ++ + /* The prolog may have pushed some high registers to use as + work registers. e.g. the testsuite file: + gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c +@@ -19137,7 +20673,9 @@ + live_regs_mask); + + /* We have either just popped the return address into the +- PC or it is was kept in LR for the entire function. */ ++ PC or it is was kept in LR for the entire function. ++ Note that thumb_pushpop has already called thumb_exit if the ++ PC was in the list. */ + if (!had_to_push_lr) + thumb_exit (asm_out_file, LR_REGNUM); + } +@@ -19319,6 +20857,7 @@ + stack_pointer_rtx); + + amount = offsets->outgoing_args - offsets->saved_regs; ++ amount -= 4 * thumb1_extra_regs_pushed (offsets, true); + if (amount) + { + if (amount < 512) +@@ -19403,6 +20942,7 @@ + emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); + amount = offsets->locals_base - offsets->saved_regs; + } ++ amount -= 4 * thumb1_extra_regs_pushed (offsets, false); + + gcc_assert (amount >= 0); + if (amount) +@@ -19623,7 +21163,11 @@ + register. */ + else if ((l_mask & 0xff) != 0 + || (high_regs_pushed == 0 && l_mask)) +- thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); ++ { ++ unsigned long mask = l_mask; ++ mask |= (1 << thumb1_extra_regs_pushed (offsets, true)) - 1; ++ thumb_pushpop (f, mask, 1, &cfa_offset, mask); ++ } + + if (high_regs_pushed) + { +@@ -19997,13 +21541,10 @@ + if (TARGET_BPABI) + { + const char *fpu_name; +- if (arm_select[0].string) +- asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string); +- else if (arm_select[1].string) +- asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string); ++ if (arm_selected_arch) ++ asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name); + else +- asm_fprintf (asm_out_file, "\t.cpu %s\n", +- all_cores[arm_default_cpu].name); ++ asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name); + + if (TARGET_SOFT_FLOAT) + { +@@ -20398,6 +21939,38 @@ + return !reg_overlap_mentioned_p (value, addr); + } + ++/* Return nonzero if the CONSUMER instruction (a store) does need ++ PRODUCER's value to calculate the address. */ ++ ++int ++arm_early_store_addr_dep (rtx producer, rtx consumer) ++{ ++ return !arm_no_early_store_addr_dep (producer, consumer); ++} ++ ++/* Return nonzero if the CONSUMER instruction (a load) does need ++ PRODUCER's value to calculate the address. */ ++ ++int ++arm_early_load_addr_dep (rtx producer, rtx consumer) ++{ ++ rtx value = PATTERN (producer); ++ rtx addr = PATTERN (consumer); ++ ++ if (GET_CODE (value) == COND_EXEC) ++ value = COND_EXEC_CODE (value); ++ if (GET_CODE (value) == PARALLEL) ++ value = XVECEXP (value, 0, 0); ++ value = XEXP (value, 0); ++ if (GET_CODE (addr) == COND_EXEC) ++ addr = COND_EXEC_CODE (addr); ++ if (GET_CODE (addr) == PARALLEL) ++ addr = XVECEXP (addr, 0, 0); ++ addr = XEXP (addr, 1); ++ ++ return reg_overlap_mentioned_p (value, addr); ++} ++ + /* Return nonzero if the CONSUMER instruction (an ALU op) does not + have an early register shift value or amount dependency on the + result of PRODUCER. */ +@@ -21254,6 +22827,16 @@ + fputc (')', fp); + return TRUE; + } ++ else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SYMBOL_OFFSET) ++ { ++ output_addr_const (fp, XVECEXP (x, 0, 0)); ++ if (GOT_PCREL) ++ fputs ("+.", fp); ++ fputs ("-(", fp); ++ output_addr_const (fp, XVECEXP (x, 0, 1)); ++ fputc (')', fp); ++ return TRUE; ++ } + else if (GET_CODE (x) == CONST_VECTOR) + return arm_emit_vector_const (fp, x); + +@@ -21362,6 +22945,7 @@ + { + case cortexr4: + case cortexr4f: ++ case cortexa5: + case cortexa8: + case cortexa9: + return 2; +@@ -21508,4 +23092,447 @@ + return !TARGET_THUMB1; + } + ++static bool ++arm_vector_alignment_reachable (const_tree type, bool is_packed) ++{ ++ /* Vectors which aren't in packed structures will not be less aligned than ++ the natural alignment of their element type, so this is safe. */ ++ if (TARGET_NEON && !BYTES_BIG_ENDIAN) ++ return !is_packed; ++ ++ return default_builtin_vector_alignment_reachable (type, is_packed); ++} ++ ++static bool ++arm_builtin_support_vector_misalignment (enum machine_mode mode, ++ const_tree type, int misalignment, ++ bool is_packed) ++{ ++ if (TARGET_NEON && !BYTES_BIG_ENDIAN) ++ { ++ HOST_WIDE_INT align = TYPE_ALIGN_UNIT (type); ++ ++ if (is_packed) ++ return align == 1; ++ ++ /* If the misalignment is unknown, we should be able to handle the access ++ so long as it is not to a member of a packed data structure. */ ++ if (misalignment == -1) ++ return true; ++ ++ /* Return true if the misalignment is a multiple of the natural alignment ++ of the vector's element type. This is probably always going to be ++ true in practice, since we've already established that this isn't a ++ packed access. */ ++ return ((misalignment % align) == 0); ++ } ++ ++ return default_builtin_support_vector_misalignment (mode, type, misalignment, ++ is_packed); ++} ++ ++/* Legitimize a memory reference for sync primitive implemented using ++ ldrex / strex. We currently force the form of the reference to be ++ indirect without offset. We do not yet support the indirect offset ++ addressing supported by some ARM targets for these ++ instructions. */ ++static rtx ++arm_legitimize_sync_memory (rtx memory) ++{ ++ rtx addr = force_reg (Pmode, XEXP (memory, 0)); ++ rtx legitimate_memory = gen_rtx_MEM (GET_MODE (memory), addr); ++ ++ set_mem_alias_set (legitimate_memory, ALIAS_SET_MEMORY_BARRIER); ++ MEM_VOLATILE_P (legitimate_memory) = MEM_VOLATILE_P (memory); ++ return legitimate_memory; ++} ++ ++/* An instruction emitter. */ ++typedef void (* emit_f) (int label, const char *, rtx *); ++ ++/* An instruction emitter that emits via the conventional ++ output_asm_insn. */ ++static void ++arm_emit (int label ATTRIBUTE_UNUSED, const char *pattern, rtx *operands) ++{ ++ output_asm_insn (pattern, operands); ++} ++ ++/* Count the number of emitted synchronization instructions. */ ++static unsigned arm_insn_count; ++ ++/* An emitter that counts emitted instructions but does not actually ++ emit instruction into the the instruction stream. */ ++static void ++arm_count (int label, ++ const char *pattern ATTRIBUTE_UNUSED, ++ rtx *operands ATTRIBUTE_UNUSED) ++{ ++ if (! label) ++ ++ arm_insn_count; ++} ++ ++/* Construct a pattern using conventional output formatting and feed ++ it to output_asm_insn. Provides a mechanism to construct the ++ output pattern on the fly. Note the hard limit on the pattern ++ buffer size. */ ++static void ++arm_output_asm_insn (emit_f emit, int label, rtx *operands, ++ const char *pattern, ...) ++{ ++ va_list ap; ++ char buffer[256]; ++ ++ va_start (ap, pattern); ++ vsprintf (buffer, pattern, ap); ++ va_end (ap); ++ emit (label, buffer, operands); ++} ++ ++/* Emit the memory barrier instruction, if any, provided by this ++ target to a specified emitter. */ ++static void ++arm_process_output_memory_barrier (emit_f emit, rtx *operands) ++{ ++ if (TARGET_HAVE_DMB) ++ { ++ /* Note we issue a system level barrier. We should consider ++ issuing a inner shareabilty zone barrier here instead, ie. ++ "DMB ISH". */ ++ emit (0, "dmb\tsy", operands); ++ return; ++ } ++ ++ if (TARGET_HAVE_DMB_MCR) ++ { ++ emit (0, "mcr\tp15, 0, r0, c7, c10, 5", operands); ++ return; ++ } ++ ++ gcc_unreachable (); ++} ++ ++/* Emit the memory barrier instruction, if any, provided by this ++ target. */ ++const char * ++arm_output_memory_barrier (rtx *operands) ++{ ++ arm_process_output_memory_barrier (arm_emit, operands); ++ return ""; ++} ++ ++/* Helper to figure out the instruction suffix required on ldrex/strex ++ for operations on an object of the specified mode. */ ++static const char * ++arm_ldrex_suffix (enum machine_mode mode) ++{ ++ switch (mode) ++ { ++ case QImode: return "b"; ++ case HImode: return "h"; ++ case SImode: return ""; ++ case DImode: return "d"; ++ default: ++ gcc_unreachable (); ++ } ++ return ""; ++} ++ ++/* Emit an ldrex{b,h,d, } instruction appropriate for the specified ++ mode. */ ++static void ++arm_output_ldrex (emit_f emit, ++ enum machine_mode mode, ++ rtx target, ++ rtx memory) ++{ ++ const char *suffix = arm_ldrex_suffix (mode); ++ rtx operands[2]; ++ ++ operands[0] = target; ++ operands[1] = memory; ++ arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix); ++} ++ ++/* Emit a strex{b,h,d, } instruction appropriate for the specified ++ mode. */ ++static void ++arm_output_strex (emit_f emit, ++ enum machine_mode mode, ++ const char *cc, ++ rtx result, ++ rtx value, ++ rtx memory) ++{ ++ const char *suffix = arm_ldrex_suffix (mode); ++ rtx operands[3]; ++ ++ operands[0] = result; ++ operands[1] = value; ++ operands[2] = memory; ++ arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2", suffix, ++ cc); ++} ++ ++/* Helper to emit a two operand instruction. */ ++static void ++arm_output_op2 (emit_f emit, const char *mnemonic, rtx d, rtx s) ++{ ++ rtx operands[2]; ++ ++ operands[0] = d; ++ operands[1] = s; ++ arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1", mnemonic); ++} ++ ++/* Helper to emit a three operand instruction. */ ++static void ++arm_output_op3 (emit_f emit, const char *mnemonic, rtx d, rtx a, rtx b) ++{ ++ rtx operands[3]; ++ ++ operands[0] = d; ++ operands[1] = a; ++ operands[2] = b; ++ arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1, %%2", mnemonic); ++} ++ ++/* Emit a load store exclusive synchronization loop. ++ ++ do ++ old_value = [mem] ++ if old_value != required_value ++ break; ++ t1 = sync_op (old_value, new_value) ++ [mem] = t1, t2 = [0|1] ++ while ! t2 ++ ++ Note: ++ t1 == t2 is not permitted ++ t1 == old_value is permitted ++ ++ required_value: ++ ++ RTX register or const_int representing the required old_value for ++ the modify to continue, if NULL no comparsion is performed. */ ++static void ++arm_output_sync_loop (emit_f emit, ++ enum machine_mode mode, ++ rtx old_value, ++ rtx memory, ++ rtx required_value, ++ rtx new_value, ++ rtx t1, ++ rtx t2, ++ enum attr_sync_op sync_op, ++ int early_barrier_required) ++{ ++ rtx operands[1]; ++ ++ gcc_assert (t1 != t2); ++ ++ if (early_barrier_required) ++ arm_process_output_memory_barrier (emit, NULL); ++ ++ arm_output_asm_insn (emit, 1, operands, "%sLSYT%%=:", LOCAL_LABEL_PREFIX); ++ ++ arm_output_ldrex (emit, mode, old_value, memory); ++ ++ if (required_value) ++ { ++ rtx operands[2]; ++ ++ operands[0] = old_value; ++ operands[1] = required_value; ++ arm_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1"); ++ arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX); ++ } ++ ++ switch (sync_op) ++ { ++ case SYNC_OP_ADD: ++ arm_output_op3 (emit, "add", t1, old_value, new_value); ++ break; ++ ++ case SYNC_OP_SUB: ++ arm_output_op3 (emit, "sub", t1, old_value, new_value); ++ break; ++ ++ case SYNC_OP_IOR: ++ arm_output_op3 (emit, "orr", t1, old_value, new_value); ++ break; ++ ++ case SYNC_OP_XOR: ++ arm_output_op3 (emit, "eor", t1, old_value, new_value); ++ break; ++ ++ case SYNC_OP_AND: ++ arm_output_op3 (emit,"and", t1, old_value, new_value); ++ break; ++ ++ case SYNC_OP_NAND: ++ arm_output_op3 (emit, "and", t1, old_value, new_value); ++ arm_output_op2 (emit, "mvn", t1, t1); ++ break; ++ ++ case SYNC_OP_NONE: ++ t1 = new_value; ++ break; ++ } ++ ++ if (t2) ++ { ++ arm_output_strex (emit, mode, "", t2, t1, memory); ++ operands[0] = t2; ++ arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0"); ++ arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", ++ LOCAL_LABEL_PREFIX); ++ } ++ else ++ { ++ /* Use old_value for the return value because for some operations ++ the old_value can easily be restored. This saves one register. */ ++ arm_output_strex (emit, mode, "", old_value, t1, memory); ++ operands[0] = old_value; ++ arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0"); ++ arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", ++ LOCAL_LABEL_PREFIX); ++ ++ switch (sync_op) ++ { ++ case SYNC_OP_ADD: ++ arm_output_op3 (emit, "sub", old_value, t1, new_value); ++ break; ++ ++ case SYNC_OP_SUB: ++ arm_output_op3 (emit, "add", old_value, t1, new_value); ++ break; ++ ++ case SYNC_OP_XOR: ++ arm_output_op3 (emit, "eor", old_value, t1, new_value); ++ break; ++ ++ case SYNC_OP_NONE: ++ arm_output_op2 (emit, "mov", old_value, required_value); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ } ++ ++ arm_process_output_memory_barrier (emit, NULL); ++ arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX); ++} ++ ++static rtx ++arm_get_sync_operand (rtx *operands, int index, rtx default_value) ++{ ++ if (index > 0) ++ default_value = operands[index - 1]; ++ ++ return default_value; ++} ++ ++#define FETCH_SYNC_OPERAND(NAME, DEFAULT) \ ++ arm_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), DEFAULT); ++ ++/* Extract the operands for a synchroniztion instruction from the ++ instructions attributes and emit the instruction. */ ++static void ++arm_process_output_sync_insn (emit_f emit, rtx insn, rtx *operands) ++{ ++ rtx result, memory, required_value, new_value, t1, t2; ++ int early_barrier; ++ enum machine_mode mode; ++ enum attr_sync_op sync_op; ++ ++ result = FETCH_SYNC_OPERAND(result, 0); ++ memory = FETCH_SYNC_OPERAND(memory, 0); ++ required_value = FETCH_SYNC_OPERAND(required_value, 0); ++ new_value = FETCH_SYNC_OPERAND(new_value, 0); ++ t1 = FETCH_SYNC_OPERAND(t1, 0); ++ t2 = FETCH_SYNC_OPERAND(t2, 0); ++ early_barrier = ++ get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES; ++ sync_op = get_attr_sync_op (insn); ++ mode = GET_MODE (memory); ++ ++ arm_output_sync_loop (emit, mode, result, memory, required_value, ++ new_value, t1, t2, sync_op, early_barrier); ++} ++ ++/* Emit a synchronization instruction loop. */ ++const char * ++arm_output_sync_insn (rtx insn, rtx *operands) ++{ ++ arm_process_output_sync_insn (arm_emit, insn, operands); ++ return ""; ++} ++ ++/* Count the number of machine instruction that will be emitted for a ++ synchronization instruction. Note that the emitter used does not ++ emit instructions, it just counts instructions being carefull not ++ to count labels. */ ++unsigned int ++arm_sync_loop_insns (rtx insn, rtx *operands) ++{ ++ arm_insn_count = 0; ++ arm_process_output_sync_insn (arm_count, insn, operands); ++ return arm_insn_count; ++} ++ ++/* Helper to call a target sync instruction generator, dealing with ++ the variation in operands required by the different generators. */ ++static rtx ++arm_call_generator (struct arm_sync_generator *generator, rtx old_value, ++ rtx memory, rtx required_value, rtx new_value) ++{ ++ switch (generator->op) ++ { ++ case arm_sync_generator_omn: ++ gcc_assert (! required_value); ++ return generator->u.omn (old_value, memory, new_value); ++ ++ case arm_sync_generator_omrn: ++ gcc_assert (required_value); ++ return generator->u.omrn (old_value, memory, required_value, new_value); ++ } ++ ++ return NULL; ++} ++ ++/* Expand a synchronization loop. The synchronization loop is expanded ++ as an opaque block of instructions in order to ensure that we do ++ not subsequently get extraneous memory accesses inserted within the ++ critical region. The exclusive access property of ldrex/strex is ++ only guaranteed in there are no intervening memory accesses. */ ++void ++arm_expand_sync (enum machine_mode mode, ++ struct arm_sync_generator *generator, ++ rtx target, rtx memory, rtx required_value, rtx new_value) ++{ ++ if (target == NULL) ++ target = gen_reg_rtx (mode); ++ ++ memory = arm_legitimize_sync_memory (memory); ++ if (mode != SImode) ++ { ++ rtx load_temp = gen_reg_rtx (SImode); ++ ++ if (required_value) ++ required_value = convert_modes (SImode, mode, required_value, true); ++ ++ new_value = convert_modes (SImode, mode, new_value, true); ++ emit_insn (arm_call_generator (generator, load_temp, memory, ++ required_value, new_value)); ++ emit_move_insn (target, gen_lowpart (mode, load_temp)); ++ } ++ else ++ { ++ emit_insn (arm_call_generator (generator, target, memory, required_value, ++ new_value)); ++ } ++} ++ + #include "gt-arm.h" +--- a/src/gcc/config/arm/arm.h ++++ b/src/gcc/config/arm/arm.h +@@ -94,7 +94,15 @@ + if (arm_arch_iwmmxt) \ + builtin_define ("__IWMMXT__"); \ + if (TARGET_AAPCS_BASED) \ +- builtin_define ("__ARM_EABI__"); \ ++ { \ ++ if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ ++ builtin_define ("__ARM_PCS_VFP"); \ ++ else if (arm_pcs_default == ARM_PCS_AAPCS) \ ++ builtin_define ("__ARM_PCS"); \ ++ builtin_define ("__ARM_EABI__"); \ ++ } \ ++ if (low_irq_latency) \ ++ builtin_define ("__low_irq_latency__"); \ + } while (0) + + /* The various ARM cores. */ +@@ -120,6 +128,24 @@ + /* The processor for which instructions should be scheduled. */ + extern enum processor_type arm_tune; + ++enum arm_sync_generator_tag ++ { ++ arm_sync_generator_omn, ++ arm_sync_generator_omrn ++ }; ++ ++/* Wrapper to pass around a polymorphic pointer to a sync instruction ++ generator and. */ ++struct arm_sync_generator ++{ ++ enum arm_sync_generator_tag op; ++ union ++ { ++ rtx (* omn) (rtx, rtx, rtx); ++ rtx (* omrn) (rtx, rtx, rtx, rtx); ++ } u; ++}; ++ + typedef enum arm_cond_code + { + ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, +@@ -264,6 +290,20 @@ + for Thumb-2. */ + #define TARGET_UNIFIED_ASM TARGET_THUMB2 + ++/* Nonzero if this chip provides the DMB instruction. */ ++#define TARGET_HAVE_DMB (arm_arch7) ++ ++/* Nonzero if this chip implements a memory barrier via CP15. */ ++#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB) ++ ++/* Nonzero if this chip implements a memory barrier instruction. */ ++#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) ++ ++/* Nonzero if this chip supports ldrex and strex */ ++#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) ++ ++/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */ ++#define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7) + + /* True iff the full BPABI is being used. If TARGET_BPABI is true, + then TARGET_AAPCS_BASED must be true -- but the converse does not +@@ -397,6 +437,12 @@ + /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ + extern int arm_arch6; + ++/* Nonzero if this chip supports the ARM Architecture 6k extensions. */ ++extern int arm_arch6k; ++ ++/* Nonzero if this chip supports the ARM Architecture 7 extensions. */ ++extern int arm_arch7; ++ + /* Nonzero if instructions not present in the 'M' profile can be used. */ + extern int arm_arch_notm; + +@@ -427,6 +473,9 @@ + /* Nonzero if tuning for stores via the write buffer. */ + extern int arm_tune_wbuf; + ++/* Nonzero if tuning for Cortex-A5. */ ++extern int arm_tune_cortex_a5; ++ + /* Nonzero if tuning for Cortex-A9. */ + extern int arm_tune_cortex_a9; + +@@ -443,6 +492,10 @@ + /* Nonzero if chip supports integer division instruction. */ + extern int arm_arch_hwdiv; + ++/* Nonzero if we should minimize interrupt latency of the ++ generated code. */ ++extern int low_irq_latency; ++ + #ifndef TARGET_DEFAULT + #define TARGET_DEFAULT (MASK_APCS_FRAME) + #endif +@@ -581,15 +634,21 @@ + /* Align definitions of arrays, unions and structures so that + initializations and copies can be made more efficient. This is not + ABI-changing, so it only affects places where we can see the +- definition. */ +-#define DATA_ALIGNMENT(EXP, ALIGN) \ +- ((((ALIGN) < BITS_PER_WORD) \ ++ definition. Increasing the alignment tends to introduce padding, ++ so don't do this when optimizing for size/conserving stack space. */ ++#define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ ++ (((COND) && ((ALIGN) < BITS_PER_WORD) \ + && (TREE_CODE (EXP) == ARRAY_TYPE \ + || TREE_CODE (EXP) == UNION_TYPE \ + || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) + ++/* Align global data. */ ++#define DATA_ALIGNMENT(EXP, ALIGN) \ ++ ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) ++ + /* Similarly, make sure that objects on the stack are sensibly aligned. */ +-#define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) ++#define LOCAL_ALIGNMENT(EXP, ALIGN) \ ++ ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) + + /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the + value set in previous versions of this toolchain was 8, which produces more +@@ -771,12 +830,11 @@ + fixed_regs[regno] = call_used_regs[regno] = 1; \ + } \ + \ +- if (TARGET_THUMB && optimize_size) \ +- { \ +- /* When optimizing for size, it's better not to use \ +- the HI regs, because of the overhead of stacking \ +- them. */ \ +- /* ??? Is this still true for thumb2? */ \ ++ if (TARGET_THUMB1 && optimize_size) \ ++ { \ ++ /* When optimizing for size on Thumb-1, it's better not \ ++ to use the HI regs, because of the overhead of \ ++ stacking them. */ \ + for (regno = FIRST_HI_REGNUM; \ + regno <= LAST_HI_REGNUM; ++regno) \ + fixed_regs[regno] = call_used_regs[regno] = 1; \ +@@ -918,9 +976,6 @@ + #define MUST_USE_SJLJ_EXCEPTIONS 1 + #endif + +-/* We can generate DWARF2 Unwind info, even though we don't use it. */ +-#define DWARF2_UNWIND_INFO 1 +- + /* Use r0 and r1 to pass exception handling information. */ + #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) + +@@ -1071,7 +1126,7 @@ + (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) + + #define VALID_IWMMXT_REG_MODE(MODE) \ +- (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) ++ (arm_vector_mode_supported_p (MODE) || (MODE) == DImode || (MODE) == SImode) + + /* Modes valid for Neon D registers. */ + #define VALID_NEON_DREG_MODE(MODE) \ +@@ -1088,6 +1143,9 @@ + ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ + || (MODE) == CImode || (MODE) == XImode) + ++/* The register numbers in sequence, for passing to arm_gen_load_multiple. */ ++extern int arm_regs_in_sequence[]; ++ + /* The order in which register should be allocated. It is good to use ip + since no saving is required (though calls clobber it) and it never contains + function parameters. It is quite good to use lr since other calls may +@@ -1122,7 +1180,11 @@ + } + + /* Use different register alloc ordering for Thumb. */ +-#define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () ++ ++/* Tell IRA to use the order we define rather than messing it up with its ++ own cost calculations. */ ++#define HONOR_REG_ALLOC_ORDER + + /* Interrupt functions can only use registers that have already been + saved by the prologue, even if they would normally be +@@ -1203,8 +1265,8 @@ + { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ + { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \ +- { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ +- { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ ++ { 0x0000DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ ++ { 0x0000FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ + { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ + } + +@@ -1242,11 +1304,14 @@ + || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ + : 0) + +-/* We need to define this for LO_REGS on thumb. Otherwise we can end up +- using r0-r4 for function arguments, r7 for the stack frame and don't +- have enough left over to do doubleword arithmetic. */ ++/* We need to define this for LO_REGS on Thumb-1. Otherwise we can end up ++ using r0-r4 for function arguments, r7 for the stack frame and don't have ++ enough left over to do doubleword arithmetic. For Thumb-2 all the ++ potentially problematic instructions accept high registers so this is not ++ necessary. Care needs to be taken to avoid adding new Thumb-2 patterns ++ that require many low registers. */ + #define CLASS_LIKELY_SPILLED_P(CLASS) \ +- ((TARGET_THUMB && (CLASS) == LO_REGS) \ ++ ((TARGET_THUMB1 && (CLASS) == LO_REGS) \ + || (CLASS) == CC_REG) + + /* The class value for index registers, and the one for base regs. */ +@@ -1257,7 +1322,7 @@ + when addressing quantities in QI or HI mode; if we don't know the + mode, then we must be conservative. */ + #define MODE_BASE_REG_CLASS(MODE) \ +- (TARGET_32BIT ? CORE_REGS : \ ++ (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \ + (((MODE) == SImode) ? BASE_REGS : LO_REGS)) + + /* For Thumb we can not support SP+reg addressing, so we return LO_REGS +@@ -1358,6 +1423,9 @@ + else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \ + /* Need to be careful, -256 is not a valid offset. */ \ + low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ ++ else if (TARGET_REALLY_IWMMXT && MODE == SImode) \ ++ /* Need to be careful, -1024 is not a valid offset. */ \ ++ low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ + else if (MODE == SImode \ + || (MODE == SFmode && TARGET_SOFT_FLOAT) \ + || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ +@@ -1648,6 +1716,9 @@ + ARM_PCS_UNKNOWN + }; + ++/* Default procedure calling standard of current compilation unit. */ ++extern enum arm_pcs arm_pcs_default; ++ + /* A C type for declaring a variable that is used as the first argument of + `FUNCTION_ARG' and other related values. */ + typedef struct +@@ -1810,10 +1881,8 @@ + + /* Determine if the epilogue should be output as RTL. + You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ +-/* This is disabled for Thumb-2 because it will confuse the +- conditional insn counter. */ + #define USE_RETURN_INSN(ISCOND) \ +- (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0) ++ ((TARGET_32BIT && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0) + + /* Definitions for register eliminations. + +@@ -2201,7 +2270,9 @@ + /* Try to generate sequences that don't involve branches, we can then use + conditional instructions */ + #define BRANCH_COST(speed_p, predictable_p) \ +- (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0)) ++ (TARGET_32BIT ? ((arm_tune_cortex_a5 && !optimize_size) ? 0 \ ++ : (TARGET_THUMB2 && optimize_size ? 1 : 4)) \ ++ : (optimize > 0 ? 2 : 0)) + + /* Position Independent Code. */ + /* We decide which register to use based on the compilation options and +@@ -2253,19 +2324,7 @@ + : reverse_condition (code)) + + #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ +- do \ +- { \ +- if (GET_CODE (OP1) == CONST_INT \ +- && ! (const_ok_for_arm (INTVAL (OP1)) \ +- || (const_ok_for_arm (- INTVAL (OP1))))) \ +- { \ +- rtx const_op = OP1; \ +- CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \ +- &const_op); \ +- OP1 = const_op; \ +- } \ +- } \ +- while (0) ++ (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1)) + + /* The arm5 clz instruction returns 32. */ + #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) +@@ -2566,6 +2625,8 @@ + #define RETURN_ADDR_RTX(COUNT, FRAME) \ + arm_return_addr (COUNT, FRAME) + ++#define RETURN_ADDR_REGNUM LR_REGNUM ++ + /* Mask of the bits in the PC that contain the real return address + when running in 26-bit mode. */ + #define RETURN_ADDR_MASK26 (0x03fffffc) +@@ -2765,4 +2826,8 @@ + #define NEED_INDICATE_EXEC_STACK 0 + #endif + ++/* The maximum number of parallel loads or stores we support in an ldm/stm ++ instruction. */ ++#define MAX_LDM_STM_OPS 4 ++ + #endif /* ! GCC_ARM_H */ +--- a/src/gcc/config/arm/arm.md ++++ b/src/gcc/config/arm/arm.md +@@ -101,6 +101,9 @@ + ; a given symbolic address. + (UNSPEC_THUMB1_CASESI 25) ; A Thumb1 compressed dispatch-table call. + (UNSPEC_RBIT 26) ; rbit operation. ++ (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from ++ ; another symbolic address. ++ (UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier. + ] + ) + +@@ -133,8 +136,15 @@ + (VUNSPEC_WCMP_EQ 12) ; Used by the iWMMXt WCMPEQ instructions + (VUNSPEC_WCMP_GTU 13) ; Used by the iWMMXt WCMPGTU instructions + (VUNSPEC_WCMP_GT 14) ; Used by the iwMMXT WCMPGT instructions ++ (VUNSPEC_ALIGN16 15) ; Used to force 16-byte alignment. ++ (VUNSPEC_ALIGN32 16) ; Used to force 32-byte alignment. + (VUNSPEC_EH_RETURN 20); Use to override the return address for exception + ; handling. ++ (VUNSPEC_SYNC_COMPARE_AND_SWAP 21) ; Represent an atomic compare swap. ++ (VUNSPEC_SYNC_LOCK 22) ; Represent a sync_lock_test_and_set. ++ (VUNSPEC_SYNC_OP 23) ; Represent a sync_ ++ (VUNSPEC_SYNC_NEW_OP 24) ; Represent a sync_new_ ++ (VUNSPEC_SYNC_OLD_OP 25) ; Represent a sync_old_ + ] + ) + +@@ -146,12 +156,8 @@ + ; patterns that share the same RTL in both ARM and Thumb code. + (define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code"))) + +-; IS_STRONGARM is set to 'yes' when compiling for StrongARM, it affects +-; scheduling decisions for the load unit and the multiplier. +-(define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_tune_strongarm"))) +- +-; IS_XSCALE is set to 'yes' when compiling for XScale. +-(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale"))) ++; IS_ARCH6 is set to 'yes' when we are generating code form ARMv6. ++(define_attr "is_arch6" "no,yes" (const (symbol_ref "arm_arch6"))) + + ;; Operand number of an input operand that is shifted. Zero if the + ;; given instruction does not shift one of its input operands. +@@ -163,8 +169,21 @@ + (define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp" + (const (symbol_ref "arm_fpu_attr"))) + ++(define_attr "sync_result" "none,0,1,2,3,4,5" (const_string "none")) ++(define_attr "sync_memory" "none,0,1,2,3,4,5" (const_string "none")) ++(define_attr "sync_required_value" "none,0,1,2,3,4,5" (const_string "none")) ++(define_attr "sync_new_value" "none,0,1,2,3,4,5" (const_string "none")) ++(define_attr "sync_t1" "none,0,1,2,3,4,5" (const_string "none")) ++(define_attr "sync_t2" "none,0,1,2,3,4,5" (const_string "none")) ++(define_attr "sync_release_barrier" "yes,no" (const_string "yes")) ++(define_attr "sync_op" "none,add,sub,ior,xor,and,nand" ++ (const_string "none")) ++ + ; LENGTH of an instruction (in bytes) +-(define_attr "length" "" (const_int 4)) ++(define_attr "length" "" ++ (cond [(not (eq_attr "sync_memory" "none")) ++ (symbol_ref "arm_sync_loop_insns (insn, operands) * 4") ++ ] (const_int 4))) + + ; POOL_RANGE is how far away from a constant pool entry that this insn + ; can be placed. If the distance is zero, then this insn will never +@@ -253,8 +272,6 @@ + (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched"))) + + ;; Classification of NEON instructions for scheduling purposes. +-;; Do not set this attribute and the "type" attribute together in +-;; any one instruction pattern. + (define_attr "neon_type" + "neon_int_1,\ + neon_int_2,\ +@@ -335,10 +352,11 @@ + ; CLOB means that the condition codes are altered in an undefined manner, if + ; they are altered at all + ; +-; UNCONDITIONAL means the instions can not be conditionally executed. ++; UNCONDITIONAL means the instruction can not be conditionally executed and ++; that the instruction does not use or alter the condition codes. + ; +-; NOCOND means that the condition codes are neither altered nor affect the +-; output of this insn ++; NOCOND means that the instruction does not use or alter the condition ++; codes but can be converted into a conditionally exectuted instruction. + + (define_attr "conds" "use,set,clob,unconditional,nocond" + (if_then_else (eq_attr "type" "call") +@@ -416,29 +434,46 @@ + ;; True if the generic scheduling description should be used. + + (define_attr "generic_sched" "yes,no" +- (const (if_then_else +- (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9") +- (eq_attr "tune_cortexr4" "yes")) ++ (const (if_then_else ++ (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4") ++ (eq_attr "tune_cortexr4" "yes")) + (const_string "no") + (const_string "yes")))) + + (define_attr "generic_vfp" "yes,no" + (const (if_then_else + (and (eq_attr "fpu" "vfp") +- (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9") ++ (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9,cortexm4") + (eq_attr "tune_cortexr4" "no")) + (const_string "yes") + (const_string "no")))) + ++; Specifies which machine an alternative is tuned for. Used to compute ++; attribute ENABLED. ++(define_attr "alt_tune" "all,onlya8,nota8" (const_string "all")) ++ ++(define_attr "enabled" "" ++ (cond [(and (eq_attr "alt_tune" "onlya8") ++ (not (eq_attr "tune" "cortexa8"))) ++ (const_int 0) ++ ++ (and (eq_attr "alt_tune" "nota8") ++ (eq_attr "tune" "cortexa8")) ++ (const_int 0)] ++ (const_int 1))) ++ + (include "arm-generic.md") + (include "arm926ejs.md") + (include "arm1020e.md") + (include "arm1026ejs.md") + (include "arm1136jfs.md") ++(include "cortex-a5.md") + (include "cortex-a8.md") + (include "cortex-a9.md") + (include "cortex-r4.md") + (include "cortex-r4f.md") ++(include "cortex-m4.md") ++(include "cortex-m4-fpu.md") + (include "vfp11.md") + + +@@ -497,15 +532,16 @@ + (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") + (match_operand:DI 2 "s_register_operand" "r, 0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON" + "#" +- "TARGET_32BIT && reload_completed" ++ "TARGET_32BIT && reload_completed ++ && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))" + [(parallel [(set (reg:CC_C CC_REGNUM) + (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) + (match_dup 1))) + (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) +- (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (plus:SI (match_dup 4) (match_dup 5))))] ++ (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + " + { + operands[3] = gen_highpart (SImode, operands[0]); +@@ -532,10 +568,10 @@ + (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) + (match_dup 1))) + (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) +- (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (plus:SI (ashiftrt:SI (match_dup 2) ++ (set (match_dup 3) (plus:SI (plus:SI (ashiftrt:SI (match_dup 2) + (const_int 31)) +- (match_dup 4))))] ++ (match_dup 4)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + " + { + operands[3] = gen_highpart (SImode, operands[0]); +@@ -561,8 +597,8 @@ + (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) + (match_dup 1))) + (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) +- (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (plus:SI (match_dup 4) (const_int 0))))] ++ (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (const_int 0)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + " + { + operands[3] = gen_highpart (SImode, operands[0]); +@@ -698,7 +734,6 @@ + "" + ) + +-;; ??? Make Thumb-2 variants which prefer low regs + (define_insn "*addsi3_compare0" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV +@@ -707,7 +742,7 @@ + (const_int 0))) + (set (match_operand:SI 0 "s_register_operand" "=r,r") + (plus:SI (match_dup 1) (match_dup 2)))] +- "TARGET_32BIT" ++ "TARGET_ARM" + "@ + add%.\\t%0, %1, %2 + sub%.\\t%0, %1, #%n2" +@@ -720,7 +755,7 @@ + (plus:SI (match_operand:SI 0 "s_register_operand" "r, r") + (match_operand:SI 1 "arm_add_operand" "rI,L")) + (const_int 0)))] +- "TARGET_32BIT" ++ "TARGET_ARM" + "@ + cmn%?\\t%0, %1 + cmp%?\\t%0, #%n1" +@@ -851,60 +886,47 @@ + [(set_attr "conds" "set")] + ) + +-(define_insn "*addsi3_carryin" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (plus:SI (match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_rhs_operand" "rI"))))] +- "TARGET_32BIT" +- "adc%?\\t%0, %1, %2" +- [(set_attr "conds" "use")] +-) ++(define_code_iterator LTUGEU [ltu geu]) ++(define_code_attr cnb [(ltu "CC_C") (geu "CC")]) ++(define_code_attr optab [(ltu "ltu") (geu "geu")]) + +-(define_insn "*addsi3_carryin_shift" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (plus:SI +- (match_operator:SI 2 "shift_operator" +- [(match_operand:SI 3 "s_register_operand" "r") +- (match_operand:SI 4 "reg_or_int_operand" "rM")]) +- (match_operand:SI 1 "s_register_operand" "r"))))] +- "TARGET_32BIT" +- "adc%?\\t%0, %1, %3%S2" +- [(set_attr "conds" "use") +- (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] +-) ++;; Assembler mnemonics for signedness of widening operations. ++(define_code_attr US [(sign_extend "s") (zero_extend "u")]) + +-(define_insn "*addsi3_carryin_alt1" ++(define_insn "*addsi3_carryin_" + [(set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") ++ (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r") + (match_operand:SI 2 "arm_rhs_operand" "rI")) +- (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] + "TARGET_32BIT" + "adc%?\\t%0, %1, %2" + [(set_attr "conds" "use")] + ) + +-(define_insn "*addsi3_carryin_alt2" ++(define_insn "*addsi3_carryin_alt2_" + [(set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (match_operand:SI 1 "s_register_operand" "r")) ++ (plus:SI (plus:SI (LTUGEU:SI (reg: CC_REGNUM) (const_int 0)) ++ (match_operand:SI 1 "s_register_operand" "%r")) + (match_operand:SI 2 "arm_rhs_operand" "rI")))] + "TARGET_32BIT" + "adc%?\\t%0, %1, %2" + [(set_attr "conds" "use")] + ) + +-(define_insn "*addsi3_carryin_alt3" ++(define_insn "*addsi3_carryin_shift_" + [(set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) +- (match_operand:SI 2 "arm_rhs_operand" "rI")) +- (match_operand:SI 1 "s_register_operand" "r")))] ++ (plus:SI (plus:SI ++ (match_operator:SI 2 "shift_operator" ++ [(match_operand:SI 3 "s_register_operand" "r") ++ (match_operand:SI 4 "reg_or_int_operand" "rM")]) ++ (match_operand:SI 1 "s_register_operand" "r")) ++ (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] + "TARGET_32BIT" +- "adc%?\\t%0, %1, %2" +- [(set_attr "conds" "use")] ++ "adc%?\\t%0, %1, %3%S2" ++ [(set_attr "conds" "use") ++ (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") ++ (const_string "alu_shift") ++ (const_string "alu_shift_reg")))] + ) + + (define_expand "incscc" +@@ -997,7 +1019,7 @@ + (minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0") + (match_operand:DI 2 "s_register_operand" "r,0,0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_32BIT" ++ "TARGET_32BIT && !TARGET_NEON" + "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2" + [(set_attr "conds" "clob") + (set_attr "length" "8")] +@@ -1106,24 +1128,27 @@ + + ; ??? Check Thumb-2 split length + (define_insn_and_split "*arm_subsi3_insn" +- [(set (match_operand:SI 0 "s_register_operand" "=r,rk,r") +- (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,!k,?n") +- (match_operand:SI 2 "s_register_operand" "r, r, r")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r,rk,r,r") ++ (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,!k,?n,r") ++ (match_operand:SI 2 "reg_or_int_operand" "r,rI, r, r,?n")))] + "TARGET_32BIT" + "@ + rsb%?\\t%0, %2, %1 + sub%?\\t%0, %1, %2 ++ sub%?\\t%0, %1, %2 ++ # + #" +- "TARGET_32BIT +- && GET_CODE (operands[1]) == CONST_INT +- && !const_ok_for_arm (INTVAL (operands[1]))" ++ "&& ((GET_CODE (operands[1]) == CONST_INT ++ && !const_ok_for_arm (INTVAL (operands[1]))) ++ || (GET_CODE (operands[2]) == CONST_INT ++ && !const_ok_for_arm (INTVAL (operands[2]))))" + [(clobber (const_int 0))] + " + arm_split_constant (MINUS, SImode, curr_insn, + INTVAL (operands[1]), operands[0], operands[2], 0); + DONE; + " +- [(set_attr "length" "4,4,16") ++ [(set_attr "length" "4,4,4,16,16") + (set_attr "predicable" "yes")] + ) + +@@ -1155,6 +1180,19 @@ + [(set_attr "conds" "set")] + ) + ++(define_insn "*subsi3_compare" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,I") ++ (match_operand:SI 2 "arm_rhs_operand" "rI,r"))) ++ (set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (minus:SI (match_dup 1) (match_dup 2)))] ++ "TARGET_32BIT" ++ "@ ++ sub%.\\t%0, %1, %2 ++ rsb%.\\t%0, %2, %1" ++ [(set_attr "conds" "set")] ++) ++ + (define_expand "decscc" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") +@@ -1352,6 +1390,49 @@ + (set_attr "predicable" "yes")] + ) + ++; The combiner cannot combine the first and last insns in the ++; following sequence because of the intervening insn, so help the ++; combiner with this splitter. The combiner does attempt to split ++; this particular combination but does not know this exact split. ++; Note that the combiner puts the constant at the outermost operation ++; as a part of canonicalization. ++; ++; mul r3, r2, r1 ++; r3, r3, ++; add r3, r3, r4 ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operator:SI 1 "plusminus_operator" ++ [(plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "") ++ (match_operand:SI 3 "s_register_operand" "")) ++ (match_operand:SI 4 "s_register_operand" "")) ++ (match_operand:SI 5 "arm_immediate_operand" "")]))] ++ "TARGET_32BIT" ++ [(set (match_dup 0) ++ (plus:SI (mult:SI (match_dup 2) (match_dup 3)) ++ (match_dup 4))) ++ (set (match_dup 0) ++ (match_op_dup:SI 1 [(match_dup 0) (match_dup 5)]))] ++ "") ++ ++; Likewise for MLS. MLS is available only on select architectures. ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operator:SI 1 "plusminus_operator" ++ [(minus:SI (match_operand:SI 2 "s_register_operand" "") ++ (mult:SI (match_operand:SI 3 "s_register_operand" "") ++ (match_operand:SI 4 "s_register_operand" ""))) ++ (match_operand:SI 5 "arm_immediate_operand" "")]))] ++ "TARGET_32BIT && arm_arch_thumb2" ++ [(set (match_dup 0) ++ (minus:SI (match_dup 2) ++ (mult:SI (match_dup 3) (match_dup 4)))) ++ (set (match_dup 0) ++ (match_op_dup:SI 1 [(match_dup 0) (match_dup 5)]))] ++ "") ++ + (define_insn "*mulsi3addsi_compare0" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV +@@ -1428,7 +1509,15 @@ + (set_attr "predicable" "yes")] + ) + +-;; Unnamed template to match long long multiply-accumulate (smlal) ++(define_expand "maddsidi4" ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (plus:DI ++ (mult:DI ++ (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")) ++ (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))) ++ (match_operand:DI 3 "s_register_operand" "")))] ++ "TARGET_32BIT && arm_arch3m" ++ "") + + (define_insn "*mulsidi3adddi" + [(set (match_operand:DI 0 "s_register_operand" "=&r") +@@ -1524,7 +1613,15 @@ + (set_attr "predicable" "yes")] + ) + +-;; Unnamed template to match long long unsigned multiply-accumulate (umlal) ++(define_expand "umaddsidi4" ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (plus:DI ++ (mult:DI ++ (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")) ++ (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))) ++ (match_operand:DI 3 "s_register_operand" "")))] ++ "TARGET_32BIT && arm_arch3m" ++ "") + + (define_insn "*umulsidi3adddi" + [(set (match_operand:DI 0 "s_register_operand" "=&r") +@@ -1692,29 +1789,29 @@ + (set_attr "predicable" "yes")] + ) + +-(define_insn "*mulhisi3addsi" ++(define_insn "maddhisi4" + [(set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (match_operand:SI 1 "s_register_operand" "r") +- (mult:SI (sign_extend:SI +- (match_operand:HI 2 "s_register_operand" "%r")) ++ (plus:SI (mult:SI (sign_extend:SI ++ (match_operand:HI 1 "s_register_operand" "r")) + (sign_extend:SI +- (match_operand:HI 3 "s_register_operand" "r")))))] ++ (match_operand:HI 2 "s_register_operand" "r"))) ++ (match_operand:SI 3 "s_register_operand" "r")))] + "TARGET_DSP_MULTIPLY" +- "smlabb%?\\t%0, %2, %3, %1" ++ "smlabb%?\\t%0, %1, %2, %3" + [(set_attr "insn" "smlaxy") + (set_attr "predicable" "yes")] + ) + +-(define_insn "*mulhidi3adddi" ++(define_insn "*maddhidi4" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (plus:DI +- (match_operand:DI 1 "s_register_operand" "0") + (mult:DI (sign_extend:DI +- (match_operand:HI 2 "s_register_operand" "%r")) ++ (match_operand:HI 1 "s_register_operand" "r")) + (sign_extend:DI +- (match_operand:HI 3 "s_register_operand" "r")))))] ++ (match_operand:HI 2 "s_register_operand" "r"))) ++ (match_operand:DI 3 "s_register_operand" "0")))] + "TARGET_DSP_MULTIPLY" +- "smlalbb%?\\t%Q0, %R0, %2, %3" ++ "smlalbb%?\\t%Q0, %R0, %1, %2" + [(set_attr "insn" "smlalxy") + (set_attr "predicable" "yes")]) + +@@ -1784,6 +1881,7 @@ + [(match_operand:DI 1 "s_register_operand" "") + (match_operand:DI 2 "s_register_operand" "")]))] + "TARGET_32BIT && reload_completed ++ && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0]))) + && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" + [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)])) + (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))] +@@ -1857,11 +1955,19 @@ + }" + ) + +-(define_insn "anddi3" ++(define_expand "anddi3" ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (and:DI (match_operand:DI 1 "s_register_operand" "") ++ (match_operand:DI 2 "neon_inv_logic_op2" "")))] ++ "TARGET_32BIT" ++ "" ++) ++ ++(define_insn "*anddi3_insn" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") + (and:DI (match_operand:DI 1 "s_register_operand" "%0,r") + (match_operand:DI 2 "s_register_operand" "r,r")))] +- "TARGET_32BIT && ! TARGET_IWMMXT" ++ "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" + "#" + [(set_attr "length" "8")] + ) +@@ -2461,7 +2567,9 @@ + (match_operand:DI 2 "s_register_operand" "r,0")))] + "TARGET_32BIT" + "#" +- "TARGET_32BIT && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" ++ "TARGET_32BIT && reload_completed ++ && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0]))) ++ && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" + [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2))) + (set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))] + " +@@ -2585,11 +2693,19 @@ + [(set_attr "conds" "set")] + ) + +-(define_insn "iordi3" ++(define_expand "iordi3" ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (ior:DI (match_operand:DI 1 "s_register_operand" "") ++ (match_operand:DI 2 "neon_logic_op2" "")))] ++ "TARGET_32BIT" ++ "" ++) ++ ++(define_insn "*iordi3_insn" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") + (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r") + (match_operand:DI 2 "s_register_operand" "r,r")))] +- "TARGET_32BIT && ! TARGET_IWMMXT" ++ "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" + "#" + [(set_attr "length" "8") + (set_attr "predicable" "yes")] +@@ -2715,11 +2831,19 @@ + [(set_attr "conds" "set")] + ) + +-(define_insn "xordi3" ++(define_expand "xordi3" ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (xor:DI (match_operand:DI 1 "s_register_operand" "") ++ (match_operand:DI 2 "s_register_operand" "")))] ++ "TARGET_32BIT" ++ "" ++) ++ ++(define_insn "*xordi3_insn" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") + (xor:DI (match_operand:DI 1 "s_register_operand" "%0,r") + (match_operand:DI 2 "s_register_operand" "r,r")))] +- "TARGET_32BIT && !TARGET_IWMMXT" ++ "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" + "#" + [(set_attr "length" "8") + (set_attr "predicable" "yes")] +@@ -3189,7 +3313,7 @@ + ) + + (define_insn "arm_ashldi3_1bit" +- [(set (match_operand:DI 0 "s_register_operand" "=&r,r") ++ [(set (match_operand:DI 0 "s_register_operand" "=r,&r") + (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r") + (const_int 1))) + (clobber (reg:CC CC_REGNUM))] +@@ -3248,7 +3372,7 @@ + ) + + (define_insn "arm_ashrdi3_1bit" +- [(set (match_operand:DI 0 "s_register_operand" "=&r,r") ++ [(set (match_operand:DI 0 "s_register_operand" "=r,&r") + (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") + (const_int 1))) + (clobber (reg:CC CC_REGNUM))] +@@ -3304,7 +3428,7 @@ + ) + + (define_insn "arm_lshrdi3_1bit" +- [(set (match_operand:DI 0 "s_register_operand" "=&r,r") ++ [(set (match_operand:DI 0 "s_register_operand" "=r,&r") + (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") + (const_int 1))) + (clobber (reg:CC CC_REGNUM))] +@@ -3970,93 +4094,46 @@ + ) + + (define_expand "zero_extendhisi2" +- [(set (match_dup 2) +- (ashift:SI (match_operand:HI 1 "nonimmediate_operand" "") +- (const_int 16))) +- (set (match_operand:SI 0 "s_register_operand" "") +- (lshiftrt:SI (match_dup 2) (const_int 16)))] ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] + "TARGET_EITHER" +- " +- { +- if ((TARGET_THUMB1 || arm_arch4) && GET_CODE (operands[1]) == MEM) +- { +- emit_insn (gen_rtx_SET (VOIDmode, operands[0], +- gen_rtx_ZERO_EXTEND (SImode, operands[1]))); +- DONE; +- } +- +- if (TARGET_ARM && GET_CODE (operands[1]) == MEM) +- { +- emit_insn (gen_movhi_bytes (operands[0], operands[1])); +- DONE; +- } +- +- if (!s_register_operand (operands[1], HImode)) +- operands[1] = copy_to_mode_reg (HImode, operands[1]); +- +- if (arm_arch6) +- { +- emit_insn (gen_rtx_SET (VOIDmode, operands[0], +- gen_rtx_ZERO_EXTEND (SImode, operands[1]))); +- DONE; +- } +- +- operands[1] = gen_lowpart (SImode, operands[1]); +- operands[2] = gen_reg_rtx (SImode); +- }" +-) +- +-(define_insn "*thumb1_zero_extendhisi2" +- [(set (match_operand:SI 0 "register_operand" "=l") +- (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] +- "TARGET_THUMB1 && !arm_arch6" +- "* +- rtx mem = XEXP (operands[1], 0); +- +- if (GET_CODE (mem) == CONST) +- mem = XEXP (mem, 0); +- +- if (GET_CODE (mem) == LABEL_REF) +- return \"ldr\\t%0, %1\"; +- +- if (GET_CODE (mem) == PLUS) ++{ ++ if (TARGET_ARM && !arm_arch4 && MEM_P (operands[1])) + { +- rtx a = XEXP (mem, 0); +- rtx b = XEXP (mem, 1); +- +- /* This can happen due to bugs in reload. */ +- if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM) +- { +- rtx ops[2]; +- ops[0] = operands[0]; +- ops[1] = a; +- +- output_asm_insn (\"mov %0, %1\", ops); +- +- XEXP (mem, 0) = operands[0]; +- } +- +- else if ( GET_CODE (a) == LABEL_REF +- && GET_CODE (b) == CONST_INT) +- return \"ldr\\t%0, %1\"; ++ emit_insn (gen_movhi_bytes (operands[0], operands[1])); ++ DONE; + } +- +- return \"ldrh\\t%0, %1\"; +- " +- [(set_attr "length" "4") +- (set_attr "type" "load_byte") +- (set_attr "pool_range" "60")] +-) ++ if (!arm_arch6 && !MEM_P (operands[1])) ++ { ++ rtx t = gen_lowpart (SImode, operands[1]); ++ rtx tmp = gen_reg_rtx (SImode); ++ emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16))); ++ emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (16))); ++ DONE; ++ } ++}) ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (zero_extend:SI (match_operand:HI 1 "s_register_operand" "")))] ++ "!TARGET_THUMB2 && !arm_arch6" ++ [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) ++ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))] ++{ ++ operands[2] = gen_lowpart (SImode, operands[1]); ++}) + +-(define_insn "*thumb1_zero_extendhisi2_v6" ++(define_insn "*thumb1_zero_extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=l,l") + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))] +- "TARGET_THUMB1 && arm_arch6" ++ "TARGET_THUMB1" + "* + rtx mem; + +- if (which_alternative == 0) ++ if (which_alternative == 0 && arm_arch6) + return \"uxth\\t%0, %1\"; ++ if (which_alternative == 0) ++ return \"#\"; + + mem = XEXP (operands[1], 0); + +@@ -4090,20 +4167,25 @@ + + return \"ldrh\\t%0, %1\"; + " +- [(set_attr "length" "2,4") ++ [(set_attr_alternative "length" ++ [(if_then_else (eq_attr "is_arch6" "yes") ++ (const_int 2) (const_int 4)) ++ (const_int 4)]) + (set_attr "type" "alu_shift,load_byte") + (set_attr "pool_range" "*,60")] + ) + + (define_insn "*arm_zero_extendhisi2" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + "TARGET_ARM && arm_arch4 && !arm_arch6" +- "ldr%(h%)\\t%0, %1" +- [(set_attr "type" "load_byte") ++ "@ ++ # ++ ldr%(h%)\\t%0, %1" ++ [(set_attr "type" "alu_shift,load_byte") + (set_attr "predicable" "yes") +- (set_attr "pool_range" "256") +- (set_attr "neg_pool_range" "244")] ++ (set_attr "pool_range" "*,256") ++ (set_attr "neg_pool_range" "*,244")] + ) + + (define_insn "*arm_zero_extendhisi2_v6" +@@ -4133,50 +4215,49 @@ + [(set (match_operand:SI 0 "s_register_operand" "") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] + "TARGET_EITHER" +- " +- if (!arm_arch6 && GET_CODE (operands[1]) != MEM) ++{ ++ if (TARGET_ARM && !arm_arch6 && GET_CODE (operands[1]) != MEM) + { +- if (TARGET_ARM) +- { +- emit_insn (gen_andsi3 (operands[0], +- gen_lowpart (SImode, operands[1]), +- GEN_INT (255))); +- } +- else /* TARGET_THUMB */ +- { +- rtx temp = gen_reg_rtx (SImode); +- rtx ops[3]; +- +- operands[1] = copy_to_mode_reg (QImode, operands[1]); +- operands[1] = gen_lowpart (SImode, operands[1]); +- +- ops[0] = temp; +- ops[1] = operands[1]; +- ops[2] = GEN_INT (24); +- +- emit_insn (gen_rtx_SET (VOIDmode, ops[0], +- gen_rtx_ASHIFT (SImode, ops[1], ops[2]))); +- +- ops[0] = operands[0]; +- ops[1] = temp; +- ops[2] = GEN_INT (24); ++ emit_insn (gen_andsi3 (operands[0], ++ gen_lowpart (SImode, operands[1]), ++ GEN_INT (255))); ++ DONE; ++ } ++ if (!arm_arch6 && !MEM_P (operands[1])) ++ { ++ rtx t = gen_lowpart (SImode, operands[1]); ++ rtx tmp = gen_reg_rtx (SImode); ++ emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (24))); ++ emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (24))); ++ DONE; ++ } ++}) + +- emit_insn (gen_rtx_SET (VOIDmode, ops[0], +- gen_rtx_LSHIFTRT (SImode, ops[1], ops[2]))); +- } ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (zero_extend:SI (match_operand:QI 1 "s_register_operand" "")))] ++ "!arm_arch6" ++ [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24))) ++ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] ++{ ++ operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0); ++ if (TARGET_ARM) ++ { ++ emit_insn (gen_andsi3 (operands[0], operands[2], GEN_INT (255))); + DONE; + } +- " +-) ++}) + + (define_insn "*thumb1_zero_extendqisi2" +- [(set (match_operand:SI 0 "register_operand" "=l") +- (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] ++ [(set (match_operand:SI 0 "register_operand" "=l,l") ++ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,m")))] + "TARGET_THUMB1 && !arm_arch6" +- "ldrb\\t%0, %1" +- [(set_attr "length" "2") +- (set_attr "type" "load_byte") +- (set_attr "pool_range" "32")] ++ "@ ++ # ++ ldrb\\t%0, %1" ++ [(set_attr "length" "4,2") ++ (set_attr "type" "alu_shift,load_byte") ++ (set_attr "pool_range" "*,32")] + ) + + (define_insn "*thumb1_zero_extendqisi2_v6" +@@ -4192,14 +4273,17 @@ + ) + + (define_insn "*arm_zero_extendqisi2" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] + "TARGET_ARM && !arm_arch6" +- "ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" +- [(set_attr "type" "load_byte") ++ "@ ++ # ++ ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" ++ [(set_attr "length" "8,4") ++ (set_attr "type" "alu_shift,load_byte") + (set_attr "predicable" "yes") +- (set_attr "pool_range" "4096") +- (set_attr "neg_pool_range" "4084")] ++ (set_attr "pool_range" "*,4096") ++ (set_attr "neg_pool_range" "*,4084")] + ) + + (define_insn "*arm_zero_extendqisi2_v6" +@@ -4278,108 +4362,42 @@ + ) + + (define_expand "extendhisi2" +- [(set (match_dup 2) +- (ashift:SI (match_operand:HI 1 "nonimmediate_operand" "") +- (const_int 16))) +- (set (match_operand:SI 0 "s_register_operand" "") +- (ashiftrt:SI (match_dup 2) +- (const_int 16)))] ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] + "TARGET_EITHER" +- " +- { +- if (GET_CODE (operands[1]) == MEM) +- { +- if (TARGET_THUMB1) +- { +- emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1])); +- DONE; +- } +- else if (arm_arch4) +- { +- emit_insn (gen_rtx_SET (VOIDmode, operands[0], +- gen_rtx_SIGN_EXTEND (SImode, operands[1]))); +- DONE; +- } +- } ++{ ++ if (TARGET_THUMB1) ++ { ++ emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1])); ++ DONE; ++ } ++ if (MEM_P (operands[1]) && TARGET_ARM && !arm_arch4) ++ { ++ emit_insn (gen_extendhisi2_mem (operands[0], operands[1])); ++ DONE; ++ } + +- if (TARGET_ARM && GET_CODE (operands[1]) == MEM) +- { +- emit_insn (gen_extendhisi2_mem (operands[0], operands[1])); +- DONE; +- } ++ if (!arm_arch6 && !MEM_P (operands[1])) ++ { ++ rtx t = gen_lowpart (SImode, operands[1]); ++ rtx tmp = gen_reg_rtx (SImode); ++ emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16))); ++ emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (16))); ++ DONE; ++ } ++}) + +- if (!s_register_operand (operands[1], HImode)) +- operands[1] = copy_to_mode_reg (HImode, operands[1]); +- +- if (arm_arch6) +- { +- if (TARGET_THUMB1) +- emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1])); +- else +- emit_insn (gen_rtx_SET (VOIDmode, operands[0], +- gen_rtx_SIGN_EXTEND (SImode, operands[1]))); +- +- DONE; +- } +- +- operands[1] = gen_lowpart (SImode, operands[1]); +- operands[2] = gen_reg_rtx (SImode); +- }" +-) +- +-(define_insn "thumb1_extendhisi2" +- [(set (match_operand:SI 0 "register_operand" "=l") +- (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))) +- (clobber (match_scratch:SI 2 "=&l"))] +- "TARGET_THUMB1 && !arm_arch6" +- "* +- { +- rtx ops[4]; +- rtx mem = XEXP (operands[1], 0); +- +- /* This code used to try to use 'V', and fix the address only if it was +- offsettable, but this fails for e.g. REG+48 because 48 is outside the +- range of QImode offsets, and offsettable_address_p does a QImode +- address check. */ +- +- if (GET_CODE (mem) == CONST) +- mem = XEXP (mem, 0); +- +- if (GET_CODE (mem) == LABEL_REF) +- return \"ldr\\t%0, %1\"; +- +- if (GET_CODE (mem) == PLUS) +- { +- rtx a = XEXP (mem, 0); +- rtx b = XEXP (mem, 1); +- +- if (GET_CODE (a) == LABEL_REF +- && GET_CODE (b) == CONST_INT) +- return \"ldr\\t%0, %1\"; +- +- if (GET_CODE (b) == REG) +- return \"ldrsh\\t%0, %1\"; +- +- ops[1] = a; +- ops[2] = b; +- } +- else +- { +- ops[1] = mem; +- ops[2] = const0_rtx; +- } +- +- gcc_assert (GET_CODE (ops[1]) == REG); +- +- ops[0] = operands[0]; +- ops[3] = operands[2]; +- output_asm_insn (\"mov\\t%3, %2\;ldrsh\\t%0, [%1, %3]\", ops); +- return \"\"; +- }" +- [(set_attr "length" "4") +- (set_attr "type" "load_byte") +- (set_attr "pool_range" "1020")] +-) ++(define_split ++ [(parallel ++ [(set (match_operand:SI 0 "register_operand" "") ++ (sign_extend:SI (match_operand:HI 1 "register_operand" ""))) ++ (clobber (match_scratch:SI 2 ""))])] ++ "!arm_arch6" ++ [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) ++ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))] ++{ ++ operands[2] = simplify_gen_subreg (SImode, operands[1], HImode, 0); ++}) + + ;; We used to have an early-clobber on the scratch register here. + ;; However, there's a bug somewhere in reload which means that this +@@ -4388,16 +4406,18 @@ + ;; we try to verify the operands. Fortunately, we don't really need + ;; the early-clobber: we can always use operand 0 if operand 2 + ;; overlaps the address. +-(define_insn "*thumb1_extendhisi2_insn_v6" ++(define_insn "thumb1_extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=l,l") + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m"))) + (clobber (match_scratch:SI 2 "=X,l"))] +- "TARGET_THUMB1 && arm_arch6" ++ "TARGET_THUMB1" + "* + { + rtx ops[4]; + rtx mem; + ++ if (which_alternative == 0 && !arm_arch6) ++ return \"#\"; + if (which_alternative == 0) + return \"sxth\\t%0, %1\"; + +@@ -4445,7 +4465,10 @@ + output_asm_insn (\"mov\\t%3, %2\;ldrsh\\t%0, [%1, %3]\", ops); + return \"\"; + }" +- [(set_attr "length" "2,4") ++ [(set_attr_alternative "length" ++ [(if_then_else (eq_attr "is_arch6" "yes") ++ (const_int 2) (const_int 4)) ++ (const_int 4)]) + (set_attr "type" "alu_shift,load_byte") + (set_attr "pool_range" "*,1020")] + ) +@@ -4486,15 +4509,28 @@ + }" + ) + ++(define_split ++ [(set (match_operand:SI 0 "register_operand" "") ++ (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] ++ "!arm_arch6" ++ [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) ++ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))] ++{ ++ operands[2] = simplify_gen_subreg (SImode, operands[1], HImode, 0); ++}) ++ + (define_insn "*arm_extendhisi2" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + "TARGET_ARM && arm_arch4 && !arm_arch6" +- "ldr%(sh%)\\t%0, %1" +- [(set_attr "type" "load_byte") ++ "@ ++ # ++ ldr%(sh%)\\t%0, %1" ++ [(set_attr "length" "8,4") ++ (set_attr "type" "alu_shift,load_byte") + (set_attr "predicable" "yes") +- (set_attr "pool_range" "256") +- (set_attr "neg_pool_range" "244")] ++ (set_attr "pool_range" "*,256") ++ (set_attr "neg_pool_range" "*,244")] + ) + + ;; ??? Check Thumb-2 pool range +@@ -4556,46 +4592,45 @@ + ) + + (define_expand "extendqisi2" +- [(set (match_dup 2) +- (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "") +- (const_int 24))) +- (set (match_operand:SI 0 "s_register_operand" "") +- (ashiftrt:SI (match_dup 2) +- (const_int 24)))] ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")))] + "TARGET_EITHER" +- " +- { +- if ((TARGET_THUMB || arm_arch4) && GET_CODE (operands[1]) == MEM) +- { +- emit_insn (gen_rtx_SET (VOIDmode, operands[0], +- gen_rtx_SIGN_EXTEND (SImode, operands[1]))); +- DONE; +- } +- +- if (!s_register_operand (operands[1], QImode)) +- operands[1] = copy_to_mode_reg (QImode, operands[1]); ++{ ++ if (!arm_arch4 && MEM_P (operands[1])) ++ operands[1] = copy_to_mode_reg (QImode, operands[1]); + +- if (arm_arch6) +- { +- emit_insn (gen_rtx_SET (VOIDmode, operands[0], +- gen_rtx_SIGN_EXTEND (SImode, operands[1]))); +- DONE; +- } ++ if (!arm_arch6 && !MEM_P (operands[1])) ++ { ++ rtx t = gen_lowpart (SImode, operands[1]); ++ rtx tmp = gen_reg_rtx (SImode); ++ emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (24))); ++ emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (24))); ++ DONE; ++ } ++}) + +- operands[1] = gen_lowpart (SImode, operands[1]); +- operands[2] = gen_reg_rtx (SImode); +- }" +-) ++(define_split ++ [(set (match_operand:SI 0 "register_operand" "") ++ (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] ++ "!arm_arch6" ++ [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24))) ++ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))] ++{ ++ operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0); ++}) + + (define_insn "*arm_extendqisi" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (sign_extend:SI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))] + "TARGET_ARM && arm_arch4 && !arm_arch6" +- "ldr%(sb%)\\t%0, %1" +- [(set_attr "type" "load_byte") ++ "@ ++ # ++ ldr%(sb%)\\t%0, %1" ++ [(set_attr "length" "8,4") ++ (set_attr "type" "alu_shift,load_byte") + (set_attr "predicable" "yes") +- (set_attr "pool_range" "256") +- (set_attr "neg_pool_range" "244")] ++ (set_attr "pool_range" "*,256") ++ (set_attr "neg_pool_range" "*,244")] + ) + + (define_insn "*arm_extendqisi_v6" +@@ -4623,162 +4658,103 @@ + (set_attr "predicable" "yes")] + ) + +-(define_insn "*thumb1_extendqisi2" +- [(set (match_operand:SI 0 "register_operand" "=l,l") +- (sign_extend:SI (match_operand:QI 1 "memory_operand" "V,m")))] +- "TARGET_THUMB1 && !arm_arch6" +- "* +- { +- rtx ops[3]; +- rtx mem = XEXP (operands[1], 0); +- +- if (GET_CODE (mem) == CONST) +- mem = XEXP (mem, 0); +- +- if (GET_CODE (mem) == LABEL_REF) +- return \"ldr\\t%0, %1\"; ++(define_split ++ [(set (match_operand:SI 0 "register_operand" "") ++ (sign_extend:SI (match_operand:QI 1 "memory_operand" "")))] ++ "TARGET_THUMB1 && reload_completed" ++ [(set (match_dup 0) (match_dup 2)) ++ (set (match_dup 0) (sign_extend:SI (match_dup 3)))] ++{ ++ rtx addr = XEXP (operands[1], 0); + +- if (GET_CODE (mem) == PLUS +- && GET_CODE (XEXP (mem, 0)) == LABEL_REF) +- return \"ldr\\t%0, %1\"; +- +- if (which_alternative == 0) +- return \"ldrsb\\t%0, %1\"; +- +- ops[0] = operands[0]; +- +- if (GET_CODE (mem) == PLUS) +- { +- rtx a = XEXP (mem, 0); +- rtx b = XEXP (mem, 1); +- +- ops[1] = a; +- ops[2] = b; ++ if (GET_CODE (addr) == CONST) ++ addr = XEXP (addr, 0); + +- if (GET_CODE (a) == REG) +- { +- if (GET_CODE (b) == REG) +- output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops); +- else if (REGNO (a) == REGNO (ops[0])) +- { +- output_asm_insn (\"ldrb\\t%0, [%1, %2]\", ops); +- output_asm_insn (\"lsl\\t%0, %0, #24\", ops); +- output_asm_insn (\"asr\\t%0, %0, #24\", ops); +- } +- else +- output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); +- } +- else +- { +- gcc_assert (GET_CODE (b) == REG); +- if (REGNO (b) == REGNO (ops[0])) +- { +- output_asm_insn (\"ldrb\\t%0, [%2, %1]\", ops); +- output_asm_insn (\"lsl\\t%0, %0, #24\", ops); +- output_asm_insn (\"asr\\t%0, %0, #24\", ops); +- } +- else +- output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); +- } +- } +- else if (GET_CODE (mem) == REG && REGNO (ops[0]) == REGNO (mem)) +- { +- output_asm_insn (\"ldrb\\t%0, [%0, #0]\", ops); +- output_asm_insn (\"lsl\\t%0, %0, #24\", ops); +- output_asm_insn (\"asr\\t%0, %0, #24\", ops); +- } +- else +- { +- ops[1] = mem; +- ops[2] = const0_rtx; +- +- output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); +- } +- return \"\"; +- }" +- [(set_attr "length" "2,6") +- (set_attr "type" "load_byte,load_byte") +- (set_attr "pool_range" "32,32")] +-) ++ if (GET_CODE (addr) == PLUS ++ && REG_P (XEXP (addr, 0)) && REG_P (XEXP (addr, 1))) ++ /* No split necessary. */ ++ FAIL; + +-(define_insn "*thumb1_extendqisi2_v6" ++ if (GET_CODE (addr) == PLUS ++ && !REG_P (XEXP (addr, 0)) && !REG_P (XEXP (addr, 1))) ++ FAIL; ++ ++ if (reg_overlap_mentioned_p (operands[0], addr)) ++ { ++ rtx t = gen_lowpart (QImode, operands[0]); ++ emit_move_insn (t, operands[1]); ++ emit_insn (gen_thumb1_extendqisi2 (operands[0], t)); ++ DONE; ++ } ++ ++ if (REG_P (addr)) ++ { ++ addr = gen_rtx_PLUS (Pmode, addr, operands[0]); ++ operands[2] = const0_rtx; ++ } ++ else if (GET_CODE (addr) != PLUS) ++ FAIL; ++ else if (REG_P (XEXP (addr, 0))) ++ { ++ operands[2] = XEXP (addr, 1); ++ addr = gen_rtx_PLUS (Pmode, XEXP (addr, 0), operands[0]); ++ } ++ else ++ { ++ operands[2] = XEXP (addr, 0); ++ addr = gen_rtx_PLUS (Pmode, XEXP (addr, 1), operands[0]); ++ } ++ ++ operands[3] = change_address (operands[1], QImode, addr); ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "register_operand" "") ++ (plus:SI (match_dup 0) (match_operand 1 "const_int_operand"))) ++ (set (match_operand:SI 2 "register_operand" "") (const_int 0)) ++ (set (match_operand:SI 3 "register_operand" "") ++ (sign_extend:SI (match_operand:QI 4 "memory_operand" "")))] ++ "TARGET_THUMB1 ++ && GET_CODE (XEXP (operands[4], 0)) == PLUS ++ && rtx_equal_p (operands[0], XEXP (XEXP (operands[4], 0), 0)) ++ && rtx_equal_p (operands[2], XEXP (XEXP (operands[4], 0), 1)) ++ && (peep2_reg_dead_p (3, operands[0]) ++ || rtx_equal_p (operands[0], operands[3])) ++ && (peep2_reg_dead_p (3, operands[2]) ++ || rtx_equal_p (operands[2], operands[3]))" ++ [(set (match_dup 2) (match_dup 1)) ++ (set (match_dup 3) (sign_extend:SI (match_dup 4)))] ++{ ++ rtx addr = gen_rtx_PLUS (Pmode, operands[0], operands[2]); ++ operands[4] = change_address (operands[4], QImode, addr); ++}) ++ ++(define_insn "thumb1_extendqisi2" + [(set (match_operand:SI 0 "register_operand" "=l,l,l") + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,V,m")))] +- "TARGET_THUMB1 && arm_arch6" +- "* +- { +- rtx ops[3]; +- rtx mem; +- +- if (which_alternative == 0) +- return \"sxtb\\t%0, %1\"; ++ "TARGET_THUMB1" ++{ ++ rtx addr; + +- mem = XEXP (operands[1], 0); +- +- if (GET_CODE (mem) == CONST) +- mem = XEXP (mem, 0); +- +- if (GET_CODE (mem) == LABEL_REF) +- return \"ldr\\t%0, %1\"; ++ if (which_alternative == 0 && arm_arch6) ++ return "sxtb\\t%0, %1"; ++ if (which_alternative == 0) ++ return "#"; + +- if (GET_CODE (mem) == PLUS +- && GET_CODE (XEXP (mem, 0)) == LABEL_REF) +- return \"ldr\\t%0, %1\"; ++ addr = XEXP (operands[1], 0); ++ if (GET_CODE (addr) == PLUS ++ && REG_P (XEXP (addr, 0)) && REG_P (XEXP (addr, 1))) ++ return "ldrsb\\t%0, %1"; + +- if (which_alternative == 0) +- return \"ldrsb\\t%0, %1\"; +- +- ops[0] = operands[0]; +- +- if (GET_CODE (mem) == PLUS) +- { +- rtx a = XEXP (mem, 0); +- rtx b = XEXP (mem, 1); +- +- ops[1] = a; +- ops[2] = b; +- +- if (GET_CODE (a) == REG) +- { +- if (GET_CODE (b) == REG) +- output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops); +- else if (REGNO (a) == REGNO (ops[0])) +- { +- output_asm_insn (\"ldrb\\t%0, [%1, %2]\", ops); +- output_asm_insn (\"sxtb\\t%0, %0\", ops); +- } +- else +- output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); +- } +- else +- { +- gcc_assert (GET_CODE (b) == REG); +- if (REGNO (b) == REGNO (ops[0])) +- { +- output_asm_insn (\"ldrb\\t%0, [%2, %1]\", ops); +- output_asm_insn (\"sxtb\\t%0, %0\", ops); +- } +- else +- output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); +- } +- } +- else if (GET_CODE (mem) == REG && REGNO (ops[0]) == REGNO (mem)) +- { +- output_asm_insn (\"ldrb\\t%0, [%0, #0]\", ops); +- output_asm_insn (\"sxtb\\t%0, %0\", ops); +- } +- else +- { +- ops[1] = mem; +- ops[2] = const0_rtx; +- +- output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); +- } +- return \"\"; +- }" +- [(set_attr "length" "2,2,4") +- (set_attr "type" "alu_shift,load_byte,load_byte") +- (set_attr "pool_range" "*,32,32")] ++ return "#"; ++} ++ [(set_attr_alternative "length" ++ [(if_then_else (eq_attr "is_arch6" "yes") ++ (const_int 2) (const_int 4)) ++ (const_int 2) ++ (if_then_else (eq_attr "is_arch6" "yes") ++ (const_int 4) (const_int 6))]) ++ (set_attr "type" "alu_shift,load_byte,load_byte")] + ) + + (define_expand "extendsfdf2" +@@ -5063,14 +5039,6 @@ + optimize && can_create_pseudo_p ()); + DONE; + } +- +- if (TARGET_USE_MOVT && !target_word_relocations +- && GET_CODE (operands[1]) == SYMBOL_REF +- && !flag_pic && !arm_tls_referenced_p (operands[1])) +- { +- arm_emit_movpair (operands[0], operands[1]); +- DONE; +- } + } + else /* TARGET_THUMB1... */ + { +@@ -5178,9 +5146,22 @@ + " + ) + ++(define_split ++ [(set (match_operand:SI 0 "arm_general_register_operand" "") ++ (match_operand:SI 1 "general_operand" ""))] ++ "TARGET_32BIT ++ && TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF ++ && !flag_pic && !target_word_relocations ++ && !arm_tls_referenced_p (operands[1])" ++ [(clobber (const_int 0))] ++{ ++ arm_emit_movpair (operands[0], operands[1]); ++ DONE; ++}) ++ + (define_insn "*thumb1_movsi_insn" +- [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*lhk") +- (match_operand:SI 1 "general_operand" "l, I,J,K,>,l,mi,l,*lhk"))] ++ [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*l*h*k") ++ (match_operand:SI 1 "general_operand" "l, I,J,K,>,l,mi,l,*l*h*k"))] + "TARGET_THUMB1 + && ( register_operand (operands[0], SImode) + || register_operand (operands[1], SImode))" +@@ -5203,17 +5184,21 @@ + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "const_int_operand" ""))] + "TARGET_THUMB1 && satisfies_constraint_J (operands[1])" +- [(set (match_dup 0) (match_dup 1)) +- (set (match_dup 0) (neg:SI (match_dup 0)))] +- "operands[1] = GEN_INT (- INTVAL (operands[1]));" ++ [(set (match_dup 2) (match_dup 1)) ++ (set (match_dup 0) (neg:SI (match_dup 2)))] ++ " ++ { ++ operands[1] = GEN_INT (- INTVAL (operands[1])); ++ operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0]; ++ }" + ) + + (define_split + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "const_int_operand" ""))] + "TARGET_THUMB1 && satisfies_constraint_K (operands[1])" +- [(set (match_dup 0) (match_dup 1)) +- (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))] ++ [(set (match_dup 2) (match_dup 1)) ++ (set (match_dup 0) (ashift:SI (match_dup 2) (match_dup 3)))] + " + { + unsigned HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffffffffu; +@@ -5224,12 +5209,13 @@ + if ((val & (mask << i)) == val) + break; + +- /* Shouldn't happen, but we don't want to split if the shift is zero. */ ++ /* Don't split if the shift is zero. */ + if (i == 0) + FAIL; + + operands[1] = GEN_INT (val >> i); +- operands[2] = GEN_INT (i); ++ operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0]; ++ operands[3] = GEN_INT (i); + }" + ) + +@@ -5238,6 +5224,34 @@ + ;; we use an unspec. The offset will be loaded from a constant pool entry, + ;; since that is the only type of relocation we can use. + ++;; Wrap calculation of the whole PIC address in a single pattern for the ++;; benefit of optimizers, particularly, PRE and HOIST. Calculation of ++;; a PIC address involves two loads from memory, so we want to CSE it ++;; as often as possible. ++;; This pattern will be split into one of the pic_load_addr_* patterns ++;; and a move after GCSE optimizations. ++;; ++;; Note: Update arm.c: legitimize_pic_address() when changing this pattern. ++(define_expand "calculate_pic_address" ++ [(set (match_operand:SI 0 "register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "") ++ (unspec:SI [(match_operand:SI 2 "" "")] ++ UNSPEC_PIC_SYM))))] ++ "flag_pic" ++) ++ ++;; Split calculate_pic_address into pic_load_addr_* and a move. ++(define_split ++ [(set (match_operand:SI 0 "register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "") ++ (unspec:SI [(match_operand:SI 2 "" "")] ++ UNSPEC_PIC_SYM))))] ++ "flag_pic" ++ [(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_PIC_SYM)) ++ (set (match_dup 0) (mem:SI (plus:SI (match_dup 1) (match_dup 3))))] ++ "operands[3] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];" ++) ++ + ;; The rather odd constraints on the following are to force reload to leave + ;; the insn alone, and to force the minipool generation pass to then move + ;; the GOT symbol to memory. +@@ -6268,7 +6282,7 @@ + + ;; load- and store-multiple insns + ;; The arm can load/store any set of registers, provided that they are in +-;; ascending order; but that is beyond GCC so stick with what it knows. ++;; ascending order, but these expanders assume a contiguous set. + + (define_expand "load_multiple" + [(match_par_dup 3 [(set (match_operand:SI 0 "" "") +@@ -6289,126 +6303,12 @@ + FAIL; + + operands[3] +- = arm_gen_load_multiple (REGNO (operands[0]), INTVAL (operands[2]), ++ = arm_gen_load_multiple (arm_regs_in_sequence + REGNO (operands[0]), ++ INTVAL (operands[2]), + force_reg (SImode, XEXP (operands[1], 0)), +- TRUE, FALSE, operands[1], &offset); ++ FALSE, operands[1], &offset); + }) + +-;; Load multiple with write-back +- +-(define_insn "*ldmsi_postinc4" +- [(match_parallel 0 "load_multiple_operation" +- [(set (match_operand:SI 1 "s_register_operand" "=r") +- (plus:SI (match_operand:SI 2 "s_register_operand" "1") +- (const_int 16))) +- (set (match_operand:SI 3 "arm_hard_register_operand" "") +- (mem:SI (match_dup 2))) +- (set (match_operand:SI 4 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 2) (const_int 4)))) +- (set (match_operand:SI 5 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 2) (const_int 8)))) +- (set (match_operand:SI 6 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 2) (const_int 12))))])] +- "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" +- "ldm%(ia%)\\t%1!, {%3, %4, %5, %6}" +- [(set_attr "type" "load4") +- (set_attr "predicable" "yes")] +-) +- +-(define_insn "*ldmsi_postinc4_thumb1" +- [(match_parallel 0 "load_multiple_operation" +- [(set (match_operand:SI 1 "s_register_operand" "=l") +- (plus:SI (match_operand:SI 2 "s_register_operand" "1") +- (const_int 16))) +- (set (match_operand:SI 3 "arm_hard_register_operand" "") +- (mem:SI (match_dup 2))) +- (set (match_operand:SI 4 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 2) (const_int 4)))) +- (set (match_operand:SI 5 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 2) (const_int 8)))) +- (set (match_operand:SI 6 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 2) (const_int 12))))])] +- "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" +- "ldmia\\t%1!, {%3, %4, %5, %6}" +- [(set_attr "type" "load4")] +-) +- +-(define_insn "*ldmsi_postinc3" +- [(match_parallel 0 "load_multiple_operation" +- [(set (match_operand:SI 1 "s_register_operand" "=r") +- (plus:SI (match_operand:SI 2 "s_register_operand" "1") +- (const_int 12))) +- (set (match_operand:SI 3 "arm_hard_register_operand" "") +- (mem:SI (match_dup 2))) +- (set (match_operand:SI 4 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 2) (const_int 4)))) +- (set (match_operand:SI 5 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 2) (const_int 8))))])] +- "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" +- "ldm%(ia%)\\t%1!, {%3, %4, %5}" +- [(set_attr "type" "load3") +- (set_attr "predicable" "yes")] +-) +- +-(define_insn "*ldmsi_postinc2" +- [(match_parallel 0 "load_multiple_operation" +- [(set (match_operand:SI 1 "s_register_operand" "=r") +- (plus:SI (match_operand:SI 2 "s_register_operand" "1") +- (const_int 8))) +- (set (match_operand:SI 3 "arm_hard_register_operand" "") +- (mem:SI (match_dup 2))) +- (set (match_operand:SI 4 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 2) (const_int 4))))])] +- "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" +- "ldm%(ia%)\\t%1!, {%3, %4}" +- [(set_attr "type" "load2") +- (set_attr "predicable" "yes")] +-) +- +-;; Ordinary load multiple +- +-(define_insn "*ldmsi4" +- [(match_parallel 0 "load_multiple_operation" +- [(set (match_operand:SI 2 "arm_hard_register_operand" "") +- (mem:SI (match_operand:SI 1 "s_register_operand" "r"))) +- (set (match_operand:SI 3 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 1) (const_int 4)))) +- (set (match_operand:SI 4 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 1) (const_int 8)))) +- (set (match_operand:SI 5 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] +- "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" +- "ldm%(ia%)\\t%1, {%2, %3, %4, %5}" +- [(set_attr "type" "load4") +- (set_attr "predicable" "yes")] +-) +- +-(define_insn "*ldmsi3" +- [(match_parallel 0 "load_multiple_operation" +- [(set (match_operand:SI 2 "arm_hard_register_operand" "") +- (mem:SI (match_operand:SI 1 "s_register_operand" "r"))) +- (set (match_operand:SI 3 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 1) (const_int 4)))) +- (set (match_operand:SI 4 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] +- "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" +- "ldm%(ia%)\\t%1, {%2, %3, %4}" +- [(set_attr "type" "load3") +- (set_attr "predicable" "yes")] +-) +- +-(define_insn "*ldmsi2" +- [(match_parallel 0 "load_multiple_operation" +- [(set (match_operand:SI 2 "arm_hard_register_operand" "") +- (mem:SI (match_operand:SI 1 "s_register_operand" "r"))) +- (set (match_operand:SI 3 "arm_hard_register_operand" "") +- (mem:SI (plus:SI (match_dup 1) (const_int 4))))])] +- "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" +- "ldm%(ia%)\\t%1, {%2, %3}" +- [(set_attr "type" "load2") +- (set_attr "predicable" "yes")] +-) +- + (define_expand "store_multiple" + [(match_par_dup 3 [(set (match_operand:SI 0 "" "") + (match_operand:SI 1 "" "")) +@@ -6428,125 +6328,12 @@ + FAIL; + + operands[3] +- = arm_gen_store_multiple (REGNO (operands[1]), INTVAL (operands[2]), ++ = arm_gen_store_multiple (arm_regs_in_sequence + REGNO (operands[1]), ++ INTVAL (operands[2]), + force_reg (SImode, XEXP (operands[0], 0)), +- TRUE, FALSE, operands[0], &offset); ++ FALSE, operands[0], &offset); + }) + +-;; Store multiple with write-back +- +-(define_insn "*stmsi_postinc4" +- [(match_parallel 0 "store_multiple_operation" +- [(set (match_operand:SI 1 "s_register_operand" "=r") +- (plus:SI (match_operand:SI 2 "s_register_operand" "1") +- (const_int 16))) +- (set (mem:SI (match_dup 2)) +- (match_operand:SI 3 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) +- (match_operand:SI 4 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) +- (match_operand:SI 5 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) +- (match_operand:SI 6 "arm_hard_register_operand" ""))])] +- "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" +- "stm%(ia%)\\t%1!, {%3, %4, %5, %6}" +- [(set_attr "predicable" "yes") +- (set_attr "type" "store4")] +-) +- +-(define_insn "*stmsi_postinc4_thumb1" +- [(match_parallel 0 "store_multiple_operation" +- [(set (match_operand:SI 1 "s_register_operand" "=l") +- (plus:SI (match_operand:SI 2 "s_register_operand" "1") +- (const_int 16))) +- (set (mem:SI (match_dup 2)) +- (match_operand:SI 3 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) +- (match_operand:SI 4 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) +- (match_operand:SI 5 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) +- (match_operand:SI 6 "arm_hard_register_operand" ""))])] +- "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" +- "stmia\\t%1!, {%3, %4, %5, %6}" +- [(set_attr "type" "store4")] +-) +- +-(define_insn "*stmsi_postinc3" +- [(match_parallel 0 "store_multiple_operation" +- [(set (match_operand:SI 1 "s_register_operand" "=r") +- (plus:SI (match_operand:SI 2 "s_register_operand" "1") +- (const_int 12))) +- (set (mem:SI (match_dup 2)) +- (match_operand:SI 3 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) +- (match_operand:SI 4 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) +- (match_operand:SI 5 "arm_hard_register_operand" ""))])] +- "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" +- "stm%(ia%)\\t%1!, {%3, %4, %5}" +- [(set_attr "predicable" "yes") +- (set_attr "type" "store3")] +-) +- +-(define_insn "*stmsi_postinc2" +- [(match_parallel 0 "store_multiple_operation" +- [(set (match_operand:SI 1 "s_register_operand" "=r") +- (plus:SI (match_operand:SI 2 "s_register_operand" "1") +- (const_int 8))) +- (set (mem:SI (match_dup 2)) +- (match_operand:SI 3 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) +- (match_operand:SI 4 "arm_hard_register_operand" ""))])] +- "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" +- "stm%(ia%)\\t%1!, {%3, %4}" +- [(set_attr "predicable" "yes") +- (set_attr "type" "store2")] +-) +- +-;; Ordinary store multiple +- +-(define_insn "*stmsi4" +- [(match_parallel 0 "store_multiple_operation" +- [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r")) +- (match_operand:SI 2 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) +- (match_operand:SI 3 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) +- (match_operand:SI 4 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) +- (match_operand:SI 5 "arm_hard_register_operand" ""))])] +- "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" +- "stm%(ia%)\\t%1, {%2, %3, %4, %5}" +- [(set_attr "predicable" "yes") +- (set_attr "type" "store4")] +-) +- +-(define_insn "*stmsi3" +- [(match_parallel 0 "store_multiple_operation" +- [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r")) +- (match_operand:SI 2 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) +- (match_operand:SI 3 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) +- (match_operand:SI 4 "arm_hard_register_operand" ""))])] +- "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" +- "stm%(ia%)\\t%1, {%2, %3, %4}" +- [(set_attr "predicable" "yes") +- (set_attr "type" "store3")] +-) +- +-(define_insn "*stmsi2" +- [(match_parallel 0 "store_multiple_operation" +- [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r")) +- (match_operand:SI 2 "arm_hard_register_operand" "")) +- (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) +- (match_operand:SI 3 "arm_hard_register_operand" ""))])] +- "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" +- "stm%(ia%)\\t%1, {%2, %3}" +- [(set_attr "predicable" "yes") +- (set_attr "type" "store2")] +-) + + ;; Move a block of memory if it is word aligned and MORE than 2 words long. + ;; We could let this apply for blocks of less than this, but it clobbers so +@@ -6557,7 +6344,7 @@ + (match_operand:BLK 1 "general_operand" "") + (match_operand:SI 2 "const_int_operand" "") + (match_operand:SI 3 "const_int_operand" "")] +- "TARGET_EITHER" ++ "TARGET_EITHER && !low_irq_latency" + " + if (TARGET_32BIT) + { +@@ -6666,6 +6453,30 @@ + operands[2] = force_reg (SImode, operands[2]); + ") + ++;; A pattern to recognize a special situation and optimize for it. ++;; On the thumb, zero-extension from memory is preferrable to sign-extension ++;; due to the available addressing modes. Hence, convert a signed comparison ++;; with zero into an unsigned comparison with 127 if possible. ++(define_expand "cbranchqi4" ++ [(set (pc) (if_then_else ++ (match_operator 0 "lt_ge_comparison_operator" ++ [(match_operand:QI 1 "memory_operand" "") ++ (match_operand:QI 2 "const0_operand" "")]) ++ (label_ref (match_operand 3 "" "")) ++ (pc)))] ++ "TARGET_THUMB1" ++{ ++ rtx xops[4]; ++ xops[1] = gen_reg_rtx (SImode); ++ emit_insn (gen_zero_extendqisi2 (xops[1], operands[1])); ++ xops[2] = GEN_INT (127); ++ xops[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]) == GE ? LEU : GTU, ++ VOIDmode, xops[1], xops[2]); ++ xops[3] = operands[3]; ++ emit_insn (gen_cbranchsi4 (xops[0], xops[1], xops[2], xops[3])); ++ DONE; ++}) ++ + (define_expand "cbranchsf4" + [(set (pc) (if_then_else + (match_operator 0 "arm_comparison_operator" +@@ -6690,20 +6501,48 @@ + operands[3])); DONE;" + ) + +-;; this uses the Cirrus DI compare instruction + (define_expand "cbranchdi4" + [(set (pc) (if_then_else + (match_operator 0 "arm_comparison_operator" +- [(match_operand:DI 1 "cirrus_fp_register" "") +- (match_operand:DI 2 "cirrus_fp_register" "")]) ++ [(match_operand:DI 1 "cmpdi_operand" "") ++ (match_operand:DI 2 "cmpdi_operand" "")]) + (label_ref (match_operand 3 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2], +- operands[3])); DONE;" ++ "TARGET_32BIT" ++ "{ ++ rtx swap = NULL_RTX; ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ /* We should not have two constants. */ ++ gcc_assert (GET_MODE (operands[1]) == DImode ++ || GET_MODE (operands[2]) == DImode); ++ ++ /* Flip unimplemented DImode comparisons to a form that ++ arm_gen_compare_reg can handle. */ ++ switch (code) ++ { ++ case GT: ++ swap = gen_rtx_LT (VOIDmode, operands[2], operands[1]); break; ++ case LE: ++ swap = gen_rtx_GE (VOIDmode, operands[2], operands[1]); break; ++ case GTU: ++ swap = gen_rtx_LTU (VOIDmode, operands[2], operands[1]); break; ++ case LEU: ++ swap = gen_rtx_GEU (VOIDmode, operands[2], operands[1]); break; ++ default: ++ break; ++ } ++ if (swap) ++ emit_jump_insn (gen_cbranch_cc (swap, operands[2], operands[1], ++ operands[3])); ++ else ++ emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2], ++ operands[3])); ++ DONE; ++ }" + ) + +-(define_insn "*cbranchsi4_insn" ++(define_insn "cbranchsi4_insn" + [(set (pc) (if_then_else + (match_operator 0 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "l,*h") +@@ -6712,7 +6551,20 @@ + (pc)))] + "TARGET_THUMB1" + "* +- output_asm_insn (\"cmp\\t%1, %2\", operands); ++ rtx t = prev_nonnote_insn (insn); ++ if (t != NULL_RTX ++ && INSN_P (t) ++ && INSN_CODE (t) == CODE_FOR_cbranchsi4_insn) ++ { ++ t = XEXP (SET_SRC (PATTERN (t)), 0); ++ if (!rtx_equal_p (XEXP (t, 0), operands[1]) ++ || !rtx_equal_p (XEXP (t, 1), operands[2])) ++ t = NULL_RTX; ++ } ++ else ++ t = NULL_RTX; ++ if (t == NULL_RTX) ++ output_asm_insn (\"cmp\\t%1, %2\", operands); + + switch (get_attr_length (insn)) + { +@@ -7528,15 +7380,15 @@ + (if_then_else + (match_operator 4 "arm_comparison_operator" + [(plus:SI +- (match_operand:SI 2 "s_register_operand" "%l,0,*0,1,1,1") +- (match_operand:SI 3 "reg_or_int_operand" "lL,IJ,*r,lIJ,lIJ,lIJ")) ++ (match_operand:SI 2 "s_register_operand" "%0,l,*l,1,1,1") ++ (match_operand:SI 3 "reg_or_int_operand" "IJ,lL,*l,lIJ,lIJ,lIJ")) + (const_int 0)]) + (label_ref (match_operand 5 "" "")) + (pc))) + (set + (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*!h,*?h,*?m,*?m") + (plus:SI (match_dup 2) (match_dup 3))) +- (clobber (match_scratch:SI 1 "=X,X,X,l,&l,&l"))] ++ (clobber (match_scratch:SI 1 "=X,X,l,l,&l,&l"))] + "TARGET_THUMB1 + && (GET_CODE (operands[4]) == EQ + || GET_CODE (operands[4]) == NE +@@ -7546,8 +7398,7 @@ + { + rtx cond[3]; + +- +- cond[0] = (which_alternative < 3) ? operands[0] : operands[1]; ++ cond[0] = (which_alternative < 2) ? operands[0] : operands[1]; + cond[1] = operands[2]; + cond[2] = operands[3]; + +@@ -7556,13 +7407,13 @@ + else + output_asm_insn (\"add\\t%0, %1, %2\", cond); + +- if (which_alternative >= 3 ++ if (which_alternative >= 2 + && which_alternative < 4) + output_asm_insn (\"mov\\t%0, %1\", operands); + else if (which_alternative >= 4) + output_asm_insn (\"str\\t%1, %0\", operands); + +- switch (get_attr_length (insn) - ((which_alternative >= 3) ? 2 : 0)) ++ switch (get_attr_length (insn) - ((which_alternative >= 2) ? 2 : 0)) + { + case 4: + return \"b%d4\\t%l5\"; +@@ -7576,7 +7427,7 @@ + [(set (attr "far_jump") + (if_then_else + (ior (and (lt (symbol_ref ("which_alternative")) +- (const_int 3)) ++ (const_int 2)) + (eq_attr "length" "8")) + (eq_attr "length" "10")) + (const_string "yes") +@@ -7584,7 +7435,7 @@ + (set (attr "length") + (if_then_else + (lt (symbol_ref ("which_alternative")) +- (const_int 3)) ++ (const_int 2)) + (if_then_else + (and (ge (minus (match_dup 5) (pc)) (const_int -250)) + (le (minus (match_dup 5) (pc)) (const_int 256))) +@@ -7852,6 +7703,52 @@ + (const_string "alu_shift_reg")))] + ) + ++;; DImode comparisons. The generic code generates branches that ++;; if-conversion can not reduce to a conditional compare, so we do ++;; that directly. ++ ++(define_insn "*arm_cmpdi_insn" ++ [(set (reg:CC_NCV CC_REGNUM) ++ (compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r") ++ (match_operand:DI 1 "arm_di_operand" "rDi"))) ++ (clobber (match_scratch:SI 2 "=r"))] ++ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1" ++ [(set_attr "conds" "set") ++ (set_attr "length" "8")] ++) ++ ++(define_insn "*arm_cmpdi_unsigned" ++ [(set (reg:CC_CZ CC_REGNUM) ++ (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r") ++ (match_operand:DI 1 "arm_di_operand" "rDi")))] ++ "TARGET_ARM" ++ "cmp%?\\t%R0, %R1\;cmpeq\\t%Q0, %Q1" ++ [(set_attr "conds" "set") ++ (set_attr "length" "8")] ++) ++ ++(define_insn "*arm_cmpdi_zero" ++ [(set (reg:CC_Z CC_REGNUM) ++ (compare:CC_Z (match_operand:DI 0 "s_register_operand" "r") ++ (const_int 0))) ++ (clobber (match_scratch:SI 1 "=r"))] ++ "TARGET_32BIT" ++ "orr%.\\t%1, %Q0, %R0" ++ [(set_attr "conds" "set")] ++) ++ ++(define_insn "*thumb_cmpdi_zero" ++ [(set (reg:CC_Z CC_REGNUM) ++ (compare:CC_Z (match_operand:DI 0 "s_register_operand" "l") ++ (const_int 0))) ++ (clobber (match_scratch:SI 1 "=l"))] ++ "TARGET_THUMB1" ++ "orr\\t%1, %Q0, %R0" ++ [(set_attr "conds" "set") ++ (set_attr "length" "2")] ++) ++ + ;; Cirrus SF compare instruction + (define_insn "*cirrus_cmpsf" + [(set (reg:CCFP CC_REGNUM) +@@ -8150,22 +8047,49 @@ + (match_operator:SI 1 "arm_comparison_operator" + [(match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "arm_float_compare_operand" "")]))] +- "TARGET_32BIT && TARGET_HARD_FLOAT" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" + "emit_insn (gen_cstore_cc (operands[0], operands[1], + operands[2], operands[3])); DONE;" + ) + +-;; this uses the Cirrus DI compare instruction + (define_expand "cstoredi4" + [(set (match_operand:SI 0 "s_register_operand" "") + (match_operator:SI 1 "arm_comparison_operator" +- [(match_operand:DI 2 "cirrus_fp_register" "") +- (match_operand:DI 3 "cirrus_fp_register" "")]))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "emit_insn (gen_cstore_cc (operands[0], operands[1], +- operands[2], operands[3])); DONE;" +-) ++ [(match_operand:DI 2 "cmpdi_operand" "") ++ (match_operand:DI 3 "cmpdi_operand" "")]))] ++ "TARGET_32BIT" ++ "{ ++ rtx swap = NULL_RTX; ++ enum rtx_code code = GET_CODE (operands[1]); + ++ /* We should not have two constants. */ ++ gcc_assert (GET_MODE (operands[2]) == DImode ++ || GET_MODE (operands[3]) == DImode); ++ ++ /* Flip unimplemented DImode comparisons to a form that ++ arm_gen_compare_reg can handle. */ ++ switch (code) ++ { ++ case GT: ++ swap = gen_rtx_LT (VOIDmode, operands[3], operands[2]); break; ++ case LE: ++ swap = gen_rtx_GE (VOIDmode, operands[3], operands[2]); break; ++ case GTU: ++ swap = gen_rtx_LTU (VOIDmode, operands[3], operands[2]); break; ++ case LEU: ++ swap = gen_rtx_GEU (VOIDmode, operands[3], operands[2]); break; ++ default: ++ break; ++ } ++ if (swap) ++ emit_insn (gen_cstore_cc (operands[0], swap, operands[3], ++ operands[2])); ++ else ++ emit_insn (gen_cstore_cc (operands[0], operands[1], operands[2], ++ operands[3])); ++ DONE; ++ }" ++) + + (define_expand "cstoresi_eq0_thumb1" + [(parallel +@@ -8625,7 +8549,7 @@ + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM ++ "TARGET_32BIT + && (GET_CODE (operands[0]) == SYMBOL_REF) + && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" + "* +@@ -8641,7 +8565,7 @@ + (match_operand:SI 2 "" ""))) + (use (match_operand 3 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM ++ "TARGET_32BIT + && (GET_CODE (operands[1]) == SYMBOL_REF) + && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" + "* +@@ -8656,7 +8580,7 @@ + (match_operand:SI 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_THUMB ++ "TARGET_THUMB1 + && GET_CODE (operands[0]) == SYMBOL_REF + && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" + "bl\\t%a0" +@@ -8670,7 +8594,7 @@ + (match_operand 2 "" ""))) + (use (match_operand 3 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_THUMB ++ "TARGET_THUMB1 + && GET_CODE (operands[1]) == SYMBOL_REF + && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" + "bl\\t%a1" +@@ -8684,7 +8608,7 @@ + (match_operand 1 "general_operand" "")) + (return) + (use (match_operand 2 "" ""))])] +- "TARGET_ARM" ++ "TARGET_32BIT" + " + { + if (operands[2] == NULL_RTX) +@@ -8698,7 +8622,7 @@ + (match_operand 2 "general_operand" ""))) + (return) + (use (match_operand 3 "" ""))])] +- "TARGET_ARM" ++ "TARGET_32BIT" + " + { + if (operands[3] == NULL_RTX) +@@ -8711,7 +8635,7 @@ + (match_operand 1 "" "")) + (return) + (use (match_operand 2 "" ""))] +- "TARGET_ARM && GET_CODE (operands[0]) == SYMBOL_REF" ++ "TARGET_32BIT && GET_CODE (operands[0]) == SYMBOL_REF" + "* + return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; + " +@@ -8724,68 +8648,79 @@ + (match_operand 2 "" ""))) + (return) + (use (match_operand 3 "" ""))] +- "TARGET_ARM && GET_CODE (operands[1]) == SYMBOL_REF" ++ "TARGET_32BIT && GET_CODE (operands[1]) == SYMBOL_REF" + "* + return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; + " + [(set_attr "type" "call")] + ) + +-;; Often the return insn will be the same as loading from memory, so set attr +-(define_insn "return" +- [(return)] +- "TARGET_ARM && USE_RETURN_INSN (FALSE)" +- "* +- { +- if (arm_ccfsm_state == 2) +- { +- arm_ccfsm_state += 2; +- return \"\"; +- } +- return output_return_instruction (const_true_rtx, TRUE, FALSE); +- }" ++;; Both kinds of return insn. ++(define_code_iterator returns [return simple_return]) ++(define_code_attr return_str [(return "") (simple_return "simple_")]) ++(define_code_attr return_simple_p [(return "false") (simple_return "true")]) ++(define_code_attr return_cond [(return " && USE_RETURN_INSN (FALSE)") ++ (simple_return " && use_simple_return_p ()")]) ++ ++(define_expand "return" ++ [(returns)] ++ "TARGET_32BIT" ++ "") ++ ++(define_insn "*arm_return" ++ [(returns)] ++ "TARGET_ARM" ++{ ++ if (arm_ccfsm_state == 2) ++ { ++ arm_ccfsm_state += 2; ++ return ""; ++ } ++ return output_return_instruction (const_true_rtx, true, false, ++ ); ++} + [(set_attr "type" "load1") + (set_attr "length" "12") + (set_attr "predicable" "yes")] + ) + +-(define_insn "*cond_return" ++(define_insn "*cond_return" + [(set (pc) + (if_then_else (match_operator 0 "arm_comparison_operator" + [(match_operand 1 "cc_register" "") (const_int 0)]) +- (return) ++ (returns) + (pc)))] +- "TARGET_ARM && USE_RETURN_INSN (TRUE)" +- "* +- { +- if (arm_ccfsm_state == 2) +- { +- arm_ccfsm_state += 2; +- return \"\"; +- } +- return output_return_instruction (operands[0], TRUE, FALSE); +- }" ++ "TARGET_ARM" ++{ ++ if (arm_ccfsm_state == 2) ++ { ++ arm_ccfsm_state += 2; ++ return ""; ++ } ++ return output_return_instruction (operands[0], true, false, ++ ); ++} + [(set_attr "conds" "use") + (set_attr "length" "12") + (set_attr "type" "load1")] + ) + +-(define_insn "*cond_return_inverted" ++(define_insn "*cond_return_inverted" + [(set (pc) + (if_then_else (match_operator 0 "arm_comparison_operator" + [(match_operand 1 "cc_register" "") (const_int 0)]) + (pc) +- (return)))] +- "TARGET_ARM && USE_RETURN_INSN (TRUE)" +- "* +- { +- if (arm_ccfsm_state == 2) +- { +- arm_ccfsm_state += 2; +- return \"\"; +- } +- return output_return_instruction (operands[0], TRUE, TRUE); +- }" ++ (returns)))] ++ "TARGET_ARM" ++{ ++ if (arm_ccfsm_state == 2) ++ { ++ arm_ccfsm_state += 2; ++ return ""; ++ } ++ return output_return_instruction (operands[0], true, true, ++ ); ++} + [(set_attr "conds" "use") + (set_attr "length" "12") + (set_attr "type" "load1")] +@@ -8869,8 +8804,8 @@ + if (REGNO (reg) == R0_REGNUM) + { + /* On thumb we have to use a write-back instruction. */ +- emit_insn (arm_gen_store_multiple (R0_REGNUM, 4, addr, TRUE, +- TARGET_THUMB ? TRUE : FALSE, mem, &offset)); ++ emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, addr, ++ TARGET_THUMB ? TRUE : FALSE, mem, &offset)); + size = TARGET_ARM ? 16 : 0; + } + else +@@ -8916,8 +8851,8 @@ + if (REGNO (reg) == R0_REGNUM) + { + /* On thumb we have to use a write-back instruction. */ +- emit_insn (arm_gen_load_multiple (R0_REGNUM, 4, addr, TRUE, +- TARGET_THUMB ? TRUE : FALSE, mem, &offset)); ++ emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, addr, ++ TARGET_THUMB ? TRUE : FALSE, mem, &offset)); + size = TARGET_ARM ? 16 : 0; + } + else +@@ -9114,7 +9049,7 @@ + [(match_operator:SI 3 "shift_operator" + [(match_operand:SI 4 "s_register_operand" "r") + (match_operand:SI 5 "reg_or_int_operand" "rI")]) +- (match_operand:SI 2 "s_register_operand" "r")]))] ++ (match_operand:SI 2 "s_register_operand" "rk")]))] + "TARGET_ARM" + "%i1%?\\t%0, %2, %4%S3" + [(set_attr "predicable" "yes") +@@ -9259,41 +9194,117 @@ + (set_attr "length" "4,8")] + ) + +-(define_insn "*compare_scc" ++; A series of splitters for the compare_scc pattern below. Note that ++; order is important. ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (lt:SI (match_operand:SI 1 "s_register_operand" "") ++ (const_int 0))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT && reload_completed" ++ [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 31)))]) ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (ge:SI (match_operand:SI 1 "s_register_operand" "") ++ (const_int 0))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT && reload_completed" ++ [(set (match_dup 0) (not:SI (match_dup 1))) ++ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 31)))]) ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (eq:SI (match_operand:SI 1 "s_register_operand" "") ++ (const_int 0))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT && reload_completed" ++ [(parallel ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (const_int 1) (match_dup 1))) ++ (set (match_dup 0) ++ (minus:SI (const_int 1) (match_dup 1)))]) ++ (cond_exec (ltu:CC (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) (const_int 0)))]) ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (ne:SI (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 2 "const_int_operand" ""))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT && reload_completed" ++ [(parallel ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))]) ++ (cond_exec (ne:CC (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) (const_int 1)))] ++{ ++ operands[3] = GEN_INT (-INTVAL (operands[2])); ++}) ++ ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (ne:SI (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 2 "arm_add_operand" ""))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT && reload_completed" ++ [(parallel ++ [(set (reg:CC_NOOV CC_REGNUM) ++ (compare:CC_NOOV (minus:SI (match_dup 1) (match_dup 2)) ++ (const_int 0))) ++ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) ++ (cond_exec (ne:CC_NOOV (reg:CC_NOOV CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) (const_int 1)))]) ++ ++(define_insn_and_split "*compare_scc" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (match_operator:SI 1 "arm_comparison_operator" + [(match_operand:SI 2 "s_register_operand" "r,r") + (match_operand:SI 3 "arm_add_operand" "rI,L")])) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "* +- if (operands[3] == const0_rtx) +- { +- if (GET_CODE (operands[1]) == LT) +- return \"mov\\t%0, %2, lsr #31\"; +- +- if (GET_CODE (operands[1]) == GE) +- return \"mvn\\t%0, %2\;mov\\t%0, %0, lsr #31\"; +- +- if (GET_CODE (operands[1]) == EQ) +- return \"rsbs\\t%0, %2, #1\;movcc\\t%0, #0\"; +- } ++ "TARGET_32BIT" ++ "#" ++ "&& reload_completed" ++ [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 3))) ++ (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0))) ++ (cond_exec (match_dup 5) (set (match_dup 0) (const_int 1)))] ++{ ++ rtx tmp1; ++ enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), ++ operands[2], operands[3]); ++ enum rtx_code rc = GET_CODE (operands[1]); ++ ++ tmp1 = gen_rtx_REG (mode, CC_REGNUM); ++ ++ operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx); ++ if (mode == CCFPmode || mode == CCFPEmode) ++ rc = reverse_condition_maybe_unordered (rc); ++ else ++ rc = reverse_condition (rc); ++ operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx); ++}) + +- if (GET_CODE (operands[1]) == NE) +- { +- if (which_alternative == 1) +- return \"adds\\t%0, %2, #%n3\;movne\\t%0, #1\"; +- return \"subs\\t%0, %2, %3\;movne\\t%0, #1\"; +- } +- if (which_alternative == 1) +- output_asm_insn (\"cmn\\t%2, #%n3\", operands); +- else +- output_asm_insn (\"cmp\\t%2, %3\", operands); +- return \"mov%D1\\t%0, #0\;mov%d1\\t%0, #1\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "12")] +-) ++;; Attempt to improve the sequence generated by the compare_scc splitters ++;; not to use conditional execution. ++(define_peephole2 ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_operand:SI 1 "register_operand" "") ++ (match_operand:SI 2 "arm_rhs_operand" ""))) ++ (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "") (const_int 0))) ++ (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) (const_int 1))) ++ (match_scratch:SI 3 "r")] ++ "TARGET_32BIT" ++ [(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) ++ (parallel ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (const_int 0) (match_dup 3))) ++ (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))]) ++ (set (match_dup 0) ++ (plus:SI (plus:SI (match_dup 0) (match_dup 3)) ++ (geu:SI (reg:CC CC_REGNUM) (const_int 0))))]) + + (define_insn "*cond_move" + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +@@ -10434,87 +10445,6 @@ + "" + ) + +-; Peepholes to spot possible load- and store-multiples, if the ordering is +-; reversed, check that the memory references aren't volatile. +- +-(define_peephole +- [(set (match_operand:SI 0 "s_register_operand" "=rk") +- (match_operand:SI 4 "memory_operand" "m")) +- (set (match_operand:SI 1 "s_register_operand" "=rk") +- (match_operand:SI 5 "memory_operand" "m")) +- (set (match_operand:SI 2 "s_register_operand" "=rk") +- (match_operand:SI 6 "memory_operand" "m")) +- (set (match_operand:SI 3 "s_register_operand" "=rk") +- (match_operand:SI 7 "memory_operand" "m"))] +- "TARGET_ARM && load_multiple_sequence (operands, 4, NULL, NULL, NULL)" +- "* +- return emit_ldm_seq (operands, 4); +- " +-) +- +-(define_peephole +- [(set (match_operand:SI 0 "s_register_operand" "=rk") +- (match_operand:SI 3 "memory_operand" "m")) +- (set (match_operand:SI 1 "s_register_operand" "=rk") +- (match_operand:SI 4 "memory_operand" "m")) +- (set (match_operand:SI 2 "s_register_operand" "=rk") +- (match_operand:SI 5 "memory_operand" "m"))] +- "TARGET_ARM && load_multiple_sequence (operands, 3, NULL, NULL, NULL)" +- "* +- return emit_ldm_seq (operands, 3); +- " +-) +- +-(define_peephole +- [(set (match_operand:SI 0 "s_register_operand" "=rk") +- (match_operand:SI 2 "memory_operand" "m")) +- (set (match_operand:SI 1 "s_register_operand" "=rk") +- (match_operand:SI 3 "memory_operand" "m"))] +- "TARGET_ARM && load_multiple_sequence (operands, 2, NULL, NULL, NULL)" +- "* +- return emit_ldm_seq (operands, 2); +- " +-) +- +-(define_peephole +- [(set (match_operand:SI 4 "memory_operand" "=m") +- (match_operand:SI 0 "s_register_operand" "rk")) +- (set (match_operand:SI 5 "memory_operand" "=m") +- (match_operand:SI 1 "s_register_operand" "rk")) +- (set (match_operand:SI 6 "memory_operand" "=m") +- (match_operand:SI 2 "s_register_operand" "rk")) +- (set (match_operand:SI 7 "memory_operand" "=m") +- (match_operand:SI 3 "s_register_operand" "rk"))] +- "TARGET_ARM && store_multiple_sequence (operands, 4, NULL, NULL, NULL)" +- "* +- return emit_stm_seq (operands, 4); +- " +-) +- +-(define_peephole +- [(set (match_operand:SI 3 "memory_operand" "=m") +- (match_operand:SI 0 "s_register_operand" "rk")) +- (set (match_operand:SI 4 "memory_operand" "=m") +- (match_operand:SI 1 "s_register_operand" "rk")) +- (set (match_operand:SI 5 "memory_operand" "=m") +- (match_operand:SI 2 "s_register_operand" "rk"))] +- "TARGET_ARM && store_multiple_sequence (operands, 3, NULL, NULL, NULL)" +- "* +- return emit_stm_seq (operands, 3); +- " +-) +- +-(define_peephole +- [(set (match_operand:SI 2 "memory_operand" "=m") +- (match_operand:SI 0 "s_register_operand" "rk")) +- (set (match_operand:SI 3 "memory_operand" "=m") +- (match_operand:SI 1 "s_register_operand" "rk"))] +- "TARGET_ARM && store_multiple_sequence (operands, 2, NULL, NULL, NULL)" +- "* +- return emit_stm_seq (operands, 2); +- " +-) +- + (define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "") +@@ -10577,8 +10507,7 @@ + DONE; + } + emit_jump_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, +- gen_rtvec (1, +- gen_rtx_RETURN (VOIDmode)), ++ gen_rtvec (1, ret_rtx), + VUNSPEC_EPILOGUE)); + DONE; + " +@@ -10595,7 +10524,7 @@ + "TARGET_32BIT" + "* + if (use_return_insn (FALSE, next_nonnote_insn (insn))) +- return output_return_instruction (const_true_rtx, FALSE, FALSE); ++ return output_return_instruction (const_true_rtx, false, false, false); + return arm_output_epilogue (next_nonnote_insn (insn)); + " + ;; Length is absolute worst case +@@ -10913,6 +10842,24 @@ + " + ) + ++(define_insn "align_16" ++ [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN16)] ++ "TARGET_EITHER" ++ "* ++ assemble_align (128); ++ return \"\"; ++ " ++) ++ ++(define_insn "align_32" ++ [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN32)] ++ "TARGET_EITHER" ++ "* ++ assemble_align (256); ++ return \"\"; ++ " ++) ++ + (define_insn "consttable_end" + [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)] + "TARGET_EITHER" +@@ -11273,37 +11220,35 @@ + (define_expand "bswapsi2" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))] +-"TARGET_EITHER" ++"TARGET_EITHER && (arm_arch6 || !optimize_size)" + " +- if (!arm_arch6) +- { +- if (!optimize_size) +- { +- rtx op2 = gen_reg_rtx (SImode); +- rtx op3 = gen_reg_rtx (SImode); ++ if (!arm_arch6) ++ { ++ rtx op2 = gen_reg_rtx (SImode); ++ rtx op3 = gen_reg_rtx (SImode); + +- if (TARGET_THUMB) +- { +- rtx op4 = gen_reg_rtx (SImode); +- rtx op5 = gen_reg_rtx (SImode); ++ if (TARGET_THUMB) ++ { ++ rtx op4 = gen_reg_rtx (SImode); ++ rtx op5 = gen_reg_rtx (SImode); + +- emit_insn (gen_thumb_legacy_rev (operands[0], operands[1], +- op2, op3, op4, op5)); +- } +- else +- { +- emit_insn (gen_arm_legacy_rev (operands[0], operands[1], +- op2, op3)); +- } ++ emit_insn (gen_thumb_legacy_rev (operands[0], operands[1], ++ op2, op3, op4, op5)); ++ } ++ else ++ { ++ emit_insn (gen_arm_legacy_rev (operands[0], operands[1], ++ op2, op3)); ++ } + +- DONE; +- } +- else +- FAIL; +- } ++ DONE; ++ } + " + ) + ++;; Make sure that the includes are reflected in MD_INCLUDES. ++;; Load the load/store multiple patterns ++(include "ldmstm.md") + ;; Load the FPA co-processor patterns + (include "fpa.md") + ;; Load the Maverick co-processor patterns +@@ -11318,4 +11263,5 @@ + (include "thumb2.md") + ;; Neon patterns + (include "neon.md") +- ++;; Synchronization Primitives ++(include "sync.md") +--- a/src/gcc/config/arm/arm.opt ++++ b/src/gcc/config/arm/arm.opt +@@ -161,6 +161,10 @@ + Target Report Mask(NEON_VECTORIZE_QUAD) + Use Neon quad-word (rather than double-word) registers for vectorization + ++mlow-irq-latency ++Target Report Var(low_irq_latency) ++Try to reduce interrupt latency of the generated code ++ + mword-relocations + Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) + Only generate absolute relocations on word sized values. +--- a/src/gcc/config/arm/arm_neon.h ++++ b/src/gcc/config/arm/arm_neon.h +@@ -414,12 +414,6 @@ + return (int32x2_t)__builtin_neon_vaddv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vadd_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1); +-} +- + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) + vadd_f32 (float32x2_t __a, float32x2_t __b) + { +@@ -444,6 +438,12 @@ + return (uint32x2_t)__builtin_neon_vaddv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vadd_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vadd_u64 (uint64x1_t __a, uint64x1_t __b) + { +@@ -1368,12 +1368,6 @@ + return (int32x2_t)__builtin_neon_vsubv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vsub_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1); +-} +- + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) + vsub_f32 (float32x2_t __a, float32x2_t __b) + { +@@ -1398,6 +1392,12 @@ + return (uint32x2_t)__builtin_neon_vsubv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vsub_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vsub_u64 (uint64x1_t __a, uint64x1_t __b) + { +@@ -5808,12 +5808,6 @@ + return (int32x2_t)__builtin_neon_vget_lowv4si (__a); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vget_low_s64 (int64x2_t __a) +-{ +- return (int64x1_t)__builtin_neon_vget_lowv2di (__a); +-} +- + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) + vget_low_f32 (float32x4_t __a) + { +@@ -5838,12 +5832,6 @@ + return (uint32x2_t)__builtin_neon_vget_lowv4si ((int32x4_t) __a); + } + +-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +-vget_low_u64 (uint64x2_t __a) +-{ +- return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a); +-} +- + __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) + vget_low_p8 (poly8x16_t __a) + { +@@ -5856,6 +5844,18 @@ + return (poly16x4_t)__builtin_neon_vget_lowv8hi ((int16x8_t) __a); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vget_low_s64 (int64x2_t __a) ++{ ++ return (int64x1_t)__builtin_neon_vget_lowv2di (__a); ++} ++ ++__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) ++vget_low_u64 (uint64x2_t __a) ++{ ++ return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a); ++} ++ + __extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) + vcvt_s32_f32 (float32x2_t __a) + { +@@ -10386,12 +10386,6 @@ + return (int32x2_t)__builtin_neon_vandv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vand_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_vanddi (__a, __b, 1); +-} +- + __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) + vand_u8 (uint8x8_t __a, uint8x8_t __b) + { +@@ -10410,6 +10404,12 @@ + return (uint32x2_t)__builtin_neon_vandv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vand_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_vanddi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vand_u64 (uint64x1_t __a, uint64x1_t __b) + { +@@ -10482,12 +10482,6 @@ + return (int32x2_t)__builtin_neon_vorrv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vorr_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_vorrdi (__a, __b, 1); +-} +- + __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) + vorr_u8 (uint8x8_t __a, uint8x8_t __b) + { +@@ -10506,6 +10500,12 @@ + return (uint32x2_t)__builtin_neon_vorrv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vorr_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_vorrdi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vorr_u64 (uint64x1_t __a, uint64x1_t __b) + { +@@ -10578,12 +10578,6 @@ + return (int32x2_t)__builtin_neon_veorv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-veor_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_veordi (__a, __b, 1); +-} +- + __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) + veor_u8 (uint8x8_t __a, uint8x8_t __b) + { +@@ -10602,6 +10596,12 @@ + return (uint32x2_t)__builtin_neon_veorv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++veor_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_veordi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + veor_u64 (uint64x1_t __a, uint64x1_t __b) + { +@@ -10674,12 +10674,6 @@ + return (int32x2_t)__builtin_neon_vbicv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vbic_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_vbicdi (__a, __b, 1); +-} +- + __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) + vbic_u8 (uint8x8_t __a, uint8x8_t __b) + { +@@ -10698,6 +10692,12 @@ + return (uint32x2_t)__builtin_neon_vbicv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vbic_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_vbicdi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vbic_u64 (uint64x1_t __a, uint64x1_t __b) + { +@@ -10770,12 +10770,6 @@ + return (int32x2_t)__builtin_neon_vornv2si (__a, __b, 1); + } + +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vorn_s64 (int64x1_t __a, int64x1_t __b) +-{ +- return (int64x1_t)__builtin_neon_vorndi (__a, __b, 1); +-} +- + __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) + vorn_u8 (uint8x8_t __a, uint8x8_t __b) + { +@@ -10794,6 +10788,12 @@ + return (uint32x2_t)__builtin_neon_vornv2si ((int32x2_t) __a, (int32x2_t) __b, 0); + } + ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vorn_s64 (int64x1_t __a, int64x1_t __b) ++{ ++ return (int64x1_t)__builtin_neon_vorndi (__a, __b, 1); ++} ++ + __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) + vorn_u64 (uint64x1_t __a, uint64x1_t __b) + { +--- a/src/gcc/config/arm/bpabi.S ++++ b/src/gcc/config/arm/bpabi.S +@@ -116,16 +116,17 @@ + test_div_by_zero signed + + sub sp, sp, #8 +-#if defined(__thumb2__) ++/* Low latency and Thumb-2 do_push implementations can't push sp directly. */ ++#if defined(__thumb2__) || defined(__irq_low_latency__) + mov ip, sp +- push {ip, lr} ++ do_push (ip, lr) + #else +- do_push {sp, lr} ++ stmfd sp!, {sp, lr} + #endif + bl SYM(__gnu_ldivmod_helper) __PLT__ + ldr lr, [sp, #4] + add sp, sp, #8 +- do_pop {r2, r3} ++ do_pop (r2, r3) + RET + + #endif /* L_aeabi_ldivmod */ +@@ -136,16 +137,17 @@ + test_div_by_zero unsigned + + sub sp, sp, #8 +-#if defined(__thumb2__) ++/* Low latency and Thumb-2 do_push implementations can't push sp directly. */ ++#if defined(__thumb2__) || defined(__irq_low_latency__) + mov ip, sp +- push {ip, lr} ++ do_push (ip, lr) + #else +- do_push {sp, lr} ++ stmfd sp!, {sp, lr} + #endif + bl SYM(__gnu_uldivmod_helper) __PLT__ + ldr lr, [sp, #4] + add sp, sp, #8 +- do_pop {r2, r3} ++ do_pop (r2, r3) + RET + + #endif /* L_aeabi_divmod */ +--- a/src/gcc/config/arm/bpabi.h ++++ b/src/gcc/config/arm/bpabi.h +@@ -26,6 +26,7 @@ + #define TARGET_BPABI (TARGET_AAPCS_BASED) + + /* BPABI targets use EABI frame unwinding tables. */ ++#define DWARF2_UNWIND_INFO 0 + #define TARGET_UNWIND_INFO 1 + + /* Section 4.1 of the AAPCS requires the use of VFP format. */ +--- a/src/gcc/config/arm/constraints.md ++++ b/src/gcc/config/arm/constraints.md +@@ -29,9 +29,9 @@ + ;; in Thumb-1 state: I, J, K, L, M, N, O + + ;; The following multi-letter normal constraints have been used: +-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy ++;; in ARM/Thumb-2 state: Da, Db, Dc, Di, Dn, Dl, DL, Dv, Dy, Dz + ;; in Thumb-1 state: Pa, Pb +-;; in Thumb-2 state: Ps, Pt ++;; in Thumb-2 state: Ps, Pt, Pv + + ;; The following memory constraints have been used: + ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us +@@ -158,6 +158,11 @@ + (and (match_code "const_int") + (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7"))) + ++(define_constraint "Pv" ++ "@internal In Thumb-2 state a constant in the range -255 to 0" ++ (and (match_code "const_int") ++ (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0"))) ++ + (define_constraint "G" + "In ARM/Thumb-2 state a valid FPA immediate constant." + (and (match_code "const_double") +@@ -168,6 +173,12 @@ + (and (match_code "const_double") + (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)"))) + ++(define_constraint "Dz" ++ "@internal ++ In ARM/Thumb-2 state a vector of constant zeros." ++ (and (match_code "const_vector") ++ (match_test "TARGET_NEON && op == CONST0_RTX (mode)"))) ++ + (define_constraint "Da" + "@internal + In ARM/Thumb-2 state a const_int, const_double or const_vector that can +@@ -191,6 +202,13 @@ + (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4 + && !(optimize_size || arm_ld_sched)"))) + ++(define_constraint "Di" ++ "@internal ++ In ARM/Thumb-2 state a const_int or const_double where both the high ++ and low SImode words can be generated as immediates in 32-bit instructions." ++ (and (match_code "const_double,const_int") ++ (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)"))) ++ + (define_constraint "Dn" + "@internal + In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov +--- a/src/gcc/config/arm/cortex-a5.md ++++ b/src/gcc/config/arm/cortex-a5.md +@@ -0,0 +1,297 @@ ++;; ARM Cortex-A5 pipeline description ++;; Copyright (C) 2010 Free Software Foundation, Inc. ++;; Contributed by CodeSourcery. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_automaton "cortex_a5") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Functional units. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; The integer (ALU) pipeline. There are five DPU pipeline ++;; stages. However the decode/issue stages operate the same for all ++;; instructions, so do not model them. We only need to model the ++;; first execute stage because instructions always advance one stage ++;; per cycle in order. Only branch instructions may dual-issue, so a ++;; single unit covers all of the LS, ALU, MAC and FPU pipelines. ++ ++(define_cpu_unit "cortex_a5_ex1" "cortex_a5") ++ ++;; The branch pipeline. Branches can dual-issue with other instructions ++;; (except when those instructions take multiple cycles to issue). ++ ++(define_cpu_unit "cortex_a5_branch" "cortex_a5") ++ ++;; Pseudo-unit for blocking the multiply pipeline when a double-precision ++;; multiply is in progress. ++ ++(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5") ++ ++;; The floating-point add pipeline (ex1/f1 stage), used to model the usage ++;; of the add pipeline by fmac instructions, etc. ++ ++(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5") ++ ++;; Floating-point div/sqrt (long latency, out-of-order completion). ++ ++(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; ALU instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a5_alu" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "alu")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_alu_shift" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "alu_shift,alu_shift_reg")) ++ "cortex_a5_ex1") ++ ++;; Forwarding path for unshifted operands. ++ ++(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" ++ "cortex_a5_alu") ++ ++(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" ++ "cortex_a5_alu_shift" ++ "arm_no_early_alu_shift_dep") ++ ++;; The multiplier pipeline can forward results from wr stage only so ++;; there's no need to specify bypasses). ++ ++(define_insn_reservation "cortex_a5_mul" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "mult")) ++ "cortex_a5_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Load/store instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; Address-generation happens in the issue stage, which is one stage behind ++;; the ex1 stage (the first stage we care about for scheduling purposes). The ++;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr. ++ ++(define_insn_reservation "cortex_a5_load1" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "load_byte,load1")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_store1" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "store1")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_load2" 3 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "load2")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_store2" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "store2")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_load3" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "load3")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ ++ cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_store3" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "store3")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ ++ cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_load4" 5 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "load3")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ ++ cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_store4" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "store3")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ ++ cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Branches. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; Direct branches are the only instructions we can dual-issue (also IT and ++;; nop, but those aren't very interesting for scheduling). (The latency here ++;; is meant to represent when the branch actually takes place, but may not be ++;; entirely correct.) ++ ++(define_insn_reservation "cortex_a5_branch" 3 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "branch,call")) ++ "cortex_a5_branch") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Floating-point arithmetic. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a5_fpalu" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ ++ fcmps, fcmpd")) ++ "cortex_a5_ex1+cortex_a5_fpadd_pipe") ++ ++;; For fconsts and fconstd, 8-bit immediate data is passed directly from ++;; f1 to f3 (which I think reduces the latency by one cycle). ++ ++(define_insn_reservation "cortex_a5_fconst" 3 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fconsts,fconstd")) ++ "cortex_a5_ex1+cortex_a5_fpadd_pipe") ++ ++;; We should try not to attempt to issue a single-precision multiplication in ++;; the middle of a double-precision multiplication operation (the usage of ++;; cortex_a5_fpmul_pipe). ++ ++(define_insn_reservation "cortex_a5_fpmuls" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fmuls")) ++ "cortex_a5_ex1+cortex_a5_fpmul_pipe") ++ ++;; For single-precision multiply-accumulate, the add (accumulate) is issued ++;; whilst the multiply is in F4. The multiply result can then be forwarded ++;; from F5 to F1. The issue unit is only used once (when we first start ++;; processing the instruction), but the usage of the FP add pipeline could ++;; block other instructions attempting to use it simultaneously. We try to ++;; avoid that using cortex_a5_fpadd_pipe. ++ ++(define_insn_reservation "cortex_a5_fpmacs" 8 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fmacs")) ++ "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") ++ ++;; Non-multiply instructions can issue in the middle two instructions of a ++;; double-precision multiply. Note that it isn't entirely clear when a branch ++;; can dual-issue when a multi-cycle multiplication is in progress; we ignore ++;; that for now though. ++ ++(define_insn_reservation "cortex_a5_fpmuld" 7 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fmuld")) ++ "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ ++ cortex_a5_ex1+cortex_a5_fpmul_pipe") ++ ++(define_insn_reservation "cortex_a5_fpmacd" 11 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fmacd")) ++ "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ ++ cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Floating-point divide/square root instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; ??? Not sure if the 14 cycles taken for single-precision divide to complete ++;; includes the time taken for the special instruction used to collect the ++;; result to travel down the multiply pipeline, or not. Assuming so. (If ++;; that's wrong, the latency should be increased by a few cycles.) ++ ++;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the ++;; multiply pipeline to collect the divide/square-root result. ++ ++(define_insn_reservation "cortex_a5_fdivs" 14 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fdivs")) ++ "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13") ++ ++;; ??? Similarly for fdivd. ++ ++(define_insn_reservation "cortex_a5_fdivd" 29 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "fdivd")) ++ "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP to/from core transfers. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; FP loads take data from wr/rot/f3. ++ ++;; Core-to-VFP transfers use the multiply pipeline. ++ ++(define_insn_reservation "cortex_a5_r2f" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "r_2_f")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_f2r" 2 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_2_r")) ++ "cortex_a5_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP flag transfer. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++;; ??? The flag forwarding from fmstat to the ex2 stage of the second ++;; instruction is not modeled at present. ++ ++(define_insn_reservation "cortex_a5_f_flags" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_flag")) ++ "cortex_a5_ex1") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP load/store. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a5_f_loads" 4 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_loads")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_f_loadd" 5 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_load,f_loadd")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_f_stores" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_stores")) ++ "cortex_a5_ex1") ++ ++(define_insn_reservation "cortex_a5_f_stored" 0 ++ (and (eq_attr "tune" "cortexa5") ++ (eq_attr "type" "f_store,f_stored")) ++ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") ++ ++;; Load-to-use for floating-point values has a penalty of one cycle, ++;; i.e. a latency of two. ++ ++(define_bypass 2 "cortex_a5_f_loads" ++ "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ ++ cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ ++ cortex_a5_f2r") ++ ++(define_bypass 3 "cortex_a5_f_loadd" ++ "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ ++ cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ ++ cortex_a5_f2r") +--- a/src/gcc/config/arm/cortex-a8-neon.md ++++ b/src/gcc/config/arm/cortex-a8-neon.md +@@ -182,12 +182,12 @@ + + ;; NEON -> core transfers. + +-(define_insn_reservation "neon_mrc" 20 ++(define_insn_reservation "cortex_a8_neon_mrc" 20 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mrc")) + "cortex_a8_neon_ls") + +-(define_insn_reservation "neon_mrrc" 21 ++(define_insn_reservation "cortex_a8_neon_mrrc" 21 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mrrc")) + "cortex_a8_neon_ls_2") +@@ -196,48 +196,48 @@ + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N3. +-(define_insn_reservation "neon_int_1" 3 ++(define_insn_reservation "cortex_a8_neon_int_1" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_int_1")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their (D|Q)m operands at N1, + ;; their (D|Q)n operands at N2, and produce a result at N3. +-(define_insn_reservation "neon_int_2" 3 ++(define_insn_reservation "cortex_a8_neon_int_2" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_int_2")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N3. +-(define_insn_reservation "neon_int_3" 3 ++(define_insn_reservation "cortex_a8_neon_int_3" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_int_3")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N4. +-(define_insn_reservation "neon_int_4" 4 ++(define_insn_reservation "cortex_a8_neon_int_4" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_int_4")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their (D|Q)m operands at N1, + ;; their (D|Q)n operands at N2, and produce a result at N4. +-(define_insn_reservation "neon_int_5" 4 ++(define_insn_reservation "cortex_a8_neon_int_5" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_int_5")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N4. +-(define_insn_reservation "neon_vqneg_vqabs" 4 ++(define_insn_reservation "cortex_a8_neon_vqneg_vqabs" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vqneg_vqabs")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation produce a result at N3. +-(define_insn_reservation "neon_vmov" 3 ++(define_insn_reservation "cortex_a8_neon_vmov" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vmov")) + "cortex_a8_neon_dp") +@@ -245,7 +245,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N6. +-(define_insn_reservation "neon_vaba" 6 ++(define_insn_reservation "cortex_a8_neon_vaba" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vaba")) + "cortex_a8_neon_dp") +@@ -253,35 +253,35 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N6 on cycle 2. +-(define_insn_reservation "neon_vaba_qqq" 7 ++(define_insn_reservation "cortex_a8_neon_vaba_qqq" 7 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vaba_qqq")) + "cortex_a8_neon_dp_2") + + ;; Instructions using this reservation read their (D|Q)m operands at N1, + ;; their (D|Q)d operands at N3, and produce a result at N6. +-(define_insn_reservation "neon_vsma" 6 ++(define_insn_reservation "cortex_a8_neon_vsma" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vsma")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N6. +-(define_insn_reservation "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 ++(define_insn_reservation "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N6 on cycle 2. +-(define_insn_reservation "neon_mul_qqq_8_16_32_ddd_32" 7 ++(define_insn_reservation "cortex_a8_neon_mul_qqq_8_16_32_ddd_32" 7 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32")) + "cortex_a8_neon_dp_2") + + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2. +-(define_insn_reservation "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 ++(define_insn_reservation "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) + "cortex_a8_neon_dp_2") +@@ -289,7 +289,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and + ;; produce a result at N6. +-(define_insn_reservation "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 ++(define_insn_reservation "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) + "cortex_a8_neon_dp") +@@ -297,7 +297,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and + ;; produce a result at N6 on cycle 2. +-(define_insn_reservation "neon_mla_qqq_8_16" 7 ++(define_insn_reservation "cortex_a8_neon_mla_qqq_8_16" 7 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mla_qqq_8_16")) + "cortex_a8_neon_dp_2") +@@ -305,7 +305,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N6 on cycle 2. +-(define_insn_reservation "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 ++(define_insn_reservation "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) + "cortex_a8_neon_dp_2") +@@ -313,21 +313,21 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N6 on cycle 4. +-(define_insn_reservation "neon_mla_qqq_32_qqd_32_scalar" 9 ++(define_insn_reservation "cortex_a8_neon_mla_qqq_32_qqd_32_scalar" 9 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar")) + "cortex_a8_neon_dp_4") + + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, and produce a result at N6. +-(define_insn_reservation "neon_mul_ddd_16_scalar_32_16_long_scalar" 6 ++(define_insn_reservation "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4. +-(define_insn_reservation "neon_mul_qqd_32_scalar" 9 ++(define_insn_reservation "cortex_a8_neon_mul_qqd_32_scalar" 9 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mul_qqd_32_scalar")) + "cortex_a8_neon_dp_4") +@@ -335,84 +335,84 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N6. +-(define_insn_reservation "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 ++(define_insn_reservation "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N3. +-(define_insn_reservation "neon_shift_1" 3 ++(define_insn_reservation "cortex_a8_neon_shift_1" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_shift_1")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N4. +-(define_insn_reservation "neon_shift_2" 4 ++(define_insn_reservation "cortex_a8_neon_shift_2" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_shift_2")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N3 on cycle 2. +-(define_insn_reservation "neon_shift_3" 4 ++(define_insn_reservation "cortex_a8_neon_shift_3" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_shift_3")) + "cortex_a8_neon_dp_2") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N1. +-(define_insn_reservation "neon_vshl_ddd" 1 ++(define_insn_reservation "cortex_a8_neon_vshl_ddd" 1 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vshl_ddd")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N4 on cycle 2. +-(define_insn_reservation "neon_vqshl_vrshl_vqrshl_qqq" 5 ++(define_insn_reservation "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq" 5 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq")) + "cortex_a8_neon_dp_2") + + ;; Instructions using this reservation read their (D|Q)m operands at N1, + ;; their (D|Q)d operands at N3, and produce a result at N6. +-(define_insn_reservation "neon_vsra_vrsra" 6 ++(define_insn_reservation "cortex_a8_neon_vsra_vrsra" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vsra_vrsra")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N5. +-(define_insn_reservation "neon_fp_vadd_ddd_vabs_dd" 5 ++(define_insn_reservation "cortex_a8_neon_fp_vadd_ddd_vabs_dd" 5 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")) + "cortex_a8_neon_fadd") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N5 on cycle 2. +-(define_insn_reservation "neon_fp_vadd_qqq_vabs_qq" 6 ++(define_insn_reservation "cortex_a8_neon_fp_vadd_qqq_vabs_qq" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq")) + "cortex_a8_neon_fadd_2") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N5. +-(define_insn_reservation "neon_fp_vsum" 5 ++(define_insn_reservation "cortex_a8_neon_fp_vsum" 5 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vsum")) + "cortex_a8_neon_fadd") + + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, and produce a result at N5. +-(define_insn_reservation "neon_fp_vmul_ddd" 5 ++(define_insn_reservation "cortex_a8_neon_fp_vmul_ddd" 5 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vmul_ddd")) + "cortex_a8_neon_dp") + + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2. +-(define_insn_reservation "neon_fp_vmul_qqd" 6 ++(define_insn_reservation "cortex_a8_neon_fp_vmul_qqd" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vmul_qqd")) + "cortex_a8_neon_dp_2") +@@ -420,7 +420,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and + ;; produce a result at N9. +-(define_insn_reservation "neon_fp_vmla_ddd" 9 ++(define_insn_reservation "cortex_a8_neon_fp_vmla_ddd" 9 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vmla_ddd")) + "cortex_a8_neon_fmul_then_fadd") +@@ -428,7 +428,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and + ;; produce a result at N9 on cycle 2. +-(define_insn_reservation "neon_fp_vmla_qqq" 10 ++(define_insn_reservation "cortex_a8_neon_fp_vmla_qqq" 10 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vmla_qqq")) + "cortex_a8_neon_fmul_then_fadd_2") +@@ -436,7 +436,7 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N9. +-(define_insn_reservation "neon_fp_vmla_ddd_scalar" 9 ++(define_insn_reservation "cortex_a8_neon_fp_vmla_ddd_scalar" 9 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar")) + "cortex_a8_neon_fmul_then_fadd") +@@ -444,869 +444,869 @@ + ;; Instructions using this reservation read their (D|Q)n operands at N2, + ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and + ;; produce a result at N9 on cycle 2. +-(define_insn_reservation "neon_fp_vmla_qqq_scalar" 10 ++(define_insn_reservation "cortex_a8_neon_fp_vmla_qqq_scalar" 10 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar")) + "cortex_a8_neon_fmul_then_fadd_2") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N9. +-(define_insn_reservation "neon_fp_vrecps_vrsqrts_ddd" 9 ++(define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_ddd" 9 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd")) + "cortex_a8_neon_fmul_then_fadd") + + ;; Instructions using this reservation read their source operands at N2, and + ;; produce a result at N9 on cycle 2. +-(define_insn_reservation "neon_fp_vrecps_vrsqrts_qqq" 10 ++(define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_qqq" 10 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq")) + "cortex_a8_neon_fmul_then_fadd_2") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N2. +-(define_insn_reservation "neon_bp_simple" 2 ++(define_insn_reservation "cortex_a8_neon_bp_simple" 2 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_bp_simple")) + "cortex_a8_neon_perm") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N2 on cycle 2. +-(define_insn_reservation "neon_bp_2cycle" 3 ++(define_insn_reservation "cortex_a8_neon_bp_2cycle" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_bp_2cycle")) + "cortex_a8_neon_perm_2") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N2 on cycle 3. +-(define_insn_reservation "neon_bp_3cycle" 4 ++(define_insn_reservation "cortex_a8_neon_bp_3cycle" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_bp_3cycle")) + "cortex_a8_neon_perm_3") + + ;; Instructions using this reservation produce a result at N1. +-(define_insn_reservation "neon_ldr" 1 ++(define_insn_reservation "cortex_a8_neon_ldr" 1 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_ldr")) + "cortex_a8_neon_ls") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_str" 0 ++(define_insn_reservation "cortex_a8_neon_str" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_str")) + "cortex_a8_neon_ls") + + ;; Instructions using this reservation produce a result at N1 on cycle 2. +-(define_insn_reservation "neon_vld1_1_2_regs" 2 ++(define_insn_reservation "cortex_a8_neon_vld1_1_2_regs" 2 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld1_1_2_regs")) + "cortex_a8_neon_ls_2") + + ;; Instructions using this reservation produce a result at N1 on cycle 3. +-(define_insn_reservation "neon_vld1_3_4_regs" 3 ++(define_insn_reservation "cortex_a8_neon_vld1_3_4_regs" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld1_3_4_regs")) + "cortex_a8_neon_ls_3") + + ;; Instructions using this reservation produce a result at N2 on cycle 2. +-(define_insn_reservation "neon_vld2_2_regs_vld1_vld2_all_lanes" 3 ++(define_insn_reservation "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) + "cortex_a8_neon_ls_2") + + ;; Instructions using this reservation produce a result at N2 on cycle 3. +-(define_insn_reservation "neon_vld2_4_regs" 4 ++(define_insn_reservation "cortex_a8_neon_vld2_4_regs" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld2_4_regs")) + "cortex_a8_neon_ls_3") + + ;; Instructions using this reservation produce a result at N2 on cycle 4. +-(define_insn_reservation "neon_vld3_vld4" 5 ++(define_insn_reservation "cortex_a8_neon_vld3_vld4" 5 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld3_vld4")) + "cortex_a8_neon_ls_4") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_vst1_1_2_regs_vst2_2_regs" 0 ++(define_insn_reservation "cortex_a8_neon_vst1_1_2_regs_vst2_2_regs" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")) + "cortex_a8_neon_ls_2") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_vst1_3_4_regs" 0 ++(define_insn_reservation "cortex_a8_neon_vst1_3_4_regs" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vst1_3_4_regs")) + "cortex_a8_neon_ls_3") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_vst2_4_regs_vst3_vst4" 0 ++(define_insn_reservation "cortex_a8_neon_vst2_4_regs_vst3_vst4" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")) + "cortex_a8_neon_ls_4") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_vst3_vst4" 0 ++(define_insn_reservation "cortex_a8_neon_vst3_vst4" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vst3_vst4")) + "cortex_a8_neon_ls_4") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N2 on cycle 3. +-(define_insn_reservation "neon_vld1_vld2_lane" 4 ++(define_insn_reservation "cortex_a8_neon_vld1_vld2_lane" 4 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld1_vld2_lane")) + "cortex_a8_neon_ls_3") + + ;; Instructions using this reservation read their source operands at N1, and + ;; produce a result at N2 on cycle 5. +-(define_insn_reservation "neon_vld3_vld4_lane" 6 ++(define_insn_reservation "cortex_a8_neon_vld3_vld4_lane" 6 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld3_vld4_lane")) + "cortex_a8_neon_ls_5") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_vst1_vst2_lane" 0 ++(define_insn_reservation "cortex_a8_neon_vst1_vst2_lane" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vst1_vst2_lane")) + "cortex_a8_neon_ls_2") + + ;; Instructions using this reservation read their source operands at N1. +-(define_insn_reservation "neon_vst3_vst4_lane" 0 ++(define_insn_reservation "cortex_a8_neon_vst3_vst4_lane" 0 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vst3_vst4_lane")) + "cortex_a8_neon_ls_3") + + ;; Instructions using this reservation produce a result at N2 on cycle 2. +-(define_insn_reservation "neon_vld3_vld4_all_lanes" 3 ++(define_insn_reservation "cortex_a8_neon_vld3_vld4_all_lanes" 3 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_vld3_vld4_all_lanes")) + "cortex_a8_neon_ls_3") + + ;; Instructions using this reservation produce a result at N2. +-(define_insn_reservation "neon_mcr" 2 ++(define_insn_reservation "cortex_a8_neon_mcr" 2 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mcr")) + "cortex_a8_neon_perm") + + ;; Instructions using this reservation produce a result at N2. +-(define_insn_reservation "neon_mcr_2_mcrr" 2 ++(define_insn_reservation "cortex_a8_neon_mcr_2_mcrr" 2 + (and (eq_attr "tune" "cortexa8") + (eq_attr "neon_type" "neon_mcr_2_mcrr")) + "cortex_a8_neon_perm_2") + + ;; Exceptions to the default latencies. + +-(define_bypass 1 "neon_mcr_2_mcrr" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 1 "neon_mcr" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_vld3_vld4_all_lanes" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_vld3_vld4_lane" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_vld1_vld2_lane" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 4 "neon_vld3_vld4" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_vld2_4_regs" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_vld2_2_regs_vld1_vld2_all_lanes" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_vld1_3_4_regs" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 1 "neon_vld1_1_2_regs" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 0 "neon_ldr" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_bp_3cycle" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_bp_2cycle" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 1 "neon_bp_simple" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 9 "neon_fp_vrecps_vrsqrts_qqq" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 8 "neon_fp_vrecps_vrsqrts_ddd" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 9 "neon_fp_vmla_qqq_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 8 "neon_fp_vmla_ddd_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 9 "neon_fp_vmla_qqq" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 8 "neon_fp_vmla_ddd" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_fp_vmul_qqd" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 4 "neon_fp_vmul_ddd" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 4 "neon_fp_vsum" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_fp_vadd_qqq_vabs_qq" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 4 "neon_fp_vadd_ddd_vabs_dd" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_vsra_vrsra" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 4 "neon_vqshl_vrshl_vqrshl_qqq" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 0 "neon_vshl_ddd" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_shift_3" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_shift_2" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_shift_1" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 8 "neon_mul_qqd_32_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_mul_ddd_16_scalar_32_16_long_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 8 "neon_mla_qqq_32_qqd_32_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 6 "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 6 "neon_mla_qqq_8_16" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 6 "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 6 "neon_mul_qqq_8_16_32_ddd_32" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_vsma" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 6 "neon_vaba_qqq" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 5 "neon_vaba" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_vmov" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_vqneg_vqabs" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_int_5" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 3 "neon_int_4" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_int_3" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_int_2" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") +- +-(define_bypass 2 "neon_int_1" +- "neon_int_1,\ +- neon_int_4,\ +- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mul_qqq_8_16_32_ddd_32,\ +- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ +- neon_mla_qqq_8_16,\ +- neon_fp_vadd_ddd_vabs_dd,\ +- neon_fp_vadd_qqq_vabs_qq,\ +- neon_fp_vmla_ddd,\ +- neon_fp_vmla_qqq,\ +- neon_fp_vrecps_vrsqrts_ddd,\ +- neon_fp_vrecps_vrsqrts_qqq") ++(define_bypass 1 "cortex_a8_neon_mcr_2_mcrr" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 1 "cortex_a8_neon_mcr" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_vld3_vld4_all_lanes" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_vld3_vld4_lane" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_vld1_vld2_lane" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a8_neon_vld3_vld4" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_vld2_4_regs" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_vld1_3_4_regs" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 1 "cortex_a8_neon_vld1_1_2_regs" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 0 "cortex_a8_neon_ldr" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_bp_3cycle" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_bp_2cycle" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 1 "cortex_a8_neon_bp_simple" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a8_neon_fp_vrecps_vrsqrts_qqq" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a8_neon_fp_vrecps_vrsqrts_ddd" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a8_neon_fp_vmla_qqq_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a8_neon_fp_vmla_ddd_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a8_neon_fp_vmla_qqq" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a8_neon_fp_vmla_ddd" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_fp_vmul_qqd" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a8_neon_fp_vmul_ddd" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a8_neon_fp_vsum" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_fp_vadd_qqq_vabs_qq" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a8_neon_fp_vadd_ddd_vabs_dd" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_vsra_vrsra" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 0 "cortex_a8_neon_vshl_ddd" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_shift_3" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_shift_2" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_shift_1" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a8_neon_mul_qqd_32_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a8_neon_mla_qqq_32_qqd_32_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a8_neon_mla_qqq_8_16" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a8_neon_mul_qqq_8_16_32_ddd_32" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_vsma" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a8_neon_vaba_qqq" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a8_neon_vaba" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_vmov" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_vqneg_vqabs" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_int_5" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a8_neon_int_4" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_int_3" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_int_2" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a8_neon_int_1" ++ "cortex_a8_neon_int_1,\ ++ cortex_a8_neon_int_4,\ ++ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a8_neon_mla_qqq_8_16,\ ++ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a8_neon_fp_vmla_ddd,\ ++ cortex_a8_neon_fp_vmla_qqq,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a8_neon_fp_vrecps_vrsqrts_qqq") + +--- a/src/gcc/config/arm/cortex-a9-neon.md ++++ b/src/gcc/config/arm/cortex-a9-neon.md +@@ -0,0 +1,1237 @@ ++;; ARM Cortex-A9 pipeline description ++;; Copyright (C) 2010 Free Software Foundation, Inc. ++;; ++;; Neon pipeline description contributed by ARM Ltd. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++ ++(define_automaton "cortex_a9_neon") ++ ++;; Only one instruction can be issued per cycle. ++(define_cpu_unit "cortex_a9_neon_issue_perm" "cortex_a9_neon") ++ ++;; Only one data-processing instruction can be issued per cycle. ++(define_cpu_unit "cortex_a9_neon_issue_dp" "cortex_a9_neon") ++ ++;; We need a special mutual exclusion (to be used in addition to ++;; cortex_a9_neon_issue_dp) for the case when an instruction such as ++;; vmla.f is forwarded from E5 of the floating-point multiply pipeline to ++;; E2 of the floating-point add pipeline. On the cycle previous to that ++;; forward we must prevent issue of any instruction to the floating-point ++;; add pipeline, but still allow issue of a data-processing instruction ++;; to any of the other pipelines. ++(define_cpu_unit "cortex_a9_neon_issue_fadd" "cortex_a9_neon") ++(define_cpu_unit "cortex_a9_neon_mcr" "cortex_a9_neon") ++ ++ ++;; Patterns of reservation. ++;; We model the NEON issue units as running in parallel with the core ones. ++;; We assume that multi-cycle NEON instructions get decomposed into ++;; micro-ops as they are issued into the NEON pipeline. ++ ++(define_reservation "cortex_a9_neon_dp" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp") ++(define_reservation "cortex_a9_neon_dp_2" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ ++ cortex_a9_neon_issue_dp") ++(define_reservation "cortex_a9_neon_dp_4" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ ++ cortex_a9_neon_issue_dp + cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp + cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp") ++ ++(define_reservation "cortex_a9_neon_fadd" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp + \ ++ cortex_a9_neon_issue_fadd") ++(define_reservation "cortex_a9_neon_fadd_2" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ ++ cortex_a9_neon_issue_fadd,\ ++ cortex_a9_neon_issue_dp") ++ ++(define_reservation "cortex_a9_neon_perm" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm") ++(define_reservation "cortex_a9_neon_perm_2" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm, \ ++ cortex_a9_neon_issue_perm") ++(define_reservation "cortex_a9_neon_perm_3" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_perm") ++ ++(define_reservation "cortex_a9_neon_ls" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm+cortex_a9_ls") ++(define_reservation "cortex_a9_neon_ls_2" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_perm") ++(define_reservation "cortex_a9_neon_ls_3" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_perm") ++(define_reservation "cortex_a9_neon_ls_4" ++ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_perm") ++(define_reservation "cortex_a9_neon_ls_5" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ ++ cortex_a9_neon_issue_perm") ++ ++(define_reservation "cortex_a9_neon_fmul_then_fadd" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ ++ nothing*3,\ ++ cortex_a9_neon_issue_fadd") ++(define_reservation "cortex_a9_neon_fmul_then_fadd_2" ++ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ ++ cortex_a9_neon_issue_dp,\ ++ nothing*2,\ ++ cortex_a9_neon_issue_fadd,\ ++ cortex_a9_neon_issue_fadd") ++ ++ ++;; NEON -> core transfers. ++(define_insn_reservation "ca9_neon_mrc" 1 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mrc")) ++ "ca9_issue_vfp_neon + cortex_a9_neon_mcr") ++ ++(define_insn_reservation "ca9_neon_mrrc" 1 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mrrc")) ++ "ca9_issue_vfp_neon + cortex_a9_neon_mcr") ++ ++;; The remainder of this file is auto-generated by neon-schedgen. ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N3. ++(define_insn_reservation "cortex_a9_neon_int_1" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_int_1")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)m operands at N1, ++;; their (D|Q)n operands at N2, and produce a result at N3. ++(define_insn_reservation "cortex_a9_neon_int_2" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_int_2")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N3. ++(define_insn_reservation "cortex_a9_neon_int_3" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_int_3")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N4. ++(define_insn_reservation "cortex_a9_neon_int_4" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_int_4")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)m operands at N1, ++;; their (D|Q)n operands at N2, and produce a result at N4. ++(define_insn_reservation "cortex_a9_neon_int_5" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_int_5")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N4. ++(define_insn_reservation "cortex_a9_neon_vqneg_vqabs" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vqneg_vqabs")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation produce a result at N3. ++(define_insn_reservation "cortex_a9_neon_vmov" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vmov")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_vaba" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vaba")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N6 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_vaba_qqq" 7 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vaba_qqq")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)m operands at N1, ++;; their (D|Q)d operands at N3, and produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_vsma" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vsma")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N6 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_mul_qqq_8_16_32_ddd_32" 7 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and ++;; produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and ++;; produce a result at N6 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_mla_qqq_8_16" 7 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mla_qqq_8_16")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N6 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N6 on cycle 4. ++(define_insn_reservation "cortex_a9_neon_mla_qqq_32_qqd_32_scalar" 9 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar")) ++ "cortex_a9_neon_dp_4") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, and produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4. ++(define_insn_reservation "cortex_a9_neon_mul_qqd_32_scalar" 9 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mul_qqd_32_scalar")) ++ "cortex_a9_neon_dp_4") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N3. ++(define_insn_reservation "cortex_a9_neon_shift_1" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_shift_1")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N4. ++(define_insn_reservation "cortex_a9_neon_shift_2" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_shift_2")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N3 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_shift_3" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_shift_3")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N1. ++(define_insn_reservation "cortex_a9_neon_vshl_ddd" 1 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vshl_ddd")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N4 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_vqshl_vrshl_vqrshl_qqq" 5 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)m operands at N1, ++;; their (D|Q)d operands at N3, and produce a result at N6. ++(define_insn_reservation "cortex_a9_neon_vsra_vrsra" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vsra_vrsra")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N5. ++(define_insn_reservation "cortex_a9_neon_fp_vadd_ddd_vabs_dd" 5 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")) ++ "cortex_a9_neon_fadd") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N5 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_fp_vadd_qqq_vabs_qq" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq")) ++ "cortex_a9_neon_fadd_2") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N5. ++(define_insn_reservation "cortex_a9_neon_fp_vsum" 5 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vsum")) ++ "cortex_a9_neon_fadd") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, and produce a result at N5. ++(define_insn_reservation "cortex_a9_neon_fp_vmul_ddd" 5 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vmul_ddd")) ++ "cortex_a9_neon_dp") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_fp_vmul_qqd" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vmul_qqd")) ++ "cortex_a9_neon_dp_2") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and ++;; produce a result at N9. ++(define_insn_reservation "cortex_a9_neon_fp_vmla_ddd" 9 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vmla_ddd")) ++ "cortex_a9_neon_fmul_then_fadd") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and ++;; produce a result at N9 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_fp_vmla_qqq" 10 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vmla_qqq")) ++ "cortex_a9_neon_fmul_then_fadd_2") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N9. ++(define_insn_reservation "cortex_a9_neon_fp_vmla_ddd_scalar" 9 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar")) ++ "cortex_a9_neon_fmul_then_fadd") ++ ++;; Instructions using this reservation read their (D|Q)n operands at N2, ++;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and ++;; produce a result at N9 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_fp_vmla_qqq_scalar" 10 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar")) ++ "cortex_a9_neon_fmul_then_fadd_2") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N9. ++(define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_ddd" 9 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd")) ++ "cortex_a9_neon_fmul_then_fadd") ++ ++;; Instructions using this reservation read their source operands at N2, and ++;; produce a result at N9 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_qqq" 10 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq")) ++ "cortex_a9_neon_fmul_then_fadd_2") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N2. ++(define_insn_reservation "cortex_a9_neon_bp_simple" 2 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_bp_simple")) ++ "cortex_a9_neon_perm") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N2 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_bp_2cycle" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_bp_2cycle")) ++ "cortex_a9_neon_perm_2") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N2 on cycle 3. ++(define_insn_reservation "cortex_a9_neon_bp_3cycle" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_bp_3cycle")) ++ "cortex_a9_neon_perm_3") ++ ++;; Instructions using this reservation produce a result at N1. ++(define_insn_reservation "cortex_a9_neon_ldr" 1 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_ldr")) ++ "cortex_a9_neon_ls") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_str" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_str")) ++ "cortex_a9_neon_ls") ++ ++;; Instructions using this reservation produce a result at N1 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_vld1_1_2_regs" 2 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld1_1_2_regs")) ++ "cortex_a9_neon_ls_2") ++ ++;; Instructions using this reservation produce a result at N1 on cycle 3. ++(define_insn_reservation "cortex_a9_neon_vld1_3_4_regs" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld1_3_4_regs")) ++ "cortex_a9_neon_ls_3") ++ ++;; Instructions using this reservation produce a result at N2 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) ++ "cortex_a9_neon_ls_2") ++ ++;; Instructions using this reservation produce a result at N2 on cycle 3. ++(define_insn_reservation "cortex_a9_neon_vld2_4_regs" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld2_4_regs")) ++ "cortex_a9_neon_ls_3") ++ ++;; Instructions using this reservation produce a result at N2 on cycle 4. ++(define_insn_reservation "cortex_a9_neon_vld3_vld4" 5 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld3_vld4")) ++ "cortex_a9_neon_ls_4") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_vst1_1_2_regs_vst2_2_regs" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")) ++ "cortex_a9_neon_ls_2") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_vst1_3_4_regs" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vst1_3_4_regs")) ++ "cortex_a9_neon_ls_3") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_vst2_4_regs_vst3_vst4" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")) ++ "cortex_a9_neon_ls_4") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_vst3_vst4" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vst3_vst4")) ++ "cortex_a9_neon_ls_4") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N2 on cycle 3. ++(define_insn_reservation "cortex_a9_neon_vld1_vld2_lane" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld1_vld2_lane")) ++ "cortex_a9_neon_ls_3") ++ ++;; Instructions using this reservation read their source operands at N1, and ++;; produce a result at N2 on cycle 5. ++(define_insn_reservation "cortex_a9_neon_vld3_vld4_lane" 6 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld3_vld4_lane")) ++ "cortex_a9_neon_ls_5") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_vst1_vst2_lane" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vst1_vst2_lane")) ++ "cortex_a9_neon_ls_2") ++ ++;; Instructions using this reservation read their source operands at N1. ++(define_insn_reservation "cortex_a9_neon_vst3_vst4_lane" 0 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vst3_vst4_lane")) ++ "cortex_a9_neon_ls_3") ++ ++;; Instructions using this reservation produce a result at N2 on cycle 2. ++(define_insn_reservation "cortex_a9_neon_vld3_vld4_all_lanes" 3 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_vld3_vld4_all_lanes")) ++ "cortex_a9_neon_ls_3") ++ ++;; Instructions using this reservation produce a result at N2. ++(define_insn_reservation "cortex_a9_neon_mcr" 2 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mcr")) ++ "cortex_a9_neon_perm") ++ ++;; Instructions using this reservation produce a result at N2. ++(define_insn_reservation "cortex_a9_neon_mcr_2_mcrr" 2 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "neon_type" "neon_mcr_2_mcrr")) ++ "cortex_a9_neon_perm_2") ++ ++;; Exceptions to the default latencies. ++ ++(define_bypass 1 "cortex_a9_neon_mcr_2_mcrr" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 1 "cortex_a9_neon_mcr" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_vld3_vld4_all_lanes" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_vld3_vld4_lane" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_vld1_vld2_lane" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a9_neon_vld3_vld4" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_vld2_4_regs" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_vld1_3_4_regs" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 1 "cortex_a9_neon_vld1_1_2_regs" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 0 "cortex_a9_neon_ldr" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_bp_3cycle" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_bp_2cycle" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 1 "cortex_a9_neon_bp_simple" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a9_neon_fp_vrecps_vrsqrts_qqq" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a9_neon_fp_vrecps_vrsqrts_ddd" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a9_neon_fp_vmla_qqq_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a9_neon_fp_vmla_ddd_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 9 "cortex_a9_neon_fp_vmla_qqq" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a9_neon_fp_vmla_ddd" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_fp_vmul_qqd" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a9_neon_fp_vmul_ddd" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a9_neon_fp_vsum" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_fp_vadd_qqq_vabs_qq" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a9_neon_fp_vadd_ddd_vabs_dd" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_vsra_vrsra" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 4 "cortex_a9_neon_vqshl_vrshl_vqrshl_qqq" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 0 "cortex_a9_neon_vshl_ddd" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_shift_3" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_shift_2" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_shift_1" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a9_neon_mul_qqd_32_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 8 "cortex_a9_neon_mla_qqq_32_qqd_32_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a9_neon_mla_qqq_8_16" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a9_neon_mul_qqq_8_16_32_ddd_32" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_vsma" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 6 "cortex_a9_neon_vaba_qqq" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 5 "cortex_a9_neon_vaba" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_vmov" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_vqneg_vqabs" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_int_5" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 3 "cortex_a9_neon_int_4" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_int_3" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_int_2" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ ++(define_bypass 2 "cortex_a9_neon_int_1" ++ "cortex_a9_neon_int_1,\ ++ cortex_a9_neon_int_4,\ ++ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ ++ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ ++ cortex_a9_neon_mla_qqq_8_16,\ ++ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ ++ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ ++ cortex_a9_neon_fp_vmla_ddd,\ ++ cortex_a9_neon_fp_vmla_qqq,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ ++ cortex_a9_neon_fp_vrecps_vrsqrts_qqq") ++ +--- a/src/gcc/config/arm/cortex-a9.md ++++ b/src/gcc/config/arm/cortex-a9.md +@@ -2,8 +2,10 @@ + ;; Copyright (C) 2008, 2009 Free Software Foundation, Inc. + ;; Originally written by CodeSourcery for VFP. + ;; +-;; Integer core pipeline description contributed by ARM Ltd. +-;; ++;; Rewritten by Ramana Radhakrishnan ++;; Integer Pipeline description contributed by ARM Ltd. ++;; VFP Pipeline description rewritten and contributed by ARM Ltd. ++ + ;; This file is part of GCC. + ;; + ;; GCC is free software; you can redistribute it and/or modify it +@@ -22,28 +24,27 @@ + + (define_automaton "cortex_a9") + +-;; The Cortex-A9 integer core is modelled as a dual issue pipeline that has ++;; The Cortex-A9 core is modelled as a dual issue pipeline that has + ;; the following components. + ;; 1. 1 Load Store Pipeline. + ;; 2. P0 / main pipeline for data processing instructions. + ;; 3. P1 / Dual pipeline for Data processing instructions. + ;; 4. MAC pipeline for multiply as well as multiply + ;; and accumulate instructions. +-;; 5. 1 VFP / Neon pipeline. +-;; The Load/Store and VFP/Neon pipeline are multiplexed. ++;; 5. 1 VFP and an optional Neon unit. ++;; The Load/Store, VFP and Neon issue pipeline are multiplexed. + ;; The P0 / main pipeline and M1 stage of the MAC pipeline are + ;; multiplexed. + ;; The P1 / dual pipeline and M2 stage of the MAC pipeline are + ;; multiplexed. +-;; There are only 4 register read ports and hence at any point of ++;; There are only 4 integer register read ports and hence at any point of + ;; time we can't have issue down the E1 and the E2 ports unless + ;; of course there are bypass paths that get exercised. + ;; Both P0 and P1 have 2 stages E1 and E2. + ;; Data processing instructions issue to E1 or E2 depending on + ;; whether they have an early shift or not. + +- +-(define_cpu_unit "cortex_a9_vfp, cortex_a9_ls" "cortex_a9") ++(define_cpu_unit "ca9_issue_vfp_neon, cortex_a9_ls" "cortex_a9") + (define_cpu_unit "cortex_a9_p0_e1, cortex_a9_p0_e2" "cortex_a9") + (define_cpu_unit "cortex_a9_p1_e1, cortex_a9_p1_e2" "cortex_a9") + (define_cpu_unit "cortex_a9_p0_wb, cortex_a9_p1_wb" "cortex_a9") +@@ -71,20 +72,18 @@ + + ;; Issue at the same time along the load store pipeline and + ;; the VFP / Neon pipeline is not possible. +-;; FIXME:: At some point we need to model the issue +-;; of the load store and the vfp being shared rather than anything else. +- +-(exclusion_set "cortex_a9_ls" "cortex_a9_vfp") +- ++(exclusion_set "cortex_a9_ls" "ca9_issue_vfp_neon") + + ;; Default data processing instruction without any shift + ;; The only exception to this is the mov instruction + ;; which can go down E2 without any problem. + (define_insn_reservation "cortex_a9_dp" 2 + (and (eq_attr "tune" "cortexa9") +- (ior (eq_attr "type" "alu") +- (and (eq_attr "type" "alu_shift_reg, alu_shift") +- (eq_attr "insn" "mov")))) ++ (ior (and (eq_attr "type" "alu") ++ (eq_attr "neon_type" "none")) ++ (and (and (eq_attr "type" "alu_shift_reg, alu_shift") ++ (eq_attr "insn" "mov")) ++ (eq_attr "neon_type" "none")))) + "cortex_a9_p0_default|cortex_a9_p1_default") + + ;; An instruction using the shifter will go down E1. +@@ -101,18 +100,13 @@ + + (define_insn_reservation "cortex_a9_load1_2" 4 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "load1, load2, load_byte")) ++ (eq_attr "type" "load1, load2, load_byte, f_loads, f_loadd")) + "cortex_a9_ls") + + ;; Loads multiples and store multiples can't be issued for 2 cycles in a + ;; row. The description below assumes that addresses are 64 bit aligned. + ;; If not, there is an extra cycle latency which is not modelled. + +-;; FIXME:: This bit might need to be reworked when we get to +-;; tuning for the VFP because strictly speaking the ldm +-;; is sent to the LSU unit as is and there is only an +-;; issue restriction between the LSU and the VFP/ Neon unit. +- + (define_insn_reservation "cortex_a9_load3_4" 5 + (and (eq_attr "tune" "cortexa9") + (eq_attr "type" "load3, load4")) +@@ -120,12 +114,13 @@ + + (define_insn_reservation "cortex_a9_store1_2" 0 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "store1, store2")) ++ (eq_attr "type" "store1, store2, f_stores, f_stored")) + "cortex_a9_ls") + + ;; Almost all our store multiples use an auto-increment + ;; form. Don't issue back to back load and store multiples + ;; because the load store unit will stall. ++ + (define_insn_reservation "cortex_a9_store3_4" 0 + (and (eq_attr "tune" "cortexa9") + (eq_attr "type" "store3, store4")) +@@ -193,47 +188,82 @@ + (define_insn_reservation "cortex_a9_call" 0 + (and (eq_attr "tune" "cortexa9") + (eq_attr "type" "call")) +- "cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + cortex_a9_vfp") ++ "cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + ca9_issue_vfp_neon") + + + ;; Pipelining for VFP instructions. ++;; Issue happens either along load store unit or the VFP / Neon unit. ++;; Pipeline Instruction Classification. ++;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r ++;; FP_ADD - fadds, faddd, fcmps (1) ++;; FPMUL - fmul{s,d}, fmac{s,d} ++;; FPDIV - fdiv{s,d} ++(define_cpu_unit "ca9fps" "cortex_a9") ++(define_cpu_unit "ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4" "cortex_a9") ++(define_cpu_unit "ca9fp_mul1, ca9fp_mul2 , ca9fp_mul3, ca9fp_mul4" "cortex_a9") ++(define_cpu_unit "ca9fp_ds1" "cortex_a9") ++ + +-(define_insn_reservation "cortex_a9_ffarith" 1 ++;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle. ++(define_insn_reservation "cortex_a9_fps" 2 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd,fconsts,fconstd")) +- "cortex_a9_vfp") ++ (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd, r_2_f, f_2_r, f_flag")) ++ "ca9_issue_vfp_neon + ca9fps") ++ ++(define_bypass 1 ++ "cortex_a9_fps" ++ "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply") ++ ++;; Scheduling on the FP_ADD pipeline. ++(define_reservation "ca9fp_add" "ca9_issue_vfp_neon + ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4") + + (define_insn_reservation "cortex_a9_fadd" 4 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fadds,faddd,f_cvt")) +- "cortex_a9_vfp") ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fadds, faddd, f_cvt")) ++ "ca9fp_add") + +-(define_insn_reservation "cortex_a9_fmuls" 5 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fmuls")) +- "cortex_a9_vfp") ++(define_insn_reservation "cortex_a9_fcmp" 1 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fcmps, fcmpd")) ++ "ca9_issue_vfp_neon + ca9fp_add1") + +-(define_insn_reservation "cortex_a9_fmuld" 6 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fmuld")) +- "cortex_a9_vfp*2") ++;; Scheduling for the Multiply and MAC instructions. ++(define_reservation "ca9fmuls" ++ "ca9fp_mul1 + ca9_issue_vfp_neon, ca9fp_mul2, ca9fp_mul3, ca9fp_mul4") ++ ++(define_reservation "ca9fmuld" ++ "ca9fp_mul1 + ca9_issue_vfp_neon, (ca9fp_mul1 + ca9fp_mul2), ca9fp_mul2, ca9fp_mul3, ca9fp_mul4") ++ ++(define_insn_reservation "cortex_a9_fmuls" 4 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fmuls")) ++ "ca9fmuls") ++ ++(define_insn_reservation "cortex_a9_fmuld" 5 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fmuld")) ++ "ca9fmuld") + + (define_insn_reservation "cortex_a9_fmacs" 8 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fmacs")) +- "cortex_a9_vfp") ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fmacs")) ++ "ca9fmuls, ca9fp_add") + +-(define_insn_reservation "cortex_a9_fmacd" 8 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fmacd")) +- "cortex_a9_vfp*2") ++(define_insn_reservation "cortex_a9_fmacd" 9 ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fmacd")) ++ "ca9fmuld, ca9fp_add") + ++;; Division pipeline description. + (define_insn_reservation "cortex_a9_fdivs" 15 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fdivs")) +- "cortex_a9_vfp*10") ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fdivs")) ++ "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*14") + + (define_insn_reservation "cortex_a9_fdivd" 25 +- (and (eq_attr "tune" "cortexa9") +- (eq_attr "type" "fdivd")) +- "cortex_a9_vfp*20") ++ (and (eq_attr "tune" "cortexa9") ++ (eq_attr "type" "fdivd")) ++ "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24") ++ ++;; Include Neon pipeline description ++(include "cortex-a9-neon.md") +--- a/src/gcc/config/arm/cortex-m4-fpu.md ++++ b/src/gcc/config/arm/cortex-m4-fpu.md +@@ -0,0 +1,111 @@ ++;; ARM Cortex-M4 FPU pipeline description ++;; Copyright (C) 2010 Free Software Foundation, Inc. ++;; Contributed by CodeSourcery. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++;; Use an artifial unit to model FPU. ++(define_cpu_unit "cortex_m4_v" "cortex_m4") ++ ++(define_reservation "cortex_m4_ex_v" "cortex_m4_ex+cortex_m4_v") ++ ++;; Integer instructions following VDIV or VSQRT complete out-of-order. ++(define_insn_reservation "cortex_m4_fdivs" 15 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "fdivs")) ++ "cortex_m4_ex_v,cortex_m4_v*13") ++ ++(define_insn_reservation "cortex_m4_vmov_1" 1 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "fcpys,fconsts")) ++ "cortex_m4_ex_v") ++ ++(define_insn_reservation "cortex_m4_vmov_2" 2 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "f_2_r,r_2_f")) ++ "cortex_m4_ex_v*2") ++ ++(define_insn_reservation "cortex_m4_fmuls" 2 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "fmuls")) ++ "cortex_m4_ex_v") ++ ++(define_insn_reservation "cortex_m4_fmacs" 4 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "fmacs")) ++ "cortex_m4_ex_v*3") ++ ++(define_insn_reservation "cortex_m4_ffariths" 1 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "ffariths")) ++ "cortex_m4_ex_v") ++ ++(define_insn_reservation "cortex_m4_fadds" 2 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "fadds")) ++ "cortex_m4_ex_v") ++ ++(define_insn_reservation "cortex_m4_fcmps" 1 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "fcmps")) ++ "cortex_m4_ex_v") ++ ++(define_insn_reservation "cortex_m4_f_flag" 1 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "f_flag")) ++ "cortex_m4_ex_v") ++ ++(define_insn_reservation "cortex_m4_f_cvt" 2 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "f_cvt")) ++ "cortex_m4_ex_v") ++ ++(define_insn_reservation "cortex_m4_f_load" 2 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "f_load")) ++ "cortex_m4_ex_v*2") ++ ++(define_insn_reservation "cortex_m4_f_store" 2 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "f_store")) ++ "cortex_m4_ex_v*2") ++ ++(define_insn_reservation "cortex_m4_f_loadd" 3 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "f_loadd")) ++ "cortex_m4_ex_v*3") ++ ++(define_insn_reservation "cortex_m4_f_stored" 3 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "f_stored")) ++ "cortex_m4_ex_v*3") ++ ++;; MAC instructions consume their addend one cycle later. If the result ++;; of an arithmetic instruction is consumed as the addend of the following ++;; MAC instruction, the latency can be decreased by one. ++ ++(define_bypass 1 "cortex_m4_fadds,cortex_m4_fmuls,cortex_m4_f_cvt" ++ "cortex_m4_fmacs" ++ "arm_no_early_mul_dep") ++ ++(define_bypass 3 "cortex_m4_fmacs" ++ "cortex_m4_fmacs" ++ "arm_no_early_mul_dep") ++ ++(define_bypass 14 "cortex_m4_fdivs" ++ "cortex_m4_fmacs" ++ "arm_no_early_mul_dep") +--- a/src/gcc/config/arm/cortex-m4.md ++++ b/src/gcc/config/arm/cortex-m4.md +@@ -0,0 +1,111 @@ ++;; ARM Cortex-M4 pipeline description ++;; Copyright (C) 2010 Free Software Foundation, Inc. ++;; Contributed by CodeSourcery. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_automaton "cortex_m4") ++ ++;; We model the pipelining of LDR instructions by using two artificial units. ++ ++(define_cpu_unit "cortex_m4_a" "cortex_m4") ++ ++(define_cpu_unit "cortex_m4_b" "cortex_m4") ++ ++(define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b") ++ ++;; ALU and multiply is one cycle. ++(define_insn_reservation "cortex_m4_alu" 1 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "alu,alu_shift,alu_shift_reg,mult")) ++ "cortex_m4_ex") ++ ++;; Byte, half-word and word load is two cycles. ++(define_insn_reservation "cortex_m4_load1" 2 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "load_byte,load1")) ++ "cortex_m4_a, cortex_m4_b") ++ ++;; str rx, [ry, #imm] is always one cycle. ++(define_insn_reservation "cortex_m4_store1_1" 1 ++ (and (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "store1")) ++ (ne (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0))) ++ "cortex_m4_a") ++ ++;; Other byte, half-word and word load is two cycles. ++(define_insn_reservation "cortex_m4_store1_2" 2 ++ (and (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "store1")) ++ (eq (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0))) ++ "cortex_m4_a*2") ++ ++(define_insn_reservation "cortex_m4_load2" 3 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "load2")) ++ "cortex_m4_ex*3") ++ ++(define_insn_reservation "cortex_m4_store2" 3 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "store2")) ++ "cortex_m4_ex*3") ++ ++(define_insn_reservation "cortex_m4_load3" 4 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "load3")) ++ "cortex_m4_ex*4") ++ ++(define_insn_reservation "cortex_m4_store3" 4 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "store3")) ++ "cortex_m4_ex*4") ++ ++(define_insn_reservation "cortex_m4_load4" 5 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "load4")) ++ "cortex_m4_ex*5") ++ ++(define_insn_reservation "cortex_m4_store4" 5 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "store4")) ++ "cortex_m4_ex*5") ++ ++;; If the address of load or store depends on the result of the preceding ++;; instruction, the latency is increased by one. ++ ++(define_bypass 2 "cortex_m4_alu" ++ "cortex_m4_load1" ++ "arm_early_load_addr_dep") ++ ++(define_bypass 2 "cortex_m4_alu" ++ "cortex_m4_store1_1,cortex_m4_store1_2" ++ "arm_early_store_addr_dep") ++ ++(define_insn_reservation "cortex_m4_branch" 3 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "branch")) ++ "cortex_m4_ex*3") ++ ++(define_insn_reservation "cortex_m4_call" 3 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "call")) ++ "cortex_m4_ex*3") ++ ++(define_insn_reservation "cortex_m4_block" 1 ++ (and (eq_attr "tune" "cortexm4") ++ (eq_attr "type" "block")) ++ "cortex_m4_ex") +--- a/src/gcc/config/arm/fp16.c ++++ b/src/gcc/config/arm/fp16.c +@@ -22,10 +22,10 @@ + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +-static inline unsigned short ++static inline unsigned int + __gnu_f2h_internal(unsigned int a, int ieee) + { +- unsigned short sign = (a >> 16) & 0x8000; ++ unsigned int sign = (a >> 16) & 0x8000; + int aexp = (a >> 23) & 0xff; + unsigned int mantissa = a & 0x007fffff; + unsigned int mask; +@@ -95,10 +95,10 @@ + return sign | (((aexp + 14) << 10) + (mantissa >> 13)); + } + +-unsigned int +-__gnu_h2f_internal(unsigned short a, int ieee) ++static inline unsigned int ++__gnu_h2f_internal(unsigned int a, int ieee) + { +- unsigned int sign = (unsigned int)(a & 0x8000) << 16; ++ unsigned int sign = (a & 0x00008000) << 16; + int aexp = (a >> 10) & 0x1f; + unsigned int mantissa = a & 0x3ff; + +@@ -120,26 +120,33 @@ + return sign | (((aexp + 0x70) << 23) + (mantissa << 13)); + } + +-unsigned short ++#define ALIAS(src, dst) \ ++ typeof (src) dst __attribute__ ((alias (#src))); ++ ++unsigned int + __gnu_f2h_ieee(unsigned int a) + { + return __gnu_f2h_internal(a, 1); + } ++ALIAS (__gnu_f2h_ieee, __aeabi_f2h) + + unsigned int +-__gnu_h2f_ieee(unsigned short a) ++__gnu_h2f_ieee(unsigned int a) + { + return __gnu_h2f_internal(a, 1); + } ++ALIAS (__gnu_h2f_ieee, __aeabi_h2f) + +-unsigned short ++unsigned int + __gnu_f2h_alternative(unsigned int x) + { + return __gnu_f2h_internal(x, 0); + } ++ALIAS (__gnu_f2h_alternative, __aeabi_f2h_alt) + + unsigned int +-__gnu_h2f_alternative(unsigned short a) ++__gnu_h2f_alternative(unsigned int a) + { + return __gnu_h2f_internal(a, 0); + } ++ALIAS (__gnu_h2f_alternative, __aeabi_h2f_alt) +--- a/src/gcc/config/arm/ieee754-df.S ++++ b/src/gcc/config/arm/ieee754-df.S +@@ -83,7 +83,7 @@ + ARM_FUNC_START adddf3 + ARM_FUNC_ALIAS aeabi_dadd adddf3 + +-1: do_push {r4, r5, lr} ++1: do_push (r4, r5, lr) + + @ Look for zeroes, equal values, INF, or NAN. + shift1 lsl, r4, xh, #1 +@@ -427,7 +427,7 @@ + do_it eq, t + moveq r1, #0 + RETc(eq) +- do_push {r4, r5, lr} ++ do_push (r4, r5, lr) + mov r4, #0x400 @ initial exponent + add r4, r4, #(52-1 - 1) + mov r5, #0 @ sign bit is 0 +@@ -447,7 +447,7 @@ + do_it eq, t + moveq r1, #0 + RETc(eq) +- do_push {r4, r5, lr} ++ do_push (r4, r5, lr) + mov r4, #0x400 @ initial exponent + add r4, r4, #(52-1 - 1) + ands r5, r0, #0x80000000 @ sign bit in r5 +@@ -481,7 +481,7 @@ + RETc(eq) @ we are done already. + + @ value was denormalized. We can normalize it now. +- do_push {r4, r5, lr} ++ do_push (r4, r5, lr) + mov r4, #0x380 @ setup corresponding exponent + and r5, xh, #0x80000000 @ move sign bit in r5 + bic xh, xh, #0x80000000 +@@ -508,9 +508,9 @@ + @ compatibility. + adr ip, LSYM(f0_ret) + @ Push pc as well so that RETLDM works correctly. +- do_push {r4, r5, ip, lr, pc} ++ do_push (r4, r5, ip, lr, pc) + #else +- do_push {r4, r5, lr} ++ do_push (r4, r5, lr) + #endif + + mov r5, #0 +@@ -534,9 +534,9 @@ + @ compatibility. + adr ip, LSYM(f0_ret) + @ Push pc as well so that RETLDM works correctly. +- do_push {r4, r5, ip, lr, pc} ++ do_push (r4, r5, ip, lr, pc) + #else +- do_push {r4, r5, lr} ++ do_push (r4, r5, lr) + #endif + + ands r5, ah, #0x80000000 @ sign bit in r5 +@@ -585,7 +585,7 @@ + @ Legacy code expects the result to be returned in f0. Copy it + @ there as well. + LSYM(f0_ret): +- do_push {r0, r1} ++ do_push (r0, r1) + ldfd f0, [sp], #8 + RETLDM + +@@ -602,7 +602,7 @@ + + ARM_FUNC_START muldf3 + ARM_FUNC_ALIAS aeabi_dmul muldf3 +- do_push {r4, r5, r6, lr} ++ do_push (r4, r5, r6, lr) + + @ Mask out exponents, trap any zero/denormal/INF/NAN. + mov ip, #0xff +@@ -910,7 +910,7 @@ + ARM_FUNC_START divdf3 + ARM_FUNC_ALIAS aeabi_ddiv divdf3 + +- do_push {r4, r5, r6, lr} ++ do_push (r4, r5, r6, lr) + + @ Mask out exponents, trap any zero/denormal/INF/NAN. + mov ip, #0xff +@@ -1195,7 +1195,7 @@ + + @ The status-returning routines are required to preserve all + @ registers except ip, lr, and cpsr. +-6: do_push {r0, lr} ++6: do_push (r0, lr) + ARM_CALL cmpdf2 + @ Set the Z flag correctly, and the C flag unconditionally. + cmp r0, #0 +--- a/src/gcc/config/arm/ieee754-sf.S ++++ b/src/gcc/config/arm/ieee754-sf.S +@@ -481,7 +481,7 @@ + and r3, ip, #0x80000000 + + @ Well, no way to make it shorter without the umull instruction. +- do_push {r3, r4, r5} ++ do_push (r3, r4, r5) + mov r4, r0, lsr #16 + mov r5, r1, lsr #16 + bic r0, r0, r4, lsl #16 +@@ -492,7 +492,7 @@ + mla r0, r4, r1, r0 + adds r3, r3, r0, lsl #16 + adc r1, ip, r0, lsr #16 +- do_pop {r0, r4, r5} ++ do_pop (r0, r4, r5) + + #else + +@@ -882,7 +882,7 @@ + + @ The status-returning routines are required to preserve all + @ registers except ip, lr, and cpsr. +-6: do_push {r0, r1, r2, r3, lr} ++6: do_push (r0, r1, r2, r3, lr) + ARM_CALL cmpsf2 + @ Set the Z flag correctly, and the C flag unconditionally. + cmp r0, #0 +--- a/src/gcc/config/arm/ldmstm.md ++++ b/src/gcc/config/arm/ldmstm.md +@@ -0,0 +1,1191 @@ ++/* ARM ldm/stm instruction patterns. This file was automatically generated ++ using arm-ldmstm.ml. Please do not edit manually. ++ ++ Copyright (C) 2010 Free Software Foundation, Inc. ++ Contributed by CodeSourcery. ++ ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published ++ by the Free Software Foundation; either version 3, or (at your ++ option) any later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ . */ ++ ++(define_insn "*ldm4_ia" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 4)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 8)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 12))))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" ++ "ldm%(ia%)\t%1, {%2, %3, %4, %5}" ++ [(set_attr "type" "load4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*thumb_ldm4_ia" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (match_operand:SI 1 "s_register_operand" "l"))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 4)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 8)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 12))))])] ++ "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" ++ "ldm%(ia%)\t%1, {%2, %3, %4, %5}" ++ [(set_attr "type" "load4")]) ++ ++(define_insn "*ldm4_ia_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (match_dup 2))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 4)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 8)))) ++ (set (match_operand:SI 6 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 12))))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" ++ "ldm%(ia%)\t%1!, {%3, %4, %5, %6}" ++ [(set_attr "type" "load4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*thumb_ldm4_ia_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=l") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (match_dup 2))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 4)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 8)))) ++ (set (match_operand:SI 6 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 12))))])] ++ "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" ++ "ldm%(ia%)\t%1!, {%3, %4, %5, %6}" ++ [(set_attr "type" "load4")]) ++ ++(define_insn "*stm4_ia" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk")) ++ (match_operand:SI 2 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) ++ (match_operand:SI 5 "arm_hard_register_operand" ""))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" ++ "stm%(ia%)\t%1, {%2, %3, %4, %5}" ++ [(set_attr "type" "store4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm4_ia_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) ++ (set (mem:SI (match_dup 2)) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) ++ (match_operand:SI 5 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) ++ (match_operand:SI 6 "arm_hard_register_operand" ""))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" ++ "stm%(ia%)\t%1!, {%3, %4, %5, %6}" ++ [(set_attr "type" "store4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*thumb_stm4_ia_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=l") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) ++ (set (mem:SI (match_dup 2)) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) ++ (match_operand:SI 5 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) ++ (match_operand:SI 6 "arm_hard_register_operand" ""))])] ++ "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" ++ "stm%(ia%)\t%1!, {%3, %4, %5, %6}" ++ [(set_attr "type" "store4")]) ++ ++(define_insn "*ldm4_ib" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") ++ (const_int 4)))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 8)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 12)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 16))))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 4" ++ "ldm%(ib%)\t%1, {%2, %3, %4, %5}" ++ [(set_attr "type" "load4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm4_ib_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 4)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 8)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 12)))) ++ (set (match_operand:SI 6 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 16))))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 5" ++ "ldm%(ib%)\t%1!, {%3, %4, %5, %6}" ++ [(set_attr "type" "load4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm4_ib" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4))) ++ (match_operand:SI 2 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) ++ (match_operand:SI 5 "arm_hard_register_operand" ""))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 4" ++ "stm%(ib%)\t%1, {%2, %3, %4, %5}" ++ [(set_attr "type" "store4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm4_ib_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) ++ (match_operand:SI 5 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) ++ (match_operand:SI 6 "arm_hard_register_operand" ""))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 5" ++ "stm%(ib%)\t%1!, {%3, %4, %5, %6}" ++ [(set_attr "type" "store4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm4_da" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") ++ (const_int -12)))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int -8)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int -4)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (match_dup 1)))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 4" ++ "ldm%(da%)\t%1, {%2, %3, %4, %5}" ++ [(set_attr "type" "load4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm4_da_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -12)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -8)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -4)))) ++ (set (match_operand:SI 6 "arm_hard_register_operand" "") ++ (mem:SI (match_dup 2)))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 5" ++ "ldm%(da%)\t%1!, {%3, %4, %5, %6}" ++ [(set_attr "type" "load4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm4_da" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -12))) ++ (match_operand:SI 2 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int -8))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (match_dup 1)) ++ (match_operand:SI 5 "arm_hard_register_operand" ""))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 4" ++ "stm%(da%)\t%1, {%2, %3, %4, %5}" ++ [(set_attr "type" "store4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm4_da_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16))) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -12))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) ++ (match_operand:SI 5 "arm_hard_register_operand" "")) ++ (set (mem:SI (match_dup 2)) ++ (match_operand:SI 6 "arm_hard_register_operand" ""))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 5" ++ "stm%(da%)\t%1!, {%3, %4, %5, %6}" ++ [(set_attr "type" "store4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm4_db" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") ++ (const_int -16)))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int -12)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int -8)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int -4))))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" ++ "ldm%(db%)\t%1, {%2, %3, %4, %5}" ++ [(set_attr "type" "load4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm4_db_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -16)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -12)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -8)))) ++ (set (match_operand:SI 6 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -4))))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" ++ "ldm%(db%)\t%1!, {%3, %4, %5, %6}" ++ [(set_attr "type" "load4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm4_db" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -16))) ++ (match_operand:SI 2 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int -12))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int -8))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) ++ (match_operand:SI 5 "arm_hard_register_operand" ""))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" ++ "stm%(db%)\t%1, {%2, %3, %4, %5}" ++ [(set_attr "type" "store4") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm4_db_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16))) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -16))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -12))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) ++ (match_operand:SI 5 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) ++ (match_operand:SI 6 "arm_hard_register_operand" ""))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" ++ "stm%(db%)\t%1!, {%3, %4, %5, %6}" ++ [(set_attr "type" "store4") ++ (set_attr "predicable" "yes")]) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 4 "memory_operand" "")) ++ (set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 5 "memory_operand" "")) ++ (set (match_operand:SI 2 "s_register_operand" "") ++ (match_operand:SI 6 "memory_operand" "")) ++ (set (match_operand:SI 3 "s_register_operand" "") ++ (match_operand:SI 7 "memory_operand" ""))] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_ldm_seq (operands, 4, false)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 4 "memory_operand" "")) ++ (parallel ++ [(set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 5 "memory_operand" "")) ++ (set (match_operand:SI 2 "s_register_operand" "") ++ (match_operand:SI 6 "memory_operand" "")) ++ (set (match_operand:SI 3 "s_register_operand" "") ++ (match_operand:SI 7 "memory_operand" ""))])] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_ldm_seq (operands, 4, false)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 8 "const_int_operand" "")) ++ (set (match_operand:SI 4 "memory_operand" "") ++ (match_dup 0)) ++ (set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 9 "const_int_operand" "")) ++ (set (match_operand:SI 5 "memory_operand" "") ++ (match_dup 1)) ++ (set (match_operand:SI 2 "s_register_operand" "") ++ (match_operand:SI 10 "const_int_operand" "")) ++ (set (match_operand:SI 6 "memory_operand" "") ++ (match_dup 2)) ++ (set (match_operand:SI 3 "s_register_operand" "") ++ (match_operand:SI 11 "const_int_operand" "")) ++ (set (match_operand:SI 7 "memory_operand" "") ++ (match_dup 3))] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_const_stm_seq (operands, 4)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 8 "const_int_operand" "")) ++ (set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 9 "const_int_operand" "")) ++ (set (match_operand:SI 2 "s_register_operand" "") ++ (match_operand:SI 10 "const_int_operand" "")) ++ (set (match_operand:SI 3 "s_register_operand" "") ++ (match_operand:SI 11 "const_int_operand" "")) ++ (set (match_operand:SI 4 "memory_operand" "") ++ (match_dup 0)) ++ (set (match_operand:SI 5 "memory_operand" "") ++ (match_dup 1)) ++ (set (match_operand:SI 6 "memory_operand" "") ++ (match_dup 2)) ++ (set (match_operand:SI 7 "memory_operand" "") ++ (match_dup 3))] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_const_stm_seq (operands, 4)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 4 "memory_operand" "") ++ (match_operand:SI 0 "s_register_operand" "")) ++ (set (match_operand:SI 5 "memory_operand" "") ++ (match_operand:SI 1 "s_register_operand" "")) ++ (set (match_operand:SI 6 "memory_operand" "") ++ (match_operand:SI 2 "s_register_operand" "")) ++ (set (match_operand:SI 7 "memory_operand" "") ++ (match_operand:SI 3 "s_register_operand" ""))] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_stm_seq (operands, 4)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_insn "*ldm3_ia" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 4)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 8))))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" ++ "ldm%(ia%)\t%1, {%2, %3, %4}" ++ [(set_attr "type" "load3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*thumb_ldm3_ia" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (match_operand:SI 1 "s_register_operand" "l"))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 4)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 8))))])] ++ "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" ++ "ldm%(ia%)\t%1, {%2, %3, %4}" ++ [(set_attr "type" "load3")]) ++ ++(define_insn "*ldm3_ia_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (match_dup 2))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 4)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 8))))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" ++ "ldm%(ia%)\t%1!, {%3, %4, %5}" ++ [(set_attr "type" "load3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*thumb_ldm3_ia_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=l") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (match_dup 2))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 4)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 8))))])] ++ "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" ++ "ldm%(ia%)\t%1!, {%3, %4, %5}" ++ [(set_attr "type" "load3")]) ++ ++(define_insn "*stm3_ia" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk")) ++ (match_operand:SI 2 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) ++ (match_operand:SI 4 "arm_hard_register_operand" ""))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" ++ "stm%(ia%)\t%1, {%2, %3, %4}" ++ [(set_attr "type" "store3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm3_ia_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) ++ (set (mem:SI (match_dup 2)) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) ++ (match_operand:SI 5 "arm_hard_register_operand" ""))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" ++ "stm%(ia%)\t%1!, {%3, %4, %5}" ++ [(set_attr "type" "store3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*thumb_stm3_ia_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=l") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) ++ (set (mem:SI (match_dup 2)) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) ++ (match_operand:SI 5 "arm_hard_register_operand" ""))])] ++ "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" ++ "stm%(ia%)\t%1!, {%3, %4, %5}" ++ [(set_attr "type" "store3")]) ++ ++(define_insn "*ldm3_ib" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") ++ (const_int 4)))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 8)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 12))))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 3" ++ "ldm%(ib%)\t%1, {%2, %3, %4}" ++ [(set_attr "type" "load3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm3_ib_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 4)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 8)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 12))))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 4" ++ "ldm%(ib%)\t%1!, {%3, %4, %5}" ++ [(set_attr "type" "load3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm3_ib" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4))) ++ (match_operand:SI 2 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) ++ (match_operand:SI 4 "arm_hard_register_operand" ""))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 3" ++ "stm%(ib%)\t%1, {%2, %3, %4}" ++ [(set_attr "type" "store3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm3_ib_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) ++ (match_operand:SI 5 "arm_hard_register_operand" ""))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 4" ++ "stm%(ib%)\t%1!, {%3, %4, %5}" ++ [(set_attr "type" "store3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm3_da" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") ++ (const_int -8)))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int -4)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (match_dup 1)))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 3" ++ "ldm%(da%)\t%1, {%2, %3, %4}" ++ [(set_attr "type" "load3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm3_da_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -8)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -4)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (match_dup 2)))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 4" ++ "ldm%(da%)\t%1!, {%3, %4, %5}" ++ [(set_attr "type" "load3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm3_da" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -8))) ++ (match_operand:SI 2 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (match_dup 1)) ++ (match_operand:SI 4 "arm_hard_register_operand" ""))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 3" ++ "stm%(da%)\t%1, {%2, %3, %4}" ++ [(set_attr "type" "store3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm3_da_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12))) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (match_dup 2)) ++ (match_operand:SI 5 "arm_hard_register_operand" ""))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 4" ++ "stm%(da%)\t%1!, {%3, %4, %5}" ++ [(set_attr "type" "store3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm3_db" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") ++ (const_int -12)))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int -8)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int -4))))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" ++ "ldm%(db%)\t%1, {%2, %3, %4}" ++ [(set_attr "type" "load3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm3_db_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -12)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -8)))) ++ (set (match_operand:SI 5 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -4))))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" ++ "ldm%(db%)\t%1!, {%3, %4, %5}" ++ [(set_attr "type" "load3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm3_db" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -12))) ++ (match_operand:SI 2 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int -8))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) ++ (match_operand:SI 4 "arm_hard_register_operand" ""))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" ++ "stm%(db%)\t%1, {%2, %3, %4}" ++ [(set_attr "type" "store3") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm3_db_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12))) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -12))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) ++ (match_operand:SI 4 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) ++ (match_operand:SI 5 "arm_hard_register_operand" ""))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" ++ "stm%(db%)\t%1!, {%3, %4, %5}" ++ [(set_attr "type" "store3") ++ (set_attr "predicable" "yes")]) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 3 "memory_operand" "")) ++ (set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 4 "memory_operand" "")) ++ (set (match_operand:SI 2 "s_register_operand" "") ++ (match_operand:SI 5 "memory_operand" ""))] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_ldm_seq (operands, 3, false)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 3 "memory_operand" "")) ++ (parallel ++ [(set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 4 "memory_operand" "")) ++ (set (match_operand:SI 2 "s_register_operand" "") ++ (match_operand:SI 5 "memory_operand" ""))])] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_ldm_seq (operands, 3, false)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 6 "const_int_operand" "")) ++ (set (match_operand:SI 3 "memory_operand" "") ++ (match_dup 0)) ++ (set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 7 "const_int_operand" "")) ++ (set (match_operand:SI 4 "memory_operand" "") ++ (match_dup 1)) ++ (set (match_operand:SI 2 "s_register_operand" "") ++ (match_operand:SI 8 "const_int_operand" "")) ++ (set (match_operand:SI 5 "memory_operand" "") ++ (match_dup 2))] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_const_stm_seq (operands, 3)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 6 "const_int_operand" "")) ++ (set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 7 "const_int_operand" "")) ++ (set (match_operand:SI 2 "s_register_operand" "") ++ (match_operand:SI 8 "const_int_operand" "")) ++ (set (match_operand:SI 3 "memory_operand" "") ++ (match_dup 0)) ++ (set (match_operand:SI 4 "memory_operand" "") ++ (match_dup 1)) ++ (set (match_operand:SI 5 "memory_operand" "") ++ (match_dup 2))] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_const_stm_seq (operands, 3)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 3 "memory_operand" "") ++ (match_operand:SI 0 "s_register_operand" "")) ++ (set (match_operand:SI 4 "memory_operand" "") ++ (match_operand:SI 1 "s_register_operand" "")) ++ (set (match_operand:SI 5 "memory_operand" "") ++ (match_operand:SI 2 "s_register_operand" ""))] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_stm_seq (operands, 3)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_insn "*ldm2_ia" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 4))))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" ++ "ldm%(ia%)\t%1, {%2, %3}" ++ [(set_attr "type" "load2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*thumb_ldm2_ia" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (match_operand:SI 1 "s_register_operand" "l"))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 4))))])] ++ "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2" ++ "ldm%(ia%)\t%1, {%2, %3}" ++ [(set_attr "type" "load2")]) ++ ++(define_insn "*ldm2_ia_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (match_dup 2))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 4))))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" ++ "ldm%(ia%)\t%1!, {%3, %4}" ++ [(set_attr "type" "load2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*thumb_ldm2_ia_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=l") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (match_dup 2))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 4))))])] ++ "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" ++ "ldm%(ia%)\t%1!, {%3, %4}" ++ [(set_attr "type" "load2")]) ++ ++(define_insn "*stm2_ia" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk")) ++ (match_operand:SI 2 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) ++ (match_operand:SI 3 "arm_hard_register_operand" ""))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" ++ "stm%(ia%)\t%1, {%2, %3}" ++ [(set_attr "type" "store2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm2_ia_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) ++ (set (mem:SI (match_dup 2)) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) ++ (match_operand:SI 4 "arm_hard_register_operand" ""))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" ++ "stm%(ia%)\t%1!, {%3, %4}" ++ [(set_attr "type" "store2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*thumb_stm2_ia_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=l") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) ++ (set (mem:SI (match_dup 2)) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) ++ (match_operand:SI 4 "arm_hard_register_operand" ""))])] ++ "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" ++ "stm%(ia%)\t%1!, {%3, %4}" ++ [(set_attr "type" "store2")]) ++ ++(define_insn "*ldm2_ib" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") ++ (const_int 4)))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int 8))))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 2" ++ "ldm%(ib%)\t%1, {%2, %3}" ++ [(set_attr "type" "load2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm2_ib_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 4)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int 8))))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 3" ++ "ldm%(ib%)\t%1!, {%3, %4}" ++ [(set_attr "type" "load2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm2_ib" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4))) ++ (match_operand:SI 2 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) ++ (match_operand:SI 3 "arm_hard_register_operand" ""))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 2" ++ "stm%(ib%)\t%1, {%2, %3}" ++ [(set_attr "type" "store2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm2_ib_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) ++ (match_operand:SI 4 "arm_hard_register_operand" ""))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 3" ++ "stm%(ib%)\t%1!, {%3, %4}" ++ [(set_attr "type" "store2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm2_da" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") ++ (const_int -4)))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (match_dup 1)))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 2" ++ "ldm%(da%)\t%1, {%2, %3}" ++ [(set_attr "type" "load2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm2_da_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -4)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (match_dup 2)))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 3" ++ "ldm%(da%)\t%1!, {%3, %4}" ++ [(set_attr "type" "load2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm2_da" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -4))) ++ (match_operand:SI 2 "arm_hard_register_operand" "")) ++ (set (mem:SI (match_dup 1)) ++ (match_operand:SI 3 "arm_hard_register_operand" ""))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 2" ++ "stm%(da%)\t%1, {%2, %3}" ++ [(set_attr "type" "store2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm2_da_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8))) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (match_dup 2)) ++ (match_operand:SI 4 "arm_hard_register_operand" ""))])] ++ "TARGET_ARM && XVECLEN (operands[0], 0) == 3" ++ "stm%(da%)\t%1!, {%3, %4}" ++ [(set_attr "type" "store2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm2_db" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 2 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") ++ (const_int -8)))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 1) ++ (const_int -4))))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" ++ "ldm%(db%)\t%1, {%2, %3}" ++ [(set_attr "type" "load2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*ldm2_db_update" ++ [(match_parallel 0 "load_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8))) ++ (set (match_operand:SI 3 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -8)))) ++ (set (match_operand:SI 4 "arm_hard_register_operand" "") ++ (mem:SI (plus:SI (match_dup 2) ++ (const_int -4))))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" ++ "ldm%(db%)\t%1!, {%3, %4}" ++ [(set_attr "type" "load2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm2_db" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -8))) ++ (match_operand:SI 2 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) ++ (match_operand:SI 3 "arm_hard_register_operand" ""))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" ++ "stm%(db%)\t%1, {%2, %3}" ++ [(set_attr "type" "store2") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*stm2_db_update" ++ [(match_parallel 0 "store_multiple_operation" ++ [(set (match_operand:SI 1 "s_register_operand" "=rk") ++ (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8))) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) ++ (match_operand:SI 3 "arm_hard_register_operand" "")) ++ (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) ++ (match_operand:SI 4 "arm_hard_register_operand" ""))])] ++ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" ++ "stm%(db%)\t%1!, {%3, %4}" ++ [(set_attr "type" "store2") ++ (set_attr "predicable" "yes")]) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 2 "memory_operand" "")) ++ (set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 3 "memory_operand" ""))] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_ldm_seq (operands, 2, false)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 4 "const_int_operand" "")) ++ (set (match_operand:SI 2 "memory_operand" "") ++ (match_dup 0)) ++ (set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 5 "const_int_operand" "")) ++ (set (match_operand:SI 3 "memory_operand" "") ++ (match_dup 1))] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_const_stm_seq (operands, 2)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 4 "const_int_operand" "")) ++ (set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 5 "const_int_operand" "")) ++ (set (match_operand:SI 2 "memory_operand" "") ++ (match_dup 0)) ++ (set (match_operand:SI 3 "memory_operand" "") ++ (match_dup 1))] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_const_stm_seq (operands, 2)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 2 "memory_operand" "") ++ (match_operand:SI 0 "s_register_operand" "")) ++ (set (match_operand:SI 3 "memory_operand" "") ++ (match_operand:SI 1 "s_register_operand" ""))] ++ "" ++ [(const_int 0)] ++{ ++ if (gen_stm_seq (operands, 2)) ++ DONE; ++ else ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 2 "memory_operand" "")) ++ (set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 3 "memory_operand" "")) ++ (parallel ++ [(set (match_operand:SI 4 "s_register_operand" "") ++ (match_operator:SI 5 "commutative_binary_operator" ++ [(match_operand:SI 6 "s_register_operand" "") ++ (match_operand:SI 7 "s_register_operand" "")])) ++ (clobber (reg:CC CC_REGNUM))])] ++ "(((operands[6] == operands[0] && operands[7] == operands[1]) ++ || (operands[7] == operands[0] && operands[6] == operands[1])) ++ && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[1]))" ++ [(parallel ++ [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)])) ++ (clobber (reg:CC CC_REGNUM))])] ++{ ++ if (!gen_ldm_seq (operands, 2, true)) ++ FAIL; ++}) ++ ++(define_peephole2 ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 2 "memory_operand" "")) ++ (set (match_operand:SI 1 "s_register_operand" "") ++ (match_operand:SI 3 "memory_operand" "")) ++ (set (match_operand:SI 4 "s_register_operand" "") ++ (match_operator:SI 5 "commutative_binary_operator" ++ [(match_operand:SI 6 "s_register_operand" "") ++ (match_operand:SI 7 "s_register_operand" "")]))] ++ "(((operands[6] == operands[0] && operands[7] == operands[1]) ++ || (operands[7] == operands[0] && operands[6] == operands[1])) ++ && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[1]))" ++ [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))] ++{ ++ if (!gen_ldm_seq (operands, 2, true)) ++ FAIL; ++}) ++ +--- a/src/gcc/config/arm/lib1funcs.asm ++++ b/src/gcc/config/arm/lib1funcs.asm +@@ -104,7 +104,8 @@ + #endif + + #if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ +- || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) ++ || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ ++ || defined(__ARM_ARCH_7EM__) + # define __ARM_ARCH__ 7 + #endif + +@@ -254,8 +255,8 @@ + .macro shift1 op, arg0, arg1, arg2 + \op \arg0, \arg1, \arg2 + .endm +-#define do_push push +-#define do_pop pop ++#define do_push(...) push {__VA_ARGS__} ++#define do_pop(...) pop {__VA_ARGS__} + #define COND(op1, op2, cond) op1 ## op2 ## cond + /* Perform an arithmetic operation with a variable shift operand. This + requires two instructions and a scratch register on Thumb-2. */ +@@ -269,8 +270,42 @@ + .macro shift1 op, arg0, arg1, arg2 + mov \arg0, \arg1, \op \arg2 + .endm +-#define do_push stmfd sp!, +-#define do_pop ldmfd sp!, ++#if defined(__low_irq_latency__) ++#define do_push(...) \ ++ _buildN1(do_push, _buildC1(__VA_ARGS__))( __VA_ARGS__) ++#define _buildN1(BASE, X) _buildN2(BASE, X) ++#define _buildN2(BASE, X) BASE##X ++#define _buildC1(...) _buildC2(__VA_ARGS__,9,8,7,6,5,4,3,2,1) ++#define _buildC2(a1,a2,a3,a4,a5,a6,a7,a8,a9,c,...) c ++ ++#define do_push1(r1) str r1, [sp, #-4]! ++#define do_push2(r1, r2) str r2, [sp, #-4]! ; str r1, [sp, #-4]! ++#define do_push3(r1, r2, r3) str r3, [sp, #-4]! ; str r2, [sp, #-4]!; str r1, [sp, #-4]! ++#define do_push4(r1, r2, r3, r4) \ ++ do_push3 (r2, r3, r4);\ ++ do_push1 (r1) ++#define do_push5(r1, r2, r3, r4, r5) \ ++ do_push4 (r2, r3, r4, r5);\ ++ do_push1 (r1) ++ ++#define do_pop(...) \ ++_buildN1(do_pop, _buildC1(__VA_ARGS__))( __VA_ARGS__) ++ ++#define do_pop1(r1) ldr r1, [sp], #4 ++#define do_pop2(r1, r2) ldr r1, [sp], #4 ; ldr r2, [sp], #4 ++#define do_pop3(r1, r2, r3) ldr r1, [sp], #4 ; str r2, [sp], #4; str r3, [sp], #4 ++#define do_pop4(r1, r2, r3, r4) \ ++ do_pop1 (r1);\ ++ do_pup3 (r2, r3, r4) ++#define do_pop5(r1, r2, r3, r4, r5) \ ++ do_pop1 (r1);\ ++ do_pop4 (r2, r3, r4, r5) ++#else ++#define do_push(...) stmfd sp!, { __VA_ARGS__} ++#define do_pop(...) ldmfd sp!, {__VA_ARGS__} ++#endif ++ ++ + #define COND(op1, op2, cond) op1 ## cond ## op2 + .macro shiftop name, dest, src1, src2, shiftop, shiftreg, tmp + \name \dest, \src1, \src2, \shiftop \shiftreg +@@ -1260,7 +1295,7 @@ + ARM_FUNC_START div0 + #endif + +- do_push {r1, lr} ++ do_push (r1, lr) + mov r0, #SIGFPE + bl SYM(raise) __PLT__ + RETLDM r1 +@@ -1277,7 +1312,7 @@ + #if defined __ARM_EABI__ && defined __linux__ + @ EABI GNU/Linux call to cacheflush syscall. + ARM_FUNC_START clear_cache +- do_push {r7} ++ do_push (r7) + #if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__) + movw r7, #2 + movt r7, #0xf +@@ -1287,7 +1322,7 @@ + #endif + mov r2, #0 + swi 0 +- do_pop {r7} ++ do_pop (r7) + RET + FUNC_END clear_cache + #else +@@ -1490,7 +1525,7 @@ + push {r4, lr} + # else + ARM_FUNC_START clzdi2 +- do_push {r4, lr} ++ do_push (r4, lr) + # endif + cmp xxh, #0 + bne 1f +--- a/src/gcc/config/arm/neon-schedgen.ml ++++ b/src/gcc/config/arm/neon-schedgen.ml +@@ -1,7 +1,6 @@ + (* Emission of the core of the Cortex-A8 NEON scheduling description. + Copyright (C) 2007, 2010 Free Software Foundation, Inc. + Contributed by CodeSourcery. +- + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it under +@@ -21,7 +20,14 @@ + + (* This scheduling description generator works as follows. + - Each group of instructions has source and destination requirements +- specified. The source requirements may be specified using ++ specified and a list of cores supported. This is then filtered ++ and per core scheduler descriptions are generated out. ++ The reservations generated are prefixed by the name of the ++ core and the check is performed on the basis of what the tuning ++ string is. Running this will generate Neon scheduler descriptions ++ for all cores supported. ++ ++ The source requirements may be specified using + Source (the stage at which all source operands not otherwise + described are read), Source_m (the stage at which Rm operands are + read), Source_n (likewise for Rn) and Source_d (likewise for Rd). +@@ -83,6 +89,17 @@ + | Ls of int + | Fmul_then_fadd | Fmul_then_fadd_2 + ++type core = CortexA8 | CortexA9 ++let allCores = [CortexA8; CortexA9] ++let coreStr = function ++ CortexA8 -> "cortex_a8" ++ | CortexA9 -> "cortex_a9" ++ ++let tuneStr = function ++ CortexA8 -> "cortexa8" ++ | CortexA9 -> "cortexa9" ++ ++ + (* This table must be kept as short as possible by conflating + entries with the same availability behavior. + +@@ -90,129 +107,136 @@ + Second components: availability requirements, in the order in which + they should appear in the comments in the .md file. + Third components: reservation info ++ Fourth components: List of supported cores. + *) + let availability_table = [ + (* NEON integer ALU instructions. *) + (* vbit vbif vbsl vorr vbic vnot vcls vclz vcnt vadd vand vorr + veor vbic vorn ddd qqq *) +- "neon_int_1", [Source n2; Dest n3], ALU; ++ "neon_int_1", [Source n2; Dest n3], ALU, allCores; + (* vadd vsub qqd vsub ddd qqq *) +- "neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU; ++ "neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU, allCores; + (* vsum vneg dd qq vadd vsub qdd *) +- "neon_int_3", [Source n1; Dest n3], ALU; ++ "neon_int_3", [Source n1; Dest n3], ALU, allCores; + (* vabs vceqz vcgez vcbtz vclez vcltz vadh vradh vsbh vrsbh dqq *) + (* vhadd vrhadd vqadd vtst ddd qqq *) +- "neon_int_4", [Source n2; Dest n4], ALU; ++ "neon_int_4", [Source n2; Dest n4], ALU, allCores; + (* vabd qdd vhsub vqsub vabd vceq vcge vcgt vmax vmin vfmx vfmn ddd ddd *) +- "neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU; ++ "neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU, allCores; + (* vqneg vqabs dd qq *) +- "neon_vqneg_vqabs", [Source n1; Dest n4], ALU; ++ "neon_vqneg_vqabs", [Source n1; Dest n4], ALU, allCores; + (* vmov vmvn *) +- "neon_vmov", [Dest n3], ALU; ++ "neon_vmov", [Dest n3], ALU, allCores; + (* vaba *) +- "neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU; ++ "neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU, allCores; + "neon_vaba_qqq", +- [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], ALU_2cycle; ++ [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], ++ ALU_2cycle, allCores; + (* vsma *) +- "neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU; ++ "neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU, allCores; + + (* NEON integer multiply instructions. *) + (* vmul, vqdmlh, vqrdmlh *) + (* vmul, vqdmul, qdd 16/8 long 32/16 long *) +- "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6], Mul; +- "neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)], Mul_2cycle; ++ "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6], ++ Mul, allCores; ++ "neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)], ++ Mul_2cycle, allCores; + (* vmul, vqdmul again *) + "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar", +- [Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle; ++ [Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle, allCores; + (* vmla, vmls *) + "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long", +- [Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul; ++ [Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul, allCores; + "neon_mla_qqq_8_16", +- [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle; ++ [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)], ++ Mul_2cycle, allCores; + "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long", +- [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle; ++ [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], ++ Mul_2cycle, allCores; + "neon_mla_qqq_32_qqd_32_scalar", +- [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)], Mul_4cycle; ++ [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)], ++ Mul_4cycle, allCores; + (* vmul, vqdmulh, vqrdmulh *) + (* vmul, vqdmul *) + "neon_mul_ddd_16_scalar_32_16_long_scalar", +- [Source_n n2; Source_m n1; Dest n6], Mul; ++ [Source_n n2; Source_m n1; Dest n6], Mul, allCores; + "neon_mul_qqd_32_scalar", +- [Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle; ++ [Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle, allCores; + (* vmla, vmls *) + (* vmla, vmla, vqdmla, vqdmls *) + "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar", +- [Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul; ++ [Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul, allCores; + + (* NEON integer shift instructions. *) + (* vshr/vshl immediate, vshr_narrow, vshl_vmvh, vsli_vsri_ddd *) +- "neon_shift_1", [Source n1; Dest n3], Shift; +- (* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow; ++ "neon_shift_1", [Source n1; Dest n3], Shift, allCores; ++ (* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow, allCores; + vqshl_vrshl_vqrshl_ddd *) +- "neon_shift_2", [Source n1; Dest n4], Shift; ++ "neon_shift_2", [Source n1; Dest n4], Shift, allCores; + (* vsli, vsri and vshl for qqq *) +- "neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle; +- "neon_vshl_ddd", [Source n1; Dest n1], Shift; ++ "neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle, allCores; ++ "neon_vshl_ddd", [Source n1; Dest n1], Shift, allCores; + "neon_vqshl_vrshl_vqrshl_qqq", [Source n1; Dest_n_after (1, n4)], +- Shift_2cycle; +- "neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift; ++ Shift_2cycle, allCores; ++ "neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift, allCores; + + (* NEON floating-point instructions. *) + (* vadd, vsub, vabd, vmul, vceq, vcge, vcgt, vcage, vcagt, vmax, vmin *) + (* vabs, vneg, vceqz, vcgez, vcgtz, vclez, vcltz, vrecpe, vrsqrte, vcvt *) +- "neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd; ++ "neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd, allCores; + "neon_fp_vadd_qqq_vabs_qq", [Source n2; Dest_n_after (1, n5)], +- Fadd_2cycle; ++ Fadd_2cycle, allCores; + (* vsum, fvmx, vfmn *) +- "neon_fp_vsum", [Source n1; Dest n5], Fadd; +- "neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul; ++ "neon_fp_vsum", [Source n1; Dest n5], Fadd, allCores; ++ "neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul, allCores; + "neon_fp_vmul_qqd", [Source_n n2; Source_m n1; Dest_n_after (1, n5)], +- Fmul_2cycle; ++ Fmul_2cycle, allCores; + (* vmla, vmls *) + "neon_fp_vmla_ddd", +- [Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd; ++ [Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd, allCores; + "neon_fp_vmla_qqq", + [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n9)], +- Fmul_then_fadd_2; ++ Fmul_then_fadd_2, allCores; + "neon_fp_vmla_ddd_scalar", +- [Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd; ++ [Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd, allCores; + "neon_fp_vmla_qqq_scalar", + [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n9)], +- Fmul_then_fadd_2; +- "neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd; ++ Fmul_then_fadd_2, allCores; ++ "neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd, allCores; + "neon_fp_vrecps_vrsqrts_qqq", [Source n2; Dest_n_after (1, n9)], +- Fmul_then_fadd_2; ++ Fmul_then_fadd_2, allCores; + + (* NEON byte permute instructions. *) + (* vmov; vtrn and vswp for dd; vzip for dd; vuzp for dd; vrev; vext for dd *) +- "neon_bp_simple", [Source n1; Dest n2], Permute 1; +- (* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1}; ++ "neon_bp_simple", [Source n1; Dest n2], Permute 1, allCores; ++ (* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1}, allCores; + similarly for vtbx *) +- "neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2; ++ "neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2, allCores; + (* all the rest *) +- "neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3; ++ "neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3, allCores; + + (* NEON load/store instructions. *) +- "neon_ldr", [Dest n1], Ls 1; +- "neon_str", [Source n1], Ls 1; +- "neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2; +- "neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3; +- "neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2; +- "neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3; +- "neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4; +- "neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2; +- "neon_vst1_3_4_regs", [Source n1], Ls 3; +- "neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4; +- "neon_vst3_vst4", [Source n1], Ls 4; +- "neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3; +- "neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5; +- "neon_vst1_vst2_lane", [Source n1], Ls 2; +- "neon_vst3_vst4_lane", [Source n1], Ls 3; +- "neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3; ++ "neon_ldr", [Dest n1], Ls 1, allCores; ++ "neon_str", [Source n1], Ls 1, allCores; ++ "neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2, allCores; ++ "neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3, allCores; ++ "neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2, allCores; ++ "neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3, allCores; ++ "neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4, allCores; ++ "neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2, allCores; ++ "neon_vst1_3_4_regs", [Source n1], Ls 3, allCores; ++ "neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4, allCores; ++ "neon_vst3_vst4", [Source n1], Ls 4, allCores; ++ "neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3, allCores; ++ "neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5, allCores; ++ "neon_vst1_vst2_lane", [Source n1], Ls 2, allCores; ++ "neon_vst3_vst4_lane", [Source n1], Ls 3, allCores; ++ "neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3, allCores; + + (* NEON register transfer instructions. *) +- "neon_mcr", [Dest n2], Permute 1; +- "neon_mcr_2_mcrr", [Dest n2], Permute 2; ++ "neon_mcr", [Dest n2], Permute 1, allCores; ++ "neon_mcr_2_mcrr", [Dest n2], Permute 2, allCores; + (* MRC instructions are in the .tpl file. *) + ] + +@@ -221,7 +245,7 @@ + required. (It is also possible that an entry in the table has no + source requirements.) *) + let calculate_sources = +- List.map (fun (name, avail, res) -> ++ List.map (fun (name, avail, res, cores) -> + let earliest_stage = + List.fold_left + (fun cur -> fun info -> +@@ -331,7 +355,7 @@ + of one bypass from this producer to any particular consumer listed + in LATENCIES.) Use a hash table to collate bypasses with the + same latency and guard. *) +-let collate_bypasses (producer_name, _, _, _) largest latencies = ++let collate_bypasses (producer_name, _, _, _) largest latencies core = + let ht = Hashtbl.create 42 in + let keys = ref [] in + List.iter ( +@@ -350,7 +374,7 @@ + (if (try ignore (Hashtbl.find ht (guard, latency)); false + with Not_found -> true) then + keys := (guard, latency) :: !keys); +- Hashtbl.add ht (guard, latency) consumer ++ Hashtbl.add ht (guard, latency) ((coreStr core) ^ "_" ^ consumer) + end + ) latencies; + (* The hash table now has bypasses collated so that ones with the +@@ -372,7 +396,7 @@ + the output in such a way that all bypasses with the same producer + and latency are together, and so that bypasses with the worst-case + latency are ignored. *) +-let worst_case_latencies_and_bypasses = ++let worst_case_latencies_and_bypasses core = + let rec f (worst_acc, bypasses_acc) prev xs = + match xs with + [] -> (worst_acc, bypasses_acc) +@@ -400,7 +424,7 @@ + (* Having got the largest latency, collect all bypasses for + this producer and filter out those with that larger + latency. Record the others for later emission. *) +- let bypasses = collate_bypasses producer largest latencies in ++ let bypasses = collate_bypasses producer largest latencies core in + (* Go on to process remaining producers, having noted + the result for this one. *) + f ((producer_name, producer_avail, largest, +@@ -444,14 +468,18 @@ + in + f avail 0 + ++ + (* Emit a define_insn_reservation for each producer. The latency + written in will be its worst-case latency. *) +-let emit_insn_reservations = +- List.iter ( ++let emit_insn_reservations core = ++ let corestring = coreStr core in ++ let tunestring = tuneStr core ++ in List.iter ( + fun (producer, avail, latency, reservation) -> + write_comment producer avail; +- Printf.printf "(define_insn_reservation \"%s\" %d\n" producer latency; +- Printf.printf " (and (eq_attr \"tune\" \"cortexa8\")\n"; ++ Printf.printf "(define_insn_reservation \"%s_%s\" %d\n" ++ corestring producer latency; ++ Printf.printf " (and (eq_attr \"tune\" \"%s\")\n" tunestring; + Printf.printf " (eq_attr \"neon_type\" \"%s\"))\n" producer; + let str = + match reservation with +@@ -467,7 +495,7 @@ + | Fmul_then_fadd -> "fmul_then_fadd" + | Fmul_then_fadd_2 -> "fmul_then_fadd_2" + in +- Printf.printf " \"cortex_a8_neon_%s\")\n\n" str ++ Printf.printf " \"%s_neon_%s\")\n\n" corestring str + ) + + (* Given a guard description, return the name of the C function to +@@ -480,10 +508,12 @@ + | Guard_none -> assert false + + (* Emit a define_bypass for each bypass. *) +-let emit_bypasses = ++let emit_bypasses core = + List.iter ( + fun (producer, consumers, latency, guard) -> +- Printf.printf "(define_bypass %d \"%s\"\n" latency producer; ++ Printf.printf "(define_bypass %d \"%s_%s\"\n" ++ latency (coreStr core) producer; ++ + if guard = Guard_none then + Printf.printf " \"%s\")\n\n" consumers + else +@@ -493,11 +523,21 @@ + end + ) + +-(* Program entry point. *) +-let main = ++ ++let calculate_per_core_availability_table core availability_table = + let table = calculate_sources availability_table in +- let worst_cases, bypasses = worst_case_latencies_and_bypasses table in +- emit_insn_reservations (List.rev worst_cases); ++ let worst_cases, bypasses = worst_case_latencies_and_bypasses core table in ++ emit_insn_reservations core (List.rev worst_cases); + Printf.printf ";; Exceptions to the default latencies.\n\n"; +- emit_bypasses bypasses ++ emit_bypasses core bypasses ++ ++let calculate_core_availability_table core availability_table = ++let filter_core = List.filter (fun (_, _, _, cores) ++ -> List.exists ((=) core) cores) ++in calculate_per_core_availability_table core (filter_core availability_table) + ++ ++(* Program entry point. *) ++let main = ++ List.map (fun core -> calculate_core_availability_table ++ core availability_table) allCores +--- a/src/gcc/config/arm/neon-testgen.ml ++++ b/src/gcc/config/arm/neon-testgen.ml +@@ -51,8 +51,8 @@ + Printf.fprintf chan "/* This file was autogenerated by neon-testgen. */\n\n"; + Printf.fprintf chan "/* { dg-do assemble } */\n"; + Printf.fprintf chan "/* { dg-require-effective-target arm_neon_ok } */\n"; +- Printf.fprintf chan +- "/* { dg-options \"-save-temps -O0 -mfpu=neon -mfloat-abi=softfp\" } */\n"; ++ Printf.fprintf chan "/* { dg-options \"-save-temps -O0\" } */\n"; ++ Printf.fprintf chan "/* { dg-add-options arm_neon } */\n"; + Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n"; + Printf.fprintf chan "void test_%s (void)\n{\n" test_name + +@@ -257,7 +257,7 @@ + intrinsic expands to. Watch out for any writeback character and + comments after the instruction. *) + let regexps = List.map (fun regexp -> insn_regexp ^ "\\[ \t\\]+" ^ regexp ^ +- "!?\\(\\[ \t\\]+@\\[a-zA-Z0-9 \\]+\\)?\\n") ++ "!?\\(\\[ \t\\]+@.*\\)?\\n") + (analyze_all_shapes features shape analyze_shape) + in + (* Emit file and function prologues. *) +--- a/src/gcc/config/arm/neon.md ++++ b/src/gcc/config/arm/neon.md +@@ -22,17 +22,12 @@ + (define_constants + [(UNSPEC_ASHIFT_SIGNED 65) + (UNSPEC_ASHIFT_UNSIGNED 66) +- (UNSPEC_VABA 67) +- (UNSPEC_VABAL 68) + (UNSPEC_VABD 69) + (UNSPEC_VABDL 70) +- (UNSPEC_VABS 71) + (UNSPEC_VADD 72) + (UNSPEC_VADDHN 73) + (UNSPEC_VADDL 74) + (UNSPEC_VADDW 75) +- (UNSPEC_VAND 76) +- (UNSPEC_VBIC 77) + (UNSPEC_VBSL 78) + (UNSPEC_VCAGE 79) + (UNSPEC_VCAGT 80) +@@ -40,18 +35,9 @@ + (UNSPEC_VCGE 82) + (UNSPEC_VCGT 83) + (UNSPEC_VCLS 84) +- (UNSPEC_VCLZ 85) +- (UNSPEC_VCNT 86) +- (UNSPEC_VCOMBINE 87) + (UNSPEC_VCVT 88) + (UNSPEC_VCVT_N 89) +- (UNSPEC_VDUP_LANE 90) +- (UNSPEC_VDUP_N 91) +- (UNSPEC_VEOR 92) + (UNSPEC_VEXT 93) +- (UNSPEC_VGET_HIGH 94) +- (UNSPEC_VGET_LANE 95) +- (UNSPEC_VGET_LOW 96) + (UNSPEC_VHADD 97) + (UNSPEC_VHSUB 98) + (UNSPEC_VLD1 99) +@@ -86,10 +72,6 @@ + (UNSPEC_VMULL 128) + (UNSPEC_VMUL_LANE 129) + (UNSPEC_VMULL_LANE 130) +- (UNSPEC_VMUL_N 131) +- (UNSPEC_VMVN 132) +- (UNSPEC_VORN 133) +- (UNSPEC_VORR 134) + (UNSPEC_VPADAL 135) + (UNSPEC_VPADD 136) + (UNSPEC_VPADDL 137) +@@ -125,7 +107,6 @@ + (UNSPEC_VREV64 167) + (UNSPEC_VRSQRTE 168) + (UNSPEC_VRSQRTS 169) +- (UNSPEC_VSET_LANE 170) + (UNSPEC_VSHL 171) + (UNSPEC_VSHLL_N 172) + (UNSPEC_VSHL_N 173) +@@ -159,7 +140,10 @@ + (UNSPEC_VUZP1 201) + (UNSPEC_VUZP2 202) + (UNSPEC_VZIP1 203) +- (UNSPEC_VZIP2 204)]) ++ (UNSPEC_VZIP2 204) ++ (UNSPEC_MISALIGNED_ACCESS 205) ++ (UNSPEC_VCLE 206) ++ (UNSPEC_VCLT 207)]) + + ;; Double-width vector modes. + (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) +@@ -251,6 +235,9 @@ + ;; Modes with 32-bit elements only. + (define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) + ++;; Modes with 8-bit, 16-bit and 32-bit elements. ++(define_mode_iterator VU [V16QI V8HI V4SI]) ++ + ;; (Opposite) mode to convert to/from for above conversions. + (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") + (V4SI "V4SF") (V4SF "V4SI")]) +@@ -332,6 +319,14 @@ + (V4HI "V2SI") (V8HI "V4SI") + (V2SI "DI") (V4SI "V2DI")]) + ++;; Double-sized modes with the same element size. ++;; Used for neon_vdup_lane, where the second operand is double-sized ++;; even when the first one is quad. ++(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") ++ (V4SI "V2SI") (V4SF "V2SF") ++ (V8QI "V8QI") (V4HI "V4HI") ++ (V2SI "V2SI") (V2SF "V2SF")]) ++ + ;; Mode of result of comparison operations (and bit-select operand 1). + (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") + (V4HI "V4HI") (V8HI "V8HI") +@@ -396,6 +391,9 @@ + ;; Same, without unsigned variants (for use with *SFmode pattern). + (define_code_iterator vqhs_ops [plus smin smax]) + ++;; A list of widening operators ++(define_code_iterator SE [sign_extend zero_extend]) ++ + ;; Assembler mnemonics for above codes. + (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") + (umin "vmin") (umax "vmax")]) +@@ -451,6 +449,12 @@ + (V2SF "2") (V4SF "4") + (DI "1") (V2DI "2")]) + ++;; Same as V_widen, but lower-case. ++(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) ++ ++;; Widen. Result is half the number of elements, but widened to double-width. ++(define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) ++ + (define_insn "*neon_mov" + [(set (match_operand:VD 0 "nonimmediate_operand" + "=w,Uv,w, w, ?r,?w,?r,?r, ?Us") +@@ -671,6 +675,52 @@ + neon_disambiguate_copy (operands, dest, src, 4); + }) + ++(define_expand "movmisalign" ++ [(set (match_operand:VDQX 0 "nonimmediate_operand" "") ++ (unspec:VDQX [(match_operand:VDQX 1 "general_operand" "")] ++ UNSPEC_MISALIGNED_ACCESS))] ++ "TARGET_NEON && !BYTES_BIG_ENDIAN" ++{ ++ /* This pattern is not permitted to fail during expansion: if both arguments ++ are non-registers (e.g. memory := constant, which can be created by the ++ auto-vectorizer), force operand 1 into a register. */ ++ if (!s_register_operand (operands[0], mode) ++ && !s_register_operand (operands[1], mode)) ++ operands[1] = force_reg (mode, operands[1]); ++}) ++ ++(define_insn "*movmisalign_neon_store" ++ [(set (match_operand:VDX 0 "memory_operand" "=Um") ++ (unspec:VDX [(match_operand:VDX 1 "s_register_operand" " w")] ++ UNSPEC_MISALIGNED_ACCESS))] ++ "TARGET_NEON && !BYTES_BIG_ENDIAN" ++ "vst1.\t{%P1}, %A0" ++ [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) ++ ++(define_insn "*movmisalign_neon_load" ++ [(set (match_operand:VDX 0 "s_register_operand" "=w") ++ (unspec:VDX [(match_operand:VDX 1 "memory_operand" " Um")] ++ UNSPEC_MISALIGNED_ACCESS))] ++ "TARGET_NEON && !BYTES_BIG_ENDIAN" ++ "vld1.\t{%P0}, %A1" ++ [(set_attr "neon_type" "neon_vld1_1_2_regs")]) ++ ++(define_insn "*movmisalign_neon_store" ++ [(set (match_operand:VQX 0 "memory_operand" "=Um") ++ (unspec:VQX [(match_operand:VQX 1 "s_register_operand" " w")] ++ UNSPEC_MISALIGNED_ACCESS))] ++ "TARGET_NEON && !BYTES_BIG_ENDIAN" ++ "vst1.\t{%q1}, %A0" ++ [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) ++ ++(define_insn "*movmisalign_neon_load" ++ [(set (match_operand:VQX 0 "s_register_operand" "=w") ++ (unspec:VQX [(match_operand:VQX 1 "memory_operand" " Um")] ++ UNSPEC_MISALIGNED_ACCESS))] ++ "TARGET_NEON && !BYTES_BIG_ENDIAN" ++ "vld1.\t{%q0}, %A1" ++ [(set_attr "neon_type" "neon_vld1_1_2_regs")]) ++ + (define_insn "vec_set_internal" + [(set (match_operand:VD 0 "s_register_operand" "=w") + (vec_merge:VD +@@ -685,7 +735,7 @@ + elt = GET_MODE_NUNITS (mode) - 1 - elt; + operands[2] = GEN_INT (elt); + +- return "vmov%?.\t%P0[%c2], %1"; ++ return "vmov%?.\t%P0[%c2], %1"; + } + [(set_attr "predicable" "yes") + (set_attr "neon_type" "neon_mcr")]) +@@ -711,7 +761,7 @@ + operands[0] = gen_rtx_REG (mode, regno + hi); + operands[2] = GEN_INT (elt); + +- return "vmov%?.\t%P0[%c2], %1"; ++ return "vmov%?.\t%P0[%c2], %1"; + } + [(set_attr "predicable" "yes") + (set_attr "neon_type" "neon_mcr")] +@@ -731,7 +781,7 @@ + + operands[0] = gen_rtx_REG (DImode, regno); + +- return "vmov%?.64\t%P0, %Q1, %R1"; ++ return "vmov%?\t%P0, %Q1, %R1"; + } + [(set_attr "predicable" "yes") + (set_attr "neon_type" "neon_mcr_2_mcrr")] +@@ -799,11 +849,11 @@ + (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] + "TARGET_NEON" + { +- int regno = REGNO (operands[1]) + INTVAL (operands[2]); ++ int regno = REGNO (operands[1]) + 2 * INTVAL (operands[2]); + + operands[1] = gen_rtx_REG (DImode, regno); + +- return "vmov%?.64\t%Q0, %R0, %P1"; ++ return "vmov%?\t%Q0, %R0, %P1 @ v2di"; + } + [(set_attr "predicable" "yes") + (set_attr "neon_type" "neon_int_1")] +@@ -820,17 +870,14 @@ + + ;; Doubleword and quadword arithmetic. + +-;; NOTE: vadd/vsub and some other instructions also support 64-bit integer +-;; element size, which we could potentially use for "long long" operations. We +-;; don't want to do this at present though, because moving values from the +-;; vector unit to the ARM core is currently slow and 64-bit addition (etc.) is +-;; easy to do with ARM instructions anyway. ++;; NOTE: some other instructions also support 64-bit integer ++;; element size, which we could potentially use for "long long" operations. + + (define_insn "*add3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (plus:VDQ (match_operand:VDQ 1 "s_register_operand" "w") + (match_operand:VDQ 2 "s_register_operand" "w")))] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + "vadd.\t%0, %1, %2" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -840,11 +887,33 @@ + (const_string "neon_int_1")))] + ) + ++(define_insn "adddi3_neon" ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r") ++ (plus:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0") ++ (match_operand:DI 2 "s_register_operand" "w,w,r,0"))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_NEON" ++{ ++ switch (which_alternative) ++ { ++ case 0: /* fall through */ ++ case 1: return "vadd.i64\t%P0, %P1, %P2"; ++ case 2: return "#"; ++ case 3: return "#"; ++ default: gcc_unreachable (); ++ } ++} ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") ++ (set_attr "conds" "*,*,clob,clob") ++ (set_attr "length" "*,*,8,8") ++ (set_attr "alt_tune" "nota8,onlya8,*,*")] ++) ++ + (define_insn "*sub3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w") + (match_operand:VDQ 2 "s_register_operand" "w")))] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + "vsub.\t%0, %1, %2" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -854,11 +923,34 @@ + (const_string "neon_int_2")))] + ) + ++(define_insn "subdi3_neon" ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r,?&r") ++ (minus:DI (match_operand:DI 1 "s_register_operand" "w,w,0,r,0") ++ (match_operand:DI 2 "s_register_operand" "w,w,r,0,0"))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_NEON" ++{ ++ switch (which_alternative) ++ { ++ case 0: /* fall through */ ++ case 1: return "vsub.i64\t%P0, %P1, %P2"; ++ case 2: /* fall through */ ++ case 3: /* fall through */ ++ case 4: return "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"; ++ default: gcc_unreachable (); ++ } ++} ++ [(set_attr "neon_type" "neon_int_2,neon_int_2,*,*,*") ++ (set_attr "conds" "*,*,clob,clob,clob") ++ (set_attr "length" "*,*,8,8,8") ++ (set_attr "alt_tune" "nota8,onlya8,*,*,*")] ++) ++ + (define_insn "*mul3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w") + (match_operand:VDQ 2 "s_register_operand" "w")))] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + "vmul.\t%0, %1, %2" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -875,12 +967,12 @@ + (const_string "neon_mul_qqq_8_16_32_ddd_32")))))] + ) + +-(define_insn "*mul3add_neon" ++(define_insn "mul3add_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w") + (match_operand:VDQ 3 "s_register_operand" "w")) + (match_operand:VDQ 1 "s_register_operand" "0")))] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + "vmla.\t%0, %2, %3" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -897,12 +989,12 @@ + (const_string "neon_mla_qqq_32_qqd_32_scalar")))))] + ) + +-(define_insn "*mul3negadd_neon" ++(define_insn "mul3negadd_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0") + (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w") + (match_operand:VDQ 3 "s_register_operand" "w"))))] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + "vmls.\t%0, %2, %3" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -937,21 +1029,26 @@ + ) + + (define_insn "iordi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w,w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0") +- (match_operand:DI 2 "neon_logic_op2" "w,Dl")] +- UNSPEC_VORR))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,w,?w,?&r,?&r") ++ (ior:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0,0,r") ++ (match_operand:DI 2 "neon_logic_op2" "w,w,Dl,Dl,r,r")))] + "TARGET_NEON" + { + switch (which_alternative) + { +- case 0: return "vorr\t%P0, %P1, %P2"; +- case 1: return neon_output_logic_immediate ("vorr", &operands[2], ++ case 0: /* fall through */ ++ case 1: return "vorr\t%P0, %P1, %P2"; ++ case 2: /* fall through */ ++ case 3: return neon_output_logic_immediate ("vorr", &operands[2], + DImode, 0, VALID_NEON_QREG_MODE (DImode)); ++ case 4: return "#"; ++ case 5: return "#"; + default: gcc_unreachable (); + } + } +- [(set_attr "neon_type" "neon_int_1")] ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,neon_int_1,neon_int_1,*,*") ++ (set_attr "length" "*,*,*,*,8,8") ++ (set_attr "alt_tune" "nota8,onlya8,nota8,onlya8,*,*")] + ) + + ;; The concrete forms of the Neon immediate-logic instructions are vbic and +@@ -977,21 +1074,26 @@ + ) + + (define_insn "anddi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w,w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0") +- (match_operand:DI 2 "neon_inv_logic_op2" "w,DL")] +- UNSPEC_VAND))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,w,?w,?&r,?&r") ++ (and:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0,0,r") ++ (match_operand:DI 2 "neon_inv_logic_op2" "w,w,DL,DL,r,r")))] + "TARGET_NEON" + { + switch (which_alternative) + { +- case 0: return "vand\t%P0, %P1, %P2"; +- case 1: return neon_output_logic_immediate ("vand", &operands[2], ++ case 0: /* fall through */ ++ case 1: return "vand\t%P0, %P1, %P2"; ++ case 2: /* fall through */ ++ case 3: return neon_output_logic_immediate ("vand", &operands[2], + DImode, 1, VALID_NEON_QREG_MODE (DImode)); ++ case 4: return "#"; ++ case 5: return "#"; + default: gcc_unreachable (); + } + } +- [(set_attr "neon_type" "neon_int_1")] ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,neon_int_1,neon_int_1,*,*") ++ (set_attr "length" "*,*,*,*,8,8") ++ (set_attr "alt_tune" "nota8,onlya8,nota8,onlya8,*,*")] + ) + + (define_insn "orn3_neon" +@@ -1004,13 +1106,16 @@ + ) + + (define_insn "orndi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") +- (match_operand:DI 2 "s_register_operand" "w")] +- UNSPEC_VORN))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r") ++ (ior:DI (match_operand:DI 1 "s_register_operand" "w,r,0") ++ (not:DI (match_operand:DI 2 "s_register_operand" "w,0,r"))))] + "TARGET_NEON" +- "vorn\t%P0, %P1, %P2" +- [(set_attr "neon_type" "neon_int_1")] ++ "@ ++ vorn\t%P0, %P1, %P2 ++ # ++ #" ++ [(set_attr "neon_type" "neon_int_1,*,*") ++ (set_attr "length" "*,8,8")] + ) + + (define_insn "bic3_neon" +@@ -1022,14 +1127,18 @@ + [(set_attr "neon_type" "neon_int_1")] + ) + ++;; Compare to *anddi_notdi_di. + (define_insn "bicdi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") +- (match_operand:DI 2 "s_register_operand" "w")] +- UNSPEC_VBIC))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r") ++ (and:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,r,0")) ++ (match_operand:DI 1 "s_register_operand" "w,0,r")))] + "TARGET_NEON" +- "vbic\t%P0, %P1, %P2" +- [(set_attr "neon_type" "neon_int_1")] ++ "@ ++ vbic\t%P0, %P1, %P2 ++ # ++ #" ++ [(set_attr "neon_type" "neon_int_1,*,*") ++ (set_attr "length" "*,8,8")] + ) + + (define_insn "xor3" +@@ -1042,13 +1151,18 @@ + ) + + (define_insn "xordi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") +- (match_operand:DI 2 "s_register_operand" "w")] +- UNSPEC_VEOR))] ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r") ++ (xor:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,r") ++ (match_operand:DI 2 "s_register_operand" "w,w,r,r")))] + "TARGET_NEON" +- "veor\t%P0, %P1, %P2" +- [(set_attr "neon_type" "neon_int_1")] ++ "@ ++ veor\t%P0, %P1, %P2 ++ veor\t%P0, %P1, %P2 ++ # ++ #" ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") ++ (set_attr "length" "*,*,8,8") ++ (set_attr "alt_tune" "nota8,onlya8,*,*")] + ) + + (define_insn "one_cmpl2" +@@ -1317,7 +1431,7 @@ + (parallel [(const_int 0) (const_int 1)])) + (vec_select:V2SF (match_dup 1) + (parallel [(const_int 2) (const_int 3)]))))] +- "TARGET_NEON" ++ "TARGET_NEON && flag_unsafe_math_optimizations" + ".f32\t%P0, %e1, %f1" + [(set_attr "vqh_mnem" "") + (set (attr "neon_type") +@@ -1452,7 +1566,7 @@ + (define_expand "reduc_splus_" + [(match_operand:VD 0 "s_register_operand" "") + (match_operand:VD 1 "s_register_operand" "")] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + { + neon_pairwise_reduce (operands[0], operands[1], mode, + &gen_neon_vpadd_internal); +@@ -1462,7 +1576,7 @@ + (define_expand "reduc_splus_" + [(match_operand:VQ 0 "s_register_operand" "") + (match_operand:VQ 1 "s_register_operand" "")] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + { + rtx step1 = gen_reg_rtx (mode); + rtx res_d = gen_reg_rtx (mode); +@@ -1497,7 +1611,7 @@ + (define_expand "reduc_smin_" + [(match_operand:VD 0 "s_register_operand" "") + (match_operand:VD 1 "s_register_operand" "")] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + { + neon_pairwise_reduce (operands[0], operands[1], mode, + &gen_neon_vpsmin); +@@ -1507,7 +1621,7 @@ + (define_expand "reduc_smin_" + [(match_operand:VQ 0 "s_register_operand" "") + (match_operand:VQ 1 "s_register_operand" "")] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + { + rtx step1 = gen_reg_rtx (mode); + rtx res_d = gen_reg_rtx (mode); +@@ -1522,7 +1636,7 @@ + (define_expand "reduc_smax_" + [(match_operand:VD 0 "s_register_operand" "") + (match_operand:VD 1 "s_register_operand" "")] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + { + neon_pairwise_reduce (operands[0], operands[1], mode, + &gen_neon_vpsmax); +@@ -1532,7 +1646,7 @@ + (define_expand "reduc_smax_" + [(match_operand:VQ 0 "s_register_operand" "") + (match_operand:VQ 1 "s_register_operand" "")] +- "TARGET_NEON" ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" + { + rtx step1 = gen_reg_rtx (mode); + rtx res_d = gen_reg_rtx (mode); +@@ -1704,15 +1818,204 @@ + [(set_attr "neon_type" "neon_int_5")] + ) + ++;; Conditional instructions. These are comparisons with conditional moves for ++;; vectors. They perform the assignment: ++;; ++;; Vop0 = (Vop4 Vop5) ? Vop1 : Vop2; ++;; ++;; where op3 is <, <=, ==, !=, >= or >. Operations are performed ++;; element-wise. ++ ++(define_expand "vcond" ++ [(set (match_operand:VDQW 0 "s_register_operand" "") ++ (if_then_else:VDQW ++ (match_operator 3 "arm_comparison_operator" ++ [(match_operand:VDQW 4 "s_register_operand" "") ++ (match_operand:VDQW 5 "nonmemory_operand" "")]) ++ (match_operand:VDQW 1 "s_register_operand" "") ++ (match_operand:VDQW 2 "s_register_operand" "")))] ++ "TARGET_NEON && (! || flag_unsafe_math_optimizations)" ++{ ++ rtx mask; ++ int inverse = 0, immediate_zero = 0; ++ /* See the description of "magic" bits in the 'T' case of ++ arm_print_operand. */ ++ HOST_WIDE_INT magic_word = (mode == V2SFmode || mode == V4SFmode) ++ ? 3 : 1; ++ rtx magic_rtx = GEN_INT (magic_word); ++ ++ mask = gen_reg_rtx (mode); ++ ++ if (operands[5] == CONST0_RTX (mode)) ++ immediate_zero = 1; ++ else if (!REG_P (operands[5])) ++ operands[5] = force_reg (mode, operands[5]); ++ ++ switch (GET_CODE (operands[3])) ++ { ++ case GE: ++ emit_insn (gen_neon_vcge (mask, operands[4], operands[5], ++ magic_rtx)); ++ break; ++ ++ case GT: ++ emit_insn (gen_neon_vcgt (mask, operands[4], operands[5], ++ magic_rtx)); ++ break; ++ ++ case EQ: ++ emit_insn (gen_neon_vceq (mask, operands[4], operands[5], ++ magic_rtx)); ++ break; ++ ++ case LE: ++ if (immediate_zero) ++ emit_insn (gen_neon_vcle (mask, operands[4], operands[5], ++ magic_rtx)); ++ else ++ emit_insn (gen_neon_vcge (mask, operands[5], operands[4], ++ magic_rtx)); ++ break; ++ ++ case LT: ++ if (immediate_zero) ++ emit_insn (gen_neon_vclt (mask, operands[4], operands[5], ++ magic_rtx)); ++ else ++ emit_insn (gen_neon_vcgt (mask, operands[5], operands[4], ++ magic_rtx)); ++ break; ++ ++ case NE: ++ emit_insn (gen_neon_vceq (mask, operands[4], operands[5], ++ magic_rtx)); ++ inverse = 1; ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ if (inverse) ++ emit_insn (gen_neon_vbsl (operands[0], mask, operands[2], ++ operands[1])); ++ else ++ emit_insn (gen_neon_vbsl (operands[0], mask, operands[1], ++ operands[2])); ++ ++ DONE; ++}) ++ ++(define_expand "vcondu" ++ [(set (match_operand:VDQIW 0 "s_register_operand" "") ++ (if_then_else:VDQIW ++ (match_operator 3 "arm_comparison_operator" ++ [(match_operand:VDQIW 4 "s_register_operand" "") ++ (match_operand:VDQIW 5 "s_register_operand" "")]) ++ (match_operand:VDQIW 1 "s_register_operand" "") ++ (match_operand:VDQIW 2 "s_register_operand" "")))] ++ "TARGET_NEON" ++{ ++ rtx mask; ++ int inverse = 0, immediate_zero = 0; ++ ++ mask = gen_reg_rtx (mode); ++ ++ if (operands[5] == CONST0_RTX (mode)) ++ immediate_zero = 1; ++ else if (!REG_P (operands[5])) ++ operands[5] = force_reg (mode, operands[5]); ++ ++ switch (GET_CODE (operands[3])) ++ { ++ case GEU: ++ emit_insn (gen_neon_vcge (mask, operands[4], operands[5], ++ const0_rtx)); ++ break; ++ ++ case GTU: ++ emit_insn (gen_neon_vcgt (mask, operands[4], operands[5], ++ const0_rtx)); ++ break; ++ ++ case EQ: ++ emit_insn (gen_neon_vceq (mask, operands[4], operands[5], ++ const0_rtx)); ++ break; ++ ++ case LEU: ++ if (immediate_zero) ++ emit_insn (gen_neon_vcle (mask, operands[4], operands[5], ++ const0_rtx)); ++ else ++ emit_insn (gen_neon_vcge (mask, operands[5], operands[4], ++ const0_rtx)); ++ break; ++ ++ case LTU: ++ if (immediate_zero) ++ emit_insn (gen_neon_vclt (mask, operands[4], operands[5], ++ const0_rtx)); ++ else ++ emit_insn (gen_neon_vcgt (mask, operands[5], operands[4], ++ const0_rtx)); ++ break; ++ ++ case NE: ++ emit_insn (gen_neon_vceq (mask, operands[4], operands[5], ++ const0_rtx)); ++ inverse = 1; ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ ++ if (inverse) ++ emit_insn (gen_neon_vbsl (operands[0], mask, operands[2], ++ operands[1])); ++ else ++ emit_insn (gen_neon_vbsl (operands[0], mask, operands[1], ++ operands[2])); ++ ++ DONE; ++}) ++ + ;; Patterns for builtins. + + ; good for plain vadd, vaddq. + +-(define_insn "neon_vadd" ++(define_expand "neon_vadd" ++ [(match_operand:VDQX 0 "s_register_operand" "=w") ++ (match_operand:VDQX 1 "s_register_operand" "w") ++ (match_operand:VDQX 2 "s_register_operand" "w") ++ (match_operand:SI 3 "immediate_operand" "i")] ++ "TARGET_NEON" ++{ ++ if (! || flag_unsafe_math_optimizations) ++ emit_insn (gen_add3 (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_neon_vadd_unspec (operands[0], operands[1], ++ operands[2])); ++ DONE; ++}) ++ ++; Note that NEON operations don't support the full IEEE 754 standard: in ++; particular, denormal values are flushed to zero. This means that GCC cannot ++; use those instructions for autovectorization, etc. unless ++; -funsafe-math-optimizations is in effect (in which case flush-to-zero ++; behaviour is permissible). Intrinsic operations (provided by the arm_neon.h ++; header) must work in either case: if -funsafe-math-optimizations is given, ++; intrinsics expand to "canonical" RTL where possible, otherwise intrinsics ++; expand to unspecs (which may potentially limit the extent to which they might ++; be optimized by generic code). ++ ++; Used for intrinsics when flag_unsafe_math_optimizations is false. ++ ++(define_insn "neon_vadd_unspec" + [(set (match_operand:VDQX 0 "s_register_operand" "=w") + (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w") +- (match_operand:VDQX 2 "s_register_operand" "w") +- (match_operand:SI 3 "immediate_operand" "i")] ++ (match_operand:VDQX 2 "s_register_operand" "w")] + UNSPEC_VADD))] + "TARGET_NEON" + "vadd.\t%0, %1, %2" +@@ -1785,6 +2088,8 @@ + [(set_attr "neon_type" "neon_int_4")] + ) + ++;; We cannot replace this unspec with mul3 because of the odd ++;; polynomial multiplication case that can specified by operand 3. + (define_insn "neon_vmul" + [(set (match_operand:VDQW 0 "s_register_operand" "=w") + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w") +@@ -1808,13 +2113,31 @@ + (const_string "neon_mul_qqq_8_16_32_ddd_32")))))] + ) + +-(define_insn "neon_vmla" +- [(set (match_operand:VDQW 0 "s_register_operand" "=w") +- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") +- (match_operand:VDQW 2 "s_register_operand" "w") +- (match_operand:VDQW 3 "s_register_operand" "w") +- (match_operand:SI 4 "immediate_operand" "i")] +- UNSPEC_VMLA))] ++(define_expand "neon_vmla" ++ [(match_operand:VDQW 0 "s_register_operand" "=w") ++ (match_operand:VDQW 1 "s_register_operand" "0") ++ (match_operand:VDQW 2 "s_register_operand" "w") ++ (match_operand:VDQW 3 "s_register_operand" "w") ++ (match_operand:SI 4 "immediate_operand" "i")] ++ "TARGET_NEON" ++{ ++ if (! || flag_unsafe_math_optimizations) ++ emit_insn (gen_mul3add_neon (operands[0], operands[1], ++ operands[2], operands[3])); ++ else ++ emit_insn (gen_neon_vmla_unspec (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}) ++ ++; Used for intrinsics when flag_unsafe_math_optimizations is false. ++ ++(define_insn "neon_vmla_unspec" ++ [(set (match_operand:VDQ 0 "s_register_operand" "=w") ++ (unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "0") ++ (match_operand:VDQ 2 "s_register_operand" "w") ++ (match_operand:VDQ 3 "s_register_operand" "w")] ++ UNSPEC_VMLA))] + "TARGET_NEON" + "vmla.\t%0, %2, %3" + [(set (attr "neon_type") +@@ -1847,13 +2170,31 @@ + (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))] + ) + +-(define_insn "neon_vmls" +- [(set (match_operand:VDQW 0 "s_register_operand" "=w") +- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") +- (match_operand:VDQW 2 "s_register_operand" "w") +- (match_operand:VDQW 3 "s_register_operand" "w") +- (match_operand:SI 4 "immediate_operand" "i")] +- UNSPEC_VMLS))] ++(define_expand "neon_vmls" ++ [(match_operand:VDQW 0 "s_register_operand" "=w") ++ (match_operand:VDQW 1 "s_register_operand" "0") ++ (match_operand:VDQW 2 "s_register_operand" "w") ++ (match_operand:VDQW 3 "s_register_operand" "w") ++ (match_operand:SI 4 "immediate_operand" "i")] ++ "TARGET_NEON" ++{ ++ if (! || flag_unsafe_math_optimizations) ++ emit_insn (gen_mul3negadd_neon (operands[0], ++ operands[1], operands[2], operands[3])); ++ else ++ emit_insn (gen_neon_vmls_unspec (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}) ++ ++; Used for intrinsics when flag_unsafe_math_optimizations is false. ++ ++(define_insn "neon_vmls_unspec" ++ [(set (match_operand:VDQ 0 "s_register_operand" "=w") ++ (unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "0") ++ (match_operand:VDQ 2 "s_register_operand" "w") ++ (match_operand:VDQ 3 "s_register_operand" "w")] ++ UNSPEC_VMLS))] + "TARGET_NEON" + "vmls.\t%0, %2, %3" + [(set (attr "neon_type") +@@ -1963,11 +2304,27 @@ + (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))] + ) + +-(define_insn "neon_vsub" ++(define_expand "neon_vsub" ++ [(match_operand:VDQX 0 "s_register_operand" "=w") ++ (match_operand:VDQX 1 "s_register_operand" "w") ++ (match_operand:VDQX 2 "s_register_operand" "w") ++ (match_operand:SI 3 "immediate_operand" "i")] ++ "TARGET_NEON" ++{ ++ if (! || flag_unsafe_math_optimizations) ++ emit_insn (gen_sub3 (operands[0], operands[1], operands[2])); ++ else ++ emit_insn (gen_neon_vsub_unspec (operands[0], operands[1], ++ operands[2])); ++ DONE; ++}) ++ ++; Used for intrinsics when flag_unsafe_math_optimizations is false. ++ ++(define_insn "neon_vsub_unspec" + [(set (match_operand:VDQX 0 "s_register_operand" "=w") + (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w") +- (match_operand:VDQX 2 "s_register_operand" "w") +- (match_operand:SI 3 "immediate_operand" "i")] ++ (match_operand:VDQX 2 "s_register_operand" "w")] + UNSPEC_VSUB))] + "TARGET_NEON" + "vsub.\t%0, %1, %2" +@@ -2035,13 +2392,16 @@ + ) + + (define_insn "neon_vceq" +- [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand:VDQW 1 "s_register_operand" "w") +- (match_operand:VDQW 2 "s_register_operand" "w") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VCEQ))] ++ [(set (match_operand: 0 "s_register_operand" "=w,w") ++ (unspec: ++ [(match_operand:VDQW 1 "s_register_operand" "w,w") ++ (match_operand:VDQW 2 "nonmemory_operand" "w,Dz") ++ (match_operand:SI 3 "immediate_operand" "i,i")] ++ UNSPEC_VCEQ))] + "TARGET_NEON" +- "vceq.\t%0, %1, %2" ++ "@ ++ vceq.\t%0, %1, %2 ++ vceq.\t%0, %1, #0" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -2051,13 +2411,16 @@ + ) + + (define_insn "neon_vcge" +- [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand:VDQW 1 "s_register_operand" "w") +- (match_operand:VDQW 2 "s_register_operand" "w") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VCGE))] ++ [(set (match_operand: 0 "s_register_operand" "=w,w") ++ (unspec: ++ [(match_operand:VDQW 1 "s_register_operand" "w,w") ++ (match_operand:VDQW 2 "nonmemory_operand" "w,Dz") ++ (match_operand:SI 3 "immediate_operand" "i,i")] ++ UNSPEC_VCGE))] + "TARGET_NEON" +- "vcge.%T3%#\t%0, %1, %2" ++ "@ ++ vcge.%T3%#\t%0, %1, %2 ++ vcge.%T3%#\t%0, %1, #0" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -2067,13 +2430,16 @@ + ) + + (define_insn "neon_vcgt" +- [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand:VDQW 1 "s_register_operand" "w") +- (match_operand:VDQW 2 "s_register_operand" "w") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VCGT))] ++ [(set (match_operand: 0 "s_register_operand" "=w,w") ++ (unspec: ++ [(match_operand:VDQW 1 "s_register_operand" "w,w") ++ (match_operand:VDQW 2 "nonmemory_operand" "w,Dz") ++ (match_operand:SI 3 "immediate_operand" "i,i")] ++ UNSPEC_VCGT))] + "TARGET_NEON" +- "vcgt.%T3%#\t%0, %1, %2" ++ "@ ++ vcgt.%T3%#\t%0, %1, %2 ++ vcgt.%T3%#\t%0, %1, #0" + [(set (attr "neon_type") + (if_then_else (ne (symbol_ref "") (const_int 0)) + (if_then_else (ne (symbol_ref "") (const_int 0)) +@@ -2082,6 +2448,43 @@ + (const_string "neon_int_5")))] + ) + ++;; VCLE and VCLT only support comparisons with immediate zero (register ++;; variants are VCGE and VCGT with operands reversed). ++ ++(define_insn "neon_vcle" ++ [(set (match_operand: 0 "s_register_operand" "=w") ++ (unspec: ++ [(match_operand:VDQW 1 "s_register_operand" "w") ++ (match_operand:VDQW 2 "nonmemory_operand" "Dz") ++ (match_operand:SI 3 "immediate_operand" "i")] ++ UNSPEC_VCLE))] ++ "TARGET_NEON" ++ "vcle.%T3%#\t%0, %1, #0" ++ [(set (attr "neon_type") ++ (if_then_else (ne (symbol_ref "") (const_int 0)) ++ (if_then_else (ne (symbol_ref "") (const_int 0)) ++ (const_string "neon_fp_vadd_ddd_vabs_dd") ++ (const_string "neon_fp_vadd_qqq_vabs_qq")) ++ (const_string "neon_int_5")))] ++) ++ ++(define_insn "neon_vclt" ++ [(set (match_operand: 0 "s_register_operand" "=w") ++ (unspec: ++ [(match_operand:VDQW 1 "s_register_operand" "w") ++ (match_operand:VDQW 2 "nonmemory_operand" "Dz") ++ (match_operand:SI 3 "immediate_operand" "i")] ++ UNSPEC_VCLT))] ++ "TARGET_NEON" ++ "vclt.%T3%#\t%0, %1, #0" ++ [(set (attr "neon_type") ++ (if_then_else (ne (symbol_ref "") (const_int 0)) ++ (if_then_else (ne (symbol_ref "") (const_int 0)) ++ (const_string "neon_fp_vadd_ddd_vabs_dd") ++ (const_string "neon_fp_vadd_qqq_vabs_qq")) ++ (const_string "neon_int_5")))] ++) ++ + (define_insn "neon_vcage" + [(set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:VCVTF 1 "s_register_operand" "w") +@@ -2150,11 +2553,11 @@ + + (define_insn "neon_vaba" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") +- (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "0") +- (match_operand:VDQIW 2 "s_register_operand" "w") +- (match_operand:VDQIW 3 "s_register_operand" "w") +- (match_operand:SI 4 "immediate_operand" "i")] +- UNSPEC_VABA))] ++ (plus:VDQIW (match_operand:VDQIW 1 "s_register_operand" "0") ++ (unspec:VDQIW [(match_operand:VDQIW 2 "s_register_operand" "w") ++ (match_operand:VDQIW 3 "s_register_operand" "w") ++ (match_operand:SI 4 "immediate_operand" "i")] ++ UNSPEC_VABD)))] + "TARGET_NEON" + "vaba.%T4%#\t%0, %2, %3" + [(set (attr "neon_type") +@@ -2164,11 +2567,11 @@ + + (define_insn "neon_vabal" + [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand: 1 "s_register_operand" "0") +- (match_operand:VW 2 "s_register_operand" "w") +- (match_operand:VW 3 "s_register_operand" "w") +- (match_operand:SI 4 "immediate_operand" "i")] +- UNSPEC_VABAL))] ++ (plus: (match_operand: 1 "s_register_operand" "0") ++ (unspec: [(match_operand:VW 2 "s_register_operand" "w") ++ (match_operand:VW 3 "s_register_operand" "w") ++ (match_operand:SI 4 "immediate_operand" "i")] ++ UNSPEC_VABDL)))] + "TARGET_NEON" + "vabal.%T4%#\t%q0, %P2, %P3" + [(set_attr "neon_type" "neon_vaba")] +@@ -2299,22 +2702,15 @@ + (const_string "neon_fp_vrecps_vrsqrts_qqq")))] + ) + +-(define_insn "neon_vabs" +- [(set (match_operand:VDQW 0 "s_register_operand" "=w") +- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VABS))] ++(define_expand "neon_vabs" ++ [(match_operand:VDQW 0 "s_register_operand" "") ++ (match_operand:VDQW 1 "s_register_operand" "") ++ (match_operand:SI 2 "immediate_operand" "")] + "TARGET_NEON" +- "vabs.\t%0, %1" +- [(set (attr "neon_type") +- (if_then_else (ior (ne (symbol_ref "") (const_int 0)) +- (ne (symbol_ref "") (const_int 0))) +- (if_then_else +- (ne (symbol_ref "") (const_int 0)) +- (const_string "neon_fp_vadd_ddd_vabs_dd") +- (const_string "neon_fp_vadd_qqq_vabs_qq")) +- (const_string "neon_vqneg_vqabs")))] +-) ++{ ++ emit_insn (gen_abs2 (operands[0], operands[1])); ++ DONE; ++}) + + (define_insn "neon_vqabs" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") +@@ -2356,26 +2752,42 @@ + [(set_attr "neon_type" "neon_int_1")] + ) + +-(define_insn "neon_vclz" ++(define_insn "clz2" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w") +- (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VCLZ))] ++ (clz:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")))] + "TARGET_NEON" + "vclz.\t%0, %1" + [(set_attr "neon_type" "neon_int_1")] + ) + +-(define_insn "neon_vcnt" ++(define_expand "neon_vclz" ++ [(match_operand:VDQIW 0 "s_register_operand" "") ++ (match_operand:VDQIW 1 "s_register_operand" "") ++ (match_operand:SI 2 "immediate_operand" "")] ++ "TARGET_NEON" ++{ ++ emit_insn (gen_clz2 (operands[0], operands[1])); ++ DONE; ++}) ++ ++(define_insn "popcount2" + [(set (match_operand:VE 0 "s_register_operand" "=w") +- (unspec:VE [(match_operand:VE 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VCNT))] ++ (popcount:VE (match_operand:VE 1 "s_register_operand" "w")))] + "TARGET_NEON" + "vcnt.\t%0, %1" + [(set_attr "neon_type" "neon_int_1")] + ) + ++(define_expand "neon_vcnt" ++ [(match_operand:VE 0 "s_register_operand" "=w") ++ (match_operand:VE 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i")] ++ "TARGET_NEON" ++{ ++ emit_insn (gen_popcount2 (operands[0], operands[1])); ++ DONE; ++}) ++ + (define_insn "neon_vrecpe" + [(set (match_operand:V32 0 "s_register_operand" "=w") + (unspec:V32 [(match_operand:V32 1 "s_register_operand" "w") +@@ -2552,126 +2964,65 @@ + ; Operand 3 (info word) is ignored because it does nothing useful with 64-bit + ; elements. + +-(define_insn "neon_vget_lanedi" +- [(set (match_operand:DI 0 "s_register_operand" "=r") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VGET_LANE))] ++(define_expand "neon_vget_lanedi" ++ [(match_operand:DI 0 "s_register_operand" "=r") ++ (match_operand:DI 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i") ++ (match_operand:SI 3 "immediate_operand" "i")] + "TARGET_NEON" + { + neon_lane_bounds (operands[2], 0, 1); +- return "vmov%?\t%Q0, %R0, %P1 @ di"; +-} +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] +-) ++ emit_move_insn (operands[0], operands[1]); ++ DONE; ++}) + +-(define_insn "neon_vget_lanev2di" +- [(set (match_operand:DI 0 "s_register_operand" "=r") +- (unspec:DI [(match_operand:V2DI 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VGET_LANE))] ++(define_expand "neon_vget_lanev2di" ++ [(match_operand:DI 0 "s_register_operand" "=r") ++ (match_operand:V2DI 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i") ++ (match_operand:SI 3 "immediate_operand" "i")] + "TARGET_NEON" + { +- rtx ops[2]; +- unsigned int regno = REGNO (operands[1]); +- unsigned int elt = INTVAL (operands[2]); +- + neon_lane_bounds (operands[2], 0, 2); ++ emit_insn (gen_vec_extractv2di (operands[0], operands[1], operands[2])); ++ DONE; ++}) + +- ops[0] = operands[0]; +- ops[1] = gen_rtx_REG (DImode, regno + 2 * elt); +- output_asm_insn ("vmov%?\t%Q0, %R0, %P1 @ v2di", ops); +- +- return ""; +-} +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] +-) +- +-(define_insn "neon_vset_lane" +- [(set (match_operand:VD 0 "s_register_operand" "=w") +- (unspec:VD [(match_operand: 1 "s_register_operand" "r") +- (match_operand:VD 2 "s_register_operand" "0") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VSET_LANE))] +- "TARGET_NEON" +-{ +- neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); +- return "vmov%?.\t%P0[%c3], %1"; +-} +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] +-) +- +-; See neon_vget_lanedi comment for reasons operands 2 & 3 are ignored. +- +-(define_insn "neon_vset_lanedi" +- [(set (match_operand:DI 0 "s_register_operand" "=w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "r") +- (match_operand:DI 2 "s_register_operand" "0") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VSET_LANE))] +- "TARGET_NEON" +-{ +- neon_lane_bounds (operands[3], 0, 1); +- return "vmov%?\t%P0, %Q1, %R1 @ di"; +-} +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] +-) +- +-(define_insn "neon_vset_lane" +- [(set (match_operand:VQ 0 "s_register_operand" "=w") +- (unspec:VQ [(match_operand: 1 "s_register_operand" "r") +- (match_operand:VQ 2 "s_register_operand" "0") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VSET_LANE))] ++(define_expand "neon_vset_lane" ++ [(match_operand:VDQ 0 "s_register_operand" "=w") ++ (match_operand: 1 "s_register_operand" "r") ++ (match_operand:VDQ 2 "s_register_operand" "0") ++ (match_operand:SI 3 "immediate_operand" "i")] + "TARGET_NEON" + { +- rtx ops[4]; +- unsigned int regno = REGNO (operands[0]); +- unsigned int halfelts = GET_MODE_NUNITS (mode) / 2; + unsigned int elt = INTVAL (operands[3]); ++ neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); + +- neon_lane_bounds (operands[3], 0, halfelts * 2); ++ if (BYTES_BIG_ENDIAN) ++ { ++ unsigned int reg_nelts ++ = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (mode)); ++ elt ^= reg_nelts - 1; ++ } + +- ops[0] = gen_rtx_REG (mode, regno + 2 * (elt / halfelts)); +- ops[1] = operands[1]; +- ops[2] = GEN_INT (elt % halfelts); +- output_asm_insn ("vmov%?.\t%P0[%c2], %1", ops); ++ emit_insn (gen_vec_set_internal (operands[0], operands[1], ++ GEN_INT (1 << elt), operands[2])); ++ DONE; ++}) + +- return ""; +-} +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] +-) ++; See neon_vget_lanedi comment for reasons operands 2 & 3 are ignored. + +-(define_insn "neon_vset_lanev2di" +- [(set (match_operand:V2DI 0 "s_register_operand" "=w") +- (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r") +- (match_operand:V2DI 2 "s_register_operand" "0") +- (match_operand:SI 3 "immediate_operand" "i")] +- UNSPEC_VSET_LANE))] ++(define_expand "neon_vset_lanedi" ++ [(match_operand:DI 0 "s_register_operand" "=w") ++ (match_operand:DI 1 "s_register_operand" "r") ++ (match_operand:DI 2 "s_register_operand" "0") ++ (match_operand:SI 3 "immediate_operand" "i")] + "TARGET_NEON" + { +- rtx ops[2]; +- unsigned int regno = REGNO (operands[0]); +- unsigned int elt = INTVAL (operands[3]); +- +- neon_lane_bounds (operands[3], 0, 2); +- +- ops[0] = gen_rtx_REG (DImode, regno + 2 * elt); +- ops[1] = operands[1]; +- output_asm_insn ("vmov%?\t%P0, %Q1, %R1 @ v2di", ops); +- +- return ""; +-} +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] +-) ++ neon_lane_bounds (operands[3], 0, 1); ++ emit_move_insn (operands[0], operands[1]); ++ DONE; ++}) + + (define_expand "neon_vcreate" + [(match_operand:VDX 0 "s_register_operand" "") +@@ -2685,8 +3036,7 @@ + + (define_insn "neon_vdup_n" + [(set (match_operand:VX 0 "s_register_operand" "=w") +- (unspec:VX [(match_operand: 1 "s_register_operand" "r")] +- UNSPEC_VDUP_N))] ++ (vec_duplicate:VX (match_operand: 1 "s_register_operand" "r")))] + "TARGET_NEON" + "vdup%?.\t%0, %1" + ;; Assume this schedules like vmov. +@@ -2696,8 +3046,7 @@ + + (define_insn "neon_vdup_n" + [(set (match_operand:V32 0 "s_register_operand" "=w,w") +- (unspec:V32 [(match_operand: 1 "s_register_operand" "r,t")] +- UNSPEC_VDUP_N))] ++ (vec_duplicate:V32 (match_operand: 1 "s_register_operand" "r,t")))] + "TARGET_NEON" + "@ + vdup%?.\t%0, %1 +@@ -2707,61 +3056,76 @@ + (set_attr "neon_type" "neon_bp_simple")] + ) + +-(define_insn "neon_vdup_ndi" +- [(set (match_operand:DI 0 "s_register_operand" "=w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "r")] +- UNSPEC_VDUP_N))] ++(define_expand "neon_vdup_ndi" ++ [(match_operand:DI 0 "s_register_operand" "=w") ++ (match_operand:DI 1 "s_register_operand" "r")] + "TARGET_NEON" +- "vmov%?\t%P0, %Q1, %R1" +- [(set_attr "predicable" "yes") +- (set_attr "neon_type" "neon_bp_simple")] ++{ ++ emit_move_insn (operands[0], operands[1]); ++ DONE; ++} + ) + + (define_insn "neon_vdup_nv2di" +- [(set (match_operand:V2DI 0 "s_register_operand" "=w") +- (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r")] +- UNSPEC_VDUP_N))] ++ [(set (match_operand:V2DI 0 "s_register_operand" "=w,w") ++ (vec_duplicate:V2DI (match_operand:DI 1 "s_register_operand" "r,w")))] + "TARGET_NEON" +- "vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1" ++ "@ ++ vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1 ++ vmov%?\t%e0, %P1\;vmov%?\t%f0, %P1" + [(set_attr "predicable" "yes") + (set_attr "length" "8") + (set_attr "neon_type" "neon_bp_simple")] + ) + +-(define_insn "neon_vdup_lane" +- [(set (match_operand:VD 0 "s_register_operand" "=w") +- (unspec:VD [(match_operand:VD 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VDUP_LANE))] ++(define_insn "neon_vdup_lane_internal" ++ [(set (match_operand:VDQW 0 "s_register_operand" "=w") ++ (vec_duplicate:VDQW ++ (vec_select: ++ (match_operand: 1 "s_register_operand" "w") ++ (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] + "TARGET_NEON" + { +- neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (mode)); +- return "vdup.\t%P0, %P1[%c2]"; ++ if (BYTES_BIG_ENDIAN) ++ { ++ int elt = INTVAL (operands[2]); ++ elt = GET_MODE_NUNITS (mode) - 1 - elt; ++ operands[2] = GEN_INT (elt); ++ } ++ if () ++ return "vdup.\t%P0, %P1[%c2]"; ++ else ++ return "vdup.\t%q0, %P1[%c2]"; + } + ;; Assume this schedules like vmov. + [(set_attr "neon_type" "neon_bp_simple")] + ) + +-(define_insn "neon_vdup_lane" +- [(set (match_operand:VQ 0 "s_register_operand" "=w") +- (unspec:VQ [(match_operand: 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VDUP_LANE))] ++(define_expand "neon_vdup_lane" ++ [(match_operand:VDQW 0 "s_register_operand" "=w") ++ (match_operand: 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i")] + "TARGET_NEON" + { +- neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (mode)); +- return "vdup.\t%q0, %P1[%c2]"; +-} +- ;; Assume this schedules like vmov. +- [(set_attr "neon_type" "neon_bp_simple")] +-) ++ neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (mode)); ++ if (BYTES_BIG_ENDIAN) ++ { ++ unsigned int elt = INTVAL (operands[2]); ++ unsigned int reg_nelts ++ = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (mode)); ++ elt ^= reg_nelts - 1; ++ operands[2] = GEN_INT (elt); ++ } ++ emit_insn (gen_neon_vdup_lane_internal (operands[0], operands[1], ++ operands[2])); ++ DONE; ++}) + + ; Scalar index is ignored, since only zero is valid here. + (define_expand "neon_vdup_lanedi" +- [(set (match_operand:DI 0 "s_register_operand" "=w") +- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VDUP_LANE))] ++ [(match_operand:DI 0 "s_register_operand" "=w") ++ (match_operand:DI 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i")] + "TARGET_NEON" + { + neon_lane_bounds (operands[2], 0, 1); +@@ -2769,20 +3133,17 @@ + DONE; + }) + +-; Likewise. +-(define_insn "neon_vdup_lanev2di" +- [(set (match_operand:V2DI 0 "s_register_operand" "=w") +- (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] +- UNSPEC_VDUP_LANE))] ++; Likewise for v2di, as the DImode second operand has only a single element. ++(define_expand "neon_vdup_lanev2di" ++ [(match_operand:V2DI 0 "s_register_operand" "=w") ++ (match_operand:DI 1 "s_register_operand" "w") ++ (match_operand:SI 2 "immediate_operand" "i")] + "TARGET_NEON" + { + neon_lane_bounds (operands[2], 0, 1); +- return "vmov\t%e0, %P1\;vmov\t%f0, %P1"; +-} +- [(set_attr "length" "8") +- (set_attr "neon_type" "neon_bp_simple")] +-) ++ emit_insn (gen_neon_vdup_nv2di (operands[0], operands[1])); ++ DONE; ++}) + + ;; In this insn, operand 1 should be low, and operand 2 the high part of the + ;; dest vector. +@@ -2793,9 +3154,8 @@ + + (define_insn "neon_vcombine" + [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand:VDX 1 "s_register_operand" "w") +- (match_operand:VDX 2 "s_register_operand" "w")] +- UNSPEC_VCOMBINE))] ++ (vec_concat: (match_operand:VDX 1 "s_register_operand" "w") ++ (match_operand:VDX 2 "s_register_operand" "w")))] + "TARGET_NEON" + { + int dest = REGNO (operands[0]); +@@ -2835,10 +3195,31 @@ + (set_attr "neon_type" "neon_bp_simple")] + ) + +-(define_insn "neon_vget_high" +- [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand:VQX 1 "s_register_operand" "w")] +- UNSPEC_VGET_HIGH))] ++(define_insn "neon_vget_highv16qi" ++ [(set (match_operand:V8QI 0 "s_register_operand" "=w") ++ (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w") ++ (parallel [(const_int 8) (const_int 9) ++ (const_int 10) (const_int 11) ++ (const_int 12) (const_int 13) ++ (const_int 14) (const_int 15)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src + 2) ++ return "vmov\t%P0, %f1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_highv8hi" ++ [(set (match_operand:V4HI 0 "s_register_operand" "=w") ++ (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w") ++ (parallel [(const_int 4) (const_int 5) ++ (const_int 6) (const_int 7)])))] + "TARGET_NEON" + { + int dest = REGNO (operands[0]); +@@ -2852,10 +3233,133 @@ + [(set_attr "neon_type" "neon_bp_simple")] + ) + +-(define_insn "neon_vget_low" +- [(set (match_operand: 0 "s_register_operand" "=w") +- (unspec: [(match_operand:VQX 1 "s_register_operand" "w")] +- UNSPEC_VGET_LOW))] ++(define_insn "neon_vget_highv4si" ++ [(set (match_operand:V2SI 0 "s_register_operand" "=w") ++ (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w") ++ (parallel [(const_int 2) (const_int 3)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src + 2) ++ return "vmov\t%P0, %f1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_highv4sf" ++ [(set (match_operand:V2SF 0 "s_register_operand" "=w") ++ (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w") ++ (parallel [(const_int 2) (const_int 3)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src + 2) ++ return "vmov\t%P0, %f1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_highv2di" ++ [(set (match_operand:DI 0 "s_register_operand" "=w") ++ (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w") ++ (parallel [(const_int 1)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src + 2) ++ return "vmov\t%P0, %f1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_lowv16qi" ++ [(set (match_operand:V8QI 0 "s_register_operand" "=w") ++ (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w") ++ (parallel [(const_int 0) (const_int 1) ++ (const_int 2) (const_int 3) ++ (const_int 4) (const_int 5) ++ (const_int 6) (const_int 7)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src) ++ return "vmov\t%P0, %e1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_lowv8hi" ++ [(set (match_operand:V4HI 0 "s_register_operand" "=w") ++ (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w") ++ (parallel [(const_int 0) (const_int 1) ++ (const_int 2) (const_int 3)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src) ++ return "vmov\t%P0, %e1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_lowv4si" ++ [(set (match_operand:V2SI 0 "s_register_operand" "=w") ++ (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w") ++ (parallel [(const_int 0) (const_int 1)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src) ++ return "vmov\t%P0, %e1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_lowv4sf" ++ [(set (match_operand:V2SF 0 "s_register_operand" "=w") ++ (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w") ++ (parallel [(const_int 0) (const_int 1)])))] ++ "TARGET_NEON" ++{ ++ int dest = REGNO (operands[0]); ++ int src = REGNO (operands[1]); ++ ++ if (dest != src) ++ return "vmov\t%P0, %e1"; ++ else ++ return ""; ++} ++ [(set_attr "neon_type" "neon_bp_simple")] ++) ++ ++(define_insn "neon_vget_lowv2di" ++ [(set (match_operand:DI 0 "s_register_operand" "=w") ++ (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w") ++ (parallel [(const_int 0)])))] + "TARGET_NEON" + { + int dest = REGNO (operands[0]); +@@ -5048,3 +5552,205 @@ + emit_insn (gen_orn3_neon (operands[0], operands[1], operands[2])); + DONE; + }) ++ ++(define_insn "neon_vec_unpack_lo_" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (SE: (vec_select: ++ (match_operand:VU 1 "register_operand" "w") ++ (match_operand:VU 2 "vect_par_constant_low" ""))))] ++ "TARGET_NEON" ++ "vmovl. %q0, %e1" ++ [(set_attr "neon_type" "neon_shift_1")] ++) ++ ++(define_insn "neon_vec_unpack_hi_" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (SE: (vec_select: ++ (match_operand:VU 1 "register_operand" "w") ++ (match_operand:VU 2 "vect_par_constant_high" ""))))] ++ "TARGET_NEON" ++ "vmovl. %q0, %f1" ++ [(set_attr "neon_type" "neon_shift_1")] ++) ++ ++(define_expand "vec_unpack_hi_" ++ [(match_operand: 0 "register_operand" "") ++ (SE: (match_operand:VU 1 "register_operand"))] ++ "TARGET_NEON" ++ { ++ rtvec v = rtvec_alloc (/2) ; ++ rtx t1; ++ int i; ++ for (i = 0; i < (/2); i++) ++ RTVEC_ELT (v, i) = GEN_INT ((/2) + i); ++ ++ t1 = gen_rtx_PARALLEL (mode, v); ++ emit_insn (gen_neon_vec_unpack_hi_ (operands[0], ++ operands[1], ++ t1)); ++ DONE; ++ } ++) ++ ++(define_expand "vec_unpack_lo_" ++ [(match_operand: 0 "register_operand" "") ++ (SE: (match_operand:VU 1 "register_operand" ""))] ++ "TARGET_NEON" ++ { ++ rtvec v = rtvec_alloc (/2) ; ++ rtx t1; ++ int i; ++ for (i = 0; i < (/2) ; i++) ++ RTVEC_ELT (v, i) = GEN_INT (i); ++ t1 = gen_rtx_PARALLEL (mode, v); ++ emit_insn (gen_neon_vec_unpack_lo_ (operands[0], ++ operands[1], ++ t1)); ++ DONE; ++ } ++) ++ ++(define_insn "neon_vec_mult_lo_" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (mult: (SE: (vec_select: ++ (match_operand:VU 1 "register_operand" "w") ++ (match_operand:VU 2 "vect_par_constant_low" ""))) ++ (SE: (vec_select: ++ (match_operand:VU 3 "register_operand" "w") ++ (match_dup 2)))))] ++ "TARGET_NEON" ++ "vmull. %q0, %e1, %e3" ++ [(set_attr "neon_type" "neon_shift_1")] ++) ++ ++(define_expand "vec_widen_mult_lo_" ++ [(match_operand: 0 "register_operand" "") ++ (SE: (match_operand:VU 1 "register_operand" "")) ++ (SE: (match_operand:VU 2 "register_operand" ""))] ++ "TARGET_NEON" ++ { ++ rtvec v = rtvec_alloc (/2) ; ++ rtx t1; ++ int i; ++ for (i = 0; i < (/2) ; i++) ++ RTVEC_ELT (v, i) = GEN_INT (i); ++ t1 = gen_rtx_PARALLEL (mode, v); ++ ++ emit_insn (gen_neon_vec_mult_lo_ (operands[0], ++ operands[1], ++ t1, ++ operands[2])); ++ DONE; ++ } ++) ++ ++(define_insn "neon_vec_mult_hi_" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (mult: (SE: (vec_select: ++ (match_operand:VU 1 "register_operand" "w") ++ (match_operand:VU 2 "vect_par_constant_high" ""))) ++ (SE: (vec_select: ++ (match_operand:VU 3 "register_operand" "w") ++ (match_dup 2)))))] ++ "TARGET_NEON" ++ "vmull. %q0, %f1, %f3" ++ [(set_attr "neon_type" "neon_shift_1")] ++) ++ ++(define_expand "vec_widen_mult_hi_" ++ [(match_operand: 0 "register_operand" "") ++ (SE: (match_operand:VU 1 "register_operand" "")) ++ (SE: (match_operand:VU 2 "register_operand" ""))] ++ "TARGET_NEON" ++ { ++ rtvec v = rtvec_alloc (/2) ; ++ rtx t1; ++ int i; ++ for (i = 0; i < (/2) ; i++) ++ RTVEC_ELT (v, i) = GEN_INT (/2 + i); ++ t1 = gen_rtx_PARALLEL (mode, v); ++ ++ emit_insn (gen_neon_vec_mult_hi_ (operands[0], ++ operands[1], ++ t1, ++ operands[2])); ++ DONE; ++ ++ } ++) ++ ++;; Vectorize for non-neon-quad case ++(define_insn "neon_unpack_" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (SE: (match_operand:VDI 1 "register_operand" "w")))] ++ "TARGET_NEON" ++ "vmovl. %q0, %P1" ++ [(set_attr "neon_type" "neon_shift_1")] ++) ++ ++(define_expand "vec_unpack_lo_" ++ [(match_operand: 0 "register_operand" "") ++ (SE:(match_operand:VDI 1 "register_operand"))] ++ "TARGET_NEON" ++{ ++ rtx tmpreg = gen_reg_rtx (mode); ++ emit_insn (gen_neon_unpack_ (tmpreg, operands[1])); ++ emit_insn (gen_neon_vget_low (operands[0], tmpreg)); ++ ++ DONE; ++} ++) ++ ++(define_expand "vec_unpack_hi_" ++ [(match_operand: 0 "register_operand" "") ++ (SE:(match_operand:VDI 1 "register_operand"))] ++ "TARGET_NEON" ++{ ++ rtx tmpreg = gen_reg_rtx (mode); ++ emit_insn (gen_neon_unpack_ (tmpreg, operands[1])); ++ emit_insn (gen_neon_vget_high (operands[0], tmpreg)); ++ ++ DONE; ++} ++) ++ ++(define_insn "neon_vec_mult_" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (mult: (SE: ++ (match_operand:VDI 1 "register_operand" "w")) ++ (SE: ++ (match_operand:VDI 2 "register_operand" "w"))))] ++ "TARGET_NEON" ++ "vmull. %q0, %P1, %P2" ++ [(set_attr "neon_type" "neon_shift_1")] ++) ++ ++(define_expand "vec_widen_mult_hi_" ++ [(match_operand: 0 "register_operand" "") ++ (SE: (match_operand:VDI 1 "register_operand" "")) ++ (SE: (match_operand:VDI 2 "register_operand" ""))] ++ "TARGET_NEON" ++ { ++ rtx tmpreg = gen_reg_rtx (mode); ++ emit_insn (gen_neon_vec_mult_ (tmpreg, operands[1], operands[2])); ++ emit_insn (gen_neon_vget_high (operands[0], tmpreg)); ++ ++ DONE; ++ ++ } ++) ++ ++(define_expand "vec_widen_mult_lo_" ++ [(match_operand: 0 "register_operand" "") ++ (SE: (match_operand:VDI 1 "register_operand" "")) ++ (SE: (match_operand:VDI 2 "register_operand" ""))] ++ "TARGET_NEON" ++ { ++ rtx tmpreg = gen_reg_rtx (mode); ++ emit_insn (gen_neon_vec_mult_ (tmpreg, operands[1], operands[2])); ++ emit_insn (gen_neon_vget_low (operands[0], tmpreg)); ++ ++ DONE; ++ ++ } ++) +--- a/src/gcc/config/arm/neon.ml ++++ b/src/gcc/config/arm/neon.ml +@@ -709,7 +709,8 @@ + let ops = + [ + (* Addition. *) +- Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_64; ++ Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_32; ++ Vadd, [No_op], All (3, Dreg), "vadd", sign_invar_2, [S64; U64]; + Vadd, [], All (3, Qreg), "vaddQ", sign_invar_2, F32 :: su_8_64; + Vadd, [], Long, "vaddl", elts_same_2, su_8_32; + Vadd, [], Wide, "vaddw", elts_same_2, su_8_32; +@@ -758,7 +759,8 @@ + Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32]; + + (* Subtraction. *) +- Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_64; ++ Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_32; ++ Vsub, [No_op], All (3, Dreg), "vsub", sign_invar_2, [S64; U64]; + Vsub, [], All (3, Qreg), "vsubQ", sign_invar_2, F32 :: su_8_64; + Vsub, [], Long, "vsubl", elts_same_2, su_8_32; + Vsub, [], Wide, "vsubw", elts_same_2, su_8_32; +@@ -967,7 +969,8 @@ + Use_operands [| Corereg; Dreg; Immed |], + "vget_lane", get_lane, pf_su_8_32; + Vget_lane, +- [InfoWord; ++ [No_op; ++ InfoWord; + Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]]; + Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)], + Use_operands [| Corereg; Dreg; Immed |], +@@ -989,7 +992,8 @@ + Instruction_name ["vmov"]], + Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane", + set_lane, pf_su_8_32; +- Vset_lane, [Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]; ++ Vset_lane, [No_op; ++ Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]; + Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)], + Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane", + set_lane_notype, [S64; U64]; +@@ -1017,7 +1021,8 @@ + Use_operands [| Dreg; Corereg |], "vdup_n", bits_1, + pf_su_8_32; + Vdup_n, +- [Instruction_name ["vmov"]; ++ [No_op; ++ Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]], + Use_operands [| Dreg; Corereg |], "vdup_n", notype_1, + [S64; U64]; +@@ -1028,7 +1033,8 @@ + Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1, + pf_su_8_32; + Vdup_n, +- [Instruction_name ["vmov"]; ++ [No_op; ++ Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]; + Use_operands [| Dreg; Corereg; Corereg |]]], + Use_operands [| Qreg; Corereg |], "vdupQ_n", notype_1, +@@ -1043,7 +1049,8 @@ + Use_operands [| Dreg; Corereg |], + "vmov_n", bits_1, pf_su_8_32; + Vmov_n, +- [Builtin_name "vdup_n"; ++ [No_op; ++ Builtin_name "vdup_n"; + Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]], + Use_operands [| Dreg; Corereg |], +@@ -1056,7 +1063,8 @@ + Use_operands [| Qreg; Corereg |], + "vmovQ_n", bits_1, pf_su_8_32; + Vmov_n, +- [Builtin_name "vdupQ_n"; ++ [No_op; ++ Builtin_name "vdupQ_n"; + Instruction_name ["vmov"]; + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]; + Use_operands [| Dreg; Corereg; Corereg |]]], +@@ -1613,23 +1621,28 @@ + store_3, [P16; F32; U16; U32; S16; S32]; + + (* Logical operations. And. *) +- Vand, [], All (3, Dreg), "vand", notype_2, su_8_64; ++ Vand, [], All (3, Dreg), "vand", notype_2, su_8_32; ++ Vand, [No_op], All (3, Dreg), "vand", notype_2, [S64; U64]; + Vand, [], All (3, Qreg), "vandQ", notype_2, su_8_64; + + (* Or. *) +- Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_64; ++ Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_32; ++ Vorr, [No_op], All (3, Dreg), "vorr", notype_2, [S64; U64]; + Vorr, [], All (3, Qreg), "vorrQ", notype_2, su_8_64; + + (* Eor. *) +- Veor, [], All (3, Dreg), "veor", notype_2, su_8_64; ++ Veor, [], All (3, Dreg), "veor", notype_2, su_8_32; ++ Veor, [No_op], All (3, Dreg), "veor", notype_2, [S64; U64]; + Veor, [], All (3, Qreg), "veorQ", notype_2, su_8_64; + + (* Bic (And-not). *) +- Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_64; ++ Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_32; ++ Vbic, [No_op], All (3, Dreg), "vbic", notype_2, [S64; U64]; + Vbic, [], All (3, Qreg), "vbicQ", notype_2, su_8_64; + + (* Or-not. *) +- Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_64; ++ Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_32; ++ Vorn, [No_op], All (3, Dreg), "vorn", notype_2, [S64; U64]; + Vorn, [], All (3, Qreg), "vornQ", notype_2, su_8_64; + ] + +--- a/src/gcc/config/arm/predicates.md ++++ b/src/gcc/config/arm/predicates.md +@@ -101,6 +101,12 @@ + (and (match_code "const_int") + (match_test "const_ok_for_arm (INTVAL (op))"))) + ++;; A constant value which fits into two instructions, each taking ++;; an arithmetic constant operand for one of the words. ++(define_predicate "arm_immediate_di_operand" ++ (and (match_code "const_int,const_double") ++ (match_test "arm_const_double_by_immediates (op)"))) ++ + (define_predicate "arm_neg_immediate_operand" + (and (match_code "const_int") + (match_test "const_ok_for_arm (-INTVAL (op))"))) +@@ -109,6 +115,10 @@ + (and (match_code "const_int") + (match_test "const_ok_for_arm (~INTVAL (op))"))) + ++(define_predicate "const0_operand" ++ (and (match_code "const_int") ++ (match_test "INTVAL (op) == 0"))) ++ + ;; Something valid on the RHS of an ARM data-processing instruction + (define_predicate "arm_rhs_operand" + (ior (match_operand 0 "s_register_operand") +@@ -130,6 +140,10 @@ + (ior (match_operand 0 "arm_rhs_operand") + (match_operand 0 "arm_not_immediate_operand"))) + ++(define_predicate "arm_di_operand" ++ (ior (match_operand 0 "s_register_operand") ++ (match_operand 0 "arm_immediate_di_operand"))) ++ + ;; True if the operand is a memory reference which contains an + ;; offsettable address. + (define_predicate "offsettable_memory_operand" +@@ -187,11 +201,21 @@ + (and (match_code "plus,minus,ior,xor,and") + (match_test "mode == GET_MODE (op)"))) + ++;; True for plus/minus operators ++(define_special_predicate "plusminus_operator" ++ (and (match_code "plus,minus") ++ (match_test "mode == GET_MODE (op)"))) ++ + ;; True for logical binary operators. + (define_special_predicate "logical_binary_operator" + (and (match_code "ior,xor,and") + (match_test "mode == GET_MODE (op)"))) + ++;; True for commutative operators ++(define_special_predicate "commutative_binary_operator" ++ (and (match_code "ior,xor,and,plus") ++ (match_test "mode == GET_MODE (op)"))) ++ + ;; True for shift operators. + (define_special_predicate "shift_operator" + (and (ior (ior (and (match_code "mult") +@@ -218,6 +242,9 @@ + && (TARGET_FPA || TARGET_VFP)") + (match_code "unordered,ordered,unlt,unle,unge,ungt")))) + ++(define_special_predicate "lt_ge_comparison_operator" ++ (match_code "lt,ge")) ++ + (define_special_predicate "minmax_operator" + (and (match_code "smin,smax,umin,umax") + (match_test "mode == GET_MODE (op)"))) +@@ -303,23 +330,29 @@ + (and (match_code "reg,subreg,mem") + (match_operand 0 "nonimmediate_soft_df_operand")))) + +-(define_predicate "const_shift_operand" ++(define_predicate "const_shift_count" + (and (match_code "const_int") +- (ior (match_operand 0 "power_of_two_operand") +- (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32")))) ++ (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))) + + + (define_special_predicate "load_multiple_operation" + (match_code "parallel") + { + HOST_WIDE_INT count = XVECLEN (op, 0); +- int dest_regno; ++ unsigned dest_regno; + rtx src_addr; + HOST_WIDE_INT i = 1, base = 0; ++ HOST_WIDE_INT offset = 0; + rtx elt; ++ bool addr_reg_loaded = false; ++ bool update = false; ++ ++ if (low_irq_latency) ++ return false; + + if (count <= 1 +- || GET_CODE (XVECEXP (op, 0, 0)) != SET) ++ || GET_CODE (XVECEXP (op, 0, 0)) != SET ++ || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))) + return false; + + /* Check to see if this might be a write-back. */ +@@ -327,6 +360,7 @@ + { + i++; + base = 1; ++ update = true; + + /* Now check it more carefully. */ + if (GET_CODE (SET_DEST (elt)) != REG +@@ -345,6 +379,15 @@ + + dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); + src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); ++ if (GET_CODE (src_addr) == PLUS) ++ { ++ if (GET_CODE (XEXP (src_addr, 1)) != CONST_INT) ++ return false; ++ offset = INTVAL (XEXP (src_addr, 1)); ++ src_addr = XEXP (src_addr, 0); ++ } ++ if (!REG_P (src_addr)) ++ return false; + + for (; i < count; i++) + { +@@ -353,16 +396,28 @@ + if (GET_CODE (elt) != SET + || GET_CODE (SET_DEST (elt)) != REG + || GET_MODE (SET_DEST (elt)) != SImode +- || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base) ++ || REGNO (SET_DEST (elt)) <= dest_regno + || GET_CODE (SET_SRC (elt)) != MEM + || GET_MODE (SET_SRC (elt)) != SImode +- || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS +- || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) +- || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT +- || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4) ++ || ((GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS ++ || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) ++ || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT ++ || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != offset + (i - base) * 4) ++ && (!REG_P (XEXP (SET_SRC (elt), 0)) ++ || offset + (i - base) * 4 != 0))) + return false; ++ dest_regno = REGNO (SET_DEST (elt)); ++ if (dest_regno == REGNO (src_addr)) ++ addr_reg_loaded = true; + } +- ++ /* For Thumb, we only have updating instructions. If the pattern does ++ not describe an update, it must be because the address register is ++ in the list of loaded registers - on the hardware, this has the effect ++ of overriding the update. */ ++ if (update && addr_reg_loaded) ++ return false; ++ if (TARGET_THUMB1) ++ return update || addr_reg_loaded; + return true; + }) + +@@ -370,11 +425,14 @@ + (match_code "parallel") + { + HOST_WIDE_INT count = XVECLEN (op, 0); +- int src_regno; ++ unsigned src_regno; + rtx dest_addr; +- HOST_WIDE_INT i = 1, base = 0; ++ HOST_WIDE_INT i = 1, base = 0, offset = 0; + rtx elt; + ++ if (low_irq_latency) ++ return false; ++ + if (count <= 1 + || GET_CODE (XVECEXP (op, 0, 0)) != SET) + return false; +@@ -403,6 +461,16 @@ + src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); + dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); + ++ if (GET_CODE (dest_addr) == PLUS) ++ { ++ if (GET_CODE (XEXP (dest_addr, 1)) != CONST_INT) ++ return false; ++ offset = INTVAL (XEXP (dest_addr, 1)); ++ dest_addr = XEXP (dest_addr, 0); ++ } ++ if (!REG_P (dest_addr)) ++ return false; ++ + for (; i < count; i++) + { + elt = XVECEXP (op, 0, i); +@@ -410,14 +478,17 @@ + if (GET_CODE (elt) != SET + || GET_CODE (SET_SRC (elt)) != REG + || GET_MODE (SET_SRC (elt)) != SImode +- || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base) ++ || REGNO (SET_SRC (elt)) <= src_regno + || GET_CODE (SET_DEST (elt)) != MEM + || GET_MODE (SET_DEST (elt)) != SImode +- || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS +- || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) +- || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT +- || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4) ++ || ((GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS ++ || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) ++ || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT ++ || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != offset + (i - base) * 4) ++ && (!REG_P (XEXP (SET_DEST (elt), 0)) ++ || offset + (i - base) * 4 != 0))) + return false; ++ src_regno = REGNO (SET_SRC (elt)); + } + + return true; +@@ -514,13 +585,15 @@ + (define_predicate "imm_for_neon_logic_operand" + (match_code "const_vector") + { +- return neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL); ++ return (TARGET_NEON ++ && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); + }) + + (define_predicate "imm_for_neon_inv_logic_operand" + (match_code "const_vector") + { +- return neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL); ++ return (TARGET_NEON ++ && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); + }) + + (define_predicate "neon_logic_op2" +@@ -534,5 +607,76 @@ + ;; TODO: We could check lane numbers more precisely based on the mode. + (define_predicate "neon_lane_number" + (and (match_code "const_int") +- (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7"))) ++ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15"))) ++;; Predicates for named expanders that overlap multiple ISAs. ++ ++(define_predicate "cmpdi_operand" ++ (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK") ++ (and (match_test "TARGET_ARM") ++ (match_operand 0 "cirrus_fp_register")) ++ (and (match_test "TARGET_32BIT") ++ (match_operand 0 "arm_di_operand")))) ++ ++;; True if the operand is memory reference suitable for a ldrex/strex. ++(define_predicate "arm_sync_memory_operand" ++ (and (match_operand 0 "memory_operand") ++ (match_code "reg" "0"))) + ++;; Predicates for parallel expanders based on mode. ++(define_special_predicate "vect_par_constant_high" ++ (match_code "parallel") ++{ ++ HOST_WIDE_INT count = XVECLEN (op, 0); ++ int i; ++ int base = GET_MODE_NUNITS (mode); ++ ++ if ((count < 1) ++ || (count != base/2)) ++ return false; ++ ++ if (!VECTOR_MODE_P (mode)) ++ return false; ++ ++ for (i = 0; i < count; i++) ++ { ++ rtx elt = XVECEXP (op, 0, i); ++ int val; ++ ++ if (GET_CODE (elt) != CONST_INT) ++ return false; ++ ++ val = INTVAL (elt); ++ if (val != (base/2) + i) ++ return false; ++ } ++ return true; ++}) ++ ++(define_special_predicate "vect_par_constant_low" ++ (match_code "parallel") ++{ ++ HOST_WIDE_INT count = XVECLEN (op, 0); ++ int i; ++ int base = GET_MODE_NUNITS (mode); ++ ++ if ((count < 1) ++ || (count != base/2)) ++ return false; ++ ++ if (!VECTOR_MODE_P (mode)) ++ return false; ++ ++ for (i = 0; i < count; i++) ++ { ++ rtx elt = XVECEXP (op, 0, i); ++ int val; ++ ++ if (GET_CODE (elt) != CONST_INT) ++ return false; ++ ++ val = INTVAL (elt); ++ if (val != i) ++ return false; ++ } ++ return true; ++}) +--- a/src/gcc/config/arm/sfp-machine.h ++++ b/src/gcc/config/arm/sfp-machine.h +@@ -99,7 +99,7 @@ + #define __fixdfdi __aeabi_d2lz + #define __fixunsdfdi __aeabi_d2ulz + #define __floatdidf __aeabi_l2d +-#define __extendhfsf2 __gnu_h2f_ieee +-#define __truncsfhf2 __gnu_f2h_ieee ++#define __extendhfsf2 __aeabi_h2f ++#define __truncsfhf2 __aeabi_f2h + + #endif /* __ARM_EABI__ */ +--- a/src/gcc/config/arm/sync.md ++++ b/src/gcc/config/arm/sync.md +@@ -0,0 +1,602 @@ ++;; Machine description for ARM processor synchronization primitives. ++;; Copyright (C) 2010 Free Software Foundation, Inc. ++;; Written by Marcus Shawcroft (marcus.shawcroft@arm.com) ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . */ ++ ++;; ARMV6 introduced ldrex and strex instruction. These instruction ++;; access SI width data. In order to implement synchronization ++;; primitives for the narrower QI and HI modes we insert appropriate ++;; AND/OR sequences into the synchronization loop to mask out the ++;; relevant component of an SI access. ++ ++(define_expand "memory_barrier" ++ [(set (match_dup 0) ++ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))] ++ "TARGET_HAVE_MEMORY_BARRIER" ++{ ++ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); ++ MEM_VOLATILE_P (operands[0]) = 1; ++}) ++ ++(define_expand "sync_compare_and_swapsi" ++ [(set (match_operand:SI 0 "s_register_operand") ++ (unspec_volatile:SI [(match_operand:SI 1 "memory_operand") ++ (match_operand:SI 2 "s_register_operand") ++ (match_operand:SI 3 "s_register_operand")] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omrn; ++ generator.u.omrn = gen_arm_sync_compare_and_swapsi; ++ arm_expand_sync (SImode, &generator, operands[0], operands[1], operands[2], ++ operands[3]); ++ DONE; ++ }) ++ ++(define_mode_iterator NARROW [QI HI]) ++ ++(define_expand "sync_compare_and_swap" ++ [(set (match_operand:NARROW 0 "s_register_operand") ++ (unspec_volatile:NARROW [(match_operand:NARROW 1 "memory_operand") ++ (match_operand:NARROW 2 "s_register_operand") ++ (match_operand:NARROW 3 "s_register_operand")] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omrn; ++ generator.u.omrn = gen_arm_sync_compare_and_swap; ++ arm_expand_sync (mode, &generator, operands[0], operands[1], ++ operands[2], operands[3]); ++ DONE; ++ }) ++ ++(define_expand "sync_lock_test_and_setsi" ++ [(match_operand:SI 0 "s_register_operand") ++ (match_operand:SI 1 "memory_operand") ++ (match_operand:SI 2 "s_register_operand")] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_lock_test_and_setsi; ++ arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, ++ operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_lock_test_and_set" ++ [(match_operand:NARROW 0 "s_register_operand") ++ (match_operand:NARROW 1 "memory_operand") ++ (match_operand:NARROW 2 "s_register_operand")] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_lock_test_and_set; ++ arm_expand_sync (mode, &generator, operands[0], operands[1], NULL, ++ operands[2]); ++ DONE; ++ }) ++ ++(define_code_iterator syncop [plus minus ior xor and]) ++ ++(define_code_attr sync_optab [(ior "ior") ++ (xor "xor") ++ (and "and") ++ (plus "add") ++ (minus "sub")]) ++ ++(define_code_attr sync_clobber [(ior "=&r") ++ (and "=&r") ++ (xor "X") ++ (plus "X") ++ (minus "X")]) ++ ++(define_code_attr sync_t2_reqd [(ior "4") ++ (and "4") ++ (xor "*") ++ (plus "*") ++ (minus "*")]) ++ ++(define_expand "sync_si" ++ [(match_operand:SI 0 "memory_operand") ++ (match_operand:SI 1 "s_register_operand") ++ (syncop:SI (match_dup 0) (match_dup 1))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_si; ++ arm_expand_sync (SImode, &generator, NULL, operands[0], NULL, operands[1]); ++ DONE; ++ }) ++ ++(define_expand "sync_nandsi" ++ [(match_operand:SI 0 "memory_operand") ++ (match_operand:SI 1 "s_register_operand") ++ (not:SI (and:SI (match_dup 0) (match_dup 1)))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_nandsi; ++ arm_expand_sync (SImode, &generator, NULL, operands[0], NULL, operands[1]); ++ DONE; ++ }) ++ ++(define_expand "sync_" ++ [(match_operand:NARROW 0 "memory_operand") ++ (match_operand:NARROW 1 "s_register_operand") ++ (syncop:NARROW (match_dup 0) (match_dup 1))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_; ++ arm_expand_sync (mode, &generator, NULL, operands[0], NULL, ++ operands[1]); ++ DONE; ++ }) ++ ++(define_expand "sync_nand" ++ [(match_operand:NARROW 0 "memory_operand") ++ (match_operand:NARROW 1 "s_register_operand") ++ (not:NARROW (and:NARROW (match_dup 0) (match_dup 1)))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_nand; ++ arm_expand_sync (mode, &generator, NULL, operands[0], NULL, ++ operands[1]); ++ DONE; ++ }) ++ ++(define_expand "sync_new_si" ++ [(match_operand:SI 0 "s_register_operand") ++ (match_operand:SI 1 "memory_operand") ++ (match_operand:SI 2 "s_register_operand") ++ (syncop:SI (match_dup 1) (match_dup 2))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_si; ++ arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, ++ operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_new_nandsi" ++ [(match_operand:SI 0 "s_register_operand") ++ (match_operand:SI 1 "memory_operand") ++ (match_operand:SI 2 "s_register_operand") ++ (not:SI (and:SI (match_dup 1) (match_dup 2)))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_nandsi; ++ arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, ++ operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_new_" ++ [(match_operand:NARROW 0 "s_register_operand") ++ (match_operand:NARROW 1 "memory_operand") ++ (match_operand:NARROW 2 "s_register_operand") ++ (syncop:NARROW (match_dup 1) (match_dup 2))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_; ++ arm_expand_sync (mode, &generator, operands[0], operands[1], ++ NULL, operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_new_nand" ++ [(match_operand:NARROW 0 "s_register_operand") ++ (match_operand:NARROW 1 "memory_operand") ++ (match_operand:NARROW 2 "s_register_operand") ++ (not:NARROW (and:NARROW (match_dup 1) (match_dup 2)))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_new_nand; ++ arm_expand_sync (mode, &generator, operands[0], operands[1], ++ NULL, operands[2]); ++ DONE; ++ }); ++ ++(define_expand "sync_old_si" ++ [(match_operand:SI 0 "s_register_operand") ++ (match_operand:SI 1 "memory_operand") ++ (match_operand:SI 2 "s_register_operand") ++ (syncop:SI (match_dup 1) (match_dup 2))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_old_si; ++ arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, ++ operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_old_nandsi" ++ [(match_operand:SI 0 "s_register_operand") ++ (match_operand:SI 1 "memory_operand") ++ (match_operand:SI 2 "s_register_operand") ++ (not:SI (and:SI (match_dup 1) (match_dup 2)))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_old_nandsi; ++ arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, ++ operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_old_" ++ [(match_operand:NARROW 0 "s_register_operand") ++ (match_operand:NARROW 1 "memory_operand") ++ (match_operand:NARROW 2 "s_register_operand") ++ (syncop:NARROW (match_dup 1) (match_dup 2))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_old_; ++ arm_expand_sync (mode, &generator, operands[0], operands[1], ++ NULL, operands[2]); ++ DONE; ++ }) ++ ++(define_expand "sync_old_nand" ++ [(match_operand:NARROW 0 "s_register_operand") ++ (match_operand:NARROW 1 "memory_operand") ++ (match_operand:NARROW 2 "s_register_operand") ++ (not:NARROW (and:NARROW (match_dup 1) (match_dup 2)))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ struct arm_sync_generator generator; ++ generator.op = arm_sync_generator_omn; ++ generator.u.omn = gen_arm_sync_old_nand; ++ arm_expand_sync (mode, &generator, operands[0], operands[1], ++ NULL, operands[2]); ++ DONE; ++ }) ++ ++(define_insn "arm_sync_compare_and_swapsi" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "arm_sync_memory_operand" "+Q") ++ (match_operand:SI 2 "s_register_operand" "r") ++ (match_operand:SI 3 "s_register_operand" "r")] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP)) ++ (set (match_dup 1) (unspec_volatile:SI [(match_dup 2)] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP)) ++ (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP)) ++ ] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_required_value" "2") ++ (set_attr "sync_new_value" "3") ++ (set_attr "sync_t1" "0") ++ (set_attr "conds" "clob") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_compare_and_swap" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (zero_extend:SI ++ (unspec_volatile:NARROW ++ [(match_operand:NARROW 1 "arm_sync_memory_operand" "+Q") ++ (match_operand:SI 2 "s_register_operand" "r") ++ (match_operand:SI 3 "s_register_operand" "r")] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP))) ++ (set (match_dup 1) (unspec_volatile:NARROW [(match_dup 2)] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP)) ++ (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)] ++ VUNSPEC_SYNC_COMPARE_AND_SWAP)) ++ ] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_required_value" "2") ++ (set_attr "sync_new_value" "3") ++ (set_attr "sync_t1" "0") ++ (set_attr "conds" "clob") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_lock_test_and_setsi" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (match_operand:SI 1 "arm_sync_memory_operand" "+Q")) ++ (set (match_dup 1) ++ (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")] ++ VUNSPEC_SYNC_LOCK)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_release_barrier" "no") ++ (set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "3") ++ (set_attr "conds" "clob") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_lock_test_and_set" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (zero_extend:SI (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))) ++ (set (match_dup 1) ++ (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")] ++ VUNSPEC_SYNC_LOCK)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_release_barrier" "no") ++ (set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "3") ++ (set_attr "conds" "clob") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_new_si" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(syncop:SI ++ (match_operand:SI 1 "arm_sync_memory_operand" "+Q") ++ (match_operand:SI 2 "s_register_operand" "r")) ++ ] ++ VUNSPEC_SYNC_NEW_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:SI [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_NEW_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "3") ++ (set_attr "sync_op" "") ++ (set_attr "conds" "clob") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_new_nandsi" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(not:SI (and:SI ++ (match_operand:SI 1 "arm_sync_memory_operand" "+Q") ++ (match_operand:SI 2 "s_register_operand" "r"))) ++ ] ++ VUNSPEC_SYNC_NEW_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:SI [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_NEW_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "3") ++ (set_attr "sync_op" "nand") ++ (set_attr "conds" "clob") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_new_" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(syncop:SI ++ (zero_extend:SI ++ (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) ++ (match_operand:SI 2 "s_register_operand" "r")) ++ ] ++ VUNSPEC_SYNC_NEW_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_NEW_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r"))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "3") ++ (set_attr "sync_op" "") ++ (set_attr "conds" "clob") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_new_nand" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI ++ [(not:SI ++ (and:SI ++ (zero_extend:SI ++ (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) ++ (match_operand:SI 2 "s_register_operand" "r"))) ++ ] VUNSPEC_SYNC_NEW_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_NEW_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "0") ++ (set_attr "sync_t2" "3") ++ (set_attr "sync_op" "nand") ++ (set_attr "conds" "clob") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_old_si" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(syncop:SI ++ (match_operand:SI 1 "arm_sync_memory_operand" "+Q") ++ (match_operand:SI 2 "s_register_operand" "r")) ++ ] ++ VUNSPEC_SYNC_OLD_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:SI [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_OLD_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r")) ++ (clobber (match_scratch:SI 4 ""))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "3") ++ (set_attr "sync_t2" "") ++ (set_attr "sync_op" "") ++ (set_attr "conds" "clob") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_old_nandsi" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(not:SI (and:SI ++ (match_operand:SI 1 "arm_sync_memory_operand" "+Q") ++ (match_operand:SI 2 "s_register_operand" "r"))) ++ ] ++ VUNSPEC_SYNC_OLD_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:SI [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_OLD_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r")) ++ (clobber (match_scratch:SI 4 "=&r"))] ++ "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "3") ++ (set_attr "sync_t2" "4") ++ (set_attr "sync_op" "nand") ++ (set_attr "conds" "clob") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_old_" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(syncop:SI ++ (zero_extend:SI ++ (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) ++ (match_operand:SI 2 "s_register_operand" "r")) ++ ] ++ VUNSPEC_SYNC_OLD_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_OLD_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r")) ++ (clobber (match_scratch:SI 4 ""))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "3") ++ (set_attr "sync_t2" "") ++ (set_attr "sync_op" "") ++ (set_attr "conds" "clob") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "arm_sync_old_nand" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(not:SI (and:SI ++ (zero_extend:SI ++ (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) ++ (match_operand:SI 2 "s_register_operand" "r"))) ++ ] ++ VUNSPEC_SYNC_OLD_OP)) ++ (set (match_dup 1) ++ (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)] ++ VUNSPEC_SYNC_OLD_OP)) ++ (clobber (reg:CC CC_REGNUM)) ++ (clobber (match_scratch:SI 3 "=&r")) ++ (clobber (match_scratch:SI 4 "=&r"))] ++ "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_sync_insn (insn, operands); ++ } ++ [(set_attr "sync_result" "0") ++ (set_attr "sync_memory" "1") ++ (set_attr "sync_new_value" "2") ++ (set_attr "sync_t1" "3") ++ (set_attr "sync_t2" "4") ++ (set_attr "sync_op" "nand") ++ (set_attr "conds" "clob") ++ (set_attr "predicable" "no")]) ++ ++(define_insn "*memory_barrier" ++ [(set (match_operand:BLK 0 "" "") ++ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))] ++ "TARGET_HAVE_MEMORY_BARRIER" ++ { ++ return arm_output_memory_barrier (operands); ++ } ++ [(set_attr "length" "4") ++ (set_attr "conds" "unconditional") ++ (set_attr "predicable" "no")]) ++ +--- a/src/gcc/config/arm/t-arm ++++ b/src/gcc/config/arm/t-arm +@@ -18,20 +18,33 @@ + # along with GCC; see the file COPYING3. If not see + # . + +-MD_INCLUDES= $(srcdir)/config/arm/arm-tune.md \ +- $(srcdir)/config/arm/predicates.md \ +- $(srcdir)/config/arm/arm-generic.md \ +- $(srcdir)/config/arm/arm1020e.md \ +- $(srcdir)/config/arm/arm1026ejs.md \ +- $(srcdir)/config/arm/arm1136jfs.md \ +- $(srcdir)/config/arm/arm926ejs.md \ +- $(srcdir)/config/arm/cirrus.md \ +- $(srcdir)/config/arm/fpa.md \ +- $(srcdir)/config/arm/vec-common.md \ +- $(srcdir)/config/arm/iwmmxt.md \ +- $(srcdir)/config/arm/vfp.md \ +- $(srcdir)/config/arm/neon.md \ +- $(srcdir)/config/arm/thumb2.md ++MD_INCLUDES= $(srcdir)/config/arm/arm-tune.md \ ++ $(srcdir)/config/arm/predicates.md \ ++ $(srcdir)/config/arm/arm-generic.md \ ++ $(srcdir)/config/arm/arm1020e.md \ ++ $(srcdir)/config/arm/arm1026ejs.md \ ++ $(srcdir)/config/arm/arm1136jfs.md \ ++ $(srcdir)/config/arm/arm926ejs.md \ ++ $(srcdir)/config/arm/cirrus.md \ ++ $(srcdir)/config/arm/fpa.md \ ++ $(srcdir)/config/arm/vec-common.md \ ++ $(srcdir)/config/arm/iwmmxt.md \ ++ $(srcdir)/config/arm/vfp.md \ ++ $(srcdir)/config/arm/cortex-a5.md \ ++ $(srcdir)/config/arm/cortex-a8.md \ ++ $(srcdir)/config/arm/cortex-a9.md \ ++ $(srcdir)/config/arm/cortex-a9-neon.md \ ++ $(srcdir)/config/arm/cortex-r4.md \ ++ $(srcdir)/config/arm/cortex-r4f.md \ ++ $(srcdir)/config/arm/cortex-m4.md \ ++ $(srcdir)/config/arm/cortex-m4-fpu.md \ ++ $(srcdir)/config/arm/vfp11.md \ ++ $(srcdir)/config/arm/ldmstm.md \ ++ $(srcdir)/config/arm/thumb2.md \ ++ $(srcdir)/config/arm/neon.md \ ++ $(srcdir)/config/arm/sync.md \ ++ $(srcdir)/config/arm/cortex-a8-neon.md \ ++ $(srcdir)/config/arm/constraints.md + + LIB1ASMSRC = arm/lib1funcs.asm + LIB1ASMFUNCS = _thumb1_case_sqi _thumb1_case_uqi _thumb1_case_shi \ +@@ -45,6 +58,15 @@ + $(srcdir)/config/arm/arm-cores.def > \ + $(srcdir)/config/arm/arm-tune.md + ++arm.o: $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ ++ $(RTL_H) $(TREE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \ ++ insn-config.h conditions.h output.h \ ++ $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \ ++ $(EXPR_H) $(OPTABS_H) toplev.h $(RECOG_H) $(CGRAPH_H) \ ++ $(GGC_H) except.h $(C_PRAGMA_H) $(INTEGRATE_H) $(TM_P_H) \ ++ $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \ ++ intl.h libfuncs.h $(PARAMS_H) ++ + arm-c.o: $(srcdir)/config/arm/arm-c.c $(CONFIG_H) $(SYSTEM_H) \ + coretypes.h $(TM_H) $(TREE_H) output.h $(C_COMMON_H) + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ +--- a/src/gcc/config/arm/thumb2.md ++++ b/src/gcc/config/arm/thumb2.md +@@ -55,7 +55,7 @@ + [(set (match_operand:SI 0 "s_register_operand" "=r") + (and:SI (not:SI (match_operator:SI 4 "shift_operator" + [(match_operand:SI 2 "s_register_operand" "r") +- (match_operand:SI 3 "const_int_operand" "M")])) ++ (match_operand:SI 3 "const_shift_count" "M")])) + (match_operand:SI 1 "s_register_operand" "r")))] + "TARGET_THUMB2" + "bic%?\\t%0, %1, %2%S4" +@@ -124,7 +124,7 @@ + [(set (match_operand:SI 0 "s_register_operand" "=r") + (not:SI (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "const_int_operand" "M")])))] ++ (match_operand:SI 2 "const_shift_count" "M")])))] + "TARGET_THUMB2" + "mvn%?\\t%0, %1%S3" + [(set_attr "predicable" "yes") +@@ -136,7 +136,7 @@ + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "const_int_operand" "M")])) ++ (match_operand:SI 2 "const_shift_count" "M")])) + (const_int 0))) + (set (match_operand:SI 0 "s_register_operand" "=r") + (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))] +@@ -151,7 +151,7 @@ + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "const_int_operand" "M")])) ++ (match_operand:SI 2 "const_shift_count" "M")])) + (const_int 0))) + (clobber (match_scratch:SI 0 "=r"))] + "TARGET_THUMB2" +@@ -223,9 +223,14 @@ + (set_attr "neg_pool_range" "*,*,*,0,*")] + ) + ++;; We have two alternatives here for memory loads (and similarly for stores) ++;; to reflect the fact that the permissible constant pool ranges differ ++;; between ldr instructions taking low regs and ldr instructions taking high ++;; regs. The high register alternatives are not taken into account when ++;; choosing register preferences in order to reflect their expense. + (define_insn "*thumb2_movsi_insn" +- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m") +- (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,rk"))] ++ [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l, *hk,m,*m") ++ (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,*mi,l,*hk"))] + "TARGET_THUMB2 && ! TARGET_IWMMXT + && !(TARGET_HARD_FLOAT && TARGET_VFP) + && ( register_operand (operands[0], SImode) +@@ -236,11 +241,13 @@ + mvn%?\\t%0, #%B1 + movw%?\\t%0, %1 + ldr%?\\t%0, %1 ++ ldr%?\\t%0, %1 ++ str%?\\t%1, %0 + str%?\\t%1, %0" +- [(set_attr "type" "*,*,*,*,load1,store1") ++ [(set_attr "type" "*,*,*,*,load1,load1,store1,store1") + (set_attr "predicable" "yes") +- (set_attr "pool_range" "*,*,*,*,4096,*") +- (set_attr "neg_pool_range" "*,*,*,*,0,*")] ++ (set_attr "pool_range" "*,*,*,*,1020,4096,*,*") ++ (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")] + ) + + (define_insn "tls_load_dot_plus_four" +@@ -312,8 +319,8 @@ + " + [(set_attr "length" "8,12,16,8,8") + (set_attr "type" "*,*,*,load2,store2") +- (set_attr "pool_range" "1020") +- (set_attr "neg_pool_range" "0")] ++ (set_attr "pool_range" "*,*,*,1020,*") ++ (set_attr "neg_pool_range" "*,*,*,0,*")] + ) + + (define_insn "*thumb2_cmpsi_shiftsi" +@@ -321,7 +328,7 @@ + (compare:CC (match_operand:SI 0 "s_register_operand" "r") + (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "const_int_operand" "M")])))] ++ (match_operand:SI 2 "const_shift_count" "M")])))] + "TARGET_THUMB2" + "cmp%?\\t%0, %1%S3" + [(set_attr "conds" "set") +@@ -333,7 +340,7 @@ + [(set (reg:CC_SWP CC_REGNUM) + (compare:CC_SWP (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "const_int_operand" "M")]) ++ (match_operand:SI 2 "const_shift_count" "M")]) + (match_operand:SI 0 "s_register_operand" "r")))] + "TARGET_THUMB2" + "cmp%?\\t%0, %1%S3" +@@ -347,7 +354,7 @@ + (compare:CC (match_operand:SI 0 "s_register_operand" "r") + (neg:SI (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "const_int_operand" "M")]))))] ++ (match_operand:SI 2 "const_shift_count" "M")]))))] + "TARGET_THUMB2" + "cmn%?\\t%0, %1%S3" + [(set_attr "conds" "set") +@@ -459,8 +466,8 @@ + (match_operator:SI 1 "shiftable_operator" + [(match_operator:SI 3 "shift_operator" + [(match_operand:SI 4 "s_register_operand" "r") +- (match_operand:SI 5 "const_int_operand" "M")]) +- (match_operand:SI 2 "s_register_operand" "r")]))] ++ (match_operand:SI 5 "const_shift_count" "M")]) ++ (match_operand:SI 2 "s_register_operand" "rk")]))] + "TARGET_THUMB2" + "%i1%?\\t%0, %2, %4%S3" + [(set_attr "predicable" "yes") +@@ -492,7 +499,7 @@ + (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator" + [(match_operator:SI 3 "shift_operator" + [(match_operand:SI 4 "s_register_operand" "r") +- (match_operand:SI 5 "const_int_operand" "M")]) ++ (match_operand:SI 5 "const_shift_count" "M")]) + (match_operand:SI 2 "s_register_operand" "r")]) + (const_int 0))) + (set (match_operand:SI 0 "s_register_operand" "=r") +@@ -510,7 +517,7 @@ + (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator" + [(match_operator:SI 3 "shift_operator" + [(match_operand:SI 4 "s_register_operand" "r") +- (match_operand:SI 5 "const_int_operand" "M")]) ++ (match_operand:SI 5 "const_shift_count" "M")]) + (match_operand:SI 2 "s_register_operand" "r")]) + (const_int 0))) + (clobber (match_scratch:SI 0 "=r"))] +@@ -526,7 +533,7 @@ + (minus:SI (match_operand:SI 1 "s_register_operand" "r") + (match_operator:SI 2 "shift_operator" + [(match_operand:SI 3 "s_register_operand" "r") +- (match_operand:SI 4 "const_int_operand" "M")])))] ++ (match_operand:SI 4 "const_shift_count" "M")])))] + "TARGET_THUMB2" + "sub%?\\t%0, %1, %3%S2" + [(set_attr "predicable" "yes") +@@ -540,7 +547,7 @@ + (minus:SI (match_operand:SI 1 "s_register_operand" "r") + (match_operator:SI 2 "shift_operator" + [(match_operand:SI 3 "s_register_operand" "r") +- (match_operand:SI 4 "const_int_operand" "M")])) ++ (match_operand:SI 4 "const_shift_count" "M")])) + (const_int 0))) + (set (match_operand:SI 0 "s_register_operand" "=r") + (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) +@@ -558,7 +565,7 @@ + (minus:SI (match_operand:SI 1 "s_register_operand" "r") + (match_operator:SI 2 "shift_operator" + [(match_operand:SI 3 "s_register_operand" "r") +- (match_operand:SI 4 "const_int_operand" "M")])) ++ (match_operand:SI 4 "const_shift_count" "M")])) + (const_int 0))) + (clobber (match_scratch:SI 0 "=r"))] + "TARGET_THUMB2" +@@ -592,42 +599,6 @@ + (set_attr "length" "6,10")] + ) + +-(define_insn "*thumb2_compare_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (match_operator:SI 1 "arm_comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_add_operand" "rI,L")])) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_THUMB2" +- "* +- if (operands[3] == const0_rtx) +- { +- if (GET_CODE (operands[1]) == LT) +- return \"lsr\\t%0, %2, #31\"; +- +- if (GET_CODE (operands[1]) == GE) +- return \"mvn\\t%0, %2\;lsr\\t%0, %0, #31\"; +- +- if (GET_CODE (operands[1]) == EQ) +- return \"rsbs\\t%0, %2, #1\;it\\tcc\;movcc\\t%0, #0\"; +- } +- +- if (GET_CODE (operands[1]) == NE) +- { +- if (which_alternative == 1) +- return \"adds\\t%0, %2, #%n3\;it\\tne\;movne\\t%0, #1\"; +- return \"subs\\t%0, %2, %3\;it\\tne\;movne\\t%0, #1\"; +- } +- if (which_alternative == 1) +- output_asm_insn (\"cmn\\t%2, #%n3\", operands); +- else +- output_asm_insn (\"cmp\\t%2, %3\", operands); +- return \"ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "14")] +-) +- + (define_insn "*thumb2_cond_move" + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (if_then_else:SI (match_operator 3 "equality_operator" +@@ -1047,6 +1018,18 @@ + (set_attr "length" "20")] + ) + ++;; Note: this is not predicable, to avoid issues with linker-generated ++;; interworking stubs. ++(define_insn "*thumb2_return" ++ [(returns)] ++ "TARGET_THUMB2" ++{ ++ return output_return_instruction (const_true_rtx, true, false, ++ ); ++} ++ [(set_attr "type" "load1") ++ (set_attr "length" "12")]) ++ + (define_insn_and_split "thumb2_eh_return" + [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")] + VUNSPEC_EH_RETURN) +@@ -1062,29 +1045,6 @@ + }" + ) + +-;; Peepholes and insns for 16-bit flag clobbering instructions. +-;; The conditional forms of these instructions do not clobber CC. +-;; However by the time peepholes are run it is probably too late to do +-;; anything useful with this information. +-(define_peephole2 +- [(set (match_operand:SI 0 "low_register_operand" "") +- (match_operator:SI 3 "thumb_16bit_operator" +- [(match_operand:SI 1 "low_register_operand" "") +- (match_operand:SI 2 "low_register_operand" "")]))] +- "TARGET_THUMB2 +- && (rtx_equal_p(operands[0], operands[1]) +- || GET_CODE(operands[3]) == PLUS +- || GET_CODE(operands[3]) == MINUS) +- && peep2_regno_dead_p(0, CC_REGNUM)" +- [(parallel +- [(set (match_dup 0) +- (match_op_dup 3 +- [(match_dup 1) +- (match_dup 2)])) +- (clobber (reg:CC CC_REGNUM))])] +- "" +-) +- + (define_insn "*thumb2_alusi3_short" + [(set (match_operand:SI 0 "s_register_operand" "=l") + (match_operator:SI 3 "thumb_16bit_operator" +@@ -1234,6 +1194,56 @@ + (set_attr "length" "2")] + ) + ++(define_insn "*thumb2_addsi3_compare0" ++ [(set (reg:CC_NOOV CC_REGNUM) ++ (compare:CC_NOOV ++ (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r") ++ (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL")) ++ (const_int 0))) ++ (set (match_operand:SI 0 "s_register_operand" "=l,l,r") ++ (plus:SI (match_dup 1) (match_dup 2)))] ++ "TARGET_THUMB2" ++ "* ++ HOST_WIDE_INT val; ++ ++ if (GET_CODE (operands[2]) == CONST_INT) ++ val = INTVAL (operands[2]); ++ else ++ val = 0; ++ ++ if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val))) ++ return \"subs\\t%0, %1, #%n2\"; ++ else ++ return \"adds\\t%0, %1, %2\"; ++ " ++ [(set_attr "conds" "set") ++ (set_attr "length" "2,2,4")] ++) ++ ++(define_insn "*thumb2_addsi3_compare0_scratch" ++ [(set (reg:CC_NOOV CC_REGNUM) ++ (compare:CC_NOOV ++ (plus:SI (match_operand:SI 0 "s_register_operand" "l, r") ++ (match_operand:SI 1 "arm_add_operand" "lPv,rIL")) ++ (const_int 0)))] ++ "TARGET_THUMB2" ++ "* ++ HOST_WIDE_INT val; ++ ++ if (GET_CODE (operands[1]) == CONST_INT) ++ val = INTVAL (operands[1]); ++ else ++ val = 0; ++ ++ if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val))) ++ return \"cmp\\t%0, #%n1\"; ++ else ++ return \"cmn\\t%0, %1\"; ++ " ++ [(set_attr "conds" "set") ++ (set_attr "length" "2,4")] ++) ++ + ;; 16-bit encodings of "muls" and "mul". We only use these when + ;; optimizing for size since "muls" is slow on all known + ;; implementations and since "mul" will be generated by +--- a/src/gcc/config/arm/uclinux-eabi.h ++++ b/src/gcc/config/arm/uclinux-eabi.h +@@ -50,6 +50,10 @@ + #undef ARM_DEFAULT_ABI + #define ARM_DEFAULT_ABI ARM_ABI_AAPCS_LINUX + ++#undef LINK_GCC_C_SEQUENCE_SPEC ++#define LINK_GCC_C_SEQUENCE_SPEC \ ++ "--start-group %G %L --end-group" ++ + /* Clear the instruction cache from `beg' to `end'. This makes an + inline system call to SYS_cacheflush. */ + #undef CLEAR_INSN_CACHE +--- a/src/gcc/config/arm/unwind-arm.c ++++ b/src/gcc/config/arm/unwind-arm.c +@@ -1196,8 +1196,6 @@ + ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1]; + + if (data[0] & uint32_highbit) +- phase2_call_unexpected_after_unwind = 1; +- else + { + data += rtti_count + 1; + /* Setup for entry to the handler. */ +@@ -1207,6 +1205,8 @@ + _Unwind_SetGR (context, 0, (_uw) ucbp); + return _URC_INSTALL_CONTEXT; + } ++ else ++ phase2_call_unexpected_after_unwind = 1; + } + if (data[0] & uint32_highbit) + data++; +--- a/src/gcc/config/arm/vec-common.md ++++ b/src/gcc/config/arm/vec-common.md +@@ -57,7 +57,8 @@ + [(set (match_operand:VALL 0 "s_register_operand" "") + (plus:VALL (match_operand:VALL 1 "s_register_operand" "") + (match_operand:VALL 2 "s_register_operand" "")))] +- "TARGET_NEON ++ "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) ++ || flag_unsafe_math_optimizations)) + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" + { + }) +@@ -66,7 +67,8 @@ + [(set (match_operand:VALL 0 "s_register_operand" "") + (minus:VALL (match_operand:VALL 1 "s_register_operand" "") + (match_operand:VALL 2 "s_register_operand" "")))] +- "TARGET_NEON ++ "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) ++ || flag_unsafe_math_optimizations)) + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" + { + }) +@@ -75,7 +77,9 @@ + [(set (match_operand:VALLW 0 "s_register_operand" "") + (mult:VALLW (match_operand:VALLW 1 "s_register_operand" "") + (match_operand:VALLW 2 "s_register_operand" "")))] +- "TARGET_NEON || (mode == V4HImode && TARGET_REALLY_IWMMXT)" ++ "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) ++ || flag_unsafe_math_optimizations)) ++ || (mode == V4HImode && TARGET_REALLY_IWMMXT)" + { + }) + +@@ -83,7 +87,8 @@ + [(set (match_operand:VALLW 0 "s_register_operand" "") + (smin:VALLW (match_operand:VALLW 1 "s_register_operand" "") + (match_operand:VALLW 2 "s_register_operand" "")))] +- "TARGET_NEON ++ "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) ++ || flag_unsafe_math_optimizations)) + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" + { + }) +@@ -101,7 +106,8 @@ + [(set (match_operand:VALLW 0 "s_register_operand" "") + (smax:VALLW (match_operand:VALLW 1 "s_register_operand" "") + (match_operand:VALLW 2 "s_register_operand" "")))] +- "TARGET_NEON ++ "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) ++ || flag_unsafe_math_optimizations)) + || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" + { + }) +--- a/src/gcc/config/arm/vfp.md ++++ b/src/gcc/config/arm/vfp.md +@@ -82,13 +82,16 @@ + " + [(set_attr "predicable" "yes") + (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") ++ (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,neon_ldr,neon_str") + (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") + (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] + ) + ++;; See thumb2.md:thumb2_movsi_insn for an explanation of the split ++;; high/low register alternatives for loads and stores here. + (define_insn "*thumb2_movsi_vfp" +- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv") +- (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))] ++ [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l,*hk,m,*m,*t,r, *t,*t, *Uv") ++ (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,*mi,l,*hk,r,*t,*t,*Uvi,*t"))] + "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT + && ( s_register_operand (operands[0], SImode) + || s_register_operand (operands[1], SImode))" +@@ -102,34 +105,37 @@ + case 3: + return \"movw%?\\t%0, %1\"; + case 4: +- return \"ldr%?\\t%0, %1\"; + case 5: +- return \"str%?\\t%1, %0\"; ++ return \"ldr%?\\t%0, %1\"; + case 6: +- return \"fmsr%?\\t%0, %1\\t%@ int\"; + case 7: +- return \"fmrs%?\\t%0, %1\\t%@ int\"; ++ return \"str%?\\t%1, %0\"; + case 8: ++ return \"fmsr%?\\t%0, %1\\t%@ int\"; ++ case 9: ++ return \"fmrs%?\\t%0, %1\\t%@ int\"; ++ case 10: + return \"fcpys%?\\t%0, %1\\t%@ int\"; +- case 9: case 10: ++ case 11: case 12: + return output_move_vfp (operands); + default: + gcc_unreachable (); + } + " + [(set_attr "predicable" "yes") +- (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_load,f_store") +- (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") +- (set_attr "neg_pool_range" "*,*,*,*, 0,*,*,*,*,1008,*")] ++ (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store") ++ (set_attr "neon_type" "*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") ++ (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*") ++ (set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] + ) + + + ;; DImode moves + + (define_insn "*arm_movdi_vfp" +- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv") ++ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,w,r,w,w, Uv") + (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8 + && ( register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" + "* +@@ -156,6 +162,49 @@ + } + " + [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") ++ (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") ++ (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) ++ (eq_attr "alternative" "5") ++ (if_then_else ++ (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1)) ++ (const_int 8) ++ (const_int 4))] ++ (const_int 4))) ++ (set_attr "pool_range" "*,1020,*,*,*,*,1020,*") ++ (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")] ++) ++ ++(define_insn "*arm_movdi_vfp_cortexa8" ++ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,!r,w,w, Uv") ++ (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8 ++ && ( register_operand (operands[0], DImode) ++ || register_operand (operands[1], DImode))" ++ "* ++ switch (which_alternative) ++ { ++ case 0: ++ return \"#\"; ++ case 1: ++ case 2: ++ return output_move_double (operands); ++ case 3: ++ return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; ++ case 4: ++ return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; ++ case 5: ++ if (TARGET_VFP_SINGLE) ++ return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\"; ++ else ++ return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; ++ case 6: case 7: ++ return output_move_vfp (operands); ++ default: ++ gcc_unreachable (); ++ } ++ " ++ [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") ++ (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") + (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) + (eq_attr "alternative" "5") + (if_then_else +@@ -194,6 +243,7 @@ + } + " + [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store") ++ (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") + (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) + (eq_attr "alternative" "5") + (if_then_else +@@ -348,6 +398,7 @@ + [(set_attr "predicable" "yes") + (set_attr "type" + "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") ++ (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") + (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*") + (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")] + ) +@@ -384,6 +435,7 @@ + [(set_attr "predicable" "yes") + (set_attr "type" + "r_2_f,f_2_r,fconsts,f_load,f_store,load1,store1,fcpys,*") ++ (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") + (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*") + (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] + ) +@@ -426,6 +478,7 @@ + " + [(set_attr "type" + "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*") ++ (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*") + (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8) + (eq_attr "alternative" "7") + (if_then_else +@@ -470,6 +523,7 @@ + " + [(set_attr "type" + "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*") ++ (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*") + (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8) + (eq_attr "alternative" "7") + (if_then_else +@@ -505,7 +559,8 @@ + fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" + [(set_attr "conds" "use") + (set_attr "length" "4,4,8,4,4,8,4,4,8") +- (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] ++ (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") ++ (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")] + ) + + (define_insn "*thumb2_movsfcc_vfp" +@@ -528,7 +583,8 @@ + ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" + [(set_attr "conds" "use") + (set_attr "length" "6,6,10,6,6,10,6,6,10") +- (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] ++ (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") ++ (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")] + ) + + (define_insn "*movdfcc_vfp" +@@ -551,7 +607,8 @@ + fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" + [(set_attr "conds" "use") + (set_attr "length" "4,4,8,4,4,8,4,4,8") +- (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] ++ (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") ++ (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")] + ) + + (define_insn "*thumb2_movdfcc_vfp" +@@ -574,7 +631,8 @@ + ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" + [(set_attr "conds" "use") + (set_attr "length" "6,6,10,6,6,10,6,6,10") +- (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] ++ (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") ++ (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")] + ) + + +@@ -1095,7 +1153,7 @@ + fcmpes%?\\t%0, %1 + fcmpezs%?\\t%0" + [(set_attr "predicable" "yes") +- (set_attr "type" "fcmpd")] ++ (set_attr "type" "fcmps")] + ) + + (define_insn "*cmpdf_vfp" +--- a/src/gcc/config/avr/avr.h ++++ b/src/gcc/config/avr/avr.h +@@ -232,7 +232,7 @@ + 32,33,34,35 \ + } + +-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () + + + #define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) +--- a/src/gcc/config/bfin/bfin.c ++++ b/src/gcc/config/bfin/bfin.c +@@ -2359,7 +2359,7 @@ + XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, picreg); + XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, cookie); + if (sibcall) +- XVECEXP (pat, 0, n++) = gen_rtx_RETURN (VOIDmode); ++ XVECEXP (pat, 0, n++) = ret_rtx; + else + XVECEXP (pat, 0, n++) = gen_rtx_CLOBBER (VOIDmode, retsreg); + call = emit_call_insn (pat); +--- a/src/gcc/config/cris/cris.c ++++ b/src/gcc/config/cris/cris.c +@@ -1771,7 +1771,7 @@ + we do that until they're fixed. Currently, all return insns in a + function must be the same (not really a limiting factor) so we need + to check that it doesn't change half-way through. */ +- emit_jump_insn (gen_rtx_RETURN (VOIDmode)); ++ emit_jump_insn (ret_rtx); + + CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack); + CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack); +--- a/src/gcc/config/h8300/h8300.c ++++ b/src/gcc/config/h8300/h8300.c +@@ -403,6 +403,10 @@ + restore er6 though, so bump up the cost. */ + h8300_move_ratio = 6; + } ++ ++ /* This target defaults to strict volatile bitfields. */ ++ if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) ++ flag_strict_volatile_bitfields = 1; + } + + /* Implement REG_CLASS_FROM_LETTER. +@@ -687,7 +691,7 @@ + /* Add the return instruction. */ + if (return_p) + { +- RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode); ++ RTVEC_ELT (vec, i) = ret_rtx; + i++; + } + +@@ -971,7 +975,7 @@ + } + + if (!returned_p) +- emit_jump_insn (gen_rtx_RETURN (VOIDmode)); ++ emit_jump_insn (ret_rtx); + } + + /* Return nonzero if the current function is an interrupt +--- a/src/gcc/config/i386/avxintrin.h ++++ b/src/gcc/config/i386/avxintrin.h +@@ -890,55 +890,55 @@ + } + + extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-_mm_maskload_pd (double const *__P, __m128d __M) ++_mm_maskload_pd (double const *__P, __m128i __M) + { + return (__m128d) __builtin_ia32_maskloadpd ((const __v2df *)__P, +- (__v2df)__M); ++ (__v2di)__M); + } + + extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-_mm_maskstore_pd (double *__P, __m128d __M, __m128d __A) ++_mm_maskstore_pd (double *__P, __m128i __M, __m128d __A) + { +- __builtin_ia32_maskstorepd ((__v2df *)__P, (__v2df)__M, (__v2df)__A); ++ __builtin_ia32_maskstorepd ((__v2df *)__P, (__v2di)__M, (__v2df)__A); + } + + extern __inline __m256d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-_mm256_maskload_pd (double const *__P, __m256d __M) ++_mm256_maskload_pd (double const *__P, __m256i __M) + { + return (__m256d) __builtin_ia32_maskloadpd256 ((const __v4df *)__P, +- (__v4df)__M); ++ (__v4di)__M); + } + + extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-_mm256_maskstore_pd (double *__P, __m256d __M, __m256d __A) ++_mm256_maskstore_pd (double *__P, __m256i __M, __m256d __A) + { +- __builtin_ia32_maskstorepd256 ((__v4df *)__P, (__v4df)__M, (__v4df)__A); ++ __builtin_ia32_maskstorepd256 ((__v4df *)__P, (__v4di)__M, (__v4df)__A); + } + + extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-_mm_maskload_ps (float const *__P, __m128 __M) ++_mm_maskload_ps (float const *__P, __m128i __M) + { + return (__m128) __builtin_ia32_maskloadps ((const __v4sf *)__P, +- (__v4sf)__M); ++ (__v4si)__M); + } + + extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-_mm_maskstore_ps (float *__P, __m128 __M, __m128 __A) ++_mm_maskstore_ps (float *__P, __m128i __M, __m128 __A) + { +- __builtin_ia32_maskstoreps ((__v4sf *)__P, (__v4sf)__M, (__v4sf)__A); ++ __builtin_ia32_maskstoreps ((__v4sf *)__P, (__v4si)__M, (__v4sf)__A); + } + + extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-_mm256_maskload_ps (float const *__P, __m256 __M) ++_mm256_maskload_ps (float const *__P, __m256i __M) + { + return (__m256) __builtin_ia32_maskloadps256 ((const __v8sf *)__P, +- (__v8sf)__M); ++ (__v8si)__M); + } + + extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-_mm256_maskstore_ps (float *__P, __m256 __M, __m256 __A) ++_mm256_maskstore_ps (float *__P, __m256i __M, __m256 __A) + { +- __builtin_ia32_maskstoreps256 ((__v8sf *)__P, (__v8sf)__M, (__v8sf)__A); ++ __builtin_ia32_maskstoreps256 ((__v8sf *)__P, (__v8si)__M, (__v8sf)__A); + } + + extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +--- a/src/gcc/config/i386/freebsd.h ++++ b/src/gcc/config/i386/freebsd.h +@@ -1,5 +1,6 @@ + /* Definitions for Intel 386 running FreeBSD with ELF format +- Copyright (C) 1996, 2000, 2002, 2004, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1996, 2000, 2002, 2004, 2007, 2011 ++ Free Software Foundation, Inc. + Contributed by Eric Youngdale. + Modified for stabs-in-ELF by H.J. Lu. + Adapted from GNU/Linux version by John Polstra. +@@ -138,3 +139,8 @@ + compiler get the contents of and std::numeric_limits correct. */ + #undef TARGET_96_ROUND_53_LONG_DOUBLE + #define TARGET_96_ROUND_53_LONG_DOUBLE (!TARGET_64BIT) ++ ++/* Support for i386 has been removed from FreeBSD 6.0 onward. */ ++#if FBSD_MAJOR >= 6 ++#define SUBTARGET32_DEFAULT_CPU "i486" ++#endif +--- a/src/gcc/config/i386/i386-builtin-types.def ++++ b/src/gcc/config/i386/i386-builtin-types.def +@@ -229,7 +229,7 @@ + DEF_FUNCTION_TYPE (V1DI, V1DI, V1DI) + DEF_FUNCTION_TYPE (V1DI, V2SI, V2SI) + DEF_FUNCTION_TYPE (V1DI, V8QI, V8QI) +-DEF_FUNCTION_TYPE (V2DF, PCV2DF, V2DF) ++DEF_FUNCTION_TYPE (V2DF, PCV2DF, V2DI) + DEF_FUNCTION_TYPE (V2DF, V2DF, DI) + DEF_FUNCTION_TYPE (V2DF, V2DF, INT) + DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE) +@@ -251,7 +251,7 @@ + DEF_FUNCTION_TYPE (V2SI, V2SI, SI) + DEF_FUNCTION_TYPE (V2SI, V2SI, V2SI) + DEF_FUNCTION_TYPE (V2SI, V4HI, V4HI) +-DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DF) ++DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DI) + DEF_FUNCTION_TYPE (V4DF, V4DF, INT) + DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF) + DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI) +@@ -260,7 +260,7 @@ + DEF_FUNCTION_TYPE (V4HI, V4HI, SI) + DEF_FUNCTION_TYPE (V4HI, V4HI, V4HI) + DEF_FUNCTION_TYPE (V4HI, V8QI, V8QI) +-DEF_FUNCTION_TYPE (V4SF, PCV4SF, V4SF) ++DEF_FUNCTION_TYPE (V4SF, PCV4SF, V4SI) + DEF_FUNCTION_TYPE (V4SF, V4SF, DI) + DEF_FUNCTION_TYPE (V4SF, V4SF, INT) + DEF_FUNCTION_TYPE (V4SF, V4SF, PCV2SF) +@@ -284,7 +284,7 @@ + DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI) + DEF_FUNCTION_TYPE (V8QI, V4HI, V4HI) + DEF_FUNCTION_TYPE (V8QI, V8QI, V8QI) +-DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SF) ++DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SI) + DEF_FUNCTION_TYPE (V8SF, V8SF, INT) + DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF) + DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI) +@@ -343,10 +343,10 @@ + DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, INT) + DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI) + DEF_FUNCTION_TYPE (VOID, PCVOID, UNSIGNED, UNSIGNED) +-DEF_FUNCTION_TYPE (VOID, PV2DF, V2DF, V2DF) +-DEF_FUNCTION_TYPE (VOID, PV4DF, V4DF, V4DF) +-DEF_FUNCTION_TYPE (VOID, PV4SF, V4SF, V4SF) +-DEF_FUNCTION_TYPE (VOID, PV8SF, V8SF, V8SF) ++DEF_FUNCTION_TYPE (VOID, PV2DF, V2DI, V2DF) ++DEF_FUNCTION_TYPE (VOID, PV4DF, V4DI, V4DF) ++DEF_FUNCTION_TYPE (VOID, PV4SF, V4SI, V4SF) ++DEF_FUNCTION_TYPE (VOID, PV8SF, V8SI, V8SF) + DEF_FUNCTION_TYPE (VOID, UINT, UINT, UINT) + DEF_FUNCTION_TYPE (VOID, UINT64, UINT, UINT) + DEF_FUNCTION_TYPE (VOID, V16QI, V16QI, PCHAR) +--- a/src/gcc/config/i386/i386.c ++++ b/src/gcc/config/i386/i386.c +@@ -6737,12 +6737,8 @@ + setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum) + { + rtx save_area, mem; +- rtx label; +- rtx label_ref; +- rtx tmp_reg; +- rtx nsse_reg; + alias_set_type set; +- int i; ++ int i, max; + + /* GPR size of varargs save area. */ + if (cfun->va_list_gpr_size) +@@ -6752,7 +6748,7 @@ + + /* FPR size of varargs save area. We don't need it if we don't pass + anything in SSE registers. */ +- if (cum->sse_nregs && cfun->va_list_fpr_size) ++ if (TARGET_SSE && cfun->va_list_fpr_size) + ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16; + else + ix86_varargs_fpr_size = 0; +@@ -6763,10 +6759,11 @@ + save_area = frame_pointer_rtx; + set = get_varargs_alias_set (); + +- for (i = cum->regno; +- i < X86_64_REGPARM_MAX +- && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD; +- i++) ++ max = cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD; ++ if (max > X86_64_REGPARM_MAX) ++ max = X86_64_REGPARM_MAX; ++ ++ for (i = cum->regno; i < max; i++) + { + mem = gen_rtx_MEM (Pmode, + plus_constant (save_area, i * UNITS_PER_WORD)); +@@ -6778,62 +6775,42 @@ + + if (ix86_varargs_fpr_size) + { +- /* Stack must be aligned to 16byte for FP register save area. */ +- if (crtl->stack_alignment_needed < 128) +- crtl->stack_alignment_needed = 128; ++ enum machine_mode smode; ++ rtx label, test; + + /* Now emit code to save SSE registers. The AX parameter contains number +- of SSE parameter registers used to call this function. We use +- sse_prologue_save insn template that produces computed jump across +- SSE saves. We need some preparation work to get this working. */ ++ of SSE parameter registers used to call this function, though all we ++ actually check here is the zero/non-zero status. */ + + label = gen_label_rtx (); +- label_ref = gen_rtx_LABEL_REF (Pmode, label); ++ test = gen_rtx_EQ (VOIDmode, gen_rtx_REG (QImode, AX_REG), const0_rtx); ++ emit_jump_insn (gen_cbranchqi4 (test, XEXP (test, 0), XEXP (test, 1), ++ label)); ++ ++ /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if ++ we used movdqa (i.e. TImode) instead? Perhaps even better would ++ be if we could determine the real mode of the data, via a hook ++ into pass_stdarg. Ignore all that for now. */ ++ smode = V4SFmode; ++ if (crtl->stack_alignment_needed < GET_MODE_ALIGNMENT (smode)) ++ crtl->stack_alignment_needed = GET_MODE_ALIGNMENT (smode); ++ ++ max = cum->sse_regno + cfun->va_list_fpr_size / 16; ++ if (max > X86_64_SSE_REGPARM_MAX) ++ max = X86_64_SSE_REGPARM_MAX; ++ ++ for (i = cum->sse_regno; i < max; ++i) ++ { ++ mem = plus_constant (save_area, i * 16 + ix86_varargs_gpr_size); ++ mem = gen_rtx_MEM (smode, mem); ++ MEM_NOTRAP_P (mem) = 1; ++ set_mem_alias_set (mem, set); ++ set_mem_align (mem, GET_MODE_ALIGNMENT (smode)); + +- /* Compute address to jump to : +- label - eax*4 + nnamed_sse_arguments*4 Or +- label - eax*5 + nnamed_sse_arguments*5 for AVX. */ +- tmp_reg = gen_reg_rtx (Pmode); +- nsse_reg = gen_reg_rtx (Pmode); +- emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG))); +- emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, +- gen_rtx_MULT (Pmode, nsse_reg, +- GEN_INT (4)))); +- +- /* vmovaps is one byte longer than movaps. */ +- if (TARGET_AVX) +- emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, +- gen_rtx_PLUS (Pmode, tmp_reg, +- nsse_reg))); +- +- if (cum->sse_regno) +- emit_move_insn +- (nsse_reg, +- gen_rtx_CONST (DImode, +- gen_rtx_PLUS (DImode, +- label_ref, +- GEN_INT (cum->sse_regno +- * (TARGET_AVX ? 5 : 4))))); +- else +- emit_move_insn (nsse_reg, label_ref); +- emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg)); +- +- /* Compute address of memory block we save into. We always use pointer +- pointing 127 bytes after first byte to store - this is needed to keep +- instruction size limited by 4 bytes (5 bytes for AVX) with one +- byte displacement. */ +- tmp_reg = gen_reg_rtx (Pmode); +- emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, +- plus_constant (save_area, +- ix86_varargs_gpr_size + 127))); +- mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127)); +- MEM_NOTRAP_P (mem) = 1; +- set_mem_alias_set (mem, set); +- set_mem_align (mem, BITS_PER_WORD); ++ emit_move_insn (mem, gen_rtx_REG (smode, SSE_REGNO (i))); ++ } + +- /* And finally do the dirty job! */ +- emit_insn (gen_sse_prologue_save (mem, nsse_reg, +- GEN_INT (cum->sse_regno), label)); ++ emit_label (label); + } + } + +@@ -9331,13 +9308,13 @@ + + pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx, + popc, -1, true); +- emit_jump_insn (gen_return_indirect_internal (ecx)); ++ emit_jump_insn (gen_simple_return_indirect_internal (ecx)); + } + else +- emit_jump_insn (gen_return_pop_internal (popc)); ++ emit_jump_insn (gen_simple_return_pop_internal (popc)); + } + else +- emit_jump_insn (gen_return_internal ()); ++ emit_jump_insn (gen_simple_return_internal ()); + + /* Restore the state back to the state from the prologue, + so that it's correct for the next epilogue. */ +@@ -10438,6 +10415,17 @@ + case TLS_MODEL_INITIAL_EXEC: + if (TARGET_64BIT) + { ++ if (TARGET_SUN_TLS) ++ { ++ /* The Sun linker took the AMD64 TLS spec literally ++ and can only handle %rax as destination of the ++ initial executable code sequence. */ ++ ++ dest = gen_reg_rtx (Pmode); ++ emit_insn (gen_tls_initial_exec_64_sun (dest, x)); ++ return dest; ++ } ++ + pic = NULL; + type = UNSPEC_GOTNTPOFF; + } +@@ -11027,7 +11015,11 @@ + return orig_x; + x = XVECEXP (XEXP (x, 0), 0, 0); + if (GET_MODE (orig_x) != Pmode) +- return simplify_gen_subreg (GET_MODE (orig_x), x, Pmode, 0); ++ { ++ x = simplify_gen_subreg (GET_MODE (orig_x), x, Pmode, 0); ++ if (x == NULL_RTX) ++ return orig_x; ++ } + return x; + } + +@@ -11096,7 +11088,11 @@ + return orig_x; + } + if (GET_MODE (orig_x) != Pmode && MEM_P (orig_x)) +- return simplify_gen_subreg (GET_MODE (orig_x), result, Pmode, 0); ++ { ++ result = simplify_gen_subreg (GET_MODE (orig_x), result, Pmode, 0); ++ if (result == NULL_RTX) ++ return orig_x; ++ } + return result; + } + +@@ -21638,14 +21634,14 @@ + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF }, + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF }, + +- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF }, +- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF }, +- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF }, +- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF }, +- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF }, +- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF }, +- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF }, +- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF }, ++ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI }, ++ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI }, ++ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI }, ++ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI }, ++ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF }, ++ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF }, ++ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF }, ++ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF }, + + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID }, + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID }, +@@ -23927,18 +23923,18 @@ + klass = load; + memory = 1; + break; +- case V8SF_FTYPE_PCV8SF_V8SF: +- case V4DF_FTYPE_PCV4DF_V4DF: +- case V4SF_FTYPE_PCV4SF_V4SF: +- case V2DF_FTYPE_PCV2DF_V2DF: ++ case V8SF_FTYPE_PCV8SF_V8SI: ++ case V4DF_FTYPE_PCV4DF_V4DI: ++ case V4SF_FTYPE_PCV4SF_V4SI: ++ case V2DF_FTYPE_PCV2DF_V2DI: + nargs = 2; + klass = load; + memory = 0; + break; +- case VOID_FTYPE_PV8SF_V8SF_V8SF: +- case VOID_FTYPE_PV4DF_V4DF_V4DF: +- case VOID_FTYPE_PV4SF_V4SF_V4SF: +- case VOID_FTYPE_PV2DF_V2DF_V2DF: ++ case VOID_FTYPE_PV8SF_V8SI_V8SF: ++ case VOID_FTYPE_PV4DF_V4DI_V4DF: ++ case VOID_FTYPE_PV4SF_V4SI_V4SF: ++ case VOID_FTYPE_PV2DF_V2DI_V2DF: + nargs = 2; + klass = store; + /* Reserve memory operand for target. */ +@@ -25118,7 +25114,8 @@ + { + /* QImode spills from non-QI registers require + intermediate register on 32bit targets. */ +- if (!in_p && mode == QImode && !TARGET_64BIT ++ if (!TARGET_64BIT ++ && !in_p && mode == QImode + && (rclass == GENERAL_REGS + || rclass == LEGACY_REGS + || rclass == INDEX_REGS)) +@@ -25138,6 +25135,45 @@ + return Q_REGS; + } + ++ /* This condition handles corner case where an expression involving ++ pointers gets vectorized. We're trying to use the address of a ++ stack slot as a vector initializer. ++ ++ (set (reg:V2DI 74 [ vect_cst_.2 ]) ++ (vec_duplicate:V2DI (reg/f:DI 20 frame))) ++ ++ Eventually frame gets turned into sp+offset like this: ++ ++ (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74]) ++ (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp) ++ (const_int 392 [0x188])))) ++ ++ That later gets turned into: ++ ++ (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74]) ++ (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp) ++ (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64])))) ++ ++ We'll have the following reload recorded: ++ ++ Reload 0: reload_in (DI) = ++ (plus:DI (reg/f:DI 7 sp) ++ (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64])) ++ reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74]) ++ SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine ++ reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188])) ++ reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74]) ++ reload_reg_rtx: (reg:V2DI 22 xmm1) ++ ++ Which isn't going to work since SSE instructions can't handle scalar ++ additions. Returning GENERAL_REGS forces the addition into integer ++ register and reload can handle subsequent reloads without problems. */ ++ ++ if (in_p && GET_CODE (x) == PLUS ++ && SSE_CLASS_P (rclass) ++ && SCALAR_INT_MODE_P (mode)) ++ return GENERAL_REGS; ++ + return NO_REGS; + } + +@@ -26619,7 +26655,7 @@ + rtx prev; + bool replace = false; + +- if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN ++ if (!JUMP_P (ret) || !ANY_RETURN_P (PATTERN (ret)) + || optimize_bb_for_size_p (bb)) + continue; + for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev)) +@@ -26649,7 +26685,10 @@ + } + if (replace) + { +- emit_jump_insn_before (gen_return_internal_long (), ret); ++ if (PATTERN (ret) == ret_rtx) ++ emit_jump_insn_before (gen_return_internal_long (), ret); ++ else ++ emit_jump_insn_before (gen_simple_return_internal_long (), ret); + delete_insn (ret); + } + } +--- a/src/gcc/config/i386/i386.h ++++ b/src/gcc/config/i386/i386.h +@@ -955,7 +955,7 @@ + registers listed in CALL_USED_REGISTERS, keeping the others + available for storage of persistent values. + +- The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, ++ The ADJUST_REG_ALLOC_ORDER actually overwrite the order, + so this is just empty initializer for array. */ + + #define REG_ALLOC_ORDER \ +@@ -964,11 +964,11 @@ + 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52 } + +-/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order ++/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order + to be rearranged based on a particular function. When using sse math, + we want to allocate SSE before x87 registers and vice versa. */ + +-#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () + + + #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) +--- a/src/gcc/config/i386/i386.md ++++ b/src/gcc/config/i386/i386.md +@@ -80,7 +80,6 @@ + ; Prologue support + (UNSPEC_STACK_ALLOC 11) + (UNSPEC_SET_GOT 12) +- (UNSPEC_SSE_PROLOGUE_SAVE 13) + (UNSPEC_REG_SAVE 14) + (UNSPEC_DEF_CFA 15) + (UNSPEC_SET_RIP 16) +@@ -92,6 +91,7 @@ + (UNSPEC_TLS_GD 21) + (UNSPEC_TLS_LD_BASE 22) + (UNSPEC_TLSDESC 23) ++ (UNSPEC_TLS_IE_SUN 24) + + ; Other random patterns + (UNSPEC_SCAS 30) +@@ -4934,6 +4934,7 @@ + (set (match_operand:SSEMODEI24 2 "register_operand" "") + (fix:SSEMODEI24 (match_dup 0)))] + "TARGET_SHORTEN_X87_SSE ++ && !(TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()) + && peep2_reg_dead_p (2, operands[0])" + [(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))] + "") +@@ -13798,24 +13799,29 @@ + "" + [(set_attr "length" "0")]) + ++(define_code_iterator returns [return simple_return]) ++(define_code_attr return_str [(return "") (simple_return "simple_")]) ++(define_code_attr return_cond [(return "ix86_can_use_return_insn_p ()") ++ (simple_return "")]) ++ + ;; Insn emitted into the body of a function to return from a function. + ;; This is only done if the function's epilogue is known to be simple. + ;; See comments for ix86_can_use_return_insn_p in i386.c. + +-(define_expand "return" +- [(return)] +- "ix86_can_use_return_insn_p ()" ++(define_expand "return" ++ [(returns)] ++ "" + { + if (crtl->args.pops_args) + { + rtx popc = GEN_INT (crtl->args.pops_args); +- emit_jump_insn (gen_return_pop_internal (popc)); ++ emit_jump_insn (gen_return_pop_internal (popc)); + DONE; + } + }) + +-(define_insn "return_internal" +- [(return)] ++(define_insn "return_internal" ++ [(returns)] + "reload_completed" + "ret" + [(set_attr "length" "1") +@@ -13826,8 +13832,8 @@ + ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET + ;; instruction Athlon and K8 have. + +-(define_insn "return_internal_long" +- [(return) ++(define_insn "return_internal_long" ++ [(returns) + (unspec [(const_int 0)] UNSPEC_REP)] + "reload_completed" + "rep\;ret" +@@ -13837,8 +13843,8 @@ + (set_attr "prefix_rep" "1") + (set_attr "modrm" "0")]) + +-(define_insn "return_pop_internal" +- [(return) ++(define_insn "return_pop_internal" ++ [(returns) + (use (match_operand:SI 0 "const_int_operand" ""))] + "reload_completed" + "ret\t%0" +@@ -13847,8 +13853,8 @@ + (set_attr "length_immediate" "2") + (set_attr "modrm" "0")]) + +-(define_insn "return_indirect_internal" +- [(return) ++(define_insn "return_indirect_internal" ++ [(returns) + (use (match_operand:SI 0 "register_operand" "r"))] + "reload_completed" + "jmp\t%A0" +@@ -14702,6 +14708,18 @@ + (set_attr "memory" "load") + (set_attr "imm_disp" "false")]) + ++;; The Sun linker took the AMD64 TLS spec literally and can only handle ++;; %rax as destination of the initial executable code sequence. ++(define_insn "tls_initial_exec_64_sun" ++ [(set (match_operand:DI 0 "register_operand" "=a") ++ (unspec:DI ++ [(match_operand:DI 1 "tls_symbolic_operand" "")] ++ UNSPEC_TLS_IE_SUN)) ++ (clobber (reg:CC FLAGS_REG))] ++ "TARGET_64BIT && TARGET_SUN_TLS" ++ "mov{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}\n\tadd{q}\t{%a1@gottpoff(%%rip), %0|%0, %a1@gottpoff[rip]}" ++ [(set_attr "type" "multi")]) ++ + ;; GNU2 TLS patterns can be split. + + (define_expand "tls_dynamic_gnu2_32" +@@ -20019,15 +20037,14 @@ + ;; leal (%edx,%eax,4), %eax + + (define_peephole2 +- [(parallel [(set (match_operand 0 "register_operand" "") ++ [(match_scratch:P 5 "r") ++ (parallel [(set (match_operand 0 "register_operand" "") + (ashift (match_operand 1 "register_operand" "") + (match_operand 2 "const_int_operand" ""))) + (clobber (reg:CC FLAGS_REG))]) +- (set (match_operand 3 "register_operand") +- (match_operand 4 "x86_64_general_operand" "")) +- (parallel [(set (match_operand 5 "register_operand" "") +- (plus (match_operand 6 "register_operand" "") +- (match_operand 7 "register_operand" ""))) ++ (parallel [(set (match_operand 3 "register_operand" "") ++ (plus (match_dup 0) ++ (match_operand 4 "x86_64_general_operand" ""))) + (clobber (reg:CC FLAGS_REG))])] + "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3 + /* Validate MODE for lea. */ +@@ -20036,31 +20053,27 @@ + || GET_MODE (operands[0]) == HImode)) + || GET_MODE (operands[0]) == SImode + || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)) ++ && (rtx_equal_p (operands[0], operands[3]) ++ || peep2_reg_dead_p (2, operands[0])) + /* We reorder load and the shift. */ +- && !rtx_equal_p (operands[1], operands[3]) +- && !reg_overlap_mentioned_p (operands[0], operands[4]) +- /* Last PLUS must consist of operand 0 and 3. */ +- && !rtx_equal_p (operands[0], operands[3]) +- && (rtx_equal_p (operands[3], operands[6]) +- || rtx_equal_p (operands[3], operands[7])) +- && (rtx_equal_p (operands[0], operands[6]) +- || rtx_equal_p (operands[0], operands[7])) +- /* The intermediate operand 0 must die or be same as output. */ +- && (rtx_equal_p (operands[0], operands[5]) +- || peep2_reg_dead_p (3, operands[0]))" +- [(set (match_dup 3) (match_dup 4)) ++ && !reg_overlap_mentioned_p (operands[0], operands[4])" ++ [(set (match_dup 5) (match_dup 4)) + (set (match_dup 0) (match_dup 1))] + { +- enum machine_mode mode = GET_MODE (operands[5]) == DImode ? DImode : SImode; ++ enum machine_mode mode = GET_MODE (operands[1]) == DImode ? DImode : SImode; + int scale = 1 << INTVAL (operands[2]); + rtx index = gen_lowpart (Pmode, operands[1]); +- rtx base = gen_lowpart (Pmode, operands[3]); +- rtx dest = gen_lowpart (mode, operands[5]); ++ rtx base = gen_lowpart (Pmode, operands[5]); ++ rtx dest = gen_lowpart (mode, operands[3]); + + operands[1] = gen_rtx_PLUS (Pmode, base, + gen_rtx_MULT (Pmode, index, GEN_INT (scale))); ++ operands[5] = base; + if (mode != Pmode) +- operands[1] = gen_rtx_SUBREG (mode, operands[1], 0); ++ { ++ operands[1] = gen_rtx_SUBREG (mode, operands[1], 0); ++ operands[5] = gen_rtx_SUBREG (mode, operands[5], 0); ++ } + operands[0] = dest; + }) + +@@ -20252,74 +20265,6 @@ + { return ASM_SHORT "0x0b0f"; } + [(set_attr "length" "2")]) + +-(define_expand "sse_prologue_save" +- [(parallel [(set (match_operand:BLK 0 "" "") +- (unspec:BLK [(reg:DI XMM0_REG) +- (reg:DI XMM1_REG) +- (reg:DI XMM2_REG) +- (reg:DI XMM3_REG) +- (reg:DI XMM4_REG) +- (reg:DI XMM5_REG) +- (reg:DI XMM6_REG) +- (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE)) +- (use (match_operand:DI 1 "register_operand" "")) +- (use (match_operand:DI 2 "immediate_operand" "")) +- (use (label_ref:DI (match_operand 3 "" "")))])] +- "TARGET_64BIT" +- "") +- +-(define_insn "*sse_prologue_save_insn" +- [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R") +- (match_operand:DI 4 "const_int_operand" "n"))) +- (unspec:BLK [(reg:DI XMM0_REG) +- (reg:DI XMM1_REG) +- (reg:DI XMM2_REG) +- (reg:DI XMM3_REG) +- (reg:DI XMM4_REG) +- (reg:DI XMM5_REG) +- (reg:DI XMM6_REG) +- (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE)) +- (use (match_operand:DI 1 "register_operand" "r")) +- (use (match_operand:DI 2 "const_int_operand" "i")) +- (use (label_ref:DI (match_operand 3 "" "X")))] +- "TARGET_64BIT +- && INTVAL (operands[4]) + X86_64_SSE_REGPARM_MAX * 16 - 16 < 128 +- && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128" +-{ +- int i; +- operands[0] = gen_rtx_MEM (Pmode, +- gen_rtx_PLUS (Pmode, operands[0], operands[4])); +- /* VEX instruction with a REX prefix will #UD. */ +- if (TARGET_AVX && GET_CODE (XEXP (operands[0], 0)) != PLUS) +- gcc_unreachable (); +- +- output_asm_insn ("jmp\t%A1", operands); +- for (i = X86_64_SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--) +- { +- operands[4] = adjust_address (operands[0], DImode, i*16); +- operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i)); +- PUT_MODE (operands[4], TImode); +- if (GET_CODE (XEXP (operands[0], 0)) != PLUS) +- output_asm_insn ("rex", operands); +- output_asm_insn ("%vmovaps\t{%5, %4|%4, %5}", operands); +- } +- (*targetm.asm_out.internal_label) (asm_out_file, "L", +- CODE_LABEL_NUMBER (operands[3])); +- return ""; +-} +- [(set_attr "type" "other") +- (set_attr "length_immediate" "0") +- (set_attr "length_address" "0") +- (set (attr "length") +- (if_then_else +- (eq (symbol_ref "TARGET_AVX") (const_int 0)) +- (const_string "34") +- (const_string "42"))) +- (set_attr "memory" "store") +- (set_attr "modrm" "0") +- (set_attr "prefix" "maybe_vex") +- (set_attr "mode" "DI")]) +- + (define_expand "prefetch" + [(prefetch (match_operand 0 "address_operand" "") + (match_operand:SI 1 "const_int_operand" "") +--- a/src/gcc/config/i386/sse.md ++++ b/src/gcc/config/i386/sse.md +@@ -5011,7 +5011,7 @@ + movsd\t{%2, %0|%0, %2} + movlpd\t{%2, %0|%0, %2} + movsd\t{%2, %0|%0, %2} +- shufpd\t{$2, %2, %0|%0, %2, 2} ++ shufpd\t{$2, %1, %0|%0, %1, 2} + movhpd\t{%H1, %0|%0, %H1} + # + # +@@ -5090,7 +5090,7 @@ + movsd\t{%2, %0|%0, %2} + movlpd\t{%2, %0|%0, %2} + movlpd\t{%2, %0|%0, %2} +- shufpd\t{$2, %2, %0|%0, %2, 2} ++ shufpd\t{$2, %1, %0|%0, %1, 2} + movhps\t{%H1, %0|%0, %H1} + movhps\t{%1, %H0|%H0, %1}" + [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov") +@@ -12097,7 +12097,7 @@ + [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x") + (unspec:AVXMODEF2P + [(match_operand:AVXMODEF2P 1 "memory_operand" "m") +- (match_operand:AVXMODEF2P 2 "register_operand" "x") ++ (match_operand: 2 "register_operand" "x") + (match_dup 0)] + UNSPEC_MASKLOAD))] + "TARGET_AVX" +@@ -12110,7 +12110,7 @@ + (define_insn "avx_maskstorep" + [(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m") + (unspec:AVXMODEF2P +- [(match_operand:AVXMODEF2P 1 "register_operand" "x") ++ [(match_operand: 1 "register_operand" "x") + (match_operand:AVXMODEF2P 2 "register_operand" "x") + (match_dup 0)] + UNSPEC_MASKSTORE))] +--- a/src/gcc/config/m32c/m32c.c ++++ b/src/gcc/config/m32c/m32c.c +@@ -428,6 +428,10 @@ + + if (TARGET_A24) + flag_ivopts = 0; ++ ++ /* This target defaults to strict volatile bitfields. */ ++ if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) ++ flag_strict_volatile_bitfields = 1; + } + + /* Defining data structures for per-function information */ +--- a/src/gcc/config/m68hc11/m68hc11.md ++++ b/src/gcc/config/m68hc11/m68hc11.md +@@ -6576,7 +6576,7 @@ + if (ret_size && ret_size <= 2) + { + emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, +- gen_rtvec (2, gen_rtx_RETURN (VOIDmode), ++ gen_rtvec (2, ret_rtx, + gen_rtx_USE (VOIDmode, + gen_rtx_REG (HImode, 1))))); + DONE; +@@ -6584,7 +6584,7 @@ + if (ret_size) + { + emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, +- gen_rtvec (2, gen_rtx_RETURN (VOIDmode), ++ gen_rtvec (2, ret_rtx, + gen_rtx_USE (VOIDmode, + gen_rtx_REG (SImode, 0))))); + DONE; +--- a/src/gcc/config/m68k/m68k.c ++++ b/src/gcc/config/m68k/m68k.c +@@ -1366,7 +1366,7 @@ + EH_RETURN_STACKADJ_RTX)); + + if (!sibcall_p) +- emit_jump_insn (gen_rtx_RETURN (VOIDmode)); ++ emit_jump_insn (ret_rtx); + } + + /* Return true if X is a valid comparison operator for the dbcc +--- a/src/gcc/config/mips/mips.c ++++ b/src/gcc/config/mips/mips.c +@@ -10497,7 +10497,8 @@ + regno = GP_REG_FIRST + 7; + else + regno = RETURN_ADDR_REGNUM; +- emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno))); ++ emit_jump_insn (gen_simple_return_internal (gen_rtx_REG (Pmode, ++ regno))); + } + } + +--- a/src/gcc/config/mips/mips.h ++++ b/src/gcc/config/mips/mips.h +@@ -2059,12 +2059,12 @@ + 182,183,184,185,186,187 \ + } + +-/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order ++/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order + to be rearranged based on a particular function. On the mips16, we + want to allocate $24 (T_REG) before other registers for + instructions for which it is possible. */ + +-#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc () + + /* True if VALUE is an unsigned 6-bit number. */ + +--- a/src/gcc/config/mips/mips.md ++++ b/src/gcc/config/mips/mips.md +@@ -5815,6 +5815,18 @@ + [(set_attr "type" "jump") + (set_attr "mode" "none")]) + ++(define_expand "simple_return" ++ [(simple_return)] ++ "!mips_can_use_return_insn ()" ++ { mips_expand_before_return (); }) ++ ++(define_insn "*simple_return" ++ [(simple_return)] ++ "!mips_can_use_return_insn ()" ++ "%*j\t$31%/" ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none")]) ++ + ;; Normal return. + + (define_insn "return_internal" +@@ -5822,6 +5834,14 @@ + (use (match_operand 0 "pmode_register_operand" ""))] + "" + "%*j\t%0%/" ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none")]) ++ ++(define_insn "simple_return_internal" ++ [(simple_return) ++ (use (match_operand 0 "pmode_register_operand" ""))] ++ "" ++ "%*j\t%0%/" + [(set_attr "type" "jump") + (set_attr "mode" "none")]) + +--- a/src/gcc/config/pa/pa-hpux11.h ++++ b/src/gcc/config/pa/pa-hpux11.h +@@ -1,5 +1,5 @@ + /* Definitions of target machine for GNU compiler, for HP PA-RISC +- Copyright (C) 1998, 1999, 2000, 2002, 2003, 2004, 2005, 2007, 2008 ++ Copyright (C) 1998, 1999, 2000, 2002, 2003, 2004, 2005, 2007, 2008, 2011 + Free Software Foundation, Inc. + + This file is part of GCC. +@@ -114,18 +114,24 @@ + -z %{mlinker-opt:-O} %{!shared:-u main -u __gcc_plt_call}\ + %{static:-a archive} %{shared:-b}" + +-/* HP-UX 11 has posix threads. HP libc contains pthread stubs so that +- non-threaded applications can be linked with a thread-safe libc +- without a subsequent loss of performance. For more details, see +- . */ ++/* HP-UX 11 has posix threads. HP's shared libc contains pthread stubs ++ so that non-threaded applications can be linked with a thread-safe ++ libc without a subsequent loss of performance. For more details, ++ see . */ + #undef LIB_SPEC + #define LIB_SPEC \ + "%{!shared:\ +- %{static|mt|pthread:%{fopenmp:%{static:-a archive_shared} -lrt\ +- %{static:-a archive}} -lpthread} -lc\ +- %{static:%{!nolibdld:-a archive_shared -ldld -a archive -lc}}}\ ++ %{fopenmp:%{static:-a archive_shared} -lrt %{static:-a archive}}\ ++ %{mt|pthread:-lpthread} -lc\ ++ %{static:%{!nolibdld:-a archive_shared -ldld -a archive -lc}\ ++ %{!mt:%{!pthread:-a shared -lc -a archive}}}}\ + %{shared:%{mt|pthread:-lpthread}}" + ++/* The libgcc_stub.a library needs to come last. */ ++#undef LINK_GCC_C_SEQUENCE_SPEC ++#define LINK_GCC_C_SEQUENCE_SPEC \ ++ "%G %L %G %{!nostdlib:%{!nodefaultlibs:%{!shared:-lgcc_stub}}}" ++ + #undef STARTFILE_SPEC + #define STARTFILE_SPEC \ + "%{!shared:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}} \ +--- a/src/gcc/config/pa/pa.c ++++ b/src/gcc/config/pa/pa.c +@@ -6097,35 +6097,92 @@ + } + + /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and +- it branches to the next real instruction. Otherwise, return FALSE. */ ++ it branches into the delay slot. Otherwise, return FALSE. */ + + static bool + branch_to_delay_slot_p (rtx insn) + { ++ rtx jump_insn; ++ + if (dbr_sequence_length ()) + return FALSE; + +- return next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn); ++ jump_insn = next_active_insn (JUMP_LABEL (insn)); ++ while (insn) ++ { ++ insn = next_active_insn (insn); ++ if (jump_insn == insn) ++ return TRUE; ++ ++ /* We can't rely on the length of asms. So, we return FALSE when ++ the branch is followed by an asm. */ ++ if (!insn ++ || GET_CODE (PATTERN (insn)) == ASM_INPUT ++ || extract_asm_operands (PATTERN (insn)) != NULL_RTX ++ || get_attr_length (insn) > 0) ++ break; ++ } ++ ++ return FALSE; + } + +-/* Return TRUE if INSN, a jump insn, needs a nop in its delay slot. ++/* Return TRUE if INSN, a forward jump insn, needs a nop in its delay slot. + + This occurs when INSN has an unfilled delay slot and is followed +- by an ASM_INPUT. Disaster can occur if the ASM_INPUT is empty and +- the jump branches into the delay slot. So, we add a nop in the delay +- slot just to be safe. This messes up our instruction count, but we +- don't know how big the ASM_INPUT insn is anyway. */ ++ by an asm. Disaster can occur if the asm is empty and the jump ++ branches into the delay slot. So, we add a nop in the delay slot ++ when this occurs. */ + + static bool + branch_needs_nop_p (rtx insn) + { +- rtx next_insn; ++ rtx jump_insn; + + if (dbr_sequence_length ()) + return FALSE; + +- next_insn = next_real_insn (insn); +- return GET_CODE (PATTERN (next_insn)) == ASM_INPUT; ++ jump_insn = next_active_insn (JUMP_LABEL (insn)); ++ while (insn) ++ { ++ insn = next_active_insn (insn); ++ if (!insn || jump_insn == insn) ++ return TRUE; ++ ++ if (!(GET_CODE (PATTERN (insn)) == ASM_INPUT ++ || extract_asm_operands (PATTERN (insn)) != NULL_RTX) ++ && get_attr_length (insn) > 0) ++ break; ++ } ++ ++ return FALSE; ++} ++ ++/* Return TRUE if INSN, a forward jump insn, can use nullification ++ to skip the following instruction. This avoids an extra cycle due ++ to a mis-predicted branch when we fall through. */ ++ ++static bool ++use_skip_p (rtx insn) ++{ ++ rtx jump_insn = next_active_insn (JUMP_LABEL (insn)); ++ ++ while (insn) ++ { ++ insn = next_active_insn (insn); ++ ++ /* We can't rely on the length of asms, so we can't skip asms. */ ++ if (!insn ++ || GET_CODE (PATTERN (insn)) == ASM_INPUT ++ || extract_asm_operands (PATTERN (insn)) != NULL_RTX) ++ break; ++ if (get_attr_length (insn) == 4 ++ && jump_insn == next_active_insn (insn)) ++ return TRUE; ++ if (get_attr_length (insn) > 0) ++ break; ++ } ++ ++ return FALSE; + } + + /* This routine handles all the normal conditional branch sequences we +@@ -6139,7 +6196,7 @@ + output_cbranch (rtx *operands, int negated, rtx insn) + { + static char buf[100]; +- int useskip = 0; ++ bool useskip; + int nullify = INSN_ANNULLED_BRANCH_P (insn); + int length = get_attr_length (insn); + int xdelay; +@@ -6177,12 +6234,7 @@ + /* A forward branch over a single nullified insn can be done with a + comclr instruction. This avoids a single cycle penalty due to + mis-predicted branch if we fall through (branch not taken). */ +- if (length == 4 +- && next_real_insn (insn) != 0 +- && get_attr_length (next_real_insn (insn)) == 4 +- && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) +- && nullify) +- useskip = 1; ++ useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE; + + switch (length) + { +@@ -6470,7 +6522,7 @@ + output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) + { + static char buf[100]; +- int useskip = 0; ++ bool useskip; + int nullify = INSN_ANNULLED_BRANCH_P (insn); + int length = get_attr_length (insn); + int xdelay; +@@ -6496,13 +6548,7 @@ + /* A forward branch over a single nullified insn can be done with a + extrs instruction. This avoids a single cycle penalty due to + mis-predicted branch if we fall through (branch not taken). */ +- +- if (length == 4 +- && next_real_insn (insn) != 0 +- && get_attr_length (next_real_insn (insn)) == 4 +- && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) +- && nullify) +- useskip = 1; ++ useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE; + + switch (length) + { +@@ -6661,7 +6707,7 @@ + output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) + { + static char buf[100]; +- int useskip = 0; ++ bool useskip; + int nullify = INSN_ANNULLED_BRANCH_P (insn); + int length = get_attr_length (insn); + int xdelay; +@@ -6687,13 +6733,7 @@ + /* A forward branch over a single nullified insn can be done with a + extrs instruction. This avoids a single cycle penalty due to + mis-predicted branch if we fall through (branch not taken). */ +- +- if (length == 4 +- && next_real_insn (insn) != 0 +- && get_attr_length (next_real_insn (insn)) == 4 +- && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) +- && nullify) +- useskip = 1; ++ useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE; + + switch (length) + { +--- a/src/gcc/config/pa/pa.md ++++ b/src/gcc/config/pa/pa.md +@@ -811,7 +811,7 @@ + (match_operand:DI 3 "arith11_operand" "rI")) + (match_operand:DI 1 "register_operand" "r")))] + "TARGET_64BIT" +- "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0" ++ "sub%I3,* %3,%2,%%r0\;add,dc %%r0,%1,%0" + [(set_attr "type" "binary") + (set_attr "length" "8")]) + +@@ -833,7 +833,7 @@ + (match_operand:DI 3 "register_operand" "r")) + (match_operand:DI 1 "register_operand" "r")))] + "TARGET_64BIT" +- "sub %2,%3,%%r0\;add,dc %%r0,%1,%0" ++ "sub,* %2,%3,%%r0\;add,dc %%r0,%1,%0" + [(set_attr "type" "binary") + (set_attr "length" "8")]) + +@@ -856,7 +856,7 @@ + (match_operand:DI 3 "int11_operand" "I")) + (match_operand:DI 1 "register_operand" "r")))] + "TARGET_64BIT" +- "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0" ++ "addi,* %k3,%2,%%r0\;add,dc %%r0,%1,%0" + [(set_attr "type" "binary") + (set_attr "length" "8")]) + +@@ -902,7 +902,7 @@ + (gtu:DI (match_operand:DI 2 "register_operand" "r") + (match_operand:DI 3 "arith11_operand" "rI"))))] + "TARGET_64BIT" +- "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0" ++ "sub%I3,* %3,%2,%%r0\;sub,db %1,%%r0,%0" + [(set_attr "type" "binary") + (set_attr "length" "8")]) + +@@ -924,7 +924,7 @@ + (match_operand:DI 3 "arith11_operand" "rI"))) + (match_operand:DI 4 "register_operand" "r")))] + "TARGET_64BIT" +- "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0" ++ "sub%I3,* %3,%2,%%r0\;sub,db %1,%4,%0" + [(set_attr "type" "binary") + (set_attr "length" "8")]) + +@@ -946,7 +946,7 @@ + (ltu:DI (match_operand:DI 2 "register_operand" "r") + (match_operand:DI 3 "register_operand" "r"))))] + "TARGET_64BIT" +- "sub %2,%3,%%r0\;sub,db %1,%%r0,%0" ++ "sub,* %2,%3,%%r0\;sub,db %1,%%r0,%0" + [(set_attr "type" "binary") + (set_attr "length" "8")]) + +@@ -968,7 +968,7 @@ + (match_operand:DI 3 "register_operand" "r"))) + (match_operand:DI 4 "register_operand" "r")))] + "TARGET_64BIT" +- "sub %2,%3,%%r0\;sub,db %1,%4,%0" ++ "sub,* %2,%3,%%r0\;sub,db %1,%4,%0" + [(set_attr "type" "binary") + (set_attr "length" "8")]) + +@@ -991,7 +991,7 @@ + (leu:DI (match_operand:DI 2 "register_operand" "r") + (match_operand:DI 3 "int11_operand" "I"))))] + "TARGET_64BIT" +- "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0" ++ "addi,* %k3,%2,%%r0\;sub,db %1,%%r0,%0" + [(set_attr "type" "binary") + (set_attr "length" "8")]) + +@@ -1013,7 +1013,7 @@ + (match_operand:DI 3 "int11_operand" "I"))) + (match_operand:DI 4 "register_operand" "r")))] + "TARGET_64BIT" +- "addi %k3,%2,%%r0\;sub,db %1,%4,%0" ++ "addi,* %k3,%2,%%r0\;sub,db %1,%4,%0" + [(set_attr "type" "binary") + (set_attr "length" "8")]) + +--- a/src/gcc/config/pa/pa64-hpux.h ++++ b/src/gcc/config/pa/pa64-hpux.h +@@ -1,6 +1,6 @@ + /* Definitions of target machine for GNU compiler, for HPs running + HPUX using the 64bit runtime model. +- Copyright (C) 1999, 2000, 2001, 2002, 2004, 2005, 2007, 2008 ++ Copyright (C) 1999, 2000, 2001, 2002, 2004, 2005, 2007, 2008, 2011 + Free Software Foundation, Inc. + + This file is part of GCC. +@@ -59,36 +59,42 @@ + #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_GNU_LD) + #define LIB_SPEC \ + "%{!shared:\ +- %{!p:%{!pg:%{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\ +- %{static:-a archive}} -lpthread} -lc\ +- %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\ ++ %{!p:%{!pg:%{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\ ++ %{mt|pthread:-lpthread} -lc\ ++ %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\ ++ %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\ + %{p:%{!pg:%{static:%{!mhp-ld:-a shared}%{mhp-ld:-a archive_shared}}\ + -lprof %{static:-a archive}\ +- %{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\ +- %{static:-a archive}} -lpthread} -lc\ +- %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\ ++ %{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\ ++ %{mt|pthread:-lpthread} -lc\ ++ %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\ ++ %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\ + %{pg:%{static:%{!mhp-ld:-a shared}%{mhp-ld:-a archive_shared}}\ + -lgprof %{static:-a archive}\ +- %{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\ +- %{static:-a archive}} -lpthread} -lc\ +- %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\ ++ %{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\ ++ %{mt|pthread:-lpthread} -lc\ ++ %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\ ++ %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\ + %{shared:%{mt|pthread:-lpthread}}" + #else + #define LIB_SPEC \ + "%{!shared:\ +- %{!p:%{!pg:%{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\ +- %{static:-a archive}} -lpthread} -lc\ +- %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\ ++ %{!p:%{!pg:%{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\ ++ %{mt|pthread:-lpthread} -lc\ ++ %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\ ++ %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\ + %{p:%{!pg:%{static:%{mgnu-ld:-a shared}%{!mgnu-ld:-a archive_shared}}\ + -lprof %{static:-a archive}\ +- %{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\ +- %{static:-a archive}} -lpthread} -lc\ +- %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\ ++ %{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\ ++ %{mt|pthread:-lpthread} -lc\ ++ %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\ ++ %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\ + %{pg:%{static:%{mgnu-ld:-a shared}%{!mgnu-ld:-a archive_shared}}\ + -lgprof %{static:-a archive}\ +- %{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\ +- %{static:-a archive}} -lpthread} -lc\ +- %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\ ++ %{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\ ++ %{mt|pthread:-lpthread} -lc\ ++ %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\ ++ %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\ + %{shared:%{mt|pthread:-lpthread}}" + #endif + +--- a/src/gcc/config/pa/stublib.c ++++ b/src/gcc/config/pa/stublib.c +@@ -1,5 +1,5 @@ + /* Stub functions. +- Copyright (C) 2006, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2006, 2009, 2011 Free Software Foundation, Inc. + + This file is part of GCC. + +@@ -56,3 +56,42 @@ + { + } + #endif ++ ++#ifdef L_pthread_default_stacksize_np ++int pthread_default_stacksize_np (unsigned long __attribute__((unused)), ++ unsigned long *); ++int ++pthread_default_stacksize_np (unsigned long new, unsigned long *old) ++{ ++ if (old) ++ *old = 0; ++ return 0; ++} ++#endif ++ ++#ifdef L_pthread_mutex_lock ++int pthread_mutex_lock (void); ++int ++pthread_mutex_lock (void) ++{ ++ return 0; ++} ++#endif ++ ++#ifdef L_pthread_mutex_unlock ++int pthread_mutex_unlock (void); ++int ++pthread_mutex_unlock (void) ++{ ++ return 0; ++} ++#endif ++ ++#ifdef L_pthread_once ++int pthread_once (void); ++int ++pthread_once (void) ++{ ++ return 0; ++} ++#endif +--- a/src/gcc/config/pa/t-pa-hpux11 ++++ b/src/gcc/config/pa/t-pa-hpux11 +@@ -1,2 +1,31 @@ + TARGET_LIBGCC2_CFLAGS = -fPIC -frandom-seed=fixed-seed + LIB2FUNCS_EXTRA=lib2funcs.asm quadlib.c ++LIBGCCSTUB_OBJS = pthread_default_stacksize_np-stub.o \ ++ pthread_mutex_lock-stub.o \ ++ pthread_mutex_unlock-stub.o \ ++ pthread_once-stub.o ++ ++stublib.c: $(srcdir)/config/pa/stublib.c ++ rm -f stublib.c ++ cp $(srcdir)/config/pa/stublib.c . ++ ++pthread_default_stacksize_np-stub.o: stublib.c $(GCC_PASSES) ++ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_default_stacksize_np stublib.c \ ++ -o pthread_default_stacksize_np-stub.o ++ ++pthread_mutex_lock-stub.o: stublib.c $(GCC_PASSES) ++ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_mutex_lock stublib.c \ ++ -o pthread_mutex_lock-stub.o ++ ++pthread_mutex_unlock-stub.o: stublib.c $(GCC_PASSES) ++ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_mutex_unlock stublib.c \ ++ -o pthread_mutex_unlock-stub.o ++ ++pthread_once-stub.o: stublib.c $(GCC_PASSES) ++ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_once stublib.c \ ++ -o pthread_once-stub.o ++ ++$(T)libgcc_stub.a: $(LIBGCCSTUB_OBJS) ++ -rm -rf $(T)libgcc_stub.a ++ $(AR) rc $(T)libgcc_stub.a $(LIBGCCSTUB_OBJS) ++ $(RANLIB) $(T)libgcc_stub.a +--- a/src/gcc/config/pa/t-pa64 ++++ b/src/gcc/config/pa/t-pa64 +@@ -1,5 +1,5 @@ + # Copyright (C) 2000, 2001, 2002, 2004, 2006, +-# 2007 Free Software Foundation, Inc. ++# 2007, 2011 Free Software Foundation, Inc. + # + # This file is part of GCC. + # +@@ -19,7 +19,11 @@ + + TARGET_LIBGCC2_CFLAGS = -fPIC -Dpa64=1 -DELF=1 -mlong-calls + LIB2FUNCS_EXTRA = quadlib.c +-LIBGCCSTUB_OBJS = rfi-stub.o dfi-stub.o jvrc-stub.o cxaf-stub.o ++LIBGCCSTUB_OBJS = rfi-stub.o dfi-stub.o jvrc-stub.o cxaf-stub.o \ ++ pthread_default_stacksize_np-stub.o \ ++ pthread_mutex_lock-stub.o \ ++ pthread_mutex_unlock-stub.o \ ++ pthread_once-stub.o + + stublib.c: $(srcdir)/config/pa/stublib.c + rm -f stublib.c +@@ -41,6 +45,22 @@ + $(GCC_FOR_TARGET) -c -O2 -DL_Jv_RegisterClasses stublib.c \ + -o jvrc-stub.o + ++pthread_default_stacksize_np-stub.o: stublib.c $(GCC_PASSES) ++ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_default_stacksize_np stublib.c \ ++ -o pthread_default_stacksize_np-stub.o ++ ++pthread_mutex_lock-stub.o: stublib.c $(GCC_PASSES) ++ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_mutex_lock stublib.c \ ++ -o pthread_mutex_lock-stub.o ++ ++pthread_mutex_unlock-stub.o: stublib.c $(GCC_PASSES) ++ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_mutex_unlock stublib.c \ ++ -o pthread_mutex_unlock-stub.o ++ ++pthread_once-stub.o: stublib.c $(GCC_PASSES) ++ $(GCC_FOR_TARGET) -c -O2 -DL_pthread_once stublib.c \ ++ -o pthread_once-stub.o ++ + $(T)libgcc_stub.a: $(LIBGCCSTUB_OBJS) + -rm -rf $(T)libgcc_stub.a + $(AR) rc $(T)libgcc_stub.a $(LIBGCCSTUB_OBJS) +--- a/src/gcc/config/picochip/picochip.c ++++ b/src/gcc/config/picochip/picochip.c +@@ -1996,7 +1996,7 @@ + rtvec p; + p = rtvec_alloc (2); + +- RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); ++ RTVEC_ELT (p, 0) = ret_rtx; + RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, + gen_rtx_REG (Pmode, LINK_REGNUM)); + emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); +--- a/src/gcc/config/picochip/picochip.h ++++ b/src/gcc/config/picochip/picochip.h +@@ -261,7 +261,7 @@ + /* We can dynamically change the REG_ALLOC_ORDER using the following hook. + It would be desirable to change it for leaf functions so we can put + r12 at the end of this list.*/ +-#define ORDER_REGS_FOR_LOCAL_ALLOC picochip_order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER picochip_order_regs_for_local_alloc () + + /* How Values Fit in Registers */ + +--- a/src/gcc/config/rs6000/altivec.h ++++ b/src/gcc/config/rs6000/altivec.h +@@ -1,5 +1,6 @@ + /* PowerPC AltiVec include file. +- Copyright (C) 2002, 2003, 2004, 2005, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2002, 2003, 2004, 2005, 2008, 2009, 2010, 2011 ++ Free Software Foundation, Inc. + Contributed by Aldy Hernandez (aldyh@redhat.com). + Rewritten by Paolo Bonzini (bonzini@gnu.org). + +@@ -315,6 +316,8 @@ + #define vec_nearbyint __builtin_vec_nearbyint + #define vec_rint __builtin_vec_rint + #define vec_sqrt __builtin_vec_sqrt ++#define vec_vsx_ld __builtin_vec_vsx_ld ++#define vec_vsx_st __builtin_vec_vsx_st + #endif + + /* Predicates. +--- a/src/gcc/config/rs6000/altivec.md ++++ b/src/gcc/config/rs6000/altivec.md +@@ -1,5 +1,5 @@ + ;; AltiVec patterns. +-;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 ++;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 + ;; Free Software Foundation, Inc. + ;; Contributed by Aldy Hernandez (aldy@quesejoda.com) + +@@ -98,7 +98,7 @@ + (UNSPEC_STVE 203) + (UNSPEC_SET_VSCR 213) + (UNSPEC_GET_VRSAVE 214) +- ;; 215 deleted ++ (UNSPEC_LVX 215) + (UNSPEC_REDUC_PLUS 217) + (UNSPEC_VECSH 219) + (UNSPEC_EXTEVEN_V4SI 220) +@@ -171,6 +171,7 @@ + (define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI]) + + (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")]) ++(define_mode_attr VI_scalar [(V4SI "SI") (V8HI "HI") (V16QI "QI")]) + + ;; Vector move instructions. + (define_insn "*altivec_mov" +@@ -1751,17 +1752,19 @@ + "lvxl %0,%y1" + [(set_attr "type" "vecload")]) + +-(define_insn "altivec_lvx" +- [(set (match_operand:V4SI 0 "register_operand" "=v") +- (match_operand:V4SI 1 "memory_operand" "Z"))] ++(define_insn "altivec_lvx_" ++ [(parallel ++ [(set (match_operand:VM2 0 "register_operand" "=v") ++ (match_operand:VM2 1 "memory_operand" "Z")) ++ (unspec [(const_int 0)] UNSPEC_LVX)])] + "TARGET_ALTIVEC" + "lvx %0,%y1" + [(set_attr "type" "vecload")]) + +-(define_insn "altivec_stvx" ++(define_insn "altivec_stvx_" + [(parallel +- [(set (match_operand:V4SI 0 "memory_operand" "=Z") +- (match_operand:V4SI 1 "register_operand" "v")) ++ [(set (match_operand:VM2 0 "memory_operand" "=Z") ++ (match_operand:VM2 1 "register_operand" "v")) + (unspec [(const_int 0)] UNSPEC_STVX)])] + "TARGET_ALTIVEC" + "stvx %1,%y0" +@@ -1777,19 +1780,15 @@ + [(set_attr "type" "vecstore")]) + + (define_insn "altivec_stvex" +- [(parallel +- [(set (match_operand:VI 0 "memory_operand" "=Z") +- (match_operand:VI 1 "register_operand" "v")) +- (unspec [(const_int 0)] UNSPEC_STVE)])] ++ [(set (match_operand: 0 "memory_operand" "=Z") ++ (unspec: [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))] + "TARGET_ALTIVEC" + "stvex %1,%y0" + [(set_attr "type" "vecstore")]) + + (define_insn "*altivec_stvesfx" +- [(parallel +- [(set (match_operand:V4SF 0 "memory_operand" "=Z") +- (match_operand:V4SF 1 "register_operand" "v")) +- (unspec [(const_int 0)] UNSPEC_STVE)])] ++ [(set (match_operand:SF 0 "memory_operand" "=Z") ++ (unspec:SF [(match_operand:V4SF 1 "register_operand" "v")] UNSPEC_STVE))] + "TARGET_ALTIVEC" + "stvewx %1,%y0" + [(set_attr "type" "vecstore")]) +--- a/src/gcc/config/rs6000/rs6000-builtin.def ++++ b/src/gcc/config/rs6000/rs6000-builtin.def +@@ -1,5 +1,5 @@ + /* Builtin functions for rs6000/powerpc. +- Copyright (C) 2009, 2010 ++ Copyright (C) 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Michael Meissner (meissner@linux.vnet.ibm.com) + +@@ -37,6 +37,10 @@ + RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_16qi, RS6000_BTC_MEM) + RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_4sf, RS6000_BTC_MEM) + RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_4sf, RS6000_BTC_MEM) ++RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_2df, RS6000_BTC_MEM) ++RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_2df, RS6000_BTC_MEM) ++RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_2di, RS6000_BTC_MEM) ++RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_2di, RS6000_BTC_MEM) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUBM, RS6000_BTC_CONST) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUHM, RS6000_BTC_CONST) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUWM, RS6000_BTC_CONST) +@@ -774,12 +778,20 @@ + + /* VSX builtins. */ + RS6000_BUILTIN(VSX_BUILTIN_LXSDX, RS6000_BTC_MEM) +-RS6000_BUILTIN(VSX_BUILTIN_LXVD2X, RS6000_BTC_MEM) ++RS6000_BUILTIN(VSX_BUILTIN_LXVD2X_V2DF, RS6000_BTC_MEM) ++RS6000_BUILTIN(VSX_BUILTIN_LXVD2X_V2DI, RS6000_BTC_MEM) + RS6000_BUILTIN(VSX_BUILTIN_LXVDSX, RS6000_BTC_MEM) +-RS6000_BUILTIN(VSX_BUILTIN_LXVW4X, RS6000_BTC_MEM) ++RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V4SF, RS6000_BTC_MEM) ++RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V4SI, RS6000_BTC_MEM) ++RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V8HI, RS6000_BTC_MEM) ++RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V16QI, RS6000_BTC_MEM) + RS6000_BUILTIN(VSX_BUILTIN_STXSDX, RS6000_BTC_MEM) +-RS6000_BUILTIN(VSX_BUILTIN_STXVD2X, RS6000_BTC_MEM) +-RS6000_BUILTIN(VSX_BUILTIN_STXVW4X, RS6000_BTC_MEM) ++RS6000_BUILTIN(VSX_BUILTIN_STXVD2X_V2DF, RS6000_BTC_MEM) ++RS6000_BUILTIN(VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTC_MEM) ++RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V4SF, RS6000_BTC_MEM) ++RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V4SI, RS6000_BTC_MEM) ++RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V8HI, RS6000_BTC_MEM) ++RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V16QI, RS6000_BTC_MEM) + RS6000_BUILTIN(VSX_BUILTIN_XSABSDP, RS6000_BTC_CONST) + RS6000_BUILTIN(VSX_BUILTIN_XSADDDP, RS6000_BTC_FP_PURE) + RS6000_BUILTIN(VSX_BUILTIN_XSCMPODP, RS6000_BTC_FP_PURE) +@@ -975,8 +987,10 @@ + RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSLDWI, RS6000_BTC_MISC) + RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSPLTD, RS6000_BTC_MISC) + RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSPLTW, RS6000_BTC_MISC) ++RS6000_BUILTIN(VSX_BUILTIN_VEC_LD, RS6000_BTC_MISC) ++RS6000_BUILTIN(VSX_BUILTIN_VEC_ST, RS6000_BTC_MISC) + RS6000_BUILTIN_EQUATE(VSX_BUILTIN_OVERLOADED_LAST, +- VSX_BUILTIN_VEC_XXSPLTW) ++ VSX_BUILTIN_VEC_ST) + + /* Combined VSX/Altivec builtins. */ + RS6000_BUILTIN(VECTOR_BUILTIN_FLOAT_V4SI_V4SF, RS6000_BTC_FP_PURE) +--- a/src/gcc/config/rs6000/rs6000-c.c ++++ b/src/gcc/config/rs6000/rs6000-c.c +@@ -965,6 +965,15 @@ + { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, ++ RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, ++ RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, +@@ -1077,9 +1086,19 @@ + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, +- RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, ++ RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, ++ RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, + { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, +@@ -1098,6 +1117,17 @@ + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, + { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_long_long, 0 }, + { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, + { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, +@@ -1116,6 +1146,17 @@ + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, + { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, ++ { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_long_long, 0 }, + { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, + { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, +@@ -2609,6 +2650,16 @@ + { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, + RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE }, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, ++ RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, ++ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, ++ RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, ++ RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, ++ RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_bool_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, +@@ -2774,6 +2825,18 @@ + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, ++ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, ++ RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, ++ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, ++ RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, ++ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, ++ RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, ++ RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, ++ RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, + { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, +@@ -2967,6 +3030,135 @@ + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_NOT_OPAQUE }, + ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, ++ RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, ++ RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V2DI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF, ++ RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF, ++ RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, ++ RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, ++ RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, ++ RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, ++ RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V4SI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_long, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, ++ RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, ++ RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, ++ RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, ++ RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V8HI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, ++ RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, ++ RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, ++ RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V16QI, 0 }, ++ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, ++ ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, ++ RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, ++ RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, ++ RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V2DI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, ++ RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_bool_V2DI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF, ++ RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF, ++ RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, ++ RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, ++ RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, ++ RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V4SI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, ++ RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_UINTSI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, ++ RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_bool_V4SI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, ++ RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_UINTSI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, ++ RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_INTSI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, ++ RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, ++ RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, ++ RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V8HI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, ++ RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_UINTHI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, ++ RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_bool_V8HI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, ++ RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_UINTHI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, ++ RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_INTHI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, ++ RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, ++ RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, ++ RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_unsigned_V16QI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, ++ RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_UINTQI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, ++ RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_bool_V16QI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, ++ RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_UINTQI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, ++ RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_INTQI }, ++ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, ++ RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ++ ~RS6000_BTI_pixel_V8HI }, ++ + /* Predicates. */ + { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, +--- a/src/gcc/config/rs6000/rs6000-protos.h ++++ b/src/gcc/config/rs6000/rs6000-protos.h +@@ -1,5 +1,6 @@ + /* Definitions of target machine for GNU compiler, for IBM RS/6000. +- Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 ++ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, ++ 2010, 2011 + Free Software Foundation, Inc. + Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) + +@@ -130,6 +131,7 @@ + + extern rtx rs6000_machopic_legitimize_pic_address (rtx, enum machine_mode, + rtx); ++extern rtx rs6000_address_for_altivec (rtx); + #endif /* RTX_CODE */ + + #ifdef TREE_CODE +--- a/src/gcc/config/rs6000/rs6000.c ++++ b/src/gcc/config/rs6000/rs6000.c +@@ -2865,9 +2865,12 @@ + /* If not explicitly specified via option, decide whether to generate indexed + load/store instructions. */ + if (TARGET_AVOID_XFORM == -1) +- /* Avoid indexed addressing when targeting Power6 in order to avoid +- the DERAT mispredict penalty. */ +- TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB); ++ /* Avoid indexed addressing when targeting Power6 in order to avoid the ++ DERAT mispredict penalty. However the LVE and STVE altivec instructions ++ need indexed accesses and the type used is the scalar type of the element ++ being loaded or stored. */ ++ TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB ++ && !TARGET_ALTIVEC); + + rs6000_init_hard_regno_mode_ok (); + } +@@ -4472,7 +4475,7 @@ + { + enum machine_mode mode = GET_MODE (vec); + enum machine_mode inner_mode = GET_MODE_INNER (mode); +- rtx mem, x; ++ rtx mem; + + if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode)) + { +@@ -4485,17 +4488,11 @@ + /* Allocate mode-sized buffer. */ + mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); + ++ emit_move_insn (mem, vec); ++ + /* Add offset to field within buffer matching vector element. */ +- mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode)); ++ mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode)); + +- /* Store single field into mode-sized buffer. */ +- x = gen_rtx_UNSPEC (VOIDmode, +- gen_rtvec (1, const0_rtx), UNSPEC_STVE); +- emit_insn (gen_rtx_PARALLEL (VOIDmode, +- gen_rtvec (2, +- gen_rtx_SET (VOIDmode, +- mem, vec), +- x))); + emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0)); + } + +@@ -9897,6 +9894,7 @@ + rtx op2 = expand_normal (arg2); + rtx pat, addr; + enum machine_mode tmode = insn_data[icode].operand[0].mode; ++ enum machine_mode smode = insn_data[icode].operand[1].mode; + enum machine_mode mode1 = Pmode; + enum machine_mode mode2 = Pmode; + +@@ -9906,8 +9904,8 @@ + || arg2 == error_mark_node) + return const0_rtx; + +- if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) +- op0 = copy_to_mode_reg (tmode, op0); ++ if (! (*insn_data[icode].operand[1].predicate) (op0, smode)) ++ op0 = copy_to_mode_reg (smode, op0); + + op2 = copy_to_mode_reg (mode2, op2); + +@@ -10041,16 +10039,22 @@ + switch (fcode) + { + case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: +- icode = CODE_FOR_vector_load_v16qi; ++ icode = CODE_FOR_vector_altivec_load_v16qi; + break; + case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: +- icode = CODE_FOR_vector_load_v8hi; ++ icode = CODE_FOR_vector_altivec_load_v8hi; + break; + case ALTIVEC_BUILTIN_LD_INTERNAL_4si: +- icode = CODE_FOR_vector_load_v4si; ++ icode = CODE_FOR_vector_altivec_load_v4si; + break; + case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: +- icode = CODE_FOR_vector_load_v4sf; ++ icode = CODE_FOR_vector_altivec_load_v4sf; ++ break; ++ case ALTIVEC_BUILTIN_LD_INTERNAL_2df: ++ icode = CODE_FOR_vector_altivec_load_v2df; ++ break; ++ case ALTIVEC_BUILTIN_LD_INTERNAL_2di: ++ icode = CODE_FOR_vector_altivec_load_v2di; + break; + default: + *expandedp = false; +@@ -10094,16 +10098,22 @@ + switch (fcode) + { + case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: +- icode = CODE_FOR_vector_store_v16qi; ++ icode = CODE_FOR_vector_altivec_store_v16qi; + break; + case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: +- icode = CODE_FOR_vector_store_v8hi; ++ icode = CODE_FOR_vector_altivec_store_v8hi; + break; + case ALTIVEC_BUILTIN_ST_INTERNAL_4si: +- icode = CODE_FOR_vector_store_v4si; ++ icode = CODE_FOR_vector_altivec_store_v4si; + break; + case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: +- icode = CODE_FOR_vector_store_v4sf; ++ icode = CODE_FOR_vector_altivec_store_v4sf; ++ break; ++ case ALTIVEC_BUILTIN_ST_INTERNAL_2df: ++ icode = CODE_FOR_vector_altivec_store_v2df; ++ break; ++ case ALTIVEC_BUILTIN_ST_INTERNAL_2di: ++ icode = CODE_FOR_vector_altivec_store_v2di; + break; + default: + *expandedp = false; +@@ -10336,7 +10346,7 @@ + switch (fcode) + { + case ALTIVEC_BUILTIN_STVX: +- return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp); ++ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp); + case ALTIVEC_BUILTIN_STVEBX: + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp); + case ALTIVEC_BUILTIN_STVEHX: +@@ -10355,6 +10365,19 @@ + case ALTIVEC_BUILTIN_STVRXL: + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp); + ++ case VSX_BUILTIN_STXVD2X_V2DF: ++ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp); ++ case VSX_BUILTIN_STXVD2X_V2DI: ++ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp); ++ case VSX_BUILTIN_STXVW4X_V4SF: ++ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp); ++ case VSX_BUILTIN_STXVW4X_V4SI: ++ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp); ++ case VSX_BUILTIN_STXVW4X_V8HI: ++ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp); ++ case VSX_BUILTIN_STXVW4X_V16QI: ++ return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp); ++ + case ALTIVEC_BUILTIN_MFVSCR: + icode = CODE_FOR_altivec_mfvscr; + tmode = insn_data[icode].operand[0].mode; +@@ -10479,7 +10502,7 @@ + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, + exp, target, false); + case ALTIVEC_BUILTIN_LVX: +- return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx, ++ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si, + exp, target, false); + case ALTIVEC_BUILTIN_LVLX: + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx, +@@ -10493,6 +10516,25 @@ + case ALTIVEC_BUILTIN_LVRXL: + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl, + exp, target, true); ++ case VSX_BUILTIN_LXVD2X_V2DF: ++ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df, ++ exp, target, false); ++ case VSX_BUILTIN_LXVD2X_V2DI: ++ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di, ++ exp, target, false); ++ case VSX_BUILTIN_LXVW4X_V4SF: ++ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf, ++ exp, target, false); ++ case VSX_BUILTIN_LXVW4X_V4SI: ++ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si, ++ exp, target, false); ++ case VSX_BUILTIN_LXVW4X_V8HI: ++ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi, ++ exp, target, false); ++ case VSX_BUILTIN_LXVW4X_V16QI: ++ return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi, ++ exp, target, false); ++ break; + default: + break; + /* Fall through. */ +@@ -11099,6 +11141,8 @@ + + long_integer_type_internal_node = long_integer_type_node; + long_unsigned_type_internal_node = long_unsigned_type_node; ++ long_long_integer_type_internal_node = long_long_integer_type_node; ++ long_long_unsigned_type_internal_node = long_long_unsigned_type_node; + intQI_type_internal_node = intQI_type_node; + uintQI_type_internal_node = unsigned_intQI_type_node; + intHI_type_internal_node = intHI_type_node; +@@ -11108,7 +11152,7 @@ + intDI_type_internal_node = intDI_type_node; + uintDI_type_internal_node = unsigned_intDI_type_node; + float_type_internal_node = float_type_node; +- double_type_internal_node = float_type_node; ++ double_type_internal_node = double_type_node; + void_type_internal_node = void_type_node; + + /* Initialize the modes for builtin_function_type, mapping a machine mode to +@@ -11631,19 +11675,11 @@ + size_t i; + tree ftype; + +- tree pfloat_type_node = build_pointer_type (float_type_node); +- tree pint_type_node = build_pointer_type (integer_type_node); +- tree pshort_type_node = build_pointer_type (short_integer_type_node); +- tree pchar_type_node = build_pointer_type (char_type_node); +- + tree pvoid_type_node = build_pointer_type (void_type_node); + +- tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); +- tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); +- tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); +- tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); +- +- tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); ++ tree pcvoid_type_node ++ = build_pointer_type (build_qualified_type (void_type_node, ++ TYPE_QUAL_CONST)); + + tree int_ftype_opaque + = build_function_type_list (integer_type_node, +@@ -11666,26 +11702,6 @@ + = build_function_type_list (integer_type_node, + integer_type_node, V4SI_type_node, + V4SI_type_node, NULL_TREE); +- tree v4sf_ftype_pcfloat +- = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); +- tree void_ftype_pfloat_v4sf +- = build_function_type_list (void_type_node, +- pfloat_type_node, V4SF_type_node, NULL_TREE); +- tree v4si_ftype_pcint +- = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); +- tree void_ftype_pint_v4si +- = build_function_type_list (void_type_node, +- pint_type_node, V4SI_type_node, NULL_TREE); +- tree v8hi_ftype_pcshort +- = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); +- tree void_ftype_pshort_v8hi +- = build_function_type_list (void_type_node, +- pshort_type_node, V8HI_type_node, NULL_TREE); +- tree v16qi_ftype_pcchar +- = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); +- tree void_ftype_pchar_v16qi +- = build_function_type_list (void_type_node, +- pchar_type_node, V16QI_type_node, NULL_TREE); + tree void_ftype_v4si + = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); + tree v8hi_ftype_void +@@ -11697,16 +11713,32 @@ + + tree opaque_ftype_long_pcvoid + = build_function_type_list (opaque_V4SI_type_node, +- long_integer_type_node, pcvoid_type_node, NULL_TREE); ++ long_integer_type_node, pcvoid_type_node, ++ NULL_TREE); + tree v16qi_ftype_long_pcvoid + = build_function_type_list (V16QI_type_node, +- long_integer_type_node, pcvoid_type_node, NULL_TREE); ++ long_integer_type_node, pcvoid_type_node, ++ NULL_TREE); + tree v8hi_ftype_long_pcvoid + = build_function_type_list (V8HI_type_node, +- long_integer_type_node, pcvoid_type_node, NULL_TREE); ++ long_integer_type_node, pcvoid_type_node, ++ NULL_TREE); + tree v4si_ftype_long_pcvoid + = build_function_type_list (V4SI_type_node, +- long_integer_type_node, pcvoid_type_node, NULL_TREE); ++ long_integer_type_node, pcvoid_type_node, ++ NULL_TREE); ++ tree v4sf_ftype_long_pcvoid ++ = build_function_type_list (V4SF_type_node, ++ long_integer_type_node, pcvoid_type_node, ++ NULL_TREE); ++ tree v2df_ftype_long_pcvoid ++ = build_function_type_list (V2DF_type_node, ++ long_integer_type_node, pcvoid_type_node, ++ NULL_TREE); ++ tree v2di_ftype_long_pcvoid ++ = build_function_type_list (V2DI_type_node, ++ long_integer_type_node, pcvoid_type_node, ++ NULL_TREE); + + tree void_ftype_opaque_long_pvoid + = build_function_type_list (void_type_node, +@@ -11724,6 +11756,18 @@ + = build_function_type_list (void_type_node, + V8HI_type_node, long_integer_type_node, + pvoid_type_node, NULL_TREE); ++ tree void_ftype_v4sf_long_pvoid ++ = build_function_type_list (void_type_node, ++ V4SF_type_node, long_integer_type_node, ++ pvoid_type_node, NULL_TREE); ++ tree void_ftype_v2df_long_pvoid ++ = build_function_type_list (void_type_node, ++ V2DF_type_node, long_integer_type_node, ++ pvoid_type_node, NULL_TREE); ++ tree void_ftype_v2di_long_pvoid ++ = build_function_type_list (void_type_node, ++ V2DI_type_node, long_integer_type_node, ++ pvoid_type_node, NULL_TREE); + tree int_ftype_int_v8hi_v8hi + = build_function_type_list (integer_type_node, + integer_type_node, V8HI_type_node, +@@ -11755,22 +11799,6 @@ + pcvoid_type_node, integer_type_node, + integer_type_node, NULL_TREE); + +- def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, +- ALTIVEC_BUILTIN_LD_INTERNAL_4sf); +- def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, +- ALTIVEC_BUILTIN_ST_INTERNAL_4sf); +- def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, +- ALTIVEC_BUILTIN_LD_INTERNAL_4si); +- def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, +- ALTIVEC_BUILTIN_ST_INTERNAL_4si); +- def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, +- ALTIVEC_BUILTIN_LD_INTERNAL_8hi); +- def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, +- ALTIVEC_BUILTIN_ST_INTERNAL_8hi); +- def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, +- ALTIVEC_BUILTIN_LD_INTERNAL_16qi); +- def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, +- ALTIVEC_BUILTIN_ST_INTERNAL_16qi); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); +@@ -11802,6 +11830,35 @@ + def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX); + def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX); + ++ def_builtin (MASK_VSX, "__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid, ++ VSX_BUILTIN_LXVD2X_V2DF); ++ def_builtin (MASK_VSX, "__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid, ++ VSX_BUILTIN_LXVD2X_V2DI); ++ def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid, ++ VSX_BUILTIN_LXVW4X_V4SF); ++ def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid, ++ VSX_BUILTIN_LXVW4X_V4SI); ++ def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v8hi", ++ v8hi_ftype_long_pcvoid, VSX_BUILTIN_LXVW4X_V8HI); ++ def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v16qi", ++ v16qi_ftype_long_pcvoid, VSX_BUILTIN_LXVW4X_V16QI); ++ def_builtin (MASK_VSX, "__builtin_vsx_stxvd2x_v2df", ++ void_ftype_v2df_long_pvoid, VSX_BUILTIN_STXVD2X_V2DF); ++ def_builtin (MASK_VSX, "__builtin_vsx_stxvd2x_v2di", ++ void_ftype_v2di_long_pvoid, VSX_BUILTIN_STXVD2X_V2DI); ++ def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v4sf", ++ void_ftype_v4sf_long_pvoid, VSX_BUILTIN_STXVW4X_V4SF); ++ def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v4si", ++ void_ftype_v4si_long_pvoid, VSX_BUILTIN_STXVW4X_V4SI); ++ def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v8hi", ++ void_ftype_v8hi_long_pvoid, VSX_BUILTIN_STXVW4X_V8HI); ++ def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v16qi", ++ void_ftype_v16qi_long_pvoid, VSX_BUILTIN_STXVW4X_V16QI); ++ def_builtin (MASK_VSX, "__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid, ++ VSX_BUILTIN_VEC_LD); ++ def_builtin (MASK_VSX, "__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid, ++ VSX_BUILTIN_VEC_ST); ++ + if (rs6000_cpu == PROCESSOR_CELL) + { + def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX); +@@ -18506,7 +18563,7 @@ + p = rtvec_alloc ((lr ? 4 : 3) + n_regs); + + if (!savep && lr) +- RTVEC_ELT (p, offset++) = gen_rtx_RETURN (VOIDmode); ++ RTVEC_ELT (p, offset++) = ret_rtx; + + RTVEC_ELT (p, offset++) + = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 65)); +@@ -19581,7 +19638,7 @@ + alloc_rname = ggc_strdup (rname); + + j = 0; +- RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode); ++ RTVEC_ELT (p, j++) = ret_rtx; + RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, + gen_rtx_REG (Pmode, + LR_REGNO)); +@@ -20197,7 +20254,7 @@ + else + p = rtvec_alloc (2); + +- RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); ++ RTVEC_ELT (p, 0) = ret_rtx; + RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr) + ? gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 65)) + : gen_rtx_CLOBBER (VOIDmode, +@@ -20638,7 +20695,7 @@ + gen_rtx_USE (VOIDmode, + gen_rtx_REG (SImode, + LR_REGNO)), +- gen_rtx_RETURN (VOIDmode)))); ++ ret_rtx))); + SIBLING_CALL_P (insn) = 1; + emit_barrier (); + +@@ -25811,4 +25868,29 @@ + } + } + ++/* Given a memory reference, if it is not in the form for altivec memory ++ reference instructions (i.e. reg or reg+reg addressing with AND of -16), ++ convert to the altivec format. */ ++ ++rtx ++rs6000_address_for_altivec (rtx x) ++{ ++ gcc_assert (MEM_P (x)); ++ if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x))) ++ { ++ rtx addr = XEXP (x, 0); ++ int strict_p = (reload_in_progress || reload_completed); ++ ++ if (!legitimate_indexed_address_p (addr, strict_p) ++ && !legitimate_indirect_address_p (addr, strict_p)) ++ addr = copy_to_mode_reg (Pmode, addr); ++ ++ addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16)); ++ x = change_address (x, GET_MODE (x), addr); ++ } ++ ++ return x; ++} ++ ++ + #include "gt-rs6000.h" +--- a/src/gcc/config/rs6000/rs6000.h ++++ b/src/gcc/config/rs6000/rs6000.h +@@ -1,6 +1,7 @@ + /* Definitions of target machine for GNU compiler, for IBM RS/6000. + Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 ++ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, ++ 2010, 2011 + Free Software Foundation, Inc. + Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) + +@@ -2489,6 +2490,8 @@ + RS6000_BTI_pixel_V8HI, /* __vector __pixel */ + RS6000_BTI_long, /* long_integer_type_node */ + RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ ++ RS6000_BTI_long_long, /* long_long_integer_type_node */ ++ RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ + RS6000_BTI_INTQI, /* intQI_type_node */ + RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ + RS6000_BTI_INTHI, /* intHI_type_node */ +@@ -2532,6 +2535,8 @@ + #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) + #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) + ++#define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) ++#define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) + #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) + #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) + #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) +--- a/src/gcc/config/rs6000/vector.md ++++ b/src/gcc/config/rs6000/vector.md +@@ -3,7 +3,7 @@ + ;; expander, and the actual vector instructions will be in altivec.md and + ;; vsx.md + +-;; Copyright (C) 2009, 2010 ++;; Copyright (C) 2009, 2010, 2011 + ;; Free Software Foundation, Inc. + ;; Contributed by Michael Meissner + +@@ -123,6 +123,43 @@ + DONE; + }) + ++;; Vector floating point load/store instructions that uses the Altivec ++;; instructions even if we are compiling for VSX, since the Altivec ++;; instructions silently ignore the bottom 3 bits of the address, and VSX does ++;; not. ++(define_expand "vector_altivec_load_" ++ [(set (match_operand:VEC_M 0 "vfloat_operand" "") ++ (match_operand:VEC_M 1 "memory_operand" ""))] ++ "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" ++ " ++{ ++ gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)); ++ ++ if (VECTOR_MEM_VSX_P (mode)) ++ { ++ operands[1] = rs6000_address_for_altivec (operands[1]); ++ emit_insn (gen_altivec_lvx_ (operands[0], operands[1])); ++ DONE; ++ } ++}") ++ ++(define_expand "vector_altivec_store_" ++ [(set (match_operand:VEC_M 0 "memory_operand" "") ++ (match_operand:VEC_M 1 "vfloat_operand" ""))] ++ "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" ++ " ++{ ++ gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)); ++ ++ if (VECTOR_MEM_VSX_P (mode)) ++ { ++ operands[0] = rs6000_address_for_altivec (operands[0]); ++ emit_insn (gen_altivec_stvx_ (operands[0], operands[1])); ++ DONE; ++ } ++}") ++ ++ + + ;; Reload patterns for vector operations. We may need an addtional base + ;; register to convert the reg+offset addressing to reg+reg for vector +--- a/src/gcc/config/rs6000/vsx.md ++++ b/src/gcc/config/rs6000/vsx.md +@@ -1,5 +1,5 @@ + ;; VSX patterns. +-;; Copyright (C) 2009 ++;; Copyright (C) 2009, 2010, 2011 + ;; Free Software Foundation, Inc. + ;; Contributed by Michael Meissner + +@@ -309,6 +309,19 @@ + } + [(set_attr "type" "vecstore,vecload,vecsimple,*,*,*,vecsimple,*,vecstore,vecload")]) + ++;; Explicit load/store expanders for the builtin functions ++(define_expand "vsx_load_" ++ [(set (match_operand:VSX_M 0 "vsx_register_operand" "") ++ (match_operand:VSX_M 1 "memory_operand" ""))] ++ "VECTOR_MEM_VSX_P (mode)" ++ "") ++ ++(define_expand "vsx_store_" ++ [(set (match_operand:VEC_M 0 "memory_operand" "") ++ (match_operand:VEC_M 1 "vsx_register_operand" ""))] ++ "VECTOR_MEM_VSX_P (mode)" ++ "") ++ + + ;; VSX scalar and vector floating point arithmetic instructions + (define_insn "*vsx_add3" +@@ -866,33 +879,34 @@ + ;; the fprs because we don't want to add the altivec registers to movdi/movsi. + ;; For the unsigned tests, there isn't a generic double -> unsigned conversion + ;; in rs6000.md so don't test VECTOR_UNIT_VSX_P, just test against VSX. ++;; Don't use vsx_register_operand here, use gpc_reg_operand to match rs6000.md. + (define_insn "vsx_float2" +- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") +- (float:VSX_B (match_operand: 1 "vsx_register_operand" ",")))] ++ [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=,?wa") ++ (float:VSX_B (match_operand: 1 "gpc_reg_operand" ",")))] + "VECTOR_UNIT_VSX_P (mode)" + "xcvsx %x0,%x1" + [(set_attr "type" "") + (set_attr "fp_type" "")]) + + (define_insn "vsx_floatuns2" +- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") +- (unsigned_float:VSX_B (match_operand: 1 "vsx_register_operand" ",")))] ++ [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=,?wa") ++ (unsigned_float:VSX_B (match_operand: 1 "gpc_reg_operand" ",")))] + "VECTOR_UNIT_VSX_P (mode)" + "xcvux %x0,%x1" + [(set_attr "type" "") + (set_attr "fp_type" "")]) + + (define_insn "vsx_fix_trunc2" +- [(set (match_operand: 0 "vsx_register_operand" "=,?") +- (fix: (match_operand:VSX_B 1 "vsx_register_operand" ",wa")))] ++ [(set (match_operand: 0 "gpc_reg_operand" "=,?") ++ (fix: (match_operand:VSX_B 1 "gpc_reg_operand" ",wa")))] + "VECTOR_UNIT_VSX_P (mode)" + "xcvsxs %x0,%x1" + [(set_attr "type" "") + (set_attr "fp_type" "")]) + + (define_insn "vsx_fixuns_trunc2" +- [(set (match_operand: 0 "vsx_register_operand" "=,?") +- (unsigned_fix: (match_operand:VSX_B 1 "vsx_register_operand" ",wa")))] ++ [(set (match_operand: 0 "gpc_reg_operand" "=,?") ++ (unsigned_fix: (match_operand:VSX_B 1 "gpc_reg_operand" ",wa")))] + "VECTOR_UNIT_VSX_P (mode)" + "xcvuxs %x0,%x1" + [(set_attr "type" "") +--- a/src/gcc/config/rx/predicates.md ++++ b/src/gcc/config/rx/predicates.md +@@ -1,5 +1,5 @@ + ;; Predicate definitions for Renesas RX. +-;; Copyright (C) 2008, 2009 Free Software Foundation, Inc. ++;; Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc. + ;; Contributed by Red Hat. + ;; + ;; This file is part of GCC. +@@ -37,19 +37,19 @@ + ;; Only small integers or a value in a register are permitted. + + (define_predicate "rx_shift_operand" +- (match_code "const_int,reg") +- { +- if (CONST_INT_P (op)) +- return IN_RANGE (INTVAL (op), 0, 31); +- return true; +- } ++ (ior (match_operand 0 "register_operand") ++ (and (match_code "const_int") ++ (match_test "IN_RANGE (INTVAL (op), 0, 31)"))) + ) + + (define_predicate "rx_constshift_operand" +- (match_code "const_int") +- { +- return IN_RANGE (INTVAL (op), 0, 31); +- } ++ (and (match_code "const_int") ++ (match_test "IN_RANGE (INTVAL (op), 0, 31)")) ++) ++ ++(define_predicate "rx_restricted_mem_operand" ++ (and (match_code "mem") ++ (match_test "rx_is_restricted_memory_address (XEXP (op, 0), mode)")) + ) + + ;; Check that the operand is suitable as the source operand +@@ -57,20 +57,9 @@ + ;; and a restricted subset of memory addresses are allowed. + + (define_predicate "rx_source_operand" +- (match_code "const_int,const_double,const,symbol_ref,label_ref,reg,mem") +- { +- if (CONSTANT_P (op)) +- return rx_is_legitimate_constant (op); +- +- if (! MEM_P (op)) +- return true; +- +- /* Do not allow size conversions whilst accessing memory. */ +- if (GET_MODE (op) != mode) +- return false; +- +- return rx_is_restricted_memory_address (XEXP (op, 0), mode); +- } ++ (ior (match_operand 0 "register_operand") ++ (match_operand 0 "immediate_operand") ++ (match_operand 0 "rx_restricted_mem_operand")) + ) + + ;; Check that the operand is suitable as the source operand +@@ -79,16 +68,8 @@ + ;; CONST_INTs are not. + + (define_predicate "rx_compare_operand" +- (match_code "subreg,reg,mem") +- { +- if (GET_CODE (op) == SUBREG) +- return REG_P (XEXP (op, 0)); +- +- if (! MEM_P (op)) +- return true; +- +- return rx_is_restricted_memory_address (XEXP (op, 0), mode); +- } ++ (ior (match_operand 0 "register_operand") ++ (match_operand 0 "rx_restricted_mem_operand")) + ) + + ;; Return true if OP is a store multiple operation. This looks like: +@@ -293,3 +274,24 @@ + element = XVECEXP (op, 0, count - 1); + return GET_CODE (element) == RETURN; + }) ++ ++(define_predicate "label_ref_operand" ++ (match_code "label_ref") ++) ++ ++(define_predicate "rx_z_comparison_operator" ++ (match_code "eq,ne") ++) ++ ++(define_predicate "rx_zs_comparison_operator" ++ (match_code "eq,ne") ++) ++ ++;; GT and LE omitted due to operand swap required. ++(define_predicate "rx_fp_comparison_operator" ++ (match_code "eq,ne,lt,ge,ordered,unordered") ++) ++ ++(define_predicate "rshift_operator" ++ (match_code "ashiftrt,lshiftrt") ++) +--- a/src/gcc/config/rx/rx-modes.def ++++ b/src/gcc/config/rx/rx-modes.def +@@ -1,5 +1,6 @@ +-/* Definitions of target machine for GNU compiler, for RX. +- Copyright (C) 2010 by Nick Clifton (nickc@redhat.com). ++/* Definitions of target specific machine modes for the RX. ++ Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. ++ Contributed by Red Hat. + + This file is part of GCC. + +@@ -20,3 +21,5 @@ + CC_MODE (CC_ZS); + CC_MODE (CC_ZSO); + CC_MODE (CC_ZSC); ++ ++CC_MODE (CC_F); /* fcmp */ +--- a/src/gcc/config/rx/rx-protos.h ++++ b/src/gcc/config/rx/rx-protos.h +@@ -1,5 +1,5 @@ + /* Exported function prototypes from the Renesas RX backend. +- Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + Contributed by Red Hat. + + This file is part of GCC. +@@ -35,15 +35,17 @@ + extern void rx_emit_stack_popm (rtx *, bool); + extern void rx_emit_stack_pushm (rtx *); + extern void rx_expand_epilogue (bool); +-extern bool rx_expand_insv (rtx *); + extern const char * rx_gen_cond_branch_template (rtx, bool); + extern char * rx_gen_move_template (rtx *, bool); + extern bool rx_is_legitimate_constant (rtx); + extern bool rx_is_mode_dependent_addr (rtx); + extern bool rx_is_restricted_memory_address (rtx, Mmode); ++extern bool rx_match_ccmode (rtx, Mmode); + extern void rx_notice_update_cc (rtx body, rtx insn); + extern void rx_print_operand (FILE *, rtx, int); + extern void rx_print_operand_address (FILE *, rtx); ++extern Mmode rx_select_cc_mode (enum rtx_code, rtx, rtx); ++extern void rx_split_cbranch (Mmode, enum rtx_code, rtx, rtx, rtx); + #endif + + #ifdef TREE_CODE +--- a/src/gcc/config/rx/rx.c ++++ b/src/gcc/config/rx/rx.c +@@ -1,5 +1,5 @@ + /* Subroutines used for code generation on Renesas RX processors. +- Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + Contributed by Red Hat. + + This file is part of GCC. +@@ -51,6 +51,12 @@ + #include "target-def.h" + #include "langhooks.h" + ++#define CC_FLAG_S (1 << 0) ++#define CC_FLAG_Z (1 << 1) ++#define CC_FLAG_O (1 << 2) ++#define CC_FLAG_C (1 << 3) ++#define CC_FLAG_FP (1 << 4) /* Fake, to differentiate CC_Fmode. */ ++ + enum rx_cpu_types rx_cpu_type = RX600; + + /* Return true if OP is a reference to an object in a small data area. */ +@@ -312,9 +318,18 @@ + break; + } + ++ case CONST: ++ if (GET_CODE (XEXP (addr, 0)) == UNSPEC) ++ { ++ addr = XEXP (addr, 0); ++ gcc_assert (XINT (addr, 1) == UNSPEC_CONST); ++ ++ addr = XVECEXP (addr, 0, 0); ++ gcc_assert (CONST_INT_P (addr)); ++ } ++ /* Fall through. */ + case LABEL_REF: + case SYMBOL_REF: +- case CONST: + fprintf (file, "#"); + default: + output_addr_const (file, addr); +@@ -351,8 +366,75 @@ + return true; + } + ++/* Convert a CC_MODE to the set of flags that it represents. */ ++ ++static unsigned int ++flags_from_mode (enum machine_mode mode) ++{ ++ switch (mode) ++ { ++ case CC_ZSmode: ++ return CC_FLAG_S | CC_FLAG_Z; ++ case CC_ZSOmode: ++ return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O; ++ case CC_ZSCmode: ++ return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_C; ++ case CCmode: ++ return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O | CC_FLAG_C; ++ case CC_Fmode: ++ return CC_FLAG_FP; ++ default: ++ gcc_unreachable (); ++ } ++} ++ ++/* Convert a set of flags to a CC_MODE that can implement it. */ ++ ++static enum machine_mode ++mode_from_flags (unsigned int f) ++{ ++ if (f & CC_FLAG_FP) ++ return CC_Fmode; ++ if (f & CC_FLAG_O) ++ { ++ if (f & CC_FLAG_C) ++ return CCmode; ++ else ++ return CC_ZSOmode; ++ } ++ else if (f & CC_FLAG_C) ++ return CC_ZSCmode; ++ else ++ return CC_ZSmode; ++} ++ ++/* Convert an RTX_CODE to the set of flags needed to implement it. ++ This assumes an integer comparison. */ + +-int rx_float_compare_mode; ++static unsigned int ++flags_from_code (enum rtx_code code) ++{ ++ switch (code) ++ { ++ case LT: ++ case GE: ++ return CC_FLAG_S | CC_FLAG_O; ++ case GT: ++ case LE: ++ return CC_FLAG_S | CC_FLAG_O | CC_FLAG_Z; ++ case GEU: ++ case LTU: ++ return CC_FLAG_C; ++ case GTU: ++ case LEU: ++ return CC_FLAG_C | CC_FLAG_Z; ++ case EQ: ++ case NE: ++ return CC_FLAG_Z; ++ default: ++ gcc_unreachable (); ++ } ++} + + /* Handles the insertion of a single operand into the assembler output. + The % directives supported are: +@@ -393,21 +475,48 @@ + break; + + case 'B': +- switch (GET_CODE (op)) +- { +- case LT: fprintf (file, "lt"); break; +- case GE: fprintf (file, "ge"); break; +- case GT: fprintf (file, "gt"); break; +- case LE: fprintf (file, "le"); break; +- case GEU: fprintf (file, "geu"); break; +- case LTU: fprintf (file, "ltu"); break; +- case GTU: fprintf (file, "gtu"); break; +- case LEU: fprintf (file, "leu"); break; +- case EQ: fprintf (file, "eq"); break; +- case NE: fprintf (file, "ne"); break; +- default: debug_rtx (op); gcc_unreachable (); +- } +- break; ++ { ++ enum rtx_code code = GET_CODE (op); ++ enum machine_mode mode = GET_MODE (XEXP (op, 0)); ++ const char * ret; ++ ++ if (mode == CC_Fmode) ++ { ++ /* C flag is undefined, and O flag carries unordered. None of the ++ branch combinations that include O use it helpfully. */ ++ switch (code) ++ { ++ case ORDERED: ret = "no"; break; ++ case UNORDERED: ret = "o"; break; ++ case LT: ret = "n"; break; ++ case GE: ret = "pz"; break; ++ case EQ: ret = "eq"; break; ++ case NE: ret = "ne"; break; ++ default: gcc_unreachable (); ++ } ++ } ++ else ++ { ++ switch (code) ++ { ++ case LT: ret = "lt"; break; ++ case GE: ret = "ge"; break; ++ case GT: ret = "gt"; break; ++ case LE: ret = "le"; break; ++ case GEU: ret = "geu"; break; ++ case LTU: ret = "ltu"; break; ++ case GTU: ret = "gtu"; break; ++ case LEU: ret = "leu"; break; ++ case EQ: ret = "eq"; break; ++ case NE: ret = "ne"; break; ++ default: gcc_unreachable (); ++ } ++ gcc_assert ((flags_from_code (code) ++ & ~flags_from_mode (mode)) == 0); ++ } ++ fputs (ret, file); ++ break; ++ } + + case 'C': + gcc_assert (CONST_INT_P (op)); +@@ -698,51 +807,6 @@ + extension, src_template, dst_template); + return out_template; + } +- +-/* Returns an assembler template for a conditional branch instruction. */ +- +-const char * +-rx_gen_cond_branch_template (rtx condition, bool reversed) +-{ +- enum rtx_code code = GET_CODE (condition); +- +- if (reversed) +- { +- if (rx_float_compare_mode) +- code = reverse_condition_maybe_unordered (code); +- else +- code = reverse_condition (code); +- } +- +- /* We do not worry about encoding the branch length here as GAS knows +- how to choose the smallest version, and how to expand a branch that +- is to a destination that is out of range. */ +- +- switch (code) +- { +- case UNEQ: return "bo\t1f\n\tbeq\t%0\n1:"; +- case LTGT: return "bo\t1f\n\tbne\t%0\n1:"; +- case UNLT: return "bo\t1f\n\tbn\t%0\n1:"; +- case UNGE: return "bo\t1f\n\tbpz\t%0\n1:"; +- case UNLE: return "bo\t1f\n\tbgt\t1f\n\tbra\t%0\n1:"; +- case UNGT: return "bo\t1f\n\tble\t1f\n\tbra\t%0\n1:"; +- case UNORDERED: return "bo\t%0"; +- case ORDERED: return "bno\t%0"; +- +- case LT: return rx_float_compare_mode ? "bn\t%0" : "blt\t%0"; +- case GE: return rx_float_compare_mode ? "bpz\t%0" : "bge\t%0"; +- case GT: return "bgt\t%0"; +- case LE: return "ble\t%0"; +- case GEU: return "bgeu\t%0"; +- case LTU: return "bltu\t%0"; +- case GTU: return "bgtu\t%0"; +- case LEU: return "bleu\t%0"; +- case EQ: return "beq\t%0"; +- case NE: return "bne\t%0"; +- default: +- gcc_unreachable (); +- } +-} + + /* Return VALUE rounded up to the next ALIGNMENT boundary. */ + +@@ -821,7 +885,35 @@ + const_tree fn_decl_or_type ATTRIBUTE_UNUSED, + bool outgoing ATTRIBUTE_UNUSED) + { +- return gen_rtx_REG (TYPE_MODE (ret_type), FUNC_RETURN_REGNUM); ++ enum machine_mode mode = TYPE_MODE (ret_type); ++ ++ /* RX ABI specifies that small integer types are ++ promoted to int when returned by a function. */ ++ if (GET_MODE_SIZE (mode) > 0 ++ && GET_MODE_SIZE (mode) < 4 ++ && ! COMPLEX_MODE_P (mode)) ++ return gen_rtx_REG (SImode, FUNC_RETURN_REGNUM); ++ ++ return gen_rtx_REG (mode, FUNC_RETURN_REGNUM); ++} ++ ++/* TARGET_PROMOTE_FUNCTION_MODE must behave in the same way with ++ regard to function returns as does TARGET_FUNCTION_VALUE. */ ++ ++static enum machine_mode ++rx_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, ++ enum machine_mode mode, ++ int * punsignedp ATTRIBUTE_UNUSED, ++ const_tree funtype ATTRIBUTE_UNUSED, ++ int for_return) ++{ ++ if (for_return != 1 ++ || GET_MODE_SIZE (mode) >= 4 ++ || COMPLEX_MODE_P (mode) ++ || GET_MODE_SIZE (mode) < 1) ++ return mode; ++ ++ return SImode; + } + + static bool +@@ -1058,7 +1150,13 @@ + + for (save_mask = high = low = 0, reg = 1; reg < CC_REGNUM; reg++) + { +- if (df_regs_ever_live_p (reg) ++ if ((df_regs_ever_live_p (reg) ++ /* Always save all call clobbered registers inside non-leaf ++ interrupt handlers, even if they are not live - they may ++ be used in (non-interrupt aware) routines called from this one. */ ++ || (call_used_regs[reg] ++ && is_interrupt_func (NULL_TREE) ++ && ! current_function_is_leaf)) + && (! call_used_regs[reg] + /* Even call clobbered registered must + be pushed inside interrupt handlers. */ +@@ -1213,6 +1311,59 @@ + } + } + ++static bool ++ok_for_max_constant (HOST_WIDE_INT val) ++{ ++ if (rx_max_constant_size == 0 || rx_max_constant_size == 4) ++ /* If there is no constraint on the size of constants ++ used as operands, then any value is legitimate. */ ++ return true; ++ ++ /* rx_max_constant_size specifies the maximum number ++ of bytes that can be used to hold a signed value. */ ++ return IN_RANGE (val, (-1 << (rx_max_constant_size * 8)), ++ ( 1 << (rx_max_constant_size * 8))); ++} ++ ++/* Generate an ADD of SRC plus VAL into DEST. ++ Handles the case where VAL is too big for max_constant_value. ++ Sets FRAME_RELATED_P on the insn if IS_FRAME_RELATED is true. */ ++ ++static void ++gen_safe_add (rtx dest, rtx src, rtx val, bool is_frame_related) ++{ ++ rtx insn; ++ ++ if (val == NULL_RTX || INTVAL (val) == 0) ++ { ++ gcc_assert (dest != src); ++ ++ insn = emit_move_insn (dest, src); ++ } ++ else if (ok_for_max_constant (INTVAL (val))) ++ insn = emit_insn (gen_addsi3 (dest, src, val)); ++ else ++ { ++ /* Wrap VAL in an UNSPEC so that rx_is_legitimate_constant ++ will not reject it. */ ++ val = gen_rtx_CONST (SImode, gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_CONST)); ++ insn = emit_insn (gen_addsi3 (dest, src, val)); ++ ++ if (is_frame_related) ++ /* We have to provide our own frame related note here ++ as the dwarf2out code cannot be expected to grok ++ our unspec. */ ++ add_reg_note (insn, REG_FRAME_RELATED_EXPR, ++ gen_rtx_SET (SImode, dest, ++ gen_rtx_PLUS (SImode, src, val))); ++ return; ++ } ++ ++ if (is_frame_related) ++ RTX_FRAME_RELATED_P (insn) = 1; ++ return; ++} ++ + void + rx_expand_prologue (void) + { +@@ -1298,23 +1449,12 @@ + emit_insn (gen_stack_pushm (GEN_INT (2 * UNITS_PER_WORD), + gen_rx_store_vector (acc_low, acc_high))); + } +- +- frame_size += 2 * UNITS_PER_WORD; + } + + /* If needed, set up the frame pointer. */ + if (frame_pointer_needed) +- { +- if (frame_size) +- insn = emit_insn (gen_addsi3 (frame_pointer_rtx, stack_pointer_rtx, +- GEN_INT (- (HOST_WIDE_INT) frame_size))); +- else +- insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); +- +- RTX_FRAME_RELATED_P (insn) = 1; +- } +- +- insn = NULL_RTX; ++ gen_safe_add (frame_pointer_rtx, stack_pointer_rtx, ++ GEN_INT (- (HOST_WIDE_INT) frame_size), true); + + /* Allocate space for the outgoing args. + If the stack frame has not already been set up then handle this as well. */ +@@ -1323,29 +1463,26 @@ + if (frame_size) + { + if (frame_pointer_needed) +- insn = emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx, +- GEN_INT (- (HOST_WIDE_INT) +- stack_size))); ++ gen_safe_add (stack_pointer_rtx, frame_pointer_rtx, ++ GEN_INT (- (HOST_WIDE_INT) stack_size), true); + else +- insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, +- GEN_INT (- (HOST_WIDE_INT) +- (frame_size + stack_size)))); ++ gen_safe_add (stack_pointer_rtx, stack_pointer_rtx, ++ GEN_INT (- (HOST_WIDE_INT) (frame_size + stack_size)), ++ true); + } + else +- insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, +- GEN_INT (- (HOST_WIDE_INT) stack_size))); ++ gen_safe_add (stack_pointer_rtx, stack_pointer_rtx, ++ GEN_INT (- (HOST_WIDE_INT) stack_size), true); + } + else if (frame_size) + { + if (! frame_pointer_needed) +- insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, +- GEN_INT (- (HOST_WIDE_INT) frame_size))); ++ gen_safe_add (stack_pointer_rtx, stack_pointer_rtx, ++ GEN_INT (- (HOST_WIDE_INT) frame_size), true); + else +- insn = emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); ++ gen_safe_add (stack_pointer_rtx, frame_pointer_rtx, NULL_RTX, ++ true); + } +- +- if (insn != NULL_RTX) +- RTX_FRAME_RELATED_P (insn) = 1; + } + + static void +@@ -1425,7 +1562,7 @@ + : plus_constant (stack_pointer_rtx, + i * UNITS_PER_WORD))); + +- XVECEXP (vector, 0, count - 1) = gen_rtx_RETURN (VOIDmode); ++ XVECEXP (vector, 0, count - 1) = ret_rtx; + + return vector; + } +@@ -1523,8 +1660,8 @@ + { + /* Cannot use the special instructions - deconstruct by hand. */ + if (total_size) +- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, +- GEN_INT (total_size))); ++ gen_safe_add (stack_pointer_rtx, stack_pointer_rtx, ++ GEN_INT (total_size), false); + + if (MUST_SAVE_ACC_REGISTER) + { +@@ -1615,8 +1752,8 @@ + return; + } + +- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, +- GEN_INT (total_size))); ++ gen_safe_add (stack_pointer_rtx, stack_pointer_rtx, ++ GEN_INT (total_size), false); + } + + if (low) +@@ -1893,7 +2030,7 @@ + if (rx_cpu_type == RX610) + return NULL_RTX; + +- if (! CONST_INT_P (arg) || ! IN_RANGE (arg, 0, (1 << 4) - 1)) ++ if (! CONST_INT_P (arg) || ! IN_RANGE (INTVAL (arg), 0, (1 << 4) - 1)) + return NULL_RTX; + + emit_insn (gen_mvtipl (arg)); +@@ -1962,6 +2099,31 @@ + return target; + } + ++static int ++valid_psw_flag (rtx op, const char *which) ++{ ++ static int mvtc_inform_done = 0; ++ ++ if (GET_CODE (op) == CONST_INT) ++ switch (INTVAL (op)) ++ { ++ case 0: case 'c': case 'C': ++ case 1: case 'z': case 'Z': ++ case 2: case 's': case 'S': ++ case 3: case 'o': case 'O': ++ case 8: case 'i': case 'I': ++ case 9: case 'u': case 'U': ++ return 1; ++ } ++ ++ error ("__builtin_rx_%s takes 'C', 'Z', 'S', 'O', 'I', or 'U'", which); ++ if (!mvtc_inform_done) ++ error ("use __builtin_rx_mvtc (0, ... ) to write arbitrary values to PSW"); ++ mvtc_inform_done = 1; ++ ++ return 0; ++} ++ + static rtx + rx_expand_builtin (tree exp, + rtx target, +@@ -1977,10 +2139,14 @@ + switch (fcode) + { + case RX_BUILTIN_BRK: emit_insn (gen_brk ()); return NULL_RTX; +- case RX_BUILTIN_CLRPSW: return rx_expand_void_builtin_1_arg +- (op, gen_clrpsw, false); +- case RX_BUILTIN_SETPSW: return rx_expand_void_builtin_1_arg +- (op, gen_setpsw, false); ++ case RX_BUILTIN_CLRPSW: ++ if (! valid_psw_flag (op, "clrpsw")) ++ return NULL_RTX; ++ return rx_expand_void_builtin_1_arg (op, gen_clrpsw, false); ++ if (! valid_psw_flag (op, "setpsw")) ++ return NULL_RTX; ++ return rx_expand_void_builtin_1_arg (op, gen_setpsw, false); ++ case RX_BUILTIN_SETPSW: + case RX_BUILTIN_INT: return rx_expand_void_builtin_1_arg + (op, gen_int, false); + case RX_BUILTIN_MACHI: return rx_expand_builtin_mac (exp, gen_machi); +@@ -2187,6 +2353,13 @@ + } + } + ++static void ++rx_option_override (void) ++{ ++ /* This target defaults to strict volatile bitfields. */ ++ if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) ++ flag_strict_volatile_bitfields = 1; ++} + + static bool + rx_allocate_stack_slots_for_args (void) +@@ -2233,50 +2406,10 @@ + static bool + rx_is_ms_bitfield_layout (const_tree record_type ATTRIBUTE_UNUSED) + { +- return TRUE; ++ /* The packed attribute overrides the MS behaviour. */ ++ return ! TYPE_PACKED (record_type); + } + +-/* Try to generate code for the "isnv" pattern which inserts bits +- into a word. +- operands[0] => Location to be altered. +- operands[1] => Number of bits to change. +- operands[2] => Starting bit. +- operands[3] => Value to insert. +- Returns TRUE if successful, FALSE otherwise. */ +- +-bool +-rx_expand_insv (rtx * operands) +-{ +- if (INTVAL (operands[1]) != 1 +- || ! CONST_INT_P (operands[3])) +- return false; +- +- if (MEM_P (operands[0]) +- && INTVAL (operands[2]) > 7) +- return false; +- +- switch (INTVAL (operands[3])) +- { +- case 0: +- if (MEM_P (operands[0])) +- emit_insn (gen_bitclr_in_memory (operands[0], operands[0], +- operands[2])); +- else +- emit_insn (gen_bitclr (operands[0], operands[0], operands[2])); +- break; +- case 1: +- case -1: +- if (MEM_P (operands[0])) +- emit_insn (gen_bitset_in_memory (operands[0], operands[0], +- operands[2])); +- else +- emit_insn (gen_bitset (operands[0], operands[0], operands[2])); +- break; +- default: +- return false; +- } +- return true; +-} + + /* Returns true if X a legitimate constant for an immediate + operand on the RX. X is already known to satisfy CONSTANT_P. */ +@@ -2284,8 +2417,6 @@ + bool + rx_is_legitimate_constant (rtx x) + { +- HOST_WIDE_INT val; +- + switch (GET_CODE (x)) + { + case CONST: +@@ -2308,7 +2439,9 @@ + case SYMBOL_REF: + return true; + +- /* One day we may have to handle UNSPEC constants here. */ ++ case UNSPEC: ++ return XINT (x, 1) == UNSPEC_CONST; ++ + default: + /* FIXME: Can this ever happen ? */ + abort (); +@@ -2328,17 +2461,7 @@ + break; + } + +- if (rx_max_constant_size == 0 || rx_max_constant_size == 4) +- /* If there is no constraint on the size of constants +- used as operands, then any value is legitimate. */ +- return true; +- +- val = INTVAL (x); +- +- /* rx_max_constant_size specifies the maximum number +- of bytes that can be used to hold a signed value. */ +- return IN_RANGE (val, (-1 << (rx_max_constant_size * 8)), +- ( 1 << (rx_max_constant_size * 8))); ++ return ok_for_max_constant (INTVAL (x)); + } + + static int +@@ -2462,211 +2585,83 @@ + } + } + ++/* Return a CC_MODE of which both M1 and M2 are subsets. */ ++ + static enum machine_mode + rx_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2) + { +- if (m1 == CCmode) +- return m2; +- if (m2 == CCmode) +- return m1; ++ unsigned f; ++ ++ /* Early out for identical modes. */ + if (m1 == m2) + return m1; +- if (m1 == CC_ZSmode) +- return m1; +- if (m2 == CC_ZSmode) +- return m2; +- return VOIDmode; ++ ++ /* There's no valid combination for FP vs non-FP. */ ++ f = flags_from_mode (m1) | flags_from_mode (m2); ++ if (f & CC_FLAG_FP) ++ return VOIDmode; ++ ++ /* Otherwise, see what mode can implement all the flags. */ ++ return mode_from_flags (f); + } + +-#define CC_FLAG_S (1 << 0) +-#define CC_FLAG_Z (1 << 1) +-#define CC_FLAG_O (1 << 2) +-#define CC_FLAG_C (1 << 3) ++/* Return the minimal CC mode needed to implement (CMP_CODE X Y). */ + +-static unsigned int +-flags_needed_for_conditional (rtx conditional) ++enum machine_mode ++rx_select_cc_mode (enum rtx_code cmp_code, rtx x, rtx y ATTRIBUTE_UNUSED) + { +- switch (GET_CODE (conditional)) +- { +- case LE: +- case GT: return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O; ++ if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) ++ return CC_Fmode; + +- case LEU: +- case GTU: return CC_FLAG_Z | CC_FLAG_C; ++ return mode_from_flags (flags_from_code (cmp_code)); ++} + +- case LT: +- case GE: return CC_FLAG_S | CC_FLAG_O; ++/* Split the conditional branch. Emit (COMPARE C1 C2) into CC_REG with ++ CC_MODE, and use that in branches based on that compare. */ + +- case LTU: +- case GEU: return CC_FLAG_C; ++void ++rx_split_cbranch (enum machine_mode cc_mode, enum rtx_code cmp1, ++ rtx c1, rtx c2, rtx label) ++{ ++ rtx flags, x; + +- case EQ: +- case NE: return CC_FLAG_Z; ++ flags = gen_rtx_REG (cc_mode, CC_REG); ++ x = gen_rtx_COMPARE (cc_mode, c1, c2); ++ x = gen_rtx_SET (VOIDmode, flags, x); ++ emit_insn (x); + +- default: gcc_unreachable (); +- } ++ x = gen_rtx_fmt_ee (cmp1, VOIDmode, flags, const0_rtx); ++ x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label, pc_rtx); ++ x = gen_rtx_SET (VOIDmode, pc_rtx, x); ++ emit_jump_insn (x); + } + +-static unsigned int +-flags_from_mode (enum machine_mode mode) +-{ +- switch (mode) +- { +- case CCmode: return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O | CC_FLAG_C; +- case CC_ZSmode: return CC_FLAG_S | CC_FLAG_Z; +- case CC_ZSOmode: return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O; +- case CC_ZSCmode: return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_C; +- default: gcc_unreachable (); +- } +-} +- +-/* Returns true if a compare insn is redundant because it +- would only set flags that are already set correctly. */ ++/* A helper function for matching parallels that set the flags. */ + + bool +-rx_compare_redundant (rtx cmp) ++rx_match_ccmode (rtx insn, enum machine_mode cc_mode) + { +- unsigned int flags_needed; +- unsigned int flags_set; +- rtx next; +- rtx prev; +- rtx source; +- rtx dest; +- static rtx cc_reg = NULL_RTX; +- +- if (cc_reg == NULL_RTX) +- cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); +- +- /* We can only eliminate compares against 0. */ +- if (GET_CODE (XEXP (SET_SRC (PATTERN (cmp)), 1)) != CONST_INT +- || INTVAL (XEXP (SET_SRC (PATTERN (cmp)), 1)) != 0) +- return false; +- +- /* Locate the branch insn that follows the +- compare and which tests the bits in the PSW. */ +- next = cmp; +- do +- { +- /* If we have found an insn that sets or clobbers the CC +- register and it was not the IF_THEN_ELSE insn that we +- are looking for, then the comparison is redundant. */ +- if (next != cmp && reg_mentioned_p (cc_reg, PATTERN (next))) +- return true; ++ rtx op1, flags; ++ enum machine_mode flags_mode; + +- next = next_nonnote_insn (next); ++ gcc_assert (XVECLEN (PATTERN (insn), 0) == 2); + +- /* If we run out of insns without finding the +- user then the comparison is unnecessary. */ +- if (next == NULL_RTX) +- return true; ++ op1 = XVECEXP (PATTERN (insn), 0, 1); ++ gcc_assert (GET_CODE (SET_SRC (op1)) == COMPARE); + +- /* If we have found another comparison +- insn then the first one is redundant. */ +- if (INSN_P (next) +- && GET_CODE (PATTERN (next)) == SET +- && REG_P (SET_DEST (PATTERN (next))) +- && REGNO (SET_DEST (PATTERN (next))) == CC_REGNUM) +- return true; ++ flags = SET_DEST (op1); ++ flags_mode = GET_MODE (flags); + +- /* If we have found another arithmetic/logic insn that +- sets the PSW flags then the comparison is redundant. */ +- if (INSN_P (next) +- && GET_CODE (PATTERN (next)) == PARALLEL +- && GET_CODE (XVECEXP (PATTERN (next), 0, 1)) == SET +- && REG_P (SET_DEST (XVECEXP (PATTERN (next), 0, 1))) +- && REGNO (SET_DEST (XVECEXP (PATTERN (next), 0, 1))) == CC_REGNUM) +- return true; +- +- /* If we have found an unconditional branch then the +- PSW flags might be carried along with the jump, so +- the comparison is necessary. */ +- if (INSN_P (next) && JUMP_P (next)) +- { +- if (GET_CODE (PATTERN (next)) != SET) +- /* If the jump does not involve setting the PC +- then it is a return of some kind, and we know +- that the comparison is not used. */ +- return true; +- +- if (GET_CODE (SET_SRC (PATTERN (next))) != IF_THEN_ELSE) +- return false; +- } +- } +- while (! INSN_P (next) +- || DEBUG_INSN_P (next) +- || GET_CODE (PATTERN (next)) != SET +- || GET_CODE (SET_SRC (PATTERN (next))) != IF_THEN_ELSE); +- +- flags_needed = flags_needed_for_conditional (XEXP (SET_SRC (PATTERN (next)), 0)); +- +- /* Now look to see if there was a previous +- instruction which set the PSW bits. */ +- source = XEXP (SET_SRC (PATTERN (cmp)), 0); +- prev = cmp; +- do +- { +- /* If this insn uses/sets/clobbers the CC register +- and it is not the insn that we are looking for +- below, then we must need the comparison. */ +- if (prev != cmp && reg_mentioned_p (cc_reg, PATTERN (prev))) +- return false; +- +- prev = prev_nonnote_insn (prev); +- +- if (prev == NULL_RTX) +- return false; +- +- /* If we encounter an insn which changes the contents of +- the register which is the source of the comparison then +- we will definitely need the comparison. */ +- if (INSN_P (prev) +- && GET_CODE (PATTERN (prev)) == SET +- && rtx_equal_p (SET_DEST (PATTERN (prev)), source)) +- { +- /* Unless this instruction is a simple register move +- instruction. In which case we can continue our +- scan backwards, but now using the *source* of this +- set instruction. */ +- if (REG_P (SET_SRC (PATTERN (prev)))) +- source = SET_SRC (PATTERN (prev)); +- /* We can also survive a sign-extension if the test is +- for EQ/NE. Note the same does not apply to zero- +- extension as this can turn a non-zero bit-pattern +- into zero. */ +- else if (flags_needed == CC_FLAG_Z +- && GET_CODE (SET_SRC (PATTERN (prev))) == SIGN_EXTEND) +- source = XEXP (SET_SRC (PATTERN (prev)), 0); +- else +- return false; +- } ++ if (GET_MODE (SET_SRC (op1)) != flags_mode) ++ return false; ++ if (GET_MODE_CLASS (flags_mode) != MODE_CC) ++ return false; + +- /* A label means a possible branch into the +- code here, so we have to stop scanning. */ +- if (LABEL_P (prev)) +- return false; +- } +- while (! INSN_P (prev) +- || DEBUG_INSN_P (prev) +- || GET_CODE (PATTERN (prev)) != PARALLEL +- || GET_CODE (XVECEXP (PATTERN (prev), 0, 1)) != SET +- || ! REG_P (SET_DEST (XVECEXP (PATTERN (prev), 0, 1))) +- || REGNO (SET_DEST (XVECEXP (PATTERN (prev), 0, 1))) != CC_REGNUM); +- +- flags_set = flags_from_mode (GET_MODE (SET_DEST (XVECEXP (PATTERN (prev), 0, 1)))); +- +- dest = SET_DEST (XVECEXP (PATTERN (prev), 0, 0)); +- /* The destination of the previous arithmetic/logic instruction +- must match the source in the comparison operation. For registers +- we ignore the mode as there may have been a sign-extension involved. */ +- if (! rtx_equal_p (source, dest)) +- { +- if (REG_P (source) && REG_P (dest) && REGNO (dest) == REGNO (source)) +- ; +- else +- return false; +- } ++ /* Ensure that the mode of FLAGS is compatible with CC_MODE. */ ++ if (flags_from_mode (flags_mode) & ~flags_from_mode (cc_mode)) ++ return false; + +- return ((flags_set & flags_needed) == flags_needed); ++ return true; + } + + #undef TARGET_FUNCTION_VALUE +@@ -2759,6 +2754,12 @@ + #undef TARGET_CC_MODES_COMPATIBLE + #define TARGET_CC_MODES_COMPATIBLE rx_cc_modes_compatible + ++#undef TARGET_PROMOTE_FUNCTION_MODE ++#define TARGET_PROMOTE_FUNCTION_MODE rx_promote_function_mode ++ ++#undef TARGET_OPTION_OVERRIDE ++#define TARGET_OPTION_OVERRIDE rx_option_override ++ + struct gcc_target targetm = TARGET_INITIALIZER; + + /* #include "gt-rx.h" */ +--- a/src/gcc/config/rx/rx.h ++++ b/src/gcc/config/rx/rx.h +@@ -1,5 +1,5 @@ + /* GCC backend definitions for the Renesas RX processor. +- Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + Contributed by Red Hat. + + This file is part of GCC. +@@ -25,7 +25,10 @@ + builtin_define ("__RX__"); \ + builtin_assert ("cpu=RX"); \ + if (rx_cpu_type == RX610) \ +- builtin_assert ("machine=RX610"); \ ++ { \ ++ builtin_define ("__RX610__"); \ ++ builtin_assert ("machine=RX610"); \ ++ } \ + else \ + builtin_assert ("machine=RX600"); \ + \ +@@ -144,6 +147,10 @@ + #define SIZE_TYPE "long unsigned int" + #undef PTRDIFF_TYPE + #define PTRDIFF_TYPE "long int" ++#undef WCHAR_TYPE ++#define WCHAR_TYPE "long int" ++#undef WCHAR_TYPE_SIZE ++#define WCHAR_TYPE_SIZE BITS_PER_WORD + #define POINTERS_EXTEND_UNSIGNED 1 + #define FUNCTION_MODE QImode + #define CASE_VECTOR_MODE Pmode +@@ -260,6 +267,7 @@ + + #define LIBCALL_VALUE(MODE) \ + gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT \ ++ || COMPLEX_MODE_P (MODE) \ + || GET_MODE_SIZE (MODE) >= 4) \ + ? (MODE) \ + : SImode), \ +@@ -354,7 +362,7 @@ + { \ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "cc" \ +- }; ++ } + + #define ADDITIONAL_REGISTER_NAMES \ + { \ +@@ -616,8 +624,6 @@ + #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ + rx_print_operand_address (FILE, ADDR) + +-extern int rx_float_compare_mode; +- + /* This is a version of REG_P that also returns TRUE for SUBREGs. */ + #define RX_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG) + +@@ -655,12 +661,5 @@ + #define REGISTER_MOVE_COST(MODE, FROM, TO) 2 + #define MEMORY_MOVE_COST(MODE, REGCLASS, IN) (2 + memory_move_secondary_cost (MODE, REGCLASS, IN)) + +-#define SELECT_CC_MODE(OP,X,Y) \ +- (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CC_ZSmode : \ +- (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS ? CC_ZSCmode : \ +- (GET_CODE (X) == ABS ? CC_ZSOmode : \ +- (GET_CODE (X) == AND || GET_CODE (X) == NOT || GET_CODE (X) == IOR \ +- || GET_CODE (X) == XOR || GET_CODE (X) == ROTATE \ +- || GET_CODE (X) == ROTATERT || GET_CODE (X) == ASHIFTRT \ +- || GET_CODE (X) == LSHIFTRT || GET_CODE (X) == ASHIFT ? CC_ZSmode : \ +- CCmode)))) ++#define SELECT_CC_MODE(OP,X,Y) rx_select_cc_mode ((OP), (X), (Y)) ++ +--- a/src/gcc/config/rx/rx.md ++++ b/src/gcc/config/rx/rx.md +@@ -1,5 +1,5 @@ + ;; Machine Description for Renesas RX processors +-;; Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. ++;; Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + ;; Contributed by Red Hat. + + ;; This file is part of GCC. +@@ -19,14 +19,6 @@ + ;; . + + +-;; This code iterator allows all branch instructions to +-;; be generated from a single define_expand template. +-(define_code_iterator most_cond [eq ne gt ge lt le gtu geu ltu leu +- unordered ordered ]) +- +-;; Likewise, but only the ones that use Z or S. +-(define_code_iterator zs_cond [eq ne gtu geu ltu leu ]) +- + ;; This code iterator is used for sign- and zero- extensions. + (define_mode_iterator small_int_modes [(HI "") (QI "")]) + +@@ -38,15 +30,6 @@ + [(SF "ALLOW_RX_FPU_INSNS") (SI "") (HI "") (QI "")]) + + +-;; Used to map RX condition names to GCC +-;; condition names for builtin instructions. +-(define_code_iterator gcc_conds [eq ne gt ge lt le gtu geu ltu leu +- unge unlt uneq ltgt]) +-(define_code_attr rx_conds [(eq "eq") (ne "ne") (gt "gt") (ge "ge") (lt "lt") +- (le "le") (gtu "gtu") (geu "geu") (ltu "ltu") +- (leu "leu") (unge "pz") (unlt "n") (uneq "o") +- (ltgt "no")]) +- + (define_constants + [ + (SP_REG 0) +@@ -58,6 +41,7 @@ + (UNSPEC_RTE 10) + (UNSPEC_RTFI 11) + (UNSPEC_NAKED 12) ++ (UNSPEC_CONST 13) + + (UNSPEC_MOVSTR 20) + (UNSPEC_MOVMEM 21) +@@ -150,6 +134,8 @@ + (define_insn_reservation "throughput_18_latency_18" 1 + (eq_attr "timings" "1818") "throughput*18") + ++;; ---------------------------------------------------------------------------- ++ + ;; Comparisons + + ;; Note - we do not specify the two instructions necessary to perform +@@ -160,254 +146,164 @@ + + (define_expand "cbranchsi4" + [(set (pc) +- (if_then_else (match_operator 0 "comparison_operator" +- [(match_operand:SI 1 "register_operand") +- (match_operand:SI 2 "rx_source_operand")]) +- (label_ref (match_operand 3 "")) +- (pc))) +- ] +- "" ++ (if_then_else ++ (match_operator 0 "comparison_operator" ++ [(match_operand:SI 1 "register_operand") ++ (match_operand:SI 2 "rx_source_operand")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] + "" + ) + +-(define_insn_and_split "*cbranchsi4_" ++(define_insn_and_split "*cbranchsi4" + [(set (pc) +- (if_then_else (most_cond (match_operand:SI 0 "register_operand" "r") +- (match_operand:SI 1 "rx_source_operand" "riQ")) +- (label_ref (match_operand 2 "" "")) +- (pc))) +- ] ++ (if_then_else ++ (match_operator 3 "comparison_operator" ++ [(match_operand:SI 0 "register_operand" "r") ++ (match_operand:SI 1 "rx_source_operand" "riQ")]) ++ (match_operand 2 "label_ref_operand" "") ++ (pc)))] + "" + "#" + "reload_completed" + [(const_int 0)] +- " +- /* We contstruct the split by hand as otherwise the JUMP_LABEL +- attribute is not set correctly on the jump insn. */ +- emit_insn (gen_cmpsi (operands[0], operands[1])); +- +- emit_jump_insn (gen_conditional_branch (operands[2], +- gen_rtx_fmt_ee (, CCmode, +- gen_rtx_REG (CCmode, CC_REG), const0_rtx))); +- " +-) ++{ ++ rx_split_cbranch (CCmode, GET_CODE (operands[3]), ++ operands[0], operands[1], operands[2]); ++ DONE; ++}) + +-;; ----------------------------------------------------------------------------- +-;; These two are the canonical TST/branch insns. However, GCC +-;; generates a wide variety of tst-like patterns, we catch those +-;; below. +-(define_insn_and_split "*tstbranchsi4_" +- [(set (pc) +- (if_then_else (zs_cond (and:SI (match_operand:SI 0 "register_operand" "r") +- (match_operand:SI 1 "rx_source_operand" "riQ")) +- (const_int 0)) +- (label_ref (match_operand 2 "" "")) +- (pc))) +- ] +- "" +- "#" ++(define_insn "*cmpsi" ++ [(set (reg:CC CC_REG) ++ (compare:CC (match_operand:SI 0 "register_operand" "r,r,r,r,r,r,r") ++ (match_operand:SI 1 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")))] + "reload_completed" +- [(const_int 0)] +- " +- emit_insn (gen_tstsi (operands[0], operands[1])); +- +- emit_jump_insn (gen_conditional_branch (operands[2], +- gen_rtx_fmt_ee (, CCmode, +- gen_rtx_REG (CCmode, CC_REG), const0_rtx))); +- " ++ "cmp\t%Q1, %0" ++ [(set_attr "timings" "11,11,11,11,11,11,33") ++ (set_attr "length" "2,2,3,4,5,6,5")] + ) + +-;; Inverse of above +-(define_insn_and_split "*tstbranchsi4_" ++;; Canonical method for representing TST. ++(define_insn_and_split "*cbranchsi4_tst" + [(set (pc) +- (if_then_else (zs_cond (and:SI (match_operand:SI 0 "register_operand" "r") +- (match_operand:SI 1 "rx_source_operand" "riQ")) +- (const_int 0)) +- (pc) +- (label_ref (match_operand 2 "" "")))) +- ] ++ (if_then_else ++ (match_operator 3 "rx_zs_comparison_operator" ++ [(and:SI (match_operand:SI 0 "register_operand" "r") ++ (match_operand:SI 1 "rx_source_operand" "riQ")) ++ (const_int 0)]) ++ (match_operand 2 "label_ref_operand" "") ++ (pc)))] + "" + "#" + "reload_completed" + [(const_int 0)] +- " +- emit_insn (gen_tstsi (operands[0], operands[1])); +- +- emit_jump_insn (gen_conditional_branch (operands[2], +- gen_rtx_fmt_ee (reverse_condition (), CCmode, +- gen_rtx_REG (CCmode, CC_REG), const0_rtx))); +- " +-) ++{ ++ rx_split_cbranch (CC_ZSmode, GET_CODE (operands[3]), ++ XEXP (operands[3], 0), XEXP (operands[3], 1), ++ operands[2]); ++ DONE; ++}) + + ;; Various other ways that GCC codes "var & const" +- +-(define_insn_and_split "*tstbranchsi4m_eq" ++(define_insn_and_split "*cbranchsi4_tst_ext" + [(set (pc) +- (if_then_else (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r") +- (match_operand 1 "rx_constshift_operand" "i") +- (match_operand 2 "rx_constshift_operand" "i")) +- (const_int 0)) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- ] ++ (if_then_else ++ (match_operator 4 "rx_z_comparison_operator" ++ [(zero_extract:SI ++ (match_operand:SI 0 "register_operand" "r") ++ (match_operand:SI 1 "rx_constshift_operand" "") ++ (match_operand:SI 2 "rx_constshift_operand" "")) ++ (const_int 0)]) ++ (match_operand 3 "label_ref_operand" "") ++ (pc)))] + "" + "#" +- "" +- [(set (pc) +- (if_then_else (eq (and:SI (match_dup 0) +- (match_dup 4)) +- (const_int 0)) +- (label_ref (match_dup 3)) +- (pc))) +- ] +- "operands[4] = GEN_INT (((1 << INTVAL (operands[1]))-1) << INTVAL (operands[2]));" +-) ++ "reload_completed" ++ [(const_int 0)] ++{ ++ HOST_WIDE_INT mask; ++ rtx x; ++ ++ mask = 1; ++ mask <<= INTVAL (operands[1]); ++ mask -= 1; ++ mask <<= INTVAL (operands[2]); ++ x = gen_rtx_AND (SImode, operands[0], gen_int_mode (mask, SImode)); ++ ++ rx_split_cbranch (CC_ZSmode, GET_CODE (operands[4]), ++ x, const0_rtx, operands[3]); ++ DONE; ++}) + +-(define_insn_and_split "*tstbranchsi4m_ne" +- [(set (pc) +- (if_then_else (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r") +- (match_operand 1 "rx_constshift_operand" "i") +- (match_operand 2 "rx_constshift_operand" "i")) +- (const_int 0)) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- ] +- "" +- "#" +- "" +- [(set (pc) +- (if_then_else (ne (and:SI (match_dup 0) +- (match_dup 4)) +- (const_int 0)) +- (label_ref (match_dup 3)) +- (pc))) +- ] +- "operands[4] = GEN_INT (((1 << INTVAL (operands[1]))-1) << INTVAL (operands[2]));" ++(define_insn "*tstsi" ++ [(set (reg:CC_ZS CC_REG) ++ (compare:CC_ZS ++ (and:SI (match_operand:SI 0 "register_operand" "r,r,r") ++ (match_operand:SI 1 "rx_source_operand" "r,i,Q")) ++ (const_int 0)))] ++ "reload_completed" ++ "tst\t%Q1, %0" ++ [(set_attr "timings" "11,11,33") ++ (set_attr "length" "3,7,6")] + ) + +-;; ----------------------------------------------------------------------------- +- + (define_expand "cbranchsf4" + [(set (pc) +- (if_then_else (match_operator 0 "comparison_operator" +- [(match_operand:SF 1 "register_operand") +- (match_operand:SF 2 "rx_source_operand")]) +- (label_ref (match_operand 3 "")) +- (pc))) +- ] ++ (if_then_else ++ (match_operator 0 "rx_fp_comparison_operator" ++ [(match_operand:SF 1 "register_operand") ++ (match_operand:SF 2 "rx_source_operand")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] + "ALLOW_RX_FPU_INSNS" +- "" + ) + +-(define_insn_and_split "*cbranchsf4_" ++(define_insn_and_split "*cbranchsf4" + [(set (pc) +- (if_then_else (most_cond (match_operand:SF 0 "register_operand" "r") +- (match_operand:SF 1 "rx_source_operand" "rFiQ")) +- (label_ref (match_operand 2 "" "")) +- (pc))) +- ] ++ (if_then_else ++ (match_operator 3 "rx_fp_comparison_operator" ++ [(match_operand:SF 0 "register_operand" "r") ++ (match_operand:SF 1 "rx_source_operand" "rFQ")]) ++ (match_operand 2 "label_ref_operand" "") ++ (pc)))] + "ALLOW_RX_FPU_INSNS" + "#" + "&& reload_completed" + [(const_int 0)] +- " +- /* We contstruct the split by hand as otherwise the JUMP_LABEL +- attribute is not set correctly on the jump insn. */ +- emit_insn (gen_cmpsf (operands[0], operands[1])); +- +- emit_jump_insn (gen_conditional_branch (operands[2], +- gen_rtx_fmt_ee (, CCmode, +- gen_rtx_REG (CCmode, CC_REG), const0_rtx))); +- " +-) +- +-(define_insn "tstsi" +- [(set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (and:SI (match_operand:SI 0 "register_operand" "r,r,r") +- (match_operand:SI 1 "rx_source_operand" "r,i,Q")) +- (const_int 0)))] +- "" +- { +- rx_float_compare_mode = false; +- return "tst\t%Q1, %0"; +- } +- [(set_attr "timings" "11,11,33") +- (set_attr "length" "3,7,6")] +-) +- +-(define_insn "cmpsi" +- [(set (reg:CC CC_REG) +- (compare:CC (match_operand:SI 0 "register_operand" "r,r,r,r,r,r,r") +- (match_operand:SI 1 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")))] +- "" +- { +- rx_float_compare_mode = false; +- if (rx_compare_redundant (insn)) +- return "; Compare Eliminated: cmp %Q1, %0"; +- return "cmp\t%Q1, %0"; +- } +- [(set_attr "timings" "11,11,11,11,11,11,33") +- (set_attr "length" "2,2,3,4,5,6,5")] +-) +- +-;; This pattern is disabled when -fnon-call-exceptions is active because +-;; it could generate a floating point exception, which would introduce an +-;; edge into the flow graph between this insn and the conditional branch +-;; insn to follow, thus breaking the cc0 relationship. Run the g++ test +-;; g++.dg/eh/080514-1.C to see this happen. +-(define_insn "cmpsf" +- [(set (reg:CC_ZSO CC_REG) +- (compare:CC_ZSO (match_operand:SF 0 "register_operand" "r,r,r") +- (match_operand:SF 1 "rx_source_operand" "r,iF,Q")))] +- "ALLOW_RX_FPU_INSNS" +- { +- rx_float_compare_mode = true; +- return "fcmp\t%1, %0"; +- } ++{ ++ rx_split_cbranch (CC_Fmode, GET_CODE (operands[3]), ++ operands[0], operands[1], operands[2]); ++ DONE; ++}) ++ ++(define_insn "*cmpsf" ++ [(set (reg:CC_F CC_REG) ++ (compare:CC_F ++ (match_operand:SF 0 "register_operand" "r,r,r") ++ (match_operand:SF 1 "rx_source_operand" "r,F,Q")))] ++ "ALLOW_RX_FPU_INSNS && reload_completed" ++ "fcmp\t%1, %0" + [(set_attr "timings" "11,11,33") + (set_attr "length" "3,7,5")] + ) + + ;; Flow Control Instructions: + +-(define_expand "b" +- [(set (pc) +- (if_then_else (most_cond (reg:CC CC_REG) (const_int 0)) +- (label_ref (match_operand 0)) +- (pc)))] +- "" +- "" +-) +- +-(define_insn "conditional_branch" ++(define_insn "*conditional_branch" + [(set (pc) +- (if_then_else (match_operator 1 "comparison_operator" +- [(reg:CC CC_REG) (const_int 0)]) +- (label_ref (match_operand 0 "" "")) +- (pc)))] +- "" +- { +- return rx_gen_cond_branch_template (operands[1], false); +- } ++ (if_then_else ++ (match_operator 1 "comparison_operator" ++ [(reg CC_REG) (const_int 0)]) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "reload_completed" ++ "b%B1\t%0" + [(set_attr "length" "8") ;; This length is wrong, but it is + ;; too hard to compute statically. + (set_attr "timings" "33")] ;; The timing assumes that the branch is taken. + ) + +-(define_insn "*reveresed_conditional_branch" +- [(set (pc) +- (if_then_else (match_operator 1 "comparison_operator" +- [(reg:CC CC_REG) (const_int 0)]) +- (pc) +- (label_ref (match_operand 0 "" ""))))] +- "" +- { +- return rx_gen_cond_branch_template (operands[1], true); +- } +- [(set_attr "length" "8") ;; This length is wrong, but it is +- ;; too hard to compute statically. +- (set_attr "timings" "33")] ;; The timing assumes that the branch is taken. +-) ++;; ---------------------------------------------------------------------------- + + (define_insn "jump" + [(set (pc) +@@ -448,10 +344,12 @@ + (set_attr "timings" "55")] + ) + ++;; Unspec used so that the constant will not be invalid ++;; if -mmax-constant-size has been specified. + (define_insn "deallocate_and_return" + [(set (reg:SI SP_REG) + (plus:SI (reg:SI SP_REG) +- (match_operand:SI 0 "immediate_operand" "i"))) ++ (const:SI (unspec:SI [(match_operand 0 "const_int_operand" "n")] UNSPEC_CONST)))) + (return)] + "" + "rtsd\t%0" +@@ -461,9 +359,10 @@ + + (define_insn "pop_and_return" + [(match_parallel 1 "rx_rtsd_vector" +- [(set:SI (reg:SI SP_REG) +- (plus:SI (reg:SI SP_REG) +- (match_operand:SI 0 "const_int_operand" "n")))])] ++ [(set (reg:SI SP_REG) ++ (plus:SI (reg:SI SP_REG) ++ (match_operand:SI 0 "const_int_operand" "n")))]) ++ (return)] + "reload_completed" + { + rx_emit_stack_popm (operands, false); +@@ -513,14 +412,14 @@ + + if (! rx_call_operand (dest, Pmode)) + dest = force_reg (Pmode, dest); +- emit_call_insn (gen_call_internal (dest, operands[1])); ++ emit_call_insn (gen_call_internal (dest)); + DONE; + } + ) + + (define_insn "call_internal" + [(call (mem:QI (match_operand:SI 0 "rx_call_operand" "r,Symbol")) +- (match_operand:SI 1 "general_operand" "g,g")) ++ (const_int 0)) + (clobber (reg:CC CC_REG))] + "" + "@ +@@ -540,7 +439,7 @@ + + if (! rx_call_operand (dest, Pmode)) + dest = force_reg (Pmode, dest); +- emit_call_insn (gen_call_value_internal (operands[0], dest, operands[2])); ++ emit_call_insn (gen_call_value_internal (operands[0], dest)); + DONE; + } + ) +@@ -548,7 +447,7 @@ + (define_insn "call_value_internal" + [(set (match_operand 0 "register_operand" "=r,r") + (call (mem:QI (match_operand:SI 1 "rx_call_operand" "r,Symbol")) +- (match_operand:SI 2 "general_operand" "g,g"))) ++ (const_int 0))) + (clobber (reg:CC CC_REG))] + "" + "@ +@@ -572,12 +471,14 @@ + { + if (MEM_P (operands[0])) + operands[0] = XEXP (operands[0], 0); ++ emit_call_insn (gen_sibcall_internal (operands[0])); ++ DONE; + } + ) + + (define_insn "sibcall_internal" + [(call (mem:QI (match_operand:SI 0 "rx_symbolic_call_operand" "Symbol")) +- (match_operand:SI 1 "general_operand" "g")) ++ (const_int 0)) + (return)] + "" + "bra\t%A0" +@@ -595,13 +496,15 @@ + { + if (MEM_P (operands[1])) + operands[1] = XEXP (operands[1], 0); ++ emit_call_insn (gen_sibcall_value_internal (operands[0], operands[1])); ++ DONE; + } + ) + + (define_insn "sibcall_value_internal" + [(set (match_operand 0 "register_operand" "=r") + (call (mem:QI (match_operand:SI 1 "rx_symbolic_call_operand" "Symbol")) +- (match_operand:SI 2 "general_operand" "g"))) ++ (const_int 0))) + (return)] + "" + "bra\t%A1" +@@ -653,6 +556,9 @@ + { + if (MEM_P (operand0) && MEM_P (operand1)) + operands[1] = copy_to_mode_reg (mode, operand1); ++ if (CONST_INT_P (operand1) ++ && ! rx_is_legitimate_constant (operand1)) ++ FAIL; + } + ) + +@@ -688,11 +594,11 @@ + ) + + (define_insn "stack_push" +- [(set:SI (reg:SI SP_REG) +- (minus:SI (reg:SI SP_REG) +- (const_int 4))) +- (set:SI (mem:SI (reg:SI SP_REG)) +- (match_operand:SI 0 "register_operand" "r"))] ++ [(set (reg:SI SP_REG) ++ (minus:SI (reg:SI SP_REG) ++ (const_int 4))) ++ (set (mem:SI (reg:SI SP_REG)) ++ (match_operand:SI 0 "register_operand" "r"))] + "" + "push.l\t%0" + [(set_attr "length" "2")] +@@ -700,9 +606,9 @@ + + (define_insn "stack_pushm" + [(match_parallel 1 "rx_store_multiple_vector" +- [(set:SI (reg:SI SP_REG) +- (minus:SI (reg:SI SP_REG) +- (match_operand:SI 0 "const_int_operand" "n")))])] ++ [(set (reg:SI SP_REG) ++ (minus:SI (reg:SI SP_REG) ++ (match_operand:SI 0 "const_int_operand" "n")))])] + "reload_completed" + { + rx_emit_stack_pushm (operands); +@@ -713,11 +619,11 @@ + ) + + (define_insn "stack_pop" +- [(set:SI (match_operand:SI 0 "register_operand" "=r") +- (mem:SI (reg:SI SP_REG))) +- (set:SI (reg:SI SP_REG) +- (plus:SI (reg:SI SP_REG) +- (const_int 4)))] ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (mem:SI (reg:SI SP_REG))) ++ (set (reg:SI SP_REG) ++ (plus:SI (reg:SI SP_REG) ++ (const_int 4)))] + "" + "pop\t%0" + [(set_attr "length" "2") +@@ -726,9 +632,9 @@ + + (define_insn "stack_popm" + [(match_parallel 1 "rx_load_multiple_vector" +- [(set:SI (reg:SI SP_REG) +- (plus:SI (reg:SI SP_REG) +- (match_operand:SI 0 "const_int_operand" "n")))])] ++ [(set (reg:SI SP_REG) ++ (plus:SI (reg:SI SP_REG) ++ (match_operand:SI 0 "const_int_operand" "n")))])] + "reload_completed" + { + rx_emit_stack_popm (operands, true); +@@ -738,68 +644,139 @@ + (set_attr "timings" "45")] ;; The timing is a guesstimate average timing. + ) + +-;; FIXME: Add memory destination options ? +-(define_insn "cstoresi4" +- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r") ++(define_insn_and_split "cstoresi4" ++ [(set (match_operand:SI 0 "register_operand" "=r") + (match_operator:SI 1 "comparison_operator" +- [(match_operand:SI 2 "register_operand" "r,r,r,r,r,r,r") +- (match_operand:SI 3 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")])) +- (clobber (reg:CC CC_REG))] ;; Because the cc flags are set based on comparing ops 2 & 3 not the value in op 0. ++ [(match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "rx_source_operand" "riQ")])) ++ (clobber (reg:CC CC_REG))] + "" +- { +- rx_float_compare_mode = false; +- return "cmp\t%Q3, %Q2\n\tsc%B1.L\t%0"; +- } +- [(set_attr "timings" "22,22,22,22,22,22,44") +- (set_attr "length" "5,5,6,7,8,9,8")] ++ "#" ++ "reload_completed" ++ [(const_int 0)] ++{ ++ rtx flags, x; ++ ++ flags = gen_rtx_REG (CCmode, CC_REG); ++ x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]); ++ x = gen_rtx_SET (VOIDmode, flags, x); ++ emit_insn (x); ++ ++ x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx); ++ x = gen_rtx_SET (VOIDmode, operands[0], x); ++ emit_insn (x); ++ DONE; ++}) ++ ++(define_insn "*sccc" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (match_operator:SI 1 "comparison_operator" ++ [(reg CC_REG) (const_int 0)]))] ++ "reload_completed" ++ "sc%B1.L\t%0" ++ [(set_attr "length" "3")] + ) + ++(define_insn_and_split "cstoresf4" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (match_operator:SI 1 "rx_fp_comparison_operator" ++ [(match_operand:SF 2 "register_operand" "r") ++ (match_operand:SF 3 "rx_source_operand" "rFQ")]))] ++ "ALLOW_RX_FPU_INSNS" ++ "#" ++ "reload_completed" ++ [(const_int 0)] ++{ ++ rtx flags, x; ++ ++ flags = gen_rtx_REG (CC_Fmode, CC_REG); ++ x = gen_rtx_COMPARE (CC_Fmode, operands[2], operands[3]); ++ x = gen_rtx_SET (VOIDmode, flags, x); ++ emit_insn (x); ++ ++ x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx); ++ x = gen_rtx_SET (VOIDmode, operands[0], x); ++ emit_insn (x); ++ DONE; ++}) ++ + (define_expand "movsicc" + [(parallel + [(set (match_operand:SI 0 "register_operand") + (if_then_else:SI (match_operand:SI 1 "comparison_operator") + (match_operand:SI 2 "nonmemory_operand") +- (match_operand:SI 3 "immediate_operand"))) +- (clobber (reg:CC CC_REG))])] ;; See cstoresi4 ++ (match_operand:SI 3 "nonmemory_operand"))) ++ (clobber (reg:CC CC_REG))])] + "" +- { +- if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE) +- FAIL; +- if (! CONST_INT_P (operands[3])) +- FAIL; +- } +-) ++{ ++ /* ??? Support other conditions via cstore into a temporary? */ ++ if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE) ++ FAIL; ++ /* One operand must be a constant. */ ++ if (!CONSTANT_P (operands[2]) && !CONSTANT_P (operands[3])) ++ FAIL; ++}) + +-(define_insn "*movsieq" +- [(set (match_operand:SI 0 "register_operand" "=r,r,r") +- (if_then_else:SI (eq (match_operand:SI 3 "register_operand" "r,r,r") +- (match_operand:SI 4 "rx_source_operand" "riQ,riQ,riQ")) +- (match_operand:SI 1 "nonmemory_operand" "0,i,r") +- (match_operand:SI 2 "immediate_operand" "i,i,i"))) +- (clobber (reg:CC CC_REG))] ;; See cstoresi4 +- "" +- "@ +- cmp\t%Q4, %Q3\n\tstnz\t%2, %0 +- cmp\t%Q4, %Q3\n\tmov.l\t%2, %0\n\tstz\t%1, %0 +- cmp\t%Q4, %Q3\n\tmov.l\t%1, %0\n\tstnz\t%2, %0" +- [(set_attr "length" "13,19,15") +- (set_attr "timings" "22,33,33")] +-) +- +-(define_insn "*movsine" +- [(set (match_operand:SI 0 "register_operand" "=r,r,r") +- (if_then_else:SI (ne (match_operand:SI 3 "register_operand" "r,r,r") +- (match_operand:SI 4 "rx_source_operand" "riQ,riQ,riQ")) +- (match_operand:SI 1 "nonmemory_operand" "0,i,r") +- (match_operand:SI 2 "immediate_operand" "i,i,i"))) +- (clobber (reg:CC CC_REG))] ;; See cstoresi4 +- "" +- "@ +- cmp\t%Q4, %Q3\n\tstz\t%2, %0 +- cmp\t%Q4, %Q3\n\tmov.l\t%2, %0\n\tstnz\t%1, %0 +- cmp\t%Q4, %Q3\n\tmov.l\t%1, %0\n\tstz\t%2, %0" +- [(set_attr "length" "13,19,15") +- (set_attr "timings" "22,33,33")] ++(define_insn_and_split "*movsicc" ++ [(set (match_operand:SI 0 "register_operand" "=r,r") ++ (if_then_else:SI ++ (match_operator 5 "rx_z_comparison_operator" ++ [(match_operand:SI 3 "register_operand" "r,r") ++ (match_operand:SI 4 "rx_source_operand" "riQ,riQ")]) ++ (match_operand:SI 1 "nonmemory_operand" "i,ri") ++ (match_operand:SI 2 "nonmemory_operand" "ri,i"))) ++ (clobber (reg:CC CC_REG))] ++ "CONSTANT_P (operands[1]) || CONSTANT_P (operands[2])" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++{ ++ rtx x, flags, op0, op1, op2; ++ enum rtx_code cmp_code; ++ ++ flags = gen_rtx_REG (CCmode, CC_REG); ++ x = gen_rtx_COMPARE (CCmode, operands[3], operands[4]); ++ emit_insn (gen_rtx_SET (VOIDmode, flags, x)); ++ ++ cmp_code = GET_CODE (operands[5]); ++ op0 = operands[0]; ++ op1 = operands[1]; ++ op2 = operands[2]; ++ ++ /* If OP2 is the constant, reverse the sense of the move. */ ++ if (!CONSTANT_P (operands[1])) ++ { ++ x = op1, op1 = op2, op2 = x; ++ cmp_code = reverse_condition (cmp_code); ++ } ++ ++ /* If OP2 does not match the output, copy it into place. We have allowed ++ these alternatives so that the destination can legitimately be one of ++ the comparison operands without increasing register pressure. */ ++ if (!rtx_equal_p (op0, op2)) ++ emit_move_insn (op0, op2); ++ ++ x = gen_rtx_fmt_ee (cmp_code, VOIDmode, flags, const0_rtx); ++ x = gen_rtx_IF_THEN_ELSE (SImode, x, op1, op0); ++ emit_insn (gen_rtx_SET (VOIDmode, op0, x)); ++ DONE; ++}) ++ ++(define_insn "*stcc" ++ [(set (match_operand:SI 0 "register_operand" "+r,r,r,r") ++ (if_then_else:SI ++ (match_operator 2 "rx_z_comparison_operator" ++ [(reg CC_REG) (const_int 0)]) ++ (match_operand:SI 1 "immediate_operand" "Sint08,Sint16,Sint24,i") ++ (match_dup 0)))] ++ "reload_completed" ++{ ++ if (GET_CODE (operands[2]) == EQ) ++ return "stz\t%1, %0"; ++ else ++ return "stnz\t%1, %0"; ++} ++ [(set_attr "length" "4,5,6,7")] + ) + + ;; Arithmetic Instructions +@@ -807,9 +784,7 @@ + (define_insn "abssi2" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (abs:SI (match_operand:SI 1 "register_operand" "0,r"))) +- (set (reg:CC_ZSO CC_REG) +- (compare:CC_ZSO (abs:SI (match_dup 1)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "" + "@ + abs\t%0 +@@ -817,13 +792,24 @@ + [(set_attr "length" "2,3")] + ) + ++(define_insn "*abssi2_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r") ++ (abs:SI (match_operand:SI 1 "register_operand" "0,r"))) ++ (set (reg CC_REG) ++ (compare (abs:SI (match_dup 1)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSOmode)" ++ "@ ++ abs\t%0 ++ abs\t%1, %0" ++ [(set_attr "length" "2,3")] ++) ++ + (define_insn "addsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r") + (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0") + (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q"))) +- (set (reg:CC_ZSC CC_REG) ;; See subsi3 +- (compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "" + "@ + add\t%2, %0 +@@ -844,27 +830,170 @@ + (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")] + ) + +-(define_insn "adddi3" +- [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r") +- (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0,0") +- (match_operand:DI 2 "rx_source_operand" +- "r,Sint08,Sint16,Sint24,i,Q"))) +- (set (reg:CC_ZSC CC_REG) ;; See subsi3 +- (compare:CC_ZSC (plus:DI (match_dup 1) (match_dup 2)) +- (const_int 0)))] +- "" +- "add\t%L2, %L0\n\tadc\t%H2, %H0" +- [(set_attr "timings" "22,22,22,22,22,44") +- (set_attr "length" "5,7,9,11,13,11")] ++(define_insn "*addsi3_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r") ++ (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0") ++ (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q"))) ++ (set (reg CC_REG) ++ (compare (plus:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)" ++ "@ ++ add\t%2, %0 ++ add\t%2, %0 ++ sub\t%N2, %0 ++ add\t%2, %0 ++ add\t%2, %0 ++ add\t%2, %0 ++ add\t%2, %0 ++ add\t%1, %0 ++ add\t%2, %1, %0 ++ add\t%2, %1, %0 ++ add\t%2, %1, %0 ++ add\t%2, %1, %0 ++ add\t%2, %1, %0 ++ add\t%Q2, %0" ++ [(set_attr "timings" "11,11,11,11,11,11,11,11,11,11,11,11,11,33") ++ (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")] ++) ++ ++;; A helper to expand the above with the CC_MODE filled in. ++(define_expand "addsi3_flags" ++ [(parallel [(set (match_operand:SI 0 "register_operand") ++ (plus:SI (match_operand:SI 1 "register_operand") ++ (match_operand:SI 2 "rx_source_operand"))) ++ (set (reg:CC_ZSC CC_REG) ++ (compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))])] ++) ++ ++(define_insn "adc_internal" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") ++ (plus:SI ++ (plus:SI ++ (ltu:SI (reg:CC CC_REG) (const_int 0)) ++ (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")) ++ (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q"))) ++ (clobber (reg:CC CC_REG))] ++ "reload_completed" ++ "adc %2,%0" ++ [(set_attr "timings" "11,11,11,11,11,33") ++ (set_attr "length" "3,4,5,6,7,6")] ++) ++ ++(define_insn "*adc_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") ++ (plus:SI ++ (plus:SI ++ (ltu:SI (reg:CC CC_REG) (const_int 0)) ++ (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")) ++ (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q"))) ++ (set (reg CC_REG) ++ (compare ++ (plus:SI ++ (plus:SI ++ (ltu:SI (reg:CC CC_REG) (const_int 0)) ++ (match_dup 1)) ++ (match_dup 2)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)" ++ "adc %2,%0" ++ [(set_attr "timings" "11,11,11,11,11,33") ++ (set_attr "length" "3,4,5,6,7,6")] + ) + ++(define_expand "adddi3" ++ [(set (match_operand:DI 0 "register_operand") ++ (plus:DI (match_operand:DI 1 "register_operand") ++ (match_operand:DI 2 "rx_source_operand")))] ++ "" ++{ ++ rtx op0l, op0h, op1l, op1h, op2l, op2h; ++ ++ op0l = gen_lowpart (SImode, operands[0]); ++ op1l = gen_lowpart (SImode, operands[1]); ++ op2l = gen_lowpart (SImode, operands[2]); ++ op0h = gen_highpart (SImode, operands[0]); ++ op1h = gen_highpart (SImode, operands[1]); ++ op2h = gen_highpart_mode (SImode, DImode, operands[2]); ++ ++ emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h)); ++ DONE; ++}) ++ ++(define_insn_and_split "adddi3_internal" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "rx_source_operand" "riQ"))) ++ (set (match_operand:SI 1 "register_operand" "=r") ++ (plus:SI ++ (plus:SI ++ (ltu:SI (plus:SI (match_dup 2) (match_dup 3)) (match_dup 2)) ++ (match_operand:SI 4 "register_operand" "%1")) ++ (match_operand:SI 5 "rx_source_operand" "riQ"))) ++ (clobber (match_scratch:SI 6 "=&r")) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "#" ++ "reload_completed" ++ [(const_int 0)] ++{ ++ rtx op0l = operands[0]; ++ rtx op0h = operands[1]; ++ rtx op1l = operands[2]; ++ rtx op2l = operands[3]; ++ rtx op1h = operands[4]; ++ rtx op2h = operands[5]; ++ rtx scratch = operands[6]; ++ rtx x; ++ ++ if (reg_overlap_mentioned_p (op0l, op1h)) ++ { ++ emit_move_insn (scratch, op0l); ++ op1h = scratch; ++ if (reg_overlap_mentioned_p (op0l, op2h)) ++ op2h = scratch; ++ } ++ else if (reg_overlap_mentioned_p (op0l, op2h)) ++ { ++ emit_move_insn (scratch, op0l); ++ op2h = scratch; ++ } ++ ++ if (rtx_equal_p (op0l, op1l)) ++ ; ++ /* It is preferable that op0l == op1l... */ ++ else if (rtx_equal_p (op0l, op2l)) ++ x = op1l, op1l = op2l, op2l = x; ++ /* ... but it is only a requirement if op2l == MEM. */ ++ else if (MEM_P (op2l)) ++ { ++ /* Let's hope that we still have a scratch register free. */ ++ gcc_assert (op1h != scratch); ++ emit_move_insn (scratch, op2l); ++ op2l = scratch; ++ } ++ ++ emit_insn (gen_addsi3_flags (op0l, op1l, op2l)); ++ ++ if (rtx_equal_p (op0h, op1h)) ++ ; ++ else if (rtx_equal_p (op0h, op2h)) ++ x = op1h, op1h = op2h, op2h = x; ++ else ++ { ++ emit_move_insn (op0h, op1h); ++ op1h = op0h; ++ } ++ emit_insn (gen_adc_internal (op0h, op1h, op2h)); ++ DONE; ++}) ++ + (define_insn "andsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") + (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") + (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (and:SI (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "" + "@ + and\t%2, %0 +@@ -880,9 +1009,31 @@ + (set_attr "length" "2,2,3,4,5,6,2,5,5")] + ) + ++(define_insn "*andsi3_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") ++ (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") ++ (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) ++ (set (reg CC_REG) ++ (compare (and:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" ++ "@ ++ and\t%2, %0 ++ and\t%2, %0 ++ and\t%2, %0 ++ and\t%2, %0 ++ and\t%2, %0 ++ and\t%2, %0 ++ and\t%1, %0 ++ and\t%2, %1, %0 ++ and\t%Q2, %0" ++ [(set_attr "timings" "11,11,11,11,11,11,11,33,33") ++ (set_attr "length" "2,2,3,4,5,6,2,5,5")] ++) ++ + ;; Byte swap (single 32-bit value). + (define_insn "bswapsi2" +- [(set (match_operand:SI 0 "register_operand" "+r") ++ [(set (match_operand:SI 0 "register_operand" "=r") + (bswap:SI (match_operand:SI 1 "register_operand" "r")))] + "" + "revl\t%1, %0" +@@ -891,7 +1042,7 @@ + + ;; Byte swap (single 16-bit value). Note - we ignore the swapping of the high 16-bits. + (define_insn "bswaphi2" +- [(set (match_operand:HI 0 "register_operand" "+r") ++ [(set (match_operand:HI 0 "register_operand" "=r") + (bswap:HI (match_operand:HI 1 "register_operand" "r")))] + "" + "revw\t%1, %0" +@@ -999,12 +1150,23 @@ + (define_insn "negsi2" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (neg:SI (match_operand:SI 1 "register_operand" "0,r"))) +- (set (reg:CC CC_REG) +- (compare:CC (neg:SI (match_dup 1)) +- (const_int 0)))] +- ;; The NEG instruction does not comply with -fwrapv semantics. +- ;; See gcc.c-torture/execute/pr22493-1.c for an example of this. +- "! flag_wrapv" ++ (clobber (reg:CC CC_REG))] ++ "" ++ "@ ++ neg\t%0 ++ neg\t%1, %0" ++ [(set_attr "length" "2,3")] ++) ++ ++;; Note that the O and C flags are not set as per a normal compare, ++;; and thus are unusable in that context. ++(define_insn "*negsi2_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r") ++ (neg:SI (match_operand:SI 1 "register_operand" "0,r"))) ++ (set (reg CC_REG) ++ (compare (neg:SI (match_dup 1)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" + "@ + neg\t%0 + neg\t%1, %0" +@@ -1014,9 +1176,7 @@ + (define_insn "one_cmplsi2" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (not:SI (match_operand:SI 1 "register_operand" "0,r"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (not:SI (match_dup 1)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "" + "@ + not\t%0 +@@ -1024,13 +1184,24 @@ + [(set_attr "length" "2,3")] + ) + ++(define_insn "*one_cmplsi2_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r") ++ (not:SI (match_operand:SI 1 "register_operand" "0,r"))) ++ (set (reg CC_REG) ++ (compare (not:SI (match_dup 1)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" ++ "@ ++ not\t%0 ++ not\t%1, %0" ++ [(set_attr "length" "2,3")] ++) ++ + (define_insn "iorsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") + (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") + (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (ior:SI (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "" + "@ + or\t%2, %0 +@@ -1046,37 +1217,77 @@ + (set_attr "length" "2,2,3,4,5,6,2,3,5")] + ) + ++(define_insn "*iorsi3_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") ++ (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") ++ (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) ++ (set (reg CC_REG) ++ (compare (ior:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" ++ "@ ++ or\t%2, %0 ++ or\t%2, %0 ++ or\t%2, %0 ++ or\t%2, %0 ++ or\t%2, %0 ++ or\t%Q2, %0 ++ or\t%1, %0 ++ or\t%2, %1, %0 ++ or\t%Q2, %0" ++ [(set_attr "timings" "11,11,11,11,11,11,11,11,33") ++ (set_attr "length" "2,2,3,4,5,6,2,3,5")] ++) ++ + (define_insn "rotlsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (rotate:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "rx_shift_operand" "rn"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (rotate:SI (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "" + "rotl\t%2, %0" + [(set_attr "length" "3")] + ) + ++(define_insn "*rotlsi3_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (rotate:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "rx_shift_operand" "rn"))) ++ (set (reg CC_REG) ++ (compare (rotate:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" ++ "rotl\t%2, %0" ++ [(set_attr "length" "3")] ++) ++ + (define_insn "rotrsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (rotatert:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "rx_shift_operand" "rn"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (rotatert:SI (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "" + "rotr\t%2, %0" + [(set_attr "length" "3")] + ) + ++(define_insn "*rotrsi3_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (rotatert:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "rx_shift_operand" "rn"))) ++ (set (reg CC_REG) ++ (compare (rotatert:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" ++ "rotr\t%2, %0" ++ [(set_attr "length" "3")] ++) ++ + (define_insn "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,r") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r") + (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (ashiftrt:SI (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "" + "@ + shar\t%2, %0 +@@ -1085,13 +1296,26 @@ + [(set_attr "length" "3,2,3")] + ) + ++(define_insn "*ashrsi3_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r") ++ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r") ++ (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) ++ (set (reg CC_REG) ++ (compare (ashiftrt:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" ++ "@ ++ shar\t%2, %0 ++ shar\t%2, %0 ++ shar\t%2, %1, %0" ++ [(set_attr "length" "3,2,3")] ++) ++ + (define_insn "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,r") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r") + (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (lshiftrt:SI (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "" + "@ + shlr\t%2, %0 +@@ -1100,13 +1324,26 @@ + [(set_attr "length" "3,2,3")] + ) + ++(define_insn "*lshrsi3_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r") ++ (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r") ++ (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) ++ (set (reg CC_REG) ++ (compare (lshiftrt:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" ++ "@ ++ shlr\t%2, %0 ++ shlr\t%2, %0 ++ shlr\t%2, %1, %0" ++ [(set_attr "length" "3,2,3")] ++) ++ + (define_insn "ashlsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,r") + (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r") + (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (ashift:SI (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "" + "@ + shll\t%2, %0 +@@ -1115,16 +1352,57 @@ + [(set_attr "length" "3,2,3")] + ) + ++(define_insn "*ashlsi3_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r") ++ (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r") ++ (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) ++ (set (reg CC_REG) ++ (compare (ashift:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" ++ "@ ++ shll\t%2, %0 ++ shll\t%2, %0 ++ shll\t%2, %1, %0" ++ [(set_attr "length" "3,2,3")] ++) ++ ++;; Saturate to 32-bits ++(define_insn_and_split "ssaddsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ss_plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "rx_source_operand" "riQ"))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "#" ++ "reload_completed" ++ [(parallel [(set (match_dup 0) ++ (plus:SI (match_dup 1) (match_dup 2))) ++ (set (reg:CC_ZSC CC_REG) ++ (compare:CC_ZSC ++ (plus:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))]) ++ (set (match_dup 0) ++ (unspec:SI [(match_dup 0) (reg:CC CC_REG)] ++ UNSPEC_BUILTIN_SAT))] ++ "" ++) ++ ++(define_insn "*sat" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "0") ++ (reg:CC CC_REG)] ++ UNSPEC_BUILTIN_SAT))] ++ "reload_completed" ++ "sat\t%0" ++ [(set_attr "length" "2")] ++) ++ + (define_insn "subsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") + (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0") + (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q"))) +- (set (reg:CC_ZSC CC_REG) +- ;; Note - we do not acknowledge that the SUB instruction sets the Overflow +- ;; flag because its interpretation is different from comparing the result +- ;; against zero. Compile and run gcc.c-torture/execute/cmpsi-1.c to see this. +- (compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "" + "@ + sub\t%2, %0 +@@ -1136,32 +1414,134 @@ + (set_attr "length" "2,2,6,3,5")] + ) + +-(define_insn "subdi3" +- [(set (match_operand:DI 0 "register_operand" "=r,r") +- (minus:DI (match_operand:DI 1 "register_operand" "0,0") +- (match_operand:DI 2 "rx_source_operand" "r,Q"))) +- (set (reg:CC_ZSC CC_REG) ;; See subsi3 +- (compare:CC_ZSC (minus:DI (match_dup 1) (match_dup 2)) +- (const_int 0)))] +- "" +- "sub\t%L2, %L0\n\tsbb\t%H2, %H0" +- [(set_attr "timings" "22,44") +- (set_attr "length" "5,11")] ++;; Note that the O flag is set as if (compare op1 op2) not for ++;; what is described here, (compare op0 0). ++(define_insn "*subsi3_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") ++ (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0") ++ (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q"))) ++ (set (reg CC_REG) ++ (compare (minus:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)" ++ "@ ++ sub\t%2, %0 ++ sub\t%2, %0 ++ add\t%N2, %0 ++ sub\t%2, %1, %0 ++ sub\t%Q2, %0" ++ [(set_attr "timings" "11,11,11,11,33") ++ (set_attr "length" "2,2,6,3,5")] + ) + ++;; A helper to expand the above with the CC_MODE filled in. ++(define_expand "subsi3_flags" ++ [(parallel [(set (match_operand:SI 0 "register_operand") ++ (minus:SI (match_operand:SI 1 "register_operand") ++ (match_operand:SI 2 "rx_source_operand"))) ++ (set (reg:CC_ZSC CC_REG) ++ (compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))])] ++) ++ ++(define_insn "sbb_internal" ++ [(set (match_operand:SI 0 "register_operand" "=r,r") ++ (minus:SI ++ (minus:SI ++ (match_operand:SI 1 "register_operand" " 0,0") ++ (match_operand:SI 2 "rx_compare_operand" " r,Q")) ++ (geu:SI (reg:CC CC_REG) (const_int 0)))) ++ (clobber (reg:CC CC_REG))] ++ "reload_completed" ++ "sbb\t%2, %0" ++ [(set_attr "timings" "11,33") ++ (set_attr "length" "3,6")] ++) ++ ++(define_insn "*sbb_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r") ++ (minus:SI ++ (minus:SI ++ (match_operand:SI 1 "register_operand" " 0,0") ++ (match_operand:SI 2 "rx_compare_operand" " r,Q")) ++ (geu:SI (reg:CC CC_REG) (const_int 0)))) ++ (set (reg CC_REG) ++ (compare ++ (minus:SI ++ (minus:SI (match_dup 1) (match_dup 2)) ++ (geu:SI (reg:CC CC_REG) (const_int 0))) ++ (const_int 0)))] ++ "reload_completed" ++ "sbb\t%2, %0" ++ [(set_attr "timings" "11,33") ++ (set_attr "length" "3,6")] ++) ++ ++(define_expand "subdi3" ++ [(set (match_operand:DI 0 "register_operand") ++ (minus:DI (match_operand:DI 1 "register_operand") ++ (match_operand:DI 2 "rx_compare_operand")))] ++ "" ++{ ++ rtx op0l, op0h, op1l, op1h, op2l, op2h; ++ ++ op0l = gen_lowpart (SImode, operands[0]); ++ op1l = gen_lowpart (SImode, operands[1]); ++ op2l = gen_lowpart (SImode, operands[2]); ++ op0h = gen_highpart (SImode, operands[0]); ++ op1h = gen_highpart (SImode, operands[1]); ++ op2h = gen_highpart_mode (SImode, DImode, operands[2]); ++ ++ emit_insn (gen_subdi3_internal (op0l, op0h, op1l, op2l, op1h, op2h)); ++ DONE; ++}) ++ ++(define_insn_and_split "subdi3_internal" ++ [(set (match_operand:SI 0 "register_operand" "=&r,&r") ++ (minus:SI (match_operand:SI 2 "register_operand" " 0, r") ++ (match_operand:SI 3 "rx_compare_operand" "rQ, r"))) ++ (set (match_operand:SI 1 "register_operand" "= r, r") ++ (minus:SI ++ (minus:SI ++ (match_operand:SI 4 "register_operand" " 1, 1") ++ (match_operand:SI 5 "rx_compare_operand" " rQ,rQ")) ++ (geu:SI (match_dup 2) (match_dup 3)))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "#" ++ "reload_completed" ++ [(const_int 0)] ++{ ++ emit_insn (gen_subsi3_flags (operands[0], operands[2], operands[3])); ++ emit_insn (gen_sbb_internal (operands[1], operands[4], operands[5])); ++ DONE; ++}) ++ + (define_insn "xorsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") + (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0") + (match_operand:SI 2 "rx_source_operand" + "r,Sint08,Sint16,Sint24,i,Q"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (xor:SI (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "" + "xor\t%Q2, %0" + [(set_attr "timings" "11,11,11,11,11,33") + (set_attr "length" "3,4,5,6,7,6")] + ) ++ ++(define_insn "*xorsi3_flags" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") ++ (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0") ++ (match_operand:SI 2 "rx_source_operand" ++ "r,Sint08,Sint16,Sint24,i,Q"))) ++ (set (reg CC_REG) ++ (compare (xor:SI (match_dup 1) (match_dup 2)) ++ (const_int 0)))] ++ "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" ++ "xor\t%Q2, %0" ++ [(set_attr "timings" "11,11,11,11,11,33") ++ (set_attr "length" "3,4,5,6,7,6")] ++) + + ;; Floating Point Instructions + +@@ -1169,9 +1549,7 @@ + [(set (match_operand:SF 0 "register_operand" "=r,r,r") + (plus:SF (match_operand:SF 1 "register_operand" "%0,0,0") + (match_operand:SF 2 "rx_source_operand" "r,F,Q"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (plus:SF (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "ALLOW_RX_FPU_INSNS" + "fadd\t%2, %0" + [(set_attr "timings" "44,44,66") +@@ -1182,9 +1560,7 @@ + [(set (match_operand:SF 0 "register_operand" "=r,r,r") + (div:SF (match_operand:SF 1 "register_operand" "0,0,0") + (match_operand:SF 2 "rx_source_operand" "r,F,Q"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (div:SF (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "ALLOW_RX_FPU_INSNS" + "fdiv\t%2, %0" + [(set_attr "timings" "1616,1616,1818") +@@ -1195,9 +1571,7 @@ + [(set (match_operand:SF 0 "register_operand" "=r,r,r") + (mult:SF (match_operand:SF 1 "register_operand" "%0,0,0") + (match_operand:SF 2 "rx_source_operand" "r,F,Q"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (mult:SF (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "ALLOW_RX_FPU_INSNS" + "fmul\t%2, %0" + [(set_attr "timings" "33,33,55") +@@ -1208,9 +1582,7 @@ + [(set (match_operand:SF 0 "register_operand" "=r,r,r") + (minus:SF (match_operand:SF 1 "register_operand" "0,0,0") + (match_operand:SF 2 "rx_source_operand" "r,F,Q"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (minus:SF (match_dup 1) (match_dup 2)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "ALLOW_RX_FPU_INSNS" + "fsub\t%Q2, %0" + [(set_attr "timings" "44,44,66") +@@ -1220,9 +1592,7 @@ + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (fix:SI (match_operand:SF 1 "rx_compare_operand" "r,Q"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (fix:SI (match_dup 1)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "ALLOW_RX_FPU_INSNS" + "ftoi\t%Q1, %0" + [(set_attr "timings" "22,44") +@@ -1232,9 +1602,7 @@ + (define_insn "floatsisf2" + [(set (match_operand:SF 0 "register_operand" "=r,r") + (float:SF (match_operand:SI 1 "rx_compare_operand" "r,Q"))) +- (set (reg:CC_ZS CC_REG) +- (compare:CC_ZS (float:SF (match_dup 1)) +- (const_int 0)))] ++ (clobber (reg:CC CC_REG))] + "ALLOW_RX_FPU_INSNS" + "itof\t%Q1, %0" + [(set_attr "timings" "22,44") +@@ -1242,217 +1610,216 @@ + ) + + ;; Bit manipulation instructions. +-;; Note - there are two versions of each pattern because the memory +-;; accessing versions use QImode whilst the register accessing +-;; versions use SImode. +-;; The peephole are here because the combiner only looks at a maximum +-;; of three instructions at a time. + +-(define_insn "bitset" +- [(set:SI (match_operand:SI 0 "register_operand" "=r") +- (ior:SI (match_operand:SI 1 "register_operand" "0") +- (ashift:SI (const_int 1) +- (match_operand:SI 2 "nonmemory_operand" "ri"))))] ++;; ??? The *_in_memory patterns will not be matched without further help. ++;; At one time we had the insv expander generate them, but I suspect that ++;; in general we get better performance by exposing the register load to ++;; the optimizers. ++;; ++;; An alternate solution would be to re-organize these patterns such ++;; that allow both register and memory operands. This would allow the ++;; register allocator to spill and not load the register operand. This ++;; would be possible only for operations for which we have a constant ++;; bit offset, so that we can adjust the address by ofs/8 and replace ++;; the offset in the insn by ofs%8. ++ ++(define_insn "*bitset" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (ashift:SI (const_int 1) ++ (match_operand:SI 1 "rx_shift_operand" "ri")) ++ (match_operand:SI 2 "register_operand" "0")))] + "" +- "bset\t%2, %0" ++ "bset\t%1, %0" + [(set_attr "length" "3")] + ) + +-(define_insn "bitset_in_memory" +- [(set:QI (match_operand:QI 0 "memory_operand" "=m") +- (ior:QI (match_operand:QI 1 "memory_operand" "0") +- (ashift:QI (const_int 1) +- (match_operand:QI 2 "nonmemory_operand" "ri"))))] ++(define_insn "*bitset_in_memory" ++ [(set (match_operand:QI 0 "memory_operand" "+Q") ++ (ior:QI (ashift:QI (const_int 1) ++ (match_operand:QI 1 "nonmemory_operand" "ri")) ++ (match_dup 0)))] + "" +- "bset\t%2, %0.B" ++ "bset\t%1, %0.B" + [(set_attr "length" "3") + (set_attr "timings" "34")] + ) + +-;; (set (reg A) (const_int 1)) +-;; (set (reg A) (ashift (reg A) (reg B))) +-;; (set (reg C) (ior (reg A) (reg C))) +-(define_peephole2 +- [(set:SI (match_operand:SI 0 "register_operand" "") +- (const_int 1)) +- (set:SI (match_dup 0) +- (ashift:SI (match_dup 0) +- (match_operand:SI 1 "register_operand" ""))) +- (set:SI (match_operand:SI 2 "register_operand" "") +- (ior:SI (match_dup 0) +- (match_dup 2)))] +- "dead_or_set_p (insn, operands[0])" +- [(set:SI (match_dup 2) +- (ior:SI (match_dup 2) +- (ashift:SI (const_int 1) +- (match_dup 1))))] +-) +- +-;; (set (reg A) (const_int 1)) +-;; (set (reg A) (ashift (reg A) (reg B))) +-;; (set (reg A) (ior (reg A) (reg C))) +-;; (set (reg C) (reg A) +-(define_peephole2 +- [(set:SI (match_operand:SI 0 "register_operand" "") +- (const_int 1)) +- (set:SI (match_dup 0) +- (ashift:SI (match_dup 0) +- (match_operand:SI 1 "register_operand" ""))) +- (set:SI (match_dup 0) +- (ior:SI (match_dup 0) +- (match_operand:SI 2 "register_operand" ""))) +- (set:SI (match_dup 2) (match_dup 0))] +- "dead_or_set_p (insn, operands[0])" +- [(set:SI (match_dup 2) +- (ior:SI (match_dup 2) +- (ashift:SI (const_int 1) +- (match_dup 1))))] +-) +- +-(define_insn "bitinvert" +- [(set:SI (match_operand:SI 0 "register_operand" "+r") +- (xor:SI (match_operand:SI 1 "register_operand" "0") +- (ashift:SI (const_int 1) +- (match_operand:SI 2 "nonmemory_operand" "ri"))))] ++(define_insn "*bitinvert" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (ashift:SI (const_int 1) ++ (match_operand:SI 1 "rx_shift_operand" "ri")) ++ (match_operand:SI 2 "register_operand" "0")))] + "" +- "bnot\t%2, %0" ++ "bnot\t%1, %0" + [(set_attr "length" "3")] + ) + +-(define_insn "bitinvert_in_memory" +- [(set:QI (match_operand:QI 0 "memory_operand" "+m") +- (xor:QI (match_operand:QI 1 "register_operand" "0") +- (ashift:QI (const_int 1) +- (match_operand:QI 2 "nonmemory_operand" "ri"))))] ++(define_insn "*bitinvert_in_memory" ++ [(set (match_operand:QI 0 "memory_operand" "+Q") ++ (xor:QI (ashift:QI (const_int 1) ++ (match_operand:QI 1 "nonmemory_operand" "ri")) ++ (match_dup 0)))] + "" +- "bnot\t%2, %0.B" ++ "bnot\t%1, %0.B" + [(set_attr "length" "5") + (set_attr "timings" "33")] + ) + +-;; (set (reg A) (const_int 1)) +-;; (set (reg A) (ashift (reg A) (reg B))) +-;; (set (reg C) (xor (reg A) (reg C))) +-(define_peephole2 +- [(set:SI (match_operand:SI 0 "register_operand" "") +- (const_int 1)) +- (set:SI (match_dup 0) +- (ashift:SI (match_dup 0) +- (match_operand:SI 1 "register_operand" ""))) +- (set:SI (match_operand:SI 2 "register_operand" "") +- (xor:SI (match_dup 0) +- (match_dup 2)))] +- "dead_or_set_p (insn, operands[0])" +- [(set:SI (match_dup 2) +- (xor:SI (match_dup 2) +- (ashift:SI (const_int 1) +- (match_dup 1))))] ++(define_insn "*bitclr" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (not:SI ++ (ashift:SI ++ (const_int 1) ++ (match_operand:SI 1 "rx_shift_operand" "ri"))) ++ (match_operand:SI 2 "register_operand" "0")))] + "" ++ "bclr\t%1, %0" ++ [(set_attr "length" "3")] + ) +- +-;; (set (reg A) (const_int 1)) +-;; (set (reg A) (ashift (reg A) (reg B))) +-;; (set (reg A) (xor (reg A) (reg C))) +-;; (set (reg C) (reg A)) +-(define_peephole2 +- [(set:SI (match_operand:SI 0 "register_operand" "") +- (const_int 1)) +- (set:SI (match_dup 0) +- (ashift:SI (match_dup 0) +- (match_operand:SI 1 "register_operand" ""))) +- (set:SI (match_dup 0) +- (xor:SI (match_dup 0) +- (match_operand:SI 2 "register_operand" ""))) +- (set:SI (match_dup 2) (match_dup 0))] +- "dead_or_set_p (insn, operands[0])" +- [(set:SI (match_dup 2) +- (xor:SI (match_dup 2) +- (ashift:SI (const_int 1) +- (match_dup 1))))] ++ ++(define_insn "*bitclr_in_memory" ++ [(set (match_operand:QI 0 "memory_operand" "+Q") ++ (and:QI (not:QI ++ (ashift:QI ++ (const_int 1) ++ (match_operand:QI 1 "nonmemory_operand" "ri"))) ++ (match_dup 0)))] + "" ++ "bclr\t%1, %0.B" ++ [(set_attr "length" "3") ++ (set_attr "timings" "34")] + ) + +-(define_insn "bitclr" +- [(set:SI (match_operand:SI 0 "register_operand" "+r") +- (and:SI (match_operand:SI 1 "register_operand" "0") +- (not:SI (ashift:SI (const_int 1) +- (match_operand:SI 2 "nonmemory_operand" "ri")))))] +- "" +- "bclr\t%2, %0" ++(define_insn "*insv_imm" ++ [(set (zero_extract:SI ++ (match_operand:SI 0 "register_operand" "+r") ++ (const_int 1) ++ (match_operand:SI 1 "rx_shift_operand" "ri")) ++ (match_operand:SI 2 "const_int_operand" ""))] ++ "" ++{ ++ if (INTVAL (operands[2]) & 1) ++ return "bset\t%1, %0"; ++ else ++ return "bclr\t%1, %0"; ++} + [(set_attr "length" "3")] + ) + +-(define_insn "bitclr_in_memory" +- [(set:QI (match_operand:QI 0 "memory_operand" "+m") +- (and:QI (match_operand:QI 1 "memory_operand" "0") +- (not:QI (ashift:QI (const_int 1) +- (match_operand:QI 2 "nonmemory_operand" "ri")))))] ++(define_insn_and_split "rx_insv_reg" ++ [(set (zero_extract:SI ++ (match_operand:SI 0 "register_operand" "+r") ++ (const_int 1) ++ (match_operand:SI 1 "const_int_operand" "")) ++ (match_operand:SI 2 "register_operand" "r")) ++ (clobber (reg:CC CC_REG))] + "" +- "bclr\t%2, %0.B" +- [(set_attr "length" "3") +- (set_attr "timings" "34")] ++ "#" ++ "reload_completed" ++ [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)) ++ (match_dup 3))] ++{ ++ rtx flags, x; ++ ++ /* Emit tst #1, op2. */ ++ flags = gen_rtx_REG (CC_ZSmode, CC_REG); ++ x = gen_rtx_AND (SImode, operands[2], const1_rtx); ++ x = gen_rtx_COMPARE (CC_ZSmode, x, const0_rtx); ++ x = gen_rtx_SET (VOIDmode, flags, x); ++ emit_insn (x); ++ ++ /* Emit bmne. */ ++ operands[3] = gen_rtx_NE (SImode, flags, const0_rtx); ++}) ++ ++(define_insn_and_split "*insv_cond" ++ [(set (zero_extract:SI ++ (match_operand:SI 0 "register_operand" "+r") ++ (const_int 1) ++ (match_operand:SI 1 "const_int_operand" "")) ++ (match_operator:SI 4 "comparison_operator" ++ [(match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "rx_source_operand" "riQ")])) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "#" ++ "reload_completed" ++ [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)) ++ (match_dup 4))] ++{ ++ rtx flags, x; ++ ++ flags = gen_rtx_REG (CCmode, CC_REG); ++ x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]); ++ x = gen_rtx_SET (VOIDmode, flags, x); ++ emit_insn (x); ++ ++ operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, ++ flags, const0_rtx); ++}) ++ ++(define_insn "*bmcc" ++ [(set (zero_extract:SI ++ (match_operand:SI 0 "register_operand" "+r") ++ (const_int 1) ++ (match_operand:SI 1 "const_int_operand" "")) ++ (match_operator:SI 2 "comparison_operator" ++ [(reg CC_REG) (const_int 0)]))] ++ "reload_completed" ++ "bm%B2\t%1, %0" ++ [(set_attr "length" "3")] + ) + +-;; (set (reg A) (const_int -2)) +-;; (set (reg A) (rotate (reg A) (reg B))) +-;; (set (reg C) (and (reg A) (reg C))) +-(define_peephole2 +- [(set:SI (match_operand:SI 0 "register_operand" "") +- (const_int -2)) +- (set:SI (match_dup 0) +- (rotate:SI (match_dup 0) +- (match_operand:SI 1 "register_operand" ""))) +- (set:SI (match_operand:SI 2 "register_operand" "") +- (and:SI (match_dup 0) +- (match_dup 2)))] +- "dead_or_set_p (insn, operands[0])" +- [(set:SI (match_dup 2) +- (and:SI (match_dup 2) +- (not:SI (ashift:SI (const_int 1) +- (match_dup 1)))))] +-) +- +-;; (set (reg A) (const_int -2)) +-;; (set (reg A) (rotate (reg A) (reg B))) +-;; (set (reg A) (and (reg A) (reg C))) +-;; (set (reg C) (reg A) +-(define_peephole2 +- [(set:SI (match_operand:SI 0 "register_operand" "") +- (const_int -2)) +- (set:SI (match_dup 0) +- (rotate:SI (match_dup 0) +- (match_operand:SI 1 "register_operand" ""))) +- (set:SI (match_dup 0) +- (and:SI (match_dup 0) +- (match_operand:SI 2 "register_operand" ""))) +- (set:SI (match_dup 2) (match_dup 0))] +- "dead_or_set_p (insn, operands[0])" +- [(set:SI (match_dup 2) +- (and:SI (match_dup 2) +- (not:SI (ashift:SI (const_int 1) +- (match_dup 1)))))] ++;; Work around the fact that X=Y<0 is preferentially expanded as a shift. ++(define_insn_and_split "*insv_cond_lt" ++ [(set (zero_extract:SI ++ (match_operand:SI 0 "register_operand" "+r") ++ (const_int 1) ++ (match_operand:SI 1 "const_int_operand" "")) ++ (match_operator:SI 3 "rshift_operator" ++ [(match_operand:SI 2 "register_operand" "r") ++ (const_int 31)])) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "#" ++ "" ++ [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)) ++ (lt:SI (match_dup 2) (const_int 0))) ++ (clobber (reg:CC CC_REG))])] ++ "" + ) + + (define_expand "insv" +- [(set:SI (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand") ;; Destination +- (match_operand 1 "immediate_operand") ;; # of bits to set +- (match_operand 2 "immediate_operand")) ;; Starting bit +- (match_operand 3 "immediate_operand"))] ;; Bits to insert +- "" +- { +- if (rx_expand_insv (operands)) ++ [(set (zero_extract:SI ++ (match_operand:SI 0 "register_operand") ;; Destination ++ (match_operand:SI 1 "const_int_operand") ;; # of bits to set ++ (match_operand:SI 2 "nonmemory_operand")) ;; Starting bit ++ (match_operand:SI 3 "nonmemory_operand"))] ;; Bits to insert ++ "" ++{ ++ /* We only handle single-bit inserts. */ ++ if (!CONST_INT_P (operands[1]) || INTVAL (operands[1]) != 1) ++ FAIL; ++ ++ /* Either the bit to insert or the position must be constant. */ ++ if (CONST_INT_P (operands[3])) ++ operands[3] = GEN_INT (INTVAL (operands[3]) & 1); ++ else if (CONST_INT_P (operands[2])) ++ { ++ emit_insn (gen_rx_insv_reg (operands[0], operands[2], operands[3])); + DONE; ++ } ++ else + FAIL; +- } +-) ++}) + + ;; Atomic exchange operation. + + (define_insn "sync_lock_test_and_setsi" +- [(set:SI (match_operand:SI 0 "register_operand" "=r,r") +- (match_operand:SI 1 "rx_compare_operand" "=r,Q")) +- (set:SI (match_dup 1) +- (match_operand:SI 2 "register_operand" "0,0"))] ++ [(set (match_operand:SI 0 "register_operand" "=r,r") ++ (match_operand:SI 1 "rx_compare_operand" "=r,Q")) ++ (set (match_dup 1) ++ (match_operand:SI 2 "register_operand" "0,0"))] + "" + "xchg\t%1, %0" + [(set_attr "length" "3,6") +@@ -1462,9 +1829,9 @@ + ;; Block move functions. + + (define_expand "movstr" +- [(set:SI (match_operand:BLK 1 "memory_operand") ;; Dest +- (match_operand:BLK 2 "memory_operand")) ;; Source +- (use (match_operand:SI 0 "register_operand")) ;; Updated Dest ++ [(set (match_operand:BLK 1 "memory_operand") ;; Dest ++ (match_operand:BLK 2 "memory_operand")) ;; Source ++ (use (match_operand:SI 0 "register_operand")) ;; Updated Dest + ] + "" + { +@@ -1487,8 +1854,8 @@ + ) + + (define_insn "rx_movstr" +- [(set:SI (mem:BLK (reg:SI 1)) +- (mem:BLK (reg:SI 2))) ++ [(set (mem:BLK (reg:SI 1)) ++ (mem:BLK (reg:SI 2))) + (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVSTR) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) +@@ -1500,8 +1867,8 @@ + ) + + (define_insn "rx_strend" +- [(set:SI (match_operand:SI 0 "register_operand" "=r") +- (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") + (reg:SI 3)] UNSPEC_STRLEN)) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) +@@ -1582,8 +1949,8 @@ + ) + + (define_insn "rx_setmem" +- [(set:BLK (mem:BLK (reg:SI 1)) (reg 2)) +- (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_SETMEM) ++ [(set (mem:BLK (reg:SI 1)) ++ (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_SETMEM)) + (clobber (reg:SI 1)) + (clobber (reg:SI 3))] + "" +@@ -1636,11 +2003,11 @@ + ) + + (define_insn "rx_cmpstrn" +- [(set:SI (match_operand:SI 0 "register_operand" "=r") +- (unspec_volatile:SI [(reg:SI 1) (reg:SI 2) (reg:SI 3)] +- UNSPEC_CMPSTRN)) +- (use (match_operand:BLK 1 "memory_operand" "m")) +- (use (match_operand:BLK 2 "memory_operand" "m")) ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI [(reg:SI 1) (reg:SI 2) (reg:SI 3)] ++ UNSPEC_CMPSTRN)) ++ (use (match_operand:BLK 1 "memory_operand" "m")) ++ (use (match_operand:BLK 2 "memory_operand" "m")) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (clobber (reg:SI 3)) +@@ -1773,7 +2140,7 @@ + + ;; Byte swap (two 16-bit values). + (define_insn "revw" +- [(set (match_operand:SI 0 "register_operand" "+r") ++ [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_BUILTIN_REVW))] + "" +@@ -1807,7 +2174,7 @@ + + ;; Clear Processor Status Word + (define_insn "clrpsw" +- [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i")] ++ [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")] + UNSPEC_BUILTIN_CLRPSW) + (clobber (reg:CC CC_REG))] + "" +@@ -1817,7 +2184,7 @@ + + ;; Set Processor Status Word + (define_insn "setpsw" +- [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i")] ++ [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")] + UNSPEC_BUILTIN_SETPSW) + (clobber (reg:CC CC_REG))] + "" +@@ -1828,7 +2195,7 @@ + ;; Move from control register + (define_insn "mvfc" + [(set (match_operand:SI 0 "register_operand" "=r") +- (unspec:SI [(match_operand:SI 1 "immediate_operand" "i")] ++ (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] + UNSPEC_BUILTIN_MVFC))] + "" + "mvfc\t%C1, %0" +@@ -1837,7 +2204,7 @@ + + ;; Move to control register + (define_insn "mvtc" +- [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i,i") ++ [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i,i") + (match_operand:SI 1 "nonmemory_operand" "r,i")] + UNSPEC_BUILTIN_MVTC)] + "" +@@ -1852,7 +2219,7 @@ + + ;; Move to interrupt priority level + (define_insn "mvtipl" +- [(unspec:SI [(match_operand:SI 0 "immediate_operand" "Uint04")] ++ [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "Uint04")] + UNSPEC_BUILTIN_MVTIPL)] + "" + "mvtipl\t%0" +--- a/src/gcc/config/s390/s390.c ++++ b/src/gcc/config/s390/s390.c +@@ -8170,7 +8170,7 @@ + + p = rtvec_alloc (2); + +- RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); ++ RTVEC_ELT (p, 0) = ret_rtx; + RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg); + emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); + } +--- a/src/gcc/config/sh/sh.c ++++ b/src/gcc/config/sh/sh.c +@@ -950,6 +950,10 @@ + + if (sh_fixed_range_str) + sh_fix_range (sh_fixed_range_str); ++ ++ /* This target defaults to strict volatile bitfields. */ ++ if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) ++ flag_strict_volatile_bitfields = 1; + } + + /* Print the operand address in x to the stream. */ +@@ -5248,7 +5252,8 @@ + } + if (prev + && JUMP_P (prev) +- && JUMP_LABEL (prev)) ++ && JUMP_LABEL (prev) ++ && !ANY_RETURN_P (JUMP_LABEL (prev))) + { + rtx x; + if (jump_to_next +@@ -5947,7 +5952,7 @@ + JUMP_LABEL (insn) = far_label; + LABEL_NUSES (far_label)++; + } +- redirect_jump (insn, NULL_RTX, 1); ++ redirect_jump (insn, ret_rtx, 1); + far_label = 0; + } + } +--- a/src/gcc/config/sparc/predicates.md ++++ b/src/gcc/config/sparc/predicates.md +@@ -1,5 +1,5 @@ + ;; Predicate definitions for SPARC. +-;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc. ++;; Copyright (C) 2005, 2007, 2008, 2010 Free Software Foundation, Inc. + ;; + ;; This file is part of GCC. + ;; +@@ -473,9 +473,3 @@ + ;; and (xor ... (not ...)) to (not (xor ...)). */ + (define_predicate "cc_arith_not_operator" + (match_code "and,ior")) +- +-;; Return true if OP is memory operand with just [%reg] addressing mode. +-(define_predicate "memory_reg_operand" +- (and (match_code "mem") +- (and (match_operand 0 "memory_operand") +- (match_test "REG_P (XEXP (op, 0))")))) +--- a/src/gcc/config/sparc/sparc.c ++++ b/src/gcc/config/sparc/sparc.c +@@ -363,7 +363,7 @@ + static int epilogue_renumber (rtx *, int); + static bool sparc_assemble_integer (rtx, unsigned int, int); + static int set_extends (rtx); +-static void load_pic_register (void); ++static void load_got_register (void); + static int save_or_restore_regs (int, int, rtx, int, int); + static void emit_save_or_restore_regs (int); + static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT); +@@ -966,6 +966,36 @@ + return 0; + } + ++/* Return true if the address of LABEL can be loaded by means of the ++ mov{si,di}_pic_label_ref patterns in PIC mode. */ ++ ++static bool ++can_use_mov_pic_label_ref (rtx label) ++{ ++ /* VxWorks does not impose a fixed gap between segments; the run-time ++ gap can be different from the object-file gap. We therefore can't ++ assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we ++ are absolutely sure that X is in the same segment as the GOT. ++ Unfortunately, the flexibility of linker scripts means that we ++ can't be sure of that in general, so assume that GOT-relative ++ accesses are never valid on VxWorks. */ ++ if (TARGET_VXWORKS_RTP) ++ return false; ++ ++ /* Similarly, if the label is non-local, it might end up being placed ++ in a different section than the current one; now mov_pic_label_ref ++ requires the label and the code to be in the same section. */ ++ if (LABEL_REF_NONLOCAL_P (label)) ++ return false; ++ ++ /* Finally, if we are reordering basic blocks and partition into hot ++ and cold sections, this might happen for any label. */ ++ if (flag_reorder_blocks_and_partition) ++ return false; ++ ++ return true; ++} ++ + /* Expand a move instruction. Return true if all work is done. */ + + bool +@@ -1000,14 +1030,9 @@ + if (pic_address_needs_scratch (operands[1])) + operands[1] = legitimize_pic_address (operands[1], NULL_RTX); + +- /* VxWorks does not impose a fixed gap between segments; the run-time +- gap can be different from the object-file gap. We therefore can't +- assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we +- are absolutely sure that X is in the same segment as the GOT. +- Unfortunately, the flexibility of linker scripts means that we +- can't be sure of that in general, so assume that _G_O_T_-relative +- accesses are never valid on VxWorks. */ +- if (GET_CODE (operands[1]) == LABEL_REF && !TARGET_VXWORKS_RTP) ++ /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */ ++ if (GET_CODE (operands[1]) == LABEL_REF ++ && can_use_mov_pic_label_ref (operands[1])) + { + if (mode == SImode) + { +@@ -2907,26 +2932,39 @@ + } + } + +-/* PIC support. */ +-static GTY(()) bool pic_helper_needed = false; +-static GTY(()) rtx pic_helper_symbol; +-static GTY(()) rtx global_offset_table; ++/* Global Offset Table support. */ ++static GTY(()) rtx got_helper_rtx = NULL_RTX; ++static GTY(()) rtx global_offset_table_rtx = NULL_RTX; ++ ++/* Return the SYMBOL_REF for the Global Offset Table. */ ++ ++static GTY(()) rtx sparc_got_symbol = NULL_RTX; ++ ++static rtx ++sparc_got (void) ++{ ++ if (!sparc_got_symbol) ++ sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); ++ ++ return sparc_got_symbol; ++} + + /* Ensure that we are not using patterns that are not OK with PIC. */ + + int + check_pic (int i) + { ++ rtx op; ++ + switch (flag_pic) + { + case 1: +- gcc_assert (GET_CODE (recog_data.operand[i]) != SYMBOL_REF +- && (GET_CODE (recog_data.operand[i]) != CONST +- || (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS +- && (XEXP (XEXP (recog_data.operand[i], 0), 0) +- == global_offset_table) +- && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) +- == CONST)))); ++ op = recog_data.operand[i]; ++ gcc_assert (GET_CODE (op) != SYMBOL_REF ++ && (GET_CODE (op) != CONST ++ || (GET_CODE (XEXP (op, 0)) == MINUS ++ && XEXP (XEXP (op, 0), 0) == sparc_got () ++ && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST))); + case 2: + default: + return 1; +@@ -3161,9 +3199,9 @@ + return 1; + } + +-/* Construct the SYMBOL_REF for the tls_get_offset function. */ ++/* Return the SYMBOL_REF for the tls_get_addr function. */ + +-static GTY(()) rtx sparc_tls_symbol; ++static GTY(()) rtx sparc_tls_symbol = NULL_RTX; + + static rtx + sparc_tls_get_addr (void) +@@ -3174,21 +3212,28 @@ + return sparc_tls_symbol; + } + ++/* Return the Global Offset Table to be used in TLS mode. */ ++ + static rtx + sparc_tls_got (void) + { +- rtx temp; ++ /* In PIC mode, this is just the PIC offset table. */ + if (flag_pic) + { + crtl->uses_pic_offset_table = 1; + return pic_offset_table_rtx; + } + +- if (!global_offset_table) +- global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); +- temp = gen_reg_rtx (Pmode); +- emit_move_insn (temp, global_offset_table); +- return temp; ++ /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for ++ the GOT symbol with the 32-bit ABI, so we reload the GOT register. */ ++ if (TARGET_SUN_TLS && TARGET_ARCH32) ++ { ++ load_got_register (); ++ return global_offset_table_rtx; ++ } ++ ++ /* In all other cases, we load a new pseudo with the GOT symbol. */ ++ return copy_to_reg (sparc_got ()); + } + + /* Return true if X contains a thread-local symbol. */ +@@ -3369,7 +3414,7 @@ + + if (GET_CODE (orig) == SYMBOL_REF + /* See the comment in sparc_expand_move. */ +- || (TARGET_VXWORKS_RTP && GET_CODE (orig) == LABEL_REF)) ++ || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig))) + { + rtx pic_ref, address; + rtx insn; +@@ -3420,11 +3465,13 @@ + } + else + { +- pic_ref = gen_const_mem (Pmode, +- gen_rtx_PLUS (Pmode, +- pic_offset_table_rtx, address)); ++ pic_ref ++ = gen_const_mem (Pmode, ++ gen_rtx_PLUS (Pmode, ++ pic_offset_table_rtx, address)); + insn = emit_move_insn (reg, pic_ref); + } ++ + /* Put a REG_EQUAL note on this insn, so that it can be optimized + by loop. */ + set_unique_reg_note (insn, REG_EQUAL, orig); +@@ -3462,9 +3509,8 @@ + return gen_rtx_PLUS (Pmode, base, offset); + } + else if (GET_CODE (orig) == LABEL_REF) +- /* ??? Why do we do this? */ +- /* Now movsi_pic_label_ref uses it, but we ought to be checking that +- the register is live instead, in case it is eliminated. */ ++ /* ??? We ought to be checking that the register is live instead, in case ++ it is eliminated. */ + crtl->uses_pic_offset_table = 1; + + return orig; +@@ -3529,59 +3575,69 @@ + static void + get_pc_thunk_name (char name[32], unsigned int regno) + { +- const char *pic_name = reg_names[regno]; ++ const char *reg_name = reg_names[regno]; + + /* Skip the leading '%' as that cannot be used in a + symbol name. */ +- pic_name += 1; ++ reg_name += 1; + + if (USE_HIDDEN_LINKONCE) +- sprintf (name, "__sparc_get_pc_thunk.%s", pic_name); ++ sprintf (name, "__sparc_get_pc_thunk.%s", reg_name); + else + ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno); + } + +-/* Emit code to load the PIC register. */ ++/* Wrapper around the load_pcrel_sym{si,di} patterns. */ + +-static void +-load_pic_register (void) ++static rtx ++gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3) + { + int orig_flag_pic = flag_pic; ++ rtx insn; + +- if (TARGET_VXWORKS_RTP) +- { +- emit_insn (gen_vxworks_load_got ()); +- emit_use (pic_offset_table_rtx); +- return; +- } +- +- /* If we haven't initialized the special PIC symbols, do so now. */ +- if (!pic_helper_needed) +- { +- char name[32]; ++ /* The load_pcrel_sym{si,di} patterns require absolute addressing. */ ++ flag_pic = 0; ++ if (TARGET_ARCH64) ++ insn = gen_load_pcrel_symdi (op0, op1, op2, op3); ++ else ++ insn = gen_load_pcrel_symsi (op0, op1, op2, op3); ++ flag_pic = orig_flag_pic; + +- pic_helper_needed = true; ++ return insn; ++} + +- get_pc_thunk_name (name, REGNO (pic_offset_table_rtx)); +- pic_helper_symbol = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); ++/* Emit code to load the GOT register. */ + +- global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); +- } ++static void ++load_got_register (void) ++{ ++ /* In PIC mode, this will retrieve pic_offset_table_rtx. */ ++ if (!global_offset_table_rtx) ++ global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM); + +- flag_pic = 0; +- if (TARGET_ARCH64) +- emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx, global_offset_table, +- pic_helper_symbol)); ++ if (TARGET_VXWORKS_RTP) ++ emit_insn (gen_vxworks_load_got ()); + else +- emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx, global_offset_table, +- pic_helper_symbol)); +- flag_pic = orig_flag_pic; ++ { ++ /* The GOT symbol is subject to a PC-relative relocation so we need a ++ helper function to add the PC value and thus get the final value. */ ++ if (!got_helper_rtx) ++ { ++ char name[32]; ++ get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM); ++ got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); ++ } ++ ++ emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (), ++ got_helper_rtx, ++ GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM))); ++ } + + /* Need to emit this whether or not we obey regdecls, + since setjmp/longjmp can cause life info to screw up. + ??? In the case where we don't obey regdecls, this is not sufficient + since we may not fall out the bottom. */ +- emit_use (pic_offset_table_rtx); ++ emit_use (global_offset_table_rtx); + } + + /* Emit a call instruction with the pattern given by PAT. ADDR is the +@@ -4113,7 +4169,7 @@ + + /* Expand the function prologue. The prologue is responsible for reserving + storage for the frame, saving the call-saved registers and loading the +- PIC register if needed. */ ++ GOT register if needed. */ + + void + sparc_expand_prologue (void) +@@ -4215,9 +4271,9 @@ + if (num_gfregs) + emit_save_or_restore_regs (SORR_SAVE); + +- /* Load the PIC register if needed. */ +- if (flag_pic && crtl->uses_pic_offset_table) +- load_pic_register (); ++ /* Load the GOT register if needed. */ ++ if (crtl->uses_pic_offset_table) ++ load_got_register (); + } + + /* This function generates the assembly code for function entry, which boils +@@ -8705,7 +8761,7 @@ + /* Emit the sequence of insns SEQ while preserving the registers REG and REG2. + This is achieved by means of a manual dynamic stack space allocation in + the current frame. We make the assumption that SEQ doesn't contain any +- function calls, with the possible exception of calls to the PIC helper. */ ++ function calls, with the possible exception of calls to the GOT helper. */ + + static void + emit_and_preserve (rtx seq, rtx reg, rtx reg2) +@@ -8868,20 +8924,19 @@ + { + /* The hoops we have to jump through in order to generate a sibcall + without using delay slots... */ +- rtx spill_reg, spill_reg2, seq, scratch = gen_rtx_REG (Pmode, 1); ++ rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1); + + if (flag_pic) + { + spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */ +- spill_reg2 = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM); + start_sequence (); +- /* Delay emitting the PIC helper function because it needs to ++ /* Delay emitting the GOT helper function because it needs to + change the section and we are emitting assembly code. */ +- load_pic_register (); /* clobbers %o7 */ ++ load_got_register (); /* clobbers %o7 */ + scratch = legitimize_pic_address (funexp, scratch); + seq = get_insns (); + end_sequence (); +- emit_and_preserve (seq, spill_reg, spill_reg2); ++ emit_and_preserve (seq, spill_reg, pic_offset_table_rtx); + } + else if (TARGET_ARCH32) + { +@@ -9032,17 +9087,15 @@ + static void + sparc_file_end (void) + { +- /* If need to emit the special PIC helper function, do so now. */ +- if (pic_helper_needed) ++ /* If we need to emit the special GOT helper function, do so now. */ ++ if (got_helper_rtx) + { +- unsigned int regno = REGNO (pic_offset_table_rtx); +- const char *pic_name = reg_names[regno]; +- char name[32]; ++ const char *name = XSTR (got_helper_rtx, 0); ++ const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM]; + #ifdef DWARF2_UNWIND_INFO + bool do_cfi; + #endif + +- get_pc_thunk_name (name, regno); + if (USE_HIDDEN_LINKONCE) + { + tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, +@@ -9055,7 +9108,9 @@ + make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl)); + DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; + DECL_VISIBILITY_SPECIFIED (decl) = 1; ++ resolve_unique_section (decl, 0, flag_function_sections); + allocate_struct_function (decl, true); ++ cfun->is_thunk = 1; + current_function_decl = decl; + init_varasm_status (); + assemble_start_function (decl, name); +@@ -9076,10 +9131,10 @@ + #endif + if (flag_delayed_branch) + fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n", +- pic_name, pic_name); ++ reg_name, reg_name); + else + fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n", +- pic_name, pic_name); ++ reg_name, reg_name); + #ifdef DWARF2_UNWIND_INFO + if (do_cfi) + fprintf (asm_out_file, "\t.cfi_endproc\n"); +--- a/src/gcc/config/sparc/sparc.h ++++ b/src/gcc/config/sparc/sparc.h +@@ -964,10 +964,15 @@ + not be a register used by the prologue. */ + #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) + ++/* Register which holds the global offset table, if any. */ ++ ++#define GLOBAL_OFFSET_TABLE_REGNUM 23 ++ + /* Register which holds offset table for position-independent + data references. */ + +-#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM) ++#define PIC_OFFSET_TABLE_REGNUM \ ++ (flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM) + + /* Pick a default value we can notice from override_options: + !v9: Default is on. +@@ -1181,7 +1186,7 @@ + 96, 97, 98, 99, /* %fcc0-3 */ \ + 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ + +-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () + + extern char sparc_leaf_regs[]; + #define LEAF_REGISTERS sparc_leaf_regs +--- a/src/gcc/config/sparc/sparc.md ++++ b/src/gcc/config/sparc/sparc.md +@@ -1106,14 +1106,15 @@ + + ;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic + ;; value subject to a PC-relative relocation. Operand 2 is a helper function +-;; that adds the PC value at the call point to operand 0. ++;; that adds the PC value at the call point to register #(operand 3). + + (define_insn "load_pcrel_sym" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(match_operand:P 1 "symbolic_operand" "") +- (match_operand:P 2 "call_address_operand" "")] UNSPEC_LOAD_PCREL_SYM)) ++ (match_operand:P 2 "call_address_operand" "") ++ (match_operand:P 3 "const_int_operand" "")] UNSPEC_LOAD_PCREL_SYM)) + (clobber (reg:P 15))] +- "" ++ "REGNO (operands[0]) == INTVAL (operands[3])" + { + if (flag_delayed_branch) + return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0"; +--- a/src/gcc/config/sparc/sync.md ++++ b/src/gcc/config/sparc/sync.md +@@ -1,5 +1,5 @@ + ;; GCC machine description for SPARC synchronization instructions. +-;; Copyright (C) 2005, 2007, 2009 ++;; Copyright (C) 2005, 2007, 2009, 2010 + ;; Free Software Foundation, Inc. + ;; + ;; This file is part of GCC. +@@ -62,7 +62,7 @@ + + (define_expand "sync_compare_and_swap" + [(parallel +- [(set (match_operand:I48MODE 0 "register_operand" "=r") ++ [(set (match_operand:I48MODE 0 "register_operand" "") + (match_operand:I48MODE 1 "memory_operand" "")) + (set (match_dup 1) + (unspec_volatile:I48MODE +@@ -71,7 +71,7 @@ + UNSPECV_CAS))])] + "TARGET_V9" + { +- if (! REG_P (XEXP (operands[1], 0))) ++ if (!REG_P (XEXP (operands[1], 0))) + { + rtx addr = force_reg (Pmode, XEXP (operands[1], 0)); + operands[1] = replace_equiv_address (operands[1], addr); +@@ -81,20 +81,20 @@ + + (define_insn "*sync_compare_and_swap" + [(set (match_operand:I48MODE 0 "register_operand" "=r") +- (match_operand:I48MODE 1 "memory_reg_operand" "+m")) +- (set (match_dup 1) ++ (mem:I48MODE (match_operand 1 "register_operand" "r"))) ++ (set (mem:I48MODE (match_dup 1)) + (unspec_volatile:I48MODE + [(match_operand:I48MODE 2 "register_operand" "r") + (match_operand:I48MODE 3 "register_operand" "0")] + UNSPECV_CAS))] + "TARGET_V9 && (mode == SImode || TARGET_ARCH64)" +- "cas\t%1, %2, %0" ++ "cas\t[%1], %2, %0" + [(set_attr "type" "multi")]) + + (define_insn "*sync_compare_and_swapdi_v8plus" + [(set (match_operand:DI 0 "register_operand" "=h") +- (match_operand:DI 1 "memory_reg_operand" "+m")) +- (set (match_dup 1) ++ (mem:DI (match_operand 1 "register_operand" "r"))) ++ (set (mem:DI (match_dup 1)) + (unspec_volatile:DI + [(match_operand:DI 2 "register_operand" "h") + (match_operand:DI 3 "register_operand" "0")] +@@ -109,7 +109,7 @@ + output_asm_insn ("srl\t%L2, 0, %L2", operands); + output_asm_insn ("sllx\t%H2, 32, %H3", operands); + output_asm_insn ("or\t%L2, %H3, %H3", operands); +- output_asm_insn ("casx\t%1, %H3, %L3", operands); ++ output_asm_insn ("casx\t[%1], %H3, %L3", operands); + return "srlx\t%L3, 32, %H3"; + } + [(set_attr "type" "multi") +--- a/src/gcc/config/spu/spu.c ++++ b/src/gcc/config/spu/spu.c +@@ -4572,7 +4572,13 @@ + spu_expand_mov (rtx * ops, enum machine_mode mode) + { + if (GET_CODE (ops[0]) == SUBREG && !valid_subreg (ops[0])) +- abort (); ++ { ++ /* Perform the move in the destination SUBREG's inner mode. */ ++ ops[0] = SUBREG_REG (ops[0]); ++ mode = GET_MODE (ops[0]); ++ ops[1] = gen_lowpart_common (mode, ops[1]); ++ gcc_assert (ops[1]); ++ } + + if (GET_CODE (ops[1]) == SUBREG && !valid_subreg (ops[1])) + { +--- a/src/gcc/config/spu/spu.md ++++ b/src/gcc/config/spu/spu.md +@@ -269,8 +269,8 @@ + ;; mov + + (define_expand "mov" +- [(set (match_operand:ALL 0 "spu_nonimm_operand" "=r,r,r,m") +- (match_operand:ALL 1 "general_operand" "r,i,m,r"))] ++ [(set (match_operand:ALL 0 "nonimmediate_operand" "") ++ (match_operand:ALL 1 "general_operand" ""))] + "" + { + if (spu_expand_mov(operands, mode)) +--- a/src/gcc/config/v850/v850.c ++++ b/src/gcc/config/v850/v850.c +@@ -1832,7 +1832,7 @@ + { + restore_all = gen_rtx_PARALLEL (VOIDmode, + rtvec_alloc (num_restore + 2)); +- XVECEXP (restore_all, 0, 0) = gen_rtx_RETURN (VOIDmode); ++ XVECEXP (restore_all, 0, 0) = ret_rtx; + XVECEXP (restore_all, 0, 1) + = gen_rtx_SET (VOIDmode, stack_pointer_rtx, + gen_rtx_PLUS (Pmode, +--- a/src/gcc/config/xtensa/xtensa.h ++++ b/src/gcc/config/xtensa/xtensa.h +@@ -286,7 +286,7 @@ + incoming argument in a2 is live throughout the function and + local-alloc decides to use a2, then the incoming argument must + either be spilled or copied to another register. To get around +- this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine ++ this, we define ADJUST_REG_ALLOC_ORDER to redefine + reg_alloc_order for leaf functions such that lowest numbered + registers are used first with the exception that the incoming + argument registers are not used until after other register choices +@@ -300,7 +300,7 @@ + 35, \ + } + +-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () ++#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () + + /* For Xtensa, the only point of this is to prevent GCC from otherwise + giving preference to call-used registers. To minimize window +--- a/src/gcc/config.gcc ++++ b/src/gcc/config.gcc +@@ -1,6 +1,6 @@ + # GCC target-specific configuration file. + # Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, +-# 2008, 2009, 2010 Free Software Foundation, Inc. ++# 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + + #This file is part of GCC. + +@@ -1066,6 +1066,7 @@ + else + tmake_file="$tmake_file pa/t-slibgcc-dwarf-ver" + fi ++ extra_parts="libgcc_stub.a" + case x${enable_threads} in + x | xyes | xposix ) + thread_file=posix +--- a/src/gcc/config.host ++++ b/src/gcc/config.host +@@ -1,6 +1,6 @@ + # GCC host-specific configuration file. +-# Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2006, 2007, 2008, 2009 +-# Free Software Foundation, Inc. ++# Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2006, 2007, 2008, 2009, ++# 2011 Free Software Foundation, Inc. + + #This file is part of GCC. + +@@ -163,6 +163,10 @@ + prefix=/gnu + local_prefix=/gnu/local + ;; ++ alpha*-dec-osf*) ++ out_host_hook_obj=host-osf.o ++ host_xmake_file="${host_xmake_file} alpha/x-osf" ++ ;; + alpha*-dec-*vms*) + host_xm_file="vms/xm-vms.h" + host_xmake_file=vms/x-vms +--- a/src/gcc/config.in ++++ b/src/gcc/config.in +@@ -132,6 +132,12 @@ + #endif + + ++/* Define to warn for use of native system header directories */ ++#ifndef USED_FOR_TARGET ++#undef ENABLE_POISON_SYSTEM_DIRECTORIES ++#endif ++ ++ + /* Define if you want all operations on RTL (the basic data structure of the + optimizer and back end) to be checked for dynamic type safety at runtime. + This is quite expensive. */ +--- a/src/gcc/configure ++++ b/src/gcc/configure +@@ -912,6 +912,7 @@ + enable_maintainer_mode + enable_version_specific_runtime_libs + with_slibdir ++enable_poison_system_directories + enable_plugin + ' + ac_precious_vars='build_alias +@@ -1619,6 +1620,8 @@ + --enable-version-specific-runtime-libs + specify that runtime libraries should be + installed in a compiler-specific directory ++ --enable-poison-system-directories ++ warn for use of native system header directories + --enable-plugin enable plugin support + + Optional Packages: +@@ -1642,7 +1645,8 @@ + use sysroot as the system root during the build + --with-sysroot=DIR Search for usr/lib, usr/include, et al, within DIR. + --with-specs=SPECS add SPECS to driver command-line processing +- --with-pkgversion=PKG Use PKG in the version string in place of "GCC" ++ --with-pkgversion=PKG Use PKG in the version string in place of "Linaro ++ GCC `cat $srcdir/LINARO-VERSION`" + --with-bugurl=URL Direct users to URL to report a bug + --with-multilib-list Select multilibs (SH only) + --with-gnu-ld assume the C compiler uses GNU ld default=no +@@ -6897,7 +6901,7 @@ + *) PKGVERSION="($withval) " ;; + esac + else +- PKGVERSION="(GCC) " ++ PKGVERSION="(Linaro GCC `cat $srcdir/LINARO-VERSION`) " + + fi + +@@ -17108,7 +17112,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 17111 "configure" ++#line 17115 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -17214,7 +17218,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 17217 "configure" ++#line 17221 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -25354,6 +25358,19 @@ + + + ++# Check whether --enable-poison-system-directories was given. ++if test "${enable_poison_system_directories+set}" = set; then : ++ enableval=$enable_poison_system_directories; ++else ++ enable_poison_system_directories=no ++fi ++ ++if test "x${enable_poison_system_directories}" = "xyes"; then ++ ++$as_echo "#define ENABLE_POISON_SYSTEM_DIRECTORIES 1" >>confdefs.h ++ ++fi ++ + # Substitute configuration variables + + +--- a/src/gcc/configure.ac ++++ b/src/gcc/configure.ac +@@ -803,7 +803,7 @@ + [onestep=""]) + AC_SUBST(onestep) + +-ACX_PKGVERSION([GCC]) ++ACX_PKGVERSION([Linaro GCC `cat $srcdir/LINARO-VERSION`]) + ACX_BUGURL([http://gcc.gnu.org/bugs.html]) + + # Sanity check enable_languages in case someone does not run the toplevel +@@ -4449,6 +4449,16 @@ + fi) + AC_SUBST(slibdir) + ++AC_ARG_ENABLE([poison-system-directories], ++ AS_HELP_STRING([--enable-poison-system-directories], ++ [warn for use of native system header directories]),, ++ [enable_poison_system_directories=no]) ++if test "x${enable_poison_system_directories}" = "xyes"; then ++ AC_DEFINE([ENABLE_POISON_SYSTEM_DIRECTORIES], ++ [1], ++ [Define to warn for use of native system header directories]) ++fi ++ + # Substitute configuration variables + AC_SUBST(subdirs) + AC_SUBST(srcdir) +--- a/src/gcc/cp/call.c ++++ b/src/gcc/cp/call.c +@@ -3946,6 +3946,10 @@ + /* In this case, there is always a common type. */ + result_type = type_after_usual_arithmetic_conversions (arg2_type, + arg3_type); ++ do_warn_double_promotion (result_type, arg2_type, arg3_type, ++ "implicit conversion from %qT to %qT to " ++ "match other result of conditional", ++ input_location); + + if (TREE_CODE (arg2_type) == ENUMERAL_TYPE + && TREE_CODE (arg3_type) == ENUMERAL_TYPE) +@@ -5179,11 +5183,14 @@ + tree + convert_arg_to_ellipsis (tree arg) + { ++ tree arg_type; ++ + /* [expr.call] + + The lvalue-to-rvalue, array-to-pointer, and function-to-pointer + standard conversions are performed. */ + arg = decay_conversion (arg); ++ arg_type = TREE_TYPE (arg); + /* [expr.call] + + If the argument has integral or enumeration type that is subject +@@ -5191,19 +5198,27 @@ + type that is subject to the floating point promotion + (_conv.fpprom_), the value of the argument is converted to the + promoted type before the call. */ +- if (TREE_CODE (TREE_TYPE (arg)) == REAL_TYPE +- && (TYPE_PRECISION (TREE_TYPE (arg)) ++ if (TREE_CODE (arg_type) == REAL_TYPE ++ && (TYPE_PRECISION (arg_type) + < TYPE_PRECISION (double_type_node)) +- && !DECIMAL_FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (arg)))) +- arg = convert_to_real (double_type_node, arg); +- else if (INTEGRAL_OR_ENUMERATION_TYPE_P (TREE_TYPE (arg))) ++ && !DECIMAL_FLOAT_MODE_P (TYPE_MODE (arg_type))) ++ { ++ if (warn_double_promotion && !c_inhibit_evaluation_warnings) ++ warning (OPT_Wdouble_promotion, ++ "implicit conversion from %qT to %qT when passing " ++ "argument to function", ++ arg_type, double_type_node); ++ arg = convert_to_real (double_type_node, arg); ++ } ++ else if (INTEGRAL_OR_ENUMERATION_TYPE_P (arg_type)) + arg = perform_integral_promotions (arg); + + arg = require_complete_type (arg); ++ arg_type = TREE_TYPE (arg); + + if (arg != error_mark_node +- && (type_has_nontrivial_copy_init (TREE_TYPE (arg)) +- || TYPE_HAS_NONTRIVIAL_DESTRUCTOR (TREE_TYPE (arg)))) ++ && (type_has_nontrivial_copy_init (arg_type) ++ || TYPE_HAS_NONTRIVIAL_DESTRUCTOR (arg_type))) + { + /* [expr.call] 5.2.2/7: + Passing a potentially-evaluated argument of class type (Clause 9) +@@ -5218,7 +5233,7 @@ + it is not potentially-evaluated. */ + if (cp_unevaluated_operand == 0) + error ("cannot pass objects of non-trivially-copyable " +- "type %q#T through %<...%>", TREE_TYPE (arg)); ++ "type %q#T through %<...%>", arg_type); + } + + return arg; +--- a/src/gcc/cp/typeck.c ++++ b/src/gcc/cp/typeck.c +@@ -260,6 +260,7 @@ + enum tree_code code2 = TREE_CODE (t2); + tree attributes; + ++ + /* In what follows, we slightly generalize the rules given in [expr] so + as to deal with `long long' and `complex'. First, merge the + attributes. */ +@@ -4226,7 +4227,14 @@ + if (!result_type + && arithmetic_types_p + && (shorten || common || short_compare)) +- result_type = cp_common_type (type0, type1); ++ { ++ result_type = cp_common_type (type0, type1); ++ do_warn_double_promotion (result_type, type0, type1, ++ "implicit conversion from %qT to %qT " ++ "to match other operand of binary " ++ "expression", ++ location); ++ } + + if (!result_type) + { +--- a/src/gcc/cp/typeck2.c ++++ b/src/gcc/cp/typeck2.c +@@ -549,13 +549,15 @@ + expression to which INIT should be assigned. INIT is a CONSTRUCTOR. */ + + static void +-split_nonconstant_init_1 (tree dest, tree init) ++split_nonconstant_init_1 (tree dest, tree *initp) + { + unsigned HOST_WIDE_INT idx; ++ tree init = *initp; + tree field_index, value; + tree type = TREE_TYPE (dest); + tree inner_type = NULL; + bool array_type_p = false; ++ HOST_WIDE_INT num_type_elements, num_initialized_elements; + + switch (TREE_CODE (type)) + { +@@ -567,6 +569,7 @@ + case RECORD_TYPE: + case UNION_TYPE: + case QUAL_UNION_TYPE: ++ num_initialized_elements = 0; + FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (init), idx, + field_index, value) + { +@@ -589,12 +592,13 @@ + sub = build3 (COMPONENT_REF, inner_type, dest, field_index, + NULL_TREE); + +- split_nonconstant_init_1 (sub, value); ++ split_nonconstant_init_1 (sub, &value); + } + else if (!initializer_constant_valid_p (value, inner_type)) + { + tree code; + tree sub; ++ HOST_WIDE_INT inner_elements; + + /* FIXME: Ordered removal is O(1) so the whole function is + worst-case quadratic. This could be fixed using an aside +@@ -617,9 +621,22 @@ + code = build2 (INIT_EXPR, inner_type, sub, value); + code = build_stmt (input_location, EXPR_STMT, code); + add_stmt (code); ++ ++ inner_elements = count_type_elements (inner_type, true); ++ if (inner_elements < 0) ++ num_initialized_elements = -1; ++ else if (num_initialized_elements >= 0) ++ num_initialized_elements += inner_elements; + continue; + } + } ++ ++ num_type_elements = count_type_elements (type, true); ++ /* If all elements of the initializer are non-constant and ++ have been split out, we don't need the empty CONSTRUCTOR. */ ++ if (num_type_elements > 0 ++ && num_type_elements == num_initialized_elements) ++ *initp = NULL; + break; + + case VECTOR_TYPE: +@@ -655,7 +672,7 @@ + if (TREE_CODE (init) == CONSTRUCTOR) + { + code = push_stmt_list (); +- split_nonconstant_init_1 (dest, init); ++ split_nonconstant_init_1 (dest, &init); + code = pop_stmt_list (code); + DECL_INITIAL (dest) = init; + TREE_READONLY (dest) = 0; +--- a/src/gcc/cse.c ++++ b/src/gcc/cse.c +@@ -6061,6 +6061,11 @@ + validate_change (object, &XEXP (x, i), + cse_process_notes (XEXP (x, i), object, changed), 0); + ++ /* Rebuild a PLUS expression in canonical form if the first operand ++ ends up as a constant. */ ++ if (code == PLUS && GET_CODE (XEXP (x, 0)) == CONST_INT) ++ return plus_constant (XEXP(x, 1), INTVAL (XEXP (x, 0))); ++ + return x; + } + +@@ -6629,9 +6634,10 @@ + case CALL_INSN: + case INSN: + case JUMP_INSN: +- /* We expect dest to be NULL_RTX here. If the insn may trap, mark +- this fact by setting DEST to pc_rtx. */ +- if (insn_could_throw_p (x)) ++ /* We expect dest to be NULL_RTX here. If the insn may trap, ++ or if it cannot be deleted due to side-effects, mark this fact ++ by setting DEST to pc_rtx. */ ++ if (insn_could_throw_p (x) || side_effects_p (PATTERN (x))) + dest = pc_rtx; + if (code == CALL_INSN) + count_reg_usage (CALL_INSN_FUNCTION_USAGE (x), counts, dest, incr); +@@ -6671,10 +6677,6 @@ + return; + + case ASM_OPERANDS: +- /* If the asm is volatile, then this insn cannot be deleted, +- and so the inputs *must* be live. */ +- if (MEM_VOLATILE_P (x)) +- dest = NULL_RTX; + /* Iterate over just the inputs, not the constraints as well. */ + for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--) + count_reg_usage (ASM_OPERANDS_INPUT (x, i), counts, dest, incr); +--- a/src/gcc/dbgcnt.def ++++ b/src/gcc/dbgcnt.def +@@ -158,6 +158,7 @@ + DEBUG_COUNTER (global_alloc_at_func) + DEBUG_COUNTER (global_alloc_at_reg) + DEBUG_COUNTER (hoist) ++DEBUG_COUNTER (hoist_insn) + DEBUG_COUNTER (ia64_sched2) + DEBUG_COUNTER (if_conversion) + DEBUG_COUNTER (if_after_combine) +--- a/src/gcc/df-problems.c ++++ b/src/gcc/df-problems.c +@@ -3748,9 +3748,22 @@ + for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++) + { + df_ref def = *def_rec; +- /* If the def is to only part of the reg, it does +- not kill the other defs that reach here. */ +- if (!(DF_REF_FLAGS (def) & (DF_REF_PARTIAL | DF_REF_CONDITIONAL))) ++ bitmap_set_bit (defs, DF_REF_REGNO (def)); ++ } ++} ++ ++/* Find the set of real DEFs, which are not clobbers, for INSN. */ ++ ++void ++df_simulate_find_noclobber_defs (rtx insn, bitmap defs) ++{ ++ df_ref *def_rec; ++ unsigned int uid = INSN_UID (insn); ++ ++ for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++) ++ { ++ df_ref def = *def_rec; ++ if (!(DF_REF_FLAGS (def) & (DF_REF_MUST_CLOBBER | DF_REF_MAY_CLOBBER))) + bitmap_set_bit (defs, DF_REF_REGNO (def)); + } + } +@@ -3921,7 +3934,7 @@ + { + df_ref def = *def_rec; + if (DF_REF_FLAGS (def) & DF_REF_AT_TOP) +- bitmap_clear_bit (live, DF_REF_REGNO (def)); ++ bitmap_set_bit (live, DF_REF_REGNO (def)); + } + } + +@@ -3942,7 +3955,7 @@ + while here the scan is performed forwards! So, first assume that the + def is live, and if this is not true REG_UNUSED notes will rectify the + situation. */ +- df_simulate_find_defs (insn, live); ++ df_simulate_find_noclobber_defs (insn, live); + + /* Clear all of the registers that go dead. */ + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) +--- a/src/gcc/df-scan.c ++++ b/src/gcc/df-scan.c +@@ -3296,6 +3296,7 @@ + } + + case RETURN: ++ case SIMPLE_RETURN: + break; + + case ASM_OPERANDS: +--- a/src/gcc/df.h ++++ b/src/gcc/df.h +@@ -978,6 +978,7 @@ + extern void df_md_add_problem (void); + extern void df_md_simulate_artificial_defs_at_top (basic_block, bitmap); + extern void df_md_simulate_one_insn (basic_block, rtx, bitmap); ++extern void df_simulate_find_noclobber_defs (rtx, bitmap); + extern void df_simulate_find_defs (rtx, bitmap); + extern void df_simulate_defs (rtx, bitmap); + extern void df_simulate_uses (rtx, bitmap); +--- a/src/gcc/doc/sourcebuild.texi.~1~ ++++ b/src/gcc/doc/sourcebuild.texi.~1~ +@@ -0,0 +1,2584 @@ ++@c Copyright (C) 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010 ++@c Free Software Foundation, Inc. ++@c This is part of the GCC manual. ++@c For copying conditions, see the file gcc.texi. ++ ++@node Source Tree ++@chapter Source Tree Structure and Build System ++ ++This chapter describes the structure of the GCC source tree, and how ++GCC is built. The user documentation for building and installing GCC ++is in a separate manual (@uref{http://gcc.gnu.org/install/}), with ++which it is presumed that you are familiar. ++ ++@menu ++* Configure Terms:: Configuration terminology and history. ++* Top Level:: The top level source directory. ++* gcc Directory:: The @file{gcc} subdirectory. ++@end menu ++ ++@include configterms.texi ++ ++@node Top Level ++@section Top Level Source Directory ++ ++The top level source directory in a GCC distribution contains several ++files and directories that are shared with other software ++distributions such as that of GNU Binutils. It also contains several ++subdirectories that contain parts of GCC and its runtime libraries: ++ ++@table @file ++@item boehm-gc ++The Boehm conservative garbage collector, used as part of the Java ++runtime library. ++ ++@item config ++Autoconf macros and Makefile fragments used throughout the tree. ++ ++@item contrib ++Contributed scripts that may be found useful in conjunction with GCC@. ++One of these, @file{contrib/texi2pod.pl}, is used to generate man ++pages from Texinfo manuals as part of the GCC build process. ++ ++@item fixincludes ++The support for fixing system headers to work with GCC@. See ++@file{fixincludes/README} for more information. The headers fixed by ++this mechanism are installed in @file{@var{libsubdir}/include-fixed}. ++Along with those headers, @file{README-fixinc} is also installed, as ++@file{@var{libsubdir}/include-fixed/README}. ++ ++@item gcc ++The main sources of GCC itself (except for runtime libraries), ++including optimizers, support for different target architectures, ++language front ends, and testsuites. @xref{gcc Directory, , The ++@file{gcc} Subdirectory}, for details. ++ ++@item gnattools ++Support tools for GNAT. ++ ++@item include ++Headers for the @code{libiberty} library. ++ ++@item intl ++GNU @code{libintl}, from GNU @code{gettext}, for systems which do not ++include it in @code{libc}. ++ ++@item libada ++The Ada runtime library. ++ ++@item libcpp ++The C preprocessor library. ++ ++@item libdecnumber ++The Decimal Float support library. ++ ++@item libffi ++The @code{libffi} library, used as part of the Java runtime library. ++ ++@item libgcc ++The GCC runtime library. ++ ++@item libgfortran ++The Fortran runtime library. ++ ++@item libgomp ++The GNU OpenMP runtime library. ++ ++@item libiberty ++The @code{libiberty} library, used for portability and for some ++generally useful data structures and algorithms. @xref{Top, , ++Introduction, libiberty, @sc{gnu} libiberty}, for more information ++about this library. ++ ++@item libjava ++The Java runtime library. ++ ++@item libmudflap ++The @code{libmudflap} library, used for instrumenting pointer and array ++dereferencing operations. ++ ++@item libobjc ++The Objective-C and Objective-C++ runtime library. ++ ++@item libssp ++The Stack protector runtime library. ++ ++@item libstdc++-v3 ++The C++ runtime library. ++ ++@item lto-plugin ++Plugin used by @command{gold} if link-time optimizations are enabled. ++ ++@item maintainer-scripts ++Scripts used by the @code{gccadmin} account on @code{gcc.gnu.org}. ++ ++@item zlib ++The @code{zlib} compression library, used by the Java front end, as ++part of the Java runtime library, and for compressing and uncompressing ++GCC's intermediate language in LTO object files. ++@end table ++ ++The build system in the top level directory, including how recursion ++into subdirectories works and how building runtime libraries for ++multilibs is handled, is documented in a separate manual, included ++with GNU Binutils. @xref{Top, , GNU configure and build system, ++configure, The GNU configure and build system}, for details. ++ ++@node gcc Directory ++@section The @file{gcc} Subdirectory ++ ++The @file{gcc} directory contains many files that are part of the C ++sources of GCC, other files used as part of the configuration and ++build process, and subdirectories including documentation and a ++testsuite. The files that are sources of GCC are documented in a ++separate chapter. @xref{Passes, , Passes and Files of the Compiler}. ++ ++@menu ++* Subdirectories:: Subdirectories of @file{gcc}. ++* Configuration:: The configuration process, and the files it uses. ++* Build:: The build system in the @file{gcc} directory. ++* Makefile:: Targets in @file{gcc/Makefile}. ++* Library Files:: Library source files and headers under @file{gcc/}. ++* Headers:: Headers installed by GCC. ++* Documentation:: Building documentation in GCC. ++* Front End:: Anatomy of a language front end. ++* Back End:: Anatomy of a target back end. ++@end menu ++ ++@node Subdirectories ++@subsection Subdirectories of @file{gcc} ++ ++The @file{gcc} directory contains the following subdirectories: ++ ++@table @file ++@item @var{language} ++Subdirectories for various languages. Directories containing a file ++@file{config-lang.in} are language subdirectories. The contents of ++the subdirectories @file{cp} (for C++), @file{lto} (for LTO), ++@file{objc} (for Objective-C) and @file{objcp} (for Objective-C++) are ++documented in this manual (@pxref{Passes, , Passes and Files of the ++Compiler}); those for other languages are not. @xref{Front End, , ++Anatomy of a Language Front End}, for details of the files in these ++directories. ++ ++@item config ++Configuration files for supported architectures and operating ++systems. @xref{Back End, , Anatomy of a Target Back End}, for ++details of the files in this directory. ++ ++@item doc ++Texinfo documentation for GCC, together with automatically generated ++man pages and support for converting the installation manual to ++HTML@. @xref{Documentation}. ++ ++@item ginclude ++System headers installed by GCC, mainly those required by the C ++standard of freestanding implementations. @xref{Headers, , Headers ++Installed by GCC}, for details of when these and other headers are ++installed. ++ ++@item po ++Message catalogs with translations of messages produced by GCC into ++various languages, @file{@var{language}.po}. This directory also ++contains @file{gcc.pot}, the template for these message catalogues, ++@file{exgettext}, a wrapper around @command{gettext} to extract the ++messages from the GCC sources and create @file{gcc.pot}, which is run ++by @samp{make gcc.pot}, and @file{EXCLUDES}, a list of files from ++which messages should not be extracted. ++ ++@item testsuite ++The GCC testsuites (except for those for runtime libraries). ++@xref{Testsuites}. ++@end table ++ ++@node Configuration ++@subsection Configuration in the @file{gcc} Directory ++ ++The @file{gcc} directory is configured with an Autoconf-generated ++script @file{configure}. The @file{configure} script is generated ++from @file{configure.ac} and @file{aclocal.m4}. From the files ++@file{configure.ac} and @file{acconfig.h}, Autoheader generates the ++file @file{config.in}. The file @file{cstamp-h.in} is used as a ++timestamp. ++ ++@menu ++* Config Fragments:: Scripts used by @file{configure}. ++* System Config:: The @file{config.build}, @file{config.host}, and ++ @file{config.gcc} files. ++* Configuration Files:: Files created by running @file{configure}. ++@end menu ++ ++@node Config Fragments ++@subsubsection Scripts Used by @file{configure} ++ ++@file{configure} uses some other scripts to help in its work: ++ ++@itemize @bullet ++@item The standard GNU @file{config.sub} and @file{config.guess} ++files, kept in the top level directory, are used. ++ ++@item The file @file{config.gcc} is used to handle configuration ++specific to the particular target machine. The file ++@file{config.build} is used to handle configuration specific to the ++particular build machine. The file @file{config.host} is used to handle ++configuration specific to the particular host machine. (In general, ++these should only be used for features that cannot reasonably be tested in ++Autoconf feature tests.) ++@xref{System Config, , The @file{config.build}; @file{config.host}; ++and @file{config.gcc} Files}, for details of the contents of these files. ++ ++@item Each language subdirectory has a file ++@file{@var{language}/config-lang.in} that is used for ++front-end-specific configuration. @xref{Front End Config, , The Front ++End @file{config-lang.in} File}, for details of this file. ++ ++@item A helper script @file{configure.frag} is used as part of ++creating the output of @file{configure}. ++@end itemize ++ ++@node System Config ++@subsubsection The @file{config.build}; @file{config.host}; and @file{config.gcc} Files ++ ++The @file{config.build} file contains specific rules for particular systems ++which GCC is built on. This should be used as rarely as possible, as the ++behavior of the build system can always be detected by autoconf. ++ ++The @file{config.host} file contains specific rules for particular systems ++which GCC will run on. This is rarely needed. ++ ++The @file{config.gcc} file contains specific rules for particular systems ++which GCC will generate code for. This is usually needed. ++ ++Each file has a list of the shell variables it sets, with descriptions, at the ++top of the file. ++ ++FIXME: document the contents of these files, and what variables should ++be set to control build, host and target configuration. ++ ++@include configfiles.texi ++ ++@node Build ++@subsection Build System in the @file{gcc} Directory ++ ++FIXME: describe the build system, including what is built in what ++stages. Also list the various source files that are used in the build ++process but aren't source files of GCC itself and so aren't documented ++below (@pxref{Passes}). ++ ++@include makefile.texi ++ ++@node Library Files ++@subsection Library Source Files and Headers under the @file{gcc} Directory ++ ++FIXME: list here, with explanation, all the C source files and headers ++under the @file{gcc} directory that aren't built into the GCC ++executable but rather are part of runtime libraries and object files, ++such as @file{crtstuff.c} and @file{unwind-dw2.c}. @xref{Headers, , ++Headers Installed by GCC}, for more information about the ++@file{ginclude} directory. ++ ++@node Headers ++@subsection Headers Installed by GCC ++ ++In general, GCC expects the system C library to provide most of the ++headers to be used with it. However, GCC will fix those headers if ++necessary to make them work with GCC, and will install some headers ++required of freestanding implementations. These headers are installed ++in @file{@var{libsubdir}/include}. Headers for non-C runtime ++libraries are also installed by GCC; these are not documented here. ++(FIXME: document them somewhere.) ++ ++Several of the headers GCC installs are in the @file{ginclude} ++directory. These headers, @file{iso646.h}, ++@file{stdarg.h}, @file{stdbool.h}, and @file{stddef.h}, ++are installed in @file{@var{libsubdir}/include}, ++unless the target Makefile fragment (@pxref{Target Fragment}) ++overrides this by setting @code{USER_H}. ++ ++In addition to these headers and those generated by fixing system ++headers to work with GCC, some other headers may also be installed in ++@file{@var{libsubdir}/include}. @file{config.gcc} may set ++@code{extra_headers}; this specifies additional headers under ++@file{config} to be installed on some systems. ++ ++GCC installs its own version of @code{}, from @file{ginclude/float.h}. ++This is done to cope with command-line options that change the ++representation of floating point numbers. ++ ++GCC also installs its own version of @code{}; this is generated ++from @file{glimits.h}, together with @file{limitx.h} and ++@file{limity.h} if the system also has its own version of ++@code{}. (GCC provides its own header because it is ++required of ISO C freestanding implementations, but needs to include ++the system header from its own header as well because other standards ++such as POSIX specify additional values to be defined in ++@code{}.) The system's @code{} header is used via ++@file{@var{libsubdir}/include/syslimits.h}, which is copied from ++@file{gsyslimits.h} if it does not need fixing to work with GCC; if it ++needs fixing, @file{syslimits.h} is the fixed copy. ++ ++GCC can also install @code{}. It will do this when ++@file{config.gcc} sets @code{use_gcc_tgmath} to @code{yes}. ++ ++@node Documentation ++@subsection Building Documentation ++ ++The main GCC documentation is in the form of manuals in Texinfo ++format. These are installed in Info format; DVI versions may be ++generated by @samp{make dvi}, PDF versions by @samp{make pdf}, and ++HTML versions by @samp{make html}. In addition, some man pages are ++generated from the Texinfo manuals, there are some other text files ++with miscellaneous documentation, and runtime libraries have their own ++documentation outside the @file{gcc} directory. FIXME: document the ++documentation for runtime libraries somewhere. ++ ++@menu ++* Texinfo Manuals:: GCC manuals in Texinfo format. ++* Man Page Generation:: Generating man pages from Texinfo manuals. ++* Miscellaneous Docs:: Miscellaneous text files with documentation. ++@end menu ++ ++@node Texinfo Manuals ++@subsubsection Texinfo Manuals ++ ++The manuals for GCC as a whole, and the C and C++ front ends, are in ++files @file{doc/*.texi}. Other front ends have their own manuals in ++files @file{@var{language}/*.texi}. Common files ++@file{doc/include/*.texi} are provided which may be included in ++multiple manuals; the following files are in @file{doc/include}: ++ ++@table @file ++@item fdl.texi ++The GNU Free Documentation License. ++@item funding.texi ++The section ``Funding Free Software''. ++@item gcc-common.texi ++Common definitions for manuals. ++@item gpl.texi ++@itemx gpl_v3.texi ++The GNU General Public License. ++@item texinfo.tex ++A copy of @file{texinfo.tex} known to work with the GCC manuals. ++@end table ++ ++DVI-formatted manuals are generated by @samp{make dvi}, which uses ++@command{texi2dvi} (via the Makefile macro @code{$(TEXI2DVI)}). ++PDF-formatted manuals are generated by @samp{make pdf}, which uses ++@command{texi2pdf} (via the Makefile macro @code{$(TEXI2PDF)}). HTML ++formatted manuals are generated by @samp{make html}. Info ++manuals are generated by @samp{make info} (which is run as part of ++a bootstrap); this generates the manuals in the source directory, ++using @command{makeinfo} via the Makefile macro @code{$(MAKEINFO)}, ++and they are included in release distributions. ++ ++Manuals are also provided on the GCC web site, in both HTML and ++PostScript forms. This is done via the script ++@file{maintainer-scripts/update_web_docs}. Each manual to be ++provided online must be listed in the definition of @code{MANUALS} in ++that file; a file @file{@var{name}.texi} must only appear once in the ++source tree, and the output manual must have the same name as the ++source file. (However, other Texinfo files, included in manuals but ++not themselves the root files of manuals, may have names that appear ++more than once in the source tree.) The manual file ++@file{@var{name}.texi} should only include other files in its own ++directory or in @file{doc/include}. HTML manuals will be generated by ++@samp{makeinfo --html}, PostScript manuals by @command{texi2dvi} ++and @command{dvips}, and PDF manuals by @command{texi2pdf}. ++All Texinfo files that are parts of manuals must ++be version-controlled, even if they are generated files, for the ++generation of online manuals to work. ++ ++The installation manual, @file{doc/install.texi}, is also provided on ++the GCC web site. The HTML version is generated by the script ++@file{doc/install.texi2html}. ++ ++@node Man Page Generation ++@subsubsection Man Page Generation ++ ++Because of user demand, in addition to full Texinfo manuals, man pages ++are provided which contain extracts from those manuals. These man ++pages are generated from the Texinfo manuals using ++@file{contrib/texi2pod.pl} and @command{pod2man}. (The man page for ++@command{g++}, @file{cp/g++.1}, just contains a @samp{.so} reference ++to @file{gcc.1}, but all the other man pages are generated from ++Texinfo manuals.) ++ ++Because many systems may not have the necessary tools installed to ++generate the man pages, they are only generated if the ++@file{configure} script detects that recent enough tools are ++installed, and the Makefiles allow generating man pages to fail ++without aborting the build. Man pages are also included in release ++distributions. They are generated in the source directory. ++ ++Magic comments in Texinfo files starting @samp{@@c man} control what ++parts of a Texinfo file go into a man page. Only a subset of Texinfo ++is supported by @file{texi2pod.pl}, and it may be necessary to add ++support for more Texinfo features to this script when generating new ++man pages. To improve the man page output, some special Texinfo ++macros are provided in @file{doc/include/gcc-common.texi} which ++@file{texi2pod.pl} understands: ++ ++@table @code ++@item @@gcctabopt ++Use in the form @samp{@@table @@gcctabopt} for tables of options, ++where for printed output the effect of @samp{@@code} is better than ++that of @samp{@@option} but for man page output a different effect is ++wanted. ++@item @@gccoptlist ++Use for summary lists of options in manuals. ++@item @@gol ++Use at the end of each line inside @samp{@@gccoptlist}. This is ++necessary to avoid problems with differences in how the ++@samp{@@gccoptlist} macro is handled by different Texinfo formatters. ++@end table ++ ++FIXME: describe the @file{texi2pod.pl} input language and magic ++comments in more detail. ++ ++@node Miscellaneous Docs ++@subsubsection Miscellaneous Documentation ++ ++In addition to the formal documentation that is installed by GCC, ++there are several other text files in the @file{gcc} subdirectory ++with miscellaneous documentation: ++ ++@table @file ++@item ABOUT-GCC-NLS ++Notes on GCC's Native Language Support. FIXME: this should be part of ++this manual rather than a separate file. ++@item ABOUT-NLS ++Notes on the Free Translation Project. ++@item COPYING ++@itemx COPYING3 ++The GNU General Public License, Versions 2 and 3. ++@item COPYING.LIB ++@itemx COPYING3.LIB ++The GNU Lesser General Public License, Versions 2.1 and 3. ++@item *ChangeLog* ++@itemx */ChangeLog* ++Change log files for various parts of GCC@. ++@item LANGUAGES ++Details of a few changes to the GCC front-end interface. FIXME: the ++information in this file should be part of general documentation of ++the front-end interface in this manual. ++@item ONEWS ++Information about new features in old versions of GCC@. (For recent ++versions, the information is on the GCC web site.) ++@item README.Portability ++Information about portability issues when writing code in GCC@. FIXME: ++why isn't this part of this manual or of the GCC Coding Conventions? ++@end table ++ ++FIXME: document such files in subdirectories, at least @file{config}, ++@file{cp}, @file{objc}, @file{testsuite}. ++ ++@node Front End ++@subsection Anatomy of a Language Front End ++ ++A front end for a language in GCC has the following parts: ++ ++@itemize @bullet ++@item ++A directory @file{@var{language}} under @file{gcc} containing source ++files for that front end. @xref{Front End Directory, , The Front End ++@file{@var{language}} Directory}, for details. ++@item ++A mention of the language in the list of supported languages in ++@file{gcc/doc/install.texi}. ++@item ++A mention of the name under which the language's runtime library is ++recognized by @option{--enable-shared=@var{package}} in the ++documentation of that option in @file{gcc/doc/install.texi}. ++@item ++A mention of any special prerequisites for building the front end in ++the documentation of prerequisites in @file{gcc/doc/install.texi}. ++@item ++Details of contributors to that front end in ++@file{gcc/doc/contrib.texi}. If the details are in that front end's ++own manual then there should be a link to that manual's list in ++@file{contrib.texi}. ++@item ++Information about support for that language in ++@file{gcc/doc/frontends.texi}. ++@item ++Information about standards for that language, and the front end's ++support for them, in @file{gcc/doc/standards.texi}. This may be a ++link to such information in the front end's own manual. ++@item ++Details of source file suffixes for that language and @option{-x ++@var{lang}} options supported, in @file{gcc/doc/invoke.texi}. ++@item ++Entries in @code{default_compilers} in @file{gcc.c} for source file ++suffixes for that language. ++@item ++Preferably testsuites, which may be under @file{gcc/testsuite} or ++runtime library directories. FIXME: document somewhere how to write ++testsuite harnesses. ++@item ++Probably a runtime library for the language, outside the @file{gcc} ++directory. FIXME: document this further. ++@item ++Details of the directories of any runtime libraries in ++@file{gcc/doc/sourcebuild.texi}. ++@item ++Check targets in @file{Makefile.def} for the top-level @file{Makefile} ++to check just the compiler or the compiler and runtime library for the ++language. ++@end itemize ++ ++If the front end is added to the official GCC source repository, the ++following are also necessary: ++ ++@itemize @bullet ++@item ++At least one Bugzilla component for bugs in that front end and runtime ++libraries. This category needs to be mentioned in ++@file{gcc/gccbug.in}, as well as being added to the Bugzilla database. ++@item ++Normally, one or more maintainers of that front end listed in ++@file{MAINTAINERS}. ++@item ++Mentions on the GCC web site in @file{index.html} and ++@file{frontends.html}, with any relevant links on ++@file{readings.html}. (Front ends that are not an official part of ++GCC may also be listed on @file{frontends.html}, with relevant links.) ++@item ++A news item on @file{index.html}, and possibly an announcement on the ++@email{gcc-announce@@gcc.gnu.org} mailing list. ++@item ++The front end's manuals should be mentioned in ++@file{maintainer-scripts/update_web_docs} (@pxref{Texinfo Manuals}) ++and the online manuals should be linked to from ++@file{onlinedocs/index.html}. ++@item ++Any old releases or CVS repositories of the front end, before its ++inclusion in GCC, should be made available on the GCC FTP site ++@uref{ftp://gcc.gnu.org/pub/gcc/old-releases/}. ++@item ++The release and snapshot script @file{maintainer-scripts/gcc_release} ++should be updated to generate appropriate tarballs for this front end. ++The associated @file{maintainer-scripts/snapshot-README} and ++@file{maintainer-scripts/snapshot-index.html} files should be updated ++to list the tarballs and diffs for this front end. ++@item ++If this front end includes its own version files that include the ++current date, @file{maintainer-scripts/update_version} should be ++updated accordingly. ++@end itemize ++ ++@menu ++* Front End Directory:: The front end @file{@var{language}} directory. ++* Front End Config:: The front end @file{config-lang.in} file. ++* Front End Makefile:: The front end @file{Make-lang.in} file. ++@end menu ++ ++@node Front End Directory ++@subsubsection The Front End @file{@var{language}} Directory ++ ++A front end @file{@var{language}} directory contains the source files ++of that front end (but not of any runtime libraries, which should be ++outside the @file{gcc} directory). This includes documentation, and ++possibly some subsidiary programs built alongside the front end. ++Certain files are special and other parts of the compiler depend on ++their names: ++ ++@table @file ++@item config-lang.in ++This file is required in all language subdirectories. @xref{Front End ++Config, , The Front End @file{config-lang.in} File}, for details of ++its contents ++@item Make-lang.in ++This file is required in all language subdirectories. @xref{Front End ++Makefile, , The Front End @file{Make-lang.in} File}, for details of its ++contents. ++@item lang.opt ++This file registers the set of switches that the front end accepts on ++the command line, and their @option{--help} text. @xref{Options}. ++@item lang-specs.h ++This file provides entries for @code{default_compilers} in ++@file{gcc.c} which override the default of giving an error that a ++compiler for that language is not installed. ++@item @var{language}-tree.def ++This file, which need not exist, defines any language-specific tree ++codes. ++@end table ++ ++@node Front End Config ++@subsubsection The Front End @file{config-lang.in} File ++ ++Each language subdirectory contains a @file{config-lang.in} file. In ++addition the main directory contains @file{c-config-lang.in}, which ++contains limited information for the C language. This file is a shell ++script that may define some variables describing the language: ++ ++@table @code ++@item language ++This definition must be present, and gives the name of the language ++for some purposes such as arguments to @option{--enable-languages}. ++@item lang_requires ++If defined, this variable lists (space-separated) language front ends ++other than C that this front end requires to be enabled (with the ++names given being their @code{language} settings). For example, the ++Java front end depends on the C++ front end, so sets ++@samp{lang_requires=c++}. ++@item subdir_requires ++If defined, this variable lists (space-separated) front end directories ++other than C that this front end requires to be present. For example, ++the Objective-C++ front end uses source files from the C++ and ++Objective-C front ends, so sets @samp{subdir_requires="cp objc"}. ++@item target_libs ++If defined, this variable lists (space-separated) targets in the top ++level @file{Makefile} to build the runtime libraries for this ++language, such as @code{target-libobjc}. ++@item lang_dirs ++If defined, this variable lists (space-separated) top level ++directories (parallel to @file{gcc}), apart from the runtime libraries, ++that should not be configured if this front end is not built. ++@item build_by_default ++If defined to @samp{no}, this language front end is not built unless ++enabled in a @option{--enable-languages} argument. Otherwise, front ++ends are built by default, subject to any special logic in ++@file{configure.ac} (as is present to disable the Ada front end if the ++Ada compiler is not already installed). ++@item boot_language ++If defined to @samp{yes}, this front end is built in stage1 of the ++bootstrap. This is only relevant to front ends written in their own ++languages. ++@item compilers ++If defined, a space-separated list of compiler executables that will ++be run by the driver. The names here will each end ++with @samp{\$(exeext)}. ++@item outputs ++If defined, a space-separated list of files that should be generated ++by @file{configure} substituting values in them. This mechanism can ++be used to create a file @file{@var{language}/Makefile} from ++@file{@var{language}/Makefile.in}, but this is deprecated, building ++everything from the single @file{gcc/Makefile} is preferred. ++@item gtfiles ++If defined, a space-separated list of files that should be scanned by ++@file{gengtype.c} to generate the garbage collection tables and routines for ++this language. This excludes the files that are common to all front ++ends. @xref{Type Information}. ++ ++@end table ++ ++@node Front End Makefile ++@subsubsection The Front End @file{Make-lang.in} File ++ ++Each language subdirectory contains a @file{Make-lang.in} file. It contains ++targets @code{@var{lang}.@var{hook}} (where @code{@var{lang}} is the ++setting of @code{language} in @file{config-lang.in}) for the following ++values of @code{@var{hook}}, and any other Makefile rules required to ++build those targets (which may if necessary use other Makefiles ++specified in @code{outputs} in @file{config-lang.in}, although this is ++deprecated). It also adds any testsuite targets that can use the ++standard rule in @file{gcc/Makefile.in} to the variable ++@code{lang_checks}. ++ ++@table @code ++@itemx all.cross ++@itemx start.encap ++@itemx rest.encap ++FIXME: exactly what goes in each of these targets? ++@item tags ++Build an @command{etags} @file{TAGS} file in the language subdirectory ++in the source tree. ++@item info ++Build info documentation for the front end, in the build directory. ++This target is only called by @samp{make bootstrap} if a suitable ++version of @command{makeinfo} is available, so does not need to check ++for this, and should fail if an error occurs. ++@item dvi ++Build DVI documentation for the front end, in the build directory. ++This should be done using @code{$(TEXI2DVI)}, with appropriate ++@option{-I} arguments pointing to directories of included files. ++@item pdf ++Build PDF documentation for the front end, in the build directory. ++This should be done using @code{$(TEXI2PDF)}, with appropriate ++@option{-I} arguments pointing to directories of included files. ++@item html ++Build HTML documentation for the front end, in the build directory. ++@item man ++Build generated man pages for the front end from Texinfo manuals ++(@pxref{Man Page Generation}), in the build directory. This target ++is only called if the necessary tools are available, but should ignore ++errors so as not to stop the build if errors occur; man pages are ++optional and the tools involved may be installed in a broken way. ++@item install-common ++Install everything that is part of the front end, apart from the ++compiler executables listed in @code{compilers} in ++@file{config-lang.in}. ++@item install-info ++Install info documentation for the front end, if it is present in the ++source directory. This target should have dependencies on info files ++that should be installed. ++@item install-man ++Install man pages for the front end. This target should ignore ++errors. ++@item install-plugin ++Install headers needed for plugins. ++@item srcextra ++Copies its dependencies into the source directory. This generally should ++be used for generated files such as Bison output files which are not ++version-controlled, but should be included in any release tarballs. This ++target will be executed during a bootstrap if ++@samp{--enable-generated-files-in-srcdir} was specified as a ++@file{configure} option. ++@item srcinfo ++@itemx srcman ++Copies its dependencies into the source directory. These targets will be ++executed during a bootstrap if @samp{--enable-generated-files-in-srcdir} ++was specified as a @file{configure} option. ++@item uninstall ++Uninstall files installed by installing the compiler. This is ++currently documented not to be supported, so the hook need not do ++anything. ++@item mostlyclean ++@itemx clean ++@itemx distclean ++@itemx maintainer-clean ++The language parts of the standard GNU ++@samp{*clean} targets. @xref{Standard Targets, , Standard Targets for ++Users, standards, GNU Coding Standards}, for details of the standard ++targets. For GCC, @code{maintainer-clean} should delete ++all generated files in the source directory that are not version-controlled, ++but should not delete anything that is. ++@end table ++ ++@file{Make-lang.in} must also define a variable @code{@var{lang}_OBJS} ++to a list of host object files that are used by that language. ++ ++@node Back End ++@subsection Anatomy of a Target Back End ++ ++A back end for a target architecture in GCC has the following parts: ++ ++@itemize @bullet ++@item ++A directory @file{@var{machine}} under @file{gcc/config}, containing a ++machine description @file{@var{machine}.md} file (@pxref{Machine Desc, ++, Machine Descriptions}), header files @file{@var{machine}.h} and ++@file{@var{machine}-protos.h} and a source file @file{@var{machine}.c} ++(@pxref{Target Macros, , Target Description Macros and Functions}), ++possibly a target Makefile fragment @file{t-@var{machine}} ++(@pxref{Target Fragment, , The Target Makefile Fragment}), and maybe ++some other files. The names of these files may be changed from the ++defaults given by explicit specifications in @file{config.gcc}. ++@item ++If necessary, a file @file{@var{machine}-modes.def} in the ++@file{@var{machine}} directory, containing additional machine modes to ++represent condition codes. @xref{Condition Code}, for further details. ++@item ++An optional @file{@var{machine}.opt} file in the @file{@var{machine}} ++directory, containing a list of target-specific options. You can also ++add other option files using the @code{extra_options} variable in ++@file{config.gcc}. @xref{Options}. ++@item ++Entries in @file{config.gcc} (@pxref{System Config, , The ++@file{config.gcc} File}) for the systems with this target ++architecture. ++@item ++Documentation in @file{gcc/doc/invoke.texi} for any command-line ++options supported by this target (@pxref{Run-time Target, , Run-time ++Target Specification}). This means both entries in the summary table ++of options and details of the individual options. ++@item ++Documentation in @file{gcc/doc/extend.texi} for any target-specific ++attributes supported (@pxref{Target Attributes, , Defining ++target-specific uses of @code{__attribute__}}), including where the ++same attribute is already supported on some targets, which are ++enumerated in the manual. ++@item ++Documentation in @file{gcc/doc/extend.texi} for any target-specific ++pragmas supported. ++@item ++Documentation in @file{gcc/doc/extend.texi} of any target-specific ++built-in functions supported. ++@item ++Documentation in @file{gcc/doc/extend.texi} of any target-specific ++format checking styles supported. ++@item ++Documentation in @file{gcc/doc/md.texi} of any target-specific ++constraint letters (@pxref{Machine Constraints, , Constraints for ++Particular Machines}). ++@item ++A note in @file{gcc/doc/contrib.texi} under the person or people who ++contributed the target support. ++@item ++Entries in @file{gcc/doc/install.texi} for all target triplets ++supported with this target architecture, giving details of any special ++notes about installation for this target, or saying that there are no ++special notes if there are none. ++@item ++Possibly other support outside the @file{gcc} directory for runtime ++libraries. FIXME: reference docs for this. The @code{libstdc++} porting ++manual needs to be installed as info for this to work, or to be a ++chapter of this manual. ++@end itemize ++ ++If the back end is added to the official GCC source repository, the ++following are also necessary: ++ ++@itemize @bullet ++@item ++An entry for the target architecture in @file{readings.html} on the ++GCC web site, with any relevant links. ++@item ++Details of the properties of the back end and target architecture in ++@file{backends.html} on the GCC web site. ++@item ++A news item about the contribution of support for that target ++architecture, in @file{index.html} on the GCC web site. ++@item ++Normally, one or more maintainers of that target listed in ++@file{MAINTAINERS}. Some existing architectures may be unmaintained, ++but it would be unusual to add support for a target that does not have ++a maintainer when support is added. ++@end itemize ++ ++@node Testsuites ++@chapter Testsuites ++ ++GCC contains several testsuites to help maintain compiler quality. ++Most of the runtime libraries and language front ends in GCC have ++testsuites. Currently only the C language testsuites are documented ++here; FIXME: document the others. ++ ++@menu ++* Test Idioms:: Idioms used in testsuite code. ++* Test Directives:: Directives used within DejaGnu tests. ++* Ada Tests:: The Ada language testsuites. ++* C Tests:: The C language testsuites. ++* libgcj Tests:: The Java library testsuites. ++* LTO Testing:: Support for testing link-time optimizations. ++* gcov Testing:: Support for testing gcov. ++* profopt Testing:: Support for testing profile-directed optimizations. ++* compat Testing:: Support for testing binary compatibility. ++* Torture Tests:: Support for torture testing using multiple options. ++@end menu ++ ++@node Test Idioms ++@section Idioms Used in Testsuite Code ++ ++In general, C testcases have a trailing @file{-@var{n}.c}, starting ++with @file{-1.c}, in case other testcases with similar names are added ++later. If the test is a test of some well-defined feature, it should ++have a name referring to that feature such as ++@file{@var{feature}-1.c}. If it does not test a well-defined feature ++but just happens to exercise a bug somewhere in the compiler, and a ++bug report has been filed for this bug in the GCC bug database, ++@file{pr@var{bug-number}-1.c} is the appropriate form of name. ++Otherwise (for miscellaneous bugs not filed in the GCC bug database), ++and previously more generally, test cases are named after the date on ++which they were added. This allows people to tell at a glance whether ++a test failure is because of a recently found bug that has not yet ++been fixed, or whether it may be a regression, but does not give any ++other information about the bug or where discussion of it may be ++found. Some other language testsuites follow similar conventions. ++ ++In the @file{gcc.dg} testsuite, it is often necessary to test that an ++error is indeed a hard error and not just a warning---for example, ++where it is a constraint violation in the C standard, which must ++become an error with @option{-pedantic-errors}. The following idiom, ++where the first line shown is line @var{line} of the file and the line ++that generates the error, is used for this: ++ ++@smallexample ++/* @{ dg-bogus "warning" "warning in place of error" @} */ ++/* @{ dg-error "@var{regexp}" "@var{message}" @{ target *-*-* @} @var{line} @} */ ++@end smallexample ++ ++It may be necessary to check that an expression is an integer constant ++expression and has a certain value. To check that @code{@var{E}} has ++value @code{@var{V}}, an idiom similar to the following is used: ++ ++@smallexample ++char x[((E) == (V) ? 1 : -1)]; ++@end smallexample ++ ++In @file{gcc.dg} tests, @code{__typeof__} is sometimes used to make ++assertions about the types of expressions. See, for example, ++@file{gcc.dg/c99-condexpr-1.c}. The more subtle uses depend on the ++exact rules for the types of conditional expressions in the C ++standard; see, for example, @file{gcc.dg/c99-intconst-1.c}. ++ ++It is useful to be able to test that optimizations are being made ++properly. This cannot be done in all cases, but it can be done where ++the optimization will lead to code being optimized away (for example, ++where flow analysis or alias analysis should show that certain code ++cannot be called) or to functions not being called because they have ++been expanded as built-in functions. Such tests go in ++@file{gcc.c-torture/execute}. Where code should be optimized away, a ++call to a nonexistent function such as @code{link_failure ()} may be ++inserted; a definition ++ ++@smallexample ++#ifndef __OPTIMIZE__ ++void ++link_failure (void) ++@{ ++ abort (); ++@} ++#endif ++@end smallexample ++ ++@noindent ++will also be needed so that linking still succeeds when the test is ++run without optimization. When all calls to a built-in function ++should have been optimized and no calls to the non-built-in version of ++the function should remain, that function may be defined as ++@code{static} to call @code{abort ()} (although redeclaring a function ++as static may not work on all targets). ++ ++All testcases must be portable. Target-specific testcases must have ++appropriate code to avoid causing failures on unsupported systems; ++unfortunately, the mechanisms for this differ by directory. ++ ++FIXME: discuss non-C testsuites here. ++ ++@node Test Directives ++@section Directives used within DejaGnu tests ++ ++@menu ++* Directives:: Syntax and descriptions of test directives. ++* Selectors:: Selecting targets to which a test applies. ++* Effective-Target Keywords:: Keywords describing target attributes. ++* Add Options:: Features for @code{dg-add-options} ++* Require Support:: Variants of @code{dg-require-@var{support}} ++* Final Actions:: Commands for use in @code{dg-final} ++@end menu ++ ++@node Directives ++@subsection Syntax and Descriptions of test directives ++ ++Test directives appear within comments in a test source file and begin ++with @code{dg-}. Some of these are defined within DejaGnu and others ++are local to the GCC testsuite. ++ ++The order in which test directives appear in a test can be important: ++directives local to GCC sometimes override information used by the ++DejaGnu directives, which know nothing about the GCC directives, so the ++DejaGnu directives must precede GCC directives. ++ ++Several test directives include selectors (@pxref{Selectors, , }) ++which are usually preceded by the keyword @code{target} or @code{xfail}. ++ ++@subsubsection Specify how to build the test ++ ++@table @code ++@item @{ dg-do @var{do-what-keyword} [@{ target/xfail @var{selector} @}] @} ++@var{do-what-keyword} specifies how the test is compiled and whether ++it is executed. It is one of: ++ ++@table @code ++@item preprocess ++Compile with @option{-E} to run only the preprocessor. ++@item compile ++Compile with @option{-S} to produce an assembly code file. ++@item assemble ++Compile with @option{-c} to produce a relocatable object file. ++@item link ++Compile, assemble, and link to produce an executable file. ++@item run ++Produce and run an executable file, which is expected to return ++an exit code of 0. ++@end table ++ ++The default is @code{compile}. That can be overridden for a set of ++tests by redefining @code{dg-do-what-default} within the @code{.exp} ++file for those tests. ++ ++If the directive includes the optional @samp{@{ target @var{selector} @}} ++then the test is skipped unless the target system matches the ++@var{selector}. ++ ++If @var{do-what-keyword} is @code{run} and the directive includes ++the optional @samp{@{ xfail @var{selector} @}} and the selector is met ++then the test is expected to fail. The @code{xfail} clause is ignored ++for other values of @var{do-what-keyword}; those tests can use ++directive @code{dg-xfail-if}. ++@end table ++ ++@subsubsection Specify additional compiler options ++ ++@table @code ++@item @{ dg-options @var{options} [@{ target @var{selector} @}] @} ++This DejaGnu directive provides a list of compiler options, to be used ++if the target system matches @var{selector}, that replace the default ++options used for this set of tests. ++ ++@item @{ dg-add-options @var{feature} @dots{} @} ++Add any compiler options that are needed to access certain features. ++This directive does nothing on targets that enable the features by ++default, or that don't provide them at all. It must come after ++all @code{dg-options} directives. ++For supported values of @var{feature} see @ref{Add Options, ,}. ++@end table ++ ++@subsubsection Modify the test timeout value ++ ++The normal timeout limit, in seconds, is found by searching the ++following in order: ++ ++@itemize @bullet ++@item the value defined by an earlier @code{dg-timeout} directive in ++the test ++ ++@item variable @var{tool_timeout} defined by the set of tests ++ ++@item @var{gcc},@var{timeout} set in the target board ++ ++@item 300 ++@end itemize ++ ++@table @code ++@item @{ dg-timeout @var{n} [@{target @var{selector} @}] @} ++Set the time limit for the compilation and for the execution of the test ++to the specified number of seconds. ++ ++@item @{ dg-timeout-factor @var{x} [@{ target @var{selector} @}] @} ++Multiply the normal time limit for compilation and execution of the test ++by the specified floating-point factor. ++@end table ++ ++@subsubsection Skip a test for some targets ++ ++@table @code ++@item @{ dg-skip-if @var{comment} @{ @var{selector} @} [@{ @var{include-opts} @} [@{ @var{exclude-opts} @}]] @} ++Arguments @var{include-opts} and @var{exclude-opts} are lists in which ++each element is a string of zero or more GCC options. ++Skip the test if all of the following conditions are met: ++@itemize @bullet ++@item the test system is included in @var{selector} ++ ++@item for at least one of the option strings in @var{include-opts}, ++every option from that string is in the set of options with which ++the test would be compiled; use @samp{"*"} for an @var{include-opts} list ++that matches any options; that is the default if @var{include-opts} is ++not specified ++ ++@item for each of the option strings in @var{exclude-opts}, at least one ++option from that string is not in the set of options with which the test ++would be compiled; use @samp{""} for an empty @var{exclude-opts} list; ++that is the default if @var{exclude-opts} is not specified ++@end itemize ++ ++For example, to skip a test if option @code{-Os} is present: ++ ++@smallexample ++/* @{ dg-skip-if "" @{ *-*-* @} @{ "-Os" @} @{ "" @} @} */ ++@end smallexample ++ ++To skip a test if both options @code{-O2} and @code{-g} are present: ++ ++@smallexample ++/* @{ dg-skip-if "" @{ *-*-* @} @{ "-O2 -g" @} @{ "" @} @} */ ++@end smallexample ++ ++To skip a test if either @code{-O2} or @code{-O3} is present: ++ ++@smallexample ++/* @{ dg-skip-if "" @{ *-*-* @} @{ "-O2" "-O3" @} @{ "" @} @} */ ++@end smallexample ++ ++To skip a test unless option @code{-Os} is present: ++ ++@smallexample ++/* @{ dg-skip-if "" @{ *-*-* @} @{ "*" @} @{ "-Os" @} @} */ ++@end smallexample ++ ++To skip a test if either @code{-O2} or @code{-O3} is used with @code{-g} ++but not if @code{-fpic} is also present: ++ ++@smallexample ++/* @{ dg-skip-if "" @{ *-*-* @} @{ "-O2 -g" "-O3 -g" @} @{ "-fpic" @} @} */ ++@end smallexample ++ ++@item @{ dg-require-effective-target @var{keyword} [@{ @var{selector} @}] @} ++Skip the test if the test target, including current multilib flags, ++is not covered by the effective-target keyword. ++If the directive includes the optional @samp{@{ @var{selector} @}} ++then the effective-target test is only performed if the target system ++matches the @var{selector}. ++This directive must appear after any @code{dg-do} directive in the test ++and before any @code{dg-additional-sources} directive. ++@xref{Effective-Target Keywords, , }. ++ ++@item @{ dg-require-@var{support} args @} ++Skip the test if the target does not provide the required support. ++These directives must appear after any @code{dg-do} directive in the test ++and before any @code{dg-additional-sources} directive. ++They require at least one argument, which can be an empty string if the ++specific procedure does not examine the argument. ++@xref{Require Support, , }, for a complete list of these directives. ++@end table ++ ++@subsubsection Expect a test to fail for some targets ++ ++@table @code ++@item @{ dg-xfail-if @var{comment} @{ @var{selector} @} [@{ @var{include-opts} @} [@{ @var{exclude-opts} @}]] @} ++Expect the test to fail if the conditions (which are the same as for ++@code{dg-skip-if}) are met. This does not affect the execute step. ++ ++@item @{ dg-xfail-run-if @var{comment} @{ @var{selector} @} [@{ @var{include-opts} @} [@{ @var{exclude-opts} @}]] @} ++Expect the execute step of a test to fail if the conditions (which are ++the same as for @code{dg-skip-if}) are met. ++@end table ++ ++@subsubsection Expect the test executable to fail ++ ++@table @code ++@item @{ dg-shouldfail @var{comment} [@{ @var{selector} @} [@{ @var{include-opts} @} [@{ @var{exclude-opts} @}]]] @} ++Expect the test executable to return a nonzero exit status if the ++conditions (which are the same as for @code{dg-skip-if}) are met. ++@end table ++ ++@subsubsection Verify compiler messages ++ ++@table @code ++@item @{ dg-error @var{regexp} [@var{comment} [@{ target/xfail @var{selector} @} [@var{line}] @}]] @} ++This DejaGnu directive appears on a source line that is expected to get ++an error message, or else specifies the source line associated with the ++message. If there is no message for that line or if the text of that ++message is not matched by @var{regexp} then the check fails and ++@var{comment} is included in the @code{FAIL} message. The check does ++not look for the string @samp{error} unless it is part of @var{regexp}. ++ ++@item @{ dg-warning @var{regexp} [@var{comment} [@{ target/xfail @var{selector} @} [@var{line}] @}]] @} ++This DejaGnu directive appears on a source line that is expected to get ++a warning message, or else specifies the source line associated with the ++message. If there is no message for that line or if the text of that ++message is not matched by @var{regexp} then the check fails and ++@var{comment} is included in the @code{FAIL} message. The check does ++not look for the string @samp{warning} unless it is part of @var{regexp}. ++ ++@item @{ dg-message @var{regexp} [@var{comment} [@{ target/xfail @var{selector} @} [@var{line}] @}]] @} ++The line is expected to get a message other than an error or warning. ++If there is no message for that line or if the text of that message is ++not matched by @var{regexp} then the check fails and @var{comment} is ++included in the @code{FAIL} message. ++ ++@item @{ dg-bogus @var{regexp} [@var{comment} [@{ target/xfail @var{selector} @} [@var{line}] @}]] @} ++This DejaGnu directive appears on a source line that should not get a ++message matching @var{regexp}, or else specifies the source line ++associated with the bogus message. It is usually used with @samp{xfail} ++to indicate that the message is a known problem for a particular set of ++targets. ++ ++@item @{ dg-excess-errors @var{comment} [@{ target/xfail @var{selector} @}] @} ++This DejaGnu directive indicates that the test is expected to fail due ++to compiler messages that are not handled by @samp{dg-error}, ++@samp{dg-warning} or @samp{dg-bogus}. For this directive @samp{xfail} ++has the same effect as @samp{target}. ++ ++@item @{ dg-prune-output @var{regexp} @} ++Prune messages matching @var{regexp} from the test output. ++@end table ++ ++@subsubsection Verify output of the test executable ++ ++@table @code ++@item @{ dg-output @var{regexp} [@{ target/xfail @var{selector} @}] @} ++This DejaGnu directive compares @var{regexp} to the combined output ++that the test executable writes to @file{stdout} and @file{stderr}. ++@end table ++ ++@subsubsection Specify additional files for a test ++ ++@table @code ++@item @{ dg-additional-files "@var{filelist}" @} ++Specify additional files, other than source files, that must be copied ++to the system where the compiler runs. ++ ++@item @{ dg-additional-sources "@var{filelist}" @} ++Specify additional source files to appear in the compile line ++following the main test file. ++@end table ++ ++@subsubsection Add checks at the end of a test ++ ++@table @code ++@item @{ dg-final @{ @var{local-directive} @} @} ++This DejaGnu directive is placed within a comment anywhere in the ++source file and is processed after the test has been compiled and run. ++Multiple @samp{dg-final} commands are processed in the order in which ++they appear in the source file. @xref{Final Actions, , }, for a list ++of directives that can be used within @code{dg-final}. ++@end table ++ ++@node Selectors ++@subsection Selecting targets to which a test applies ++ ++Several test directives include @var{selector}s to limit the targets ++for which a test is run or to declare that a test is expected to fail ++on particular targets. ++ ++A selector is: ++@itemize @bullet ++@item one or more target triplets, possibly including wildcard characters ++@item a single effective-target keyword (@pxref{Effective-Target Keywords}) ++@item a logical expression ++@end itemize ++ ++Depending on the ++context, the selector specifies whether a test is skipped and reported ++as unsupported or is expected to fail. Use @samp{*-*-*} to match any ++target. ++ ++A selector expression appears within curly braces and uses a single ++logical operator: one of @samp{!}, @samp{&&}, or @samp{||}. An ++operand is another selector expression, an effective-target keyword, ++a single target triplet, or a list of target triplets within quotes or ++curly braces. For example: ++ ++@smallexample ++@{ target @{ ! "hppa*-*-* ia64*-*-*" @} @} ++@{ target @{ powerpc*-*-* && lp64 @} @} ++@{ xfail @{ lp64 || vect_no_align @} @} ++@end smallexample ++ ++@node Effective-Target Keywords ++@subsection Keywords describing target attributes ++ ++Effective-target keywords identify sets of targets that support ++particular functionality. They are used to limit tests to be run only ++for particular targets, or to specify that particular sets of targets ++are expected to fail some tests. ++ ++Effective-target keywords are defined in @file{lib/target-supports.exp} in ++the GCC testsuite, with the exception of those that are documented as ++being local to a particular test directory. ++ ++The @samp{effective target} takes into account all of the compiler options ++with which the test will be compiled, including the multilib options. ++By convention, keywords ending in @code{_nocache} can also include options ++specified for the particular test in an earlier @code{dg-options} or ++@code{dg-add-options} directive. ++ ++@subsubsection Data type sizes ++ ++@table @code ++@item ilp32 ++Target has 32-bit @code{int}, @code{long}, and pointers. ++ ++@item lp64 ++Target has 32-bit @code{int}, 64-bit @code{long} and pointers. ++ ++@item llp64 ++Target has 32-bit @code{int} and @code{long}, 64-bit @code{long long} ++and pointers. ++ ++@item double64 ++Target has 64-bit @code{double}. ++ ++@item double64plus ++Target has @code{double} that is 64 bits or longer. ++ ++@item int32plus ++Target has @code{int} that is at 32 bits or longer. ++ ++@item int16 ++Target has @code{int} that is 16 bits or shorter. ++ ++@item large_double ++Target supports @code{double} that is longer than @code{float}. ++ ++@item large_long_double ++Target supports @code{long double} that is longer than @code{double}. ++ ++@item ptr32plus ++Target has pointers that are 32 bits or longer. ++ ++@item size32plus ++Target supports array and structure sizes that are 32 bits or longer. ++ ++@item 4byte_wchar_t ++Target has @code{wchar_t} that is at least 4 bytes. ++@end table ++ ++@subsubsection Fortran-specific attributes ++ ++@table @code ++@item fortran_integer_16 ++Target supports Fortran @code{integer} that is 16 bytes or longer. ++ ++@item fortran_large_int ++Target supports Fortran @code{integer} kinds larger than @code{integer(8)}. ++ ++@item fortran_large_real ++Target supports Fortran @code{real} kinds larger than @code{real(8)}. ++@end table ++ ++@subsubsection Vector-specific attributes ++ ++@table @code ++@item vect_condition ++Target supports vector conditional operations. ++ ++@item vect_double ++Target supports hardware vectors of @code{double}. ++ ++@item vect_float ++Target supports hardware vectors of @code{float}. ++ ++@item vect_int ++Target supports hardware vectors of @code{int}. ++ ++@item vect_int_mult ++Target supports a vector widening multiplication of @code{short} operands ++into an @code{int} result, or supports promotion (unpacking) from ++@code{short} to @code{int} and a non-widening multiplication of @code{int}. ++ ++@item vect_long ++Target supports hardware vectors of @code{long}. ++ ++@item vect_long_long ++Target supports hardware vectors of @code{long long}. ++ ++@item vect_aligned_arrays ++Target aligns arrays to vector alignment boundary. ++ ++@item vect_hw_misalign ++Target supports a vector misalign access. ++ ++@item vect_no_align ++Target does not support a vector alignment mechanism. ++ ++@item vect_no_int_max ++Target does not support a vector max instruction on @code{int}. ++ ++@item vect_no_int_add ++Target does not support a vector add instruction on @code{int}. ++ ++@item vect_no_bitwise ++Target does not support vector bitwise instructions. ++ ++@item vect_char_mult ++Target supports @code{vector char} multiplication. ++ ++@item vect_short_mult ++Target supports @code{vector short} multiplication. ++ ++@item vect_int_mult ++Target supports @code{vector int} multiplication. ++ ++@item vect_extract_even_odd ++Target supports vector even/odd element extraction. ++ ++@item vect_extract_even_odd_wide ++Target supports vector even/odd element extraction of vectors with elements ++@code{SImode} or larger. ++ ++@item vect_interleave ++Target supports vector interleaving. ++ ++@item vect_strided ++Target supports vector interleaving and extract even/odd. ++ ++@item vect_strided_wide ++Target supports vector interleaving and extract even/odd for wide ++element types. ++ ++@item vect_perm ++Target supports vector permutation. ++ ++@item vect_shift ++Target supports a hardware vector shift operation. ++ ++@item vect_widen_sum_hi_to_si ++Target supports a vector widening summation of @code{short} operands ++into @code{int} results, or can promote (unpack) from @code{short} ++to @code{int}. ++ ++@item vect_widen_sum_qi_to_hi ++Target supports a vector widening summation of @code{char} operands ++into @code{short} results, or can promote (unpack) from @code{char} ++to @code{short}. ++ ++@item vect_widen_sum_qi_to_si ++Target supports a vector widening summation of @code{char} operands ++into @code{int} results. ++ ++@item vect_widen_mult_qi_to_hi ++Target supports a vector widening multiplication of @code{char} operands ++into @code{short} results, or can promote (unpack) from @code{char} to ++@code{short} and perform non-widening multiplication of @code{short}. ++ ++@item vect_widen_mult_hi_to_si ++Target supports a vector widening multiplication of @code{short} operands ++into @code{int} results, or can promote (unpack) from @code{short} to ++@code{int} and perform non-widening multiplication of @code{int}. ++ ++@item vect_sdot_qi ++Target supports a vector dot-product of @code{signed char}. ++ ++@item vect_udot_qi ++Target supports a vector dot-product of @code{unsigned char}. ++ ++@item vect_sdot_hi ++Target supports a vector dot-product of @code{signed short}. ++ ++@item vect_udot_hi ++Target supports a vector dot-product of @code{unsigned short}. ++ ++@item vect_pack_trunc ++Target supports a vector demotion (packing) of @code{short} to @code{char} ++and from @code{int} to @code{short} using modulo arithmetic. ++ ++@item vect_unpack ++Target supports a vector promotion (unpacking) of @code{char} to @code{short} ++and from @code{char} to @code{int}. ++ ++@item vect_intfloat_cvt ++Target supports conversion from @code{signed int} to @code{float}. ++ ++@item vect_uintfloat_cvt ++Target supports conversion from @code{unsigned int} to @code{float}. ++ ++@item vect_floatint_cvt ++Target supports conversion from @code{float} to @code{signed int}. ++ ++@item vect_floatuint_cvt ++Target supports conversion from @code{float} to @code{unsigned int}. ++@end table ++ ++@subsubsection Thread Local Storage attributes ++ ++@table @code ++@item tls ++Target supports thread-local storage. ++ ++@item tls_native ++Target supports native (rather than emulated) thread-local storage. ++ ++@item tls_runtime ++Test system supports executing TLS executables. ++@end table ++ ++@subsubsection Decimal floating point attributes ++ ++@table @code ++@item dfp ++Targets supports compiling decimal floating point extension to C. ++ ++@item dfp_nocache ++Including the options used to compile this particular test, the ++target supports compiling decimal floating point extension to C. ++ ++@item dfprt ++Test system can execute decimal floating point tests. ++ ++@item dfprt_nocache ++Including the options used to compile this particular test, the ++test system can execute decimal floating point tests. ++ ++@item hard_dfp ++Target generates decimal floating point instructions with current options. ++@end table ++ ++@subsubsection ARM-specific attributes ++ ++@table @code ++@item arm32 ++ARM target generates 32-bit code. ++ ++@item arm_eabi ++ARM target adheres to the ABI for the ARM Architecture. ++ ++@item arm_hard_vfp_ok ++ARM target supports @code{-mfpu=vfp -mfloat-abi=hard}. ++Some multilibs may be incompatible with these options. ++ ++@item arm_iwmmxt_ok ++ARM target supports @code{-mcpu=iwmmxt}. ++Some multilibs may be incompatible with this option. ++ ++@item arm_neon ++ARM target supports generating NEON instructions. ++ ++@item arm_neon_hw ++Test system supports executing NEON instructions. ++ ++@item arm_neon_ok ++@anchor{arm_neon_ok} ++ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp} or compatible ++options. Some multilibs may be incompatible with these options. ++ ++@item arm_neon_fp16_ok ++@anchor{arm_neon_fp16_ok} ++ARM Target supports @code{-mfpu=neon-fp16 -mfloat-abi=softfp} or compatible ++options. Some multilibs may be incompatible with these options. ++ ++@item arm_thumb1_ok ++ARM target generates Thumb-1 code for @code{-mthumb}. ++ ++@item arm_thumb2_ok ++ARM target generates Thumb-2 code for @code{-mthumb}. ++ ++@item arm_vfp_ok ++ARM target supports @code{-mfpu=vfp -mfloat-abi=softfp}. ++Some multilibs may be incompatible with these options. ++@end table ++ ++@subsubsection MIPS-specific attributes ++ ++@table @code ++@item mips64 ++MIPS target supports 64-bit instructions. ++ ++@item nomips16 ++MIPS target does not produce MIPS16 code. ++ ++@item mips16_attribute ++MIPS target can generate MIPS16 code. ++ ++@item mips_loongson ++MIPS target is a Loongson-2E or -2F target using an ABI that supports ++the Loongson vector modes. ++ ++@item mips_newabi_large_long_double ++MIPS target supports @code{long double} larger than @code{double} ++when using the new ABI. ++ ++@item mpaired_single ++MIPS target supports @code{-mpaired-single}. ++@end table ++ ++@subsubsection PowerPC-specific attributes ++ ++@table @code ++@item powerpc64 ++Test system supports executing 64-bit instructions. ++ ++@item powerpc_altivec ++PowerPC target supports AltiVec. ++ ++@item powerpc_altivec_ok ++PowerPC target supports @code{-maltivec}. ++ ++@item powerpc_fprs ++PowerPC target supports floating-point registers. ++ ++@item powerpc_hard_double ++PowerPC target supports hardware double-precision floating-point. ++ ++@item powerpc_ppu_ok ++PowerPC target supports @code{-mcpu=cell}. ++ ++@item powerpc_spe ++PowerPC target supports PowerPC SPE. ++ ++@item powerpc_spe_nocache ++Including the options used to compile this particular test, the ++PowerPC target supports PowerPC SPE. ++ ++@item powerpc_spu ++PowerPC target supports PowerPC SPU. ++ ++@item spu_auto_overlay ++SPU target has toolchain that supports automatic overlay generation. ++ ++@item powerpc_vsx_ok ++PowerPC target supports @code{-mvsx}. ++ ++@item powerpc_405_nocache ++Including the options used to compile this particular test, the ++PowerPC target supports PowerPC 405. ++ ++@item vmx_hw ++PowerPC target supports executing AltiVec instructions. ++@end table ++ ++@subsubsection Other hardware attributes ++ ++@table @code ++@item avx ++Target supports compiling AVX instructions. ++ ++@item cell_hw ++Test system can execute AltiVec and Cell PPU instructions. ++ ++@item coldfire_fpu ++Target uses a ColdFire FPU. ++ ++@item hard_float ++Target supports FPU instructions. ++ ++@item sse ++Target supports compiling @code{sse} instructions. ++ ++@item sse_runtime ++Target supports the execution of @code{sse} instructions. ++ ++@item sse2 ++Target supports compiling @code{sse2} instructions. ++ ++@item sse2_runtime ++Target supports the execution of @code{sse2} instructions. ++ ++@item sync_char_short ++Target supports atomic operations on @code{char} and @code{short}. ++ ++@item sync_int_long ++Target supports atomic operations on @code{int} and @code{long}. ++ ++@item ultrasparc_hw ++Test environment appears to run executables on a simulator that ++accepts only @code{EM_SPARC} executables and chokes on @code{EM_SPARC32PLUS} ++or @code{EM_SPARCV9} executables. ++ ++@item vect_cmdline_needed ++Target requires a command line argument to enable a SIMD instruction set. ++@end table ++ ++@subsubsection Environment attributes ++ ++@table @code ++@item c ++The language for the compiler under test is C. ++ ++@item c++ ++The language for the compiler under test is C++. ++ ++@item c99_runtime ++Target provides a full C99 runtime. ++ ++@item correct_iso_cpp_string_wchar_protos ++Target @code{string.h} and @code{wchar.h} headers provide C++ required ++overloads for @code{strchr} etc. functions. ++ ++@item dummy_wcsftime ++Target uses a dummy @code{wcsftime} function that always returns zero. ++ ++@item fd_truncate ++Target can truncate a file from a file descriptor, as used by ++@file{libgfortran/io/unix.c:fd_truncate}; i.e. @code{ftruncate} or ++@code{chsize}. ++ ++@item freestanding ++Target is @samp{freestanding} as defined in section 4 of the C99 standard. ++Effectively, it is a target which supports no extra headers or libraries ++other than what is considered essential. ++ ++@item init_priority ++Target supports constructors with initialization priority arguments. ++ ++@item inttypes_types ++Target has the basic signed and unsigned types in @code{inttypes.h}. ++This is for tests that GCC's notions of these types agree with those ++in the header, as some systems have only @code{inttypes.h}. ++ ++@item lax_strtofp ++Target might have errors of a few ULP in string to floating-point ++conversion functions and overflow is not always detected correctly by ++those functions. ++ ++@item newlib ++Target supports Newlib. ++ ++@item pow10 ++Target provides @code{pow10} function. ++ ++@item pthread ++Target can compile using @code{pthread.h} with no errors or warnings. ++ ++@item pthread_h ++Target has @code{pthread.h}. ++ ++@item run_expensive_tests ++Expensive testcases (usually those that consume excessive amounts of CPU ++time) should be run on this target. This can be enabled by setting the ++@env{GCC_TEST_RUN_EXPENSIVE} environment variable to a non-empty string. ++ ++@item simulator ++Test system runs executables on a simulator (i.e. slowly) rather than ++hardware (i.e. fast). ++ ++@item stdint_types ++Target has the basic signed and unsigned C types in @code{stdint.h}. ++This will be obsolete when GCC ensures a working @code{stdint.h} for ++all targets. ++ ++@item trampolines ++Target supports trampolines. ++ ++@item uclibc ++Target supports uClibc. ++ ++@item unwrapped ++Target does not use a status wrapper. ++ ++@item vxworks_kernel ++Target is a VxWorks kernel. ++ ++@item vxworks_rtp ++Target is a VxWorks RTP. ++ ++@item wchar ++Target supports wide characters. ++@end table ++ ++@subsubsection Other attributes ++ ++@table @code ++@item automatic_stack_alignment ++Target supports automatic stack alignment. ++ ++@item cxa_atexit ++Target uses @code{__cxa_atexit}. ++ ++@item default_packed ++Target has packed layout of structure members by default. ++ ++@item fgraphite ++Target supports Graphite optimizations. ++ ++@item fixed_point ++Target supports fixed-point extension to C. ++ ++@item fopenmp ++Target supports OpenMP via @option{-fopenmp}. ++ ++@item fpic ++Target supports @option{-fpic} and @option{-fPIC}. ++ ++@item freorder ++Target supports @option{-freorder-blocks-and-partition}. ++ ++@item fstack_protector ++Target supports @option{-fstack-protector}. ++ ++@item gas ++Target uses GNU @command{as}. ++ ++@item gc_sections ++Target supports @option{--gc-sections}. ++ ++@item keeps_null_pointer_checks ++Target keeps null pointer checks, either due to the use of ++@option{-fno-delete-null-pointer-checks} or hardwired into the target. ++ ++@item lto ++Compiler has been configured to support link-time optimization (LTO). ++ ++@item named_sections ++Target supports named sections. ++ ++@item natural_alignment_32 ++Target uses natural alignment (aligned to type size) for types of ++32 bits or less. ++ ++@item target_natural_alignment_64 ++Target uses natural alignment (aligned to type size) for types of ++64 bits or less. ++ ++@item nonpic ++Target does not generate PIC by default. ++ ++@item pcc_bitfield_type_matters ++Target defines @code{PCC_BITFIELD_TYPE_MATTERS}. ++ ++@item pe_aligned_commons ++Target supports @option{-mpe-aligned-commons}. ++ ++@item section_anchors ++Target supports section anchors. ++ ++@item short_enums ++Target defaults to short enums. ++ ++@item static ++Target supports @option{-static}. ++ ++@item static_libgfortran ++Target supports statically linking @samp{libgfortran}. ++ ++@item string_merging ++Target supports merging string constants at link time. ++ ++@item ucn ++Target supports compiling and assembling UCN. ++ ++@item ucn_nocache ++Including the options used to compile this particular test, the ++target supports compiling and assembling UCN. ++ ++@item unaligned_stack ++Target does not guarantee that its @code{STACK_BOUNDARY} is greater than ++or equal to the required vector alignment. ++ ++@item vector_alignment_reachable ++Vector alignment is reachable for types of 32 bits or less. ++ ++@item vector_alignment_reachable_for_64bit ++Vector alignment is reachable for types of 64 bits or less. ++ ++@item wchar_t_char16_t_compatible ++Target supports @code{wchar_t} that is compatible with @code{char16_t}. ++ ++@item wchar_t_char32_t_compatible ++Target supports @code{wchar_t} that is compatible with @code{char32_t}. ++@end table ++ ++@subsubsection Local to tests in @code{gcc.target/i386} ++ ++@table @code ++@item 3dnow ++Target supports compiling @code{3dnow} instructions. ++ ++@item aes ++Target supports compiling @code{aes} instructions. ++ ++@item fma4 ++Target supports compiling @code{fma4} instructions. ++ ++@item ms_hook_prologue ++Target supports attribute @code{ms_hook_prologue}. ++ ++@item pclmul ++Target supports compiling @code{pclmul} instructions. ++ ++@item sse3 ++Target supports compiling @code{sse3} instructions. ++ ++@item sse4 ++Target supports compiling @code{sse4} instructions. ++ ++@item sse4a ++Target supports compiling @code{sse4a} instructions. ++ ++@item ssse3 ++Target supports compiling @code{ssse3} instructions. ++ ++@item vaes ++Target supports compiling @code{vaes} instructions. ++ ++@item vpclmul ++Target supports compiling @code{vpclmul} instructions. ++ ++@item xop ++Target supports compiling @code{xop} instructions. ++@end table ++ ++@subsubsection Local to tests in @code{gcc.target/spu/ea} ++ ++@table @code ++@item ealib ++Target @code{__ea} library functions are available. ++@end table ++ ++@subsubsection Local to tests in @code{gcc.test-framework} ++ ++@table @code ++@item no ++Always returns 0. ++ ++@item yes ++Always returns 1. ++@end table ++ ++@node Add Options ++@subsection Features for @code{dg-add-options} ++ ++The supported values of @var{feature} for directive @code{dg-add-options} ++are: ++ ++@table @code ++@item bind_pic_locally ++Add the target-specific flags needed to enable functions to bind ++locally when using pic/PIC passes in the testsuite. ++ ++@item c99_runtime ++Add the target-specific flags needed to access the C99 runtime. ++ ++@item ieee ++Add the target-specific flags needed to enable full IEEE ++compliance mode. ++ ++@item mips16_attribute ++@code{mips16} function attributes. ++Only MIPS targets support this feature, and only then in certain modes. ++ ++@item tls ++Add the target-specific flags needed to use thread-local storage. ++ ++@item arm_neon ++NEON support. Only ARM targets support this feature, and only then ++in certain modes; see the @ref{arm_neon_ok,,arm_neon_ok effective target ++keyword}. ++ ++@item arm_neon_fp16 ++NEON and half-precision floating point support. Only ARM targets ++support this feature, and only then in certain modes; see ++the @ref{arm_neon_ok,,arm_neon_fp16_ok effective target keyword}. ++ ++@item tls ++Add the target-specific flags needed to use thread-local storage. ++@end table ++ ++@node Require Support ++@subsection Variants of @code{dg-require-@var{support}} ++ ++A few of the @code{dg-require} directives take arguments. ++ ++@table @code ++@item dg-require-iconv @var{codeset} ++Skip the test if the target does not support iconv. @var{codeset} is ++the codeset to convert to. ++ ++@item dg-require-profiling @var{profopt} ++Skip the test if the target does not support profiling with option ++@var{profopt}. ++ ++@item dg-require-visibility @var{vis} ++Skip the test if the target does not support the @code{visibility} attribute. ++If @var{vis} is @code{""}, support for @code{visibility("hidden")} is ++checked, for @code{visibility("@var{vis}")} otherwise. ++@end table ++ ++The original @code{dg-require} directives were defined before there ++was support for effective-target keywords. The directives that do not ++take arguments could be replaced with effective-target keywords. ++ ++@table @code ++@item dg-require-alias "" ++Skip the test if the target does not support the @samp{alias} attribute. ++ ++@item dg-require-compat-dfp "" ++Skip this test unless both compilers in a @file{compat} testsuite ++support decimal floating point. ++ ++@item dg-require-cxa-atexit "" ++Skip the test if the target does not support @code{__cxa_atexit}. ++This is equivalent to @code{dg-require-effective-target cxa_atexit}. ++ ++@item dg-require-dll "" ++Skip the test if the target does not support DLL attributes. ++ ++@item dg-require-fork "" ++Skip the test if the target does not support @code{fork}. ++ ++@item dg-require-gc-sections "" ++Skip the test if the target's linker does not support the ++@code{--gc-sections} flags. ++This is equivalent to @code{dg-require-effective-target gc-sections}. ++ ++@item dg-require-host-local "" ++Skip the test if the host is remote, rather than the same as the build ++system. Some tests are incompatible with DejaGnu's handling of remote ++hosts, which involves copying the source file to the host and compiling ++it with a relative path and "@code{-o a.out}". ++ ++@item dg-require-mkfifo "" ++Skip the test if the target does not support @code{mkfifo}. ++ ++@item dg-require-named-sections "" ++Skip the test is the target does not support named sections. ++This is equivalent to @code{dg-require-effective-target named_sections}. ++ ++@item dg-require-weak "" ++Skip the test if the target does not support weak symbols. ++ ++@item dg-require-weak-override "" ++Skip the test if the target does not support overriding weak symbols. ++@end table ++ ++@node Final Actions ++@subsection Commands for use in @code{dg-final} ++ ++The GCC testsuite defines the following directives to be used within ++@code{dg-final}. ++ ++@subsubsection Scan a particular file ++ ++@table @code ++@item scan-file @var{filename} @var{regexp} [@{ target/xfail @var{selector} @}] ++Passes if @var{regexp} matches text in @var{filename}. ++@item scan-file-not @var{filename} @var{regexp} [@{ target/xfail @var{selector} @}] ++Passes if @var{regexp} does not match text in @var{filename}. ++@item scan-module @var{module} @var{regexp} [@{ target/xfail @var{selector} @}] ++Passes if @var{regexp} matches in Fortran module @var{module}. ++@end table ++ ++@subsubsection Scan the assembly output ++ ++@table @code ++@item scan-assembler @var{regex} [@{ target/xfail @var{selector} @}] ++Passes if @var{regex} matches text in the test's assembler output. ++ ++@item scan-assembler-not @var{regex} [@{ target/xfail @var{selector} @}] ++Passes if @var{regex} does not match text in the test's assembler output. ++ ++@item scan-assembler-times @var{regex} @var{num} [@{ target/xfail @var{selector} @}] ++Passes if @var{regex} is matched exactly @var{num} times in the test's ++assembler output. ++ ++@item scan-assembler-dem @var{regex} [@{ target/xfail @var{selector} @}] ++Passes if @var{regex} matches text in the test's demangled assembler output. ++ ++@item scan-assembler-dem-not @var{regex} [@{ target/xfail @var{selector} @}] ++Passes if @var{regex} does not match text in the test's demangled assembler ++output. ++ ++@item scan-hidden @var{symbol} [@{ target/xfail @var{selector} @}] ++Passes if @var{symbol} is defined as a hidden symbol in the test's ++assembly output. ++ ++@item scan-not-hidden @var{symbol} [@{ target/xfail @var{selector} @}] ++Passes if @var{symbol} is not defined as a hidden symbol in the test's ++assembly output. ++@end table ++ ++@subsubsection Scan optimization dump files ++ ++These commands are available for @var{kind} of @code{tree}, @code{rtl}, ++and @code{ipa}. ++ ++@table @code ++@item scan-@var{kind}-dump @var{regex} @var{suffix} [@{ target/xfail @var{selector} @}] ++Passes if @var{regex} matches text in the dump file with suffix @var{suffix}. ++ ++@item scan-@var{kind}-dump-not @var{regex} @var{suffix} [@{ target/xfail @var{selector} @}] ++Passes if @var{regex} does not match text in the dump file with suffix ++@var{suffix}. ++ ++@item scan-@var{kind}-dump-times @var{regex} @var{num} @var{suffix} [@{ target/xfail @var{selector} @}] ++Passes if @var{regex} is found exactly @var{num} times in the dump file ++with suffix @var{suffix}. ++ ++@item scan-@var{kind}-dump-dem @var{regex} @var{suffix} [@{ target/xfail @var{selector} @}] ++Passes if @var{regex} matches demangled text in the dump file with ++suffix @var{suffix}. ++ ++@item scan-@var{kind}-dump-dem-not @var{regex} @var{suffix} [@{ target/xfail @var{selector} @}] ++Passes if @var{regex} does not match demangled text in the dump file with ++suffix @var{suffix}. ++@end table ++ ++@subsubsection Verify that an output files exists or not ++ ++@table @code ++@item output-exists [@{ target/xfail @var{selector} @}] ++Passes if compiler output file exists. ++ ++@item output-exists-not [@{ target/xfail @var{selector} @}] ++Passes if compiler output file does not exist. ++@end table ++ ++@subsubsection Check for LTO tests ++ ++@table @code ++@item scan-symbol @var{regexp} [@{ target/xfail @var{selector} @}] ++Passes if the pattern is present in the final executable. ++@end table ++ ++@subsubsection Checks for @command{gcov} tests ++ ++@table @code ++@item run-gcov @var{sourcefile} ++Check line counts in @command{gcov} tests. ++ ++@item run-gcov [branches] [calls] @{ @var{opts} @var{sourcefile} @} ++Check branch and/or call counts, in addition to line counts, in ++@command{gcov} tests. ++@end table ++ ++@subsubsection Clean up generated test files ++ ++@table @code ++@item cleanup-coverage-files ++Removes coverage data files generated for this test. ++ ++@item cleanup-ipa-dump @var{suffix} ++Removes IPA dump files generated for this test. ++ ++@item cleanup-modules ++Removes Fortran module files generated for this test. ++ ++@item cleanup-profile-file ++Removes profiling files generated for this test. ++ ++@item cleanup-repo-files ++Removes files generated for this test for @option{-frepo}. ++ ++@item cleanup-rtl-dump @var{suffix} ++Removes RTL dump files generated for this test. ++ ++@item cleanup-saved-temps ++Removes files for the current test which were kept for @option{-save-temps}. ++ ++@item cleanup-tree-dump @var{suffix} ++Removes tree dump files matching @var{suffix} which were generated for ++this test. ++@end table ++ ++@node Ada Tests ++@section Ada Language Testsuites ++ ++The Ada testsuite includes executable tests from the ACATS 2.5 ++testsuite, publicly available at ++@uref{http://www.adaic.org/compilers/acats/2.5}. ++ ++These tests are integrated in the GCC testsuite in the ++@file{ada/acats} directory, and ++enabled automatically when running @code{make check}, assuming ++the Ada language has been enabled when configuring GCC@. ++ ++You can also run the Ada testsuite independently, using ++@code{make check-ada}, or run a subset of the tests by specifying which ++chapter to run, e.g.: ++ ++@smallexample ++$ make check-ada CHAPTERS="c3 c9" ++@end smallexample ++ ++The tests are organized by directory, each directory corresponding to ++a chapter of the Ada Reference Manual. So for example, @file{c9} corresponds ++to chapter 9, which deals with tasking features of the language. ++ ++There is also an extra chapter called @file{gcc} containing a template for ++creating new executable tests, although this is deprecated in favor of ++the @file{gnat.dg} testsuite. ++ ++The tests are run using two @command{sh} scripts: @file{run_acats} and ++@file{run_all.sh}. To run the tests using a simulator or a cross ++target, see the small ++customization section at the top of @file{run_all.sh}. ++ ++These tests are run using the build tree: they can be run without doing ++a @code{make install}. ++ ++@node C Tests ++@section C Language Testsuites ++ ++GCC contains the following C language testsuites, in the ++@file{gcc/testsuite} directory: ++ ++@table @file ++@item gcc.dg ++This contains tests of particular features of the C compiler, using the ++more modern @samp{dg} harness. Correctness tests for various compiler ++features should go here if possible. ++ ++Magic comments determine whether the file ++is preprocessed, compiled, linked or run. In these tests, error and warning ++message texts are compared against expected texts or regular expressions ++given in comments. These tests are run with the options @samp{-ansi -pedantic} ++unless other options are given in the test. Except as noted below they ++are not run with multiple optimization options. ++@item gcc.dg/compat ++This subdirectory contains tests for binary compatibility using ++@file{lib/compat.exp}, which in turn uses the language-independent support ++(@pxref{compat Testing, , Support for testing binary compatibility}). ++@item gcc.dg/cpp ++This subdirectory contains tests of the preprocessor. ++@item gcc.dg/debug ++This subdirectory contains tests for debug formats. Tests in this ++subdirectory are run for each debug format that the compiler supports. ++@item gcc.dg/format ++This subdirectory contains tests of the @option{-Wformat} format ++checking. Tests in this directory are run with and without ++@option{-DWIDE}. ++@item gcc.dg/noncompile ++This subdirectory contains tests of code that should not compile and ++does not need any special compilation options. They are run with ++multiple optimization options, since sometimes invalid code crashes ++the compiler with optimization. ++@item gcc.dg/special ++FIXME: describe this. ++ ++@item gcc.c-torture ++This contains particular code fragments which have historically broken easily. ++These tests are run with multiple optimization options, so tests for features ++which only break at some optimization levels belong here. This also contains ++tests to check that certain optimizations occur. It might be worthwhile to ++separate the correctness tests cleanly from the code quality tests, but ++it hasn't been done yet. ++ ++@item gcc.c-torture/compat ++FIXME: describe this. ++ ++This directory should probably not be used for new tests. ++@item gcc.c-torture/compile ++This testsuite contains test cases that should compile, but do not ++need to link or run. These test cases are compiled with several ++different combinations of optimization options. All warnings are ++disabled for these test cases, so this directory is not suitable if ++you wish to test for the presence or absence of compiler warnings. ++While special options can be set, and tests disabled on specific ++platforms, by the use of @file{.x} files, mostly these test cases ++should not contain platform dependencies. FIXME: discuss how defines ++such as @code{NO_LABEL_VALUES} and @code{STACK_SIZE} are used. ++@item gcc.c-torture/execute ++This testsuite contains test cases that should compile, link and run; ++otherwise the same comments as for @file{gcc.c-torture/compile} apply. ++@item gcc.c-torture/execute/ieee ++This contains tests which are specific to IEEE floating point. ++@item gcc.c-torture/unsorted ++FIXME: describe this. ++ ++This directory should probably not be used for new tests. ++@item gcc.misc-tests ++This directory contains C tests that require special handling. Some ++of these tests have individual expect files, and others share ++special-purpose expect files: ++ ++@table @file ++@item @code{bprob*.c} ++Test @option{-fbranch-probabilities} using ++@file{gcc.misc-tests/bprob.exp}, which ++in turn uses the generic, language-independent framework ++(@pxref{profopt Testing, , Support for testing profile-directed ++optimizations}). ++ ++@item @code{gcov*.c} ++Test @command{gcov} output using @file{gcov.exp}, which in turn uses the ++language-independent support (@pxref{gcov Testing, , Support for testing gcov}). ++ ++@item @code{i386-pf-*.c} ++Test i386-specific support for data prefetch using @file{i386-prefetch.exp}. ++@end table ++ ++@item gcc.test-framework ++@table @file ++@item @code{dg-*.c} ++Test the testsuite itself using @file{gcc.test-framework/test-framework.exp}. ++@end table ++ ++@end table ++ ++FIXME: merge in @file{testsuite/README.gcc} and discuss the format of ++test cases and magic comments more. ++ ++@node libgcj Tests ++@section The Java library testsuites. ++ ++Runtime tests are executed via @samp{make check} in the ++@file{@var{target}/libjava/testsuite} directory in the build ++tree. Additional runtime tests can be checked into this testsuite. ++ ++Regression testing of the core packages in libgcj is also covered by the ++Mauve testsuite. The @uref{http://sourceware.org/mauve/,,Mauve Project} ++develops tests for the Java Class Libraries. These tests are run as part ++of libgcj testing by placing the Mauve tree within the libjava testsuite ++sources at @file{libjava/testsuite/libjava.mauve/mauve}, or by specifying ++the location of that tree when invoking @samp{make}, as in ++@samp{make MAUVEDIR=~/mauve check}. ++ ++To detect regressions, a mechanism in @file{mauve.exp} compares the ++failures for a test run against the list of expected failures in ++@file{libjava/testsuite/libjava.mauve/xfails} from the source hierarchy. ++Update this file when adding new failing tests to Mauve, or when fixing ++bugs in libgcj that had caused Mauve test failures. ++ ++We encourage developers to contribute test cases to Mauve. ++ ++@node LTO Testing ++@section Support for testing link-time optimizations ++ ++Tests for link-time optimizations usually require multiple source files ++that are compiled separately, perhaps with different sets of options. ++There are several special-purpose test directives used for these tests. ++ ++@table @code ++@item @{ dg-lto-do @var{do-what-keyword} @} ++@var{do-what-keyword} specifies how the test is compiled and whether ++it is executed. It is one of: ++ ++@table @code ++@item assemble ++Compile with @option{-c} to produce a relocatable object file. ++@item link ++Compile, assemble, and link to produce an executable file. ++@item run ++Produce and run an executable file, which is expected to return ++an exit code of 0. ++@end table ++ ++The default is @code{assemble}. That can be overridden for a set of ++tests by redefining @code{dg-do-what-default} within the @code{.exp} ++file for those tests. ++ ++Unlike @code{dg-do}, @code{dg-lto-do} does not support an optional ++@samp{target} or @samp{xfail} list. Use @code{dg-skip-if}, ++@code{dg-xfail-if}, or @code{dg-xfail-run-if}. ++ ++@item @{ dg-lto-options @{ @{ @var{options} @} [@{ @var{options} @}] @} [@{ target @var{selector} @}]@} ++This directive provides a list of one or more sets of compiler options ++to override @var{LTO_OPTIONS}. Each test will be compiled and run with ++each of these sets of options. ++ ++@item @{ dg-extra-ld-options @var{options} @} ++This directive adds @var{options} to the linker options used. ++ ++@item @{ dg-suppress-ld-options @var{options} @} ++This directive removes @var{options} from the set of linker options used. ++@end table ++ ++@node gcov Testing ++@section Support for testing @command{gcov} ++ ++Language-independent support for testing @command{gcov}, and for checking ++that branch profiling produces expected values, is provided by the ++expect file @file{lib/gcov.exp}. @command{gcov} tests also rely on procedures ++in @file{lib/gcc-dg.exp} to compile and run the test program. A typical ++@command{gcov} test contains the following DejaGnu commands within comments: ++ ++@smallexample ++@{ dg-options "-fprofile-arcs -ftest-coverage" @} ++@{ dg-do run @{ target native @} @} ++@{ dg-final @{ run-gcov sourcefile @} @} ++@end smallexample ++ ++Checks of @command{gcov} output can include line counts, branch percentages, ++and call return percentages. All of these checks are requested via ++commands that appear in comments in the test's source file. ++Commands to check line counts are processed by default. ++Commands to check branch percentages and call return percentages are ++processed if the @command{run-gcov} command has arguments @code{branches} ++or @code{calls}, respectively. For example, the following specifies ++checking both, as well as passing @option{-b} to @command{gcov}: ++ ++@smallexample ++@{ dg-final @{ run-gcov branches calls @{ -b sourcefile @} @} @} ++@end smallexample ++ ++A line count command appears within a comment on the source line ++that is expected to get the specified count and has the form ++@code{count(@var{cnt})}. A test should only check line counts for ++lines that will get the same count for any architecture. ++ ++Commands to check branch percentages (@code{branch}) and call ++return percentages (@code{returns}) are very similar to each other. ++A beginning command appears on or before the first of a range of ++lines that will report the percentage, and the ending command ++follows that range of lines. The beginning command can include a ++list of percentages, all of which are expected to be found within ++the range. A range is terminated by the next command of the same ++kind. A command @code{branch(end)} or @code{returns(end)} marks ++the end of a range without starting a new one. For example: ++ ++@smallexample ++if (i > 10 && j > i && j < 20) /* @r{branch(27 50 75)} */ ++ /* @r{branch(end)} */ ++ foo (i, j); ++@end smallexample ++ ++For a call return percentage, the value specified is the ++percentage of calls reported to return. For a branch percentage, ++the value is either the expected percentage or 100 minus that ++value, since the direction of a branch can differ depending on the ++target or the optimization level. ++ ++Not all branches and calls need to be checked. A test should not ++check for branches that might be optimized away or replaced with ++predicated instructions. Don't check for calls inserted by the ++compiler or ones that might be inlined or optimized away. ++ ++A single test can check for combinations of line counts, branch ++percentages, and call return percentages. The command to check a ++line count must appear on the line that will report that count, but ++commands to check branch percentages and call return percentages can ++bracket the lines that report them. ++ ++@node profopt Testing ++@section Support for testing profile-directed optimizations ++ ++The file @file{profopt.exp} provides language-independent support for ++checking correct execution of a test built with profile-directed ++optimization. This testing requires that a test program be built and ++executed twice. The first time it is compiled to generate profile ++data, and the second time it is compiled to use the data that was ++generated during the first execution. The second execution is to ++verify that the test produces the expected results. ++ ++To check that the optimization actually generated better code, a ++test can be built and run a third time with normal optimizations to ++verify that the performance is better with the profile-directed ++optimizations. @file{profopt.exp} has the beginnings of this kind ++of support. ++ ++@file{profopt.exp} provides generic support for profile-directed ++optimizations. Each set of tests that uses it provides information ++about a specific optimization: ++ ++@table @code ++@item tool ++tool being tested, e.g., @command{gcc} ++ ++@item profile_option ++options used to generate profile data ++ ++@item feedback_option ++options used to optimize using that profile data ++ ++@item prof_ext ++suffix of profile data files ++ ++@item PROFOPT_OPTIONS ++list of options with which to run each test, similar to the lists for ++torture tests ++ ++@item @{ dg-final-generate @{ @var{local-directive} @} @} ++This directive is similar to @code{dg-final}, but the ++@var{local-directive} is run after the generation of profile data. ++ ++@item @{ dg-final-use @{ @var{local-directive} @} @} ++The @var{local-directive} is run after the profile data have been ++used. ++@end table ++ ++@node compat Testing ++@section Support for testing binary compatibility ++ ++The file @file{compat.exp} provides language-independent support for ++binary compatibility testing. It supports testing interoperability of ++two compilers that follow the same ABI, or of multiple sets of ++compiler options that should not affect binary compatibility. It is ++intended to be used for testsuites that complement ABI testsuites. ++ ++A test supported by this framework has three parts, each in a ++separate source file: a main program and two pieces that interact ++with each other to split up the functionality being tested. ++ ++@table @file ++@item @var{testname}_main.@var{suffix} ++Contains the main program, which calls a function in file ++@file{@var{testname}_x.@var{suffix}}. ++ ++@item @var{testname}_x.@var{suffix} ++Contains at least one call to a function in ++@file{@var{testname}_y.@var{suffix}}. ++ ++@item @var{testname}_y.@var{suffix} ++Shares data with, or gets arguments from, ++@file{@var{testname}_x.@var{suffix}}. ++@end table ++ ++Within each test, the main program and one functional piece are ++compiled by the GCC under test. The other piece can be compiled by ++an alternate compiler. If no alternate compiler is specified, ++then all three source files are all compiled by the GCC under test. ++You can specify pairs of sets of compiler options. The first element ++of such a pair specifies options used with the GCC under test, and the ++second element of the pair specifies options used with the alternate ++compiler. Each test is compiled with each pair of options. ++ ++@file{compat.exp} defines default pairs of compiler options. ++These can be overridden by defining the environment variable ++@env{COMPAT_OPTIONS} as: ++ ++@smallexample ++COMPAT_OPTIONS="[list [list @{@var{tst1}@} @{@var{alt1}@}] ++ @dots{}[list @{@var{tstn}@} @{@var{altn}@}]]" ++@end smallexample ++ ++where @var{tsti} and @var{alti} are lists of options, with @var{tsti} ++used by the compiler under test and @var{alti} used by the alternate ++compiler. For example, with ++@code{[list [list @{-g -O0@} @{-O3@}] [list @{-fpic@} @{-fPIC -O2@}]]}, ++the test is first built with @option{-g -O0} by the compiler under ++test and with @option{-O3} by the alternate compiler. The test is ++built a second time using @option{-fpic} by the compiler under test ++and @option{-fPIC -O2} by the alternate compiler. ++ ++An alternate compiler is specified by defining an environment ++variable to be the full pathname of an installed compiler; for C ++define @env{ALT_CC_UNDER_TEST}, and for C++ define ++@env{ALT_CXX_UNDER_TEST}. These will be written to the ++@file{site.exp} file used by DejaGnu. The default is to build each ++test with the compiler under test using the first of each pair of ++compiler options from @env{COMPAT_OPTIONS}. When ++@env{ALT_CC_UNDER_TEST} or ++@env{ALT_CXX_UNDER_TEST} is @code{same}, each test is built using ++the compiler under test but with combinations of the options from ++@env{COMPAT_OPTIONS}. ++ ++To run only the C++ compatibility suite using the compiler under test ++and another version of GCC using specific compiler options, do the ++following from @file{@var{objdir}/gcc}: ++ ++@smallexample ++rm site.exp ++make -k \ ++ ALT_CXX_UNDER_TEST=$@{alt_prefix@}/bin/g++ \ ++ COMPAT_OPTIONS="@var{lists as shown above}" \ ++ check-c++ \ ++ RUNTESTFLAGS="compat.exp" ++@end smallexample ++ ++A test that fails when the source files are compiled with different ++compilers, but passes when the files are compiled with the same ++compiler, demonstrates incompatibility of the generated code or ++runtime support. A test that fails for the alternate compiler but ++passes for the compiler under test probably tests for a bug that was ++fixed in the compiler under test but is present in the alternate ++compiler. ++ ++The binary compatibility tests support a small number of test framework ++commands that appear within comments in a test file. ++ ++@table @code ++@item dg-require-* ++These commands can be used in @file{@var{testname}_main.@var{suffix}} ++to skip the test if specific support is not available on the target. ++ ++@item dg-options ++The specified options are used for compiling this particular source ++file, appended to the options from @env{COMPAT_OPTIONS}. When this ++command appears in @file{@var{testname}_main.@var{suffix}} the options ++are also used to link the test program. ++ ++@item dg-xfail-if ++This command can be used in a secondary source file to specify that ++compilation is expected to fail for particular options on particular ++targets. ++@end table ++ ++@node Torture Tests ++@section Support for torture testing using multiple options ++ ++Throughout the compiler testsuite there are several directories whose ++tests are run multiple times, each with a different set of options. ++These are known as torture tests. ++@file{lib/torture-options.exp} defines procedures to ++set up these lists: ++ ++@table @code ++@item torture-init ++Initialize use of torture lists. ++@item set-torture-options ++Set lists of torture options to use for tests with and without loops. ++Optionally combine a set of torture options with a set of other ++options, as is done with Objective-C runtime options. ++@item torture-finish ++Finalize use of torture lists. ++@end table ++ ++The @file{.exp} file for a set of tests that use torture options must ++include calls to these three procedures if: ++ ++@itemize @bullet ++@item It calls @code{gcc-dg-runtest} and overrides @var{DG_TORTURE_OPTIONS}. ++ ++@item It calls @var{$@{tool@}}@code{-torture} or ++@var{$@{tool@}}@code{-torture-execute}, where @var{tool} is @code{c}, ++@code{fortran}, or @code{objc}. ++ ++@item It calls @code{dg-pch}. ++@end itemize ++ ++It is not necessary for a @file{.exp} file that calls @code{gcc-dg-runtest} ++to call the torture procedures if the tests should use the list in ++@var{DG_TORTURE_OPTIONS} defined in @file{gcc-dg.exp}. ++ ++Most uses of torture options can override the default lists by defining ++@var{TORTURE_OPTIONS} or add to the default list by defining ++@var{ADDITIONAL_TORTURE_OPTIONS}. Define these in a @file{.dejagnurc} ++file or add them to the @file{site.exp} file; for example ++ ++@smallexample ++set ADDITIONAL_TORTURE_OPTIONS [list \ ++ @{ -O2 -ftree-loop-linear @} \ ++ @{ -O2 -fpeel-loops @} ] ++@end smallexample +--- a/src/gcc/dominance.c ++++ b/src/gcc/dominance.c +@@ -782,16 +782,20 @@ + } + + /* Returns the list of basic blocks including BB dominated by BB, in the +- direction DIR. The vector will be sorted in preorder. */ ++ direction DIR up to DEPTH in the dominator tree. The DEPTH of zero will ++ produce a vector containing all dominated blocks. The vector will be sorted ++ in preorder. */ + + VEC (basic_block, heap) * +-get_all_dominated_blocks (enum cdi_direction dir, basic_block bb) ++get_dominated_to_depth (enum cdi_direction dir, basic_block bb, int depth) + { + VEC(basic_block, heap) *bbs = NULL; + unsigned i; ++ unsigned next_level_start; + + i = 0; + VEC_safe_push (basic_block, heap, bbs, bb); ++ next_level_start = 1; /* = VEC_length (basic_block, bbs); */ + + do + { +@@ -802,12 +806,24 @@ + son; + son = next_dom_son (dir, son)) + VEC_safe_push (basic_block, heap, bbs, son); ++ ++ if (i == next_level_start && --depth) ++ next_level_start = VEC_length (basic_block, bbs); + } +- while (i < VEC_length (basic_block, bbs)); ++ while (i < next_level_start); + + return bbs; + } + ++/* Returns the list of basic blocks including BB dominated by BB, in the ++ direction DIR. The vector will be sorted in preorder. */ ++ ++VEC (basic_block, heap) * ++get_all_dominated_blocks (enum cdi_direction dir, basic_block bb) ++{ ++ return get_dominated_to_depth (dir, bb, 0); ++} ++ + /* Redirect all edges pointing to BB to TO. */ + void + redirect_immediate_dominators (enum cdi_direction dir, basic_block bb, +--- a/src/gcc/dwarf2out.c ++++ b/src/gcc/dwarf2out.c +@@ -124,6 +124,9 @@ + # endif + #endif + ++#define NEED_UNWIND_TABLES \ ++ (flag_unwind_tables || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS)) ++ + /* Map register numbers held in the call frame info that gcc has + collected using DWARF_FRAME_REGNUM to those that should be output in + .debug_frame and .eh_frame. */ +@@ -147,9 +150,7 @@ + || write_symbols == VMS_AND_DWARF2_DEBUG + || DWARF2_FRAME_INFO || saved_do_cfi_asm + #ifdef DWARF2_UNWIND_INFO +- || (DWARF2_UNWIND_INFO +- && (flag_unwind_tables +- || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS))) ++ || (DWARF2_UNWIND_INFO && NEED_UNWIND_TABLES) + #endif + ); + } +@@ -185,7 +186,7 @@ + #ifdef TARGET_UNWIND_INFO + return false; + #else +- if (USING_SJLJ_EXCEPTIONS || (!flag_unwind_tables && !flag_exceptions)) ++ if (!NEED_UNWIND_TABLES) + return false; + #endif + } +@@ -1395,7 +1396,7 @@ + { + rtx dest = JUMP_LABEL (insn); + +- if (dest) ++ if (dest && !ANY_RETURN_P (dest)) + { + if (barrier_args_size [INSN_UID (dest)] < 0) + { +@@ -3905,8 +3906,7 @@ + /* ??? current_function_func_begin_label is also used by except.c + for call-site information. We must emit this label if it might + be used. */ +- if ((! flag_exceptions || USING_SJLJ_EXCEPTIONS) +- && ! dwarf2out_do_frame ()) ++ if (! NEED_UNWIND_TABLES && ! dwarf2out_do_frame ()) + return; + #else + if (! dwarf2out_do_frame ()) +@@ -4066,7 +4066,7 @@ + + #ifndef TARGET_UNWIND_INFO + /* Output another copy for the unwinder. */ +- if (! USING_SJLJ_EXCEPTIONS && (flag_unwind_tables || flag_exceptions)) ++ if (NEED_UNWIND_TABLES) + output_call_frame_info (1); + #endif + } +@@ -19000,6 +19000,16 @@ + if (type == NULL_TREE || type == error_mark_node) + return; + ++ if (TYPE_NAME (type) != NULL_TREE ++ && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL ++ && is_redundant_typedef (TYPE_NAME (type)) ++ && DECL_ORIGINAL_TYPE (TYPE_NAME (type))) ++ /* The DECL of this type is a typedef we don't want to emit debug ++ info for but we want debug info for its underlying typedef. ++ This can happen for e.g, the injected-class-name of a C++ ++ type. */ ++ type = DECL_ORIGINAL_TYPE (TYPE_NAME (type)); ++ + /* If TYPE is a typedef type variant, let's generate debug info + for the parent typedef which TYPE is a type of. */ + if (TYPE_NAME (type) && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL +@@ -20748,10 +20758,15 @@ + { + if (HAVE_GAS_CFI_SECTIONS_DIRECTIVE && dwarf2out_do_cfi_asm ()) + { +-#ifndef TARGET_UNWIND_INFO +- if (USING_SJLJ_EXCEPTIONS || (!flag_unwind_tables && !flag_exceptions)) +-#endif ++#ifdef TARGET_UNWIND_INFO ++ /* We're only ever interested in .debug_frame. */ ++ fprintf (asm_out_file, "\t.cfi_sections\t.debug_frame\n"); ++#else ++ /* GAS defaults to emitting .eh_frame only, and .debug_frame is not ++ wanted in case that the former one is present. */ ++ if (! NEED_UNWIND_TABLES) + fprintf (asm_out_file, "\t.cfi_sections\t.debug_frame\n"); ++#endif + } + } + +--- a/src/gcc/ee.c ++++ b/src/gcc/ee.c +@@ -0,0 +1,662 @@ ++/* Redundant extension elimination ++ Copyright (C) 2010 Free Software Foundation, Inc. ++ Contributed by Tom de Vries (tom@codesourcery.com) ++ ++This file is part of GCC. ++ ++GCC is free software; you can redistribute it and/or modify it under ++the terms of the GNU General Public License as published by the Free ++Software Foundation; either version 3, or (at your option) any later ++version. ++ ++GCC is distributed in the hope that it will be useful, but WITHOUT ANY ++WARRANTY; without even the implied warranty of MERCHANTABILITY or ++FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++for more details. ++ ++You should have received a copy of the GNU General Public License ++along with GCC; see the file COPYING3. If not see ++. */ ++ ++/* ++ ++ MOTIVATING EXAMPLE ++ ++ The motivating example for this pass is: ++ ++ void f(unsigned char *p, short s, int c, int *z) ++ { ++ if (c) ++ *z = 0; ++ *p ^= (unsigned char)s; ++ } ++ ++ For MIPS, compilation results in the following insns. ++ ++ (set (reg/v:SI 199) ++ (sign_extend:SI (subreg:HI (reg:SI 200) 2))) ++ ++ ... ++ ++ (set (reg:QI 203) ++ (subreg:QI (reg/v:SI 199) 3)) ++ ++ These insns are the only def and the only use of reg 199, each located in a ++ different bb. ++ ++ The sign-extension preserves the lower half of reg 200 and copies them to ++ reg 199, and the subreg use of reg 199 only reads the least significant byte. ++ The sign extension is therefore redundant (the extension part, not the copy ++ part), and can safely be replaced with a regcopy from reg 200 to reg 199. ++ ++ ++ OTHER SIGN/ZERO EXTENSION ELIMINATION PASSES ++ ++ There are other passes which eliminate sign/zero-extension: combine and ++ implicit_zee. Both attempt to eliminate extensions by combining them with ++ other instructions. The combine pass does this at bb level, ++ implicit_zee works at inter-bb level. ++ ++ The combine pass combine an extension with either: ++ - all uses of the extension, or ++ - all defs of the operand of the extension. ++ The implicit_zee pass only implements the latter. ++ ++ For our motivating example, combine doesn't work since the def and the use of ++ reg 199 are in a different bb. ++ ++ Implicit_zee does not work since it only combines an extension with the defs ++ of its operand. ++ ++ ++ INTENDED EFFECT ++ ++ This pass works by removing sign/zero-extensions, or replacing them with ++ regcopies. The idea there is that the regcopy might be eliminated by a later ++ pass. In case the regcopy cannot be eliminated, it might at least be cheaper ++ than the extension. ++ ++ ++ IMPLEMENTATION ++ ++ The pass scans twice over all instructions. ++ ++ The first scan registers all uses of a reg in the biggest_use array. After ++ that first scan, the biggest_use array contains the size in bits of the ++ biggest use of each reg. ++ ++ The second scan finds extensions, determines whether they are redundant based ++ on the biggest use, and deletes or replaces them. ++ ++ In case that the src and dest reg of the replacement are not of the same size, ++ we do not replace with a normal regcopy, but with a truncate or with the copy ++ of a paradoxical subreg instead. ++ ++ ++ LIMITATIONS ++ ++ The scope of the analysis is limited to an extension and its uses. The other ++ type of analysis (related to the defs of the operand of an extension) is not ++ done. ++ ++ Furthermore, we do the analysis of biggest use per reg. So when determining ++ whether an extension is redundant, we take all uses of a the dest reg into ++ account, also the ones that are not uses of the extension. This could be ++ overcome by calculating the def-use chains and using those for analysis ++ instead. ++ ++ Finally, during the analysis each insn is looked at in isolation. There is no ++ propagation of information during the analysis. To overcome this limitation, ++ a backward iterative bit-level liveness analysis is needed. */ ++ ++ ++#include "config.h" ++#include "system.h" ++#include "coretypes.h" ++#include "tm.h" ++#include "rtl.h" ++#include "tree.h" ++#include "tm_p.h" ++#include "flags.h" ++#include "regs.h" ++#include "hard-reg-set.h" ++#include "basic-block.h" ++#include "insn-config.h" ++#include "function.h" ++#include "expr.h" ++#include "insn-attr.h" ++#include "recog.h" ++#include "toplev.h" ++#include "target.h" ++#include "timevar.h" ++#include "optabs.h" ++#include "insn-codes.h" ++#include "rtlhooks-def.h" ++#include "output.h" ++#include "params.h" ++#include "timevar.h" ++#include "tree-pass.h" ++#include "cgraph.h" ++ ++#define SKIP_REG (-1) ++ ++/* Array to register the biggest use of a reg, in bits. */ ++ ++static int *biggest_use; ++ ++/* Forward declaration. */ ++ ++static void note_use (rtx *x, void *data); ++ ++/* The following two functions are borrowed from trunk/gcc/toplev.c. They can be ++ removed for a check-in into gcc trunk. */ ++ ++/* Given X, an unsigned number, return the number of least significant bits ++ that are zero. When X == 0, the result is the word size. */ ++ ++static int ++ctz_hwi (unsigned HOST_WIDE_INT x) ++{ ++ return x ? floor_log2 (x & -x) : HOST_BITS_PER_WIDE_INT; ++} ++ ++/* Similarly for most significant bits. */ ++ ++static int ++clz_hwi (unsigned HOST_WIDE_INT x) ++{ ++ return HOST_BITS_PER_WIDE_INT - 1 - floor_log2(x); ++} ++ ++/* Check whether this is a paradoxical subreg. */ ++ ++static bool ++paradoxical_subreg_p (rtx subreg) ++{ ++ enum machine_mode subreg_mode, reg_mode; ++ ++ if (GET_CODE (subreg) != SUBREG) ++ return false; ++ ++ subreg_mode = GET_MODE (subreg); ++ reg_mode = GET_MODE (SUBREG_REG (subreg)); ++ ++ if (GET_MODE_SIZE (subreg_mode) > GET_MODE_SIZE (reg_mode)) ++ return true; ++ ++ return false; ++} ++ ++/* Get the size and reg number of a REG or SUBREG use. */ ++ ++static bool ++reg_use_p (rtx use, int *size, unsigned int *regno) ++{ ++ rtx reg; ++ ++ if (REG_P (use)) ++ { ++ *regno = REGNO (use); ++ *size = GET_MODE_BITSIZE (GET_MODE (use)); ++ return true; ++ } ++ else if (GET_CODE (use) == SUBREG) ++ { ++ reg = SUBREG_REG (use); ++ ++ if (!REG_P (reg)) ++ return false; ++ ++ *regno = REGNO (reg); ++ ++ if (paradoxical_subreg_p (use)) ++ *size = GET_MODE_BITSIZE (GET_MODE (reg)); ++ else ++ *size = subreg_lsb (use) + GET_MODE_BITSIZE (GET_MODE (use)); ++ ++ return true; ++ } ++ ++ return false; ++} ++ ++/* Register the use of a reg. */ ++ ++static void ++register_use (int size, unsigned int regno) ++{ ++ int *current = &biggest_use[regno]; ++ ++ if (*current == SKIP_REG) ++ return; ++ ++ *current = MAX (*current, size); ++} ++ ++/* Handle embedded uses. */ ++ ++static void ++note_embedded_uses (rtx use, rtx pattern) ++{ ++ const char *format_ptr; ++ int i, j; ++ ++ format_ptr = GET_RTX_FORMAT (GET_CODE (use)); ++ for (i = 0; i < GET_RTX_LENGTH (GET_CODE (use)); i++) ++ if (format_ptr[i] == 'e') ++ note_use (&XEXP (use, i), pattern); ++ else if (format_ptr[i] == 'E') ++ for (j = 0; j < XVECLEN (use, i); j++) ++ note_use (&XVECEXP (use, i, j), pattern); ++} ++ ++/* Get the set that has use as its SRC operand. */ ++ ++static rtx ++get_set (rtx use, rtx pattern) ++{ ++ rtx sub; ++ int i; ++ ++ if (GET_CODE (pattern) == SET && SET_SRC (pattern) == use) ++ return pattern; ++ ++ if (GET_CODE (pattern) == PARALLEL) ++ for (i = 0; i < XVECLEN (pattern, 0); ++i) ++ { ++ sub = XVECEXP (pattern, 0, i); ++ if (GET_CODE (sub) == SET && SET_SRC (sub) == use) ++ return sub; ++ } ++ ++ return NULL_RTX; ++} ++ ++/* Handle a restricted op use. In this context restricted means that a bit in an ++ operand influences only the same bit or more significant bits in the result. ++ The bitwise ops are a subclass, but PLUS is one as well. */ ++ ++static void ++note_restricted_op_use (rtx use, unsigned int nr_operands, rtx pattern) ++{ ++ unsigned int i, smallest; ++ int operand_size[2]; ++ int used_size; ++ unsigned int operand_regno[2]; ++ bool operand_reg[2]; ++ bool operand_ignore[2]; ++ rtx set; ++ ++ /* Init operand_reg, operand_size, operand_regno and operand_ignore. */ ++ for (i = 0; i < nr_operands; ++i) ++ { ++ operand_reg[i] = reg_use_p (XEXP (use, i), &operand_size[i], ++ &operand_regno[i]); ++ operand_ignore[i] = false; ++ } ++ ++ /* Handle case of reg and-masked with const. */ ++ if (GET_CODE (use) == AND && CONST_INT_P (XEXP (use, 1)) && operand_reg[0]) ++ { ++ used_size = ++ HOST_BITS_PER_WIDE_INT - clz_hwi (UINTVAL (XEXP (use, 1))); ++ operand_size[0] = MIN (operand_size[0], used_size); ++ } ++ ++ /* Handle case of reg or-masked with const. */ ++ if (GET_CODE (use) == IOR && CONST_INT_P (XEXP (use, 1)) && operand_reg[0]) ++ { ++ used_size = ++ HOST_BITS_PER_WIDE_INT - clz_hwi (~UINTVAL (XEXP (use, 1))); ++ operand_size[0] = MIN (operand_size[0], used_size); ++ } ++ ++ /* Ignore the use of a in 'a = a + b'. */ ++ set = get_set (use, pattern); ++ if (set != NULL_RTX && REG_P (SET_DEST (set))) ++ for (i = 0; i < nr_operands; ++i) ++ operand_ignore[i] = (operand_reg[i] ++ && (REGNO (SET_DEST (set)) == operand_regno[i])); ++ ++ /* Handle the case a reg is combined with don't care bits. */ ++ if (nr_operands == 2 && operand_reg[0] && operand_reg[1] ++ && operand_size[0] != operand_size[1]) ++ { ++ smallest = operand_size[0] > operand_size[1]; ++ ++ if (paradoxical_subreg_p (XEXP (use, smallest)) ++ && !SUBREG_PROMOTED_VAR_P (XEXP (use, smallest))) ++ operand_size[1 - smallest] = operand_size[smallest]; ++ } ++ ++ /* Register the operand use, if necessary. */ ++ for (i = 0; i < nr_operands; ++i) ++ if (!operand_reg[i]) ++ note_use (&XEXP (use, i), pattern); ++ else if (!operand_ignore[i]) ++ register_use (operand_size[i], operand_regno[i]); ++} ++ ++/* Handle all uses noted by note_uses. */ ++ ++static void ++note_use (rtx *x, void *data) ++{ ++ rtx use = *x; ++ rtx pattern = (rtx)data; ++ int use_size; ++ unsigned int use_regno; ++ ++ switch (GET_CODE (use)) ++ { ++ case REG: ++ case SUBREG: ++ if (!reg_use_p (use, &use_size, &use_regno)) ++ { ++ note_embedded_uses (use, pattern); ++ return; ++ } ++ register_use (use_size, use_regno); ++ return; ++ case IOR: ++ case AND: ++ case XOR: ++ case PLUS: ++ case MINUS: ++ note_restricted_op_use (use, 2, pattern); ++ return; ++ case NOT: ++ case NEG: ++ note_restricted_op_use (use, 1, pattern); ++ return; ++ case ASHIFT: ++ if (!reg_use_p (XEXP (use, 0), &use_size, &use_regno) ++ || !CONST_INT_P (XEXP (use, 1)) ++ || INTVAL (XEXP (use, 1)) <= 0 ++ || paradoxical_subreg_p (XEXP (use, 0))) ++ { ++ note_embedded_uses (use, pattern); ++ return; ++ } ++ register_use (use_size - INTVAL (XEXP (use, 1)), use_regno); ++ return; ++ default: ++ note_embedded_uses (use, pattern); ++ return; ++ } ++} ++ ++/* Check whether reg is implicitly used. */ ++ ++static bool ++implicit_use_p (int regno) ++{ ++#ifdef EPILOGUE_USES ++ if (EPILOGUE_USES (regno)) ++ return true; ++#endif ++ ++#ifdef EH_USES ++ if (EH_USES (regno)) ++ return true; ++#endif ++ ++ return false; ++} ++ ++/* Note the uses of argument registers in a call. */ ++ ++static void ++note_call_uses (rtx insn) ++{ ++ rtx link, link_expr; ++ ++ if (!CALL_P (insn)) ++ return; ++ ++ for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) ++ { ++ link_expr = XEXP (link, 0); ++ ++ if (GET_CODE (link_expr) == USE) ++ note_use (&XEXP (link_expr, 0), link); ++ } ++} ++ ++/* Calculate the biggest use mode for all regs. */ ++ ++static void ++calculate_biggest_use (void) ++{ ++ int i; ++ basic_block bb; ++ rtx insn; ++ ++ /* Initialize biggest_use for all regs to 0. If a reg is used implicitly, we ++ handle that reg conservatively and set it to SKIP_REG instead. */ ++ for (i = 0; i < max_reg_num (); i++) ++ biggest_use[i] = ((implicit_use_p (i) || HARD_REGISTER_NUM_P (i)) ++ ? SKIP_REG : 0); ++ ++ /* For all insns, call note_use for each use in insn. */ ++ FOR_EACH_BB (bb) ++ FOR_BB_INSNS (bb, insn) ++ { ++ if (!NONDEBUG_INSN_P (insn)) ++ continue; ++ ++ note_uses (&PATTERN (insn), note_use, PATTERN (insn)); ++ ++ if (CALL_P (insn)) ++ note_call_uses (insn); ++ } ++ ++ /* Dump the biggest uses found. */ ++ if (dump_file) ++ for (i = 0; i < max_reg_num (); i++) ++ if (biggest_use[i] > 0) ++ fprintf (dump_file, "reg %d: size %d\n", i, biggest_use[i]); ++} ++ ++/* Check whether this is a sign/zero extension. */ ++ ++static bool ++extension_p (rtx insn, rtx *dest, rtx *inner, int *preserved_size) ++{ ++ rtx src, op0; ++ ++ /* Detect set of reg. */ ++ if (GET_CODE (PATTERN (insn)) != SET) ++ return false; ++ ++ src = SET_SRC (PATTERN (insn)); ++ *dest = SET_DEST (PATTERN (insn)); ++ ++ if (!REG_P (*dest)) ++ return false; ++ ++ /* Detect sign or zero extension. */ ++ if (GET_CODE (src) == ZERO_EXTEND || GET_CODE (src) == SIGN_EXTEND ++ || (GET_CODE (src) == AND && CONST_INT_P (XEXP (src, 1)))) ++ { ++ op0 = XEXP (src, 0); ++ ++ /* Determine amount of least significant bits preserved by operation. */ ++ if (GET_CODE (src) == AND) ++ *preserved_size = ctz_hwi (~UINTVAL (XEXP (src, 1))); ++ else ++ *preserved_size = GET_MODE_BITSIZE (GET_MODE (op0)); ++ ++ if (GET_CODE (op0) == SUBREG) ++ { ++ if (subreg_lsb (op0) != 0) ++ return false; ++ ++ *inner = SUBREG_REG (op0); ++ return true; ++ } ++ else if (REG_P (op0)) ++ { ++ *inner = op0; ++ return true; ++ } ++ } ++ ++ return false; ++} ++ ++/* Check whether this is a redundant sign/zero extension. */ ++ ++static bool ++redundant_extension_p (rtx insn, rtx *dest, rtx *inner) ++{ ++ int biggest_dest_use; ++ int preserved_size; ++ ++ if (!extension_p (insn, dest, inner, &preserved_size)) ++ return false; ++ ++ if (dump_file) ++ fprintf (dump_file, "considering extension %u with preserved size %d\n", ++ INSN_UID (insn), preserved_size); ++ ++ biggest_dest_use = biggest_use[REGNO (*dest)]; ++ ++ if (biggest_dest_use == SKIP_REG) ++ return false; ++ ++ if (preserved_size < biggest_dest_use) ++ return false; ++ ++ if (dump_file) ++ fprintf (dump_file, "found superfluous extension %u\n", INSN_UID (insn)); ++ ++ return true; ++} ++ ++/* Try to remove or replace the redundant extension. */ ++ ++static void ++try_remove_or_replace_extension (rtx insn, rtx dest, rtx inner) ++{ ++ rtx cp_src, cp_dest, seq, one; ++ ++ if (GET_MODE_CLASS (GET_MODE (dest)) != GET_MODE_CLASS (GET_MODE (inner))) ++ return; ++ ++ /* Check whether replacement is needed. */ ++ if (dest != inner) ++ { ++ start_sequence (); ++ ++ /* Determine the proper replacement operation. */ ++ if (GET_MODE (dest) == GET_MODE (inner)) ++ { ++ cp_src = inner; ++ cp_dest = dest; ++ } ++ else if (GET_MODE_SIZE (GET_MODE (dest)) ++ > GET_MODE_SIZE (GET_MODE (inner))) ++ { ++ emit_clobber (dest); ++ cp_src = inner; ++ cp_dest = gen_lowpart_SUBREG (GET_MODE (inner), dest); ++ } ++ else ++ { ++ cp_src = gen_rtx_TRUNCATE (GET_MODE (dest), inner); ++ cp_dest = dest; ++ } ++ ++ emit_move_insn (cp_dest, cp_src); ++ ++ seq = get_insns (); ++ end_sequence (); ++ ++ /* If the replacement is not supported, bail out. */ ++ for (one = seq; one != NULL_RTX; one = NEXT_INSN (one)) ++ if (recog_memoized (one) < 0 && GET_CODE (PATTERN (one)) != CLOBBER) ++ return; ++ ++ /* Insert the replacement. */ ++ emit_insn_before (seq, insn); ++ } ++ ++ /* Note replacement/removal in the dump. */ ++ if (dump_file) ++ { ++ fprintf (dump_file, "superfluous extension %u ", INSN_UID (insn)); ++ if (dest != inner) ++ fprintf (dump_file, "replaced by %u\n", INSN_UID (seq)); ++ else ++ fprintf (dump_file, "removed\n"); ++ } ++ ++ /* Remove the extension. */ ++ delete_insn (insn); ++} ++ ++/* Find redundant extensions and remove or replace them if possible. */ ++ ++static void ++remove_redundant_extensions (void) ++{ ++ basic_block bb; ++ rtx insn, next, dest, inner; ++ ++ biggest_use = XNEWVEC (int, max_reg_num ()); ++ calculate_biggest_use (); ++ ++ /* Remove redundant extensions. */ ++ FOR_EACH_BB (bb) ++ FOR_BB_INSNS_SAFE (bb, insn, next) ++ { ++ if (!NONDEBUG_INSN_P (insn)) ++ continue; ++ ++ if (!redundant_extension_p (insn, &dest, &inner)) ++ continue; ++ ++ try_remove_or_replace_extension (insn, dest, inner); ++ } ++ ++ free (biggest_use); ++} ++ ++/* Remove redundant extensions. */ ++ ++static unsigned int ++rest_of_handle_ee (void) ++{ ++ remove_redundant_extensions (); ++ return 0; ++} ++ ++/* Run ee pass when flag_ee is set at optimization level > 0. */ ++ ++static bool ++gate_handle_ee (void) ++{ ++ return (optimize > 0 && flag_ee); ++} ++ ++struct rtl_opt_pass pass_ee = ++{ ++ { ++ RTL_PASS, ++ "ee", /* name */ ++ gate_handle_ee, /* gate */ ++ rest_of_handle_ee, /* execute */ ++ NULL, /* sub */ ++ NULL, /* next */ ++ 0, /* static_pass_number */ ++ TV_EE, /* tv_id */ ++ 0, /* properties_required */ ++ 0, /* properties_provided */ ++ 0, /* properties_destroyed */ ++ 0, /* todo_flags_start */ ++ TODO_ggc_collect | ++ TODO_dump_func | ++ TODO_verify_rtl_sharing, /* todo_flags_finish */ ++ } ++}; +--- a/src/gcc/emit-rtl.c ++++ b/src/gcc/emit-rtl.c +@@ -1648,6 +1648,11 @@ + MEM_READONLY_P (ref) = 1; + } + ++ /* Mark static const strings readonly as well. */ ++ if (base && TREE_CODE (base) == STRING_CST && TREE_READONLY (base) ++ && TREE_STATIC (base)) ++ MEM_READONLY_P (ref) = 1; ++ + /* If this expression uses it's parent's alias set, mark it such + that we won't change it. */ + if (component_uses_parent_alias_set (t)) +@@ -2427,6 +2432,8 @@ + case CODE_LABEL: + case PC: + case CC0: ++ case RETURN: ++ case SIMPLE_RETURN: + case SCRATCH: + return; + /* SCRATCH must be shared because they represent distinct values. */ +@@ -3318,14 +3325,17 @@ + return insn; + } + +-/* Return the last label to mark the same position as LABEL. Return null +- if LABEL itself is null. */ ++/* Return the last label to mark the same position as LABEL. Return LABEL ++ itself if it is null or any return rtx. */ + + rtx + skip_consecutive_labels (rtx label) + { + rtx insn; + ++ if (label && ANY_RETURN_P (label)) ++ return label; ++ + for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn)) + if (LABEL_P (insn)) + label = insn; +@@ -5204,7 +5214,7 @@ + return CODE_LABEL; + if (GET_CODE (x) == CALL) + return CALL_INSN; +- if (GET_CODE (x) == RETURN) ++ if (GET_CODE (x) == RETURN || GET_CODE (x) == SIMPLE_RETURN) + return JUMP_INSN; + if (GET_CODE (x) == SET) + { +@@ -5710,8 +5720,10 @@ + init_reg_modes_target (); + + /* Assign register numbers to the globally defined register rtx. */ +- pc_rtx = gen_rtx_PC (VOIDmode); +- cc0_rtx = gen_rtx_CC0 (VOIDmode); ++ pc_rtx = gen_rtx_fmt_ (PC, VOIDmode); ++ ret_rtx = gen_rtx_fmt_ (RETURN, VOIDmode); ++ simple_return_rtx = gen_rtx_fmt_ (SIMPLE_RETURN, VOIDmode); ++ cc0_rtx = gen_rtx_fmt_ (CC0, VOIDmode); + stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); + frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); + hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM); +--- a/src/gcc/expmed.c ++++ b/src/gcc/expmed.c +@@ -47,7 +47,7 @@ + static rtx extract_fixed_bit_field (enum machine_mode, rtx, + unsigned HOST_WIDE_INT, + unsigned HOST_WIDE_INT, +- unsigned HOST_WIDE_INT, rtx, int); ++ unsigned HOST_WIDE_INT, rtx, int, bool); + static rtx mask_rtx (enum machine_mode, int, int, int); + static rtx lshift_value (enum machine_mode, rtx, int, int); + static rtx extract_split_bit_field (rtx, unsigned HOST_WIDE_INT, +@@ -904,8 +904,14 @@ + if (GET_MODE_BITSIZE (mode) == 0 + || GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (word_mode)) + mode = word_mode; +- mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, +- MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0)); ++ ++ if (MEM_VOLATILE_P (op0) ++ && GET_MODE_BITSIZE (GET_MODE (op0)) > 0 ++ && flag_strict_volatile_bitfields > 0) ++ mode = GET_MODE (op0); ++ else ++ mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, ++ MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0)); + + if (mode == VOIDmode) + { +@@ -1099,7 +1105,7 @@ + endianness compensation) to fetch the piece we want. */ + part = extract_fixed_bit_field (word_mode, value, 0, thissize, + total_bits - bitsize + bitsdone, +- NULL_RTX, 1); ++ NULL_RTX, 1, false); + } + else + { +@@ -1110,7 +1116,7 @@ + & (((HOST_WIDE_INT) 1 << thissize) - 1)); + else + part = extract_fixed_bit_field (word_mode, value, 0, thissize, +- bitsdone, NULL_RTX, 1); ++ bitsdone, NULL_RTX, 1, false); + } + + /* If OP0 is a register, then handle OFFSET here. +@@ -1176,7 +1182,8 @@ + + static rtx + extract_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize, +- unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target, ++ unsigned HOST_WIDE_INT bitnum, ++ int unsignedp, bool packedp, rtx target, + enum machine_mode mode, enum machine_mode tmode, + bool fallback_p) + { +@@ -1378,6 +1385,14 @@ + ? mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) + : mode); + ++ /* If the bitfield is volatile, we need to make sure the access ++ remains on a type-aligned boundary. */ ++ if (GET_CODE (op0) == MEM ++ && MEM_VOLATILE_P (op0) ++ && GET_MODE_BITSIZE (GET_MODE (op0)) > 0 ++ && flag_strict_volatile_bitfields > 0) ++ goto no_subreg_mode_swap; ++ + if (((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode) + && bitpos % BITS_PER_WORD == 0) + || (mode1 != BLKmode +@@ -1450,7 +1465,7 @@ + rtx result_part + = extract_bit_field (op0, MIN (BITS_PER_WORD, + bitsize - i * BITS_PER_WORD), +- bitnum + bit_offset, 1, target_part, mode, ++ bitnum + bit_offset, 1, false, target_part, mode, + word_mode); + + gcc_assert (target_part); +@@ -1649,7 +1664,7 @@ + xop0 = adjust_address (op0, bestmode, xoffset); + xop0 = force_reg (bestmode, xop0); + result = extract_bit_field_1 (xop0, bitsize, xbitpos, +- unsignedp, target, ++ unsignedp, packedp, target, + mode, tmode, false); + if (result) + return result; +@@ -1663,7 +1678,7 @@ + return NULL; + + target = extract_fixed_bit_field (int_mode, op0, offset, bitsize, +- bitpos, target, unsignedp); ++ bitpos, target, unsignedp, packedp); + return convert_extracted_bit_field (target, mode, tmode, unsignedp); + } + +@@ -1674,6 +1689,7 @@ + + STR_RTX is the structure containing the byte (a REG or MEM). + UNSIGNEDP is nonzero if this is an unsigned bit field. ++ PACKEDP is nonzero if the field has the packed attribute. + MODE is the natural mode of the field value once extracted. + TMODE is the mode the caller would like the value to have; + but the value may be returned with type MODE instead. +@@ -1685,10 +1701,10 @@ + + rtx + extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize, +- unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target, +- enum machine_mode mode, enum machine_mode tmode) ++ unsigned HOST_WIDE_INT bitnum, int unsignedp, bool packedp, ++ rtx target, enum machine_mode mode, enum machine_mode tmode) + { +- return extract_bit_field_1 (str_rtx, bitsize, bitnum, unsignedp, ++ return extract_bit_field_1 (str_rtx, bitsize, bitnum, unsignedp, packedp, + target, mode, tmode, true); + } + +@@ -1704,6 +1720,8 @@ + which is significant on bigendian machines.) + + UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value). ++ PACKEDP is true if the field has the packed attribute. ++ + If TARGET is nonzero, attempts to store the value there + and return TARGET, but this is not guaranteed. + If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */ +@@ -1713,7 +1731,7 @@ + unsigned HOST_WIDE_INT offset, + unsigned HOST_WIDE_INT bitsize, + unsigned HOST_WIDE_INT bitpos, rtx target, +- int unsignedp) ++ int unsignedp, bool packedp) + { + unsigned int total_bits = BITS_PER_WORD; + enum machine_mode mode; +@@ -1730,8 +1748,19 @@ + includes the entire field. If such a mode would be larger than + a word, we won't be doing the extraction the normal way. */ + +- mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, +- MEM_ALIGN (op0), word_mode, MEM_VOLATILE_P (op0)); ++ if (MEM_VOLATILE_P (op0) ++ && flag_strict_volatile_bitfields > 0) ++ { ++ if (GET_MODE_BITSIZE (GET_MODE (op0)) > 0) ++ mode = GET_MODE (op0); ++ else if (target && GET_MODE_BITSIZE (GET_MODE (target)) > 0) ++ mode = GET_MODE (target); ++ else ++ mode = tmode; ++ } ++ else ++ mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, ++ MEM_ALIGN (op0), word_mode, MEM_VOLATILE_P (op0)); + + if (mode == VOIDmode) + /* The only way this should occur is if the field spans word +@@ -1752,12 +1781,67 @@ + * BITS_PER_UNIT); + } + +- /* Get ref to an aligned byte, halfword, or word containing the field. +- Adjust BITPOS to be position within a word, +- and OFFSET to be the offset of that word. +- Then alter OP0 to refer to that word. */ +- bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; +- offset -= (offset % (total_bits / BITS_PER_UNIT)); ++ /* If we're accessing a volatile MEM, we can't do the next ++ alignment step if it results in a multi-word access where we ++ otherwise wouldn't have one. So, check for that case ++ here. */ ++ if (MEM_P (op0) ++ && MEM_VOLATILE_P (op0) ++ && flag_strict_volatile_bitfields > 0 ++ && bitpos + bitsize <= total_bits ++ && bitpos + bitsize + (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT > total_bits) ++ { ++ if (STRICT_ALIGNMENT) ++ { ++ static bool informed_about_misalignment = false; ++ bool warned; ++ ++ if (packedp) ++ { ++ if (bitsize == total_bits) ++ warned = warning_at (input_location, OPT_fstrict_volatile_bitfields, ++ "multiple accesses to volatile structure member" ++ " because of packed attribute"); ++ else ++ warned = warning_at (input_location, OPT_fstrict_volatile_bitfields, ++ "multiple accesses to volatile structure bitfield" ++ " because of packed attribute"); ++ ++ return extract_split_bit_field (op0, bitsize, ++ bitpos + offset * BITS_PER_UNIT, ++ unsignedp); ++ } ++ ++ if (bitsize == total_bits) ++ warned = warning_at (input_location, OPT_fstrict_volatile_bitfields, ++ "mis-aligned access used for structure member"); ++ else ++ warned = warning_at (input_location, OPT_fstrict_volatile_bitfields, ++ "mis-aligned access used for structure bitfield"); ++ ++ if (! informed_about_misalignment && warned) ++ { ++ informed_about_misalignment = true; ++ inform (input_location, ++ "When a volatile object spans multiple type-sized locations," ++ " the compiler must choose between using a single mis-aligned access to" ++ " preserve the volatility, or using multiple aligned accesses to avoid" ++ " runtime faults. This code may fail at runtime if the hardware does" ++ " not allow this access."); ++ } ++ } ++ } ++ else ++ { ++ ++ /* Get ref to an aligned byte, halfword, or word containing the field. ++ Adjust BITPOS to be position within a word, ++ and OFFSET to be the offset of that word. ++ Then alter OP0 to refer to that word. */ ++ bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; ++ offset -= (offset % (total_bits / BITS_PER_UNIT)); ++ } ++ + op0 = adjust_address (op0, mode, offset); + } + +@@ -1966,7 +2050,7 @@ + extract_fixed_bit_field wants offset in bytes. */ + part = extract_fixed_bit_field (word_mode, word, + offset * unit / BITS_PER_UNIT, +- thissize, thispos, 0, 1); ++ thissize, thispos, 0, 1, false); + bitsdone += thissize; + + /* Shift this part into place for the result. */ +@@ -3255,6 +3339,60 @@ + gcc_assert (op0); + return op0; + } ++ ++/* Perform a widening multiplication and return an rtx for the result. ++ MODE is mode of value; OP0 and OP1 are what to multiply (rtx's); ++ TARGET is a suggestion for where to store the result (an rtx). ++ THIS_OPTAB is the optab we should use, it must be either umul_widen_optab ++ or smul_widen_optab. ++ ++ We check specially for a constant integer as OP1, comparing the ++ cost of a widening multiply against the cost of a sequence of shifts ++ and adds. */ ++ ++rtx ++expand_widening_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, ++ int unsignedp, optab this_optab) ++{ ++ bool speed = optimize_insn_for_speed_p (); ++ rtx cop1; ++ ++ if (CONST_INT_P (op1) ++ && GET_MODE (op0) != VOIDmode ++ && (cop1 = convert_modes (mode, GET_MODE (op0), op1, ++ this_optab == umul_widen_optab)) ++ && CONST_INT_P (cop1) ++ && (INTVAL (cop1) >= 0 ++ || GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)) ++ { ++ HOST_WIDE_INT coeff = INTVAL (cop1); ++ int max_cost; ++ enum mult_variant variant; ++ struct algorithm algorithm; ++ ++ /* Special case powers of two. */ ++ if (EXACT_POWER_OF_2_OR_ZERO_P (coeff)) ++ { ++ op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab); ++ return expand_shift (LSHIFT_EXPR, mode, op0, ++ build_int_cst (NULL_TREE, floor_log2 (coeff)), ++ target, unsignedp); ++ } ++ ++ /* Exclude cost of op0 from max_cost to match the cost ++ calculation of the synth_mult. */ ++ max_cost = mul_widen_cost[speed][mode]; ++ if (choose_mult_variant (mode, coeff, &algorithm, &variant, ++ max_cost)) ++ { ++ op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab); ++ return expand_mult_const (mode, op0, coeff, target, ++ &algorithm, variant); ++ } ++ } ++ return expand_binop (mode, this_optab, op0, op1, target, ++ unsignedp, OPTAB_LIB_WIDEN); ++} + + /* Return the smallest n such that 2**n >= X. */ + +--- a/src/gcc/expr.c ++++ b/src/gcc/expr.c +@@ -1749,7 +1749,7 @@ + && (!REG_P (tmps[i]) || GET_MODE (tmps[i]) != mode)) + tmps[i] = extract_bit_field (tmps[i], bytelen * BITS_PER_UNIT, + (bytepos % slen0) * BITS_PER_UNIT, +- 1, NULL_RTX, mode, mode); ++ 1, false, NULL_RTX, mode, mode); + } + else + { +@@ -1759,7 +1759,7 @@ + mem = assign_stack_temp (GET_MODE (src), slen, 0); + emit_move_insn (mem, src); + tmps[i] = extract_bit_field (mem, bytelen * BITS_PER_UNIT, +- 0, 1, NULL_RTX, mode, mode); ++ 0, 1, false, NULL_RTX, mode, mode); + } + } + /* FIXME: A SIMD parallel will eventually lead to a subreg of a +@@ -1800,7 +1800,7 @@ + tmps[i] = src; + else + tmps[i] = extract_bit_field (src, bytelen * BITS_PER_UNIT, +- bytepos * BITS_PER_UNIT, 1, NULL_RTX, ++ bytepos * BITS_PER_UNIT, 1, false, NULL_RTX, + mode, mode); + + if (shift) +@@ -2213,7 +2213,7 @@ + bitpos for the destination store (left justified). */ + store_bit_field (dst, bitsize, bitpos % BITS_PER_WORD, copy_mode, + extract_bit_field (src, bitsize, +- xbitpos % BITS_PER_WORD, 1, ++ xbitpos % BITS_PER_WORD, 1, false, + NULL_RTX, copy_mode, copy_mode)); + } + +@@ -2970,7 +2970,7 @@ + } + + return extract_bit_field (cplx, ibitsize, imag_p ? ibitsize : 0, +- true, NULL_RTX, imode, imode); ++ true, false, NULL_RTX, imode, imode); + } + + /* A subroutine of emit_move_insn_1. Yet another lowpart generator. +@@ -4233,6 +4233,13 @@ + + to_rtx = expand_normal (tem); + ++ /* If the bitfield is volatile, we want to access it in the ++ field's mode, not the computed mode. */ ++ if (volatilep ++ && GET_CODE (to_rtx) == MEM ++ && flag_strict_volatile_bitfields > 0) ++ to_rtx = adjust_address (to_rtx, mode1, 0); ++ + if (offset != 0) + { + enum machine_mode address_mode; +@@ -4362,7 +4369,10 @@ + && op_mode1 != VOIDmode) + reg = copy_to_mode_reg (op_mode1, reg); + +- insn = GEN_FCN (icode) (mem, reg); ++ insn = GEN_FCN (icode) (mem, reg); ++ /* The movmisalign pattern cannot fail, else the assignment would ++ silently be omitted. */ ++ gcc_assert (insn != NULL_RTX); + emit_insn (insn); + return; + } +@@ -4730,7 +4740,10 @@ + /* If store_expr stores a DECL whose DECL_RTL(exp) == TARGET, + but TARGET is not valid memory reference, TEMP will differ + from TARGET although it is really the same location. */ +- && !(alt_rtl && rtx_equal_p (alt_rtl, target)) ++ && !(alt_rtl ++ && rtx_equal_p (alt_rtl, target) ++ && !side_effects_p (alt_rtl) ++ && !side_effects_p (target)) + /* If there's nothing to copy, don't bother. Don't call + expr_size unless necessary, because some front-ends (C++) + expr_size-hook must not be given objects that are not +@@ -5838,6 +5851,8 @@ + || bitpos % GET_MODE_ALIGNMENT (mode)) + && SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (target))) + || (bitpos % BITS_PER_UNIT != 0))) ++ || (bitsize >= 0 && mode != BLKmode ++ && GET_MODE_BITSIZE (mode) > bitsize) + /* If the RHS and field are a constant size and the size of the + RHS isn't the same size as the bitfield, we must use bitfield + operations. */ +@@ -5990,6 +6005,12 @@ + mode = DECL_MODE (field); + else if (DECL_MODE (field) == BLKmode) + blkmode_bitfield = true; ++ else if (TREE_THIS_VOLATILE (exp) ++ && flag_strict_volatile_bitfields > 0) ++ /* Volatile bitfields should be accessed in the mode of the ++ field's type, not the mode computed based on the bit ++ size. */ ++ mode = TYPE_MODE (DECL_BIT_FIELD_TYPE (field)); + + *punsignedp = DECL_UNSIGNED (field); + } +@@ -7221,10 +7242,7 @@ + optab this_optab; + rtx subtarget, original_target; + int ignore; +- tree subexp0, subexp1; + bool reduce_bit_field; +- gimple subexp0_def, subexp1_def; +- tree top0, top1; + location_t loc = ops->location; + tree treeop0, treeop1; + #define REDUCE_BIT_FIELD(expr) (reduce_bit_field \ +@@ -7244,7 +7262,8 @@ + exactly those that are valid in gimple expressions that aren't + GIMPLE_SINGLE_RHS (or invalid). */ + gcc_assert (get_gimple_rhs_class (code) == GIMPLE_UNARY_RHS +- || get_gimple_rhs_class (code) == GIMPLE_BINARY_RHS); ++ || get_gimple_rhs_class (code) == GIMPLE_BINARY_RHS ++ || get_gimple_rhs_class (code) == GIMPLE_TERNARY_RHS); + + ignore = (target == const0_rtx + || ((CONVERT_EXPR_CODE_P (code) +@@ -7419,58 +7438,6 @@ + fold_convert_loc (loc, ssizetype, + treeop1)); + case PLUS_EXPR: +- +- /* Check if this is a case for multiplication and addition. */ +- if ((TREE_CODE (type) == INTEGER_TYPE +- || TREE_CODE (type) == FIXED_POINT_TYPE) +- && (subexp0_def = get_def_for_expr (treeop0, +- MULT_EXPR))) +- { +- tree subsubexp0, subsubexp1; +- gimple subsubexp0_def, subsubexp1_def; +- enum tree_code this_code; +- +- this_code = TREE_CODE (type) == INTEGER_TYPE ? NOP_EXPR +- : FIXED_CONVERT_EXPR; +- subsubexp0 = gimple_assign_rhs1 (subexp0_def); +- subsubexp0_def = get_def_for_expr (subsubexp0, this_code); +- subsubexp1 = gimple_assign_rhs2 (subexp0_def); +- subsubexp1_def = get_def_for_expr (subsubexp1, this_code); +- if (subsubexp0_def && subsubexp1_def +- && (top0 = gimple_assign_rhs1 (subsubexp0_def)) +- && (top1 = gimple_assign_rhs1 (subsubexp1_def)) +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- < TYPE_PRECISION (TREE_TYPE (subsubexp0))) +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- == TYPE_PRECISION (TREE_TYPE (top1))) +- && (TYPE_UNSIGNED (TREE_TYPE (top0)) +- == TYPE_UNSIGNED (TREE_TYPE (top1)))) +- { +- tree op0type = TREE_TYPE (top0); +- enum machine_mode innermode = TYPE_MODE (op0type); +- bool zextend_p = TYPE_UNSIGNED (op0type); +- bool sat_p = TYPE_SATURATING (TREE_TYPE (subsubexp0)); +- if (sat_p == 0) +- this_optab = zextend_p ? umadd_widen_optab : smadd_widen_optab; +- else +- this_optab = zextend_p ? usmadd_widen_optab +- : ssmadd_widen_optab; +- if (mode == GET_MODE_2XWIDER_MODE (innermode) +- && (optab_handler (this_optab, mode)->insn_code +- != CODE_FOR_nothing)) +- { +- expand_operands (top0, top1, NULL_RTX, &op0, &op1, +- EXPAND_NORMAL); +- op2 = expand_expr (treeop1, subtarget, +- VOIDmode, EXPAND_NORMAL); +- temp = expand_ternary_op (mode, this_optab, op0, op1, op2, +- target, unsignedp); +- gcc_assert (temp); +- return REDUCE_BIT_FIELD (temp); +- } +- } +- } +- + /* If we are adding a constant, a VAR_DECL that is sp, fp, or ap, and + something else, make sure we add the register to the constant and + then to the other thing. This case can occur during strength +@@ -7585,57 +7552,6 @@ + return REDUCE_BIT_FIELD (simplify_gen_binary (PLUS, mode, op0, op1)); + + case MINUS_EXPR: +- /* Check if this is a case for multiplication and subtraction. */ +- if ((TREE_CODE (type) == INTEGER_TYPE +- || TREE_CODE (type) == FIXED_POINT_TYPE) +- && (subexp1_def = get_def_for_expr (treeop1, +- MULT_EXPR))) +- { +- tree subsubexp0, subsubexp1; +- gimple subsubexp0_def, subsubexp1_def; +- enum tree_code this_code; +- +- this_code = TREE_CODE (type) == INTEGER_TYPE ? NOP_EXPR +- : FIXED_CONVERT_EXPR; +- subsubexp0 = gimple_assign_rhs1 (subexp1_def); +- subsubexp0_def = get_def_for_expr (subsubexp0, this_code); +- subsubexp1 = gimple_assign_rhs2 (subexp1_def); +- subsubexp1_def = get_def_for_expr (subsubexp1, this_code); +- if (subsubexp0_def && subsubexp1_def +- && (top0 = gimple_assign_rhs1 (subsubexp0_def)) +- && (top1 = gimple_assign_rhs1 (subsubexp1_def)) +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- < TYPE_PRECISION (TREE_TYPE (subsubexp0))) +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- == TYPE_PRECISION (TREE_TYPE (top1))) +- && (TYPE_UNSIGNED (TREE_TYPE (top0)) +- == TYPE_UNSIGNED (TREE_TYPE (top1)))) +- { +- tree op0type = TREE_TYPE (top0); +- enum machine_mode innermode = TYPE_MODE (op0type); +- bool zextend_p = TYPE_UNSIGNED (op0type); +- bool sat_p = TYPE_SATURATING (TREE_TYPE (subsubexp0)); +- if (sat_p == 0) +- this_optab = zextend_p ? umsub_widen_optab : smsub_widen_optab; +- else +- this_optab = zextend_p ? usmsub_widen_optab +- : ssmsub_widen_optab; +- if (mode == GET_MODE_2XWIDER_MODE (innermode) +- && (optab_handler (this_optab, mode)->insn_code +- != CODE_FOR_nothing)) +- { +- expand_operands (top0, top1, NULL_RTX, &op0, &op1, +- EXPAND_NORMAL); +- op2 = expand_expr (treeop0, subtarget, +- VOIDmode, EXPAND_NORMAL); +- temp = expand_ternary_op (mode, this_optab, op0, op1, op2, +- target, unsignedp); +- gcc_assert (temp); +- return REDUCE_BIT_FIELD (temp); +- } +- } +- } +- + /* For initializers, we are allowed to return a MINUS of two + symbolic constants. Here we handle all cases when both operands + are constant. */ +@@ -7676,13 +7592,15 @@ + + goto binop2; + +- case MULT_EXPR: +- /* If this is a fixed-point operation, then we cannot use the code +- below because "expand_mult" doesn't support sat/no-sat fixed-point +- multiplications. */ +- if (ALL_FIXED_POINT_MODE_P (mode)) +- goto binop; ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, EXPAND_NORMAL); ++ op2 = expand_normal (ops->op2); ++ target = expand_widen_pattern_expr (ops, op0, op1, op2, ++ target, unsignedp); ++ return target; + ++ case WIDEN_MULT_EXPR: + /* If first operand is constant, swap them. + Thus the following special case checks need only + check the second operand. */ +@@ -7693,123 +7611,61 @@ + treeop1 = t1; + } + +- /* Attempt to return something suitable for generating an +- indexed address, for machines that support that. */ +- +- if (modifier == EXPAND_SUM && mode == ptr_mode +- && host_integerp (treeop1, 0)) +- { +- tree exp1 = treeop1; +- +- op0 = expand_expr (treeop0, subtarget, VOIDmode, +- EXPAND_SUM); +- +- if (!REG_P (op0)) +- op0 = force_operand (op0, NULL_RTX); +- if (!REG_P (op0)) +- op0 = copy_to_mode_reg (mode, op0); +- +- return REDUCE_BIT_FIELD (gen_rtx_MULT (mode, op0, +- gen_int_mode (tree_low_cst (exp1, 0), +- TYPE_MODE (TREE_TYPE (exp1))))); +- } +- +- if (modifier == EXPAND_STACK_PARM) +- target = 0; +- +- /* Check for multiplying things that have been extended +- from a narrower type. If this machine supports multiplying +- in that narrower type with a result in the desired type, +- do it that way, and avoid the explicit type-conversion. */ +- +- subexp0 = treeop0; +- subexp1 = treeop1; +- subexp0_def = get_def_for_expr (subexp0, NOP_EXPR); +- subexp1_def = get_def_for_expr (subexp1, NOP_EXPR); +- top0 = top1 = NULL_TREE; +- + /* First, check if we have a multiplication of one signed and one + unsigned operand. */ +- if (subexp0_def +- && (top0 = gimple_assign_rhs1 (subexp0_def)) +- && subexp1_def +- && (top1 = gimple_assign_rhs1 (subexp1_def)) +- && TREE_CODE (type) == INTEGER_TYPE +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- < TYPE_PRECISION (TREE_TYPE (subexp0))) +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- == TYPE_PRECISION (TREE_TYPE (top1))) +- && (TYPE_UNSIGNED (TREE_TYPE (top0)) +- != TYPE_UNSIGNED (TREE_TYPE (top1)))) ++ if (TREE_CODE (treeop1) != INTEGER_CST ++ && (TYPE_UNSIGNED (TREE_TYPE (treeop0)) ++ != TYPE_UNSIGNED (TREE_TYPE (treeop1)))) + { +- enum machine_mode innermode +- = TYPE_MODE (TREE_TYPE (top0)); ++ enum machine_mode innermode = TYPE_MODE (TREE_TYPE (treeop0)); + this_optab = usmul_widen_optab; +- if (mode == GET_MODE_WIDER_MODE (innermode)) ++ if (mode == GET_MODE_2XWIDER_MODE (innermode)) + { + if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing) + { +- if (TYPE_UNSIGNED (TREE_TYPE (top0))) +- expand_operands (top0, top1, NULL_RTX, &op0, &op1, ++ if (TYPE_UNSIGNED (TREE_TYPE (treeop0))) ++ expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, + EXPAND_NORMAL); + else +- expand_operands (top0, top1, NULL_RTX, &op1, &op0, ++ expand_operands (treeop0, treeop1, NULL_RTX, &op1, &op0, + EXPAND_NORMAL); +- + goto binop3; + } + } + } +- /* Check for a multiplication with matching signedness. If +- valid, TOP0 and TOP1 were set in the previous if +- condition. */ +- else if (top0 +- && TREE_CODE (type) == INTEGER_TYPE +- && (TYPE_PRECISION (TREE_TYPE (top0)) +- < TYPE_PRECISION (TREE_TYPE (subexp0))) +- && ((TREE_CODE (subexp1) == INTEGER_CST +- && int_fits_type_p (subexp1, TREE_TYPE (top0)) +- /* Don't use a widening multiply if a shift will do. */ +- && ((GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (subexp1))) +- > HOST_BITS_PER_WIDE_INT) +- || exact_log2 (TREE_INT_CST_LOW (subexp1)) < 0)) +- || +- (top1 +- && (TYPE_PRECISION (TREE_TYPE (top1)) +- == TYPE_PRECISION (TREE_TYPE (top0)) +- /* If both operands are extended, they must either both +- be zero-extended or both be sign-extended. */ +- && (TYPE_UNSIGNED (TREE_TYPE (top1)) +- == TYPE_UNSIGNED (TREE_TYPE (top0))))))) ++ /* Check for a multiplication with matching signedness. */ ++ else if ((TREE_CODE (treeop1) == INTEGER_CST ++ && int_fits_type_p (treeop1, TREE_TYPE (treeop0))) ++ || (TYPE_UNSIGNED (TREE_TYPE (treeop1)) ++ == TYPE_UNSIGNED (TREE_TYPE (treeop0)))) + { +- tree op0type = TREE_TYPE (top0); ++ tree op0type = TREE_TYPE (treeop0); + enum machine_mode innermode = TYPE_MODE (op0type); + bool zextend_p = TYPE_UNSIGNED (op0type); + optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab; + this_optab = zextend_p ? umul_widen_optab : smul_widen_optab; + +- if (mode == GET_MODE_2XWIDER_MODE (innermode)) ++ if (mode == GET_MODE_2XWIDER_MODE (innermode) ++ && TREE_CODE (treeop0) != INTEGER_CST) + { + if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing) + { +- if (TREE_CODE (subexp1) == INTEGER_CST) +- expand_operands (top0, subexp1, NULL_RTX, &op0, &op1, +- EXPAND_NORMAL); +- else +- expand_operands (top0, top1, NULL_RTX, &op0, &op1, +- EXPAND_NORMAL); +- goto binop3; ++ expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, ++ EXPAND_NORMAL); ++ temp = expand_widening_mult (mode, op0, op1, target, ++ unsignedp, this_optab); ++ return REDUCE_BIT_FIELD (temp); + } +- else if (optab_handler (other_optab, mode)->insn_code != CODE_FOR_nothing +- && innermode == word_mode) ++ if (optab_handler (other_optab, mode)->insn_code != CODE_FOR_nothing ++ && innermode == word_mode) + { + rtx htem, hipart; +- op0 = expand_normal (top0); +- if (TREE_CODE (subexp1) == INTEGER_CST) ++ op0 = expand_normal (treeop0); ++ if (TREE_CODE (treeop1) == INTEGER_CST) + op1 = convert_modes (innermode, mode, +- expand_normal (subexp1), unsignedp); ++ expand_normal (treeop1), unsignedp); + else +- op1 = expand_normal (top1); ++ op1 = expand_normal (treeop1); + temp = expand_binop (mode, other_optab, op0, op1, target, + unsignedp, OPTAB_LIB_WIDEN); + hipart = gen_highpart (innermode, temp); +@@ -7822,7 +7678,53 @@ + } + } + } +- expand_operands (subexp0, subexp1, subtarget, &op0, &op1, EXPAND_NORMAL); ++ treeop0 = fold_build1 (CONVERT_EXPR, type, treeop0); ++ treeop1 = fold_build1 (CONVERT_EXPR, type, treeop1); ++ expand_operands (treeop0, treeop1, subtarget, &op0, &op1, EXPAND_NORMAL); ++ return REDUCE_BIT_FIELD (expand_mult (mode, op0, op1, target, unsignedp)); ++ ++ case MULT_EXPR: ++ /* If this is a fixed-point operation, then we cannot use the code ++ below because "expand_mult" doesn't support sat/no-sat fixed-point ++ multiplications. */ ++ if (ALL_FIXED_POINT_MODE_P (mode)) ++ goto binop; ++ ++ /* If first operand is constant, swap them. ++ Thus the following special case checks need only ++ check the second operand. */ ++ if (TREE_CODE (treeop0) == INTEGER_CST) ++ { ++ tree t1 = treeop0; ++ treeop0 = treeop1; ++ treeop1 = t1; ++ } ++ ++ /* Attempt to return something suitable for generating an ++ indexed address, for machines that support that. */ ++ ++ if (modifier == EXPAND_SUM && mode == ptr_mode ++ && host_integerp (treeop1, 0)) ++ { ++ tree exp1 = treeop1; ++ ++ op0 = expand_expr (treeop0, subtarget, VOIDmode, ++ EXPAND_SUM); ++ ++ if (!REG_P (op0)) ++ op0 = force_operand (op0, NULL_RTX); ++ if (!REG_P (op0)) ++ op0 = copy_to_mode_reg (mode, op0); ++ ++ return REDUCE_BIT_FIELD (gen_rtx_MULT (mode, op0, ++ gen_int_mode (tree_low_cst (exp1, 0), ++ TYPE_MODE (TREE_TYPE (exp1))))); ++ } ++ ++ if (modifier == EXPAND_STACK_PARM) ++ target = 0; ++ ++ expand_operands (treeop0, treeop1, subtarget, &op0, &op1, EXPAND_NORMAL); + return REDUCE_BIT_FIELD (expand_mult (mode, op0, op1, target, unsignedp)); + + case TRUNC_DIV_EXPR: +@@ -8308,6 +8210,8 @@ + location_t loc = EXPR_LOCATION (exp); + struct separate_ops ops; + tree treeop0, treeop1, treeop2; ++ tree ssa_name = NULL_TREE; ++ gimple g; + + type = TREE_TYPE (exp); + mode = TYPE_MODE (type); +@@ -8420,15 +8324,17 @@ + base variable. This unnecessarily allocates a pseudo, see how we can + reuse it, if partition base vars have it set already. */ + if (!currently_expanding_to_rtl) +- return expand_expr_real_1 (SSA_NAME_VAR (exp), target, tmode, modifier, NULL); +- { +- gimple g = get_gimple_for_ssa_name (exp); +- if (g) +- return expand_expr_real (gimple_assign_rhs_to_tree (g), target, +- tmode, modifier, NULL); +- } +- decl_rtl = get_rtx_for_ssa_name (exp); +- exp = SSA_NAME_VAR (exp); ++ return expand_expr_real_1 (SSA_NAME_VAR (exp), target, tmode, modifier, ++ NULL); ++ ++ g = get_gimple_for_ssa_name (exp); ++ if (g) ++ return expand_expr_real (gimple_assign_rhs_to_tree (g), target, tmode, ++ modifier, NULL); ++ ++ ssa_name = exp; ++ decl_rtl = get_rtx_for_ssa_name (ssa_name); ++ exp = SSA_NAME_VAR (ssa_name); + goto expand_decl_rtl; + + case PARM_DECL: +@@ -8458,6 +8364,19 @@ + expand_decl_rtl: + gcc_assert (decl_rtl); + decl_rtl = copy_rtx (decl_rtl); ++ /* Record writes to register variables. */ ++ if (modifier == EXPAND_WRITE && REG_P (decl_rtl) ++ && REGNO (decl_rtl) < FIRST_PSEUDO_REGISTER) ++ { ++ int i = REGNO (decl_rtl); ++ int nregs = hard_regno_nregs[i][GET_MODE (decl_rtl)]; ++ while (nregs) ++ { ++ SET_HARD_REG_BIT (crtl->asm_clobbers, i); ++ i++; ++ nregs--; ++ } ++ } + + /* Ensure variable marked as used even if it doesn't go through + a parser. If it hasn't be used yet, write out an external +@@ -8517,15 +8436,21 @@ + /* If the mode of DECL_RTL does not match that of the decl, it + must be a promoted value. We return a SUBREG of the wanted mode, + but mark it so that we know that it was already extended. */ +- +- if (REG_P (decl_rtl) +- && GET_MODE (decl_rtl) != DECL_MODE (exp)) ++ if (REG_P (decl_rtl) && GET_MODE (decl_rtl) != DECL_MODE (exp)) + { + enum machine_mode pmode; + +- /* Get the signedness used for this variable. Ensure we get the +- same mode we got when the variable was declared. */ +- pmode = promote_decl_mode (exp, &unsignedp); ++ /* Get the signedness to be used for this variable. Ensure we get ++ the same mode we got when the variable was declared. */ ++ if (code == SSA_NAME ++ && (g = SSA_NAME_DEF_STMT (ssa_name)) ++ && gimple_code (g) == GIMPLE_CALL) ++ pmode = promote_function_mode (type, mode, &unsignedp, ++ TREE_TYPE ++ (TREE_TYPE (gimple_call_fn (g))), ++ 2); ++ else ++ pmode = promote_decl_mode (exp, &unsignedp); + gcc_assert (GET_MODE (decl_rtl) == pmode); + + temp = gen_lowpart_SUBREG (mode, decl_rtl); +@@ -8729,6 +8654,7 @@ + + /* Nor can the insn generator. */ + insn = GEN_FCN (icode) (reg, temp); ++ gcc_assert (insn != NULL_RTX); + emit_insn (insn); + + return reg; +@@ -8941,6 +8867,7 @@ + HOST_WIDE_INT bitsize, bitpos; + tree offset; + int volatilep = 0, must_force_mem; ++ bool packedp = false; + tree tem = get_inner_reference (exp, &bitsize, &bitpos, &offset, + &mode1, &unsignedp, &volatilep, true); + rtx orig_op0, memloc; +@@ -8950,6 +8877,11 @@ + infinitely recurse. */ + gcc_assert (tem != exp); + ++ if (TYPE_PACKED (TREE_TYPE (TREE_OPERAND (exp, 0))) ++ || (TREE_CODE (TREE_OPERAND (exp, 1)) == FIELD_DECL ++ && DECL_PACKED (TREE_OPERAND (exp, 1)))) ++ packedp = true; ++ + /* If TEM's type is a union of variable size, pass TARGET to the inner + computation, since it will need a temporary and TARGET is known + to have to do. This occurs in unchecked conversion in Ada. */ +@@ -8966,6 +8898,14 @@ + || modifier == EXPAND_STACK_PARM) + ? modifier : EXPAND_NORMAL); + ++ ++ /* If the bitfield is volatile, we want to access it in the ++ field's mode, not the computed mode. */ ++ if (volatilep ++ && GET_CODE (op0) == MEM ++ && flag_strict_volatile_bitfields > 0) ++ op0 = adjust_address (op0, mode1, 0); ++ + mode2 + = CONSTANT_P (op0) ? TYPE_MODE (TREE_TYPE (tem)) : GET_MODE (op0); + +@@ -9091,6 +9031,9 @@ + && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT + && modifier != EXPAND_CONST_ADDRESS + && modifier != EXPAND_INITIALIZER) ++ /* If the field is volatile, we always want an aligned ++ access. */ ++ || (volatilep && flag_strict_volatile_bitfields > 0) + /* If the field isn't aligned enough to fetch as a memref, + fetch it as a bit field. */ + || (mode1 != BLKmode +@@ -9151,7 +9094,7 @@ + if (MEM_P (op0) && REG_P (XEXP (op0, 0))) + mark_reg_pointer (XEXP (op0, 0), MEM_ALIGN (op0)); + +- op0 = extract_bit_field (op0, bitsize, bitpos, unsignedp, ++ op0 = extract_bit_field (op0, bitsize, bitpos, unsignedp, packedp, + (modifier == EXPAND_STACK_PARM + ? NULL_RTX : target), + ext_mode, ext_mode); +--- a/src/gcc/expr.h ++++ b/src/gcc/expr.h +@@ -802,7 +802,7 @@ + extern void store_bit_field (rtx, unsigned HOST_WIDE_INT, + unsigned HOST_WIDE_INT, enum machine_mode, rtx); + extern rtx extract_bit_field (rtx, unsigned HOST_WIDE_INT, +- unsigned HOST_WIDE_INT, int, rtx, ++ unsigned HOST_WIDE_INT, int, bool, rtx, + enum machine_mode, enum machine_mode); + extern rtx extract_low_bits (enum machine_mode, enum machine_mode, rtx); + extern rtx expand_mult (enum machine_mode, rtx, rtx, rtx, int); +--- a/src/gcc/final.c ++++ b/src/gcc/final.c +@@ -2428,7 +2428,7 @@ + delete_insn (insn); + break; + } +- else if (GET_CODE (SET_SRC (body)) == RETURN) ++ else if (ANY_RETURN_P (SET_SRC (body))) + /* Replace (set (pc) (return)) with (return). */ + PATTERN (insn) = body = SET_SRC (body); + +--- a/src/gcc/fold-const.c ++++ b/src/gcc/fold-const.c +@@ -4217,11 +4217,16 @@ + + /* See if we can find a mode to refer to this field. We should be able to, + but fail if we can't. */ +- nmode = get_best_mode (lbitsize, lbitpos, +- const_p ? TYPE_ALIGN (TREE_TYPE (linner)) +- : MIN (TYPE_ALIGN (TREE_TYPE (linner)), +- TYPE_ALIGN (TREE_TYPE (rinner))), +- word_mode, lvolatilep || rvolatilep); ++ if (lvolatilep ++ && GET_MODE_BITSIZE (lmode) > 0 ++ && flag_strict_volatile_bitfields > 0) ++ nmode = lmode; ++ else ++ nmode = get_best_mode (lbitsize, lbitpos, ++ const_p ? TYPE_ALIGN (TREE_TYPE (linner)) ++ : MIN (TYPE_ALIGN (TREE_TYPE (linner)), ++ TYPE_ALIGN (TREE_TYPE (rinner))), ++ word_mode, lvolatilep || rvolatilep); + if (nmode == VOIDmode) + return 0; + +@@ -5751,6 +5756,76 @@ + const_binop (BIT_XOR_EXPR, c, temp, 0)); + } + ++/* For an expression that has the form ++ (A && B) || ~B ++ or ++ (A || B) && ~B, ++ we can drop one of the inner expressions and simplify to ++ A || ~B ++ or ++ A && ~B ++ LOC is the location of the resulting expression. OP is the inner ++ logical operation; the left-hand side in the examples above, while CMPOP ++ is the right-hand side. RHS_ONLY is used to prevent us from accidentally ++ removing a condition that guards another, as in ++ (A != NULL && A->...) || A == NULL ++ which we must not transform. If RHS_ONLY is true, only eliminate the ++ right-most operand of the inner logical operation. */ ++ ++static tree ++merge_truthop_with_opposite_arm (location_t loc, tree op, tree cmpop, ++ bool rhs_only) ++{ ++ tree type = TREE_TYPE (cmpop); ++ enum tree_code code = TREE_CODE (cmpop); ++ enum tree_code truthop_code = TREE_CODE (op); ++ tree lhs = TREE_OPERAND (op, 0); ++ tree rhs = TREE_OPERAND (op, 1); ++ tree orig_lhs = lhs, orig_rhs = rhs; ++ enum tree_code rhs_code = TREE_CODE (rhs); ++ enum tree_code lhs_code = TREE_CODE (lhs); ++ enum tree_code inv_code; ++ ++ if (TREE_SIDE_EFFECTS (op) || TREE_SIDE_EFFECTS (cmpop)) ++ return NULL_TREE; ++ ++ if (TREE_CODE_CLASS (code) != tcc_comparison) ++ return NULL_TREE; ++ ++ if (rhs_code == truthop_code) ++ { ++ tree newrhs = merge_truthop_with_opposite_arm (loc, rhs, cmpop, rhs_only); ++ if (newrhs != NULL_TREE) ++ { ++ rhs = newrhs; ++ rhs_code = TREE_CODE (rhs); ++ } ++ } ++ if (lhs_code == truthop_code && !rhs_only) ++ { ++ tree newlhs = merge_truthop_with_opposite_arm (loc, lhs, cmpop, false); ++ if (newlhs != NULL_TREE) ++ { ++ lhs = newlhs; ++ lhs_code = TREE_CODE (lhs); ++ } ++ } ++ ++ inv_code = invert_tree_comparison (code, HONOR_NANS (TYPE_MODE (type))); ++ if (inv_code == rhs_code ++ && operand_equal_p (TREE_OPERAND (rhs, 0), TREE_OPERAND (cmpop, 0), 0) ++ && operand_equal_p (TREE_OPERAND (rhs, 1), TREE_OPERAND (cmpop, 1), 0)) ++ return lhs; ++ if (!rhs_only && inv_code == lhs_code ++ && operand_equal_p (TREE_OPERAND (lhs, 0), TREE_OPERAND (cmpop, 0), 0) ++ && operand_equal_p (TREE_OPERAND (lhs, 1), TREE_OPERAND (cmpop, 1), 0)) ++ return rhs; ++ if (rhs != orig_rhs || lhs != orig_lhs) ++ return fold_build2_loc (loc, truthop_code, TREE_TYPE (cmpop), ++ lhs, rhs); ++ return NULL_TREE; ++} ++ + /* Find ways of folding logical expressions of LHS and RHS: + Try to merge two comparisons to the same innermost item. + Look for range tests like "ch >= '0' && ch <= '9'". +@@ -12555,6 +12630,22 @@ + if (0 != (tem = fold_range_test (loc, code, type, op0, op1))) + return tem; + ++ if ((code == TRUTH_ANDIF_EXPR && TREE_CODE (arg0) == TRUTH_ORIF_EXPR) ++ || (code == TRUTH_ORIF_EXPR && TREE_CODE (arg0) == TRUTH_ANDIF_EXPR)) ++ { ++ tem = merge_truthop_with_opposite_arm (loc, arg0, arg1, true); ++ if (tem) ++ return fold_build2_loc (loc, code, type, tem, arg1); ++ } ++ ++ if ((code == TRUTH_ANDIF_EXPR && TREE_CODE (arg1) == TRUTH_ORIF_EXPR) ++ || (code == TRUTH_ORIF_EXPR && TREE_CODE (arg1) == TRUTH_ANDIF_EXPR)) ++ { ++ tem = merge_truthop_with_opposite_arm (loc, arg1, arg0, false); ++ if (tem) ++ return fold_build2_loc (loc, code, type, arg0, tem); ++ } ++ + /* Check for the possibility of merging component references. If our + lhs is another similar operation, try to merge its rhs with our + rhs. Then try to merge our lhs and rhs. */ +--- a/src/gcc/fortran/ChangeLog ++++ b/src/gcc/fortran/ChangeLog +@@ -1,3 +1,74 @@ ++2011-02-19 Tobias Burnus ++ ++ PR fortran/47775 ++ * trans-expr.c (arrayfunc_assign_needs_temporary): Use ++ esym to check whether the specific procedure returns an ++ allocatable or pointer. ++ ++2011-02-14 Tobias Burnus ++ ++ PR fortran/47569 ++ * interface.c (compare_parameter): Avoid ICE with ++ character components. ++ ++2011-01-25 Tobias Burnus ++ ++ Backport from mainline ++ 2011-01-17 Jakub Jelinek ++ ++ PR fortran/47331 ++ * gfortran.h (struct gfc_omp_saved_state): New type. ++ (gfc_omp_save_and_clear_state, gfc_omp_restore_state): New prototypes. ++ * resolve.c (resolve_global_procedure): Call it around gfc_resolve ++ call. ++ * openmp.c (gfc_omp_save_and_clear_state, gfc_omp_restore_state): New ++ functions. ++ ++2011-01-25 Tobias Burnus ++ ++ PR fortran/47448 ++ * interface.c (gfc_check_operator_interface): Fix ++ defined-assignment check. ++ ++2011-01-21 Tobias Burnus ++ ++ PR fortran/47394 ++ * error.c (gfc_error_now, gfc_fatal_error, gfc_error_check): ++ Use defined instead of magic number exit status codes. ++ * scanner.c (include_line, gfc_new_file): Ditto. ++ * gfortranspec.c (lang_specific_driver): Ditto. ++ ++2011-01-16 Jakub Jelinek ++ ++ Backport from mainline ++ 2010-12-14 Jakub Jelinek ++ ++ PR fortran/46874 ++ * trans-openmp.c (gfc_trans_omp_array_reduction): Handle allocatable ++ dummy variables. ++ ++2011-01-16 Thomas Koenig ++ ++ Backport from trunk ++ PR fortran/45777 ++ * symbol.c (gfc_symbols_could_alias): Strip gfc_ prefix, ++ make static and move in front of its only caller, to ... ++ * trans-array.c (symbols_could_alias): ... here. ++ Pass information about pointer and target status as ++ arguments. Allocatable arrays don't alias anything ++ unless they have the POINTER attribute. ++ (gfc_could_be_alias): Keep track of pointer and target ++ status when following references. Also check if typespecs ++ of components match those of other components or symbols. ++ * gfortran.h: Remove prototype for gfc_symbols_could_alias. ++ ++2011-01-02 Thomas Koenig ++ ++ Backport from mainline ++ PR fortran/45338 ++ * resolve.c (resolve_operator): Mark function for user-defined ++ operator as referenced. ++ + 2010-12-16 Release Manager + + * GCC 4.5.2 released. +--- a/src/gcc/fortran/error.c ++++ b/src/gcc/fortran/error.c +@@ -939,7 +939,7 @@ + buffer_flag = i; + + if (flag_fatal_errors) +- exit (1); ++ exit (FATAL_EXIT_CODE); + } + + +@@ -956,7 +956,7 @@ + error_print (_("Fatal Error:"), _(gmsgid), argp); + va_end (argp); + +- exit (3); ++ exit (FATAL_EXIT_CODE); + } + + +@@ -1019,7 +1019,7 @@ + gfc_increment_error_count(); + + if (flag_fatal_errors) +- exit (1); ++ exit (FATAL_EXIT_CODE); + } + + return rc; +--- a/src/gcc/fortran/gfortran.h ++++ b/src/gcc/fortran/gfortran.h +@@ -2483,8 +2483,6 @@ + int gfc_get_ha_symbol (const char *, gfc_symbol **); + int gfc_get_ha_sym_tree (const char *, gfc_symtree **); + +-int gfc_symbols_could_alias (gfc_symbol *, gfc_symbol *); +- + void gfc_undo_symbols (void); + void gfc_commit_symbols (void); + void gfc_commit_symbol (gfc_symbol *); +@@ -2577,11 +2575,14 @@ + gfc_expr *gfc_get_parentheses (gfc_expr *); + + /* openmp.c */ ++struct gfc_omp_saved_state { void *ptrs[2]; int ints[1]; }; + void gfc_free_omp_clauses (gfc_omp_clauses *); + void gfc_resolve_omp_directive (gfc_code *, gfc_namespace *); + void gfc_resolve_do_iterator (gfc_code *, gfc_symbol *); + void gfc_resolve_omp_parallel_blocks (gfc_code *, gfc_namespace *); + void gfc_resolve_omp_do_blocks (gfc_code *, gfc_namespace *); ++void gfc_omp_save_and_clear_state (struct gfc_omp_saved_state *); ++void gfc_omp_restore_state (struct gfc_omp_saved_state *); + + /* expr.c */ + void gfc_free_actual_arglist (gfc_actual_arglist *); +--- a/src/gcc/fortran/gfortranspec.c ++++ b/src/gcc/fortran/gfortranspec.c +@@ -375,7 +375,7 @@ + You may redistribute copies of GNU Fortran\n\ + under the terms of the GNU General Public License.\n\ + For more information about these matters, see the file named COPYING\n\n")); +- exit (0); ++ exit (SUCCESS_EXIT_CODE); + break; + + case OPTION_help: +--- a/src/gcc/fortran/interface.c ++++ b/src/gcc/fortran/interface.c +@@ -624,11 +624,12 @@ + + /* Allowed are (per F2003, 12.3.2.1.2 Defined assignments): + - First argument an array with different rank than second, +- - Types and kinds do not conform, and ++ - First argument is a scalar and second an array, ++ - Types and kinds do not conform, or + - First argument is of derived type. */ + if (sym->formal->sym->ts.type != BT_DERIVED + && sym->formal->sym->ts.type != BT_CLASS +- && (r1 == 0 || r1 == r2) ++ && (r2 == 0 || r1 == r2) + && (sym->formal->sym->ts.type == sym->formal->next->sym->ts.type + || (gfc_numeric_ts (&sym->formal->sym->ts) + && gfc_numeric_ts (&sym->formal->next->sym->ts)))) +@@ -1385,7 +1386,7 @@ + int ranks_must_agree, int is_elemental, locus *where) + { + gfc_ref *ref; +- bool rank_check; ++ bool rank_check, is_pointer; + + /* If the formal arg has type BT_VOID, it's to one of the iso_c_binding + procs c_f_pointer or c_f_procpointer, and we need to accept most +@@ -1468,22 +1469,56 @@ + return 1; + + /* At this point, we are considering a scalar passed to an array. This +- is valid (cf. F95 12.4.1.1; F2003 12.4.1.2), ++ is valid (cf. F95 12.4.1.1, F2003 12.4.1.2, and F2008 12.5.2.4), + - if the actual argument is (a substring of) an element of a +- non-assumed-shape/non-pointer array; +- - (F2003) if the actual argument is of type character. */ ++ non-assumed-shape/non-pointer/non-polymorphic array; or ++ - (F2003) if the actual argument is of type character of default/c_char ++ kind. */ ++ ++ is_pointer = actual->expr_type == EXPR_VARIABLE ++ ? actual->symtree->n.sym->attr.pointer : false; + + for (ref = actual->ref; ref; ref = ref->next) +- if (ref->type == REF_ARRAY && ref->u.ar.type == AR_ELEMENT) +- break; ++ { ++ if (ref->type == REF_COMPONENT) ++ is_pointer = ref->u.c.component->attr.pointer; ++ else if (ref->type == REF_ARRAY && ref->u.ar.type == AR_ELEMENT ++ && ref->u.ar.dimen > 0 ++ && (!ref->next ++ || (ref->next->type == REF_SUBSTRING && !ref->next->next))) ++ break; ++ } + +- /* Not an array element. */ +- if (formal->ts.type == BT_CHARACTER +- && (ref == NULL +- || (actual->expr_type == EXPR_VARIABLE +- && (actual->symtree->n.sym->as->type == AS_ASSUMED_SHAPE +- || actual->symtree->n.sym->attr.pointer)))) ++ if (actual->ts.type == BT_CLASS && actual->expr_type != EXPR_NULL) + { ++ if (where) ++ gfc_error ("Polymorphic scalar passed to array dummy argument '%s' " ++ "at %L", formal->name, &actual->where); ++ return 0; ++ } ++ ++ if (actual->expr_type != EXPR_NULL && ref && actual->ts.type != BT_CHARACTER ++ && (is_pointer || ref->u.ar.as->type == AS_ASSUMED_SHAPE)) ++ { ++ if (where) ++ gfc_error ("Element of assumed-shaped or pointer " ++ "array passed to array dummy argument '%s' at %L", ++ formal->name, &actual->where); ++ return 0; ++ } ++ ++ if (actual->ts.type == BT_CHARACTER && actual->expr_type != EXPR_NULL ++ && (!ref || is_pointer || ref->u.ar.as->type == AS_ASSUMED_SHAPE)) ++ { ++ if (formal->ts.kind != 1 && (gfc_option.allow_std & GFC_STD_GNU) == 0) ++ { ++ if (where) ++ gfc_error ("Extension: Scalar non-default-kind, non-C_CHAR-kind " ++ "CHARACTER actual argument with array dummy argument " ++ "'%s' at %L", formal->name, &actual->where); ++ return 0; ++ } ++ + if (where && (gfc_option.allow_std & GFC_STD_F2003) == 0) + { + gfc_error ("Fortran 2003: Scalar CHARACTER actual argument with " +@@ -1496,7 +1531,8 @@ + else + return 1; + } +- else if (ref == NULL && actual->expr_type != EXPR_NULL) ++ ++ if (ref == NULL && actual->expr_type != EXPR_NULL) + { + if (where) + gfc_error ("Rank mismatch in argument '%s' at %L (%d and %d)", +@@ -1505,17 +1541,6 @@ + return 0; + } + +- if (actual->expr_type == EXPR_VARIABLE +- && actual->symtree->n.sym->as +- && (actual->symtree->n.sym->as->type == AS_ASSUMED_SHAPE +- || actual->symtree->n.sym->attr.pointer)) +- { +- if (where) +- gfc_error ("Element of assumed-shaped array passed to dummy " +- "argument '%s' at %L", formal->name, &actual->where); +- return 0; +- } +- + return 1; + } + +--- a/src/gcc/fortran/openmp.c ++++ b/src/gcc/fortran/openmp.c +@@ -1363,6 +1363,31 @@ + } + + ++/* Save and clear openmp.c private state. */ ++ ++void ++gfc_omp_save_and_clear_state (struct gfc_omp_saved_state *state) ++{ ++ state->ptrs[0] = omp_current_ctx; ++ state->ptrs[1] = omp_current_do_code; ++ state->ints[0] = omp_current_do_collapse; ++ omp_current_ctx = NULL; ++ omp_current_do_code = NULL; ++ omp_current_do_collapse = 0; ++} ++ ++ ++/* Restore openmp.c private state from the saved state. */ ++ ++void ++gfc_omp_restore_state (struct gfc_omp_saved_state *state) ++{ ++ omp_current_ctx = (struct omp_context *) state->ptrs[0]; ++ omp_current_do_code = (gfc_code *) state->ptrs[1]; ++ omp_current_do_collapse = state->ints[0]; ++} ++ ++ + /* Note a DO iterator variable. This is special in !$omp parallel + construct, where they are predetermined private. */ + +--- a/src/gcc/fortran/resolve.c ++++ b/src/gcc/fortran/resolve.c +@@ -1810,11 +1810,14 @@ + if (!gsym->ns->resolved) + { + gfc_dt_list *old_dt_list; ++ struct gfc_omp_saved_state old_omp_state; + + /* Stash away derived types so that the backend_decls do not + get mixed up. */ + old_dt_list = gfc_derived_types; + gfc_derived_types = NULL; ++ /* And stash away openmp state. */ ++ gfc_omp_save_and_clear_state (&old_omp_state); + + gfc_resolve (gsym->ns); + +@@ -1824,6 +1827,8 @@ + + /* Restore the derived types of this namespace. */ + gfc_derived_types = old_dt_list; ++ /* And openmp state. */ ++ gfc_omp_restore_state (&old_omp_state); + } + + /* Make sure that translation for the gsymbol occurs before +@@ -3577,9 +3582,12 @@ + sprintf (msg, _("Operand of user operator '%s' at %%L is %s"), + e->value.op.uop->name, gfc_typename (&op1->ts)); + else +- sprintf (msg, _("Operands of user operator '%s' at %%L are %s/%s"), +- e->value.op.uop->name, gfc_typename (&op1->ts), +- gfc_typename (&op2->ts)); ++ { ++ sprintf (msg, _("Operands of user operator '%s' at %%L are %s/%s"), ++ e->value.op.uop->name, gfc_typename (&op1->ts), ++ gfc_typename (&op2->ts)); ++ e->value.op.uop->op->sym->attr.referenced = 1; ++ } + + goto bad_op; + +--- a/src/gcc/fortran/scanner.c ++++ b/src/gcc/fortran/scanner.c +@@ -1841,7 +1841,7 @@ + + filename = gfc_widechar_to_char (begin, -1); + if (load_file (filename, NULL, false) == FAILURE) +- exit (1); ++ exit (FATAL_EXIT_CODE); + + gfc_free (filename); + return true; +@@ -2045,7 +2045,7 @@ + printf ("%s:%3d %s\n", LOCATION_FILE (line_head->location), + LOCATION_LINE (line_head->location), line_head->line); + +- exit (0); ++ exit (SUCCESS_EXIT_CODE); + #endif + + return result; +--- a/src/gcc/fortran/symbol.c ++++ b/src/gcc/fortran/symbol.c +@@ -2733,41 +2733,6 @@ + return i; + } + +-/* Return true if both symbols could refer to the same data object. Does +- not take account of aliasing due to equivalence statements. */ +- +-int +-gfc_symbols_could_alias (gfc_symbol *lsym, gfc_symbol *rsym) +-{ +- /* Aliasing isn't possible if the symbols have different base types. */ +- if (gfc_compare_types (&lsym->ts, &rsym->ts) == 0) +- return 0; +- +- /* Pointers can point to other pointers, target objects and allocatable +- objects. Two allocatable objects cannot share the same storage. */ +- if (lsym->attr.pointer +- && (rsym->attr.pointer || rsym->attr.allocatable || rsym->attr.target)) +- return 1; +- if (lsym->attr.target && rsym->attr.pointer) +- return 1; +- if (lsym->attr.allocatable && rsym->attr.pointer) +- return 1; +- +- /* Special case: Argument association, cf. F90 12.4.1.6, F2003 12.4.1.7 +- and F2008 12.5.2.13 items 3b and 4b. The pointer case (a) is already +- checked above. */ +- if (lsym->attr.target && rsym->attr.target +- && ((lsym->attr.dummy +- && (!lsym->attr.dimension || lsym->as->type == AS_ASSUMED_SHAPE)) +- || (rsym->attr.dummy +- && (!rsym->attr.dimension +- || rsym->as->type == AS_ASSUMED_SHAPE)))) +- return 1; +- +- return 0; +-} +- +- + /* Undoes all the changes made to symbols in the current statement. + This subroutine is made simpler due to the fact that attributes are + never removed once added. */ +--- a/src/gcc/fortran/trans-array.c ++++ b/src/gcc/fortran/trans-array.c +@@ -3389,6 +3389,37 @@ + } + } + ++/* Return true if both symbols could refer to the same data object. Does ++ not take account of aliasing due to equivalence statements. */ ++ ++static int ++symbols_could_alias (gfc_symbol *lsym, gfc_symbol *rsym, bool lsym_pointer, ++ bool lsym_target, bool rsym_pointer, bool rsym_target) ++{ ++ /* Aliasing isn't possible if the symbols have different base types. */ ++ if (gfc_compare_types (&lsym->ts, &rsym->ts) == 0) ++ return 0; ++ ++ /* Pointers can point to other pointers and target objects. */ ++ ++ if ((lsym_pointer && (rsym_pointer || rsym_target)) ++ || (rsym_pointer && (lsym_pointer || lsym_target))) ++ return 1; ++ ++ /* Special case: Argument association, cf. F90 12.4.1.6, F2003 12.4.1.7 ++ and F2008 12.5.2.13 items 3b and 4b. The pointer case (a) is already ++ checked above. */ ++ if (lsym->attr.target && rsym->attr.target ++ && ((lsym->attr.dummy ++ && (!lsym->attr.dimension || lsym->as->type == AS_ASSUMED_SHAPE)) ++ || (rsym->attr.dummy ++ && (!rsym->attr.dimension ++ || rsym->as->type == AS_ASSUMED_SHAPE)))) ++ return 1; ++ ++ return 0; ++} ++ + + /* Return true if the two SS could be aliased, i.e. both point to the same data + object. */ +@@ -3401,10 +3432,18 @@ + gfc_ref *rref; + gfc_symbol *lsym; + gfc_symbol *rsym; ++ bool lsym_pointer, lsym_target, rsym_pointer, rsym_target; + + lsym = lss->expr->symtree->n.sym; + rsym = rss->expr->symtree->n.sym; +- if (gfc_symbols_could_alias (lsym, rsym)) ++ ++ lsym_pointer = lsym->attr.pointer; ++ lsym_target = lsym->attr.target; ++ rsym_pointer = rsym->attr.pointer; ++ rsym_target = rsym->attr.target; ++ ++ if (symbols_could_alias (lsym, rsym, lsym_pointer, lsym_target, ++ rsym_pointer, rsym_target)) + return 1; + + if (rsym->ts.type != BT_DERIVED +@@ -3419,27 +3458,75 @@ + if (lref->type != REF_COMPONENT) + continue; + +- if (gfc_symbols_could_alias (lref->u.c.sym, rsym)) ++ lsym_pointer = lsym_pointer || lref->u.c.sym->attr.pointer; ++ lsym_target = lsym_target || lref->u.c.sym->attr.target; ++ ++ if (symbols_could_alias (lref->u.c.sym, rsym, lsym_pointer, lsym_target, ++ rsym_pointer, rsym_target)) + return 1; + ++ if ((lsym_pointer && (rsym_pointer || rsym_target)) ++ || (rsym_pointer && (lsym_pointer || lsym_target))) ++ { ++ if (gfc_compare_types (&lref->u.c.component->ts, ++ &rsym->ts)) ++ return 1; ++ } ++ + for (rref = rss->expr->ref; rref != rss->data.info.ref; + rref = rref->next) + { + if (rref->type != REF_COMPONENT) + continue; + +- if (gfc_symbols_could_alias (lref->u.c.sym, rref->u.c.sym)) ++ rsym_pointer = rsym_pointer || rref->u.c.sym->attr.pointer; ++ rsym_target = lsym_target || rref->u.c.sym->attr.target; ++ ++ if (symbols_could_alias (lref->u.c.sym, rref->u.c.sym, ++ lsym_pointer, lsym_target, ++ rsym_pointer, rsym_target)) + return 1; ++ ++ if ((lsym_pointer && (rsym_pointer || rsym_target)) ++ || (rsym_pointer && (lsym_pointer || lsym_target))) ++ { ++ if (gfc_compare_types (&lref->u.c.component->ts, ++ &rref->u.c.sym->ts)) ++ return 1; ++ if (gfc_compare_types (&lref->u.c.sym->ts, ++ &rref->u.c.component->ts)) ++ return 1; ++ if (gfc_compare_types (&lref->u.c.component->ts, ++ &rref->u.c.component->ts)) ++ return 1; ++ } + } + } + ++ lsym_pointer = lsym->attr.pointer; ++ lsym_target = lsym->attr.target; ++ lsym_pointer = lsym->attr.pointer; ++ lsym_target = lsym->attr.target; ++ + for (rref = rss->expr->ref; rref != rss->data.info.ref; rref = rref->next) + { + if (rref->type != REF_COMPONENT) + break; + +- if (gfc_symbols_could_alias (rref->u.c.sym, lsym)) ++ rsym_pointer = rsym_pointer || rref->u.c.sym->attr.pointer; ++ rsym_target = lsym_target || rref->u.c.sym->attr.target; ++ ++ if (symbols_could_alias (rref->u.c.sym, lsym, ++ lsym_pointer, lsym_target, ++ rsym_pointer, rsym_target)) + return 1; ++ ++ if ((lsym_pointer && (rsym_pointer || rsym_target)) ++ || (rsym_pointer && (lsym_pointer || lsym_target))) ++ { ++ if (gfc_compare_types (&lsym->ts, &rref->u.c.component->ts)) ++ return 1; ++ } + } + + return 0; +--- a/src/gcc/fortran/trans-expr.c ++++ b/src/gcc/fortran/trans-expr.c +@@ -5051,9 +5051,13 @@ + if (gfc_ref_needs_temporary_p (expr1->ref)) + return true; + +- /* Functions returning pointers need temporaries. */ +- if (expr2->symtree->n.sym->attr.pointer +- || expr2->symtree->n.sym->attr.allocatable) ++ /* Functions returning pointers or allocatables need temporaries. */ ++ c = expr2->value.function.esym ++ ? (expr2->value.function.esym->attr.pointer ++ || expr2->value.function.esym->attr.allocatable) ++ : (expr2->symtree->n.sym->attr.pointer ++ || expr2->symtree->n.sym->attr.allocatable); ++ if (c) + return true; + + /* Character array functions need temporaries unless the +--- a/src/gcc/fortran/trans-openmp.c ++++ b/src/gcc/fortran/trans-openmp.c +@@ -480,13 +480,23 @@ + gfc_symbol init_val_sym, outer_sym, intrinsic_sym; + gfc_expr *e1, *e2, *e3, *e4; + gfc_ref *ref; +- tree decl, backend_decl, stmt; ++ tree decl, backend_decl, stmt, type, outer_decl; + locus old_loc = gfc_current_locus; + const char *iname; + gfc_try t; + + decl = OMP_CLAUSE_DECL (c); + gfc_current_locus = where; ++ type = TREE_TYPE (decl); ++ outer_decl = create_tmp_var_raw (type, NULL); ++ if (TREE_CODE (decl) == PARM_DECL ++ && TREE_CODE (type) == REFERENCE_TYPE ++ && GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (type)) ++ && GFC_TYPE_ARRAY_AKIND (TREE_TYPE (type)) == GFC_ARRAY_ALLOCATABLE) ++ { ++ decl = build_fold_indirect_ref (decl); ++ type = TREE_TYPE (type); ++ } + + /* Create a fake symbol for init value. */ + memset (&init_val_sym, 0, sizeof (init_val_sym)); +@@ -505,7 +515,9 @@ + outer_sym.attr.dummy = 0; + outer_sym.attr.result = 0; + outer_sym.attr.flavor = FL_VARIABLE; +- outer_sym.backend_decl = create_tmp_var_raw (TREE_TYPE (decl), NULL); ++ outer_sym.backend_decl = outer_decl; ++ if (decl != OMP_CLAUSE_DECL (c)) ++ outer_sym.backend_decl = build_fold_indirect_ref (outer_decl); + + /* Create fake symtrees for it. */ + symtree1 = gfc_new_symtree (&root1, sym->name); +@@ -622,12 +634,12 @@ + + /* Create the init statement list. */ + pushlevel (0); +- if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (decl)) +- && GFC_TYPE_ARRAY_AKIND (TREE_TYPE (decl)) == GFC_ARRAY_ALLOCATABLE) ++ if (GFC_DESCRIPTOR_TYPE_P (type) ++ && GFC_TYPE_ARRAY_AKIND (type) == GFC_ARRAY_ALLOCATABLE) + { + /* If decl is an allocatable array, it needs to be allocated + with the same bounds as the outer var. */ +- tree type = TREE_TYPE (decl), rank, size, esize, ptr; ++ tree rank, size, esize, ptr; + stmtblock_t block; + + gfc_start_block (&block); +@@ -663,8 +675,8 @@ + + /* Create the merge statement list. */ + pushlevel (0); +- if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (decl)) +- && GFC_TYPE_ARRAY_AKIND (TREE_TYPE (decl)) == GFC_ARRAY_ALLOCATABLE) ++ if (GFC_DESCRIPTOR_TYPE_P (type) ++ && GFC_TYPE_ARRAY_AKIND (type) == GFC_ARRAY_ALLOCATABLE) + { + /* If decl is an allocatable array, it needs to be deallocated + afterwards. */ +@@ -684,7 +696,7 @@ + OMP_CLAUSE_REDUCTION_MERGE (c) = stmt; + + /* And stick the placeholder VAR_DECL into the clause as well. */ +- OMP_CLAUSE_REDUCTION_PLACEHOLDER (c) = outer_sym.backend_decl; ++ OMP_CLAUSE_REDUCTION_PLACEHOLDER (c) = outer_decl; + + gfc_current_locus = old_loc; + +--- a/src/gcc/function.c ++++ b/src/gcc/function.c +@@ -147,9 +147,6 @@ + can always export `prologue_epilogue_contains'. */ + static void record_insns (rtx, rtx, htab_t *) ATTRIBUTE_UNUSED; + static bool contains (const_rtx, htab_t); +-#ifdef HAVE_return +-static void emit_return_into_block (basic_block); +-#endif + static void prepare_function_start (void); + static void do_clobber_return_reg (rtx, void *); + static void do_use_return_reg (rtx, void *); +@@ -4987,35 +4984,190 @@ + return 0; + } + ++#ifdef HAVE_simple_return ++/* This collects sets and clobbers of hard registers in a HARD_REG_SET, ++ which is pointed to by DATA. */ ++static void ++record_hard_reg_sets (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) ++{ ++ HARD_REG_SET *pset = (HARD_REG_SET *)data; ++ if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) ++ { ++ int nregs = hard_regno_nregs[REGNO (x)][GET_MODE (x)]; ++ while (nregs-- > 0) ++ SET_HARD_REG_BIT (*pset, REGNO (x) + nregs); ++ } ++} ++ ++/* A subroutine of requires_stack_frame_p, called via for_each_rtx. ++ If any change is made, set CHANGED ++ to true. */ ++ ++static int ++frame_required_for_rtx (rtx *loc, void *data ATTRIBUTE_UNUSED) ++{ ++ rtx x = *loc; ++ if (x == stack_pointer_rtx || x == hard_frame_pointer_rtx ++ || x == arg_pointer_rtx || x == pic_offset_table_rtx ++#ifdef RETURN_ADDR_REGNUM ++ || (REG_P (x) && REGNO (x) == RETURN_ADDR_REGNUM) ++#endif ++ ) ++ return 1; ++ return 0; ++} ++ ++static bool ++requires_stack_frame_p (rtx insn) ++{ ++ HARD_REG_SET hardregs; ++ unsigned regno; ++ ++ if (!INSN_P (insn) || DEBUG_INSN_P (insn)) ++ return false; ++ if (CALL_P (insn)) ++ return !SIBLING_CALL_P (insn); ++ if (for_each_rtx (&PATTERN (insn), frame_required_for_rtx, NULL)) ++ return true; ++ CLEAR_HARD_REG_SET (hardregs); ++ note_stores (PATTERN (insn), record_hard_reg_sets, &hardregs); ++ AND_COMPL_HARD_REG_SET (hardregs, call_used_reg_set); ++ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) ++ if (TEST_HARD_REG_BIT (hardregs, regno) ++ && df_regs_ever_live_p (regno)) ++ return true; ++ return false; ++} ++#endif ++ + #ifdef HAVE_return +-/* Insert gen_return at the end of block BB. This also means updating +- block_for_insn appropriately. */ ++ ++static rtx ++gen_return_pattern (bool simple_p) ++{ ++#ifdef HAVE_simple_return ++ return simple_p ? gen_simple_return () : gen_return (); ++#else ++ gcc_assert (!simple_p); ++ return gen_return (); ++#endif ++} ++ ++/* Insert an appropriate return pattern at the end of block BB. This ++ also means updating block_for_insn appropriately. */ + + static void +-emit_return_into_block (basic_block bb) ++emit_return_into_block (bool simple_p, basic_block bb) + { +- emit_jump_insn_after (gen_return (), BB_END (bb)); ++ rtx jump; ++ jump = emit_jump_insn_after (gen_return_pattern (simple_p), BB_END (bb)); ++ JUMP_LABEL (jump) = simple_p ? simple_return_rtx : ret_rtx; + } +-#endif /* HAVE_return */ ++#endif + + /* Generate the prologue and epilogue RTL if the machine supports it. Thread + this into place with notes indicating where the prologue ends and where +- the epilogue begins. Update the basic block information when possible. */ ++ the epilogue begins. Update the basic block information when possible. ++ ++ Notes on epilogue placement: ++ There are several kinds of edges to the exit block: ++ * a single fallthru edge from LAST_BB ++ * possibly, edges from blocks containing sibcalls ++ * possibly, fake edges from infinite loops ++ ++ The epilogue is always emitted on the fallthru edge from the last basic ++ block in the function, LAST_BB, into the exit block. ++ ++ If LAST_BB is empty except for a label, it is the target of every ++ other basic block in the function that ends in a return. If a ++ target has a return or simple_return pattern (possibly with ++ conditional variants), these basic blocks can be changed so that a ++ return insn is emitted into them, and their target is adjusted to ++ the real exit block. ++ ++ Notes on shrink wrapping: We implement a fairly conservative ++ version of shrink-wrapping rather than the textbook one. We only ++ generate a single prologue and a single epilogue. This is ++ sufficient to catch a number of interesting cases involving early ++ exits. ++ ++ First, we identify the blocks that require the prologue to occur before ++ them. These are the ones that modify a call-saved register, or reference ++ any of the stack or frame pointer registers. To simplify things, we then ++ mark everything reachable from these blocks as also requiring a prologue. ++ This takes care of loops automatically, and avoids the need to examine ++ whether MEMs reference the frame, since it is sufficient to check for ++ occurrences of the stack or frame pointer. ++ ++ We then compute the set of blocks for which the need for a prologue ++ is anticipatable (borrowing terminology from the shrink-wrapping ++ description in Muchnick's book). These are the blocks which either ++ require a prologue themselves, or those that have only successors ++ where the prologue is anticipatable. The prologue needs to be ++ inserted on all edges from BB1->BB2 where BB2 is in ANTIC and BB1 ++ is not. For the moment, we ensure that only one such edge exists. ++ ++ The epilogue is placed as described above, but we make a ++ distinction between inserting return and simple_return patterns ++ when modifying other blocks that end in a return. Blocks that end ++ in a sibcall omit the sibcall_epilogue if the block is not in ++ ANTIC. */ + + static void + thread_prologue_and_epilogue_insns (void) + { + int inserted = 0; ++ basic_block last_bb; ++ bool last_bb_active; ++#ifdef HAVE_simple_return ++ bool unconverted_simple_returns = false; ++ basic_block simple_return_block = NULL; ++#endif ++ rtx returnjump ATTRIBUTE_UNUSED; ++ rtx seq ATTRIBUTE_UNUSED, epilogue_end ATTRIBUTE_UNUSED; ++ rtx prologue_seq ATTRIBUTE_UNUSED, split_prologue_seq ATTRIBUTE_UNUSED; ++ edge entry_edge, orig_entry_edge, exit_fallthru_edge; + edge e; +-#if defined (HAVE_sibcall_epilogue) || defined (HAVE_epilogue) || defined (HAVE_return) || defined (HAVE_prologue) +- rtx seq; +-#endif +-#if defined (HAVE_epilogue) || defined(HAVE_return) +- rtx epilogue_end = NULL_RTX; +-#endif + edge_iterator ei; ++ bitmap_head bb_flags; ++ ++ df_analyze (); + + rtl_profile_for_bb (ENTRY_BLOCK_PTR); ++ ++ epilogue_end = NULL_RTX; ++ returnjump = NULL_RTX; ++ ++ /* Can't deal with multiple successors of the entry block at the ++ moment. Function should always have at least one entry ++ point. */ ++ gcc_assert (single_succ_p (ENTRY_BLOCK_PTR)); ++ entry_edge = single_succ_edge (ENTRY_BLOCK_PTR); ++ orig_entry_edge = entry_edge; ++ ++ exit_fallthru_edge = find_fallthru_edge (EXIT_BLOCK_PTR->preds); ++ if (exit_fallthru_edge != NULL) ++ { ++ rtx label; ++ ++ last_bb = exit_fallthru_edge->src; ++ /* Test whether there are active instructions in the last block. */ ++ label = BB_END (last_bb); ++ while (label && !LABEL_P (label)) ++ { ++ if (active_insn_p (label)) ++ break; ++ label = PREV_INSN (label); ++ } ++ ++ last_bb_active = BB_HEAD (last_bb) != label || !LABEL_P (label); ++ } ++ else ++ { ++ last_bb = NULL; ++ last_bb_active = false; ++ } ++ + #ifdef HAVE_prologue + if (HAVE_prologue) + { +@@ -5040,20 +5192,169 @@ + emit_insn (gen_blockage ()); + #endif + +- seq = get_insns (); ++ prologue_seq = get_insns (); + end_sequence (); + set_insn_locators (seq, prologue_locator); ++ } ++#endif + +- /* Can't deal with multiple successors of the entry block +- at the moment. Function should always have at least one +- entry point. */ +- gcc_assert (single_succ_p (ENTRY_BLOCK_PTR)); ++ bitmap_initialize (&bb_flags, &bitmap_default_obstack); + +- insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR)); +- inserted = 1; ++#ifdef HAVE_simple_return ++ /* Try to perform a kind of shrink-wrapping, making sure the ++ prologue/epilogue is emitted only around those parts of the ++ function that require it. */ ++ ++ if (flag_shrink_wrap && HAVE_simple_return && !flag_non_call_exceptions ++ && HAVE_prologue && !crtl->calls_eh_return) ++ { ++ HARD_REG_SET prologue_clobbered, live_on_edge; ++ rtx p_insn; ++ VEC(basic_block, heap) *vec; ++ basic_block bb; ++ bitmap_head bb_antic_flags; ++ bitmap_head bb_on_list; ++ ++ bitmap_initialize (&bb_antic_flags, &bitmap_default_obstack); ++ bitmap_initialize (&bb_on_list, &bitmap_default_obstack); ++ ++ vec = VEC_alloc (basic_block, heap, n_basic_blocks); ++ ++ FOR_EACH_BB (bb) ++ { ++ rtx insn; ++ FOR_BB_INSNS (bb, insn) ++ { ++ if (requires_stack_frame_p (insn)) ++ { ++ bitmap_set_bit (&bb_flags, bb->index); ++ VEC_quick_push (basic_block, vec, bb); ++ break; ++ } ++ } ++ } ++ ++ /* For every basic block that needs a prologue, mark all blocks ++ reachable from it, so as to ensure they are also seen as ++ requiring a prologue. */ ++ while (!VEC_empty (basic_block, vec)) ++ { ++ basic_block tmp_bb = VEC_pop (basic_block, vec); ++ edge e; ++ edge_iterator ei; ++ FOR_EACH_EDGE (e, ei, tmp_bb->succs) ++ { ++ if (e->dest == EXIT_BLOCK_PTR ++ || bitmap_bit_p (&bb_flags, e->dest->index)) ++ continue; ++ bitmap_set_bit (&bb_flags, e->dest->index); ++ VEC_quick_push (basic_block, vec, e->dest); ++ } ++ } ++ /* If the last basic block contains only a label, we'll be able ++ to convert jumps to it to (potentially conditional) return ++ insns later. This means we don't necessarily need a prologue ++ for paths reaching it. */ ++ if (last_bb) ++ { ++ if (!last_bb_active) ++ bitmap_clear_bit (&bb_flags, last_bb->index); ++ else if (!bitmap_bit_p (&bb_flags, last_bb->index)) ++ goto fail_shrinkwrap; ++ } ++ ++ /* Now walk backwards from every block that is marked as needing ++ a prologue to compute the bb_antic_flags bitmap. */ ++ bitmap_copy (&bb_antic_flags, &bb_flags); ++ FOR_EACH_BB (bb) ++ { ++ edge e; ++ edge_iterator ei; ++ if (!bitmap_bit_p (&bb_flags, bb->index)) ++ continue; ++ FOR_EACH_EDGE (e, ei, bb->preds) ++ if (!bitmap_bit_p (&bb_antic_flags, e->src->index)) ++ { ++ VEC_quick_push (basic_block, vec, e->src); ++ bitmap_set_bit (&bb_on_list, e->src->index); ++ } ++ } ++ while (!VEC_empty (basic_block, vec)) ++ { ++ basic_block tmp_bb = VEC_pop (basic_block, vec); ++ edge e; ++ edge_iterator ei; ++ bool all_set = true; ++ ++ bitmap_clear_bit (&bb_on_list, tmp_bb->index); ++ FOR_EACH_EDGE (e, ei, tmp_bb->succs) ++ { ++ if (!bitmap_bit_p (&bb_antic_flags, e->dest->index)) ++ { ++ all_set = false; ++ break; ++ } ++ } ++ if (all_set) ++ { ++ bitmap_set_bit (&bb_antic_flags, tmp_bb->index); ++ FOR_EACH_EDGE (e, ei, tmp_bb->preds) ++ if (!bitmap_bit_p (&bb_antic_flags, e->src->index)) ++ { ++ VEC_quick_push (basic_block, vec, e->src); ++ bitmap_set_bit (&bb_on_list, e->src->index); ++ } ++ } ++ } ++ /* Find exactly one edge that leads to a block in ANTIC from ++ a block that isn't. */ ++ if (!bitmap_bit_p (&bb_antic_flags, entry_edge->dest->index)) ++ FOR_EACH_BB (bb) ++ { ++ if (!bitmap_bit_p (&bb_antic_flags, bb->index)) ++ continue; ++ FOR_EACH_EDGE (e, ei, bb->preds) ++ if (!bitmap_bit_p (&bb_antic_flags, e->src->index)) ++ { ++ if (entry_edge != orig_entry_edge) ++ { ++ entry_edge = orig_entry_edge; ++ goto fail_shrinkwrap; ++ } ++ entry_edge = e; ++ } ++ } ++ ++ /* Test whether the prologue is known to clobber any register ++ (other than FP or SP) which are live on the edge. */ ++ CLEAR_HARD_REG_SET (prologue_clobbered); ++ for (p_insn = prologue_seq; p_insn; p_insn = NEXT_INSN (p_insn)) ++ if (NONDEBUG_INSN_P (p_insn)) ++ note_stores (PATTERN (p_insn), record_hard_reg_sets, ++ &prologue_clobbered); ++ CLEAR_HARD_REG_BIT (prologue_clobbered, STACK_POINTER_REGNUM); ++ if (frame_pointer_needed) ++ CLEAR_HARD_REG_BIT (prologue_clobbered, HARD_FRAME_POINTER_REGNUM); ++ ++ CLEAR_HARD_REG_SET (live_on_edge); ++ reg_set_to_hard_reg_set (&live_on_edge, ++ df_get_live_in (entry_edge->dest)); ++ if (hard_reg_set_intersect_p (live_on_edge, prologue_clobbered)) ++ entry_edge = orig_entry_edge; ++ ++ fail_shrinkwrap: ++ bitmap_clear (&bb_antic_flags); ++ bitmap_clear (&bb_on_list); ++ VEC_free (basic_block, heap, vec); + } + #endif + ++ if (prologue_seq != NULL_RTX) ++ { ++ insert_insn_on_edge (prologue_seq, entry_edge); ++ inserted = true; ++ } ++ + /* If the exit block has no non-fake predecessors, we don't need + an epilogue. */ + FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) +@@ -5063,100 +5364,130 @@ + goto epilogue_done; + + rtl_profile_for_bb (EXIT_BLOCK_PTR); ++ + #ifdef HAVE_return +- if (optimize && HAVE_return) ++ /* If we're allowed to generate a simple return instruction, then by ++ definition we don't need a full epilogue. If the last basic ++ block before the exit block does not contain active instructions, ++ examine its predecessors and try to emit (conditional) return ++ instructions. */ ++ if (optimize && !last_bb_active ++ && (HAVE_return || entry_edge != orig_entry_edge)) + { +- /* If we're allowed to generate a simple return instruction, +- then by definition we don't need a full epilogue. Examine +- the block that falls through to EXIT. If it does not +- contain any code, examine its predecessors and try to +- emit (conditional) return instructions. */ +- +- basic_block last; ++ edge_iterator ei2; ++ int i; ++ basic_block bb; + rtx label; ++ VEC(basic_block,heap) *src_bbs; + +- FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) +- if (e->flags & EDGE_FALLTHRU) +- break; +- if (e == NULL) ++ if (exit_fallthru_edge == NULL) + goto epilogue_done; +- last = e->src; ++ label = BB_HEAD (last_bb); + +- /* Verify that there are no active instructions in the last block. */ +- label = BB_END (last); +- while (label && !LABEL_P (label)) +- { +- if (active_insn_p (label)) +- break; +- label = PREV_INSN (label); +- } ++ src_bbs = VEC_alloc (basic_block, heap, EDGE_COUNT (last_bb->preds)); ++ FOR_EACH_EDGE (e, ei2, last_bb->preds) ++ if (e->src != ENTRY_BLOCK_PTR) ++ VEC_quick_push (basic_block, src_bbs, e->src); + +- if (BB_HEAD (last) == label && LABEL_P (label)) ++ FOR_EACH_VEC_ELT (basic_block, src_bbs, i, bb) + { +- edge_iterator ei2; ++ bool simple_p; ++ rtx jump; ++ e = find_edge (bb, last_bb); + +- for (ei2 = ei_start (last->preds); (e = ei_safe_edge (ei2)); ) +- { +- basic_block bb = e->src; +- rtx jump; ++ jump = BB_END (bb); + +- if (bb == ENTRY_BLOCK_PTR) +- { +- ei_next (&ei2); +- continue; +- } ++#ifdef HAVE_simple_return ++ simple_p = (entry_edge != orig_entry_edge ++ ? !bitmap_bit_p (&bb_flags, bb->index) : false); ++#else ++ simple_p = false; ++#endif + +- jump = BB_END (bb); +- if (!JUMP_P (jump) || JUMP_LABEL (jump) != label) +- { +- ei_next (&ei2); +- continue; +- } ++ if (!simple_p ++ && (!HAVE_return || !JUMP_P (jump) ++ || JUMP_LABEL (jump) != label)) ++ continue; + +- /* If we have an unconditional jump, we can replace that +- with a simple return instruction. */ +- if (simplejump_p (jump)) +- { +- emit_return_into_block (bb); +- delete_insn (jump); +- } ++ /* If we have an unconditional jump, we can replace that ++ with a simple return instruction. */ ++ if (!JUMP_P (jump)) ++ { ++ emit_barrier_after (BB_END (bb)); ++ emit_return_into_block (simple_p, bb); ++ } ++ else if (simplejump_p (jump)) ++ { ++ emit_return_into_block (simple_p, bb); ++ delete_insn (jump); ++ } ++ else if (condjump_p (jump) && JUMP_LABEL (jump) != label) ++ { ++ basic_block new_bb; ++ edge new_e; + +- /* If we have a conditional jump, we can try to replace +- that with a conditional return instruction. */ +- else if (condjump_p (jump)) +- { +- if (! redirect_jump (jump, 0, 0)) +- { +- ei_next (&ei2); +- continue; +- } ++ gcc_assert (simple_p); ++ new_bb = split_edge (e); ++ emit_barrier_after (BB_END (new_bb)); ++ emit_return_into_block (simple_p, new_bb); ++#ifdef HAVE_simple_return ++ simple_return_block = new_bb; ++#endif ++ new_e = single_succ_edge (new_bb); ++ redirect_edge_succ (new_e, EXIT_BLOCK_PTR); + +- /* If this block has only one successor, it both jumps +- and falls through to the fallthru block, so we can't +- delete the edge. */ +- if (single_succ_p (bb)) +- { +- ei_next (&ei2); +- continue; +- } +- } ++ continue; ++ } ++ /* If we have a conditional jump branching to the last ++ block, we can try to replace that with a conditional ++ return instruction. */ ++ else if (condjump_p (jump)) ++ { ++ rtx dest; ++ if (simple_p) ++ dest = simple_return_rtx; + else ++ dest = ret_rtx; ++ if (! redirect_jump (jump, dest, 0)) + { +- ei_next (&ei2); ++#ifdef HAVE_simple_return ++ if (simple_p) ++ unconverted_simple_returns = true; ++#endif + continue; + } + +- /* Fix up the CFG for the successful change we just made. */ +- redirect_edge_succ (e, EXIT_BLOCK_PTR); ++ /* If this block has only one successor, it both jumps ++ and falls through to the fallthru block, so we can't ++ delete the edge. */ ++ if (single_succ_p (bb)) ++ continue; + } ++ else ++ { ++#ifdef HAVE_simple_return ++ if (simple_p) ++ unconverted_simple_returns = true; ++#endif ++ continue; ++ } ++ ++ /* Fix up the CFG for the successful change we just made. */ ++ redirect_edge_succ (e, EXIT_BLOCK_PTR); ++ } ++ VEC_free (basic_block, heap, src_bbs); + ++ if (HAVE_return) ++ { + /* Emit a return insn for the exit fallthru block. Whether + this is still reachable will be determined later. */ + +- emit_barrier_after (BB_END (last)); +- emit_return_into_block (last); +- epilogue_end = BB_END (last); +- single_succ_edge (last)->flags &= ~EDGE_FALLTHRU; ++ emit_barrier_after (BB_END (last_bb)); ++ emit_return_into_block (false, last_bb); ++ epilogue_end = BB_END (last_bb); ++ if (JUMP_P (epilogue_end)) ++ JUMP_LABEL (epilogue_end) = ret_rtx; ++ single_succ_edge (last_bb)->flags &= ~EDGE_FALLTHRU; + goto epilogue_done; + } + } +@@ -5193,15 +5524,10 @@ + } + #endif + +- /* Find the edge that falls through to EXIT. Other edges may exist +- due to RETURN instructions, but those don't need epilogues. +- There really shouldn't be a mixture -- either all should have +- been converted or none, however... */ ++ /* If nothing falls through into the exit block, we don't need an ++ epilogue. */ + +- FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) +- if (e->flags & EDGE_FALLTHRU) +- break; +- if (e == NULL) ++ if (exit_fallthru_edge == NULL) + goto epilogue_done; + + #ifdef HAVE_epilogue +@@ -5217,25 +5543,36 @@ + set_insn_locators (seq, epilogue_locator); + + seq = get_insns (); ++ returnjump = get_last_insn (); + end_sequence (); + +- insert_insn_on_edge (seq, e); ++ insert_insn_on_edge (seq, exit_fallthru_edge); + inserted = 1; ++ if (JUMP_P (returnjump)) ++ { ++ rtx pat = PATTERN (returnjump); ++ if (GET_CODE (pat) == PARALLEL) ++ pat = XVECEXP (pat, 0, 0); ++ if (ANY_RETURN_P (pat)) ++ JUMP_LABEL (returnjump) = pat; ++ else ++ JUMP_LABEL (returnjump) = ret_rtx; ++ } + } + else + #endif + { + basic_block cur_bb; + +- if (! next_active_insn (BB_END (e->src))) ++ if (! next_active_insn (BB_END (exit_fallthru_edge->src))) + goto epilogue_done; + /* We have a fall-through edge to the exit block, the source is not +- at the end of the function, and there will be an assembler epilogue +- at the end of the function. +- We can't use force_nonfallthru here, because that would try to +- use return. Inserting a jump 'by hand' is extremely messy, so ++ at the end of the function, and there will be an assembler epilogue ++ at the end of the function. ++ We can't use force_nonfallthru here, because that would try to ++ use return. Inserting a jump 'by hand' is extremely messy, so + we take advantage of cfg_layout_finalize using +- fixup_fallthru_exit_predecessor. */ ++ fixup_fallthru_exit_predecessor. */ + cfg_layout_initialize (0); + FOR_EACH_BB (cur_bb) + if (cur_bb->index >= NUM_FIXED_BLOCKS +@@ -5244,6 +5581,7 @@ + cfg_layout_finalize (); + } + epilogue_done: ++ + default_rtl_profile (); + + if (inserted) +@@ -5260,33 +5598,93 @@ + } + } + ++#ifdef HAVE_simple_return ++ /* If there were branches to an empty LAST_BB which we tried to ++ convert to conditional simple_returns, but couldn't for some ++ reason, create a block to hold a simple_return insn and redirect ++ those remaining edges. */ ++ if (unconverted_simple_returns) ++ { ++ edge_iterator ei2; ++ basic_block exit_pred = EXIT_BLOCK_PTR->prev_bb; ++ ++ gcc_assert (entry_edge != orig_entry_edge); ++ ++#ifdef HAVE_epilogue ++ if (simple_return_block == NULL && returnjump != NULL_RTX ++ && JUMP_LABEL (returnjump) == simple_return_rtx) ++ { ++ edge e = split_block (exit_fallthru_edge->src, ++ PREV_INSN (returnjump)); ++ simple_return_block = e->dest; ++ } ++#endif ++ if (simple_return_block == NULL) ++ { ++ basic_block bb; ++ rtx start; ++ ++ bb = create_basic_block (NULL, NULL, exit_pred); ++ start = emit_jump_insn_after (gen_simple_return (), ++ BB_END (bb)); ++ JUMP_LABEL (start) = simple_return_rtx; ++ emit_barrier_after (start); ++ ++ simple_return_block = bb; ++ make_edge (bb, EXIT_BLOCK_PTR, 0); ++ } ++ ++ restart_scan: ++ for (ei2 = ei_start (last_bb->preds); (e = ei_safe_edge (ei2)); ) ++ { ++ basic_block bb = e->src; ++ ++ if (bb != ENTRY_BLOCK_PTR ++ && !bitmap_bit_p (&bb_flags, bb->index)) ++ { ++ redirect_edge_and_branch_force (e, simple_return_block); ++ goto restart_scan; ++ } ++ ei_next (&ei2); ++ ++ } ++ } ++#endif ++ + #ifdef HAVE_sibcall_epilogue + /* Emit sibling epilogues before any sibling call sites. */ + for (ei = ei_start (EXIT_BLOCK_PTR->preds); (e = ei_safe_edge (ei)); ) + { + basic_block bb = e->src; + rtx insn = BB_END (bb); ++ rtx ep_seq; + + if (!CALL_P (insn) +- || ! SIBLING_CALL_P (insn)) ++ || ! SIBLING_CALL_P (insn) ++ || (entry_edge != orig_entry_edge ++ && !bitmap_bit_p (&bb_flags, bb->index))) + { + ei_next (&ei); + continue; + } + +- start_sequence (); +- emit_note (NOTE_INSN_EPILOGUE_BEG); +- emit_insn (gen_sibcall_epilogue ()); +- seq = get_insns (); +- end_sequence (); ++ ep_seq = gen_sibcall_epilogue (); ++ if (ep_seq) ++ { ++ start_sequence (); ++ emit_note (NOTE_INSN_EPILOGUE_BEG); ++ emit_insn (ep_seq); ++ seq = get_insns (); ++ end_sequence (); + +- /* Retain a map of the epilogue insns. Used in life analysis to +- avoid getting rid of sibcall epilogue insns. Do this before we +- actually emit the sequence. */ +- record_insns (seq, NULL, &epilogue_insn_hash); +- set_insn_locators (seq, epilogue_locator); ++ /* Retain a map of the epilogue insns. Used in life analysis to ++ avoid getting rid of sibcall epilogue insns. Do this before we ++ actually emit the sequence. */ ++ record_insns (seq, NULL, &epilogue_insn_hash); ++ set_insn_locators (seq, epilogue_locator); + +- emit_insn_before (seq, insn); ++ emit_insn_before (seq, insn); ++ } + ei_next (&ei); + } + #endif +@@ -5311,6 +5709,8 @@ + } + #endif + ++ bitmap_clear (&bb_flags); ++ + /* Threading the prologue and epilogue changes the artificial refs + in the entry and exit blocks. */ + epilogue_completed = 1; +--- a/src/gcc/function.h ++++ b/src/gcc/function.h +@@ -25,6 +25,7 @@ + #include "tree.h" + #include "hashtab.h" + #include "vecprim.h" ++#include "hard-reg-set.h" + + /* Stack of pending (incomplete) sequences saved by `start_sequence'. + Each element describes one pending sequence. +@@ -433,6 +434,12 @@ + TREE_NOTHROW (current_function_decl) it is set even for overwritable + function where currently compiled version of it is nothrow. */ + bool nothrow; ++ ++ /* Like regs_ever_live, but 1 if a reg is set or clobbered from an ++ asm. Unlike regs_ever_live, elements of this array corresponding ++ to eliminable regs (like the frame pointer) are set if an asm ++ sets them. */ ++ HARD_REG_SET asm_clobbers; + }; + + #define return_label (crtl->x_return_label) +--- a/src/gcc/fwprop.c ++++ b/src/gcc/fwprop.c +@@ -228,7 +228,10 @@ + + process_uses (df_get_artificial_uses (bb_index), DF_REF_AT_TOP); + process_defs (df_get_artificial_defs (bb_index), DF_REF_AT_TOP); +- df_simulate_initialize_forwards (bb, local_lr); ++ ++ /* We don't call df_simulate_initialize_forwards, as it may overestimate ++ the live registers if there are unused artificial defs. We prefer ++ liveness to be underestimated. */ + + FOR_BB_INSNS (bb, insn) + if (INSN_P (insn)) +--- a/src/gcc/gcc.c ++++ b/src/gcc/gcc.c +@@ -792,6 +792,8 @@ + %{flto} %{fwhopr} %l " LINK_PIE_SPEC \ + "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\ + %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\ ++ %{Wno-poison-system-directories:--no-poison-system-directories}\ ++ %{Werror=poison-system-directories:--error-poison-system-directories}\ + %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\ + %{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)} %(mflib)\ + %{fprofile-arcs|fprofile-generate*|coverage:-lgcov}\ +--- a/src/gcc/gcse.c ++++ b/src/gcc/gcse.c +@@ -296,6 +296,12 @@ + The value is the newly created pseudo-reg to record a copy of the + expression in all the places that reach the redundant copy. */ + rtx reaching_reg; ++ /* Maximum distance in instructions this expression can travel. ++ We avoid moving simple expressions for more than a few instructions ++ to keep register pressure under control. ++ A value of "0" removes restrictions on how far the expression can ++ travel. */ ++ int max_distance; + }; + + /* Occurrence of an expression. +@@ -317,6 +323,10 @@ + char copied_p; + }; + ++typedef struct occr *occr_t; ++DEF_VEC_P (occr_t); ++DEF_VEC_ALLOC_P (occr_t, heap); ++ + /* Expression and copy propagation hash tables. + Each hash table is an array of buckets. + ??? It is known that if it were an array of entries, structure elements +@@ -419,6 +429,9 @@ + /* Number of global copies propagated. */ + static int global_copy_prop_count; + ++/* Doing code hoisting. */ ++static bool doing_code_hoisting_p = false; ++ + /* For available exprs */ + static sbitmap *ae_kill; + +@@ -432,12 +445,12 @@ + static void hash_scan_set (rtx, rtx, struct hash_table_d *); + static void hash_scan_clobber (rtx, rtx, struct hash_table_d *); + static void hash_scan_call (rtx, rtx, struct hash_table_d *); +-static int want_to_gcse_p (rtx); ++static int want_to_gcse_p (rtx, int *); + static bool gcse_constant_p (const_rtx); + static int oprs_unchanged_p (const_rtx, const_rtx, int); + static int oprs_anticipatable_p (const_rtx, const_rtx); + static int oprs_available_p (const_rtx, const_rtx); +-static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int, ++static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int, int, + struct hash_table_d *); + static void insert_set_in_table (rtx, rtx, struct hash_table_d *); + static unsigned int hash_expr (const_rtx, enum machine_mode, int *, int); +@@ -462,7 +475,6 @@ + static void alloc_cprop_mem (int, int); + static void free_cprop_mem (void); + static void compute_transp (const_rtx, int, sbitmap *, int); +-static void compute_transpout (void); + static void compute_local_properties (sbitmap *, sbitmap *, sbitmap *, + struct hash_table_d *); + static void compute_cprop_data (void); +@@ -486,7 +498,7 @@ + static void compute_pre_data (void); + static int pre_expr_reaches_here_p (basic_block, struct expr *, + basic_block); +-static void insert_insn_end_basic_block (struct expr *, basic_block, int); ++static void insert_insn_end_basic_block (struct expr *, basic_block); + static void pre_insert_copy_insn (struct expr *, rtx); + static void pre_insert_copies (void); + static int pre_delete (void); +@@ -497,7 +509,8 @@ + static void free_code_hoist_mem (void); + static void compute_code_hoist_vbeinout (void); + static void compute_code_hoist_data (void); +-static int hoist_expr_reaches_here_p (basic_block, int, basic_block, char *); ++static int hoist_expr_reaches_here_p (basic_block, int, basic_block, char *, ++ int, int *); + static int hoist_code (void); + static int one_code_hoisting_pass (void); + static rtx process_insert_insn (struct expr *); +@@ -755,7 +768,7 @@ + GCSE. */ + + static int +-want_to_gcse_p (rtx x) ++want_to_gcse_p (rtx x, int *max_distance_ptr) + { + #ifdef STACK_REGS + /* On register stack architectures, don't GCSE constants from the +@@ -765,18 +778,67 @@ + x = avoid_constant_pool_reference (x); + #endif + ++ /* GCSE'ing constants: ++ ++ We do not specifically distinguish between constant and non-constant ++ expressions in PRE and Hoist. We use rtx_cost below to limit ++ the maximum distance simple expressions can travel. ++ ++ Nevertheless, constants are much easier to GCSE, and, hence, ++ it is easy to overdo the optimizations. Usually, excessive PRE and ++ Hoisting of constant leads to increased register pressure. ++ ++ RA can deal with this by rematerialing some of the constants. ++ Therefore, it is important that the back-end generates sets of constants ++ in a way that allows reload rematerialize them under high register ++ pressure, i.e., a pseudo register with REG_EQUAL to constant ++ is set only once. Failing to do so will result in IRA/reload ++ spilling such constants under high register pressure instead of ++ rematerializing them. */ ++ + switch (GET_CODE (x)) + { + case REG: + case SUBREG: ++ case CALL: ++ return 0; ++ + case CONST_INT: + case CONST_DOUBLE: + case CONST_FIXED: + case CONST_VECTOR: +- case CALL: +- return 0; ++ if (!doing_code_hoisting_p) ++ /* Do not PRE constants. */ ++ return 0; ++ ++ /* FALLTHRU */ + + default: ++ if (doing_code_hoisting_p) ++ /* PRE doesn't implement max_distance restriction. */ ++ { ++ int cost; ++ int max_distance; ++ ++ gcc_assert (!optimize_function_for_speed_p (cfun) ++ && optimize_function_for_size_p (cfun)); ++ cost = rtx_cost (x, SET, 0); ++ ++ if (cost < COSTS_N_INSNS (GCSE_UNRESTRICTED_COST)) ++ { ++ max_distance = (GCSE_COST_DISTANCE_RATIO * cost) / 10; ++ if (max_distance == 0) ++ return 0; ++ ++ gcc_assert (max_distance > 0); ++ } ++ else ++ max_distance = 0; ++ ++ if (max_distance_ptr) ++ *max_distance_ptr = max_distance; ++ } ++ + return can_assign_to_reg_without_clobbers_p (x); + } + } +@@ -1090,11 +1152,14 @@ + It is only used if X is a CONST_INT. + + ANTIC_P is nonzero if X is an anticipatable expression. +- AVAIL_P is nonzero if X is an available expression. */ ++ AVAIL_P is nonzero if X is an available expression. ++ ++ MAX_DISTANCE is the maximum distance in instructions this expression can ++ be moved. */ + + static void + insert_expr_in_table (rtx x, enum machine_mode mode, rtx insn, int antic_p, +- int avail_p, struct hash_table_d *table) ++ int avail_p, int max_distance, struct hash_table_d *table) + { + int found, do_not_record_p; + unsigned int hash; +@@ -1137,7 +1202,11 @@ + cur_expr->next_same_hash = NULL; + cur_expr->antic_occr = NULL; + cur_expr->avail_occr = NULL; ++ gcc_assert (max_distance >= 0); ++ cur_expr->max_distance = max_distance; + } ++ else ++ gcc_assert (cur_expr->max_distance == max_distance); + + /* Now record the occurrence(s). */ + if (antic_p) +@@ -1238,6 +1307,8 @@ + cur_expr->next_same_hash = NULL; + cur_expr->antic_occr = NULL; + cur_expr->avail_occr = NULL; ++ /* Not used for set_p tables. */ ++ cur_expr->max_distance = 0; + } + + /* Now record the occurrence. */ +@@ -1307,6 +1378,7 @@ + { + unsigned int regno = REGNO (dest); + rtx tmp; ++ int max_distance = 0; + + /* See if a REG_EQUAL note shows this equivalent to a simpler expression. + +@@ -1329,7 +1401,7 @@ + && !REG_P (src) + && (table->set_p + ? gcse_constant_p (XEXP (note, 0)) +- : want_to_gcse_p (XEXP (note, 0)))) ++ : want_to_gcse_p (XEXP (note, 0), NULL))) + src = XEXP (note, 0), pat = gen_rtx_SET (VOIDmode, dest, src); + + /* Only record sets of pseudo-regs in the hash table. */ +@@ -1344,7 +1416,7 @@ + can't do the same thing at the rtl level. */ + && !can_throw_internal (insn) + /* Is SET_SRC something we want to gcse? */ +- && want_to_gcse_p (src) ++ && want_to_gcse_p (src, &max_distance) + /* Don't CSE a nop. */ + && ! set_noop_p (pat) + /* Don't GCSE if it has attached REG_EQUIV note. +@@ -1368,7 +1440,8 @@ + int avail_p = (oprs_available_p (src, insn) + && ! JUMP_P (insn)); + +- insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, table); ++ insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, ++ max_distance, table); + } + + /* Record sets for constant/copy propagation. */ +@@ -1394,6 +1467,7 @@ + else if (flag_gcse_las && REG_P (src) && MEM_P (dest)) + { + unsigned int regno = REGNO (src); ++ int max_distance = 0; + + /* Do not do this for constant/copy propagation. */ + if (! table->set_p +@@ -1405,7 +1479,7 @@ + do that easily for EH edges so disable GCSE on these for now. */ + && !can_throw_internal (insn) + /* Is SET_DEST something we want to gcse? */ +- && want_to_gcse_p (dest) ++ && want_to_gcse_p (dest, &max_distance) + /* Don't CSE a nop. */ + && ! set_noop_p (pat) + /* Don't GCSE if it has attached REG_EQUIV note. +@@ -1427,7 +1501,7 @@ + + /* Record the memory expression (DEST) in the hash table. */ + insert_expr_in_table (dest, GET_MODE (dest), insn, +- antic_p, avail_p, table); ++ antic_p, avail_p, max_distance, table); + } + } + } +@@ -1513,8 +1587,8 @@ + if (flat_table[i] != 0) + { + expr = flat_table[i]; +- fprintf (file, "Index %d (hash value %d)\n ", +- expr->bitmap_index, hash_val[i]); ++ fprintf (file, "Index %d (hash value %d; max distance %d)\n ", ++ expr->bitmap_index, hash_val[i], expr->max_distance); + print_rtl (file, expr->expr); + fprintf (file, "\n"); + } +@@ -3168,11 +3242,6 @@ + /* Nonzero for expressions that are transparent in the block. */ + static sbitmap *transp; + +-/* Nonzero for expressions that are transparent at the end of the block. +- This is only zero for expressions killed by abnormal critical edge +- created by a calls. */ +-static sbitmap *transpout; +- + /* Nonzero for expressions that are computed (available) in the block. */ + static sbitmap *comp; + +@@ -3236,33 +3305,59 @@ + pre_optimal = pre_redundant = pre_insert_map = pre_delete_map = NULL; + } + +-/* Top level routine to do the dataflow analysis needed by PRE. */ ++/* Remove certain expressions from anticipatable and transparent ++ sets of basic blocks that have incoming abnormal edge. ++ For PRE remove potentially trapping expressions to avoid placing ++ them on abnormal edges. For hoisting remove memory references that ++ can be clobbered by calls. */ + + static void +-compute_pre_data (void) ++prune_expressions (bool pre_p) + { +- sbitmap trapping_expr; +- basic_block bb; ++ sbitmap prune_exprs; + unsigned int ui; ++ basic_block bb; + +- compute_local_properties (transp, comp, antloc, &expr_hash_table); +- sbitmap_vector_zero (ae_kill, last_basic_block); +- +- /* Collect expressions which might trap. */ +- trapping_expr = sbitmap_alloc (expr_hash_table.n_elems); +- sbitmap_zero (trapping_expr); ++ prune_exprs = sbitmap_alloc (expr_hash_table.n_elems); ++ sbitmap_zero (prune_exprs); + for (ui = 0; ui < expr_hash_table.size; ui++) + { + struct expr *e; + for (e = expr_hash_table.table[ui]; e != NULL; e = e->next_same_hash) +- if (may_trap_p (e->expr)) +- SET_BIT (trapping_expr, e->bitmap_index); +- } ++ { ++ /* Note potentially trapping expressions. */ ++ if (may_trap_p (e->expr)) ++ { ++ SET_BIT (prune_exprs, e->bitmap_index); ++ continue; ++ } + +- /* Compute ae_kill for each basic block using: ++ if (!pre_p && MEM_P (e->expr)) ++ /* Note memory references that can be clobbered by a call. ++ We do not split abnormal edges in hoisting, so would ++ a memory reference get hoisted along an abnormal edge, ++ it would be placed /before/ the call. Therefore, only ++ constant memory references can be hoisted along abnormal ++ edges. */ ++ { ++ if (GET_CODE (XEXP (e->expr, 0)) == SYMBOL_REF ++ && CONSTANT_POOL_ADDRESS_P (XEXP (e->expr, 0))) ++ continue; + +- ~(TRANSP | COMP) +- */ ++ if (MEM_READONLY_P (e->expr) ++ && !MEM_VOLATILE_P (e->expr) ++ && MEM_NOTRAP_P (e->expr)) ++ /* Constant memory reference, e.g., a PIC address. */ ++ continue; ++ ++ /* ??? Optimally, we would use interprocedural alias ++ analysis to determine if this mem is actually killed ++ by this call. */ ++ ++ SET_BIT (prune_exprs, e->bitmap_index); ++ } ++ } ++ } + + FOR_EACH_BB (bb) + { +@@ -3270,17 +3365,53 @@ + edge_iterator ei; + + /* If the current block is the destination of an abnormal edge, we +- kill all trapping expressions because we won't be able to properly +- place the instruction on the edge. So make them neither +- anticipatable nor transparent. This is fairly conservative. */ ++ kill all trapping (for PRE) and memory (for hoist) expressions ++ because we won't be able to properly place the instruction on ++ the edge. So make them neither anticipatable nor transparent. ++ This is fairly conservative. ++ ++ ??? For hoisting it may be necessary to check for set-and-jump ++ instructions here, not just for abnormal edges. The general problem ++ is that when an expression cannot not be placed right at the end of ++ a basic block we should account for any side-effects of a subsequent ++ jump instructions that could clobber the expression. It would ++ be best to implement this check along the lines of ++ hoist_expr_reaches_here_p where the target block is already known ++ and, hence, there's no need to conservatively prune expressions on ++ "intermediate" set-and-jump instructions. */ + FOR_EACH_EDGE (e, ei, bb->preds) +- if (e->flags & EDGE_ABNORMAL) ++ if ((e->flags & EDGE_ABNORMAL) ++ && (pre_p || CALL_P (BB_END (e->src)))) + { +- sbitmap_difference (antloc[bb->index], antloc[bb->index], trapping_expr); +- sbitmap_difference (transp[bb->index], transp[bb->index], trapping_expr); ++ sbitmap_difference (antloc[bb->index], ++ antloc[bb->index], prune_exprs); ++ sbitmap_difference (transp[bb->index], ++ transp[bb->index], prune_exprs); + break; + } ++ } ++ ++ sbitmap_free (prune_exprs); ++} ++ ++/* Top level routine to do the dataflow analysis needed by PRE. */ + ++static void ++compute_pre_data (void) ++{ ++ basic_block bb; ++ ++ compute_local_properties (transp, comp, antloc, &expr_hash_table); ++ prune_expressions (true); ++ sbitmap_vector_zero (ae_kill, last_basic_block); ++ ++ /* Compute ae_kill for each basic block using: ++ ++ ~(TRANSP | COMP) ++ */ ++ ++ FOR_EACH_BB (bb) ++ { + sbitmap_a_or_b (ae_kill[bb->index], transp[bb->index], comp[bb->index]); + sbitmap_not (ae_kill[bb->index], ae_kill[bb->index]); + } +@@ -3291,7 +3422,6 @@ + antloc = NULL; + sbitmap_vector_free (ae_kill); + ae_kill = NULL; +- sbitmap_free (trapping_expr); + } + + /* PRE utilities */ +@@ -3406,14 +3536,10 @@ + + /* Add EXPR to the end of basic block BB. + +- This is used by both the PRE and code hoisting. +- +- For PRE, we want to verify that the expr is either transparent +- or locally anticipatable in the target block. This check makes +- no sense for code hoisting. */ ++ This is used by both the PRE and code hoisting. */ + + static void +-insert_insn_end_basic_block (struct expr *expr, basic_block bb, int pre) ++insert_insn_end_basic_block (struct expr *expr, basic_block bb) + { + rtx insn = BB_END (bb); + rtx new_insn; +@@ -3440,12 +3566,6 @@ + #ifdef HAVE_cc0 + rtx note; + #endif +- /* It should always be the case that we can put these instructions +- anywhere in the basic block with performing PRE optimizations. +- Check this. */ +- gcc_assert (!NONJUMP_INSN_P (insn) || !pre +- || TEST_BIT (antloc[bb->index], expr->bitmap_index) +- || TEST_BIT (transp[bb->index], expr->bitmap_index)); + + /* If this is a jump table, then we can't insert stuff here. Since + we know the previous real insn must be the tablejump, we insert +@@ -3482,15 +3602,7 @@ + /* Keeping in mind SMALL_REGISTER_CLASSES and parameters in registers, + we search backward and place the instructions before the first + parameter is loaded. Do this for everyone for consistency and a +- presumption that we'll get better code elsewhere as well. +- +- It should always be the case that we can put these instructions +- anywhere in the basic block with performing PRE optimizations. +- Check this. */ +- +- gcc_assert (!pre +- || TEST_BIT (antloc[bb->index], expr->bitmap_index) +- || TEST_BIT (transp[bb->index], expr->bitmap_index)); ++ presumption that we'll get better code elsewhere as well. */ + + /* Since different machines initialize their parameter registers + in different orders, assume nothing. Collect the set of all +@@ -3587,7 +3699,7 @@ + now. */ + + if (eg->flags & EDGE_ABNORMAL) +- insert_insn_end_basic_block (index_map[j], bb, 0); ++ insert_insn_end_basic_block (index_map[j], bb); + else + { + insn = process_insert_insn (index_map[j]); +@@ -4046,61 +4158,12 @@ + } + } + +-/* Compute transparent outgoing information for each block. +- +- An expression is transparent to an edge unless it is killed by +- the edge itself. This can only happen with abnormal control flow, +- when the edge is traversed through a call. This happens with +- non-local labels and exceptions. +- +- This would not be necessary if we split the edge. While this is +- normally impossible for abnormal critical edges, with some effort +- it should be possible with exception handling, since we still have +- control over which handler should be invoked. But due to increased +- EH table sizes, this may not be worthwhile. */ +- +-static void +-compute_transpout (void) +-{ +- basic_block bb; +- unsigned int i; +- struct expr *expr; +- +- sbitmap_vector_ones (transpout, last_basic_block); +- +- FOR_EACH_BB (bb) +- { +- /* Note that flow inserted a nop at the end of basic blocks that +- end in call instructions for reasons other than abnormal +- control flow. */ +- if (! CALL_P (BB_END (bb))) +- continue; +- +- for (i = 0; i < expr_hash_table.size; i++) +- for (expr = expr_hash_table.table[i]; expr ; expr = expr->next_same_hash) +- if (MEM_P (expr->expr)) +- { +- if (GET_CODE (XEXP (expr->expr, 0)) == SYMBOL_REF +- && CONSTANT_POOL_ADDRESS_P (XEXP (expr->expr, 0))) +- continue; +- +- /* ??? Optimally, we would use interprocedural alias +- analysis to determine if this mem is actually killed +- by this call. */ +- RESET_BIT (transpout[bb->index], expr->bitmap_index); +- } +- } +-} +- + /* Code Hoisting variables and subroutines. */ + + /* Very busy expressions. */ + static sbitmap *hoist_vbein; + static sbitmap *hoist_vbeout; + +-/* Hoistable expressions. */ +-static sbitmap *hoist_exprs; +- + /* ??? We could compute post dominators and run this algorithm in + reverse to perform tail merging, doing so would probably be + more effective than the tail merging code in jump.c. +@@ -4119,8 +4182,6 @@ + + hoist_vbein = sbitmap_vector_alloc (n_blocks, n_exprs); + hoist_vbeout = sbitmap_vector_alloc (n_blocks, n_exprs); +- hoist_exprs = sbitmap_vector_alloc (n_blocks, n_exprs); +- transpout = sbitmap_vector_alloc (n_blocks, n_exprs); + } + + /* Free vars used for code hoisting analysis. */ +@@ -4134,8 +4195,6 @@ + + sbitmap_vector_free (hoist_vbein); + sbitmap_vector_free (hoist_vbeout); +- sbitmap_vector_free (hoist_exprs); +- sbitmap_vector_free (transpout); + + free_dominance_info (CDI_DOMINATORS); + } +@@ -4166,8 +4225,15 @@ + FOR_EACH_BB_REVERSE (bb) + { + if (bb->next_bb != EXIT_BLOCK_PTR) +- sbitmap_intersection_of_succs (hoist_vbeout[bb->index], +- hoist_vbein, bb->index); ++ { ++ sbitmap_intersection_of_succs (hoist_vbeout[bb->index], ++ hoist_vbein, bb->index); ++ ++ /* Include expressions in VBEout that are calculated ++ in BB and available at its end. */ ++ sbitmap_a_or_b (hoist_vbeout[bb->index], ++ hoist_vbeout[bb->index], comp[bb->index]); ++ } + + changed |= sbitmap_a_or_b_and_c_cg (hoist_vbein[bb->index], + antloc[bb->index], +@@ -4179,7 +4245,17 @@ + } + + if (dump_file) +- fprintf (dump_file, "hoisting vbeinout computation: %d passes\n", passes); ++ { ++ fprintf (dump_file, "hoisting vbeinout computation: %d passes\n", passes); ++ ++ FOR_EACH_BB (bb) ++ { ++ fprintf (dump_file, "vbein (%d): ", bb->index); ++ dump_sbitmap_file (dump_file, hoist_vbein[bb->index]); ++ fprintf (dump_file, "vbeout(%d): ", bb->index); ++ dump_sbitmap_file (dump_file, hoist_vbeout[bb->index]); ++ } ++ } + } + + /* Top level routine to do the dataflow analysis needed by code hoisting. */ +@@ -4188,7 +4264,7 @@ + compute_code_hoist_data (void) + { + compute_local_properties (transp, comp, antloc, &expr_hash_table); +- compute_transpout (); ++ prune_expressions (false); + compute_code_hoist_vbeinout (); + calculate_dominance_info (CDI_DOMINATORS); + if (dump_file) +@@ -4197,6 +4273,8 @@ + + /* Determine if the expression identified by EXPR_INDEX would + reach BB unimpared if it was placed at the end of EXPR_BB. ++ Stop the search if the expression would need to be moved more ++ than DISTANCE instructions. + + It's unclear exactly what Muchnick meant by "unimpared". It seems + to me that the expression must either be computed or transparent in +@@ -4209,12 +4287,24 @@ + paths. */ + + static int +-hoist_expr_reaches_here_p (basic_block expr_bb, int expr_index, basic_block bb, char *visited) ++hoist_expr_reaches_here_p (basic_block expr_bb, int expr_index, basic_block bb, ++ char *visited, int distance, int *bb_size) + { + edge pred; + edge_iterator ei; + int visited_allocated_locally = 0; + ++ /* Terminate the search if distance, for which EXPR is allowed to move, ++ is exhausted. */ ++ if (distance > 0) ++ { ++ distance -= bb_size[bb->index]; ++ ++ if (distance <= 0) ++ return 0; ++ } ++ else ++ gcc_assert (distance == 0); + + if (visited == NULL) + { +@@ -4233,9 +4323,6 @@ + else if (visited[pred_bb->index]) + continue; + +- /* Does this predecessor generate this expression? */ +- else if (TEST_BIT (comp[pred_bb->index], expr_index)) +- break; + else if (! TEST_BIT (transp[pred_bb->index], expr_index)) + break; + +@@ -4243,8 +4330,8 @@ + else + { + visited[pred_bb->index] = 1; +- if (! hoist_expr_reaches_here_p (expr_bb, expr_index, +- pred_bb, visited)) ++ if (! hoist_expr_reaches_here_p (expr_bb, expr_index, pred_bb, ++ visited, distance, bb_size)) + break; + } + } +@@ -4254,20 +4341,33 @@ + return (pred == NULL); + } + ++/* Find occurence in BB. */ ++static struct occr * ++find_occr_in_bb (struct occr *occr, basic_block bb) ++{ ++ /* Find the right occurrence of this expression. */ ++ while (occr && BLOCK_FOR_INSN (occr->insn) != bb) ++ occr = occr->next; ++ ++ return occr; ++} ++ + /* Actually perform code hoisting. */ + + static int + hoist_code (void) + { + basic_block bb, dominated; ++ VEC (basic_block, heap) *dom_tree_walk; ++ unsigned int dom_tree_walk_index; + VEC (basic_block, heap) *domby; + unsigned int i,j; + struct expr **index_map; + struct expr *expr; ++ int *to_bb_head; ++ int *bb_size; + int changed = 0; + +- sbitmap_vector_zero (hoist_exprs, last_basic_block); +- + /* Compute a mapping from expression number (`bitmap_index') to + hash table entry. */ + +@@ -4276,28 +4376,98 @@ + for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash) + index_map[expr->bitmap_index] = expr; + ++ /* Calculate sizes of basic blocks and note how far ++ each instruction is from the start of its block. We then use this ++ data to restrict distance an expression can travel. */ ++ ++ to_bb_head = XCNEWVEC (int, get_max_uid ()); ++ bb_size = XCNEWVEC (int, last_basic_block); ++ ++ FOR_EACH_BB (bb) ++ { ++ rtx insn; ++ int to_head; ++ ++ to_head = 0; ++ FOR_BB_INSNS (bb, insn) ++ { ++ /* Don't count debug instructions to avoid them affecting ++ decision choices. */ ++ if (NONDEBUG_INSN_P (insn)) ++ to_bb_head[INSN_UID (insn)] = to_head++; ++ } ++ ++ bb_size[bb->index] = to_head; ++ } ++ ++ gcc_assert (EDGE_COUNT (ENTRY_BLOCK_PTR->succs) == 1 ++ && (EDGE_SUCC (ENTRY_BLOCK_PTR, 0)->dest ++ == ENTRY_BLOCK_PTR->next_bb)); ++ ++ dom_tree_walk = get_all_dominated_blocks (CDI_DOMINATORS, ++ ENTRY_BLOCK_PTR->next_bb); ++ + /* Walk over each basic block looking for potentially hoistable + expressions, nothing gets hoisted from the entry block. */ +- FOR_EACH_BB (bb) ++ for (dom_tree_walk_index = 0; ++ VEC_iterate (basic_block, dom_tree_walk, dom_tree_walk_index, bb); ++ dom_tree_walk_index++) + { +- int found = 0; +- int insn_inserted_p; ++ domby = get_dominated_to_depth (CDI_DOMINATORS, bb, MAX_HOIST_DEPTH); ++ ++ if (VEC_length (basic_block, domby) == 0) ++ continue; + +- domby = get_dominated_by (CDI_DOMINATORS, bb); + /* Examine each expression that is very busy at the exit of this + block. These are the potentially hoistable expressions. */ + for (i = 0; i < hoist_vbeout[bb->index]->n_bits; i++) + { +- int hoistable = 0; +- +- if (TEST_BIT (hoist_vbeout[bb->index], i) +- && TEST_BIT (transpout[bb->index], i)) ++ if (TEST_BIT (hoist_vbeout[bb->index], i)) + { ++ /* Current expression. */ ++ struct expr *expr = index_map[i]; ++ /* Number of occurences of EXPR that can be hoisted to BB. */ ++ int hoistable = 0; ++ /* Basic blocks that have occurences reachable from BB. */ ++ bitmap_head _from_bbs, *from_bbs = &_from_bbs; ++ /* Occurences reachable from BB. */ ++ VEC (occr_t, heap) *occrs_to_hoist = NULL; ++ /* We want to insert the expression into BB only once, so ++ note when we've inserted it. */ ++ int insn_inserted_p; ++ occr_t occr; ++ ++ bitmap_initialize (from_bbs, 0); ++ ++ /* If an expression is computed in BB and is available at end of ++ BB, hoist all occurences dominated by BB to BB. */ ++ if (TEST_BIT (comp[bb->index], i)) ++ { ++ occr = find_occr_in_bb (expr->antic_occr, bb); ++ ++ if (occr) ++ { ++ /* An occurence might've been already deleted ++ while processing a dominator of BB. */ ++ if (occr->deleted_p) ++ gcc_assert (MAX_HOIST_DEPTH > 1); ++ else ++ { ++ gcc_assert (NONDEBUG_INSN_P (occr->insn)); ++ hoistable++; ++ } ++ } ++ else ++ hoistable++; ++ } ++ + /* We've found a potentially hoistable expression, now + we look at every block BB dominates to see if it + computes the expression. */ + for (j = 0; VEC_iterate (basic_block, domby, j, dominated); j++) + { ++ int max_distance; ++ + /* Ignore self dominance. */ + if (bb == dominated) + continue; +@@ -4307,17 +4477,43 @@ + if (!TEST_BIT (antloc[dominated->index], i)) + continue; + ++ occr = find_occr_in_bb (expr->antic_occr, dominated); ++ gcc_assert (occr); ++ ++ /* An occurence might've been already deleted ++ while processing a dominator of BB. */ ++ if (occr->deleted_p) ++ { ++ gcc_assert (MAX_HOIST_DEPTH > 1); ++ continue; ++ } ++ gcc_assert (NONDEBUG_INSN_P (occr->insn)); ++ ++ max_distance = expr->max_distance; ++ if (max_distance > 0) ++ /* Adjust MAX_DISTANCE to account for the fact that ++ OCCR won't have to travel all of DOMINATED, but ++ only part of it. */ ++ max_distance += (bb_size[dominated->index] ++ - to_bb_head[INSN_UID (occr->insn)]); ++ + /* Note if the expression would reach the dominated block + unimpared if it was placed at the end of BB. + + Keep track of how many times this expression is hoistable + from a dominated block into BB. */ +- if (hoist_expr_reaches_here_p (bb, i, dominated, NULL)) +- hoistable++; ++ if (hoist_expr_reaches_here_p (bb, i, dominated, NULL, ++ max_distance, bb_size)) ++ { ++ hoistable++; ++ VEC_safe_push (occr_t, heap, ++ occrs_to_hoist, occr); ++ bitmap_set_bit (from_bbs, dominated->index); ++ } + } + + /* If we found more than one hoistable occurrence of this +- expression, then note it in the bitmap of expressions to ++ expression, then note it in the vector of expressions to + hoist. It makes no sense to hoist things which are computed + in only one BB, and doing so tends to pessimize register + allocation. One could increase this value to try harder +@@ -4326,91 +4522,80 @@ + the vast majority of hoistable expressions are only movable + from two successors, so raising this threshold is likely + to nullify any benefit we get from code hoisting. */ +- if (hoistable > 1) ++ if (hoistable > 1 && dbg_cnt (hoist_insn)) + { +- SET_BIT (hoist_exprs[bb->index], i); +- found = 1; ++ /* If (hoistable != VEC_length), then there is ++ an occurence of EXPR in BB itself. Don't waste ++ time looking for LCA in this case. */ ++ if ((unsigned) hoistable ++ == VEC_length (occr_t, occrs_to_hoist)) ++ { ++ basic_block lca; ++ ++ lca = nearest_common_dominator_for_set (CDI_DOMINATORS, ++ from_bbs); ++ if (lca != bb) ++ /* Punt, it's better to hoist these occurences to ++ LCA. */ ++ VEC_free (occr_t, heap, occrs_to_hoist); ++ } + } +- } +- } +- /* If we found nothing to hoist, then quit now. */ +- if (! found) +- { +- VEC_free (basic_block, heap, domby); +- continue; +- } ++ else ++ /* Punt, no point hoisting a single occurence. */ ++ VEC_free (occr_t, heap, occrs_to_hoist); + +- /* Loop over all the hoistable expressions. */ +- for (i = 0; i < hoist_exprs[bb->index]->n_bits; i++) +- { +- /* We want to insert the expression into BB only once, so +- note when we've inserted it. */ +- insn_inserted_p = 0; ++ insn_inserted_p = 0; + +- /* These tests should be the same as the tests above. */ +- if (TEST_BIT (hoist_exprs[bb->index], i)) +- { +- /* We've found a potentially hoistable expression, now +- we look at every block BB dominates to see if it +- computes the expression. */ +- for (j = 0; VEC_iterate (basic_block, domby, j, dominated); j++) ++ /* Walk through occurences of I'th expressions we want ++ to hoist to BB and make the transformations. */ ++ for (j = 0; ++ VEC_iterate (occr_t, occrs_to_hoist, j, occr); ++ j++) + { +- /* Ignore self dominance. */ +- if (bb == dominated) +- continue; ++ rtx insn; ++ rtx set; + +- /* We've found a dominated block, now see if it computes +- the busy expression and whether or not moving that +- expression to the "beginning" of that block is safe. */ +- if (!TEST_BIT (antloc[dominated->index], i)) +- continue; ++ gcc_assert (!occr->deleted_p); + +- /* The expression is computed in the dominated block and +- it would be safe to compute it at the start of the +- dominated block. Now we have to determine if the +- expression would reach the dominated block if it was +- placed at the end of BB. */ +- if (hoist_expr_reaches_here_p (bb, i, dominated, NULL)) +- { +- struct expr *expr = index_map[i]; +- struct occr *occr = expr->antic_occr; +- rtx insn; +- rtx set; +- +- /* Find the right occurrence of this expression. */ +- while (BLOCK_FOR_INSN (occr->insn) != dominated && occr) +- occr = occr->next; +- +- gcc_assert (occr); +- insn = occr->insn; +- set = single_set (insn); +- gcc_assert (set); +- +- /* Create a pseudo-reg to store the result of reaching +- expressions into. Get the mode for the new pseudo +- from the mode of the original destination pseudo. */ +- if (expr->reaching_reg == NULL) +- expr->reaching_reg +- = gen_reg_rtx_and_attrs (SET_DEST (set)); +- +- gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), insn); +- delete_insn (insn); +- occr->deleted_p = 1; +- changed = 1; +- gcse_subst_count++; ++ insn = occr->insn; ++ set = single_set (insn); ++ gcc_assert (set); ++ ++ /* Create a pseudo-reg to store the result of reaching ++ expressions into. Get the mode for the new pseudo ++ from the mode of the original destination pseudo. ++ ++ It is important to use new pseudos whenever we ++ emit a set. This will allow reload to use ++ rematerialization for such registers. */ ++ if (!insn_inserted_p) ++ expr->reaching_reg ++ = gen_reg_rtx_and_attrs (SET_DEST (set)); ++ ++ gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), ++ insn); ++ delete_insn (insn); ++ occr->deleted_p = 1; ++ changed = 1; ++ gcse_subst_count++; + +- if (!insn_inserted_p) +- { +- insert_insn_end_basic_block (index_map[i], bb, 0); +- insn_inserted_p = 1; +- } ++ if (!insn_inserted_p) ++ { ++ insert_insn_end_basic_block (expr, bb); ++ insn_inserted_p = 1; + } + } ++ ++ VEC_free (occr_t, heap, occrs_to_hoist); ++ bitmap_clear (from_bbs); + } + } + VEC_free (basic_block, heap, domby); + } + ++ VEC_free (basic_block, heap, dom_tree_walk); ++ free (bb_size); ++ free (to_bb_head); + free (index_map); + + return changed; +@@ -4433,6 +4618,8 @@ + || is_too_expensive (_("GCSE disabled"))) + return 0; + ++ doing_code_hoisting_p = true; ++ + /* We need alias. */ + init_alias_analysis (); + +@@ -4468,6 +4655,8 @@ + gcse_subst_count, gcse_create_count); + } + ++ doing_code_hoisting_p = false; ++ + return changed; + } + +--- a/src/gcc/genautomata.c ++++ b/src/gcc/genautomata.c +@@ -7865,12 +7865,15 @@ + { + fprintf (output_file, ") / %d];\n", + automaton->min_issue_delay_table_compression_factor); +- fprintf (output_file, " %s = (%s >> (8 - (", ++ fprintf (output_file, " %s = (%s >> (8 - ((", + TEMPORARY_VARIABLE_NAME, TEMPORARY_VARIABLE_NAME); + output_translate_vect_name (output_file, automaton); ++ fprintf (output_file, " [%s] + ", INTERNAL_INSN_CODE_NAME); ++ fprintf (output_file, "%s->", CHIP_PARAMETER_NAME); ++ output_chip_member_name (output_file, automaton); ++ fprintf (output_file, " * %d)", automaton->insn_equiv_classes_num); + fprintf +- (output_file, " [%s] %% %d + 1) * %d)) & %d;\n", +- INTERNAL_INSN_CODE_NAME, ++ (output_file, " %% %d + 1) * %d)) & %d;\n", + automaton->min_issue_delay_table_compression_factor, + 8 / automaton->min_issue_delay_table_compression_factor, + (1 << (8 / automaton->min_issue_delay_table_compression_factor)) +--- a/src/gcc/genemit.c ++++ b/src/gcc/genemit.c +@@ -222,6 +222,12 @@ + case PC: + printf ("pc_rtx"); + return; ++ case RETURN: ++ printf ("ret_rtx"); ++ return; ++ case SIMPLE_RETURN: ++ printf ("simple_return_rtx"); ++ return; + case CLOBBER: + if (REG_P (XEXP (x, 0))) + { +@@ -544,8 +550,8 @@ + || (GET_CODE (next) == PARALLEL + && ((GET_CODE (XVECEXP (next, 0, 0)) == SET + && GET_CODE (SET_DEST (XVECEXP (next, 0, 0))) == PC) +- || GET_CODE (XVECEXP (next, 0, 0)) == RETURN)) +- || GET_CODE (next) == RETURN) ++ || ANY_RETURN_P (XVECEXP (next, 0, 0)))) ++ || ANY_RETURN_P (next)) + printf (" emit_jump_insn ("); + else if ((GET_CODE (next) == SET && GET_CODE (SET_SRC (next)) == CALL) + || GET_CODE (next) == CALL +@@ -660,7 +666,7 @@ + || (GET_CODE (next) == PARALLEL + && GET_CODE (XVECEXP (next, 0, 0)) == SET + && GET_CODE (SET_DEST (XVECEXP (next, 0, 0))) == PC) +- || GET_CODE (next) == RETURN) ++ || ANY_RETURN_P (next)) + printf (" emit_jump_insn ("); + else if ((GET_CODE (next) == SET && GET_CODE (SET_SRC (next)) == CALL) + || GET_CODE (next) == CALL +--- a/src/gcc/gengenrtl.c ++++ b/src/gcc/gengenrtl.c +@@ -146,6 +146,10 @@ + || strcmp (defs[idx].enumname, "REG") == 0 + || strcmp (defs[idx].enumname, "SUBREG") == 0 + || strcmp (defs[idx].enumname, "MEM") == 0 ++ || strcmp (defs[idx].enumname, "PC") == 0 ++ || strcmp (defs[idx].enumname, "CC0") == 0 ++ || strcmp (defs[idx].enumname, "RETURN") == 0 ++ || strcmp (defs[idx].enumname, "SIMPLE_RETURN") == 0 + || strcmp (defs[idx].enumname, "CONST_VECTOR") == 0); + } + +--- a/src/gcc/gengtype-lex.c ++++ b/src/gcc/gengtype-lex.c +@@ -54,7 +54,6 @@ + typedef unsigned char flex_uint8_t; + typedef unsigned short int flex_uint16_t; + typedef unsigned int flex_uint32_t; +-#endif /* ! C99 */ + + /* Limits of integral types. */ + #ifndef INT8_MIN +@@ -85,6 +84,8 @@ + #define UINT32_MAX (4294967295U) + #endif + ++#endif /* ! C99 */ ++ + #endif /* ! FLEXINT_H */ + + #ifdef __cplusplus +@@ -141,7 +142,15 @@ + + /* Size of default input buffer. */ + #ifndef YY_BUF_SIZE ++#ifdef __ia64__ ++/* On IA-64, the buffer size is 16k, not 8k. ++ * Moreover, YY_BUF_SIZE is 2*YY_READ_BUF_SIZE in the general case. ++ * Ditto for the __ia64__ case accordingly. ++ */ ++#define YY_BUF_SIZE 32768 ++#else + #define YY_BUF_SIZE 16384 ++#endif /* __ia64__ */ + #endif + + /* The state buf must be large enough to hold one state per character in the main buffer. +@@ -372,7 +381,7 @@ + flex_int32_t yy_verify; + flex_int32_t yy_nxt; + }; +-static yyconst flex_int16_t yy_accept[438] = ++static yyconst flex_int16_t yy_accept[458] = + { 0, + 0, 0, 0, 0, 0, 0, 0, 0, 49, 36, + 33, 45, 36, 45, 34, 36, 36, 34, 34, 34, +@@ -383,43 +392,45 @@ + 0, 38, 32, 34, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 34, 34, 34, 34, 34, 10, 0, + 25, 0, 0, 0, 0, 9, 20, 24, 0, 0, +- 0, 0, 0, 0, 0, 0, 26, 11, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 26, 11, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 10, 0, 0, 0, 0, 42, 44, 43, +- 35, 0, 0, 0, 0, 0, 0, 34, 34, 34, +- 34, 34, 34, 27, 28, 0, 0, 0, 0, 0, ++ 0, 0, 0, 10, 0, 0, 0, 0, 42, 44, ++ 43, 35, 0, 0, 0, 0, 0, 0, 34, 34, ++ 34, 34, 34, 34, 27, 28, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 30, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 34, +- 34, 34, 34, 34, 34, 0, 0, 0, 13, 0, +- 14, 0, 0, 0, 0, 22, 22, 0, 0, 0, ++ 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 34, 34, 34, 34, 34, 34, 0, 0, 0, ++ 13, 0, 0, 14, 0, 0, 0, 0, 22, 22, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + +- 0, 0, 0, 0, 34, 34, 34, 34, 34, 34, +- 0, 0, 0, 0, 0, 17, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 34, 34, 34, ++ 34, 34, 34, 0, 0, 0, 0, 0, 0, 17, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 34, 34, 34, 34, 34, 3, 0, 0, +- 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, +- 0, 0, 0, 0, 0, 0, 0, 34, 4, 5, +- 2, 34, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 34, 34, 34, 34, ++ 34, 3, 0, 0, 0, 0, 0, 12, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, ++ 0, 0, 0, 34, 4, 5, 2, 34, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + +- 0, 0, 16, 0, 0, 0, 0, 34, 1, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 16, 0, 0, 0, 0, 34, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 22, 22, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 34, 34, 34, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 21, 0, 0, 0, 0, 0, 0, +- 34, 7, 6, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 18, 0, 0, 0, 34, 0, 0, 0, +- 0, 0, 0, 0, 0, 19, 0, 0, 47, 34, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 34, 0, 0, 0, 0, 0, 0, 0, 0, 34, +- +- 0, 24, 24, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, ++ 0, 0, 34, 7, 6, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 18, 0, 0, 0, + 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 19, 0, 0, 47, 34, 0, 0, 0, 0, ++ ++ 0, 0, 0, 0, 0, 0, 0, 34, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 34, 0, 24, ++ 24, 0, 0, 0, 0, 0, 0, 0, 0, 34, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 8, 0, 23, 0, 0, 0, 0, 0, + 40, 0, 0, 0, 0, 0, 0 + } ; +@@ -467,116 +478,122 @@ + 9, 9 + } ; + +-static yyconst flex_int16_t yy_base[476] = ++static yyconst flex_int16_t yy_base[496] = + { 0, +- 0, 38, 96, 12, 12, 13, 15, 16, 991, 1444, +- 1444, 16, 953, 979, 0, 157, 19, 970, 927, 929, +- 924, 932, 1444, 25, 27, 20, 1444, 946, 971, 971, +- 967, 215, 253, 4, 7, 25, 952, 36, 925, 959, +- 8, 31, 33, 37, 38, 32, 39, 133, 134, 40, +- 66, 959, 0, 1444, 948, 947, 159, 1444, 0, 951, +- 954, 1444, 1444, 0, 187, 162, 938, 895, 897, 892, +- 900, 163, 907, 931, 892, 32, 894, 899, 77, 162, +- 1444, 943, 938, 941, 932, 1444, 929, 1444, 914, 898, +- 140, 54, 142, 43, 156, 886, 1444, 1444, 144, 148, +- +- 143, 149, 151, 175, 158, 173, 152, 157, 184, 220, +- 212, 221, 231, 921, 920, 291, 0, 1444, 1444, 1444, +- 1444, 902, 863, 195, 865, 870, 872, 877, 871, 857, +- 855, 868, 858, 1444, 1444, 64, 171, 213, 353, 215, +- 391, 153, 349, 214, 244, 222, 245, 429, 241, 348, +- 248, 247, 351, 355, 339, 350, 357, 340, 429, 1444, +- 0, 0, 871, 865, 851, 849, 862, 852, 856, 870, +- 832, 838, 843, 841, 831, 341, 258, 342, 1444, 346, +- 1444, 352, 359, 491, 360, 1444, 528, 398, 392, 384, +- 387, 418, 419, 421, 395, 477, 0, 849, 826, 832, +- +- 837, 835, 825, 824, 857, 822, 831, 815, 827, 586, +- 434, 399, 437, 159, 624, 1444, 0, 843, 841, 841, +- 814, 819, 821, 797, 795, 323, 795, 478, 493, 483, +- 481, 393, 394, 662, 0, 828, 793, 802, 786, 798, +- 0, 797, 824, 700, 738, 776, 794, 1444, 254, 345, +- 396, 432, 1444, 811, 809, 806, 782, 794, 774, 400, +- 780, 778, 463, 774, 480, 499, 486, 487, 814, 1444, +- 0, 813, 0, 0, 0, 783, 453, 788, 1444, 1444, +- 1444, 852, 484, 509, 491, 520, 787, 794, 778, 758, +- 752, 767, 766, 514, 758, 748, 750, 757, 752, 512, +- +- 518, 513, 1444, 0, 760, 0, 539, 536, 1444, 527, +- 385, 533, 538, 759, 776, 757, 738, 737, 1444, 0, +- 736, 748, 752, 744, 524, 890, 545, 0, 585, 758, +- 749, 928, 966, 535, 546, 553, 575, 757, 757, 736, +- 726, 711, 528, 1444, 1004, 0, 743, 0, 0, 731, +- 741, 1444, 1444, 582, 583, 588, 577, 555, 742, 734, +- 740, 1042, 1444, 0, 737, 752, 732, 592, 591, 613, +- 540, 594, 727, 718, 739, 1444, 0, 728, 1444, 738, +- 621, 623, 622, 620, 624, 734, 722, 733, 0, 719, +- 695, 626, 686, 618, 711, 710, 645, 0, 692, 630, +- +- 651, 674, 677, 654, 711, 707, 695, 675, 0, 664, +- 1080, 656, 712, 693, 714, 716, 669, 633, 617, 628, +- 0, 0, 1444, 719, 1444, 721, 629, 593, 563, 530, +- 1444, 443, 252, 191, 163, 62, 1444, 1118, 1127, 1136, ++ 0, 38, 96, 12, 12, 13, 15, 16, 1038, 1444, ++ 1444, 16, 1000, 1026, 0, 157, 19, 1017, 974, 976, ++ 971, 979, 1444, 25, 27, 20, 1444, 993, 1018, 1018, ++ 1014, 215, 253, 4, 7, 25, 40, 41, 988, 1022, ++ 8, 31, 33, 36, 37, 38, 39, 133, 134, 136, ++ 67, 1022, 0, 1444, 1011, 1010, 160, 1444, 0, 1014, ++ 1017, 1444, 1444, 0, 187, 163, 1001, 958, 960, 940, ++ 948, 164, 955, 979, 940, 31, 942, 947, 77, 163, ++ 1444, 991, 986, 989, 980, 1444, 977, 1444, 962, 961, ++ 65, 58, 46, 141, 142, 159, 949, 1444, 1444, 149, ++ ++ 144, 151, 150, 152, 181, 153, 156, 184, 213, 214, ++ 220, 215, 221, 191, 984, 983, 291, 0, 1444, 1444, ++ 1444, 1444, 965, 926, 195, 928, 933, 935, 940, 919, ++ 905, 903, 916, 906, 1444, 1444, 171, 256, 160, 353, ++ 219, 201, 391, 354, 350, 222, 246, 355, 247, 429, ++ 339, 172, 244, 248, 352, 356, 340, 351, 359, 394, ++ 429, 1444, 0, 0, 919, 913, 899, 897, 910, 900, ++ 904, 918, 895, 901, 906, 904, 894, 249, 347, 348, ++ 1444, 349, 383, 1444, 386, 387, 491, 388, 1444, 528, ++ 419, 396, 384, 391, 477, 422, 478, 398, 479, 0, ++ ++ 912, 889, 895, 900, 898, 873, 872, 905, 870, 879, ++ 863, 875, 586, 437, 495, 492, 252, 203, 624, 1444, ++ 0, 891, 889, 496, 863, 868, 870, 861, 859, 322, ++ 859, 481, 499, 484, 489, 399, 488, 662, 0, 892, ++ 857, 866, 850, 862, 0, 861, 888, 700, 738, 776, ++ 858, 1444, 431, 344, 432, 433, 435, 1444, 860, 858, ++ 856, 854, 830, 842, 822, 363, 828, 826, 471, 822, ++ 508, 523, 491, 510, 814, 1444, 0, 861, 0, 0, ++ 0, 831, 511, 836, 1444, 1444, 1444, 852, 515, 513, ++ 524, 521, 536, 850, 857, 855, 840, 820, 814, 829, ++ ++ 828, 554, 820, 810, 797, 804, 799, 527, 545, 533, ++ 1444, 0, 807, 0, 562, 552, 1444, 353, 572, 540, ++ 573, 550, 806, 823, 804, 803, 784, 783, 1444, 0, ++ 782, 794, 798, 790, 548, 890, 558, 0, 589, 804, ++ 810, 928, 966, 582, 586, 588, 591, 610, 818, 818, ++ 802, 796, 786, 771, 592, 1444, 1004, 0, 803, 0, ++ 0, 776, 786, 1444, 1444, 621, 618, 623, 624, 625, ++ 631, 787, 779, 789, 784, 1042, 1444, 0, 781, 796, ++ 776, 619, 580, 630, 628, 648, 650, 771, 762, 780, ++ 782, 1444, 0, 771, 1444, 781, 661, 662, 664, 657, ++ ++ 655, 777, 765, 755, 775, 0, 776, 752, 666, 724, ++ 668, 768, 767, 743, 683, 0, 733, 692, 658, 713, ++ 715, 665, 753, 750, 751, 736, 743, 0, 701, 1080, ++ 703, 750, 722, 752, 754, 740, 709, 702, 692, 664, ++ 0, 0, 1444, 757, 1444, 759, 627, 602, 561, 530, ++ 1444, 438, 393, 378, 202, 56, 1444, 1118, 1127, 1136, + 1145, 1154, 1158, 1167, 1176, 1185, 1194, 1202, 1211, 1220, + 1229, 1238, 1247, 1256, 1265, 1273, 1282, 1290, 1298, 1306, + 1314, 1323, 1331, 1340, 1349, 1357, 1365, 1374, 1383, 1392, + 1400, 1409, 1417, 1426, 1435 ++ + } ; + +-static yyconst flex_int16_t yy_def[476] = ++static yyconst flex_int16_t yy_def[496] = + { 0, +- 438, 438, 437, 3, 439, 439, 439, 439, 437, 437, +- 437, 440, 441, 442, 443, 437, 437, 443, 443, 443, +- 443, 443, 437, 437, 437, 444, 437, 445, 437, 437, +- 437, 446, 446, 33, 33, 33, 33, 33, 447, 437, ++ 458, 458, 457, 3, 459, 459, 459, 459, 457, 457, ++ 457, 460, 461, 462, 463, 457, 457, 463, 463, 463, ++ 463, 463, 457, 457, 457, 464, 457, 465, 457, 457, ++ 457, 466, 466, 33, 33, 33, 33, 33, 467, 457, + 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, +- 437, 448, 449, 437, 450, 450, 440, 437, 440, 437, +- 441, 437, 437, 443, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 443, 443, 443, 443, 443, 437, 444, +- 437, 444, 437, 445, 437, 437, 437, 437, 33, 33, +- 33, 33, 33, 33, 33, 447, 437, 437, 33, 33, ++ 457, 468, 469, 457, 470, 470, 460, 457, 460, 457, ++ 461, 457, 457, 463, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 463, 463, 463, 463, 463, 457, 464, ++ 457, 464, 457, 465, 457, 457, 457, 457, 33, 33, ++ 33, 33, 33, 33, 33, 33, 467, 457, 457, 33, + + 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, +- 33, 33, 437, 448, 448, 437, 451, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 443, 443, 443, +- 443, 443, 443, 437, 437, 33, 33, 33, 446, 33, +- 446, 33, 33, 33, 33, 33, 33, 446, 33, 33, +- 33, 33, 33, 33, 33, 33, 33, 33, 116, 437, +- 116, 452, 437, 437, 437, 437, 437, 437, 437, 443, +- 443, 443, 443, 443, 443, 33, 33, 33, 437, 33, +- 437, 33, 33, 446, 33, 437, 437, 33, 33, 33, +- 33, 33, 33, 33, 33, 33, 453, 437, 437, 437, +- +- 437, 437, 437, 437, 443, 443, 443, 443, 443, 443, +- 33, 33, 33, 33, 446, 437, 187, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 33, 33, 33, +- 33, 33, 33, 446, 454, 437, 437, 437, 437, 437, +- 455, 437, 443, 443, 443, 443, 443, 437, 33, 33, +- 33, 33, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 33, 33, 33, 33, 446, 437, +- 456, 437, 457, 458, 459, 437, 437, 443, 437, 437, +- 437, 443, 33, 33, 33, 33, 437, 437, 437, 437, +- 437, 437, 437, 460, 437, 437, 437, 437, 437, 33, +- +- 33, 33, 437, 461, 437, 462, 437, 443, 437, 33, +- 33, 33, 33, 437, 437, 437, 437, 437, 437, 187, +- 437, 437, 437, 437, 33, 446, 33, 463, 437, 437, +- 443, 443, 443, 33, 33, 33, 33, 437, 437, 437, +- 437, 437, 33, 437, 446, 464, 437, 465, 466, 437, +- 443, 437, 437, 33, 33, 33, 33, 33, 437, 437, +- 437, 446, 437, 467, 437, 437, 443, 33, 33, 33, +- 33, 33, 437, 437, 437, 437, 468, 437, 437, 443, +- 33, 33, 33, 33, 33, 437, 437, 437, 469, 437, +- 443, 33, 33, 33, 437, 437, 437, 470, 437, 443, +- +- 33, 437, 471, 33, 437, 437, 437, 437, 472, 437, +- 443, 33, 437, 471, 471, 473, 437, 437, 437, 437, +- 474, 475, 437, 437, 437, 473, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 0, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437 ++ 33, 33, 33, 457, 468, 468, 457, 471, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 463, 463, ++ 463, 463, 463, 463, 457, 457, 33, 33, 33, 466, ++ 33, 33, 466, 33, 33, 33, 33, 33, 33, 466, ++ 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, ++ 117, 457, 117, 472, 457, 457, 457, 457, 457, 457, ++ 457, 463, 463, 463, 463, 463, 463, 33, 33, 33, ++ 457, 33, 33, 457, 33, 33, 466, 33, 457, 457, ++ 33, 33, 33, 33, 33, 33, 33, 33, 33, 473, ++ ++ 457, 457, 457, 457, 457, 457, 457, 463, 463, 463, ++ 463, 463, 463, 33, 33, 33, 33, 33, 466, 457, ++ 190, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 33, 33, 33, 33, 33, 33, 466, 474, 457, ++ 457, 457, 457, 457, 475, 457, 463, 463, 463, 463, ++ 463, 457, 33, 33, 33, 33, 33, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 33, 33, 33, 33, 466, 457, 476, 457, 477, 478, ++ 479, 457, 457, 463, 457, 457, 457, 463, 33, 33, ++ 33, 33, 33, 457, 457, 457, 457, 457, 457, 457, ++ ++ 457, 480, 457, 457, 457, 457, 457, 33, 33, 33, ++ 457, 481, 457, 482, 457, 463, 457, 33, 33, 33, ++ 33, 33, 457, 457, 457, 457, 457, 457, 457, 190, ++ 457, 457, 457, 457, 33, 466, 33, 483, 457, 457, ++ 463, 463, 463, 33, 33, 33, 33, 33, 457, 457, ++ 457, 457, 457, 457, 33, 457, 466, 484, 457, 485, ++ 486, 457, 463, 457, 457, 33, 33, 33, 33, 33, ++ 33, 457, 457, 457, 457, 466, 457, 487, 457, 457, ++ 463, 33, 33, 33, 33, 33, 33, 457, 457, 457, ++ 457, 457, 488, 457, 457, 463, 33, 33, 33, 33, ++ ++ 33, 457, 457, 457, 457, 489, 457, 463, 33, 33, ++ 33, 457, 457, 457, 457, 490, 457, 463, 33, 457, ++ 491, 33, 457, 457, 457, 457, 457, 492, 457, 463, ++ 33, 457, 491, 491, 493, 457, 457, 457, 457, 457, ++ 494, 495, 457, 457, 457, 493, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 0, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457 ++ + } ; + + static yyconst flex_int16_t yy_nxt[1507] = +@@ -586,11 +603,11 @@ + 72, 55, 55, 81, 56, 56, 79, 79, 79, 79, + 89, 91, 92, 89, 89, 10, 10, 10, 10, 16, + 11, 12, 17, 10, 13, 10, 10, 10, 10, 14, +- 10, 89, 59, 95, 18, 93, 82, 89, 89, 89, +- 99, 73, 89, 89, 89, 89, 89, 113, 79, 89, +- 114, 130, 140, 10, 10, 10, 102, 100, 79, 79, +- 89, 19, 106, 101, 105, 138, 131, 176, 103, 104, +- 89, 112, 294, 20, 21, 22, 23, 24, 25, 26, ++ 10, 89, 59, 94, 18, 93, 82, 89, 96, 89, ++ 100, 73, 89, 89, 89, 89, 95, 89, 114, 79, ++ 131, 115, 89, 10, 10, 10, 103, 101, 79, 79, ++ 140, 19, 107, 102, 89, 132, 302, 104, 105, 139, ++ 106, 89, 138, 20, 21, 22, 23, 24, 25, 26, + + 23, 27, 28, 27, 27, 27, 29, 30, 31, 32, + 33, 34, 32, 35, 32, 36, 37, 32, 32, 32, +@@ -598,155 +615,155 @@ + 32, 39, 40, 23, 32, 32, 41, 42, 43, 44, + 32, 32, 32, 45, 32, 46, 32, 47, 32, 48, + 32, 49, 32, 50, 32, 32, 32, 32, 65, 89, +- 89, 66, 58, 72, 72, 81, 89, 137, 89, 89, +- 89, 141, 107, 67, 89, 89, 139, 89, 89, 89, +- 109, 110, 89, 89, 89, 89, 177, 143, 65, 108, +- 111, 66, 252, 294, 144, 59, 142, 89, 82, 89, ++ 89, 66, 89, 58, 72, 72, 81, 89, 89, 141, ++ 89, 142, 108, 67, 143, 89, 89, 89, 89, 89, ++ 110, 111, 89, 145, 180, 89, 89, 113, 65, 109, ++ 112, 66, 114, 79, 178, 115, 59, 89, 89, 82, + +- 68, 89, 148, 67, 73, 73, 151, 145, 146, 149, ++ 68, 144, 146, 67, 151, 73, 73, 89, 147, 148, + 89, 152, 69, 70, 71, 88, 88, 88, 88, 88, +- 88, 88, 88, 88, 88, 88, 88, 147, 150, 436, +- 68, 148, 113, 79, 165, 114, 153, 178, 89, 89, +- 89, 89, 69, 70, 71, 180, 89, 89, 89, 166, ++ 88, 88, 88, 88, 88, 88, 88, 89, 191, 89, ++ 68, 183, 302, 149, 167, 182, 257, 150, 153, 89, ++ 89, 89, 69, 70, 71, 89, 89, 89, 89, 168, + 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, +- 88, 88, 88, 88, 88, 154, 156, 89, 157, 182, +- 89, 89, 184, 89, 89, 283, 158, 435, 212, 90, +- 89, 155, 183, 185, 89, 190, 148, 189, 88, 88, +- 88, 159, 159, 160, 159, 159, 159, 159, 159, 159, +- +- 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, +- 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, +- 159, 159, 159, 159, 159, 159, 159, 159, 159, 161, ++ 88, 88, 88, 88, 88, 156, 155, 154, 159, 158, ++ 89, 179, 89, 89, 89, 89, 160, 185, 89, 90, ++ 256, 157, 89, 192, 186, 188, 193, 214, 88, 88, ++ 88, 161, 161, 162, 161, 161, 161, 161, 161, 161, ++ ++ 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, ++ 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, ++ 161, 161, 161, 161, 161, 161, 161, 161, 161, 163, ++ 163, 163, 163, 163, 163, 163, 163, 163, 163, 163, ++ 163, 163, 163, 163, 163, 163, 163, 163, 163, 163, ++ 163, 163, 163, 181, 181, 181, 181, 181, 181, 181, ++ 181, 181, 181, 181, 181, 89, 89, 215, 268, 269, ++ 89, 344, 290, 89, 89, 89, 89, 89, 89, 89, ++ 89, 89, 89, 196, 150, 89, 216, 217, 181, 181, ++ 181, 184, 184, 184, 184, 184, 184, 184, 184, 184, ++ ++ 184, 184, 184, 150, 150, 187, 194, 195, 197, 89, ++ 89, 198, 89, 89, 89, 301, 456, 89, 455, 302, ++ 89, 218, 89, 234, 89, 89, 184, 184, 184, 189, ++ 190, 190, 189, 189, 189, 189, 189, 189, 189, 189, ++ 189, 199, 219, 150, 150, 89, 233, 150, 89, 238, ++ 292, 253, 289, 291, 454, 150, 293, 89, 89, 89, ++ 236, 89, 232, 89, 189, 189, 189, 161, 161, 161, + 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, + 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, +- 161, 161, 161, 179, 179, 179, 179, 179, 179, 179, +- 179, 179, 179, 179, 179, 89, 89, 89, 89, 262, +- 263, 89, 89, 284, 89, 89, 89, 89, 89, 211, +- 213, 89, 193, 89, 214, 89, 89, 196, 179, 179, +- 179, 181, 181, 181, 181, 181, 181, 181, 181, 181, +- +- 181, 181, 181, 148, 188, 191, 192, 194, 215, 195, +- 89, 89, 250, 89, 335, 148, 148, 285, 89, 89, +- 89, 89, 89, 230, 89, 89, 181, 181, 181, 186, +- 187, 187, 186, 186, 186, 186, 186, 186, 186, 186, +- 186, 228, 229, 148, 89, 89, 234, 89, 249, 148, +- 269, 251, 293, 286, 307, 307, 294, 232, 89, 434, +- 89, 231, 233, 89, 186, 186, 186, 159, 159, 159, +- 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, +- 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, +- 159, 216, 216, 216, 216, 216, 216, 216, 216, 216, +- +- 216, 216, 216, 89, 89, 266, 89, 89, 297, 89, +- 89, 266, 89, 89, 310, 320, 320, 89, 300, 89, +- 265, 312, 154, 148, 298, 89, 216, 216, 216, 217, +- 217, 267, 268, 301, 302, 89, 313, 267, 89, 89, +- 307, 307, 218, 219, 89, 334, 89, 311, 220, 331, +- 89, 336, 327, 89, 89, 337, 354, 332, 330, 89, +- 294, 89, 333, 333, 89, 325, 89, 355, 221, 222, +- 223, 89, 89, 326, 356, 224, 372, 225, 384, 89, +- 343, 89, 362, 226, 433, 227, 248, 248, 248, 248, +- 248, 248, 248, 248, 248, 248, 248, 248, 347, 368, +- +- 345, 89, 369, 89, 357, 370, 348, 371, 89, 89, +- 432, 349, 349, 358, 89, 381, 382, 89, 89, 385, +- 89, 248, 248, 248, 253, 253, 253, 253, 253, 253, +- 253, 253, 253, 253, 253, 253, 383, 148, 393, 89, +- 392, 394, 401, 404, 89, 294, 89, 89, 89, 89, +- 89, 411, 89, 430, 148, 429, 411, 411, 428, 253, +- 253, 253, 270, 270, 270, 270, 270, 270, 270, 270, +- 270, 270, 270, 270, 407, 413, 413, 89, 415, 415, +- 89, 414, 89, 408, 148, 422, 148, 402, 402, 412, +- 422, 422, 427, 403, 415, 415, 420, 270, 270, 270, +- +- 279, 279, 279, 279, 279, 279, 279, 279, 279, 279, +- 279, 279, 89, 413, 413, 415, 415, 424, 424, 414, +- 424, 424, 424, 424, 425, 419, 418, 425, 417, 425, +- 410, 406, 405, 400, 399, 279, 279, 279, 280, 280, +- 280, 280, 280, 280, 280, 280, 280, 280, 280, 280, +- 397, 396, 395, 391, 390, 388, 387, 386, 380, 379, +- 378, 375, 374, 373, 367, 366, 365, 294, 294, 361, +- 360, 359, 351, 280, 280, 280, 281, 281, 281, 281, +- 281, 281, 281, 281, 281, 281, 281, 281, 350, 297, +- 342, 341, 294, 294, 294, 340, 339, 338, 329, 324, +- +- 323, 322, 321, 294, 318, 317, 294, 294, 316, 315, +- 314, 281, 281, 281, 303, 303, 303, 303, 303, 303, +- 303, 303, 303, 303, 303, 303, 308, 306, 305, 299, +- 296, 295, 292, 291, 290, 289, 288, 287, 282, 278, +- 277, 276, 275, 274, 273, 272, 264, 261, 260, 303, +- 303, 303, 309, 309, 309, 309, 309, 309, 309, 309, +- 309, 309, 309, 309, 259, 258, 257, 256, 255, 254, +- 247, 246, 245, 244, 243, 242, 241, 240, 239, 238, +- 237, 236, 210, 209, 208, 207, 206, 309, 309, 309, +- 344, 344, 344, 344, 344, 344, 344, 344, 344, 344, +- +- 344, 344, 205, 204, 203, 202, 201, 200, 199, 198, +- 175, 174, 173, 172, 171, 170, 169, 168, 167, 164, +- 163, 115, 115, 97, 136, 344, 344, 344, 352, 352, +- 352, 352, 352, 352, 352, 352, 352, 352, 352, 352, +- 89, 87, 135, 437, 134, 437, 133, 132, 129, 128, +- 127, 126, 125, 124, 123, 122, 437, 121, 120, 119, +- 115, 98, 97, 352, 352, 352, 353, 353, 353, 353, +- 353, 353, 353, 353, 353, 353, 353, 353, 94, 87, +- 86, 85, 84, 78, 77, 76, 75, 74, 63, 61, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- +- 437, 353, 353, 353, 363, 363, 363, 363, 363, 363, +- 363, 363, 363, 363, 363, 363, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 363, +- 363, 363, 376, 376, 376, 376, 376, 376, 376, 376, +- 376, 376, 376, 376, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 376, 376, 376, +- 423, 423, 423, 423, 423, 423, 423, 423, 423, 423, +- 423, 423, 437, 437, 437, 437, 437, 437, 437, 437, ++ 161, 220, 220, 220, 220, 220, 220, 220, 220, 220, + +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 423, 423, 423, 15, 15, ++ 220, 220, 220, 89, 89, 89, 255, 89, 254, 261, ++ 89, 272, 315, 315, 89, 89, 305, 89, 89, 237, ++ 235, 89, 262, 271, 156, 89, 220, 220, 220, 221, ++ 221, 150, 306, 274, 89, 272, 89, 273, 309, 89, ++ 321, 89, 222, 223, 275, 318, 308, 89, 224, 89, ++ 89, 319, 322, 89, 320, 330, 330, 310, 346, 89, ++ 302, 273, 89, 315, 315, 341, 89, 348, 225, 226, ++ 227, 89, 337, 342, 89, 228, 89, 229, 343, 343, ++ 335, 340, 453, 230, 89, 231, 252, 252, 252, 252, ++ 252, 252, 252, 252, 252, 252, 252, 252, 89, 89, ++ ++ 336, 345, 359, 366, 355, 398, 89, 367, 89, 368, ++ 360, 347, 89, 357, 89, 361, 361, 89, 89, 452, ++ 369, 252, 252, 252, 258, 258, 258, 258, 258, 258, ++ 258, 258, 258, 258, 258, 258, 89, 383, 382, 370, ++ 384, 385, 397, 302, 89, 89, 376, 89, 371, 89, ++ 89, 89, 387, 399, 89, 386, 89, 89, 150, 258, ++ 258, 258, 276, 276, 276, 276, 276, 276, 276, 276, ++ 276, 276, 276, 276, 89, 401, 89, 150, 411, 409, ++ 410, 89, 419, 89, 89, 150, 400, 89, 89, 450, ++ 89, 89, 89, 422, 89, 150, 431, 276, 276, 276, ++ ++ 285, 285, 285, 285, 285, 285, 285, 285, 285, 285, ++ 285, 285, 426, 430, 432, 432, 434, 434, 430, 430, ++ 433, 427, 442, 434, 434, 420, 420, 442, 442, 89, ++ 449, 421, 302, 150, 448, 285, 285, 285, 286, 286, ++ 286, 286, 286, 286, 286, 286, 286, 286, 286, 286, ++ 89, 432, 432, 434, 434, 444, 444, 433, 444, 444, ++ 444, 444, 445, 447, 440, 445, 439, 445, 438, 437, ++ 436, 429, 425, 286, 286, 286, 287, 287, 287, 287, ++ 287, 287, 287, 287, 287, 287, 287, 287, 424, 423, ++ 418, 417, 415, 414, 413, 412, 408, 407, 405, 404, ++ ++ 403, 402, 396, 395, 394, 391, 390, 389, 388, 381, ++ 380, 287, 287, 287, 311, 311, 311, 311, 311, 311, ++ 311, 311, 311, 311, 311, 311, 379, 302, 302, 375, ++ 374, 373, 372, 363, 362, 305, 354, 353, 302, 302, ++ 302, 352, 351, 350, 349, 339, 334, 333, 332, 311, ++ 311, 311, 317, 317, 317, 317, 317, 317, 317, 317, ++ 317, 317, 317, 317, 331, 302, 328, 327, 302, 302, ++ 326, 325, 324, 323, 316, 314, 313, 307, 304, 303, ++ 300, 299, 298, 297, 296, 295, 294, 317, 317, 317, ++ 356, 356, 356, 356, 356, 356, 356, 356, 356, 356, ++ ++ 356, 356, 288, 284, 283, 282, 281, 280, 279, 278, ++ 270, 267, 266, 265, 264, 263, 260, 259, 251, 250, ++ 249, 248, 247, 246, 245, 356, 356, 356, 364, 364, ++ 364, 364, 364, 364, 364, 364, 364, 364, 364, 364, ++ 244, 243, 242, 241, 240, 213, 212, 211, 210, 209, ++ 208, 207, 206, 205, 204, 203, 202, 201, 177, 176, ++ 175, 174, 173, 364, 364, 364, 365, 365, 365, 365, ++ 365, 365, 365, 365, 365, 365, 365, 365, 172, 171, ++ 170, 169, 166, 165, 116, 116, 98, 137, 89, 87, ++ 136, 457, 135, 457, 134, 133, 130, 129, 128, 127, ++ ++ 126, 365, 365, 365, 377, 377, 377, 377, 377, 377, ++ 377, 377, 377, 377, 377, 377, 125, 124, 123, 457, ++ 122, 121, 120, 116, 99, 98, 87, 86, 85, 84, ++ 78, 77, 76, 75, 74, 63, 61, 457, 457, 377, ++ 377, 377, 392, 392, 392, 392, 392, 392, 392, 392, ++ 392, 392, 392, 392, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 392, 392, 392, ++ 443, 443, 443, 443, 443, 443, 443, 443, 443, 443, ++ 443, 443, 457, 457, 457, 457, 457, 457, 457, 457, ++ ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 443, 443, 443, 15, 15, + 15, 15, 15, 15, 15, 15, 15, 53, 53, 53, + 53, 53, 53, 53, 53, 53, 57, 57, 57, 57, + 57, 57, 57, 57, 57, 60, 60, 60, 60, 60, + 60, 60, 60, 60, 62, 62, 62, 62, 62, 62, +- 62, 62, 62, 64, 64, 437, 64, 80, 80, 80, ++ 62, 62, 62, 64, 64, 457, 64, 80, 80, 80, + 80, 80, 80, 80, 80, 80, 83, 83, 83, 83, + 83, 83, 83, 83, 83, 89, 89, 89, 89, 89, +- 89, 89, 89, 89, 96, 96, 96, 96, 96, 96, ++ 89, 89, 89, 89, 97, 97, 97, 97, 97, 97, + +- 96, 437, 96, 116, 437, 437, 437, 437, 437, 437, +- 116, 117, 117, 437, 117, 437, 117, 117, 117, 117, +- 118, 118, 118, 118, 118, 118, 118, 118, 118, 162, +- 162, 437, 162, 437, 162, 162, 162, 162, 197, 197, +- 437, 197, 437, 197, 197, 197, 197, 235, 235, 437, +- 235, 437, 235, 235, 235, 235, 271, 271, 437, 271, +- 437, 271, 271, 271, 271, 248, 248, 248, 248, 248, +- 437, 437, 248, 304, 304, 437, 304, 437, 304, 304, +- 304, 304, 279, 279, 279, 279, 279, 437, 437, 279, +- 280, 280, 280, 280, 280, 437, 437, 280, 281, 281, +- +- 281, 281, 281, 437, 437, 281, 319, 319, 319, 319, +- 319, 437, 437, 319, 328, 328, 437, 328, 437, 328, +- 328, 328, 328, 309, 309, 309, 309, 309, 437, 437, +- 309, 346, 346, 437, 346, 437, 346, 346, 346, 346, +- 364, 364, 437, 364, 437, 364, 364, 364, 364, 352, +- 352, 352, 352, 352, 437, 437, 352, 353, 353, 353, +- 353, 353, 437, 437, 353, 377, 377, 437, 377, 437, +- 377, 377, 377, 377, 389, 389, 437, 389, 437, 389, +- 389, 389, 389, 398, 398, 437, 398, 437, 398, 398, +- 398, 398, 409, 409, 437, 409, 437, 409, 409, 409, +- +- 409, 416, 416, 437, 437, 437, 416, 437, 416, 421, +- 421, 437, 421, 437, 421, 421, 421, 421, 426, 426, +- 426, 437, 426, 426, 437, 426, 431, 431, 437, 431, +- 437, 431, 431, 431, 431, 423, 423, 423, 423, 423, +- 437, 437, 423, 9, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, ++ 97, 457, 97, 117, 457, 457, 457, 457, 457, 457, ++ 117, 118, 118, 457, 118, 457, 118, 118, 118, 118, ++ 119, 119, 119, 119, 119, 119, 119, 119, 119, 164, ++ 164, 457, 164, 457, 164, 164, 164, 164, 200, 200, ++ 457, 200, 457, 200, 200, 200, 200, 239, 239, 457, ++ 239, 457, 239, 239, 239, 239, 277, 277, 457, 277, ++ 457, 277, 277, 277, 277, 252, 252, 252, 252, 252, ++ 457, 457, 252, 312, 312, 457, 312, 457, 312, 312, ++ 312, 312, 285, 285, 285, 285, 285, 457, 457, 285, ++ 286, 286, 286, 286, 286, 457, 457, 286, 287, 287, ++ ++ 287, 287, 287, 457, 457, 287, 329, 329, 329, 329, ++ 329, 457, 457, 329, 338, 338, 457, 338, 457, 338, ++ 338, 338, 338, 317, 317, 317, 317, 317, 457, 457, ++ 317, 358, 358, 457, 358, 457, 358, 358, 358, 358, ++ 378, 378, 457, 378, 457, 378, 378, 378, 378, 364, ++ 364, 364, 364, 364, 457, 457, 364, 365, 365, 365, ++ 365, 365, 457, 457, 365, 393, 393, 457, 393, 457, ++ 393, 393, 393, 393, 406, 406, 457, 406, 457, 406, ++ 406, 406, 406, 416, 416, 457, 416, 457, 416, 416, ++ 416, 416, 428, 428, 457, 428, 457, 428, 428, 428, ++ ++ 428, 435, 435, 457, 457, 457, 435, 457, 435, 441, ++ 441, 457, 441, 457, 441, 441, 441, 441, 446, 446, ++ 446, 457, 446, 446, 457, 446, 451, 451, 457, 451, ++ 457, 451, 451, 451, 451, 443, 443, 443, 443, 443, ++ 457, 457, 443, 9, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, + +- 437, 437, 437, 437, 437, 437 ++ 457, 457, 457, 457, 457, 457 + } ; + + static yyconst flex_int16_t yy_chk[1507] = +@@ -756,11 +773,11 @@ + 17, 5, 6, 26, 7, 8, 24, 24, 25, 25, + 34, 34, 35, 35, 41, 1, 1, 1, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, +- 2, 36, 12, 38, 2, 36, 26, 42, 46, 43, +- 41, 17, 38, 44, 45, 47, 50, 51, 51, 94, +- 51, 76, 94, 2, 2, 2, 43, 42, 79, 79, +- 92, 2, 47, 42, 46, 92, 76, 136, 44, 45, +- 136, 50, 436, 2, 2, 2, 3, 3, 3, 3, ++ 2, 36, 12, 37, 2, 36, 26, 42, 38, 43, ++ 41, 17, 44, 45, 46, 47, 37, 38, 51, 51, ++ 76, 51, 93, 2, 2, 2, 43, 42, 79, 79, ++ 93, 2, 47, 42, 92, 76, 456, 44, 45, 92, ++ 46, 91, 91, 2, 2, 2, 3, 3, 3, 3, + + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, +@@ -768,155 +785,155 @@ + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 16, 48, +- 49, 16, 57, 66, 72, 80, 91, 91, 93, 101, +- 99, 95, 48, 16, 100, 102, 93, 103, 107, 142, +- 49, 49, 95, 108, 105, 214, 137, 100, 65, 48, +- 49, 65, 214, 435, 101, 57, 99, 137, 80, 106, +- +- 16, 104, 142, 65, 66, 72, 107, 102, 103, 105, +- 109, 108, 16, 16, 16, 32, 32, 32, 32, 32, +- 32, 32, 32, 32, 32, 32, 32, 104, 106, 434, +- 65, 104, 113, 113, 124, 113, 109, 138, 111, 138, +- 144, 140, 65, 65, 65, 140, 110, 112, 146, 124, ++ 49, 16, 50, 57, 66, 72, 80, 94, 95, 94, ++ 101, 95, 48, 16, 96, 100, 103, 102, 104, 106, ++ 49, 49, 107, 101, 139, 96, 139, 50, 65, 48, ++ 49, 65, 114, 114, 137, 114, 57, 137, 152, 80, ++ ++ 16, 100, 102, 65, 106, 66, 72, 105, 103, 104, ++ 108, 107, 16, 16, 16, 32, 32, 32, 32, 32, ++ 32, 32, 32, 32, 32, 32, 32, 142, 152, 218, ++ 65, 142, 455, 105, 125, 141, 218, 105, 108, 109, ++ 110, 112, 65, 65, 65, 141, 111, 113, 146, 125, + 32, 32, 32, 33, 33, 33, 33, 33, 33, 33, +- 33, 33, 33, 33, 33, 110, 111, 149, 112, 144, +- 145, 147, 146, 152, 151, 249, 112, 433, 177, 33, +- 249, 110, 145, 147, 177, 152, 149, 151, 33, 33, +- 33, 116, 116, 116, 116, 116, 116, 116, 116, 116, +- +- 116, 116, 116, 116, 116, 116, 116, 116, 116, 116, +- 116, 116, 116, 116, 116, 116, 116, 116, 116, 116, +- 116, 116, 116, 116, 116, 116, 116, 116, 116, 116, +- 116, 116, 116, 116, 116, 116, 116, 116, 116, 116, +- 116, 116, 116, 116, 116, 116, 116, 116, 116, 116, +- 116, 116, 116, 139, 139, 139, 139, 139, 139, 139, +- 139, 139, 139, 139, 139, 155, 158, 176, 178, 226, +- 226, 250, 180, 250, 150, 143, 156, 153, 182, 176, +- 178, 154, 155, 157, 180, 183, 185, 158, 139, 139, +- 139, 141, 141, 141, 141, 141, 141, 141, 141, 141, +- +- 141, 141, 141, 143, 150, 153, 154, 156, 182, 157, +- 190, 311, 212, 191, 311, 183, 185, 251, 189, 232, +- 233, 195, 251, 190, 188, 212, 141, 141, 141, 148, +- 148, 148, 148, 148, 148, 148, 148, 148, 148, 148, +- 148, 188, 189, 191, 192, 193, 195, 194, 211, 232, +- 233, 213, 260, 252, 277, 277, 260, 193, 252, 432, +- 211, 192, 194, 213, 148, 148, 148, 159, 159, 159, +- 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, +- 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, +- 159, 184, 184, 184, 184, 184, 184, 184, 184, 184, +- +- 184, 184, 184, 196, 228, 229, 265, 231, 263, 230, +- 283, 266, 267, 268, 283, 294, 294, 285, 265, 229, +- 228, 285, 196, 231, 263, 266, 184, 184, 184, 187, +- 187, 229, 230, 267, 268, 284, 286, 266, 300, 302, +- 307, 307, 187, 187, 301, 310, 286, 284, 187, 308, +- 325, 312, 302, 310, 343, 313, 334, 308, 307, 312, +- 430, 334, 308, 308, 313, 300, 371, 335, 187, 187, +- 187, 327, 335, 301, 336, 187, 358, 187, 371, 336, +- 325, 358, 343, 187, 429, 187, 210, 210, 210, 210, +- 210, 210, 210, 210, 210, 210, 210, 210, 329, 354, +- +- 327, 337, 355, 357, 337, 356, 329, 357, 354, 355, +- 428, 329, 329, 337, 356, 368, 369, 369, 368, 372, +- 372, 210, 210, 210, 215, 215, 215, 215, 215, 215, +- 215, 215, 215, 215, 215, 215, 370, 381, 383, 370, +- 382, 384, 392, 394, 394, 427, 384, 381, 383, 382, +- 385, 400, 392, 420, 385, 419, 400, 400, 418, 215, +- 215, 215, 234, 234, 234, 234, 234, 234, 234, 234, +- 234, 234, 234, 234, 397, 402, 402, 401, 403, 403, +- 404, 402, 412, 397, 404, 410, 412, 393, 393, 401, +- 410, 410, 417, 393, 414, 414, 408, 234, 234, 234, +- +- 244, 244, 244, 244, 244, 244, 244, 244, 244, 244, +- 244, 244, 393, 413, 413, 415, 415, 416, 416, 413, +- 424, 424, 426, 426, 416, 407, 406, 424, 405, 426, +- 399, 396, 395, 391, 390, 244, 244, 244, 245, 245, +- 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, +- 388, 387, 386, 380, 378, 375, 374, 373, 367, 366, +- 365, 361, 360, 359, 351, 350, 347, 342, 341, 340, +- 339, 338, 331, 245, 245, 245, 246, 246, 246, 246, +- 246, 246, 246, 246, 246, 246, 246, 246, 330, 324, +- 323, 322, 321, 318, 317, 316, 315, 314, 305, 299, +- +- 298, 297, 296, 295, 293, 292, 291, 290, 289, 288, +- 287, 246, 246, 246, 269, 269, 269, 269, 269, 269, +- 269, 269, 269, 269, 269, 269, 278, 276, 272, 264, +- 262, 261, 259, 258, 257, 256, 255, 254, 247, 243, +- 242, 240, 239, 238, 237, 236, 227, 225, 224, 269, +- 269, 269, 282, 282, 282, 282, 282, 282, 282, 282, +- 282, 282, 282, 282, 223, 222, 221, 220, 219, 218, +- 209, 208, 207, 206, 205, 204, 203, 202, 201, 200, +- 199, 198, 175, 174, 173, 172, 171, 282, 282, 282, +- 326, 326, 326, 326, 326, 326, 326, 326, 326, 326, +- +- 326, 326, 170, 169, 168, 167, 166, 165, 164, 163, +- 133, 132, 131, 130, 129, 128, 127, 126, 125, 123, +- 122, 115, 114, 96, 90, 326, 326, 326, 332, 332, +- 332, 332, 332, 332, 332, 332, 332, 332, 332, 332, +- 89, 87, 85, 84, 83, 82, 78, 77, 75, 74, +- 73, 71, 70, 69, 68, 67, 61, 60, 56, 55, +- 52, 40, 39, 332, 332, 332, 333, 333, 333, 333, +- 333, 333, 333, 333, 333, 333, 333, 333, 37, 31, +- 30, 29, 28, 22, 21, 20, 19, 18, 14, 13, +- 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 33, 33, 33, 33, 33, 111, 110, 109, 113, 112, ++ 153, 138, 147, 149, 154, 178, 113, 146, 217, 33, ++ 217, 111, 138, 153, 147, 149, 154, 178, 33, 33, ++ 33, 117, 117, 117, 117, 117, 117, 117, 117, 117, ++ ++ 117, 117, 117, 117, 117, 117, 117, 117, 117, 117, ++ 117, 117, 117, 117, 117, 117, 117, 117, 117, 117, ++ 117, 117, 117, 117, 117, 117, 117, 117, 117, 117, ++ 117, 117, 117, 117, 117, 117, 117, 117, 117, 117, ++ 117, 117, 117, 117, 117, 117, 117, 117, 117, 117, ++ 117, 117, 117, 140, 140, 140, 140, 140, 140, 140, ++ 140, 140, 140, 140, 140, 151, 157, 179, 230, 230, ++ 254, 318, 254, 179, 180, 182, 145, 158, 155, 318, ++ 144, 148, 156, 157, 151, 159, 180, 182, 140, 140, ++ 140, 143, 143, 143, 143, 143, 143, 143, 143, 143, ++ ++ 143, 143, 143, 144, 145, 148, 155, 156, 158, 183, ++ 193, 159, 185, 186, 188, 266, 454, 194, 453, 266, ++ 160, 183, 192, 193, 198, 236, 143, 143, 143, 150, ++ 150, 150, 150, 150, 150, 150, 150, 150, 150, 150, ++ 150, 160, 185, 186, 188, 191, 192, 194, 196, 198, ++ 256, 214, 253, 255, 452, 236, 257, 253, 255, 256, ++ 196, 257, 191, 214, 150, 150, 150, 161, 161, 161, ++ 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, ++ 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, ++ 161, 187, 187, 187, 187, 187, 187, 187, 187, 187, + +- 0, 333, 333, 333, 345, 345, 345, 345, 345, 345, +- 345, 345, 345, 345, 345, 345, 0, 0, 0, 0, ++ 187, 187, 187, 195, 197, 199, 216, 232, 215, 224, ++ 234, 233, 283, 283, 237, 235, 269, 273, 216, 197, ++ 195, 215, 224, 232, 199, 233, 187, 187, 187, 190, ++ 190, 235, 269, 234, 271, 272, 274, 233, 273, 290, ++ 292, 289, 190, 190, 237, 289, 271, 292, 190, 272, ++ 291, 290, 293, 308, 291, 302, 302, 274, 320, 310, ++ 450, 272, 293, 315, 315, 316, 320, 322, 190, 190, ++ 190, 309, 310, 316, 335, 190, 322, 190, 316, 316, ++ 308, 315, 449, 190, 337, 190, 213, 213, 213, 213, ++ 213, 213, 213, 213, 213, 213, 213, 213, 319, 321, ++ ++ 309, 319, 339, 344, 335, 383, 383, 345, 344, 346, ++ 339, 321, 345, 337, 346, 339, 339, 347, 355, 448, ++ 347, 213, 213, 213, 219, 219, 219, 219, 219, 219, ++ 219, 219, 219, 219, 219, 219, 348, 367, 366, 348, ++ 368, 369, 382, 447, 367, 382, 355, 366, 348, 368, ++ 369, 370, 371, 384, 385, 370, 384, 371, 385, 219, ++ 219, 219, 238, 238, 238, 238, 238, 238, 238, 238, ++ 238, 238, 238, 238, 386, 387, 387, 397, 400, 398, ++ 399, 401, 409, 400, 419, 401, 386, 397, 398, 440, ++ 399, 422, 409, 411, 411, 422, 419, 238, 238, 238, ++ ++ 248, 248, 248, 248, 248, 248, 248, 248, 248, 248, ++ 248, 248, 415, 418, 420, 420, 421, 421, 418, 418, ++ 420, 415, 429, 433, 433, 410, 410, 429, 429, 431, ++ 439, 410, 438, 431, 437, 248, 248, 248, 249, 249, ++ 249, 249, 249, 249, 249, 249, 249, 249, 249, 249, ++ 410, 432, 432, 434, 434, 435, 435, 432, 444, 444, ++ 446, 446, 435, 436, 427, 444, 426, 446, 425, 424, ++ 423, 417, 414, 249, 249, 249, 250, 250, 250, 250, ++ 250, 250, 250, 250, 250, 250, 250, 250, 413, 412, ++ 408, 407, 405, 404, 403, 402, 396, 394, 391, 390, ++ ++ 389, 388, 381, 380, 379, 375, 374, 373, 372, 363, ++ 362, 250, 250, 250, 275, 275, 275, 275, 275, 275, ++ 275, 275, 275, 275, 275, 275, 359, 354, 353, 352, ++ 351, 350, 349, 341, 340, 334, 333, 332, 331, 328, ++ 327, 326, 325, 324, 323, 313, 307, 306, 305, 275, ++ 275, 275, 288, 288, 288, 288, 288, 288, 288, 288, ++ 288, 288, 288, 288, 304, 303, 301, 300, 299, 298, ++ 297, 296, 295, 294, 284, 282, 278, 270, 268, 267, ++ 265, 264, 263, 262, 261, 260, 259, 288, 288, 288, ++ 336, 336, 336, 336, 336, 336, 336, 336, 336, 336, ++ ++ 336, 336, 251, 247, 246, 244, 243, 242, 241, 240, ++ 231, 229, 228, 227, 226, 225, 223, 222, 212, 211, ++ 210, 209, 208, 207, 206, 336, 336, 336, 342, 342, ++ 342, 342, 342, 342, 342, 342, 342, 342, 342, 342, ++ 205, 204, 203, 202, 201, 177, 176, 175, 174, 173, ++ 172, 171, 170, 169, 168, 167, 166, 165, 134, 133, ++ 132, 131, 130, 342, 342, 342, 343, 343, 343, 343, ++ 343, 343, 343, 343, 343, 343, 343, 343, 129, 128, ++ 127, 126, 124, 123, 116, 115, 97, 90, 89, 87, ++ 85, 84, 83, 82, 78, 77, 75, 74, 73, 71, ++ ++ 70, 343, 343, 343, 357, 357, 357, 357, 357, 357, ++ 357, 357, 357, 357, 357, 357, 69, 68, 67, 61, ++ 60, 56, 55, 52, 40, 39, 31, 30, 29, 28, ++ 22, 21, 20, 19, 18, 14, 13, 9, 0, 357, ++ 357, 357, 376, 376, 376, 376, 376, 376, 376, 376, ++ 376, 376, 376, 376, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 345, +- 345, 345, 362, 362, 362, 362, 362, 362, 362, 362, +- 362, 362, 362, 362, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 362, 362, 362, +- 411, 411, 411, 411, 411, 411, 411, 411, 411, 411, +- 411, 411, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 376, 376, 376, ++ 430, 430, 430, 430, 430, 430, 430, 430, 430, 430, ++ 430, 430, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 411, 411, 411, 438, 438, +- 438, 438, 438, 438, 438, 438, 438, 439, 439, 439, +- 439, 439, 439, 439, 439, 439, 440, 440, 440, 440, +- 440, 440, 440, 440, 440, 441, 441, 441, 441, 441, +- 441, 441, 441, 441, 442, 442, 442, 442, 442, 442, +- 442, 442, 442, 443, 443, 0, 443, 444, 444, 444, +- 444, 444, 444, 444, 444, 444, 445, 445, 445, 445, +- 445, 445, 445, 445, 445, 446, 446, 446, 446, 446, +- 446, 446, 446, 446, 447, 447, 447, 447, 447, 447, +- +- 447, 0, 447, 448, 0, 0, 0, 0, 0, 0, +- 448, 449, 449, 0, 449, 0, 449, 449, 449, 449, +- 450, 450, 450, 450, 450, 450, 450, 450, 450, 451, +- 451, 0, 451, 0, 451, 451, 451, 451, 452, 452, +- 0, 452, 0, 452, 452, 452, 452, 453, 453, 0, +- 453, 0, 453, 453, 453, 453, 454, 454, 0, 454, +- 0, 454, 454, 454, 454, 455, 455, 455, 455, 455, +- 0, 0, 455, 456, 456, 0, 456, 0, 456, 456, +- 456, 456, 457, 457, 457, 457, 457, 0, 0, 457, +- 458, 458, 458, 458, 458, 0, 0, 458, 459, 459, +- +- 459, 459, 459, 0, 0, 459, 460, 460, 460, 460, +- 460, 0, 0, 460, 461, 461, 0, 461, 0, 461, +- 461, 461, 461, 462, 462, 462, 462, 462, 0, 0, +- 462, 463, 463, 0, 463, 0, 463, 463, 463, 463, +- 464, 464, 0, 464, 0, 464, 464, 464, 464, 465, +- 465, 465, 465, 465, 0, 0, 465, 466, 466, 466, +- 466, 466, 0, 0, 466, 467, 467, 0, 467, 0, +- 467, 467, 467, 467, 468, 468, 0, 468, 0, 468, +- 468, 468, 468, 469, 469, 0, 469, 0, 469, 469, +- 469, 469, 470, 470, 0, 470, 0, 470, 470, 470, +- +- 470, 471, 471, 0, 0, 0, 471, 0, 471, 472, +- 472, 0, 472, 0, 472, 472, 472, 472, 473, 473, +- 473, 0, 473, 473, 0, 473, 474, 474, 0, 474, ++ 0, 0, 0, 0, 0, 430, 430, 430, 458, 458, ++ 458, 458, 458, 458, 458, 458, 458, 459, 459, 459, ++ 459, 459, 459, 459, 459, 459, 460, 460, 460, 460, ++ 460, 460, 460, 460, 460, 461, 461, 461, 461, 461, ++ 461, 461, 461, 461, 462, 462, 462, 462, 462, 462, ++ 462, 462, 462, 463, 463, 0, 463, 464, 464, 464, ++ 464, 464, 464, 464, 464, 464, 465, 465, 465, 465, ++ 465, 465, 465, 465, 465, 466, 466, 466, 466, 466, ++ 466, 466, 466, 466, 467, 467, 467, 467, 467, 467, ++ ++ 467, 0, 467, 468, 0, 0, 0, 0, 0, 0, ++ 468, 469, 469, 0, 469, 0, 469, 469, 469, 469, ++ 470, 470, 470, 470, 470, 470, 470, 470, 470, 471, ++ 471, 0, 471, 0, 471, 471, 471, 471, 472, 472, ++ 0, 472, 0, 472, 472, 472, 472, 473, 473, 0, ++ 473, 0, 473, 473, 473, 473, 474, 474, 0, 474, + 0, 474, 474, 474, 474, 475, 475, 475, 475, 475, +- 0, 0, 475, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, +- 437, 437, 437, 437, 437, 437, 437, 437, 437, 437, ++ 0, 0, 475, 476, 476, 0, 476, 0, 476, 476, ++ 476, 476, 477, 477, 477, 477, 477, 0, 0, 477, ++ 478, 478, 478, 478, 478, 0, 0, 478, 479, 479, ++ ++ 479, 479, 479, 0, 0, 479, 480, 480, 480, 480, ++ 480, 0, 0, 480, 481, 481, 0, 481, 0, 481, ++ 481, 481, 481, 482, 482, 482, 482, 482, 0, 0, ++ 482, 483, 483, 0, 483, 0, 483, 483, 483, 483, ++ 484, 484, 0, 484, 0, 484, 484, 484, 484, 485, ++ 485, 485, 485, 485, 0, 0, 485, 486, 486, 486, ++ 486, 486, 0, 0, 486, 487, 487, 0, 487, 0, ++ 487, 487, 487, 487, 488, 488, 0, 488, 0, 488, ++ 488, 488, 488, 489, 489, 0, 489, 0, 489, 489, ++ 489, 489, 490, 490, 0, 490, 0, 490, 490, 490, ++ ++ 490, 491, 491, 0, 0, 0, 491, 0, 491, 492, ++ 492, 0, 492, 0, 492, 492, 492, 492, 493, 493, ++ 493, 0, 493, 493, 0, 493, 494, 494, 0, 494, ++ 0, 494, 494, 494, 494, 495, 495, 495, 495, 495, ++ 0, 0, 495, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, ++ 457, 457, 457, 457, 457, 457, 457, 457, 457, 457, + +- 437, 437, 437, 437, 437, 437 ++ 457, 457, 457, 457, 457, 457 + } ; + + static yy_state_type yy_last_accepting_state; +@@ -933,7 +950,7 @@ + #define YY_MORE_ADJ 0 + #define YY_RESTORE_YY_MORE_OFFSET + char *yytext; +-#line 1 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 1 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + /* -*- indented-text -*- */ + /* Process source files and output type information. + Copyright (C) 2002, 2003, 2004, 2005, 2007, 2008, 2009 +@@ -955,7 +972,7 @@ + along with GCC; see the file COPYING3. If not see + . */ + #define YY_NO_INPUT 1 +-#line 25 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 25 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + #include "bconfig.h" + #include "system.h" + +@@ -979,7 +996,7 @@ + } + + +-#line 983 "gengtype-lex.c" ++#line 1000 "gengtype-lex.c" + + #define INITIAL 0 + #define in_struct 1 +@@ -1061,7 +1078,12 @@ + + /* Amount of stuff to slurp up with each read. */ + #ifndef YY_READ_BUF_SIZE ++#ifdef __ia64__ ++/* On IA-64, the buffer size is 16k, not 8k */ ++#define YY_READ_BUF_SIZE 16384 ++#else + #define YY_READ_BUF_SIZE 8192 ++#endif /* __ia64__ */ + #endif + + /* Copy whatever the last rule matched to the standard output. */ +@@ -1069,7 +1091,7 @@ + /* This used to be an fputs(), but since the string might contain NUL's, + * we now use fwrite(). + */ +-#define ECHO fwrite( yytext, yyleng, 1, yyout ) ++#define ECHO do { if (fwrite( yytext, yyleng, 1, yyout )) {} } while (0) + #endif + + /* Gets input and stuffs it into "buf". number of characters read, or YY_NULL, +@@ -1080,7 +1102,7 @@ + if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \ + { \ + int c = '*'; \ +- int n; \ ++ size_t n; \ + for ( n = 0; n < max_size && \ + (c = getc( yyin )) != EOF && c != '\n'; ++n ) \ + buf[n] = (char) c; \ +@@ -1165,7 +1187,7 @@ + register char *yy_cp, *yy_bp; + register int yy_act; + +-#line 59 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 59 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + + /* Do this on entry to yylex(): */ + *yylval = 0; +@@ -1176,7 +1198,7 @@ + } + + /* Things we look for in skipping mode: */ +-#line 1180 "gengtype-lex.c" ++#line 1202 "gengtype-lex.c" + + if ( !(yy_init) ) + { +@@ -1230,13 +1252,13 @@ + while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) + { + yy_current_state = (int) yy_def[yy_current_state]; +- if ( yy_current_state >= 438 ) ++ if ( yy_current_state >= 458 ) + yy_c = yy_meta[(unsigned int) yy_c]; + } + yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; + ++yy_cp; + } +- while ( yy_current_state != 437 ); ++ while ( yy_current_state != 457 ); + yy_cp = (yy_last_accepting_cpos); + yy_current_state = (yy_last_accepting_state); + +@@ -1262,7 +1284,7 @@ + (yy_c_buf_p) = yy_cp -= 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 70 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 70 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + BEGIN(in_struct); + return TYPEDEF; +@@ -1274,7 +1296,7 @@ + (yy_c_buf_p) = yy_cp -= 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 74 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 74 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + BEGIN(in_struct); + return STRUCT; +@@ -1286,7 +1308,7 @@ + (yy_c_buf_p) = yy_cp -= 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 78 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 78 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + BEGIN(in_struct); + return UNION; +@@ -1298,7 +1320,7 @@ + (yy_c_buf_p) = yy_cp -= 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 82 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 82 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + BEGIN(in_struct); + return EXTERN; +@@ -1310,7 +1332,7 @@ + (yy_c_buf_p) = yy_cp -= 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 86 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 86 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + BEGIN(in_struct); + return STATIC; +@@ -1322,7 +1344,7 @@ + (yy_c_buf_p) = yy_cp -= 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 91 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 91 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + BEGIN(in_struct); + return DEFVEC_OP; +@@ -1334,7 +1356,7 @@ + (yy_c_buf_p) = yy_cp -= 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 95 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 95 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + BEGIN(in_struct); + return DEFVEC_I; +@@ -1346,7 +1368,7 @@ + (yy_c_buf_p) = yy_cp -= 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 99 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 99 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + BEGIN(in_struct); + return DEFVEC_ALLOC; +@@ -1356,19 +1378,19 @@ + + case 9: + YY_RULE_SETUP +-#line 107 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 107 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { BEGIN(in_struct_comment); } + YY_BREAK + case 10: + /* rule 10 can match eol */ + YY_RULE_SETUP +-#line 109 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 109 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { update_lineno (yytext, yyleng); } + YY_BREAK + case 11: + /* rule 11 can match eol */ + YY_RULE_SETUP +-#line 110 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 110 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { lexer_line.line++; } + YY_BREAK + case 12: +@@ -1377,7 +1399,7 @@ + (yy_c_buf_p) = yy_cp = yy_bp + 5; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 112 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 112 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + /* don't care */ + YY_BREAK + case 13: +@@ -1386,7 +1408,7 @@ + (yy_c_buf_p) = yy_cp = yy_bp + 3; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 113 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 113 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { return GTY_TOKEN; } + YY_BREAK + case 14: +@@ -1395,7 +1417,7 @@ + (yy_c_buf_p) = yy_cp = yy_bp + 3; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 114 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 114 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { return VEC_TOKEN; } + YY_BREAK + case 15: +@@ -1404,7 +1426,7 @@ + (yy_c_buf_p) = yy_cp = yy_bp + 5; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 115 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 115 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { return UNION; } + YY_BREAK + case 16: +@@ -1413,7 +1435,7 @@ + (yy_c_buf_p) = yy_cp = yy_bp + 6; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 116 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 116 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { return STRUCT; } + YY_BREAK + case 17: +@@ -1422,7 +1444,7 @@ + (yy_c_buf_p) = yy_cp = yy_bp + 4; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 117 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 117 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { return ENUM; } + YY_BREAK + case 18: +@@ -1431,7 +1453,7 @@ + (yy_c_buf_p) = yy_cp = yy_bp + 9; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 118 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 118 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { return PTR_ALIAS; } + YY_BREAK + case 19: +@@ -1440,12 +1462,12 @@ + (yy_c_buf_p) = yy_cp = yy_bp + 10; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 119 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 119 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { return NESTED_PTR; } + YY_BREAK + case 20: + YY_RULE_SETUP +-#line 120 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 120 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { return NUM; } + YY_BREAK + case 21: +@@ -1454,7 +1476,7 @@ + (yy_c_buf_p) = yy_cp -= 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 121 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 121 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + *yylval = XDUPVAR (const char, yytext, yyleng, yyleng+1); + return PARAM_IS; +@@ -1465,11 +1487,11 @@ + *yy_cp = (yy_hold_char); /* undo effects of setting up yytext */ + (yy_c_buf_p) = yy_cp -= 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ +-#line 127 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 127 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + case 23: + /* rule 23 can match eol */ + YY_RULE_SETUP +-#line 127 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 127 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + size_t len; + +@@ -1487,7 +1509,7 @@ + (yy_c_buf_p) = yy_cp -= 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 139 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 139 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + *yylval = XDUPVAR (const char, yytext, yyleng, yyleng+1); + return ID; +@@ -1496,7 +1518,7 @@ + case 25: + /* rule 25 can match eol */ + YY_RULE_SETUP +-#line 144 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 144 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + *yylval = XDUPVAR (const char, yytext+1, yyleng-2, yyleng-1); + return STRING; +@@ -1506,7 +1528,7 @@ + case 26: + /* rule 26 can match eol */ + YY_RULE_SETUP +-#line 149 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 149 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + *yylval = XDUPVAR (const char, yytext+1, yyleng-2, yyleng-1); + return ARRAY; +@@ -1515,7 +1537,7 @@ + case 27: + /* rule 27 can match eol */ + YY_RULE_SETUP +-#line 153 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 153 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + *yylval = XDUPVAR (const char, yytext+1, yyleng-2, yyleng); + return CHAR; +@@ -1523,24 +1545,24 @@ + YY_BREAK + case 28: + YY_RULE_SETUP +-#line 158 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 158 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { return ELLIPSIS; } + YY_BREAK + case 29: + YY_RULE_SETUP +-#line 159 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 159 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { return yytext[0]; } + YY_BREAK + /* ignore pp-directives */ + case 30: + /* rule 30 can match eol */ + YY_RULE_SETUP +-#line 162 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 162 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + {lexer_line.line++;} + YY_BREAK + case 31: + YY_RULE_SETUP +-#line 164 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 164 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + error_at_line (&lexer_line, "unexpected character `%s'", yytext); + } +@@ -1548,30 +1570,30 @@ + + case 32: + YY_RULE_SETUP +-#line 169 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 169 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { BEGIN(in_comment); } + YY_BREAK + case 33: + /* rule 33 can match eol */ + YY_RULE_SETUP +-#line 170 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 170 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { lexer_line.line++; } + YY_BREAK + case 34: +-#line 172 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 172 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + case 35: + /* rule 35 can match eol */ +-#line 173 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 173 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + case 36: + /* rule 36 can match eol */ + YY_RULE_SETUP +-#line 173 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 173 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + /* do nothing */ + YY_BREAK + case 37: + /* rule 37 can match eol */ + YY_RULE_SETUP +-#line 174 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 174 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { update_lineno (yytext, yyleng); } + YY_BREAK + case 38: +@@ -1580,21 +1602,21 @@ + (yy_c_buf_p) = yy_cp = yy_bp + 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 175 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 175 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + /* do nothing */ + YY_BREAK + + case 39: + /* rule 39 can match eol */ + YY_RULE_SETUP +-#line 178 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 178 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { lexer_line.line++; } + YY_BREAK + case 40: +-#line 180 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 180 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + case 41: + YY_RULE_SETUP +-#line 180 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 180 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + /* do nothing */ + YY_BREAK + case 42: +@@ -1603,25 +1625,25 @@ + (yy_c_buf_p) = yy_cp = yy_bp + 1; + YY_DO_BEFORE_ACTION; /* set up yytext again */ + YY_RULE_SETUP +-#line 181 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 181 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + /* do nothing */ + YY_BREAK + + case 43: + YY_RULE_SETUP +-#line 183 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 183 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { BEGIN(INITIAL); } + YY_BREAK + case 44: + YY_RULE_SETUP +-#line 184 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 184 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { BEGIN(in_struct); } + YY_BREAK + case 45: +-#line 187 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 187 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + case 46: + YY_RULE_SETUP +-#line 187 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 187 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + { + error_at_line (&lexer_line, + "unterminated comment or string; unexpected EOF"); +@@ -1630,15 +1652,15 @@ + case 47: + /* rule 47 can match eol */ + YY_RULE_SETUP +-#line 192 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 192 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + /* do nothing */ + YY_BREAK + case 48: + YY_RULE_SETUP +-#line 194 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 194 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + YY_FATAL_ERROR( "flex scanner jammed" ); + YY_BREAK +-#line 1642 "gengtype-lex.c" ++#line 1664 "gengtype-lex.c" + case YY_STATE_EOF(INITIAL): + case YY_STATE_EOF(in_struct): + case YY_STATE_EOF(in_struct_comment): +@@ -1935,7 +1957,7 @@ + while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) + { + yy_current_state = (int) yy_def[yy_current_state]; +- if ( yy_current_state >= 438 ) ++ if ( yy_current_state >= 458 ) + yy_c = yy_meta[(unsigned int) yy_c]; + } + yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; +@@ -1963,11 +1985,11 @@ + while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) + { + yy_current_state = (int) yy_def[yy_current_state]; +- if ( yy_current_state >= 438 ) ++ if ( yy_current_state >= 458 ) + yy_c = yy_meta[(unsigned int) yy_c]; + } + yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; +- yy_is_jam = (yy_current_state == 437); ++ yy_is_jam = (yy_current_state == 457); + + return yy_is_jam ? 0 : yy_current_state; + } +@@ -2362,8 +2384,8 @@ + + /** Setup the input buffer state to scan the given bytes. The next call to yylex() will + * scan from a @e copy of @a bytes. +- * @param bytes the byte buffer to scan +- * @param len the number of bytes in the buffer pointed to by @a bytes. ++ * @param yybytes the byte buffer to scan ++ * @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes. + * + * @return the newly allocated buffer state object. + */ +@@ -2602,7 +2624,7 @@ + + #define YYTABLES_NAME "yytables" + +-#line 194 "/space/rguenther/gcc-4.5.2/gcc-4.5.2/gcc/gengtype-lex.l" ++#line 194 "/home/doko/gcc-snap-20110303/gcc-snap-20110303/gcc/gengtype-lex.l" + + + +--- a/src/gcc/gengtype-lex.l ++++ b/src/gcc/gengtype-lex.l +@@ -49,7 +49,7 @@ + ID [[:alpha:]_][[:alnum:]_]* + WS [[:space:]]+ + HWS [ \t\r\v\f]* +-IWORD short|long|(un)?signed|char|int|HOST_WIDE_INT|HOST_WIDEST_INT|bool|size_t|BOOL_BITFIELD|CPPCHAR_SIGNED_T|ino_t|dev_t ++IWORD short|long|(un)?signed|char|int|HOST_WIDE_INT|HOST_WIDEST_INT|bool|size_t|BOOL_BITFIELD|CPPCHAR_SIGNED_T|ino_t|dev_t|HARD_REG_SET + ITYPE {IWORD}({WS}{IWORD})* + EOID [^[:alnum:]_] + +--- a/src/gcc/genoutput.c ++++ b/src/gcc/genoutput.c +@@ -266,6 +266,8 @@ + + printf (" %d,\n", d->strict_low); + ++ printf (" %d,\n", d->constraint == NULL ? 1 : 0); ++ + printf (" %d\n", d->eliminable); + + printf(" },\n"); +--- a/src/gcc/genrecog.c ++++ b/src/gcc/genrecog.c +@@ -1782,20 +1782,11 @@ + int odepth = strlen (oldpos); + int ndepth = strlen (newpos); + int depth; +- int old_has_insn, new_has_insn; + + /* Pop up as many levels as necessary. */ + for (depth = odepth; strncmp (oldpos, newpos, depth) != 0; --depth) + continue; + +- /* Hunt for the last [A-Z] in both strings. */ +- for (old_has_insn = odepth - 1; old_has_insn >= 0; --old_has_insn) +- if (ISUPPER (oldpos[old_has_insn])) +- break; +- for (new_has_insn = ndepth - 1; new_has_insn >= 0; --new_has_insn) +- if (ISUPPER (newpos[new_has_insn])) +- break; +- + /* Go down to desired level. */ + while (depth < ndepth) + { +--- a/src/gcc/gimple-pretty-print.c ++++ b/src/gcc/gimple-pretty-print.c +@@ -376,6 +376,34 @@ + } + } + ++/* Helper for dump_gimple_assign. Print the ternary RHS of the ++ assignment GS. BUFFER, SPC and FLAGS are as in dump_gimple_stmt. */ ++ ++static void ++dump_ternary_rhs (pretty_printer *buffer, gimple gs, int spc, int flags) ++{ ++ const char *p; ++ enum tree_code code = gimple_assign_rhs_code (gs); ++ switch (code) ++ { ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ for (p = tree_code_name [(int) code]; *p; p++) ++ pp_character (buffer, TOUPPER (*p)); ++ pp_string (buffer, " <"); ++ dump_generic_node (buffer, gimple_assign_rhs1 (gs), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, gimple_assign_rhs2 (gs), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, gimple_assign_rhs3 (gs), spc, flags, false); ++ pp_character (buffer, '>'); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++} ++ + + /* Dump the gimple assignment GS. BUFFER, SPC and FLAGS are as in + dump_gimple_stmt. */ +@@ -418,6 +446,8 @@ + dump_unary_rhs (buffer, gs, spc, flags); + else if (gimple_num_ops (gs) == 3) + dump_binary_rhs (buffer, gs, spc, flags); ++ else if (gimple_num_ops (gs) == 4) ++ dump_ternary_rhs (buffer, gs, spc, flags); + else + gcc_unreachable (); + if (!(flags & TDF_RHS_ONLY)) +--- a/src/gcc/gimple.c ++++ b/src/gcc/gimple.c +@@ -289,31 +289,40 @@ + + + /* Extract the operands and code for expression EXPR into *SUBCODE_P, +- *OP1_P and *OP2_P respectively. */ ++ *OP1_P, *OP2_P and *OP3_P respectively. */ + + void +-extract_ops_from_tree (tree expr, enum tree_code *subcode_p, tree *op1_p, +- tree *op2_p) ++extract_ops_from_tree_1 (tree expr, enum tree_code *subcode_p, tree *op1_p, ++ tree *op2_p, tree *op3_p) + { + enum gimple_rhs_class grhs_class; + + *subcode_p = TREE_CODE (expr); + grhs_class = get_gimple_rhs_class (*subcode_p); + +- if (grhs_class == GIMPLE_BINARY_RHS) ++ if (grhs_class == GIMPLE_TERNARY_RHS) + { + *op1_p = TREE_OPERAND (expr, 0); + *op2_p = TREE_OPERAND (expr, 1); ++ *op3_p = TREE_OPERAND (expr, 2); ++ } ++ else if (grhs_class == GIMPLE_BINARY_RHS) ++ { ++ *op1_p = TREE_OPERAND (expr, 0); ++ *op2_p = TREE_OPERAND (expr, 1); ++ *op3_p = NULL_TREE; + } + else if (grhs_class == GIMPLE_UNARY_RHS) + { + *op1_p = TREE_OPERAND (expr, 0); + *op2_p = NULL_TREE; ++ *op3_p = NULL_TREE; + } + else if (grhs_class == GIMPLE_SINGLE_RHS) + { + *op1_p = expr; + *op2_p = NULL_TREE; ++ *op3_p = NULL_TREE; + } + else + gcc_unreachable (); +@@ -329,10 +338,10 @@ + gimple_build_assign_stat (tree lhs, tree rhs MEM_STAT_DECL) + { + enum tree_code subcode; +- tree op1, op2; ++ tree op1, op2, op3; + +- extract_ops_from_tree (rhs, &subcode, &op1, &op2); +- return gimple_build_assign_with_ops_stat (subcode, lhs, op1, op2 ++ extract_ops_from_tree_1 (rhs, &subcode, &op1, &op2, &op3); ++ return gimple_build_assign_with_ops_stat (subcode, lhs, op1, op2, op3 + PASS_MEM_STAT); + } + +@@ -343,7 +352,7 @@ + + gimple + gimple_build_assign_with_ops_stat (enum tree_code subcode, tree lhs, tree op1, +- tree op2 MEM_STAT_DECL) ++ tree op2, tree op3 MEM_STAT_DECL) + { + unsigned num_ops; + gimple p; +@@ -362,6 +371,12 @@ + gimple_assign_set_rhs2 (p, op2); + } + ++ if (op3) ++ { ++ gcc_assert (num_ops > 3); ++ gimple_assign_set_rhs3 (p, op3); ++ } ++ + return p; + } + +@@ -1860,22 +1875,22 @@ + gimple_assign_set_rhs_from_tree (gimple_stmt_iterator *gsi, tree expr) + { + enum tree_code subcode; +- tree op1, op2; ++ tree op1, op2, op3; + +- extract_ops_from_tree (expr, &subcode, &op1, &op2); +- gimple_assign_set_rhs_with_ops (gsi, subcode, op1, op2); ++ extract_ops_from_tree_1 (expr, &subcode, &op1, &op2, &op3); ++ gimple_assign_set_rhs_with_ops_1 (gsi, subcode, op1, op2, op3); + } + + + /* Set the RHS of assignment statement pointed-to by GSI to CODE with +- operands OP1 and OP2. ++ operands OP1, OP2 and OP3. + + NOTE: The statement pointed-to by GSI may be reallocated if it + did not have enough operand slots. */ + + void +-gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *gsi, enum tree_code code, +- tree op1, tree op2) ++gimple_assign_set_rhs_with_ops_1 (gimple_stmt_iterator *gsi, enum tree_code code, ++ tree op1, tree op2, tree op3) + { + unsigned new_rhs_ops = get_gimple_rhs_num_ops (code); + gimple stmt = gsi_stmt (*gsi); +@@ -1899,6 +1914,8 @@ + gimple_assign_set_rhs1 (stmt, op1); + if (new_rhs_ops > 1) + gimple_assign_set_rhs2 (stmt, op2); ++ if (new_rhs_ops > 2) ++ gimple_assign_set_rhs3 (stmt, op3); + } + + +@@ -2378,6 +2395,8 @@ + return 1; + else if (rhs_class == GIMPLE_BINARY_RHS) + return 2; ++ else if (rhs_class == GIMPLE_TERNARY_RHS) ++ return 3; + else + gcc_unreachable (); + } +@@ -2394,6 +2413,8 @@ + || (SYM) == TRUTH_OR_EXPR \ + || (SYM) == TRUTH_XOR_EXPR) ? GIMPLE_BINARY_RHS \ + : (SYM) == TRUTH_NOT_EXPR ? GIMPLE_UNARY_RHS \ ++ : ((SYM) == WIDEN_MULT_PLUS_EXPR \ ++ || (SYM) == WIDEN_MULT_MINUS_EXPR) ? GIMPLE_TERNARY_RHS \ + : ((SYM) == COND_EXPR \ + || (SYM) == CONSTRUCTOR \ + || (SYM) == OBJ_TYPE_REF \ +@@ -2591,7 +2612,13 @@ + + op = strip_invariant_refs (TREE_OPERAND (t, 0)); + +- return op && (CONSTANT_CLASS_P (op) || decl_address_invariant_p (op)); ++ if (!op) ++ return false; ++ ++ if (TREE_CODE (op) == INDIRECT_REF) ++ return CONSTANT_CLASS_P (TREE_OPERAND (op, 0)); ++ else ++ return CONSTANT_CLASS_P (op) || decl_address_invariant_p (op); + } + + /* Return true if T is a gimple invariant address at IPA level +--- a/src/gcc/gimple.h ++++ b/src/gcc/gimple.h +@@ -80,6 +80,7 @@ + enum gimple_rhs_class + { + GIMPLE_INVALID_RHS, /* The expression cannot be used on the RHS. */ ++ GIMPLE_TERNARY_RHS, /* The expression is a ternary operation. */ + GIMPLE_BINARY_RHS, /* The expression is a binary operation. */ + GIMPLE_UNARY_RHS, /* The expression is a unary operation. */ + GIMPLE_SINGLE_RHS /* The expression is a single object (an SSA +@@ -786,12 +787,14 @@ + gimple gimple_build_assign_stat (tree, tree MEM_STAT_DECL); + #define gimple_build_assign(l,r) gimple_build_assign_stat (l, r MEM_STAT_INFO) + +-void extract_ops_from_tree (tree, enum tree_code *, tree *, tree *); ++void extract_ops_from_tree_1 (tree, enum tree_code *, tree *, tree *, tree *); + + gimple gimple_build_assign_with_ops_stat (enum tree_code, tree, tree, +- tree MEM_STAT_DECL); +-#define gimple_build_assign_with_ops(c,o1,o2,o3) \ +- gimple_build_assign_with_ops_stat (c, o1, o2, o3 MEM_STAT_INFO) ++ tree, tree MEM_STAT_DECL); ++#define gimple_build_assign_with_ops(c,o1,o2,o3) \ ++ gimple_build_assign_with_ops_stat (c, o1, o2, o3, NULL_TREE MEM_STAT_INFO) ++#define gimple_build_assign_with_ops3(c,o1,o2,o3,o4) \ ++ gimple_build_assign_with_ops_stat (c, o1, o2, o3, o4 MEM_STAT_INFO) + + gimple gimple_build_debug_bind_stat (tree, tree, gimple MEM_STAT_DECL); + #define gimple_build_debug_bind(var,val,stmt) \ +@@ -850,8 +853,8 @@ + bool gimple_assign_unary_nop_p (gimple); + void gimple_set_bb (gimple, struct basic_block_def *); + void gimple_assign_set_rhs_from_tree (gimple_stmt_iterator *, tree); +-void gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *, enum tree_code, +- tree, tree); ++void gimple_assign_set_rhs_with_ops_1 (gimple_stmt_iterator *, enum tree_code, ++ tree, tree, tree); + tree gimple_get_lhs (const_gimple); + void gimple_set_lhs (gimple, tree); + void gimple_replace_lhs (gimple, tree); +@@ -1793,6 +1796,63 @@ + gimple_set_op (gs, 2, rhs); + } + ++/* Return the third operand on the RHS of assignment statement GS. ++ If GS does not have two operands, NULL is returned instead. */ ++ ++static inline tree ++gimple_assign_rhs3 (const_gimple gs) ++{ ++ GIMPLE_CHECK (gs, GIMPLE_ASSIGN); ++ ++ if (gimple_num_ops (gs) >= 4) ++ return gimple_op (gs, 3); ++ else ++ return NULL_TREE; ++} ++ ++/* Return a pointer to the third operand on the RHS of assignment ++ statement GS. */ ++ ++static inline tree * ++gimple_assign_rhs3_ptr (const_gimple gs) ++{ ++ GIMPLE_CHECK (gs, GIMPLE_ASSIGN); ++ return gimple_op_ptr (gs, 3); ++} ++ ++ ++/* Set RHS to be the third operand on the RHS of assignment statement GS. */ ++ ++static inline void ++gimple_assign_set_rhs3 (gimple gs, tree rhs) ++{ ++ GIMPLE_CHECK (gs, GIMPLE_ASSIGN); ++ ++ gimple_set_op (gs, 3, rhs); ++} ++ ++/* A wrapper around gimple_assign_set_rhs_with_ops_1, for callers which expect ++ to see only a maximum of two operands. */ ++ ++static inline void ++gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *gsi, enum tree_code code, ++ tree op1, tree op2) ++{ ++ gimple_assign_set_rhs_with_ops_1 (gsi, code, op1, op2, NULL); ++} ++ ++/* A wrapper around extract_ops_from_tree_1, for callers which expect ++ to see only a maximum of two operands. */ ++ ++static inline void ++extract_ops_from_tree (tree expr, enum tree_code *code, tree *op0, ++ tree *op1) ++{ ++ tree op2; ++ extract_ops_from_tree_1 (expr, code, op0, op1, &op2); ++ gcc_assert (op2 == NULL_TREE); ++} ++ + /* Returns true if GS is a nontemporal move. */ + + static inline bool +@@ -4764,4 +4824,9 @@ + + extern void dump_gimple_statistics (void); + ++extern tree maybe_fold_and_comparisons (enum tree_code, tree, tree, ++ enum tree_code, tree, tree); ++extern tree maybe_fold_or_comparisons (enum tree_code, tree, tree, ++ enum tree_code, tree, tree); ++ + #endif /* GCC_GIMPLE_H */ +--- a/src/gcc/graphite-sese-to-poly.c ++++ b/src/gcc/graphite-sese-to-poly.c +@@ -715,7 +715,7 @@ + gcc_assert (TREE_CODE (e) == INTEGER_CST); + + value_init (val); +- value_set_si (val, int_cst_value (e)); ++ tree_int_to_gmp (e, val); + add_value_to_dim (l, expr, val); + value_clear (val); + } +@@ -729,16 +729,13 @@ + { + Value val; + ppl_Coefficient_t coef; +- int v = int_cst_value (cst); ++ tree type = TREE_TYPE (cst); + + value_init (val); +- value_set_si (val, 0); + + /* Necessary to not get "-1 = 2^n - 1". */ +- if (v < 0) +- value_sub_int (val, val, -v); +- else +- value_add_int (val, val, v); ++ mpz_set_double_int (val, double_int_sext (tree_to_double_int (cst), ++ TYPE_PRECISION (type)), false); + + value_multiply (val, val, k); + ppl_new_Coefficient (&coef); +@@ -816,7 +813,7 @@ + Value val; + gcc_assert (host_integerp (TREE_OPERAND (e, 1), 0)); + value_init (val); +- value_set_si (val, int_cst_value (TREE_OPERAND (e, 1))); ++ tree_int_to_gmp (TREE_OPERAND (e, 1), val); + value_multiply (val, val, k); + scan_tree_for_params (s, TREE_OPERAND (e, 0), c, val); + value_clear (val); +@@ -831,7 +828,7 @@ + Value val; + gcc_assert (host_integerp (TREE_OPERAND (e, 0), 0)); + value_init (val); +- value_set_si (val, int_cst_value (TREE_OPERAND (e, 0))); ++ tree_int_to_gmp (TREE_OPERAND (e, 0), val); + value_multiply (val, val, k); + scan_tree_for_params (s, TREE_OPERAND (e, 1), c, val); + value_clear (val); +@@ -1717,10 +1714,13 @@ + /* subscript - low >= 0 */ + if (host_integerp (low, 0)) + { ++ tree minus_low; ++ + ppl_new_Linear_Expression_with_dimension (&expr, accessp_nb_dims); + ppl_set_coef (expr, subscript, 1); + +- ppl_set_inhomogeneous (expr, -int_cst_value (low)); ++ minus_low = fold_build1 (NEGATE_EXPR, TREE_TYPE (low), low); ++ ppl_set_inhomogeneous_tree (expr, minus_low); + + ppl_new_Constraint (&cstr, expr, PPL_CONSTRAINT_TYPE_GREATER_OR_EQUAL); + ppl_Polyhedron_add_constraint (accesses, cstr); +@@ -1740,7 +1740,7 @@ + ppl_new_Linear_Expression_with_dimension (&expr, accessp_nb_dims); + ppl_set_coef (expr, subscript, -1); + +- ppl_set_inhomogeneous (expr, int_cst_value (high)); ++ ppl_set_inhomogeneous_tree (expr, high); + + ppl_new_Constraint (&cstr, expr, PPL_CONSTRAINT_TYPE_GREATER_OR_EQUAL); + ppl_Polyhedron_add_constraint (accesses, cstr); +--- a/src/gcc/graphite.c ++++ b/src/gcc/graphite.c +@@ -210,6 +210,7 @@ + return false; + } + ++ scev_reset (); + recompute_all_dominators (); + initialize_original_copy_tables (); + cloog_initialize (); +--- a/src/gcc/gthr-posix.h ++++ b/src/gcc/gthr-posix.h +@@ -1,7 +1,7 @@ + /* Threads compatibility routines for libgcc2 and libobjc. */ + /* Compile this one with gcc. */ + /* Copyright (C) 1997, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, +- 2008, 2009 Free Software Foundation, Inc. ++ 2008, 2009, 2011 Free Software Foundation, Inc. + + This file is part of GCC. + +@@ -250,61 +250,34 @@ + calls in shared flavors of the HP-UX C library. Most of the stubs + have no functionality. The details are described in the "libc cumulative + patch" for each subversion of HP-UX 11. There are two special interfaces +- provided for checking whether an application is linked to a pthread ++ provided for checking whether an application is linked to a shared pthread + library or not. However, these interfaces aren't available in early +- libc versions. We also can't use pthread_once as some libc versions +- call the init function. So, we use pthread_create to check whether it +- is possible to create a thread or not. The stub implementation returns +- the error number ENOSYS. */ ++ libpthread libraries. We also need a test that works for archive ++ libraries. We can't use pthread_once as some libc versions call the ++ init function. We also can't use pthread_create or pthread_attr_init ++ as these create a thread and thereby prevent changing the default stack ++ size. The function pthread_default_stacksize_np is available in both ++ the archive and shared versions of libpthread. It can be used to ++ determine the default pthread stack size. There is a stub in some ++ shared libc versions which returns a zero size if pthreads are not ++ active. We provide an equivalent stub to handle cases where libc ++ doesn't provide one. */ + + #if defined(__hppa__) && defined(__hpux__) + +-#include +- + static volatile int __gthread_active = -1; + +-static void * +-__gthread_start (void *__arg __attribute__((unused))) +-{ +- return NULL; +-} +- +-static void __gthread_active_init (void) __attribute__((noinline)); +-static void +-__gthread_active_init (void) +-{ +- static pthread_mutex_t __gthread_active_mutex = PTHREAD_MUTEX_INITIALIZER; +- pthread_t __t; +- pthread_attr_t __a; +- int __result; +- +- __gthrw_(pthread_mutex_lock) (&__gthread_active_mutex); +- if (__gthread_active < 0) +- { +- __gthrw_(pthread_attr_init) (&__a); +- __gthrw_(pthread_attr_setdetachstate) (&__a, PTHREAD_CREATE_DETACHED); +- __result = __gthrw_(pthread_create) (&__t, &__a, __gthread_start, NULL); +- if (__result != ENOSYS) +- __gthread_active = 1; +- else +- __gthread_active = 0; +- __gthrw_(pthread_attr_destroy) (&__a); +- } +- __gthrw_(pthread_mutex_unlock) (&__gthread_active_mutex); +-} +- + static inline int + __gthread_active_p (void) + { + /* Avoid reading __gthread_active twice on the main code path. */ + int __gthread_active_latest_value = __gthread_active; ++ size_t __s; + +- /* This test is not protected to avoid taking a lock on the main code +- path so every update of __gthread_active in a threaded program must +- be atomic with regard to the result of the test. */ + if (__builtin_expect (__gthread_active_latest_value < 0, 0)) + { +- __gthread_active_init (); ++ pthread_default_stacksize_np (0, &__s); ++ __gthread_active = __s ? 1 : 0; + __gthread_active_latest_value = __gthread_active; + } + +--- a/src/gcc/gthr-posix95.h ++++ b/src/gcc/gthr-posix95.h +@@ -1,6 +1,7 @@ + /* Threads compatibility routines for libgcc2 and libobjc. */ + /* Compile this one with gcc. */ +-/* Copyright (C) 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc. ++/* Copyright (C) 2004, 2005, 2007, 2008, 2009, 2011 ++ Free Software Foundation, Inc. + + This file is part of GCC. + +@@ -184,61 +185,34 @@ + calls in shared flavors of the HP-UX C library. Most of the stubs + have no functionality. The details are described in the "libc cumulative + patch" for each subversion of HP-UX 11. There are two special interfaces +- provided for checking whether an application is linked to a pthread ++ provided for checking whether an application is linked to a shared pthread + library or not. However, these interfaces aren't available in early +- libc versions. We also can't use pthread_once as some libc versions +- call the init function. So, we use pthread_create to check whether it +- is possible to create a thread or not. The stub implementation returns +- the error number ENOSYS. */ ++ pthread libraries. We also need a test that works for archive ++ libraries. We can't use pthread_once as some libc versions call the ++ init function. We also can't use pthread_create or pthread_attr_init ++ as these create a thread and thereby prevent changing the default stack ++ size. The function pthread_default_stacksize_np is available in both ++ the archive and shared versions of libpthread. It can be used to ++ determine the default pthread stack size. There is a stub in some ++ shared libc versions which returns a zero size if pthreads are not ++ active. We provide an equivalent stub to handle cases where libc ++ doesn't provide one. */ + + #if defined(__hppa__) && defined(__hpux__) + +-#include +- + static volatile int __gthread_active = -1; + +-static void * +-__gthread_start (void *arg __attribute__((unused))) +-{ +- return NULL; +-} +- +-static void __gthread_active_init (void) __attribute__((noinline)); +-static void +-__gthread_active_init (void) +-{ +- static pthread_mutex_t __gthread_active_mutex = PTHREAD_MUTEX_INITIALIZER; +- pthread_t t; +- pthread_attr_t a; +- int result; +- +- __gthrw_(pthread_mutex_lock) (&__gthread_active_mutex); +- if (__gthread_active < 0) +- { +- __gthrw_(pthread_attr_init) (&a); +- __gthrw_(pthread_attr_setdetachstate) (&a, PTHREAD_CREATE_DETACHED); +- result = __gthrw_(pthread_create) (&t, &a, __gthread_start, NULL); +- if (result != ENOSYS) +- __gthread_active = 1; +- else +- __gthread_active = 0; +- __gthrw_(pthread_attr_destroy) (&a); +- } +- __gthrw_(pthread_mutex_unlock) (&__gthread_active_mutex); +-} +- + static inline int + __gthread_active_p (void) + { + /* Avoid reading __gthread_active twice on the main code path. */ + int __gthread_active_latest_value = __gthread_active; ++ size_t __s; + +- /* This test is not protected to avoid taking a lock on the main code +- path so every update of __gthread_active in a threaded program must +- be atomic with regard to the result of the test. */ + if (__builtin_expect (__gthread_active_latest_value < 0, 0)) + { +- __gthread_active_init (); ++ pthread_default_stacksize_np (0, &__s); ++ __gthread_active = __s ? 1 : 0; + __gthread_active_latest_value = __gthread_active; + } + +--- a/src/gcc/haifa-sched.c ++++ b/src/gcc/haifa-sched.c +@@ -4231,7 +4231,7 @@ + /* Helper function. + Find fallthru edge from PRED. */ + edge +-find_fallthru_edge (basic_block pred) ++find_fallthru_edge_from (basic_block pred) + { + edge e; + edge_iterator ei; +@@ -4298,7 +4298,7 @@ + edge e; + + last = EXIT_BLOCK_PTR->prev_bb; +- e = find_fallthru_edge (last); ++ e = find_fallthru_edge_from (last); + + if (e) + { +@@ -5234,6 +5234,11 @@ + gcc_assert (/* Usual case. */ + (EDGE_COUNT (bb->succs) > 1 + && !BARRIER_P (NEXT_INSN (head))) ++ /* Special cases, see cfglayout.c: ++ fixup_reorder_chain. */ ++ || (EDGE_COUNT (bb->succs) == 1 ++ && (!onlyjump_p (head) ++ || returnjump_p (head))) + /* Or jump to the next instruction. */ + || (EDGE_COUNT (bb->succs) == 1 + && (BB_HEAD (EDGE_I (bb->succs, 0)->dest) +--- a/src/gcc/ifcvt.c ++++ b/src/gcc/ifcvt.c +@@ -88,6 +88,8 @@ + static bool cheap_bb_rtx_cost_p (const_basic_block, int); + static rtx first_active_insn (basic_block); + static rtx last_active_insn (basic_block, int); ++static rtx find_active_insn_before (basic_block, rtx); ++static rtx find_active_insn_after (basic_block, rtx); + static basic_block block_fallthru (basic_block); + static int cond_exec_process_insns (ce_if_block_t *, rtx, rtx, rtx, rtx, int); + static rtx cond_exec_get_condition (rtx); +@@ -103,7 +105,7 @@ + static int find_if_case_2 (basic_block, edge, edge); + static int find_memory (rtx *, void *); + static int dead_or_predicable (basic_block, basic_block, basic_block, +- basic_block, int); ++ edge, int); + static void noce_emit_move_insn (rtx, rtx); + static rtx block_has_only_trap (basic_block); + +@@ -230,6 +232,48 @@ + return insn; + } + ++/* Return the active insn before INSN inside basic block CURR_BB. */ ++ ++static rtx ++find_active_insn_before (basic_block curr_bb, rtx insn) ++{ ++ if (!insn || insn == BB_HEAD (curr_bb)) ++ return NULL_RTX; ++ ++ while ((insn = PREV_INSN (insn)) != NULL_RTX) ++ { ++ if (NONJUMP_INSN_P (insn) || JUMP_P (insn) || CALL_P (insn)) ++ break; ++ ++ /* No other active insn all the way to the start of the basic block. */ ++ if (insn == BB_HEAD (curr_bb)) ++ return NULL_RTX; ++ } ++ ++ return insn; ++} ++ ++/* Return the active insn after INSN inside basic block CURR_BB. */ ++ ++static rtx ++find_active_insn_after (basic_block curr_bb, rtx insn) ++{ ++ if (!insn || insn == BB_END (curr_bb)) ++ return NULL_RTX; ++ ++ while ((insn = NEXT_INSN (insn)) != NULL_RTX) ++ { ++ if (NONJUMP_INSN_P (insn) || JUMP_P (insn) || CALL_P (insn)) ++ break; ++ ++ /* No other active insn all the way to the end of the basic block. */ ++ if (insn == BB_END (curr_bb)) ++ return NULL_RTX; ++ } ++ ++ return insn; ++} ++ + /* Return the basic block reached by falling though the basic block BB. */ + + static basic_block +@@ -385,7 +429,11 @@ + rtx false_expr; /* test for then block insns */ + rtx true_prob_val; /* probability of else block */ + rtx false_prob_val; /* probability of then block */ +- int n_insns; ++ rtx then_last_head = NULL_RTX; /* Last match at the head of THEN */ ++ rtx else_last_head = NULL_RTX; /* Last match at the head of ELSE */ ++ rtx then_first_tail = NULL_RTX; /* First match at the tail of THEN */ ++ rtx else_first_tail = NULL_RTX; /* First match at the tail of ELSE */ ++ int then_n_insns, else_n_insns, n_insns; + enum rtx_code false_code; + + /* If test is comprised of && or || elements, and we've failed at handling +@@ -418,15 +466,78 @@ + number of insns and see if it is small enough to convert. */ + then_start = first_active_insn (then_bb); + then_end = last_active_insn (then_bb, TRUE); +- n_insns = ce_info->num_then_insns = count_bb_insns (then_bb); ++ then_n_insns = ce_info->num_then_insns = count_bb_insns (then_bb); ++ n_insns = then_n_insns; + max = MAX_CONDITIONAL_EXECUTE; + + if (else_bb) + { ++ int n_matching; ++ + max *= 2; + else_start = first_active_insn (else_bb); + else_end = last_active_insn (else_bb, TRUE); +- n_insns += ce_info->num_else_insns = count_bb_insns (else_bb); ++ else_n_insns = ce_info->num_else_insns = count_bb_insns (else_bb); ++ n_insns += else_n_insns; ++ ++ /* Look for matching sequences at the head and tail of the two blocks, ++ and limit the range of insns to be converted if possible. */ ++ n_matching = flow_find_cross_jump (then_bb, else_bb, ++ &then_first_tail, &else_first_tail); ++ if (then_first_tail == BB_HEAD (then_bb)) ++ then_start = then_end = NULL_RTX; ++ if (else_first_tail == BB_HEAD (else_bb)) ++ else_start = else_end = NULL_RTX; ++ ++ if (n_matching > 0) ++ { ++ if (then_end) ++ then_end = find_active_insn_before (then_bb, then_first_tail); ++ if (else_end) ++ else_end = find_active_insn_before (else_bb, else_first_tail); ++ n_insns -= 2 * n_matching; ++ } ++ ++ if (then_start && else_start) ++ { ++ int longest_match = MIN (then_n_insns - n_matching, ++ else_n_insns - n_matching); ++ n_matching ++ = flow_find_head_matching_sequence (then_bb, else_bb, ++ &then_last_head, ++ &else_last_head, ++ longest_match); ++ ++ if (n_matching > 0) ++ { ++ rtx insn; ++ ++ /* We won't pass the insns in the head sequence to ++ cond_exec_process_insns, so we need to test them here ++ to make sure that they don't clobber the condition. */ ++ for (insn = BB_HEAD (then_bb); ++ insn != NEXT_INSN (then_last_head); ++ insn = NEXT_INSN (insn)) ++ if (!LABEL_P (insn) && !NOTE_P (insn) ++ && !DEBUG_INSN_P (insn) ++ && modified_in_p (test_expr, insn)) ++ return FALSE; ++ } ++ ++ if (then_last_head == then_end) ++ then_start = then_end = NULL_RTX; ++ if (else_last_head == else_end) ++ else_start = else_end = NULL_RTX; ++ ++ if (n_matching > 0) ++ { ++ if (then_start) ++ then_start = find_active_insn_after (then_bb, then_last_head); ++ if (else_start) ++ else_start = find_active_insn_after (else_bb, else_last_head); ++ n_insns -= 2 * n_matching; ++ } ++ } + } + + if (n_insns > max) +@@ -570,7 +681,21 @@ + fprintf (dump_file, "%d insn%s converted to conditional execution.\n", + n_insns, (n_insns == 1) ? " was" : "s were"); + +- /* Merge the blocks! */ ++ /* Merge the blocks! If we had matching sequences, make sure to delete one ++ copy at the appropriate location first: delete the copy in the THEN branch ++ for a tail sequence so that the remaining one is executed last for both ++ branches, and delete the copy in the ELSE branch for a head sequence so ++ that the remaining one is executed first for both branches. */ ++ if (then_first_tail) ++ { ++ rtx from = then_first_tail; ++ if (!INSN_P (from)) ++ from = find_active_insn_after (then_bb, from); ++ delete_insn_chain (from, BB_END (then_bb), false); ++ } ++ if (else_last_head) ++ delete_insn_chain (first_active_insn (else_bb), else_last_head, false); ++ + merge_if_block (ce_info); + cond_exec_changed_p = TRUE; + return TRUE; +@@ -1213,6 +1338,9 @@ + noce_emit_cmove (struct noce_if_info *if_info, rtx x, enum rtx_code code, + rtx cmp_a, rtx cmp_b, rtx vfalse, rtx vtrue) + { ++ rtx target; ++ int unsignedp; ++ + /* If earliest == jump, try to build the cmove insn directly. + This is helpful when combine has created some complex condition + (like for alpha's cmovlbs) that we can't hope to regenerate +@@ -1247,10 +1375,62 @@ + return NULL_RTX; + + #if HAVE_conditional_move +- return emit_conditional_move (x, code, cmp_a, cmp_b, VOIDmode, +- vtrue, vfalse, GET_MODE (x), +- (code == LTU || code == GEU +- || code == LEU || code == GTU)); ++ unsignedp = (code == LTU || code == GEU ++ || code == LEU || code == GTU); ++ ++ target = emit_conditional_move (x, code, cmp_a, cmp_b, VOIDmode, ++ vtrue, vfalse, GET_MODE (x), ++ unsignedp); ++ if (target) ++ return target; ++ ++ /* We might be faced with a situation like: ++ ++ x = (reg:M TARGET) ++ vtrue = (subreg:M (reg:N VTRUE) BYTE) ++ vfalse = (subreg:M (reg:N VFALSE) BYTE) ++ ++ We can't do a conditional move in mode M, but it's possible that we ++ could do a conditional move in mode N instead and take a subreg of ++ the result. ++ ++ If we can't create new pseudos, though, don't bother. */ ++ if (reload_completed) ++ return NULL_RTX; ++ ++ if (GET_CODE (vtrue) == SUBREG && GET_CODE (vfalse) == SUBREG) ++ { ++ rtx reg_vtrue = SUBREG_REG (vtrue); ++ rtx reg_vfalse = SUBREG_REG (vfalse); ++ unsigned int byte_vtrue = SUBREG_BYTE (vtrue); ++ unsigned int byte_vfalse = SUBREG_BYTE (vfalse); ++ rtx promoted_target; ++ ++ if (GET_MODE (reg_vtrue) != GET_MODE (reg_vfalse) ++ || byte_vtrue != byte_vfalse ++ || (SUBREG_PROMOTED_VAR_P (vtrue) ++ != SUBREG_PROMOTED_VAR_P (vfalse)) ++ || (SUBREG_PROMOTED_UNSIGNED_P (vtrue) ++ != SUBREG_PROMOTED_UNSIGNED_P (vfalse))) ++ return NULL_RTX; ++ ++ promoted_target = gen_reg_rtx (GET_MODE (reg_vtrue)); ++ ++ target = emit_conditional_move (promoted_target, code, cmp_a, cmp_b, ++ VOIDmode, reg_vtrue, reg_vfalse, ++ GET_MODE (reg_vtrue), unsignedp); ++ /* Nope, couldn't do it in that mode either. */ ++ if (!target) ++ return NULL_RTX; ++ ++ target = gen_rtx_SUBREG (GET_MODE (vtrue), promoted_target, byte_vtrue); ++ SUBREG_PROMOTED_VAR_P (target) = SUBREG_PROMOTED_VAR_P (vtrue); ++ SUBREG_PROMOTED_UNSIGNED_SET (target, SUBREG_PROMOTED_UNSIGNED_P (vtrue)); ++ emit_move_insn (x, target); ++ return x; ++ } ++ else ++ return NULL_RTX; + #else + /* We'll never get here, as noce_process_if_block doesn't call the + functions involved. Ifdef code, however, should be discouraged +@@ -3611,6 +3791,7 @@ + basic_block then_bb = then_edge->dest; + basic_block else_bb = else_edge->dest; + basic_block new_bb; ++ rtx else_target = NULL_RTX; + int then_bb_index; + + /* If we are partitioning hot/cold basic blocks, we don't want to +@@ -3660,9 +3841,16 @@ + predictable_edge_p (then_edge))))) + return FALSE; + ++ if (else_bb == EXIT_BLOCK_PTR) ++ { ++ rtx jump = BB_END (else_edge->src); ++ gcc_assert (JUMP_P (jump)); ++ else_target = JUMP_LABEL (jump); ++ } ++ + /* Registers set are dead, or are predicable. */ + if (! dead_or_predicable (test_bb, then_bb, else_bb, +- single_succ (then_bb), 1)) ++ single_succ_edge (then_bb), 1)) + return FALSE; + + /* Conversion went ok, including moving the insns and fixing up the +@@ -3679,6 +3867,9 @@ + redirect_edge_succ (FALLTHRU_EDGE (test_bb), else_bb); + new_bb = 0; + } ++ else if (else_bb == EXIT_BLOCK_PTR) ++ new_bb = force_nonfallthru_and_redirect (FALLTHRU_EDGE (test_bb), ++ else_bb, else_target); + else + new_bb = redirect_edge_and_branch_force (FALLTHRU_EDGE (test_bb), + else_bb); +@@ -3777,7 +3968,7 @@ + return FALSE; + + /* Registers set are dead, or are predicable. */ +- if (! dead_or_predicable (test_bb, else_bb, then_bb, else_succ->dest, 0)) ++ if (! dead_or_predicable (test_bb, else_bb, then_bb, else_succ, 0)) + return FALSE; + + /* Conversion went ok, including moving the insns and fixing up the +@@ -3815,12 +4006,35 @@ + + static int + dead_or_predicable (basic_block test_bb, basic_block merge_bb, +- basic_block other_bb, basic_block new_dest, int reversep) ++ basic_block other_bb, edge dest_edge, int reversep) + { +- rtx head, end, jump, earliest = NULL_RTX, old_dest, new_label = NULL_RTX; ++ basic_block new_dest = dest_edge->dest; ++ rtx head, end, jump, earliest = NULL_RTX, old_dest; + bitmap merge_set = NULL; ++ bitmap merge_set_noclobber = NULL; + /* Number of pending changes. */ + int n_validated_changes = 0; ++ rtx new_dest_label; ++ ++ jump = BB_END (dest_edge->src); ++ if (JUMP_P (jump)) ++ { ++ new_dest_label = JUMP_LABEL (jump); ++ if (new_dest_label == NULL_RTX) ++ { ++ new_dest_label = PATTERN (jump); ++ gcc_assert (ANY_RETURN_P (new_dest_label)); ++ } ++ } ++ else if (other_bb != new_dest) ++ { ++ if (new_dest == EXIT_BLOCK_PTR) ++ new_dest_label = ret_rtx; ++ else ++ new_dest_label = block_label (new_dest); ++ } ++ else ++ new_dest_label = NULL_RTX; + + jump = BB_END (test_bb); + +@@ -3956,6 +4170,7 @@ + end of the block. */ + + merge_set = BITMAP_ALLOC (®_obstack); ++ merge_set_noclobber = BITMAP_ALLOC (®_obstack); + + /* If we allocated new pseudos (e.g. in the conditional move + expander called from noce_emit_cmove), we must resize the +@@ -3974,6 +4189,7 @@ + df_ref def = *def_rec; + bitmap_set_bit (merge_set, DF_REF_REGNO (def)); + } ++ df_simulate_find_noclobber_defs (insn, merge_set_noclobber); + } + } + +@@ -3984,7 +4200,7 @@ + unsigned i; + bitmap_iterator bi; + +- EXECUTE_IF_SET_IN_BITMAP (merge_set, 0, i, bi) ++ EXECUTE_IF_SET_IN_BITMAP (merge_set_noclobber, 0, i, bi) + { + if (i < FIRST_PSEUDO_REGISTER + && ! fixed_regs[i] +@@ -4020,7 +4236,7 @@ + TEST_SET & DF_LIVE_IN (merge_bb) + are empty. */ + +- if (bitmap_intersect_p (merge_set, test_set) ++ if (bitmap_intersect_p (merge_set_noclobber, test_set) + || bitmap_intersect_p (merge_set, test_live) + || bitmap_intersect_p (test_set, df_get_live_in (merge_bb))) + intersect = true; +@@ -4040,10 +4256,9 @@ + old_dest = JUMP_LABEL (jump); + if (other_bb != new_dest) + { +- new_label = block_label (new_dest); + if (reversep +- ? ! invert_jump_1 (jump, new_label) +- : ! redirect_jump_1 (jump, new_label)) ++ ? ! invert_jump_1 (jump, new_dest_label) ++ : ! redirect_jump_1 (jump, new_dest_label)) + goto cancel; + } + +@@ -4054,7 +4269,7 @@ + + if (other_bb != new_dest) + { +- redirect_jump_2 (jump, old_dest, new_label, 0, reversep); ++ redirect_jump_2 (jump, old_dest, new_dest_label, 0, reversep); + + redirect_edge_succ (BRANCH_EDGE (test_bb), new_dest); + if (reversep) +@@ -4108,6 +4323,7 @@ + remove_reg_equal_equiv_notes_for_regno (i); + + BITMAP_FREE (merge_set); ++ BITMAP_FREE (merge_set_noclobber); + } + + reorder_insns (head, end, PREV_INSN (earliest)); +@@ -4128,7 +4344,10 @@ + cancel_changes (0); + fail: + if (merge_set) +- BITMAP_FREE (merge_set); ++ { ++ BITMAP_FREE (merge_set); ++ BITMAP_FREE (merge_set_noclobber); ++ } + return FALSE; + } + +--- a/src/gcc/incpath.c ++++ b/src/gcc/incpath.c +@@ -30,6 +30,8 @@ + #include "intl.h" + #include "incpath.h" + #include "cppdefault.h" ++#include "flags.h" ++#include "toplev.h" + + /* Microsoft Windows does not natively support inodes. + VMS has non-numeric inodes. */ +@@ -353,6 +355,24 @@ + } + fprintf (stderr, _("End of search list.\n")); + } ++ ++#ifdef ENABLE_POISON_SYSTEM_DIRECTORIES ++ if (flag_poison_system_directories) ++ { ++ struct cpp_dir *p; ++ ++ for (p = heads[QUOTE]; p; p = p->next) ++ { ++ if ((!strncmp (p->name, "/usr/include", 12)) ++ || (!strncmp (p->name, "/usr/local/include", 18)) ++ || (!strncmp (p->name, "/usr/X11R6/include", 18))) ++ warning (OPT_Wpoison_system_directories, ++ "include location \"%s\" is unsafe for " ++ "cross-compilation", ++ p->name); ++ } ++ } ++#endif + } + + /* Use given -I paths for #include "..." but not #include <...>, and +--- a/src/gcc/ipa-inline.c ++++ b/src/gcc/ipa-inline.c +@@ -1967,7 +1967,7 @@ + + /* Estimate the stack size for the function. But not at -O0 + because estimated_stack_frame_size is a quadratic problem. */ +- self_stack_size = optimize ? estimated_stack_frame_size () : 0; ++ self_stack_size = optimize ? estimated_stack_frame_size (node->decl) : 0; + inline_summary (node)->estimated_self_stack_size = self_stack_size; + node->global.estimated_stack_size = self_stack_size; + node->global.stack_frame_offset = 0; +--- a/src/gcc/ira-color.c ++++ b/src/gcc/ira-color.c +@@ -447,14 +447,18 @@ + { + HARD_REG_SET conflicting_regs; + int i, j, k, hard_regno, best_hard_regno, class_size; +- int cost, mem_cost, min_cost, full_cost, min_full_cost, add_cost; ++ int cost, mem_cost, min_cost, full_cost, min_full_cost; + int *a_costs; + int *conflict_costs; +- enum reg_class cover_class, rclass, conflict_cover_class; ++ enum reg_class cover_class, conflict_cover_class; + enum machine_mode mode; + ira_allocno_t a, conflict_allocno; + ira_allocno_conflict_iterator aci; + static int costs[FIRST_PSEUDO_REGISTER], full_costs[FIRST_PSEUDO_REGISTER]; ++#ifndef HONOR_REG_ALLOC_ORDER ++ enum reg_class rclass; ++ int add_cost; ++#endif + #ifdef STACK_REGS + bool no_stack_reg_p; + #endif +@@ -592,6 +596,7 @@ + continue; + cost = costs[i]; + full_cost = full_costs[i]; ++#ifndef HONOR_REG_ALLOC_ORDER + if (! allocated_hardreg_p[hard_regno] + && ira_hard_reg_not_in_set_p (hard_regno, mode, call_used_reg_set)) + /* We need to save/restore the hard register in +@@ -604,6 +609,7 @@ + cost += add_cost; + full_cost += add_cost; + } ++#endif + if (min_cost > cost) + min_cost = cost; + if (min_full_cost > full_cost) +--- a/src/gcc/ira-costs.c ++++ b/src/gcc/ira-costs.c +@@ -33,6 +33,7 @@ + #include "addresses.h" + #include "insn-config.h" + #include "recog.h" ++#include "reload.h" + #include "toplev.h" + #include "target.h" + #include "params.h" +@@ -123,6 +124,10 @@ + /* Record cover register class of each allocno with the same regno. */ + static enum reg_class *regno_cover_class; + ++/* Record cost gains for not allocating a register with an invariant ++ equivalence. */ ++static int *regno_equiv_gains; ++ + /* Execution frequency of the current insn. */ + static int frequency; + +@@ -224,6 +229,14 @@ + int alt_fail = 0; + int alt_cost = 0, op_cost_add; + ++ if (!recog_data.alternative_enabled_p[alt]) ++ { ++ for (i = 0; i < recog_data.n_operands; i++) ++ constraints[i] = skip_alternative (constraints[i]); ++ ++ continue; ++ } ++ + for (i = 0; i < n_ops; i++) + { + unsigned char c; +@@ -1255,6 +1268,7 @@ + #ifdef FORBIDDEN_INC_DEC_CLASSES + int inc_dec_p = false; + #endif ++ int equiv_savings = regno_equiv_gains[i]; + + if (! allocno_p) + { +@@ -1303,6 +1317,15 @@ + #endif + } + } ++ if (equiv_savings < 0) ++ temp_costs->mem_cost = -equiv_savings; ++ else if (equiv_savings > 0) ++ { ++ temp_costs->mem_cost = 0; ++ for (k = 0; k < cost_classes_num; k++) ++ temp_costs->cost[k] += equiv_savings; ++ } ++ + best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; + best = ALL_REGS; + alt_class = NO_REGS; +@@ -1672,6 +1695,8 @@ + regno_cover_class + = (enum reg_class *) ira_allocate (sizeof (enum reg_class) + * max_reg_num ()); ++ regno_equiv_gains = (int *) ira_allocate (sizeof (int) * max_reg_num ()); ++ memset (regno_equiv_gains, 0, sizeof (int) * max_reg_num ()); + } + + /* Common finalization function for ira_costs and +@@ -1679,6 +1704,7 @@ + static void + finish_costs (void) + { ++ ira_free (regno_equiv_gains); + ira_free (regno_cover_class); + ira_free (pref_buffer); + ira_free (costs); +@@ -1694,6 +1720,7 @@ + init_costs (); + total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size + * ira_allocnos_num); ++ calculate_elim_costs_all_insns (); + find_costs_and_classes (ira_dump_file); + setup_allocno_cover_class_and_costs (); + finish_costs (); +@@ -1767,3 +1794,16 @@ + ALLOCNO_COVER_CLASS_COST (a) = min_cost; + } + } ++ ++/* Add COST to the estimated gain for eliminating REGNO with its ++ equivalence. If COST is zero, record that no such elimination is ++ possible. */ ++ ++void ++ira_adjust_equiv_reg_cost (unsigned regno, int cost) ++{ ++ if (cost == 0) ++ regno_equiv_gains[regno] = 0; ++ else ++ regno_equiv_gains[regno] += cost; ++} +--- a/src/gcc/ira-lives.c ++++ b/src/gcc/ira-lives.c +@@ -805,6 +805,9 @@ + ? GENERAL_REGS + : REG_CLASS_FROM_CONSTRAINT (c, p)); + if (cl != NO_REGS ++ /* There is no register pressure problem if all of the ++ regs in this class are fixed. */ ++ && ira_available_class_regs[cl] != 0 + && (ira_available_class_regs[cl] + <= ira_reg_class_nregs[cl][mode])) + IOR_HARD_REG_SET (*set, reg_class_contents[cl]); +--- a/src/gcc/ira.c ++++ b/src/gcc/ira.c +@@ -431,9 +431,6 @@ + HARD_REG_SET processed_hard_reg_set; + + ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); +- /* We could call ORDER_REGS_FOR_LOCAL_ALLOC here (it is usually +- putting hard callee-used hard registers first). But our +- heuristics work better. */ + for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) + { + COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); +@@ -490,6 +487,9 @@ + static void + setup_alloc_regs (bool use_hard_frame_p) + { ++#ifdef ADJUST_REG_ALLOC_ORDER ++ ADJUST_REG_ALLOC_ORDER; ++#endif + COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); + if (! use_hard_frame_p) + SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); +@@ -1385,14 +1385,12 @@ + return for_each_rtx (&insn, insn_contains_asm_1, NULL); + } + +-/* Set up regs_asm_clobbered. */ ++/* Add register clobbers from asm statements. */ + static void +-compute_regs_asm_clobbered (char *regs_asm_clobbered) ++compute_regs_asm_clobbered (void) + { + basic_block bb; + +- memset (regs_asm_clobbered, 0, sizeof (char) * FIRST_PSEUDO_REGISTER); +- + FOR_EACH_BB (bb) + { + rtx insn; +@@ -1413,7 +1411,7 @@ + + hard_regno_nregs[dregno][mode] - 1; + + for (i = dregno; i <= end; ++i) +- regs_asm_clobbered[i] = 1; ++ SET_HARD_REG_BIT(crtl->asm_clobbers, i); + } + } + } +@@ -1425,12 +1423,6 @@ + void + ira_setup_eliminable_regset (void) + { +- /* Like regs_ever_live, but 1 if a reg is set or clobbered from an +- asm. Unlike regs_ever_live, elements of this array corresponding +- to eliminable regs (like the frame pointer) are set if an asm +- sets them. */ +- char *regs_asm_clobbered +- = (char *) alloca (FIRST_PSEUDO_REGISTER * sizeof (char)); + #ifdef ELIMINABLE_REGS + int i; + static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; +@@ -1454,7 +1446,8 @@ + COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs); + CLEAR_HARD_REG_SET (eliminable_regset); + +- compute_regs_asm_clobbered (regs_asm_clobbered); ++ compute_regs_asm_clobbered (); ++ + /* Build the regset of all eliminable registers and show we can't + use those that we already know won't be eliminated. */ + #ifdef ELIMINABLE_REGS +@@ -1464,7 +1457,7 @@ + = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to) + || (eliminables[i].to == STACK_POINTER_REGNUM && need_fp)); + +- if (! regs_asm_clobbered[eliminables[i].from]) ++ if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from)) + { + SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); + +@@ -1478,7 +1471,7 @@ + df_set_regs_ever_live (eliminables[i].from, true); + } + #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM +- if (! regs_asm_clobbered[HARD_FRAME_POINTER_REGNUM]) ++ if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) + { + SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM); + if (need_fp) +@@ -1492,7 +1485,7 @@ + #endif + + #else +- if (! regs_asm_clobbered[FRAME_POINTER_REGNUM]) ++ if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) + { + SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM); + if (need_fp) +@@ -1540,12 +1533,8 @@ + + x = XEXP (note, 0); + +- if (! function_invariant_p (x) +- || ! flag_pic +- /* A function invariant is often CONSTANT_P but may +- include a register. We promise to only pass CONSTANT_P +- objects to LEGITIMATE_PIC_OPERAND_P. */ +- || (CONSTANT_P (x) && LEGITIMATE_PIC_OPERAND_P (x))) ++ if (! CONSTANT_P (x) ++ || ! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)) + { + /* It can happen that a REG_EQUIV note contains a MEM + that is not a legitimate memory operand. As later +@@ -3103,8 +3092,19 @@ + if (dump_file) + print_insn_chains (dump_file); + } +- + ++/* Allocate memory for reg_equiv_memory_loc. */ ++static void ++init_reg_equiv_memory_loc (void) ++{ ++ max_regno = max_reg_num (); ++ ++ /* And the reg_equiv_memory_loc array. */ ++ VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno); ++ memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0, ++ sizeof (rtx) * max_regno); ++ reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec); ++} + + /* All natural loops. */ + struct loops ira_loops; +@@ -3209,6 +3209,8 @@ + record_loop_exits (); + current_loops = &ira_loops; + ++ init_reg_equiv_memory_loc (); ++ + if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) + fprintf (ira_dump_file, "Building IRA IR\n"); + loops_p = ira_build (optimize +@@ -3272,13 +3274,8 @@ + #endif + + delete_trivially_dead_insns (get_insns (), max_reg_num ()); +- max_regno = max_reg_num (); + +- /* And the reg_equiv_memory_loc array. */ +- VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno); +- memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0, +- sizeof (rtx) * max_regno); +- reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec); ++ init_reg_equiv_memory_loc (); + + if (max_regno != max_regno_before_ira) + { +--- a/src/gcc/ira.h ++++ b/src/gcc/ira.h +@@ -87,3 +87,4 @@ + extern void ira_mark_new_stack_slot (rtx, int, unsigned int); + extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx); + ++extern void ira_adjust_equiv_reg_cost (unsigned, int); +--- a/src/gcc/jump.c ++++ b/src/gcc/jump.c +@@ -29,7 +29,8 @@ + JUMP_LABEL internal field. With this we can detect labels that + become unused because of the deletion of all the jumps that + formerly used them. The JUMP_LABEL info is sometimes looked +- at by later passes. ++ at by later passes. For return insns, it contains either a ++ RETURN or a SIMPLE_RETURN rtx. + + The subroutines redirect_jump and invert_jump are used + from other passes as well. */ +@@ -194,7 +195,7 @@ + rtx prev_nonjump_insn = NULL; + + for (insn = f; insn; insn = NEXT_INSN (insn)) +- if (INSN_P (insn)) ++ if (NONDEBUG_INSN_P (insn)) + { + mark_jump_label (PATTERN (insn), insn, 0); + +@@ -742,10 +743,10 @@ + return (GET_CODE (x) == IF_THEN_ELSE + && ((GET_CODE (XEXP (x, 2)) == PC + && (GET_CODE (XEXP (x, 1)) == LABEL_REF +- || GET_CODE (XEXP (x, 1)) == RETURN)) ++ || ANY_RETURN_P (XEXP (x, 1)))) + || (GET_CODE (XEXP (x, 1)) == PC + && (GET_CODE (XEXP (x, 2)) == LABEL_REF +- || GET_CODE (XEXP (x, 2)) == RETURN)))); ++ || ANY_RETURN_P (XEXP (x, 2)))))); + } + + /* Return nonzero if INSN is a (possibly) conditional jump inside a +@@ -774,11 +775,11 @@ + return 0; + if (XEXP (SET_SRC (x), 2) == pc_rtx + && (GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF +- || GET_CODE (XEXP (SET_SRC (x), 1)) == RETURN)) ++ || ANY_RETURN_P (XEXP (SET_SRC (x), 1)) == RETURN)) + return 1; + if (XEXP (SET_SRC (x), 1) == pc_rtx + && (GET_CODE (XEXP (SET_SRC (x), 2)) == LABEL_REF +- || GET_CODE (XEXP (SET_SRC (x), 2)) == RETURN)) ++ || ANY_RETURN_P (XEXP (SET_SRC (x), 2)))) + return 1; + return 0; + } +@@ -840,8 +841,9 @@ + a = GET_CODE (XEXP (SET_SRC (x), 1)); + b = GET_CODE (XEXP (SET_SRC (x), 2)); + +- return ((b == PC && (a == LABEL_REF || a == RETURN)) +- || (a == PC && (b == LABEL_REF || b == RETURN))); ++ return ((b == PC && (a == LABEL_REF || a == RETURN || a == SIMPLE_RETURN)) ++ || (a == PC ++ && (b == LABEL_REF || b == RETURN || b == SIMPLE_RETURN))); + } + + /* Return the label of a conditional jump. */ +@@ -878,6 +880,7 @@ + switch (GET_CODE (x)) + { + case RETURN: ++ case SIMPLE_RETURN: + case EH_RETURN: + return true; + +@@ -1200,7 +1203,7 @@ + /* If deleting a jump, decrement the count of the label, + and delete the label if it is now unused. */ + +- if (JUMP_P (insn) && JUMP_LABEL (insn)) ++ if (JUMP_P (insn) && JUMP_LABEL (insn) && !ANY_RETURN_P (JUMP_LABEL (insn))) + { + rtx lab = JUMP_LABEL (insn), lab_next; + +@@ -1331,6 +1334,18 @@ + is also an unconditional jump in that case. */ + } + ++/* A helper function for redirect_exp_1; examines its input X and returns ++ either a LABEL_REF around a label, or a RETURN if X was NULL. */ ++static rtx ++redirect_target (rtx x) ++{ ++ if (x == NULL_RTX) ++ return ret_rtx; ++ if (!ANY_RETURN_P (x)) ++ return gen_rtx_LABEL_REF (Pmode, x); ++ return x; ++} ++ + /* Throughout LOC, redirect OLABEL to NLABEL. Treat null OLABEL or + NLABEL as a return. Accrue modifications into the change group. */ + +@@ -1342,37 +1357,19 @@ + int i; + const char *fmt; + +- if (code == LABEL_REF) ++ if ((code == LABEL_REF && XEXP (x, 0) == olabel) ++ || x == olabel) + { +- if (XEXP (x, 0) == olabel) +- { +- rtx n; +- if (nlabel) +- n = gen_rtx_LABEL_REF (Pmode, nlabel); +- else +- n = gen_rtx_RETURN (VOIDmode); +- +- validate_change (insn, loc, n, 1); +- return; +- } +- } +- else if (code == RETURN && olabel == 0) +- { +- if (nlabel) +- x = gen_rtx_LABEL_REF (Pmode, nlabel); +- else +- x = gen_rtx_RETURN (VOIDmode); +- if (loc == &PATTERN (insn)) +- x = gen_rtx_SET (VOIDmode, pc_rtx, x); +- validate_change (insn, loc, x, 1); ++ validate_change (insn, loc, redirect_target (nlabel), 1); + return; + } + +- if (code == SET && nlabel == 0 && SET_DEST (x) == pc_rtx ++ if (code == SET && SET_DEST (x) == pc_rtx ++ && ANY_RETURN_P (nlabel) + && GET_CODE (SET_SRC (x)) == LABEL_REF + && XEXP (SET_SRC (x), 0) == olabel) + { +- validate_change (insn, loc, gen_rtx_RETURN (VOIDmode), 1); ++ validate_change (insn, loc, nlabel, 1); + return; + } + +@@ -1409,6 +1406,7 @@ + int ochanges = num_validated_changes (); + rtx *loc, asmop; + ++ gcc_assert (nlabel); + asmop = extract_asm_operands (PATTERN (jump)); + if (asmop) + { +@@ -1430,17 +1428,20 @@ + jump target label is unused as a result, it and the code following + it may be deleted. + +- If NLABEL is zero, we are to turn the jump into a (possibly conditional) +- RETURN insn. ++ Normally, NLABEL will be a label, but it may also be a RETURN or ++ SIMPLE_RETURN rtx; in that case we are to turn the jump into a ++ (possibly conditional) return insn. + + The return value will be 1 if the change was made, 0 if it wasn't +- (this can only occur for NLABEL == 0). */ ++ (this can only occur when trying to produce return insns). */ + + int + redirect_jump (rtx jump, rtx nlabel, int delete_unused) + { + rtx olabel = JUMP_LABEL (jump); + ++ gcc_assert (nlabel != NULL_RTX); ++ + if (nlabel == olabel) + return 1; + +@@ -1452,7 +1453,7 @@ + } + + /* Fix up JUMP_LABEL and label ref counts after OLABEL has been replaced with +- NLABEL in JUMP. ++ NEW_DEST in JUMP. + If DELETE_UNUSED is positive, delete related insn to OLABEL if its ref + count has dropped to zero. */ + void +@@ -1468,13 +1469,14 @@ + about this. */ + gcc_assert (delete_unused >= 0); + JUMP_LABEL (jump) = nlabel; +- if (nlabel) ++ if (nlabel && !ANY_RETURN_P (nlabel)) + ++LABEL_NUSES (nlabel); + + /* Update labels in any REG_EQUAL note. */ + if ((note = find_reg_note (jump, REG_EQUAL, NULL_RTX)) != NULL_RTX) + { +- if (!nlabel || (invert && !invert_exp_1 (XEXP (note, 0), jump))) ++ if (ANY_RETURN_P (nlabel) ++ || (invert && !invert_exp_1 (XEXP (note, 0), jump))) + remove_note (jump, note); + else + { +@@ -1483,7 +1485,8 @@ + } + } + +- if (olabel && --LABEL_NUSES (olabel) == 0 && delete_unused > 0 ++ if (olabel && !ANY_RETURN_P (olabel) ++ && --LABEL_NUSES (olabel) == 0 && delete_unused > 0 + /* Undefined labels will remain outside the insn stream. */ + && INSN_UID (olabel)) + delete_related_insns (olabel); +@@ -1728,7 +1731,13 @@ + + case 'i': + if (XINT (x, i) != XINT (y, i)) +- return 0; ++ { ++ if (((code == ASM_OPERANDS && i == 6) ++ || (code == ASM_INPUT && i == 1)) ++ && locator_eq (XINT (x, i), XINT (y, i))) ++ break; ++ return 0; ++ } + break; + + case 't': +--- a/src/gcc/loop-invariant.c ++++ b/src/gcc/loop-invariant.c +@@ -1173,11 +1173,13 @@ + /* Calculates gain for eliminating invariant INV. REGS_USED is the number + of registers used in the loop, NEW_REGS is the number of new variables + already added due to the invariant motion. The number of registers needed +- for it is stored in *REGS_NEEDED. */ ++ for it is stored in *REGS_NEEDED. SPEED and CALL_P are flags passed ++ through to estimate_reg_pressure_cost. */ + + static int + gain_for_invariant (struct invariant *inv, unsigned *regs_needed, +- unsigned *new_regs, unsigned regs_used, bool speed) ++ unsigned *new_regs, unsigned regs_used, ++ bool speed, bool call_p) + { + int comp_cost, size_cost; + +@@ -1188,9 +1190,9 @@ + if (! flag_ira_loop_pressure) + { + size_cost = (estimate_reg_pressure_cost (new_regs[0] + regs_needed[0], +- regs_used, speed) ++ regs_used, speed, call_p) + - estimate_reg_pressure_cost (new_regs[0], +- regs_used, speed)); ++ regs_used, speed, call_p)); + } + else + { +@@ -1245,7 +1247,8 @@ + + static int + best_gain_for_invariant (struct invariant **best, unsigned *regs_needed, +- unsigned *new_regs, unsigned regs_used, bool speed) ++ unsigned *new_regs, unsigned regs_used, ++ bool speed, bool call_p) + { + struct invariant *inv; + int i, gain = 0, again; +@@ -1261,7 +1264,7 @@ + continue; + + again = gain_for_invariant (inv, aregs_needed, new_regs, regs_used, +- speed); ++ speed, call_p); + if (again > gain) + { + gain = again; +@@ -1314,7 +1317,7 @@ + /* Determines which invariants to move. */ + + static void +-find_invariants_to_move (bool speed) ++find_invariants_to_move (bool speed, bool call_p) + { + int gain; + unsigned i, regs_used, regs_needed[N_REG_CLASSES], new_regs[N_REG_CLASSES]; +@@ -1353,7 +1356,8 @@ + new_regs[ira_reg_class_cover[i]] = 0; + } + while ((gain = best_gain_for_invariant (&inv, regs_needed, +- new_regs, regs_used, speed)) > 0) ++ new_regs, regs_used, ++ speed, call_p)) > 0) + { + set_move_mark (inv->invno, gain); + if (! flag_ira_loop_pressure) +@@ -1554,7 +1558,8 @@ + init_inv_motion_data (); + + find_invariants (loop); +- find_invariants_to_move (optimize_loop_for_speed_p (loop)); ++ find_invariants_to_move (optimize_loop_for_speed_p (loop), ++ LOOP_DATA (loop)->has_call); + move_invariants (loop); + + free_inv_motion_data (); +--- a/src/gcc/loop-iv.c ++++ b/src/gcc/loop-iv.c +@@ -796,6 +796,13 @@ + outer_step)) + return false; + ++ /* CSL local: workaround get_biv_step_1() inability to handle DU ++ chains originating at sets of subregs. Such subregs are introduced ++ by Tom's extension elimination pass. For upstream duscussion see ++ http://gcc.gnu.org/ml/gcc/2010-11/msg00552.html . */ ++ if (!((*inner_mode == *outer_mode) != (*extend != UNKNOWN))) ++ return false; ++ + gcc_assert ((*inner_mode == *outer_mode) != (*extend != UNKNOWN)); + gcc_assert (*inner_mode != *outer_mode || *outer_step == const0_rtx); + +--- a/src/gcc/objc/lang-specs.h ++++ b/src/gcc/objc/lang-specs.h +@@ -26,29 +26,33 @@ + {"@objective-c", + "%{E|M|MM:cc1obj -E %{traditional|ftraditional|traditional-cpp:-traditional-cpp}\ + %(cpp_options) %(cpp_debug_options)}\ ++ %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \ + %{!E:%{!M:%{!MM:\ + %{traditional|ftraditional|traditional-cpp:\ + %eGNU Objective C no longer supports traditional compilation}\ + %{save-temps|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps:%b.mi} %{!save-temps:%g.mi} \n\ +- cc1obj -fpreprocessed %{save-temps:%b.mi} %{!save-temps:%g.mi} %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}\ ++ cc1obj -fpreprocessed -fno-section-anchors %{save-temps:%b.mi} %{!save-temps:%g.mi} %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}\ + %{!save-temps:%{!no-integrated-cpp:\ +- cc1obj %(cpp_unique_options) %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}}\ ++ cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}}\ + %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, + {".mi", "@objc-cpp-output", 0, 0, 0}, + {"@objc-cpp-output", +- "%{!M:%{!MM:%{!E:cc1obj -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ +- %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, ++ "%{!M:%{!MM:%{!E:cc1obj -fno-section-anchors -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ ++ %{!fsyntax-only:%(invoke_as)}}}} \ ++ %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} ", 0, 0, 0}, + {"@objective-c-header", + "%{E|M|MM:cc1obj -E %{traditional|ftraditional|traditional-cpp:-traditional-cpp}\ + %(cpp_options) %(cpp_debug_options)}\ ++ %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \ + %{!E:%{!M:%{!MM:\ + %{traditional|ftraditional|traditional-cpp:\ + %eGNU Objective C no longer supports traditional compilation}\ + %{save-temps|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps:%b.mi} %{!save-temps:%g.mi} \n\ +- cc1obj -fpreprocessed %b.mi %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ ++ cc1obj -fpreprocessed %b.mi %(cc1_options) -fno-section-anchors %{print-objc-runtime-info} %{gen-decls}\ + -o %g.s %{!o*:--output-pch=%i.gch}\ + %W{o*:--output-pch=%*}%V}\ ++ %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \ + %{!save-temps:%{!no-integrated-cpp:\ +- cc1obj %(cpp_unique_options) %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ ++ cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ + -o %g.s %{!o*:--output-pch=%i.gch}\ + %W{o*:--output-pch=%*}%V}}}}}", 0, 0, 0}, +--- a/src/gcc/optabs.c ++++ b/src/gcc/optabs.c +@@ -408,6 +408,20 @@ + case DOT_PROD_EXPR: + return TYPE_UNSIGNED (type) ? udot_prod_optab : sdot_prod_optab; + ++ case WIDEN_MULT_PLUS_EXPR: ++ return (TYPE_UNSIGNED (type) ++ ? (TYPE_SATURATING (type) ++ ? usmadd_widen_optab : umadd_widen_optab) ++ : (TYPE_SATURATING (type) ++ ? ssmadd_widen_optab : smadd_widen_optab)); ++ ++ case WIDEN_MULT_MINUS_EXPR: ++ return (TYPE_UNSIGNED (type) ++ ? (TYPE_SATURATING (type) ++ ? usmsub_widen_optab : umsub_widen_optab) ++ : (TYPE_SATURATING (type) ++ ? ssmsub_widen_optab : smsub_widen_optab)); ++ + case REDUC_MAX_EXPR: + return TYPE_UNSIGNED (type) ? reduc_umax_optab : reduc_smax_optab; + +@@ -547,7 +561,12 @@ + tmode0 = TYPE_MODE (TREE_TYPE (oprnd0)); + widen_pattern_optab = + optab_for_tree_code (ops->code, TREE_TYPE (oprnd0), optab_default); +- icode = (int) optab_handler (widen_pattern_optab, tmode0)->insn_code; ++ if (ops->code == WIDEN_MULT_PLUS_EXPR ++ || ops->code == WIDEN_MULT_MINUS_EXPR) ++ icode = (int) optab_handler (widen_pattern_optab, ++ TYPE_MODE (TREE_TYPE (ops->op2)))->insn_code; ++ else ++ icode = (int) optab_handler (widen_pattern_optab, tmode0)->insn_code; + gcc_assert (icode != CODE_FOR_nothing); + xmode0 = insn_data[icode].operand[1].mode; + +--- a/src/gcc/optabs.h ++++ b/src/gcc/optabs.h +@@ -771,6 +771,9 @@ + /* Generate code for float to integral conversion. */ + extern bool expand_sfix_optab (rtx, rtx, convert_optab); + ++/* Generate code for a widening multiply. */ ++extern rtx expand_widening_mult (enum machine_mode, rtx, rtx, rtx, int, optab); ++ + /* Return tree if target supports vector operations for COND_EXPR. */ + bool expand_vec_cond_expr_p (tree, enum machine_mode); + +--- a/src/gcc/opts.c ++++ b/src/gcc/opts.c +@@ -905,8 +905,11 @@ + flag_tree_builtin_call_dce = opt2; + flag_tree_pre = opt2; + flag_tree_switch_conversion = opt2; ++ flag_tree_if_to_switch_conversion = opt2; + flag_ipa_cp = opt2; + flag_ipa_sra = opt2; ++ flag_ee = opt2; ++ flag_shrink_wrap = opt2; + + /* Track fields in field-sensitive alias analysis. */ + set_param_value ("max-fields-for-field-sensitive", +--- a/src/gcc/output.h ++++ b/src/gcc/output.h +@@ -173,6 +173,11 @@ + Prefixes such as % are optional. */ + extern int decode_reg_name (const char *); + ++/* Similar to decode_reg_name, but takes an extra parameter that is a ++ pointer to the number of (internal) registers described by the ++ external name. */ ++extern int decode_reg_name_and_count (const char *, int *); ++ + extern void assemble_alias (tree, tree); + + extern void default_assemble_visibility (tree, int); +--- a/src/gcc/params.def ++++ b/src/gcc/params.def +@@ -219,6 +219,29 @@ + "gcse-after-reload-critical-fraction", + "The threshold ratio of critical edges execution count that permit performing redundancy elimination after reload", + 10, 0, 0) ++ ++/* GCSE will use GCSE_COST_DISTANCE_RATION as a scaling factor ++ to calculate maximum distance for which an expression is allowed to move ++ from its rtx_cost. */ ++DEFPARAM(PARAM_GCSE_COST_DISTANCE_RATIO, ++ "gcse-cost-distance-ratio", ++ "Scaling factor in calculation of maximum distance an expression can be moved by GCSE optimizations", ++ 10, 0, 0) ++/* GCSE won't restrict distance for which an expression with rtx_cost greater ++ than COSTS_N_INSN(GCSE_UNRESTRICTED_COST) is allowed to move. */ ++DEFPARAM(PARAM_GCSE_UNRESTRICTED_COST, ++ "gcse-unrestricted-cost", ++ "Cost at which GCSE optimizations will not constraint the distance an expression can travel", ++ 3, 0, 0) ++ ++/* How deep from a given basic block the dominator tree should be searched ++ for expressions to hoist to the block. The value of 0 will avoid limiting ++ the search. */ ++DEFPARAM(PARAM_MAX_HOIST_DEPTH, ++ "max-hoist-depth", ++ "Maximum depth of search in the dominator tree for expressions to hoist", ++ 30, 0, 0) ++ + /* This parameter limits the number of insns in a loop that will be unrolled, + and by how much the loop is unrolled. + +@@ -803,6 +826,11 @@ + "a pointer to an aggregate with", + 2, 0, 0) + ++DEFPARAM (PARAM_IF_TO_SWITCH_THRESHOLD, ++ "if-to-switch-threshold", ++ "Threshold for converting an if-chain into a switch", ++ 3, 0, 0) ++ + /* + Local variables: + mode:c +--- a/src/gcc/params.h ++++ b/src/gcc/params.h +@@ -125,6 +125,12 @@ + PARAM_VALUE (PARAM_GCSE_AFTER_RELOAD_PARTIAL_FRACTION) + #define GCSE_AFTER_RELOAD_CRITICAL_FRACTION \ + PARAM_VALUE (PARAM_GCSE_AFTER_RELOAD_CRITICAL_FRACTION) ++#define GCSE_COST_DISTANCE_RATIO \ ++ PARAM_VALUE (PARAM_GCSE_COST_DISTANCE_RATIO) ++#define GCSE_UNRESTRICTED_COST \ ++ PARAM_VALUE (PARAM_GCSE_UNRESTRICTED_COST) ++#define MAX_HOIST_DEPTH \ ++ PARAM_VALUE (PARAM_MAX_HOIST_DEPTH) + #define MAX_UNROLLED_INSNS \ + PARAM_VALUE (PARAM_MAX_UNROLLED_INSNS) + #define MAX_SMS_LOOP_NUMBER \ +--- a/src/gcc/passes.c ++++ b/src/gcc/passes.c +@@ -788,6 +788,7 @@ + NEXT_PASS (pass_cd_dce); + NEXT_PASS (pass_early_ipa_sra); + NEXT_PASS (pass_tail_recursion); ++ NEXT_PASS (pass_if_to_switch); + NEXT_PASS (pass_convert_switch); + NEXT_PASS (pass_cleanup_eh); + NEXT_PASS (pass_profile); +@@ -844,6 +845,7 @@ + NEXT_PASS (pass_phiprop); + NEXT_PASS (pass_fre); + NEXT_PASS (pass_copy_prop); ++ NEXT_PASS (pass_if_to_switch); + NEXT_PASS (pass_merge_phi); + NEXT_PASS (pass_vrp); + NEXT_PASS (pass_dce); +@@ -944,6 +946,7 @@ + NEXT_PASS (pass_forwprop); + NEXT_PASS (pass_phiopt); + NEXT_PASS (pass_fold_builtins); ++ NEXT_PASS (pass_optimize_widening_mul); + NEXT_PASS (pass_tail_calls); + NEXT_PASS (pass_rename_ssa_copies); + NEXT_PASS (pass_uncprop); +@@ -973,6 +976,7 @@ + NEXT_PASS (pass_lower_subreg); + NEXT_PASS (pass_df_initialize_opt); + NEXT_PASS (pass_cse); ++ NEXT_PASS (pass_ee); + NEXT_PASS (pass_rtl_fwprop); + NEXT_PASS (pass_rtl_cprop); + NEXT_PASS (pass_rtl_pre); +--- a/src/gcc/postreload.c ++++ b/src/gcc/postreload.c +@@ -44,6 +44,7 @@ + #include "toplev.h" + #include "except.h" + #include "tree.h" ++#include "target.h" + #include "timevar.h" + #include "tree-pass.h" + #include "df.h" +@@ -56,10 +57,10 @@ + static int reload_cse_simplify_operands (rtx, rtx); + + static void reload_combine (void); +-static void reload_combine_note_use (rtx *, rtx); ++static void reload_combine_note_use (rtx *, rtx, int, rtx); + static void reload_combine_note_store (rtx, const_rtx, void *); + +-static void reload_cse_move2add (rtx); ++static bool reload_cse_move2add (rtx); + static void move2add_note_store (rtx, const_rtx, void *); + + /* Call cse / combine like post-reload optimization phases. +@@ -67,11 +68,16 @@ + void + reload_cse_regs (rtx first ATTRIBUTE_UNUSED) + { ++ bool moves_converted; + reload_cse_regs_1 (first); + reload_combine (); +- reload_cse_move2add (first); ++ moves_converted = reload_cse_move2add (first); + if (flag_expensive_optimizations) +- reload_cse_regs_1 (first); ++ { ++ if (moves_converted) ++ reload_combine (); ++ reload_cse_regs_1 (first); ++ } + } + + /* See whether a single set SET is a noop. */ +@@ -660,30 +666,43 @@ + + /* The maximum number of uses of a register we can keep track of to + replace them with reg+reg addressing. */ +-#define RELOAD_COMBINE_MAX_USES 6 ++#define RELOAD_COMBINE_MAX_USES 16 + +-/* INSN is the insn where a register has been used, and USEP points to the +- location of the register within the rtl. */ +-struct reg_use { rtx insn, *usep; }; ++/* Describes a recorded use of a register. */ ++struct reg_use ++{ ++ /* The insn where a register has been used. */ ++ rtx insn; ++ /* Points to the memory reference enclosing the use, if any, NULL_RTX ++ otherwise. */ ++ rtx containing_mem; ++ /* Location of the register withing INSN. */ ++ rtx *usep; ++ /* The reverse uid of the insn. */ ++ int ruid; ++}; + + /* If the register is used in some unknown fashion, USE_INDEX is negative. + If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID +- indicates where it becomes live again. ++ indicates where it is first set or clobbered. + Otherwise, USE_INDEX is the index of the last encountered use of the +- register (which is first among these we have seen since we scan backwards), +- OFFSET contains the constant offset that is added to the register in +- all encountered uses, and USE_RUID indicates the first encountered, i.e. +- last, of these uses. ++ register (which is first among these we have seen since we scan backwards). ++ USE_RUID indicates the first encountered, i.e. last, of these uses. ++ If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS ++ with a constant offset; OFFSET contains this constant in that case. + STORE_RUID is always meaningful if we only want to use a value in a + register in a different place: it denotes the next insn in the insn +- stream (i.e. the last encountered) that sets or clobbers the register. */ ++ stream (i.e. the last encountered) that sets or clobbers the register. ++ REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */ + static struct + { + struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; +- int use_index; + rtx offset; ++ int use_index; + int store_ruid; ++ int real_store_ruid; + int use_ruid; ++ bool all_offsets_match; + } reg_state[FIRST_PSEUDO_REGISTER]; + + /* Reverse linear uid. This is increased in reload_combine while scanning +@@ -691,42 +710,548 @@ + and the store_ruid / use_ruid fields in reg_state. */ + static int reload_combine_ruid; + ++/* The RUID of the last label we encountered in reload_combine. */ ++static int last_label_ruid; ++ ++/* The RUID of the last jump we encountered in reload_combine. */ ++static int last_jump_ruid; ++ ++/* The register numbers of the first and last index register. A value of ++ -1 in LAST_INDEX_REG indicates that we've previously computed these ++ values and found no suitable index registers. */ ++static int first_index_reg = -1; ++static int last_index_reg; ++ + #define LABEL_LIVE(LABEL) \ + (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) + ++/* Subroutine of reload_combine_split_ruids, called to fix up a single ++ ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */ ++ ++static inline void ++reload_combine_split_one_ruid (int *pruid, int split_ruid) ++{ ++ if (*pruid > split_ruid) ++ (*pruid)++; ++} ++ ++/* Called when we insert a new insn in a position we've already passed in ++ the scan. Examine all our state, increasing all ruids that are higher ++ than SPLIT_RUID by one in order to make room for a new insn. */ ++ ++static void ++reload_combine_split_ruids (int split_ruid) ++{ ++ unsigned i; ++ ++ reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid); ++ reload_combine_split_one_ruid (&last_label_ruid, split_ruid); ++ reload_combine_split_one_ruid (&last_jump_ruid, split_ruid); ++ ++ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) ++ { ++ int j, idx = reg_state[i].use_index; ++ reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid); ++ reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid); ++ reload_combine_split_one_ruid (®_state[i].real_store_ruid, ++ split_ruid); ++ if (idx < 0) ++ continue; ++ for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++) ++ { ++ reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid, ++ split_ruid); ++ } ++ } ++} ++ ++/* Called when we are about to rescan a previously encountered insn with ++ reload_combine_note_use after modifying some part of it. This clears all ++ information about uses in that particular insn. */ ++ ++static void ++reload_combine_purge_insn_uses (rtx insn) ++{ ++ unsigned i; ++ ++ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) ++ { ++ int j, k, idx = reg_state[i].use_index; ++ if (idx < 0) ++ continue; ++ j = k = RELOAD_COMBINE_MAX_USES; ++ while (j-- > idx) ++ { ++ if (reg_state[i].reg_use[j].insn != insn) ++ { ++ k--; ++ if (k != j) ++ reg_state[i].reg_use[k] = reg_state[i].reg_use[j]; ++ } ++ } ++ reg_state[i].use_index = k; ++ } ++} ++ ++/* Called when we need to forget about all uses of REGNO after an insn ++ which is identified by RUID. */ ++ ++static void ++reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid) ++{ ++ int j, k, idx = reg_state[regno].use_index; ++ if (idx < 0) ++ return; ++ j = k = RELOAD_COMBINE_MAX_USES; ++ while (j-- > idx) ++ { ++ if (reg_state[regno].reg_use[j].ruid >= ruid) ++ { ++ k--; ++ if (k != j) ++ reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j]; ++ } ++ } ++ reg_state[regno].use_index = k; ++} ++ ++/* Find the use of REGNO with the ruid that is highest among those ++ lower than RUID_LIMIT, and return it if it is the only use of this ++ reg in the insn. Return NULL otherwise. */ ++ ++static struct reg_use * ++reload_combine_closest_single_use (unsigned regno, int ruid_limit) ++{ ++ int i, best_ruid = 0; ++ int use_idx = reg_state[regno].use_index; ++ struct reg_use *retval; ++ ++ if (use_idx < 0) ++ return NULL; ++ retval = NULL; ++ for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++) ++ { ++ struct reg_use *use = reg_state[regno].reg_use + i; ++ int this_ruid = use->ruid; ++ if (this_ruid >= ruid_limit) ++ continue; ++ if (this_ruid > best_ruid) ++ { ++ best_ruid = this_ruid; ++ retval = use; ++ } ++ else if (this_ruid == best_ruid) ++ retval = NULL; ++ } ++ if (last_label_ruid >= best_ruid) ++ return NULL; ++ return retval; ++} ++ ++/* After we've moved an add insn, fix up any debug insns that occur ++ between the old location of the add and the new location. REG is ++ the destination register of the add insn; REPLACEMENT is the ++ SET_SRC of the add. FROM and TO specify the range in which we ++ should make this change on debug insns. */ ++ ++static void ++fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to) ++{ ++ rtx insn; ++ for (insn = from; insn != to; insn = NEXT_INSN (insn)) ++ { ++ rtx t; ++ ++ if (!DEBUG_INSN_P (insn)) ++ continue; ++ ++ t = INSN_VAR_LOCATION_LOC (insn); ++ t = simplify_replace_rtx (t, reg, replacement); ++ validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0); ++ } ++} ++ ++/* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG ++ with SRC in the insn described by USE, taking costs into account. Return ++ true if we made the replacement. */ ++ ++static bool ++try_replace_in_use (struct reg_use *use, rtx reg, rtx src) ++{ ++ rtx use_insn = use->insn; ++ rtx mem = use->containing_mem; ++ bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); ++ ++ if (mem != NULL_RTX) ++ { ++ addr_space_t as = MEM_ADDR_SPACE (mem); ++ rtx oldaddr = XEXP (mem, 0); ++ rtx newaddr = NULL_RTX; ++ int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed); ++ int new_cost; ++ ++ newaddr = simplify_replace_rtx (oldaddr, reg, src); ++ if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as)) ++ { ++ XEXP (mem, 0) = newaddr; ++ new_cost = address_cost (newaddr, GET_MODE (mem), as, speed); ++ XEXP (mem, 0) = oldaddr; ++ if (new_cost <= old_cost ++ && validate_change (use_insn, ++ &XEXP (mem, 0), newaddr, 0)) ++ return true; ++ } ++ } ++ else ++ { ++ rtx new_set = single_set (use_insn); ++ if (new_set ++ && REG_P (SET_DEST (new_set)) ++ && GET_CODE (SET_SRC (new_set)) == PLUS ++ && REG_P (XEXP (SET_SRC (new_set), 0)) ++ && CONSTANT_P (XEXP (SET_SRC (new_set), 1))) ++ { ++ rtx new_src; ++ int old_cost = rtx_cost (SET_SRC (new_set), SET, speed); ++ ++ gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg)); ++ new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src); ++ ++ if (rtx_cost (new_src, SET, speed) <= old_cost ++ && validate_change (use_insn, &SET_SRC (new_set), ++ new_src, 0)) ++ return true; ++ } ++ } ++ return false; ++} ++ ++/* Called by reload_combine when scanning INSN. This function tries to detect ++ patterns where a constant is added to a register, and the result is used ++ in an address. ++ Return true if no further processing is needed on INSN; false if it wasn't ++ recognized and should be handled normally. */ ++ ++static bool ++reload_combine_recognize_const_pattern (rtx insn) ++{ ++ int from_ruid = reload_combine_ruid; ++ rtx set, pat, reg, src, addreg; ++ unsigned int regno; ++ struct reg_use *use; ++ bool must_move_add; ++ rtx add_moved_after_insn = NULL_RTX; ++ int add_moved_after_ruid = 0; ++ int clobbered_regno = -1; ++ ++ set = single_set (insn); ++ if (set == NULL_RTX) ++ return false; ++ ++ reg = SET_DEST (set); ++ src = SET_SRC (set); ++ if (!REG_P (reg) ++ || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1 ++ || GET_MODE (reg) != Pmode ++ || reg == stack_pointer_rtx) ++ return false; ++ ++ regno = REGNO (reg); ++ ++ /* We look for a REG1 = REG2 + CONSTANT insn, followed by either ++ uses of REG1 inside an address, or inside another add insn. If ++ possible and profitable, merge the addition into subsequent ++ uses. */ ++ if (GET_CODE (src) != PLUS ++ || !REG_P (XEXP (src, 0)) ++ || !CONSTANT_P (XEXP (src, 1))) ++ return false; ++ ++ addreg = XEXP (src, 0); ++ must_move_add = rtx_equal_p (reg, addreg); ++ ++ pat = PATTERN (insn); ++ if (must_move_add && set != pat) ++ { ++ /* We have to be careful when moving the add; apart from the ++ single_set there may also be clobbers. Recognize one special ++ case, that of one clobber alongside the set (likely a clobber ++ of the CC register). */ ++ gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL); ++ if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set ++ || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER ++ || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))) ++ return false; ++ clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0)); ++ } ++ ++ do ++ { ++ use = reload_combine_closest_single_use (regno, from_ruid); ++ ++ if (use) ++ /* Start the search for the next use from here. */ ++ from_ruid = use->ruid; ++ ++ if (use && GET_MODE (*use->usep) == Pmode) ++ { ++ bool delete_add = false; ++ rtx use_insn = use->insn; ++ int use_ruid = use->ruid; ++ ++ /* Avoid moving the add insn past a jump. */ ++ if (must_move_add && use_ruid <= last_jump_ruid) ++ break; ++ ++ /* If the add clobbers another hard reg in parallel, don't move ++ it past a real set of this hard reg. */ ++ if (must_move_add && clobbered_regno >= 0 ++ && reg_state[clobbered_regno].real_store_ruid >= use_ruid) ++ break; ++ ++ gcc_assert (reg_state[regno].store_ruid <= use_ruid); ++ /* Avoid moving a use of ADDREG past a point where it is stored. */ ++ if (reg_state[REGNO (addreg)].store_ruid > use_ruid) ++ break; ++ ++ /* We also must not move the addition past an insn that sets ++ the same register, unless we can combine two add insns. */ ++ if (must_move_add && reg_state[regno].store_ruid == use_ruid) ++ { ++ if (use->containing_mem == NULL_RTX) ++ delete_add = true; ++ else ++ break; ++ } ++ ++ if (try_replace_in_use (use, reg, src)) ++ { ++ reload_combine_purge_insn_uses (use_insn); ++ reload_combine_note_use (&PATTERN (use_insn), use_insn, ++ use_ruid, NULL_RTX); ++ ++ if (delete_add) ++ { ++ fixup_debug_insns (reg, src, insn, use_insn); ++ delete_insn (insn); ++ return true; ++ } ++ if (must_move_add) ++ { ++ add_moved_after_insn = use_insn; ++ add_moved_after_ruid = use_ruid; ++ } ++ continue; ++ } ++ } ++ /* If we get here, we couldn't handle this use. */ ++ if (must_move_add) ++ break; ++ } ++ while (use); ++ ++ if (!must_move_add || add_moved_after_insn == NULL_RTX) ++ /* Process the add normally. */ ++ return false; ++ ++ fixup_debug_insns (reg, src, insn, add_moved_after_insn); ++ ++ reorder_insns (insn, insn, add_moved_after_insn); ++ reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid); ++ reload_combine_split_ruids (add_moved_after_ruid - 1); ++ reload_combine_note_use (&PATTERN (insn), insn, ++ add_moved_after_ruid, NULL_RTX); ++ reg_state[regno].store_ruid = add_moved_after_ruid; ++ ++ return true; ++} ++ ++/* Called by reload_combine when scanning INSN. Try to detect a pattern we ++ can handle and improve. Return true if no further processing is needed on ++ INSN; false if it wasn't recognized and should be handled normally. */ ++ ++static bool ++reload_combine_recognize_pattern (rtx insn) ++{ ++ rtx set, reg, src; ++ unsigned int regno; ++ ++ set = single_set (insn); ++ if (set == NULL_RTX) ++ return false; ++ ++ reg = SET_DEST (set); ++ src = SET_SRC (set); ++ if (!REG_P (reg) ++ || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1) ++ return false; ++ ++ regno = REGNO (reg); ++ ++ /* Look for (set (REGX) (CONST_INT)) ++ (set (REGX) (PLUS (REGX) (REGY))) ++ ... ++ ... (MEM (REGX)) ... ++ and convert it to ++ (set (REGZ) (CONST_INT)) ++ ... ++ ... (MEM (PLUS (REGZ) (REGY)))... . ++ ++ First, check that we have (set (REGX) (PLUS (REGX) (REGY))) ++ and that we know all uses of REGX before it dies. ++ Also, explicitly check that REGX != REGY; our life information ++ does not yet show whether REGY changes in this insn. */ ++ ++ if (GET_CODE (src) == PLUS ++ && reg_state[regno].all_offsets_match ++ && last_index_reg != -1 ++ && REG_P (XEXP (src, 1)) ++ && rtx_equal_p (XEXP (src, 0), reg) ++ && !rtx_equal_p (XEXP (src, 1), reg) ++ && reg_state[regno].use_index >= 0 ++ && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES ++ && last_label_ruid < reg_state[regno].use_ruid) ++ { ++ rtx base = XEXP (src, 1); ++ rtx prev = prev_nonnote_insn (insn); ++ rtx prev_set = prev ? single_set (prev) : NULL_RTX; ++ rtx index_reg = NULL_RTX; ++ rtx reg_sum = NULL_RTX; ++ int i; ++ ++ /* Now we need to set INDEX_REG to an index register (denoted as ++ REGZ in the illustration above) and REG_SUM to the expression ++ register+register that we want to use to substitute uses of REG ++ (typically in MEMs) with. First check REG and BASE for being ++ index registers; we can use them even if they are not dead. */ ++ if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) ++ || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], ++ REGNO (base))) ++ { ++ index_reg = reg; ++ reg_sum = src; ++ } ++ else ++ { ++ /* Otherwise, look for a free index register. Since we have ++ checked above that neither REG nor BASE are index registers, ++ if we find anything at all, it will be different from these ++ two registers. */ ++ for (i = first_index_reg; i <= last_index_reg; i++) ++ { ++ if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) ++ && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES ++ && reg_state[i].store_ruid <= reg_state[regno].use_ruid ++ && (call_used_regs[i] || df_regs_ever_live_p (i)) ++ && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM) ++ && !fixed_regs[i] && !global_regs[i] ++ && hard_regno_nregs[i][GET_MODE (reg)] == 1 ++ && targetm.hard_regno_scratch_ok (i)) ++ { ++ index_reg = gen_rtx_REG (GET_MODE (reg), i); ++ reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); ++ break; ++ } ++ } ++ } ++ ++ /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that ++ (REGY), i.e. BASE, is not clobbered before the last use we'll ++ create. */ ++ if (reg_sum ++ && prev_set ++ && CONST_INT_P (SET_SRC (prev_set)) ++ && rtx_equal_p (SET_DEST (prev_set), reg) ++ && (reg_state[REGNO (base)].store_ruid ++ <= reg_state[regno].use_ruid)) ++ { ++ /* Change destination register and, if necessary, the constant ++ value in PREV, the constant loading instruction. */ ++ validate_change (prev, &SET_DEST (prev_set), index_reg, 1); ++ if (reg_state[regno].offset != const0_rtx) ++ validate_change (prev, ++ &SET_SRC (prev_set), ++ GEN_INT (INTVAL (SET_SRC (prev_set)) ++ + INTVAL (reg_state[regno].offset)), ++ 1); ++ ++ /* Now for every use of REG that we have recorded, replace REG ++ with REG_SUM. */ ++ for (i = reg_state[regno].use_index; ++ i < RELOAD_COMBINE_MAX_USES; i++) ++ validate_unshare_change (reg_state[regno].reg_use[i].insn, ++ reg_state[regno].reg_use[i].usep, ++ /* Each change must have its own ++ replacement. */ ++ reg_sum, 1); ++ ++ if (apply_change_group ()) ++ { ++ struct reg_use *lowest_ruid = NULL; ++ ++ /* For every new use of REG_SUM, we have to record the use ++ of BASE therein, i.e. operand 1. */ ++ for (i = reg_state[regno].use_index; ++ i < RELOAD_COMBINE_MAX_USES; i++) ++ { ++ struct reg_use *use = reg_state[regno].reg_use + i; ++ reload_combine_note_use (&XEXP (*use->usep, 1), use->insn, ++ use->ruid, use->containing_mem); ++ if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid) ++ lowest_ruid = use; ++ } ++ ++ fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn); ++ ++ /* Delete the reg-reg addition. */ ++ delete_insn (insn); ++ ++ if (reg_state[regno].offset != const0_rtx) ++ /* Previous REG_EQUIV / REG_EQUAL notes for PREV ++ are now invalid. */ ++ remove_reg_equal_equiv_notes (prev); ++ ++ reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; ++ return true; ++ } ++ } ++ } ++ return false; ++} ++ + static void + reload_combine (void) + { +- rtx insn, set; +- int first_index_reg = -1; +- int last_index_reg = 0; ++ rtx insn, prev; + int i; + basic_block bb; + unsigned int r; +- int last_label_ruid; + int min_labelno, n_labels; + HARD_REG_SET ever_live_at_start, *label_live; + +- /* If reg+reg can be used in offsetable memory addresses, the main chunk of +- reload has already used it where appropriate, so there is no use in +- trying to generate it now. */ +- if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS) +- return; +- + /* To avoid wasting too much time later searching for an index register, + determine the minimum and maximum index register numbers. */ +- for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) +- if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) +- { +- if (first_index_reg == -1) +- first_index_reg = r; ++ if (INDEX_REG_CLASS == NO_REGS) ++ last_index_reg = -1; ++ else if (first_index_reg == -1 && last_index_reg == 0) ++ { ++ for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) ++ if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) ++ { ++ if (first_index_reg == -1) ++ first_index_reg = r; + +- last_index_reg = r; +- } ++ last_index_reg = r; ++ } + +- /* If no index register is available, we can quit now. */ +- if (first_index_reg == -1) +- return; ++ /* If no index register is available, we can quit now. Set LAST_INDEX_REG ++ to -1 so we'll know to quit early the next time we get here. */ ++ if (first_index_reg == -1) ++ { ++ last_index_reg = -1; ++ return; ++ } ++ } + + /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime + information is a bit fuzzy immediately after reload, but it's +@@ -753,20 +1278,23 @@ + } + + /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ +- last_label_ruid = reload_combine_ruid = 0; ++ last_label_ruid = last_jump_ruid = reload_combine_ruid = 0; + for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) + { +- reg_state[r].store_ruid = reload_combine_ruid; ++ reg_state[r].store_ruid = 0; ++ reg_state[r].real_store_ruid = 0; + if (fixed_regs[r]) + reg_state[r].use_index = -1; + else + reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; + } + +- for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) ++ for (insn = get_last_insn (); insn; insn = prev) + { + rtx note; + ++ prev = PREV_INSN (insn); ++ + /* We cannot do our optimization across labels. Invalidating all the use + information we have would be costly, so we just note where the label + is and then later disable any optimization that would cross it. */ +@@ -777,141 +1305,17 @@ + if (! fixed_regs[r]) + reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; + +- if (! INSN_P (insn)) ++ if (! NONDEBUG_INSN_P (insn)) + continue; + + reload_combine_ruid++; + +- /* Look for (set (REGX) (CONST_INT)) +- (set (REGX) (PLUS (REGX) (REGY))) +- ... +- ... (MEM (REGX)) ... +- and convert it to +- (set (REGZ) (CONST_INT)) +- ... +- ... (MEM (PLUS (REGZ) (REGY)))... . +- +- First, check that we have (set (REGX) (PLUS (REGX) (REGY))) +- and that we know all uses of REGX before it dies. +- Also, explicitly check that REGX != REGY; our life information +- does not yet show whether REGY changes in this insn. */ +- set = single_set (insn); +- if (set != NULL_RTX +- && REG_P (SET_DEST (set)) +- && (hard_regno_nregs[REGNO (SET_DEST (set))] +- [GET_MODE (SET_DEST (set))] +- == 1) +- && GET_CODE (SET_SRC (set)) == PLUS +- && REG_P (XEXP (SET_SRC (set), 1)) +- && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set)) +- && !rtx_equal_p (XEXP (SET_SRC (set), 1), SET_DEST (set)) +- && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid) +- { +- rtx reg = SET_DEST (set); +- rtx plus = SET_SRC (set); +- rtx base = XEXP (plus, 1); +- rtx prev = prev_nonnote_nondebug_insn (insn); +- rtx prev_set = prev ? single_set (prev) : NULL_RTX; +- unsigned int regno = REGNO (reg); +- rtx index_reg = NULL_RTX; +- rtx reg_sum = NULL_RTX; +- +- /* Now we need to set INDEX_REG to an index register (denoted as +- REGZ in the illustration above) and REG_SUM to the expression +- register+register that we want to use to substitute uses of REG +- (typically in MEMs) with. First check REG and BASE for being +- index registers; we can use them even if they are not dead. */ +- if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) +- || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], +- REGNO (base))) +- { +- index_reg = reg; +- reg_sum = plus; +- } +- else +- { +- /* Otherwise, look for a free index register. Since we have +- checked above that neither REG nor BASE are index registers, +- if we find anything at all, it will be different from these +- two registers. */ +- for (i = first_index_reg; i <= last_index_reg; i++) +- { +- if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], +- i) +- && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES +- && reg_state[i].store_ruid <= reg_state[regno].use_ruid +- && hard_regno_nregs[i][GET_MODE (reg)] == 1) +- { +- index_reg = gen_rtx_REG (GET_MODE (reg), i); +- reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); +- break; +- } +- } +- } +- +- /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that +- (REGY), i.e. BASE, is not clobbered before the last use we'll +- create. */ +- if (reg_sum +- && prev_set +- && CONST_INT_P (SET_SRC (prev_set)) +- && rtx_equal_p (SET_DEST (prev_set), reg) +- && reg_state[regno].use_index >= 0 +- && (reg_state[REGNO (base)].store_ruid +- <= reg_state[regno].use_ruid)) +- { +- int i; +- +- /* Change destination register and, if necessary, the constant +- value in PREV, the constant loading instruction. */ +- validate_change (prev, &SET_DEST (prev_set), index_reg, 1); +- if (reg_state[regno].offset != const0_rtx) +- validate_change (prev, +- &SET_SRC (prev_set), +- GEN_INT (INTVAL (SET_SRC (prev_set)) +- + INTVAL (reg_state[regno].offset)), +- 1); +- +- /* Now for every use of REG that we have recorded, replace REG +- with REG_SUM. */ +- for (i = reg_state[regno].use_index; +- i < RELOAD_COMBINE_MAX_USES; i++) +- validate_unshare_change (reg_state[regno].reg_use[i].insn, +- reg_state[regno].reg_use[i].usep, +- /* Each change must have its own +- replacement. */ +- reg_sum, 1); +- +- if (apply_change_group ()) +- { +- /* For every new use of REG_SUM, we have to record the use +- of BASE therein, i.e. operand 1. */ +- for (i = reg_state[regno].use_index; +- i < RELOAD_COMBINE_MAX_USES; i++) +- reload_combine_note_use +- (&XEXP (*reg_state[regno].reg_use[i].usep, 1), +- reg_state[regno].reg_use[i].insn); +- +- if (reg_state[REGNO (base)].use_ruid +- > reg_state[regno].use_ruid) +- reg_state[REGNO (base)].use_ruid +- = reg_state[regno].use_ruid; ++ if (control_flow_insn_p (insn)) ++ last_jump_ruid = reload_combine_ruid; + +- /* Delete the reg-reg addition. */ +- delete_insn (insn); +- +- if (reg_state[regno].offset != const0_rtx) +- /* Previous REG_EQUIV / REG_EQUAL notes for PREV +- are now invalid. */ +- remove_reg_equal_equiv_notes (prev); +- +- reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; +- reg_state[REGNO (index_reg)].store_ruid +- = reload_combine_ruid; +- continue; +- } +- } +- } ++ if (reload_combine_recognize_const_pattern (insn) ++ || reload_combine_recognize_pattern (insn)) ++ continue; + + note_stores (PATTERN (insn), reload_combine_note_store, NULL); + +@@ -967,7 +1371,8 @@ + reg_state[i].use_index = -1; + } + +- reload_combine_note_use (&PATTERN (insn), insn); ++ reload_combine_note_use (&PATTERN (insn), insn, ++ reload_combine_ruid, NULL_RTX); + for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) + { + if (REG_NOTE_KIND (note) == REG_INC +@@ -976,6 +1381,7 @@ + int regno = REGNO (XEXP (note, 0)); + + reg_state[regno].store_ruid = reload_combine_ruid; ++ reg_state[regno].real_store_ruid = reload_combine_ruid; + reg_state[regno].use_index = -1; + } + } +@@ -985,8 +1391,8 @@ + } + + /* Check if DST is a register or a subreg of a register; if it is, +- update reg_state[regno].store_ruid and reg_state[regno].use_index +- accordingly. Called via note_stores from reload_combine. */ ++ update store_ruid, real_store_ruid and use_index in the reg_state ++ structure accordingly. Called via note_stores from reload_combine. */ + + static void + reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) +@@ -1010,14 +1416,14 @@ + /* note_stores might have stripped a STRICT_LOW_PART, so we have to be + careful with registers / register parts that are not full words. + Similarly for ZERO_EXTRACT. */ +- if (GET_CODE (set) != SET +- || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT ++ if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT + || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) + { + for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) + { + reg_state[i].use_index = -1; + reg_state[i].store_ruid = reload_combine_ruid; ++ reg_state[i].real_store_ruid = reload_combine_ruid; + } + } + else +@@ -1025,6 +1431,8 @@ + for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) + { + reg_state[i].store_ruid = reload_combine_ruid; ++ if (GET_CODE (set) == SET) ++ reg_state[i].real_store_ruid = reload_combine_ruid; + reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; + } + } +@@ -1035,7 +1443,7 @@ + *XP is the pattern of INSN, or a part of it. + Called from reload_combine, and recursively by itself. */ + static void +-reload_combine_note_use (rtx *xp, rtx insn) ++reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem) + { + rtx x = *xp; + enum rtx_code code = x->code; +@@ -1048,7 +1456,7 @@ + case SET: + if (REG_P (SET_DEST (x))) + { +- reload_combine_note_use (&SET_SRC (x), insn); ++ reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX); + return; + } + break; +@@ -1104,6 +1512,11 @@ + return; + } + ++ /* We may be called to update uses in previously seen insns. ++ Don't add uses beyond the last store we saw. */ ++ if (ruid < reg_state[regno].store_ruid) ++ return; ++ + /* If this register is already used in some unknown fashion, we + can't do anything. + If we decrement the index from zero to -1, we can't store more +@@ -1112,29 +1525,34 @@ + if (use_index < 0) + return; + +- if (use_index != RELOAD_COMBINE_MAX_USES - 1) +- { +- /* We have found another use for a register that is already +- used later. Check if the offsets match; if not, mark the +- register as used in an unknown fashion. */ +- if (! rtx_equal_p (offset, reg_state[regno].offset)) +- { +- reg_state[regno].use_index = -1; +- return; +- } +- } +- else ++ if (use_index == RELOAD_COMBINE_MAX_USES - 1) + { + /* This is the first use of this register we have seen since we + marked it as dead. */ + reg_state[regno].offset = offset; +- reg_state[regno].use_ruid = reload_combine_ruid; ++ reg_state[regno].all_offsets_match = true; ++ reg_state[regno].use_ruid = ruid; + } ++ else ++ { ++ if (reg_state[regno].use_ruid > ruid) ++ reg_state[regno].use_ruid = ruid; ++ ++ if (! rtx_equal_p (offset, reg_state[regno].offset)) ++ reg_state[regno].all_offsets_match = false; ++ } ++ + reg_state[regno].reg_use[use_index].insn = insn; ++ reg_state[regno].reg_use[use_index].ruid = ruid; ++ reg_state[regno].reg_use[use_index].containing_mem = containing_mem; + reg_state[regno].reg_use[use_index].usep = xp; + return; + } + ++ case MEM: ++ containing_mem = x; ++ break; ++ + default: + break; + } +@@ -1144,11 +1562,12 @@ + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') +- reload_combine_note_use (&XEXP (x, i), insn); ++ reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem); + else if (fmt[i] == 'E') + { + for (j = XVECLEN (x, i) - 1; j >= 0; j--) +- reload_combine_note_use (&XVECEXP (x, i, j), insn); ++ reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid, ++ containing_mem); + } + } + } +@@ -1160,17 +1579,19 @@ + information about register contents we have would be costly, so we + use move2add_last_label_luid to note where the label is and then + later disable any optimization that would cross it. +- reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if +- reg_set_luid[n] is greater than move2add_last_label_luid. */ ++ reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n] ++ are only valid if reg_set_luid[n] is greater than ++ move2add_last_label_luid. */ + static int reg_set_luid[FIRST_PSEUDO_REGISTER]; + + /* If reg_base_reg[n] is negative, register n has been set to +- reg_offset[n] in mode reg_mode[n] . ++ reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n]. + If reg_base_reg[n] is non-negative, register n has been set to the + sum of reg_offset[n] and the value of register reg_base_reg[n] + before reg_set_luid[n], calculated in mode reg_mode[n] . */ + static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; + static int reg_base_reg[FIRST_PSEUDO_REGISTER]; ++static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER]; + static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; + + /* move2add_luid is linearly increased while scanning the instructions +@@ -1190,14 +1611,176 @@ + && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \ + GET_MODE_BITSIZE (INMODE)))) + +-static void ++/* This function is called with INSN that sets REG to (SYM + OFF), ++ while REG is known to already have value (SYM + offset). ++ This function tries to change INSN into an add instruction ++ (set (REG) (plus (REG) (OFF - offset))) using the known value. ++ It also updates the information about REG's known value. ++ Return true if we made a change. */ ++ ++static bool ++move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn) ++{ ++ rtx pat = PATTERN (insn); ++ rtx src = SET_SRC (pat); ++ int regno = REGNO (reg); ++ rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno], ++ GET_MODE (reg)); ++ bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); ++ bool changed = false; ++ ++ /* (set (reg) (plus (reg) (const_int 0))) is not canonical; ++ use (set (reg) (reg)) instead. ++ We don't delete this insn, nor do we convert it into a ++ note, to avoid losing register notes or the return ++ value flag. jump2 already knows how to get rid of ++ no-op moves. */ ++ if (new_src == const0_rtx) ++ { ++ /* If the constants are different, this is a ++ truncation, that, if turned into (set (reg) ++ (reg)), would be discarded. Maybe we should ++ try a truncMN pattern? */ ++ if (INTVAL (off) == reg_offset [regno]) ++ changed = validate_change (insn, &SET_SRC (pat), reg, 0); ++ } ++ else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed) ++ && have_add2_insn (reg, new_src)) ++ { ++ rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); ++ changed = validate_change (insn, &SET_SRC (pat), tem, 0); ++ } ++ else if (sym == NULL_RTX && GET_MODE (reg) != BImode) ++ { ++ enum machine_mode narrow_mode; ++ for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); ++ narrow_mode != VOIDmode ++ && narrow_mode != GET_MODE (reg); ++ narrow_mode = GET_MODE_WIDER_MODE (narrow_mode)) ++ { ++ if (have_insn_for (STRICT_LOW_PART, narrow_mode) ++ && ((reg_offset[regno] ++ & ~GET_MODE_MASK (narrow_mode)) ++ == (INTVAL (off) ++ & ~GET_MODE_MASK (narrow_mode)))) ++ { ++ rtx narrow_reg = gen_rtx_REG (narrow_mode, ++ REGNO (reg)); ++ rtx narrow_src = gen_int_mode (INTVAL (off), ++ narrow_mode); ++ rtx new_set = ++ gen_rtx_SET (VOIDmode, ++ gen_rtx_STRICT_LOW_PART (VOIDmode, ++ narrow_reg), ++ narrow_src); ++ changed = validate_change (insn, &PATTERN (insn), ++ new_set, 0); ++ if (changed) ++ break; ++ } ++ } ++ } ++ reg_set_luid[regno] = move2add_luid; ++ reg_base_reg[regno] = -1; ++ reg_mode[regno] = GET_MODE (reg); ++ reg_symbol_ref[regno] = sym; ++ reg_offset[regno] = INTVAL (off); ++ return changed; ++} ++ ++ ++/* This function is called with INSN that sets REG to (SYM + OFF), ++ but REG doesn't have known value (SYM + offset). This function ++ tries to find another register which is known to already have ++ value (SYM + offset) and change INSN into an add instruction ++ (set (REG) (plus (the found register) (OFF - offset))) if such ++ a register is found. It also updates the information about ++ REG's known value. ++ Return true iff we made a change. */ ++ ++static bool ++move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn) ++{ ++ rtx pat = PATTERN (insn); ++ rtx src = SET_SRC (pat); ++ int regno = REGNO (reg); ++ int min_cost = INT_MAX; ++ int min_regno; ++ bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); ++ int i; ++ bool changed = false; ++ ++ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) ++ if (reg_set_luid[i] > move2add_last_label_luid ++ && reg_mode[i] == GET_MODE (reg) ++ && reg_base_reg[i] < 0 ++ && reg_symbol_ref[i] != NULL_RTX ++ && rtx_equal_p (sym, reg_symbol_ref[i])) ++ { ++ rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i], ++ GET_MODE (reg)); ++ /* (set (reg) (plus (reg) (const_int 0))) is not canonical; ++ use (set (reg) (reg)) instead. ++ We don't delete this insn, nor do we convert it into a ++ note, to avoid losing register notes or the return ++ value flag. jump2 already knows how to get rid of ++ no-op moves. */ ++ if (new_src == const0_rtx) ++ { ++ min_cost = 0; ++ min_regno = i; ++ break; ++ } ++ else ++ { ++ int cost = rtx_cost (new_src, PLUS, speed); ++ if (cost < min_cost) ++ { ++ min_cost = cost; ++ min_regno = i; ++ } ++ } ++ } ++ ++ if (min_cost < rtx_cost (src, SET, speed)) ++ { ++ rtx tem; ++ ++ tem = gen_rtx_REG (GET_MODE (reg), min_regno); ++ if (i != min_regno) ++ { ++ rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno], ++ GET_MODE (reg)); ++ tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); ++ } ++ if (validate_change (insn, &SET_SRC (pat), tem, 0)) ++ changed = true; ++ } ++ reg_set_luid[regno] = move2add_luid; ++ reg_base_reg[regno] = -1; ++ reg_mode[regno] = GET_MODE (reg); ++ reg_symbol_ref[regno] = sym; ++ reg_offset[regno] = INTVAL (off); ++ return changed; ++} ++ ++/* Convert move insns with constant inputs to additions if they are cheaper. ++ Return true if any changes were made. */ ++static bool + reload_cse_move2add (rtx first) + { + int i; + rtx insn; ++ bool changed = false; + + for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) +- reg_set_luid[i] = 0; ++ { ++ reg_set_luid[i] = 0; ++ reg_offset[i] = 0; ++ reg_base_reg[i] = 0; ++ reg_symbol_ref[i] = NULL_RTX; ++ reg_mode[i] = VOIDmode; ++ } + + move2add_last_label_luid = 0; + move2add_luid = 2; +@@ -1245,65 +1828,11 @@ + (set (STRICT_LOW_PART (REGX)) (CONST_INT B)) + */ + +- if (CONST_INT_P (src) && reg_base_reg[regno] < 0) ++ if (CONST_INT_P (src) ++ && reg_base_reg[regno] < 0 ++ && reg_symbol_ref[regno] == NULL_RTX) + { +- rtx new_src = gen_int_mode (INTVAL (src) - reg_offset[regno], +- GET_MODE (reg)); +- bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); +- +- /* (set (reg) (plus (reg) (const_int 0))) is not canonical; +- use (set (reg) (reg)) instead. +- We don't delete this insn, nor do we convert it into a +- note, to avoid losing register notes or the return +- value flag. jump2 already knows how to get rid of +- no-op moves. */ +- if (new_src == const0_rtx) +- { +- /* If the constants are different, this is a +- truncation, that, if turned into (set (reg) +- (reg)), would be discarded. Maybe we should +- try a truncMN pattern? */ +- if (INTVAL (src) == reg_offset [regno]) +- validate_change (insn, &SET_SRC (pat), reg, 0); +- } +- else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed) +- && have_add2_insn (reg, new_src)) +- { +- rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); +- validate_change (insn, &SET_SRC (pat), tem, 0); +- } +- else if (GET_MODE (reg) != BImode) +- { +- enum machine_mode narrow_mode; +- for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); +- narrow_mode != VOIDmode +- && narrow_mode != GET_MODE (reg); +- narrow_mode = GET_MODE_WIDER_MODE (narrow_mode)) +- { +- if (have_insn_for (STRICT_LOW_PART, narrow_mode) +- && ((reg_offset[regno] +- & ~GET_MODE_MASK (narrow_mode)) +- == (INTVAL (src) +- & ~GET_MODE_MASK (narrow_mode)))) +- { +- rtx narrow_reg = gen_rtx_REG (narrow_mode, +- REGNO (reg)); +- rtx narrow_src = gen_int_mode (INTVAL (src), +- narrow_mode); +- rtx new_set = +- gen_rtx_SET (VOIDmode, +- gen_rtx_STRICT_LOW_PART (VOIDmode, +- narrow_reg), +- narrow_src); +- if (validate_change (insn, &PATTERN (insn), +- new_set, 0)) +- break; +- } +- } +- } +- reg_set_luid[regno] = move2add_luid; +- reg_mode[regno] = GET_MODE (reg); +- reg_offset[regno] = INTVAL (src); ++ changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn); + continue; + } + +@@ -1364,6 +1893,7 @@ + } + if (success) + delete_insn (insn); ++ changed |= success; + insn = next; + reg_mode[regno] = GET_MODE (reg); + reg_offset[regno] = +@@ -1373,6 +1903,51 @@ + } + } + } ++ ++ /* Try to transform ++ (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) ++ ... ++ (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B)))) ++ to ++ (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) ++ ... ++ (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */ ++ if ((GET_CODE (src) == SYMBOL_REF ++ || (GET_CODE (src) == CONST ++ && GET_CODE (XEXP (src, 0)) == PLUS ++ && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF ++ && CONST_INT_P (XEXP (XEXP (src, 0), 1)))) ++ && dbg_cnt (cse2_move2add)) ++ { ++ rtx sym, off; ++ ++ if (GET_CODE (src) == SYMBOL_REF) ++ { ++ sym = src; ++ off = const0_rtx; ++ } ++ else ++ { ++ sym = XEXP (XEXP (src, 0), 0); ++ off = XEXP (XEXP (src, 0), 1); ++ } ++ ++ /* If the reg already contains the value which is sum of ++ sym and some constant value, we can use an add2 insn. */ ++ if (reg_set_luid[regno] > move2add_last_label_luid ++ && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]) ++ && reg_base_reg[regno] < 0 ++ && reg_symbol_ref[regno] != NULL_RTX ++ && rtx_equal_p (sym, reg_symbol_ref[regno])) ++ changed |= move2add_use_add2_insn (reg, sym, off, insn); ++ ++ /* Otherwise, we have to find a register whose value is sum ++ of sym and some constant value. */ ++ else ++ changed |= move2add_use_add3_insn (reg, sym, off, insn); ++ ++ continue; ++ } + } + + for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) +@@ -1386,7 +1961,7 @@ + reg_set_luid[regno] = 0; + } + } +- note_stores (PATTERN (insn), move2add_note_store, NULL); ++ note_stores (PATTERN (insn), move2add_note_store, insn); + + /* If INSN is a conditional branch, we try to extract an + implicit set out of it. */ +@@ -1408,7 +1983,7 @@ + { + rtx implicit_set = + gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1)); +- move2add_note_store (SET_DEST (implicit_set), implicit_set, 0); ++ move2add_note_store (SET_DEST (implicit_set), implicit_set, insn); + } + } + +@@ -1424,15 +1999,18 @@ + } + } + } ++ return changed; + } + +-/* SET is a SET or CLOBBER that sets DST. ++/* SET is a SET or CLOBBER that sets DST. DATA is the insn which ++ contains SET. + Update reg_set_luid, reg_offset and reg_base_reg accordingly. + Called from reload_cse_move2add via note_stores. */ + + static void +-move2add_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) ++move2add_note_store (rtx dst, const_rtx set, void *data) + { ++ rtx insn = (rtx) data; + unsigned int regno = 0; + unsigned int nregs = 0; + unsigned int i; +@@ -1466,6 +2044,38 @@ + nregs = hard_regno_nregs[regno][mode]; + + if (SCALAR_INT_MODE_P (GET_MODE (dst)) ++ && nregs == 1 && GET_CODE (set) == SET) ++ { ++ rtx note, sym = NULL_RTX; ++ HOST_WIDE_INT off; ++ ++ note = find_reg_equal_equiv_note (insn); ++ if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) ++ { ++ sym = XEXP (note, 0); ++ off = 0; ++ } ++ else if (note && GET_CODE (XEXP (note, 0)) == CONST ++ && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS ++ && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF ++ && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1))) ++ { ++ sym = XEXP (XEXP (XEXP (note, 0), 0), 0); ++ off = INTVAL (XEXP (XEXP (XEXP (note, 0), 0), 1)); ++ } ++ ++ if (sym != NULL_RTX) ++ { ++ reg_base_reg[regno] = -1; ++ reg_symbol_ref[regno] = sym; ++ reg_offset[regno] = off; ++ reg_mode[regno] = mode; ++ reg_set_luid[regno] = move2add_luid; ++ return; ++ } ++ } ++ ++ if (SCALAR_INT_MODE_P (GET_MODE (dst)) + && nregs == 1 && GET_CODE (set) == SET + && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT + && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) +@@ -1493,15 +2103,17 @@ + && (MODES_OK_FOR_MOVE2ADD + (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))) + { +- if (reg_base_reg[REGNO (XEXP (src, 1))] < 0) ++ if (reg_base_reg[REGNO (XEXP (src, 1))] < 0 ++ && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX) + offset = reg_offset[REGNO (XEXP (src, 1))]; + /* Maybe the first register is known to be a + constant. */ + else if (reg_set_luid[REGNO (base_reg)] + > move2add_last_label_luid + && (MODES_OK_FOR_MOVE2ADD +- (dst_mode, reg_mode[REGNO (XEXP (src, 1))])) +- && reg_base_reg[REGNO (base_reg)] < 0) ++ (dst_mode, reg_mode[REGNO (base_reg)])) ++ && reg_base_reg[REGNO (base_reg)] < 0 ++ && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX) + { + offset = reg_offset[REGNO (base_reg)]; + base_reg = XEXP (src, 1); +@@ -1525,6 +2137,7 @@ + case CONST_INT: + /* Start tracking the register as a constant. */ + reg_base_reg[regno] = -1; ++ reg_symbol_ref[regno] = NULL_RTX; + reg_offset[regno] = INTVAL (SET_SRC (set)); + /* We assign the same luid to all registers set to constants. */ + reg_set_luid[regno] = move2add_last_label_luid + 1; +@@ -1545,6 +2158,7 @@ + if (reg_set_luid[base_regno] <= move2add_last_label_luid) + { + reg_base_reg[base_regno] = base_regno; ++ reg_symbol_ref[base_regno] = NULL_RTX; + reg_offset[base_regno] = 0; + reg_set_luid[base_regno] = move2add_luid; + reg_mode[base_regno] = mode; +@@ -1558,6 +2172,7 @@ + /* Copy base information from our base register. */ + reg_set_luid[regno] = reg_set_luid[base_regno]; + reg_base_reg[regno] = reg_base_reg[base_regno]; ++ reg_symbol_ref[regno] = reg_symbol_ref[base_regno]; + + /* Compute the sum of the offsets or constants. */ + reg_offset[regno] = trunc_int_for_mode (offset +--- a/src/gcc/print-rtl.c ++++ b/src/gcc/print-rtl.c +@@ -308,9 +308,16 @@ + } + } + else if (i == 8 && JUMP_P (in_rtx) && JUMP_LABEL (in_rtx) != NULL) +- /* Output the JUMP_LABEL reference. */ +- fprintf (outfile, "\n%s%*s -> %d", print_rtx_head, indent * 2, "", +- INSN_UID (JUMP_LABEL (in_rtx))); ++ { ++ /* Output the JUMP_LABEL reference. */ ++ fprintf (outfile, "\n%s%*s -> ", print_rtx_head, indent * 2, ""); ++ if (GET_CODE (JUMP_LABEL (in_rtx)) == RETURN) ++ fprintf (outfile, "return"); ++ else if (GET_CODE (JUMP_LABEL (in_rtx)) == SIMPLE_RETURN) ++ fprintf (outfile, "simple_return"); ++ else ++ fprintf (outfile, "%d", INSN_UID (JUMP_LABEL (in_rtx))); ++ } + else if (i == 0 && GET_CODE (in_rtx) == VALUE) + { + #ifndef GENERATOR_FILE +--- a/src/gcc/recog.c ++++ b/src/gcc/recog.c +@@ -31,10 +31,10 @@ + #include "hard-reg-set.h" + #include "recog.h" + #include "regs.h" +-#include "addresses.h" + #include "expr.h" + #include "function.h" + #include "flags.h" ++#include "addresses.h" + #include "real.h" + #include "toplev.h" + #include "basic-block.h" +@@ -2082,6 +2082,7 @@ + recog_data.operand_loc, + recog_data.constraints, + recog_data.operand_mode, NULL); ++ memset (recog_data.is_operator, 0, sizeof recog_data.is_operator); + if (noperands > 0) + { + const char *p = recog_data.constraints[0]; +@@ -2111,6 +2112,7 @@ + for (i = 0; i < noperands; i++) + { + recog_data.constraints[i] = insn_data[icode].operand[i].constraint; ++ recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator; + recog_data.operand_mode[i] = insn_data[icode].operand[i].mode; + /* VOIDmode match_operands gets mode from their real operand. */ + if (recog_data.operand_mode[i] == VOIDmode) +@@ -2909,6 +2911,10 @@ + + static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1]; + static int peep2_current; ++ ++static bool peep2_do_rebuild_jump_labels; ++static bool peep2_do_cleanup_cfg; ++ + /* The number of instructions available to match a peep2. */ + int peep2_current_count; + +@@ -2917,6 +2923,16 @@ + DF_LIVE_OUT for the block. */ + #define PEEP2_EOB pc_rtx + ++/* Wrap N to fit into the peep2_insn_data buffer. */ ++ ++static int ++peep2_buf_position (int n) ++{ ++ if (n >= MAX_INSNS_PER_PEEP2 + 1) ++ n -= MAX_INSNS_PER_PEEP2 + 1; ++ return n; ++} ++ + /* Return the Nth non-note insn after `current', or return NULL_RTX if it + does not exist. Used by the recognizer to find the next insn to match + in a multi-insn pattern. */ +@@ -2926,9 +2942,7 @@ + { + gcc_assert (n <= peep2_current_count); + +- n += peep2_current; +- if (n >= MAX_INSNS_PER_PEEP2 + 1) +- n -= MAX_INSNS_PER_PEEP2 + 1; ++ n = peep2_buf_position (peep2_current + n); + + return peep2_insn_data[n].insn; + } +@@ -2941,9 +2955,7 @@ + { + gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1); + +- ofs += peep2_current; +- if (ofs >= MAX_INSNS_PER_PEEP2 + 1) +- ofs -= MAX_INSNS_PER_PEEP2 + 1; ++ ofs = peep2_buf_position (peep2_current + ofs); + + gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX); + +@@ -2959,9 +2971,7 @@ + + gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1); + +- ofs += peep2_current; +- if (ofs >= MAX_INSNS_PER_PEEP2 + 1) +- ofs -= MAX_INSNS_PER_PEEP2 + 1; ++ ofs = peep2_buf_position (peep2_current + ofs); + + gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX); + +@@ -2996,12 +3006,8 @@ + gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1); + gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1); + +- from += peep2_current; +- if (from >= MAX_INSNS_PER_PEEP2 + 1) +- from -= MAX_INSNS_PER_PEEP2 + 1; +- to += peep2_current; +- if (to >= MAX_INSNS_PER_PEEP2 + 1) +- to -= MAX_INSNS_PER_PEEP2 + 1; ++ from = peep2_buf_position (peep2_current + from); ++ to = peep2_buf_position (peep2_current + to); + + gcc_assert (peep2_insn_data[from].insn != NULL_RTX); + REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before); +@@ -3010,8 +3016,7 @@ + { + HARD_REG_SET this_live; + +- if (++from >= MAX_INSNS_PER_PEEP2 + 1) +- from = 0; ++ from = peep2_buf_position (from + 1); + gcc_assert (peep2_insn_data[from].insn != NULL_RTX); + REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before); + IOR_HARD_REG_SET (live, this_live); +@@ -3104,19 +3109,234 @@ + COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live); + } + ++/* While scanning basic block BB, we found a match of length MATCH_LEN, ++ starting at INSN. Perform the replacement, removing the old insns and ++ replacing them with ATTEMPT. Returns the last insn emitted. */ ++ ++static rtx ++peep2_attempt (basic_block bb, rtx insn, int match_len, rtx attempt) ++{ ++ int i; ++ rtx last, note, before_try, x; ++ bool was_call = false; ++ ++ /* If we are splitting a CALL_INSN, look for the CALL_INSN ++ in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other ++ cfg-related call notes. */ ++ for (i = 0; i <= match_len; ++i) ++ { ++ int j; ++ rtx old_insn, new_insn, note; ++ ++ j = peep2_buf_position (peep2_current + i); ++ old_insn = peep2_insn_data[j].insn; ++ if (!CALL_P (old_insn)) ++ continue; ++ was_call = true; ++ ++ new_insn = attempt; ++ while (new_insn != NULL_RTX) ++ { ++ if (CALL_P (new_insn)) ++ break; ++ new_insn = NEXT_INSN (new_insn); ++ } ++ ++ gcc_assert (new_insn != NULL_RTX); ++ ++ CALL_INSN_FUNCTION_USAGE (new_insn) ++ = CALL_INSN_FUNCTION_USAGE (old_insn); ++ ++ for (note = REG_NOTES (old_insn); ++ note; ++ note = XEXP (note, 1)) ++ switch (REG_NOTE_KIND (note)) ++ { ++ case REG_NORETURN: ++ case REG_SETJMP: ++ add_reg_note (new_insn, REG_NOTE_KIND (note), ++ XEXP (note, 0)); ++ break; ++ default: ++ /* Discard all other reg notes. */ ++ break; ++ } ++ ++ /* Croak if there is another call in the sequence. */ ++ while (++i <= match_len) ++ { ++ j = peep2_buf_position (peep2_current + i); ++ old_insn = peep2_insn_data[j].insn; ++ gcc_assert (!CALL_P (old_insn)); ++ } ++ break; ++ } ++ ++ i = peep2_buf_position (peep2_current + match_len); ++ ++ note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX); ++ ++ /* Replace the old sequence with the new. */ ++ last = emit_insn_after_setloc (attempt, ++ peep2_insn_data[i].insn, ++ INSN_LOCATOR (peep2_insn_data[i].insn)); ++ before_try = PREV_INSN (insn); ++ delete_insn_chain (insn, peep2_insn_data[i].insn, false); ++ ++ /* Re-insert the EH_REGION notes. */ ++ if (note || (was_call && nonlocal_goto_handler_labels)) ++ { ++ edge eh_edge; ++ edge_iterator ei; ++ ++ FOR_EACH_EDGE (eh_edge, ei, bb->succs) ++ if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL)) ++ break; ++ ++ if (note) ++ copy_reg_eh_region_note_backward (note, last, before_try); ++ ++ if (eh_edge) ++ for (x = last; x != before_try; x = PREV_INSN (x)) ++ if (x != BB_END (bb) ++ && (can_throw_internal (x) ++ || can_nonlocal_goto (x))) ++ { ++ edge nfte, nehe; ++ int flags; ++ ++ nfte = split_block (bb, x); ++ flags = (eh_edge->flags ++ & (EDGE_EH | EDGE_ABNORMAL)); ++ if (CALL_P (x)) ++ flags |= EDGE_ABNORMAL_CALL; ++ nehe = make_edge (nfte->src, eh_edge->dest, ++ flags); ++ ++ nehe->probability = eh_edge->probability; ++ nfte->probability ++ = REG_BR_PROB_BASE - nehe->probability; ++ ++ peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest); ++ bb = nfte->src; ++ eh_edge = nehe; ++ } ++ ++ /* Converting possibly trapping insn to non-trapping is ++ possible. Zap dummy outgoing edges. */ ++ peep2_do_cleanup_cfg |= purge_dead_edges (bb); ++ } ++ ++ /* If we generated a jump instruction, it won't have ++ JUMP_LABEL set. Recompute after we're done. */ ++ for (x = last; x != before_try; x = PREV_INSN (x)) ++ if (JUMP_P (x)) ++ { ++ peep2_do_rebuild_jump_labels = true; ++ break; ++ } ++ ++ return last; ++} ++ ++/* After performing a replacement in basic block BB, fix up the life ++ information in our buffer. LAST is the last of the insns that we ++ emitted as a replacement. PREV is the insn before the start of ++ the replacement. MATCH_LEN is the number of instructions that were ++ matched, and which now need to be replaced in the buffer. */ ++ ++static void ++peep2_update_life (basic_block bb, int match_len, rtx last, rtx prev) ++{ ++ int i = peep2_buf_position (peep2_current + match_len + 1); ++ rtx x; ++ regset_head live; ++ ++ INIT_REG_SET (&live); ++ COPY_REG_SET (&live, peep2_insn_data[i].live_before); ++ ++ gcc_assert (peep2_current_count >= match_len + 1); ++ peep2_current_count -= match_len + 1; ++ ++ x = last; ++ do ++ { ++ if (INSN_P (x)) ++ { ++ df_insn_rescan (x); ++ if (peep2_current_count < MAX_INSNS_PER_PEEP2) ++ { ++ peep2_current_count++; ++ if (--i < 0) ++ i = MAX_INSNS_PER_PEEP2; ++ peep2_insn_data[i].insn = x; ++ df_simulate_one_insn_backwards (bb, x, &live); ++ COPY_REG_SET (peep2_insn_data[i].live_before, &live); ++ } ++ } ++ x = PREV_INSN (x); ++ } ++ while (x != prev); ++ CLEAR_REG_SET (&live); ++ ++ peep2_current = i; ++} ++ ++/* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible. ++ Return true if we added it, false otherwise. The caller will try to match ++ peepholes against the buffer if we return false; otherwise it will try to ++ add more instructions to the buffer. */ ++ ++static bool ++peep2_fill_buffer (basic_block bb, rtx insn, regset live) ++{ ++ int pos; ++ ++ /* Once we have filled the maximum number of insns the buffer can hold, ++ allow the caller to match the insns against peepholes. We wait until ++ the buffer is full in case the target has similar peepholes of different ++ length; we always want to match the longest if possible. */ ++ if (peep2_current_count == MAX_INSNS_PER_PEEP2) ++ return false; ++ ++ /* If an insn has RTX_FRAME_RELATED_P set, peephole substitution would lose ++ the REG_FRAME_RELATED_EXPR that is attached. */ ++ if (RTX_FRAME_RELATED_P (insn)) ++ { ++ /* Let the buffer drain first. */ ++ if (peep2_current_count > 0) ++ return false; ++ /* Step over the insn then return true without adding the insn ++ to the buffer; this will cause us to process the next ++ insn. */ ++ df_simulate_one_insn_forwards (bb, insn, live); ++ return true; ++ } ++ ++ pos = peep2_buf_position (peep2_current + peep2_current_count); ++ peep2_insn_data[pos].insn = insn; ++ COPY_REG_SET (peep2_insn_data[pos].live_before, live); ++ peep2_current_count++; ++ ++ df_simulate_one_insn_forwards (bb, insn, live); ++ return true; ++} ++ + /* Perform the peephole2 optimization pass. */ + + static void + peephole2_optimize (void) + { +- rtx insn, prev; ++ rtx insn; + bitmap live; + int i; + basic_block bb; +- bool do_cleanup_cfg = false; +- bool do_rebuild_jump_labels = false; ++ ++ peep2_do_cleanup_cfg = false; ++ peep2_do_rebuild_jump_labels = false; + + df_set_flags (DF_LR_RUN_DCE); ++ df_note_add_problem (); + df_analyze (); + + /* Initialize the regsets we're going to use. */ +@@ -3126,214 +3346,59 @@ + + FOR_EACH_BB_REVERSE (bb) + { ++ bool past_end = false; ++ int pos; ++ + rtl_profile_for_bb (bb); + + /* Start up propagation. */ +- bitmap_copy (live, DF_LR_OUT (bb)); +- df_simulate_initialize_backwards (bb, live); ++ bitmap_copy (live, DF_LR_IN (bb)); ++ df_simulate_initialize_forwards (bb, live); + peep2_reinit_state (live); + +- for (insn = BB_END (bb); ; insn = prev) ++ insn = BB_HEAD (bb); ++ for (;;) + { +- prev = PREV_INSN (insn); +- if (NONDEBUG_INSN_P (insn)) +- { +- rtx attempt, before_try, x; +- int match_len; +- rtx note; +- bool was_call = false; +- +- /* Record this insn. */ +- if (--peep2_current < 0) +- peep2_current = MAX_INSNS_PER_PEEP2; +- if (peep2_current_count < MAX_INSNS_PER_PEEP2 +- && peep2_insn_data[peep2_current].insn == NULL_RTX) +- peep2_current_count++; +- peep2_insn_data[peep2_current].insn = insn; +- df_simulate_one_insn_backwards (bb, insn, live); +- COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live); ++ rtx attempt, head; ++ int match_len; + +- if (RTX_FRAME_RELATED_P (insn)) +- { +- /* If an insn has RTX_FRAME_RELATED_P set, peephole +- substitution would lose the +- REG_FRAME_RELATED_EXPR that is attached. */ +- peep2_reinit_state (live); +- attempt = NULL; +- } +- else +- /* Match the peephole. */ +- attempt = peephole2_insns (PATTERN (insn), insn, &match_len); +- +- if (attempt != NULL) +- { +- /* If we are splitting a CALL_INSN, look for the CALL_INSN +- in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other +- cfg-related call notes. */ +- for (i = 0; i <= match_len; ++i) +- { +- int j; +- rtx old_insn, new_insn, note; +- +- j = i + peep2_current; +- if (j >= MAX_INSNS_PER_PEEP2 + 1) +- j -= MAX_INSNS_PER_PEEP2 + 1; +- old_insn = peep2_insn_data[j].insn; +- if (!CALL_P (old_insn)) +- continue; +- was_call = true; +- +- new_insn = attempt; +- while (new_insn != NULL_RTX) +- { +- if (CALL_P (new_insn)) +- break; +- new_insn = NEXT_INSN (new_insn); +- } +- +- gcc_assert (new_insn != NULL_RTX); +- +- CALL_INSN_FUNCTION_USAGE (new_insn) +- = CALL_INSN_FUNCTION_USAGE (old_insn); +- +- for (note = REG_NOTES (old_insn); +- note; +- note = XEXP (note, 1)) +- switch (REG_NOTE_KIND (note)) +- { +- case REG_NORETURN: +- case REG_SETJMP: +- add_reg_note (new_insn, REG_NOTE_KIND (note), +- XEXP (note, 0)); +- break; +- default: +- /* Discard all other reg notes. */ +- break; +- } +- +- /* Croak if there is another call in the sequence. */ +- while (++i <= match_len) +- { +- j = i + peep2_current; +- if (j >= MAX_INSNS_PER_PEEP2 + 1) +- j -= MAX_INSNS_PER_PEEP2 + 1; +- old_insn = peep2_insn_data[j].insn; +- gcc_assert (!CALL_P (old_insn)); +- } +- break; +- } +- +- i = match_len + peep2_current; +- if (i >= MAX_INSNS_PER_PEEP2 + 1) +- i -= MAX_INSNS_PER_PEEP2 + 1; +- +- note = find_reg_note (peep2_insn_data[i].insn, +- REG_EH_REGION, NULL_RTX); +- +- /* Replace the old sequence with the new. */ +- attempt = emit_insn_after_setloc (attempt, +- peep2_insn_data[i].insn, +- INSN_LOCATOR (peep2_insn_data[i].insn)); +- before_try = PREV_INSN (insn); +- delete_insn_chain (insn, peep2_insn_data[i].insn, false); +- +- /* Re-insert the EH_REGION notes. */ +- if (note || (was_call && nonlocal_goto_handler_labels)) +- { +- edge eh_edge; +- edge_iterator ei; +- +- FOR_EACH_EDGE (eh_edge, ei, bb->succs) +- if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL)) +- break; +- +- if (note) +- copy_reg_eh_region_note_backward (note, attempt, +- before_try); +- +- if (eh_edge) +- for (x = attempt ; x != before_try ; x = PREV_INSN (x)) +- if (x != BB_END (bb) +- && (can_throw_internal (x) +- || can_nonlocal_goto (x))) +- { +- edge nfte, nehe; +- int flags; +- +- nfte = split_block (bb, x); +- flags = (eh_edge->flags +- & (EDGE_EH | EDGE_ABNORMAL)); +- if (CALL_P (x)) +- flags |= EDGE_ABNORMAL_CALL; +- nehe = make_edge (nfte->src, eh_edge->dest, +- flags); +- +- nehe->probability = eh_edge->probability; +- nfte->probability +- = REG_BR_PROB_BASE - nehe->probability; +- +- do_cleanup_cfg |= purge_dead_edges (nfte->dest); +- bb = nfte->src; +- eh_edge = nehe; +- } +- +- /* Converting possibly trapping insn to non-trapping is +- possible. Zap dummy outgoing edges. */ +- do_cleanup_cfg |= purge_dead_edges (bb); +- } ++ if (!past_end && !NONDEBUG_INSN_P (insn)) ++ { ++ next_insn: ++ insn = NEXT_INSN (insn); ++ if (insn == NEXT_INSN (BB_END (bb))) ++ past_end = true; ++ continue; ++ } ++ if (!past_end && peep2_fill_buffer (bb, insn, live)) ++ goto next_insn; + +- if (targetm.have_conditional_execution ()) +- { +- for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) +- peep2_insn_data[i].insn = NULL_RTX; +- peep2_insn_data[peep2_current].insn = PEEP2_EOB; +- peep2_current_count = 0; +- } +- else +- { +- /* Back up lifetime information past the end of the +- newly created sequence. */ +- if (++i >= MAX_INSNS_PER_PEEP2 + 1) +- i = 0; +- bitmap_copy (live, peep2_insn_data[i].live_before); +- +- /* Update life information for the new sequence. */ +- x = attempt; +- do +- { +- if (INSN_P (x)) +- { +- if (--i < 0) +- i = MAX_INSNS_PER_PEEP2; +- if (peep2_current_count < MAX_INSNS_PER_PEEP2 +- && peep2_insn_data[i].insn == NULL_RTX) +- peep2_current_count++; +- peep2_insn_data[i].insn = x; +- df_insn_rescan (x); +- df_simulate_one_insn_backwards (bb, x, live); +- bitmap_copy (peep2_insn_data[i].live_before, +- live); +- } +- x = PREV_INSN (x); +- } +- while (x != prev); ++ /* If we did not fill an empty buffer, it signals the end of the ++ block. */ ++ if (peep2_current_count == 0) ++ break; + +- peep2_current = i; +- } ++ /* The buffer filled to the current maximum, so try to match. */ + +- /* If we generated a jump instruction, it won't have +- JUMP_LABEL set. Recompute after we're done. */ +- for (x = attempt; x != before_try; x = PREV_INSN (x)) +- if (JUMP_P (x)) +- { +- do_rebuild_jump_labels = true; +- break; +- } +- } ++ pos = peep2_buf_position (peep2_current + peep2_current_count); ++ peep2_insn_data[pos].insn = PEEP2_EOB; ++ COPY_REG_SET (peep2_insn_data[pos].live_before, live); ++ ++ /* Match the peephole. */ ++ head = peep2_insn_data[peep2_current].insn; ++ attempt = peephole2_insns (PATTERN (head), head, &match_len); ++ if (attempt != NULL) ++ { ++ rtx last; ++ last = peep2_attempt (bb, head, match_len, attempt); ++ peep2_update_life (bb, match_len, last, PREV_INSN (attempt)); ++ } ++ else ++ { ++ /* If no match, advance the buffer by one insn. */ ++ peep2_current = peep2_buf_position (peep2_current + 1); ++ peep2_current_count--; + } +- +- if (insn == BB_HEAD (bb)) +- break; + } + } + +@@ -3341,7 +3406,7 @@ + for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) + BITMAP_FREE (peep2_insn_data[i].live_before); + BITMAP_FREE (live); +- if (do_rebuild_jump_labels) ++ if (peep2_do_rebuild_jump_labels) + rebuild_jump_labels (get_insns ()); + } + #endif /* HAVE_peephole2 */ +--- a/src/gcc/recog.h ++++ b/src/gcc/recog.h +@@ -194,6 +194,9 @@ + /* Gives the constraint string for operand N. */ + const char *constraints[MAX_RECOG_OPERANDS]; + ++ /* Nonzero if operand N is a match_operator or a match_parallel. */ ++ char is_operator[MAX_RECOG_OPERANDS]; ++ + /* Gives the mode of operand N. */ + enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; + +@@ -260,6 +263,8 @@ + + const char strict_low; + ++ const char is_operator; ++ + const char eliminable; + }; + +--- a/src/gcc/regcprop.c ++++ b/src/gcc/regcprop.c +@@ -26,7 +26,6 @@ + #include "tm_p.h" + #include "insn-config.h" + #include "regs.h" +-#include "addresses.h" + #include "hard-reg-set.h" + #include "basic-block.h" + #include "reload.h" +@@ -34,6 +33,7 @@ + #include "function.h" + #include "recog.h" + #include "flags.h" ++#include "addresses.h" + #include "toplev.h" + #include "obstack.h" + #include "timevar.h" +--- a/src/gcc/reginfo.c ++++ b/src/gcc/reginfo.c +@@ -799,36 +799,41 @@ + fix_register (const char *name, int fixed, int call_used) + { + int i; ++ int reg, nregs; + + /* Decode the name and update the primary form of + the register info. */ + +- if ((i = decode_reg_name (name)) >= 0) ++ if ((reg = decode_reg_name_and_count (name, &nregs)) >= 0) + { +- if ((i == STACK_POINTER_REGNUM ++ gcc_assert (nregs >= 1); ++ for (i = reg; i < reg + nregs; i++) ++ { ++ if ((i == STACK_POINTER_REGNUM + #ifdef HARD_FRAME_POINTER_REGNUM +- || i == HARD_FRAME_POINTER_REGNUM ++ || i == HARD_FRAME_POINTER_REGNUM + #else +- || i == FRAME_POINTER_REGNUM ++ || i == FRAME_POINTER_REGNUM + #endif +- ) +- && (fixed == 0 || call_used == 0)) +- { +- static const char * const what_option[2][2] = { +- { "call-saved", "call-used" }, +- { "no-such-option", "fixed" }}; ++ ) ++ && (fixed == 0 || call_used == 0)) ++ { ++ static const char * const what_option[2][2] = { ++ { "call-saved", "call-used" }, ++ { "no-such-option", "fixed" }}; + +- error ("can't use '%s' as a %s register", name, +- what_option[fixed][call_used]); +- } +- else +- { +- fixed_regs[i] = fixed; +- call_used_regs[i] = call_used; ++ error ("can't use '%s' as a %s register", name, ++ what_option[fixed][call_used]); ++ } ++ else ++ { ++ fixed_regs[i] = fixed; ++ call_used_regs[i] = call_used; + #ifdef CALL_REALLY_USED_REGISTERS +- if (fixed == 0) +- call_really_used_regs[i] = call_used; ++ if (fixed == 0) ++ call_really_used_regs[i] = call_used; + #endif ++ } + } + } + else +--- a/src/gcc/regmove.c ++++ b/src/gcc/regmove.c +@@ -513,7 +513,7 @@ + rtx src_reg = XEXP (src, 0); + int src_no = REGNO (src_reg); + int dst_no = REGNO (dest); +- rtx p, set; ++ rtx p, set, set_insn; + enum machine_mode old_mode; + basic_block bb = BLOCK_FOR_INSN (insn); + +@@ -551,6 +551,7 @@ + GET_MODE_BITSIZE (GET_MODE (src_reg)))) + return; + ++ set_insn = p; + old_mode = GET_MODE (src_reg); + PUT_MODE (src_reg, GET_MODE (src)); + XEXP (src, 0) = SET_SRC (set); +@@ -583,9 +584,19 @@ + } + else + { +- rtx note = find_reg_note (p, REG_EQUAL, NULL_RTX); ++ rtx note = find_reg_note (set_insn, REG_EQUAL, NULL_RTX); + if (note) +- remove_note (p, note); ++ { ++ if (rtx_equal_p (XEXP (note, 0), XEXP (src, 0))) ++ { ++ XEXP (note, 0) ++ = gen_rtx_fmt_e (GET_CODE (src), GET_MODE (src), ++ XEXP (note, 0)); ++ df_notes_rescan (set_insn); ++ } ++ else ++ remove_note (set_insn, note); ++ } + } + } + +--- a/src/gcc/regrename.c ++++ b/src/gcc/regrename.c +@@ -26,7 +26,6 @@ + #include "tm_p.h" + #include "insn-config.h" + #include "regs.h" +-#include "addresses.h" + #include "hard-reg-set.h" + #include "basic-block.h" + #include "reload.h" +@@ -34,6 +33,7 @@ + #include "function.h" + #include "recog.h" + #include "flags.h" ++#include "addresses.h" + #include "toplev.h" + #include "obstack.h" + #include "timevar.h" +--- a/src/gcc/reload.c ++++ b/src/gcc/reload.c +@@ -3631,7 +3631,7 @@ + || modified[j] != RELOAD_WRITE) + && j != i + /* Ignore things like match_operator operands. */ +- && *recog_data.constraints[j] != 0 ++ && !recog_data.is_operator[j] + /* Don't count an input operand that is constrained to match + the early clobber operand. */ + && ! (this_alternative_matches[j] == i +--- a/src/gcc/reload.h ++++ b/src/gcc/reload.h +@@ -347,6 +347,10 @@ + extern rtx eliminate_regs (rtx, enum machine_mode, rtx); + extern bool elimination_target_reg_p (rtx); + ++/* Called from the register allocator to estimate costs of eliminating ++ invariant registers. */ ++extern void calculate_elim_costs_all_insns (void); ++ + /* Deallocate the reload register used by reload number R. */ + extern void deallocate_reload_reg (int r); + +--- a/src/gcc/reload1.c ++++ b/src/gcc/reload1.c +@@ -1,7 +1,7 @@ + /* Reload pseudo regs into hard regs for insns that require hard regs. + Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, +- 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +- Free Software Foundation, Inc. ++ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, ++ 2011 Free Software Foundation, Inc. + + This file is part of GCC. + +@@ -413,6 +413,7 @@ + static void set_label_offsets (rtx, rtx, int); + static void check_eliminable_occurrences (rtx); + static void elimination_effects (rtx, enum machine_mode); ++static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool); + static int eliminate_regs_in_insn (rtx, int); + static void update_eliminable_offsets (void); + static void mark_not_eliminable (rtx, const_rtx, void *); +@@ -420,8 +421,11 @@ + static bool verify_initial_elim_offsets (void); + static void set_initial_label_offsets (void); + static void set_offsets_for_label (rtx); ++static void init_eliminable_invariants (rtx, bool); + static void init_elim_table (void); ++static void free_reg_equiv (void); + static void update_eliminables (HARD_REG_SET *); ++static void elimination_costs_in_insn (rtx); + static void spill_hard_reg (unsigned int, int); + static int finish_spills (int); + static void scan_paradoxical_subregs (rtx); +@@ -697,6 +701,9 @@ + + /* Global variables used by reload and its subroutines. */ + ++/* The current basic block while in calculate_elim_costs_all_insns. */ ++static basic_block elim_bb; ++ + /* Set during calculate_needs if an insn needs register elimination. */ + static int something_needs_elimination; + /* Set during calculate_needs if an insn needs an operand changed. */ +@@ -775,22 +782,6 @@ + if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) + df_set_regs_ever_live (i, true); + +- /* Find all the pseudo registers that didn't get hard regs +- but do have known equivalent constants or memory slots. +- These include parameters (known equivalent to parameter slots) +- and cse'd or loop-moved constant memory addresses. +- +- Record constant equivalents in reg_equiv_constant +- so they will be substituted by find_reloads. +- Record memory equivalents in reg_mem_equiv so they can +- be substituted eventually by altering the REG-rtx's. */ +- +- reg_equiv_constant = XCNEWVEC (rtx, max_regno); +- reg_equiv_invariant = XCNEWVEC (rtx, max_regno); +- reg_equiv_mem = XCNEWVEC (rtx, max_regno); +- reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno); +- reg_equiv_address = XCNEWVEC (rtx, max_regno); +- reg_max_ref_width = XCNEWVEC (unsigned int, max_regno); + reg_old_renumber = XCNEWVEC (short, max_regno); + memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); + pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno); +@@ -798,115 +789,9 @@ + + CLEAR_HARD_REG_SET (bad_spill_regs_global); + +- /* Look for REG_EQUIV notes; record what each pseudo is equivalent +- to. Also find all paradoxical subregs and find largest such for +- each pseudo. */ +- +- num_eliminable_invariants = 0; +- for (insn = first; insn; insn = NEXT_INSN (insn)) +- { +- rtx set = single_set (insn); +- +- /* We may introduce USEs that we want to remove at the end, so +- we'll mark them with QImode. Make sure there are no +- previously-marked insns left by say regmove. */ +- if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE +- && GET_MODE (insn) != VOIDmode) +- PUT_MODE (insn, VOIDmode); +- +- if (NONDEBUG_INSN_P (insn)) +- scan_paradoxical_subregs (PATTERN (insn)); +- +- if (set != 0 && REG_P (SET_DEST (set))) +- { +- rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); +- rtx x; +- +- if (! note) +- continue; +- +- i = REGNO (SET_DEST (set)); +- x = XEXP (note, 0); +- +- if (i <= LAST_VIRTUAL_REGISTER) +- continue; +- +- if (! function_invariant_p (x) +- || ! flag_pic +- /* A function invariant is often CONSTANT_P but may +- include a register. We promise to only pass +- CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ +- || (CONSTANT_P (x) +- && LEGITIMATE_PIC_OPERAND_P (x))) +- { +- /* It can happen that a REG_EQUIV note contains a MEM +- that is not a legitimate memory operand. As later +- stages of reload assume that all addresses found +- in the reg_equiv_* arrays were originally legitimate, +- we ignore such REG_EQUIV notes. */ +- if (memory_operand (x, VOIDmode)) +- { +- /* Always unshare the equivalence, so we can +- substitute into this insn without touching the +- equivalence. */ +- reg_equiv_memory_loc[i] = copy_rtx (x); +- } +- else if (function_invariant_p (x)) +- { +- if (GET_CODE (x) == PLUS) +- { +- /* This is PLUS of frame pointer and a constant, +- and might be shared. Unshare it. */ +- reg_equiv_invariant[i] = copy_rtx (x); +- num_eliminable_invariants++; +- } +- else if (x == frame_pointer_rtx || x == arg_pointer_rtx) +- { +- reg_equiv_invariant[i] = x; +- num_eliminable_invariants++; +- } +- else if (LEGITIMATE_CONSTANT_P (x)) +- reg_equiv_constant[i] = x; +- else +- { +- reg_equiv_memory_loc[i] +- = force_const_mem (GET_MODE (SET_DEST (set)), x); +- if (! reg_equiv_memory_loc[i]) +- reg_equiv_init[i] = NULL_RTX; +- } +- } +- else +- { +- reg_equiv_init[i] = NULL_RTX; +- continue; +- } +- } +- else +- reg_equiv_init[i] = NULL_RTX; +- } +- } +- +- if (dump_file) +- for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) +- if (reg_equiv_init[i]) +- { +- fprintf (dump_file, "init_insns for %u: ", i); +- print_inline_rtx (dump_file, reg_equiv_init[i], 20); +- fprintf (dump_file, "\n"); +- } +- ++ init_eliminable_invariants (first, true); + init_elim_table (); + +- first_label_num = get_first_label_num (); +- num_labels = max_label_num () - first_label_num; +- +- /* Allocate the tables used to store offset information at labels. */ +- /* We used to use alloca here, but the size of what it would try to +- allocate would occasionally cause it to exceed the stack limit and +- cause a core dump. */ +- offsets_known_at = XNEWVEC (char, num_labels); +- offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT)); +- + /* Alter each pseudo-reg rtx to contain its hard reg number. Assign + stack slots to the pseudos that lack hard regs or equivalents. + Do not touch virtual registers. */ +@@ -1410,31 +1295,11 @@ + } + } + +- /* Indicate that we no longer have known memory locations or constants. */ +- if (reg_equiv_constant) +- free (reg_equiv_constant); +- if (reg_equiv_invariant) +- free (reg_equiv_invariant); +- reg_equiv_constant = 0; +- reg_equiv_invariant = 0; +- VEC_free (rtx, gc, reg_equiv_memory_loc_vec); +- reg_equiv_memory_loc = 0; +- + free (temp_pseudo_reg_arr); + +- if (offsets_known_at) +- free (offsets_known_at); +- if (offsets_at) +- free (offsets_at); +- +- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) +- if (reg_equiv_alt_mem_list[i]) +- free_EXPR_LIST_list (®_equiv_alt_mem_list[i]); +- free (reg_equiv_alt_mem_list); +- +- free (reg_equiv_mem); ++ /* Indicate that we no longer have known memory locations or constants. */ ++ free_reg_equiv (); + reg_equiv_init = 0; +- free (reg_equiv_address); + free (reg_max_ref_width); + free (reg_old_renumber); + free (pseudo_previous_regs); +@@ -1727,6 +1592,100 @@ + *pprev_reload = 0; + } + ++/* This function is called from the register allocator to set up estimates ++ for the cost of eliminating pseudos which have REG_EQUIV equivalences to ++ an invariant. The structure is similar to calculate_needs_all_insns. */ ++ ++void ++calculate_elim_costs_all_insns (void) ++{ ++ int *reg_equiv_init_cost; ++ basic_block bb; ++ int i; ++ ++ reg_equiv_init_cost = XCNEWVEC (int, max_regno); ++ init_elim_table (); ++ init_eliminable_invariants (get_insns (), false); ++ ++ set_initial_elim_offsets (); ++ set_initial_label_offsets (); ++ ++ FOR_EACH_BB (bb) ++ { ++ rtx insn; ++ elim_bb = bb; ++ ++ FOR_BB_INSNS (bb, insn) ++ { ++ /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might ++ include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see ++ what effects this has on the known offsets at labels. */ ++ ++ if (LABEL_P (insn) || JUMP_P (insn) ++ || (INSN_P (insn) && REG_NOTES (insn) != 0)) ++ set_label_offsets (insn, insn, 0); ++ ++ if (INSN_P (insn)) ++ { ++ rtx set = single_set (insn); ++ ++ /* Skip insns that only set an equivalence. */ ++ if (set && REG_P (SET_DEST (set)) ++ && reg_renumber[REGNO (SET_DEST (set))] < 0 ++ && (reg_equiv_constant[REGNO (SET_DEST (set))] ++ || (reg_equiv_invariant[REGNO (SET_DEST (set))]))) ++ { ++ unsigned regno = REGNO (SET_DEST (set)); ++ rtx init = reg_equiv_init[regno]; ++ if (init) ++ { ++ rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn, ++ false, true); ++ int cost = rtx_cost (t, SET, ++ optimize_bb_for_speed_p (bb)); ++ int freq = REG_FREQ_FROM_BB (bb); ++ ++ reg_equiv_init_cost[regno] = cost * freq; ++ continue; ++ } ++ } ++ /* If needed, eliminate any eliminable registers. */ ++ if (num_eliminable || num_eliminable_invariants) ++ elimination_costs_in_insn (insn); ++ ++ if (num_eliminable) ++ update_eliminable_offsets (); ++ } ++ } ++ } ++ for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) ++ { ++ if (reg_equiv_invariant[i]) ++ { ++ if (reg_equiv_init[i]) ++ { ++ int cost = reg_equiv_init_cost[i]; ++ if (dump_file) ++ fprintf (dump_file, ++ "Reg %d has equivalence, initial gains %d\n", i, cost); ++ if (cost != 0) ++ ira_adjust_equiv_reg_cost (i, cost); ++ } ++ else ++ { ++ if (dump_file) ++ fprintf (dump_file, ++ "Reg %d had equivalence, but can't be eliminated\n", ++ i); ++ ira_adjust_equiv_reg_cost (i, 0); ++ } ++ } ++ } ++ ++ free_reg_equiv (); ++ free (reg_equiv_init_cost); ++} ++ + /* Comparison function for qsort to decide which of two reloads + should be handled first. *P1 and *P2 are the reload numbers. */ + +@@ -2513,6 +2472,36 @@ + } + } + ++/* Called through for_each_rtx, this function examines every reg that occurs ++ in PX and adjusts the costs for its elimination which are gathered by IRA. ++ DATA is the insn in which PX occurs. We do not recurse into MEM ++ expressions. */ ++ ++static int ++note_reg_elim_costly (rtx *px, void *data) ++{ ++ rtx insn = (rtx)data; ++ rtx x = *px; ++ ++ if (MEM_P (x)) ++ return -1; ++ ++ if (REG_P (x) ++ && REGNO (x) >= FIRST_PSEUDO_REGISTER ++ && reg_equiv_init[REGNO (x)] ++ && reg_equiv_invariant[REGNO (x)]) ++ { ++ rtx t = reg_equiv_invariant[REGNO (x)]; ++ rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true); ++ int cost = rtx_cost (new_rtx, SET, optimize_bb_for_speed_p (elim_bb)); ++ int freq = REG_FREQ_FROM_BB (elim_bb); ++ ++ if (cost != 0) ++ ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq); ++ } ++ return 0; ++} ++ + /* Scan X and replace any eliminable registers (such as fp) with a + replacement (such as sp), plus an offset. + +@@ -2532,6 +2521,9 @@ + This means, do not set ref_outside_mem even if the reference + is outside of MEMs. + ++ If FOR_COSTS is true, we are being called before reload in order to ++ estimate the costs of keeping registers with an equivalence unallocated. ++ + REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had + replacements done assuming all offsets are at their initial values. If + they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we +@@ -2540,7 +2532,7 @@ + + static rtx + eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn, +- bool may_use_invariant) ++ bool may_use_invariant, bool for_costs) + { + enum rtx_code code = GET_CODE (x); + struct elim_table *ep; +@@ -2588,11 +2580,12 @@ + { + if (may_use_invariant || (insn && DEBUG_INSN_P (insn))) + return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]), +- mem_mode, insn, true); ++ mem_mode, insn, true, for_costs); + /* There exists at least one use of REGNO that cannot be + eliminated. Prevent the defining insn from being deleted. */ + reg_equiv_init[regno] = NULL_RTX; +- alter_reg (regno, -1, true); ++ if (!for_costs) ++ alter_reg (regno, -1, true); + } + return x; + +@@ -2653,8 +2646,10 @@ + operand of a load-address insn. */ + + { +- rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); +- rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); ++ rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true, ++ for_costs); ++ rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true, ++ for_costs); + + if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) + { +@@ -2728,9 +2723,11 @@ + case GE: case GT: case GEU: case GTU: + case LE: case LT: case LEU: case LTU: + { +- rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); ++ rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false, ++ for_costs); + rtx new1 = XEXP (x, 1) +- ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0; ++ ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false, ++ for_costs) : 0; + + if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) + return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); +@@ -2741,7 +2738,8 @@ + /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ + if (XEXP (x, 0)) + { +- new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); ++ new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true, ++ for_costs); + if (new_rtx != XEXP (x, 0)) + { + /* If this is a REG_DEAD note, it is not valid anymore. +@@ -2749,7 +2747,8 @@ + REG_DEAD note for the stack or frame pointer. */ + if (REG_NOTE_KIND (x) == REG_DEAD) + return (XEXP (x, 1) +- ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true) ++ ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true, ++ for_costs) + : NULL_RTX); + + x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1)); +@@ -2764,7 +2763,8 @@ + strictly needed, but it simplifies the code. */ + if (XEXP (x, 1)) + { +- new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); ++ new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true, ++ for_costs); + if (new_rtx != XEXP (x, 1)) + return + gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx); +@@ -2790,7 +2790,7 @@ + && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) + { + rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode, +- insn, true); ++ insn, true, for_costs); + + if (new_rtx != XEXP (XEXP (x, 1), 1)) + return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0), +@@ -2813,7 +2813,8 @@ + case POPCOUNT: + case PARITY: + case BSWAP: +- new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); ++ new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false, ++ for_costs); + if (new_rtx != XEXP (x, 0)) + return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx); + return x; +@@ -2834,7 +2835,8 @@ + new_rtx = SUBREG_REG (x); + } + else +- new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false); ++ new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, ++ for_costs); + + if (new_rtx != SUBREG_REG (x)) + { +@@ -2868,14 +2870,20 @@ + /* Our only special processing is to pass the mode of the MEM to our + recursive call and copy the flags. While we are here, handle this + case more efficiently. */ +- return +- replace_equiv_address_nv (x, +- eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), +- insn, true)); ++ ++ new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true, ++ for_costs); ++ if (for_costs ++ && memory_address_p (GET_MODE (x), XEXP (x, 0)) ++ && !memory_address_p (GET_MODE (x), new_rtx)) ++ for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn); ++ ++ return replace_equiv_address_nv (x, new_rtx); + + case USE: + /* Handle insn_list USE that a call to a pure function may generate. */ +- new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false); ++ new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false, ++ for_costs); + if (new_rtx != XEXP (x, 0)) + return gen_rtx_USE (GET_MODE (x), new_rtx); + return x; +@@ -2899,7 +2907,8 @@ + { + if (*fmt == 'e') + { +- new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false); ++ new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false, ++ for_costs); + if (new_rtx != XEXP (x, i) && ! copied) + { + x = shallow_copy_rtx (x); +@@ -2912,7 +2921,8 @@ + int copied_vec = 0; + for (j = 0; j < XVECLEN (x, i); j++) + { +- new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false); ++ new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false, ++ for_costs); + if (new_rtx != XVECEXP (x, i, j) && ! copied_vec) + { + rtvec new_v = gen_rtvec_v (XVECLEN (x, i), +@@ -2936,7 +2946,7 @@ + rtx + eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn) + { +- return eliminate_regs_1 (x, mem_mode, insn, false); ++ return eliminate_regs_1 (x, mem_mode, insn, false, false); + } + + /* Scan rtx X for modifications of elimination target registers. Update +@@ -3454,7 +3464,8 @@ + /* Companion to the above plus substitution, we can allow + invariants as the source of a plain move. */ + is_set_src = false; +- if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set)) ++ if (old_set ++ && recog_data.operand_loc[i] == &SET_SRC (old_set)) + is_set_src = true; + in_plus = false; + if (plus_src +@@ -3465,7 +3476,7 @@ + substed_operand[i] + = eliminate_regs_1 (recog_data.operand[i], VOIDmode, + replace ? insn : NULL_RTX, +- is_set_src || in_plus); ++ is_set_src || in_plus, false); + if (substed_operand[i] != orig_operand[i]) + val = 1; + /* Terminate the search in check_eliminable_occurrences at +@@ -3556,7 +3567,10 @@ + { + /* Restore the old body. */ + for (i = 0; i < recog_data.n_operands; i++) +- *recog_data.operand_loc[i] = orig_operand[i]; ++ /* Restoring a top-level match_parallel would clobber the new_body ++ we installed in the insn. */ ++ if (recog_data.operand_loc[i] != &PATTERN (insn)) ++ *recog_data.operand_loc[i] = orig_operand[i]; + for (i = 0; i < recog_data.n_dups; i++) + *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; + } +@@ -3593,11 +3607,167 @@ + the pre-passes. */ + if (val && REG_NOTES (insn) != 0) + REG_NOTES (insn) +- = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true); ++ = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true, ++ false); + + return val; + } + ++/* Like eliminate_regs_in_insn, but only estimate costs for the use of the ++ register allocator. INSN is the instruction we need to examine, we perform ++ eliminations in its operands and record cases where eliminating a reg with ++ an invariant equivalence would add extra cost. */ ++ ++static void ++elimination_costs_in_insn (rtx insn) ++{ ++ int icode = recog_memoized (insn); ++ rtx old_body = PATTERN (insn); ++ int insn_is_asm = asm_noperands (old_body) >= 0; ++ rtx old_set = single_set (insn); ++ int i; ++ rtx orig_operand[MAX_RECOG_OPERANDS]; ++ rtx orig_dup[MAX_RECOG_OPERANDS]; ++ struct elim_table *ep; ++ rtx plus_src, plus_cst_src; ++ bool sets_reg_p; ++ ++ if (! insn_is_asm && icode < 0) ++ { ++ gcc_assert (GET_CODE (PATTERN (insn)) == USE ++ || GET_CODE (PATTERN (insn)) == CLOBBER ++ || GET_CODE (PATTERN (insn)) == ADDR_VEC ++ || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC ++ || GET_CODE (PATTERN (insn)) == ASM_INPUT ++ || DEBUG_INSN_P (insn)); ++ return; ++ } ++ ++ if (old_set != 0 && REG_P (SET_DEST (old_set)) ++ && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) ++ { ++ /* Check for setting an eliminable register. */ ++ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) ++ if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) ++ return; ++ } ++ ++ /* We allow one special case which happens to work on all machines we ++ currently support: a single set with the source or a REG_EQUAL ++ note being a PLUS of an eliminable register and a constant. */ ++ plus_src = plus_cst_src = 0; ++ sets_reg_p = false; ++ if (old_set && REG_P (SET_DEST (old_set))) ++ { ++ sets_reg_p = true; ++ if (GET_CODE (SET_SRC (old_set)) == PLUS) ++ plus_src = SET_SRC (old_set); ++ /* First see if the source is of the form (plus (...) CST). */ ++ if (plus_src ++ && CONST_INT_P (XEXP (plus_src, 1))) ++ plus_cst_src = plus_src; ++ else if (REG_P (SET_SRC (old_set)) ++ || plus_src) ++ { ++ /* Otherwise, see if we have a REG_EQUAL note of the form ++ (plus (...) CST). */ ++ rtx links; ++ for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) ++ { ++ if ((REG_NOTE_KIND (links) == REG_EQUAL ++ || REG_NOTE_KIND (links) == REG_EQUIV) ++ && GET_CODE (XEXP (links, 0)) == PLUS ++ && CONST_INT_P (XEXP (XEXP (links, 0), 1))) ++ { ++ plus_cst_src = XEXP (links, 0); ++ break; ++ } ++ } ++ } ++ } ++ ++ /* Determine the effects of this insn on elimination offsets. */ ++ elimination_effects (old_body, VOIDmode); ++ ++ /* Eliminate all eliminable registers occurring in operands that ++ can be handled by reload. */ ++ extract_insn (insn); ++ for (i = 0; i < recog_data.n_dups; i++) ++ orig_dup[i] = *recog_data.dup_loc[i]; ++ ++ for (i = 0; i < recog_data.n_operands; i++) ++ { ++ orig_operand[i] = recog_data.operand[i]; ++ ++ /* For an asm statement, every operand is eliminable. */ ++ if (insn_is_asm || insn_data[icode].operand[i].eliminable) ++ { ++ bool is_set_src, in_plus; ++ ++ /* Check for setting a register that we know about. */ ++ if (recog_data.operand_type[i] != OP_IN ++ && REG_P (orig_operand[i])) ++ { ++ /* If we are assigning to a register that can be eliminated, it ++ must be as part of a PARALLEL, since the code above handles ++ single SETs. We must indicate that we can no longer ++ eliminate this reg. */ ++ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ++ ep++) ++ if (ep->from_rtx == orig_operand[i]) ++ ep->can_eliminate = 0; ++ } ++ ++ /* Companion to the above plus substitution, we can allow ++ invariants as the source of a plain move. */ ++ is_set_src = false; ++ if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set)) ++ is_set_src = true; ++ if (is_set_src && !sets_reg_p) ++ note_reg_elim_costly (&SET_SRC (old_set), insn); ++ in_plus = false; ++ if (plus_src && sets_reg_p ++ && (recog_data.operand_loc[i] == &XEXP (plus_src, 0) ++ || recog_data.operand_loc[i] == &XEXP (plus_src, 1))) ++ in_plus = true; ++ ++ eliminate_regs_1 (recog_data.operand[i], VOIDmode, ++ NULL_RTX, ++ is_set_src || in_plus, true); ++ /* Terminate the search in check_eliminable_occurrences at ++ this point. */ ++ *recog_data.operand_loc[i] = 0; ++ } ++ } ++ ++ for (i = 0; i < recog_data.n_dups; i++) ++ *recog_data.dup_loc[i] ++ = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; ++ ++ /* If any eliminable remain, they aren't eliminable anymore. */ ++ check_eliminable_occurrences (old_body); ++ ++ /* Restore the old body. */ ++ for (i = 0; i < recog_data.n_operands; i++) ++ *recog_data.operand_loc[i] = orig_operand[i]; ++ for (i = 0; i < recog_data.n_dups; i++) ++ *recog_data.dup_loc[i] = orig_dup[i]; ++ ++ /* Update all elimination pairs to reflect the status after the current ++ insn. The changes we make were determined by the earlier call to ++ elimination_effects. */ ++ ++ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) ++ { ++ if (ep->previous_offset != ep->offset && ep->ref_outside_mem) ++ ep->can_eliminate = 0; ++ ++ ep->ref_outside_mem = 0; ++ } ++ ++ return; ++} ++ + /* Loop through all elimination pairs. + Recalculate the number not at initial offset. + +@@ -3907,6 +4077,168 @@ + ep->to_rtx = gen_rtx_REG (Pmode, ep->to); + } + } ++ ++/* Find all the pseudo registers that didn't get hard regs ++ but do have known equivalent constants or memory slots. ++ These include parameters (known equivalent to parameter slots) ++ and cse'd or loop-moved constant memory addresses. ++ ++ Record constant equivalents in reg_equiv_constant ++ so they will be substituted by find_reloads. ++ Record memory equivalents in reg_mem_equiv so they can ++ be substituted eventually by altering the REG-rtx's. */ ++ ++static void ++init_eliminable_invariants (rtx first, bool do_subregs) ++{ ++ int i; ++ rtx insn; ++ ++ reg_equiv_constant = XCNEWVEC (rtx, max_regno); ++ reg_equiv_invariant = XCNEWVEC (rtx, max_regno); ++ reg_equiv_mem = XCNEWVEC (rtx, max_regno); ++ reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno); ++ reg_equiv_address = XCNEWVEC (rtx, max_regno); ++ if (do_subregs) ++ reg_max_ref_width = XCNEWVEC (unsigned int, max_regno); ++ else ++ reg_max_ref_width = NULL; ++ ++ num_eliminable_invariants = 0; ++ ++ first_label_num = get_first_label_num (); ++ num_labels = max_label_num () - first_label_num; ++ ++ /* Allocate the tables used to store offset information at labels. */ ++ offsets_known_at = XNEWVEC (char, num_labels); ++ offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT)); ++ ++/* Look for REG_EQUIV notes; record what each pseudo is equivalent ++ to. If DO_SUBREGS is true, also find all paradoxical subregs and ++ find largest such for each pseudo. FIRST is the head of the insn ++ list. */ ++ ++ for (insn = first; insn; insn = NEXT_INSN (insn)) ++ { ++ rtx set = single_set (insn); ++ ++ /* We may introduce USEs that we want to remove at the end, so ++ we'll mark them with QImode. Make sure there are no ++ previously-marked insns left by say regmove. */ ++ if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE ++ && GET_MODE (insn) != VOIDmode) ++ PUT_MODE (insn, VOIDmode); ++ ++ if (do_subregs && NONDEBUG_INSN_P (insn)) ++ scan_paradoxical_subregs (PATTERN (insn)); ++ ++ if (set != 0 && REG_P (SET_DEST (set))) ++ { ++ rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); ++ rtx x; ++ ++ if (! note) ++ continue; ++ ++ i = REGNO (SET_DEST (set)); ++ x = XEXP (note, 0); ++ ++ if (i <= LAST_VIRTUAL_REGISTER) ++ continue; ++ ++ /* If flag_pic and we have constant, verify it's legitimate. */ ++ if (!CONSTANT_P (x) ++ || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x)) ++ { ++ /* It can happen that a REG_EQUIV note contains a MEM ++ that is not a legitimate memory operand. As later ++ stages of reload assume that all addresses found ++ in the reg_equiv_* arrays were originally legitimate, ++ we ignore such REG_EQUIV notes. */ ++ if (memory_operand (x, VOIDmode)) ++ { ++ /* Always unshare the equivalence, so we can ++ substitute into this insn without touching the ++ equivalence. */ ++ reg_equiv_memory_loc[i] = copy_rtx (x); ++ } ++ else if (function_invariant_p (x)) ++ { ++ if (GET_CODE (x) == PLUS) ++ { ++ /* This is PLUS of frame pointer and a constant, ++ and might be shared. Unshare it. */ ++ reg_equiv_invariant[i] = copy_rtx (x); ++ num_eliminable_invariants++; ++ } ++ else if (x == frame_pointer_rtx || x == arg_pointer_rtx) ++ { ++ reg_equiv_invariant[i] = x; ++ num_eliminable_invariants++; ++ } ++ else if (LEGITIMATE_CONSTANT_P (x)) ++ reg_equiv_constant[i] = x; ++ else ++ { ++ reg_equiv_memory_loc[i] ++ = force_const_mem (GET_MODE (SET_DEST (set)), x); ++ if (! reg_equiv_memory_loc[i]) ++ reg_equiv_init[i] = NULL_RTX; ++ } ++ } ++ else ++ { ++ reg_equiv_init[i] = NULL_RTX; ++ continue; ++ } ++ } ++ else ++ reg_equiv_init[i] = NULL_RTX; ++ } ++ } ++ ++ if (dump_file) ++ for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) ++ if (reg_equiv_init[i]) ++ { ++ fprintf (dump_file, "init_insns for %u: ", i); ++ print_inline_rtx (dump_file, reg_equiv_init[i], 20); ++ fprintf (dump_file, "\n"); ++ } ++} ++ ++/* Indicate that we no longer have known memory locations or constants. ++ Free all data involved in tracking these. */ ++ ++static void ++free_reg_equiv (void) ++{ ++ int i; ++ ++ if (reg_equiv_constant) ++ free (reg_equiv_constant); ++ if (reg_equiv_invariant) ++ free (reg_equiv_invariant); ++ reg_equiv_constant = 0; ++ reg_equiv_invariant = 0; ++ VEC_free (rtx, gc, reg_equiv_memory_loc_vec); ++ reg_equiv_memory_loc = 0; ++ ++ if (offsets_known_at) ++ free (offsets_known_at); ++ if (offsets_at) ++ free (offsets_at); ++ offsets_at = 0; ++ offsets_known_at = 0; ++ ++ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) ++ if (reg_equiv_alt_mem_list[i]) ++ free_EXPR_LIST_list (®_equiv_alt_mem_list[i]); ++ free (reg_equiv_alt_mem_list); ++ ++ free (reg_equiv_mem); ++ free (reg_equiv_address); ++} + + /* Kick all pseudos out of hard register REGNO. + +@@ -5657,7 +5989,7 @@ + return 1; + if (GET_CODE (x) == PLUS + && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) +- && CONSTANT_P (XEXP (x, 1))) ++ && GET_CODE (XEXP (x, 1)) == CONST_INT) + return 1; + return 0; + } +@@ -6266,17 +6598,6 @@ + && (rld[r].nregs == max_group_size + || ! reg_classes_intersect_p (rld[r].rclass, group_class))) + search_equiv = rld[r].in; +- /* If this is an output reload from a simple move insn, look +- if an equivalence for the input is available. */ +- else if (inheritance && rld[r].in == 0 && rld[r].out != 0) +- { +- rtx set = single_set (insn); +- +- if (set +- && rtx_equal_p (rld[r].out, SET_DEST (set)) +- && CONSTANT_P (SET_SRC (set))) +- search_equiv = SET_SRC (set); +- } + + if (search_equiv) + { +@@ -7759,10 +8080,22 @@ + /* Maybe the spill reg contains a copy of reload_out. */ + if (rld[r].out != 0 + && (REG_P (rld[r].out) +-#ifdef AUTO_INC_DEC +- || ! rld[r].out_reg +-#endif +- || REG_P (rld[r].out_reg))) ++ || (rld[r].out_reg ++ ? REG_P (rld[r].out_reg) ++ /* The reload value is an auto-modification of ++ some kind. For PRE_INC, POST_INC, PRE_DEC ++ and POST_DEC, we record an equivalence ++ between the reload register and the operand ++ on the optimistic assumption that we can make ++ the equivalence hold. reload_as_needed must ++ then either make it hold or invalidate the ++ equivalence. ++ ++ PRE_MODIFY and POST_MODIFY addresses are reloaded ++ somewhat differently, and allowing them here leads ++ to problems. */ ++ : (GET_CODE (rld[r].out) != POST_MODIFY ++ && GET_CODE (rld[r].out) != PRE_MODIFY)))) + { + rtx reg; + enum machine_mode mode; +@@ -8706,7 +9039,7 @@ + be used as an address. */ + + if (! post) +- emit_insn (gen_move_insn (reloadreg, incloc)); ++ add_insn = emit_insn (gen_move_insn (reloadreg, incloc)); + + return add_insn; + } +--- a/src/gcc/reorg.c ++++ b/src/gcc/reorg.c +@@ -161,8 +161,11 @@ + #define unfilled_slots_next \ + ((rtx *) obstack_next_free (&unfilled_slots_obstack)) + +-/* Points to the label before the end of the function. */ +-static rtx end_of_function_label; ++/* Points to the label before the end of the function, or before a ++ return insn. */ ++static rtx function_return_label; ++/* Likewise for a simple_return. */ ++static rtx function_simple_return_label; + + /* Mapping between INSN_UID's and position in the code since INSN_UID's do + not always monotonically increase. */ +@@ -175,7 +178,7 @@ + static int resource_conflicts_p (struct resources *, struct resources *); + static int insn_references_resource_p (rtx, struct resources *, bool); + static int insn_sets_resource_p (rtx, struct resources *, bool); +-static rtx find_end_label (void); ++static rtx find_end_label (rtx); + static rtx emit_delay_sequence (rtx, rtx, int); + static rtx add_to_delay_list (rtx, rtx); + static rtx delete_from_delay_slot (rtx); +@@ -220,6 +223,15 @@ + static void make_return_insns (rtx); + #endif + ++/* Return true iff INSN is a simplejump, or any kind of return insn. */ ++ ++static bool ++simplejump_or_return_p (rtx insn) ++{ ++ return (JUMP_P (insn) ++ && (simplejump_p (insn) || ANY_RETURN_P (PATTERN (insn)))); ++} ++ + /* Return TRUE if this insn should stop the search for insn to fill delay + slots. LABELS_P indicates that labels should terminate the search. + In all cases, jumps terminate the search. */ +@@ -335,23 +347,29 @@ + + ??? There may be a problem with the current implementation. Suppose + we start with a bare RETURN insn and call find_end_label. It may set +- end_of_function_label just before the RETURN. Suppose the machinery ++ function_return_label just before the RETURN. Suppose the machinery + is able to fill the delay slot of the RETURN insn afterwards. Then +- end_of_function_label is no longer valid according to the property ++ function_return_label is no longer valid according to the property + described above and find_end_label will still return it unmodified. + Note that this is probably mitigated by the following observation: +- once end_of_function_label is made, it is very likely the target of ++ once function_return_label is made, it is very likely the target of + a jump, so filling the delay slot of the RETURN will be much more + difficult. */ + + static rtx +-find_end_label (void) ++find_end_label (rtx kind) + { + rtx insn; ++ rtx *plabel; ++ ++ if (kind == ret_rtx) ++ plabel = &function_return_label; ++ else ++ plabel = &function_simple_return_label; + + /* If we found one previously, return it. */ +- if (end_of_function_label) +- return end_of_function_label; ++ if (*plabel) ++ return *plabel; + + /* Otherwise, see if there is a label at the end of the function. If there + is, it must be that RETURN insns aren't needed, so that is our return +@@ -366,44 +384,44 @@ + + /* When a target threads its epilogue we might already have a + suitable return insn. If so put a label before it for the +- end_of_function_label. */ ++ function_return_label. */ + if (BARRIER_P (insn) + && JUMP_P (PREV_INSN (insn)) +- && GET_CODE (PATTERN (PREV_INSN (insn))) == RETURN) ++ && PATTERN (PREV_INSN (insn)) == kind) + { + rtx temp = PREV_INSN (PREV_INSN (insn)); +- end_of_function_label = gen_label_rtx (); +- LABEL_NUSES (end_of_function_label) = 0; ++ rtx label = gen_label_rtx (); ++ LABEL_NUSES (label) = 0; + + /* Put the label before an USE insns that may precede the RETURN insn. */ + while (GET_CODE (temp) == USE) + temp = PREV_INSN (temp); + +- emit_label_after (end_of_function_label, temp); ++ emit_label_after (label, temp); ++ *plabel = label; + } + + else if (LABEL_P (insn)) +- end_of_function_label = insn; ++ *plabel = insn; + else + { +- end_of_function_label = gen_label_rtx (); +- LABEL_NUSES (end_of_function_label) = 0; ++ rtx label = gen_label_rtx (); ++ LABEL_NUSES (label) = 0; + /* If the basic block reorder pass moves the return insn to + some other place try to locate it again and put our +- end_of_function_label there. */ +- while (insn && ! (JUMP_P (insn) +- && (GET_CODE (PATTERN (insn)) == RETURN))) ++ function_return_label there. */ ++ while (insn && ! (JUMP_P (insn) && (PATTERN (insn) == kind))) + insn = PREV_INSN (insn); + if (insn) + { + insn = PREV_INSN (insn); + +- /* Put the label before an USE insns that may proceed the ++ /* Put the label before an USE insns that may precede the + RETURN insn. */ + while (GET_CODE (insn) == USE) + insn = PREV_INSN (insn); + +- emit_label_after (end_of_function_label, insn); ++ emit_label_after (label, insn); + } + else + { +@@ -413,19 +431,16 @@ + && ! HAVE_return + #endif + ) +- { +- /* The RETURN insn has its delay slot filled so we cannot +- emit the label just before it. Since we already have +- an epilogue and cannot emit a new RETURN, we cannot +- emit the label at all. */ +- end_of_function_label = NULL_RTX; +- return end_of_function_label; +- } ++ /* The RETURN insn has its delay slot filled so we cannot ++ emit the label just before it. Since we already have ++ an epilogue and cannot emit a new RETURN, we cannot ++ emit the label at all. */ ++ return NULL_RTX; + #endif /* HAVE_epilogue */ + + /* Otherwise, make a new label and emit a RETURN and BARRIER, + if needed. */ +- emit_label (end_of_function_label); ++ emit_label (label); + #ifdef HAVE_return + /* We don't bother trying to create a return insn if the + epilogue has filled delay-slots; we would have to try and +@@ -437,19 +452,21 @@ + /* The return we make may have delay slots too. */ + rtx insn = gen_return (); + insn = emit_jump_insn (insn); ++ JUMP_LABEL (insn) = ret_rtx; + emit_barrier (); + if (num_delay_slots (insn) > 0) + obstack_ptr_grow (&unfilled_slots_obstack, insn); + } + #endif + } ++ *plabel = label; + } + + /* Show one additional use for this label so it won't go away until + we are done. */ +- ++LABEL_NUSES (end_of_function_label); ++ ++LABEL_NUSES (*plabel); + +- return end_of_function_label; ++ return *plabel; + } + + /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace +@@ -797,10 +814,8 @@ + if ((next_trial == next_active_insn (JUMP_LABEL (insn)) + && ! (next_trial == 0 && crtl->epilogue_delay_list != 0)) + || (next_trial != 0 +- && JUMP_P (next_trial) +- && JUMP_LABEL (insn) == JUMP_LABEL (next_trial) +- && (simplejump_p (next_trial) +- || GET_CODE (PATTERN (next_trial)) == RETURN))) ++ && simplejump_or_return_p (next_trial) ++ && JUMP_LABEL (insn) == JUMP_LABEL (next_trial))) + { + if (eligible_for_annul_false (insn, 0, trial, flags)) + { +@@ -819,13 +834,11 @@ + branch, thread our jump to the target of that branch. Don't + change this into a RETURN here, because it may not accept what + we have in the delay slot. We'll fix this up later. */ +- if (next_trial && JUMP_P (next_trial) +- && (simplejump_p (next_trial) +- || GET_CODE (PATTERN (next_trial)) == RETURN)) ++ if (next_trial && simplejump_or_return_p (next_trial)) + { + rtx target_label = JUMP_LABEL (next_trial); +- if (target_label == 0) +- target_label = find_end_label (); ++ if (ANY_RETURN_P (target_label)) ++ target_label = find_end_label (target_label); + + if (target_label) + { +@@ -866,7 +879,7 @@ + if (JUMP_P (insn) + && (condjump_p (insn) || condjump_in_parallel_p (insn)) + && INSN_UID (insn) <= max_uid +- && label != 0 ++ && label != 0 && !ANY_RETURN_P (label) + && INSN_UID (label) <= max_uid) + flags + = (uid_to_ruid[INSN_UID (label)] > uid_to_ruid[INSN_UID (insn)]) +@@ -1038,7 +1051,7 @@ + pat = XVECEXP (pat, 0, 0); + + if (GET_CODE (pat) == RETURN) +- return target == 0 ? const_true_rtx : 0; ++ return ANY_RETURN_P (target) ? const_true_rtx : 0; + + else if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx) + return 0; +@@ -1318,7 +1331,11 @@ + } + + /* Show the place to which we will be branching. */ +- *pnew_thread = next_active_insn (JUMP_LABEL (XVECEXP (seq, 0, 0))); ++ temp = JUMP_LABEL (XVECEXP (seq, 0, 0)); ++ if (ANY_RETURN_P (temp)) ++ *pnew_thread = temp; ++ else ++ *pnew_thread = next_active_insn (temp); + + /* Add any new insns to the delay list and update the count of the + number of slots filled. */ +@@ -1358,8 +1375,7 @@ + /* We can't do anything if SEQ's delay insn isn't an + unconditional branch. */ + +- if (! simplejump_p (XVECEXP (seq, 0, 0)) +- && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) != RETURN) ++ if (! simplejump_or_return_p (XVECEXP (seq, 0, 0))) + return delay_list; + + for (i = 1; i < XVECLEN (seq, 0); i++) +@@ -1827,7 +1843,7 @@ + rtx insn; + + /* We don't own the function end. */ +- if (thread == 0) ++ if (ANY_RETURN_P (thread)) + return 0; + + /* Get the first active insn, or THREAD, if it is an active insn. */ +@@ -2245,7 +2261,8 @@ + && (!JUMP_P (insn) + || ((condjump_p (insn) || condjump_in_parallel_p (insn)) + && ! simplejump_p (insn) +- && JUMP_LABEL (insn) != 0))) ++ && JUMP_LABEL (insn) != 0 ++ && !ANY_RETURN_P (JUMP_LABEL (insn))))) + { + /* Invariant: If insn is a JUMP_INSN, the insn's jump + label. Otherwise, zero. */ +@@ -2270,7 +2287,7 @@ + target = JUMP_LABEL (insn); + } + +- if (target == 0) ++ if (target == 0 || ANY_RETURN_P (target)) + for (trial = next_nonnote_insn (insn); trial; trial = next_trial) + { + next_trial = next_nonnote_insn (trial); +@@ -2349,6 +2366,7 @@ + && JUMP_P (trial) + && simplejump_p (trial) + && (target == 0 || JUMP_LABEL (trial) == target) ++ && !ANY_RETURN_P (JUMP_LABEL (trial)) + && (next_trial = next_active_insn (JUMP_LABEL (trial))) != 0 + && ! (NONJUMP_INSN_P (next_trial) + && GET_CODE (PATTERN (next_trial)) == SEQUENCE) +@@ -2371,7 +2389,7 @@ + if (new_label != 0) + new_label = get_label_before (new_label); + else +- new_label = find_end_label (); ++ new_label = find_end_label (simple_return_rtx); + + if (new_label) + { +@@ -2503,7 +2521,8 @@ + + /* Follow any unconditional jump at LABEL; + return the ultimate label reached by any such chain of jumps. +- Return null if the chain ultimately leads to a return instruction. ++ Return a suitable return rtx if the chain ultimately leads to a ++ return instruction. + If LABEL is not followed by a jump, return LABEL. + If the chain loops or we can't find end, return LABEL, + since that tells caller to avoid changing the insn. */ +@@ -2518,6 +2537,7 @@ + + for (depth = 0; + (depth < 10 ++ && !ANY_RETURN_P (value) + && (insn = next_active_insn (value)) != 0 + && JUMP_P (insn) + && ((JUMP_LABEL (insn) != 0 && any_uncondjump_p (insn) +@@ -2527,18 +2547,22 @@ + && BARRIER_P (next)); + depth++) + { +- rtx tem; ++ rtx this_label = JUMP_LABEL (insn); + + /* If we have found a cycle, make the insn jump to itself. */ +- if (JUMP_LABEL (insn) == label) ++ if (this_label == label) + return label; + +- tem = next_active_insn (JUMP_LABEL (insn)); +- if (tem && (GET_CODE (PATTERN (tem)) == ADDR_VEC ++ if (!ANY_RETURN_P (this_label)) ++ { ++ rtx tem = next_active_insn (this_label); ++ if (tem ++ && (GET_CODE (PATTERN (tem)) == ADDR_VEC + || GET_CODE (PATTERN (tem)) == ADDR_DIFF_VEC)) +- break; ++ break; ++ } + +- value = JUMP_LABEL (insn); ++ value = this_label; + } + if (depth == 10) + return label; +@@ -2901,6 +2925,7 @@ + arithmetic insn after the jump insn and put the arithmetic insn in the + delay slot. If we can't do this, return. */ + if (delay_list == 0 && likely && new_thread ++ && !ANY_RETURN_P (new_thread) + && NONJUMP_INSN_P (new_thread) + && GET_CODE (PATTERN (new_thread)) != ASM_INPUT + && asm_noperands (PATTERN (new_thread)) < 0) +@@ -2985,16 +3010,14 @@ + + gcc_assert (thread_if_true); + +- if (new_thread && JUMP_P (new_thread) +- && (simplejump_p (new_thread) +- || GET_CODE (PATTERN (new_thread)) == RETURN) ++ if (new_thread && simplejump_or_return_p (new_thread) + && redirect_with_delay_list_safe_p (insn, + JUMP_LABEL (new_thread), + delay_list)) + new_thread = follow_jumps (JUMP_LABEL (new_thread)); + +- if (new_thread == 0) +- label = find_end_label (); ++ if (ANY_RETURN_P (new_thread)) ++ label = find_end_label (new_thread); + else if (LABEL_P (new_thread)) + label = new_thread; + else +@@ -3340,11 +3363,12 @@ + group of consecutive labels. */ + if (JUMP_P (insn) + && (condjump_p (insn) || condjump_in_parallel_p (insn)) +- && (target_label = JUMP_LABEL (insn)) != 0) ++ && (target_label = JUMP_LABEL (insn)) != 0 ++ && !ANY_RETURN_P (target_label)) + { + target_label = skip_consecutive_labels (follow_jumps (target_label)); +- if (target_label == 0) +- target_label = find_end_label (); ++ if (ANY_RETURN_P (target_label)) ++ target_label = find_end_label (target_label); + + if (target_label && next_active_insn (target_label) == next + && ! condjump_in_parallel_p (insn)) +@@ -3359,9 +3383,8 @@ + /* See if this jump conditionally branches around an unconditional + jump. If so, invert this jump and point it to the target of the + second jump. */ +- if (next && JUMP_P (next) ++ if (next && simplejump_or_return_p (next) + && any_condjump_p (insn) +- && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN) + && target_label + && next_active_insn (target_label) == next_active_insn (next) + && no_labels_between_p (insn, next)) +@@ -3403,8 +3426,7 @@ + Don't do this if we expect the conditional branch to be true, because + we would then be making the more common case longer. */ + +- if (JUMP_P (insn) +- && (simplejump_p (insn) || GET_CODE (PATTERN (insn)) == RETURN) ++ if (simplejump_or_return_p (insn) + && (other = prev_active_insn (insn)) != 0 + && any_condjump_p (other) + && no_labels_between_p (other, insn) +@@ -3445,10 +3467,10 @@ + Only do so if optimizing for size since this results in slower, but + smaller code. */ + if (optimize_function_for_size_p (cfun) +- && GET_CODE (PATTERN (delay_insn)) == RETURN ++ && ANY_RETURN_P (PATTERN (delay_insn)) + && next + && JUMP_P (next) +- && GET_CODE (PATTERN (next)) == RETURN) ++ && PATTERN (next) == PATTERN (delay_insn)) + { + rtx after; + int i; +@@ -3487,14 +3509,16 @@ + continue; + + target_label = JUMP_LABEL (delay_insn); ++ if (target_label && ANY_RETURN_P (target_label)) ++ continue; + + if (target_label) + { + /* If this jump goes to another unconditional jump, thread it, but + don't convert a jump into a RETURN here. */ + trial = skip_consecutive_labels (follow_jumps (target_label)); +- if (trial == 0) +- trial = find_end_label (); ++ if (ANY_RETURN_P (trial)) ++ trial = find_end_label (trial); + + if (trial && trial != target_label + && redirect_with_delay_slots_safe_p (delay_insn, trial, insn)) +@@ -3517,7 +3541,7 @@ + later incorrectly compute register live/death info. */ + rtx tmp = next_active_insn (trial); + if (tmp == 0) +- tmp = find_end_label (); ++ tmp = find_end_label (simple_return_rtx); + + if (tmp) + { +@@ -3537,14 +3561,12 @@ + delay list and that insn is redundant, thread the jump. */ + if (trial && GET_CODE (PATTERN (trial)) == SEQUENCE + && XVECLEN (PATTERN (trial), 0) == 2 +- && JUMP_P (XVECEXP (PATTERN (trial), 0, 0)) +- && (simplejump_p (XVECEXP (PATTERN (trial), 0, 0)) +- || GET_CODE (PATTERN (XVECEXP (PATTERN (trial), 0, 0))) == RETURN) ++ && simplejump_or_return_p (XVECEXP (PATTERN (trial), 0, 0)) + && redundant_insn (XVECEXP (PATTERN (trial), 0, 1), insn, 0)) + { + target_label = JUMP_LABEL (XVECEXP (PATTERN (trial), 0, 0)); +- if (target_label == 0) +- target_label = find_end_label (); ++ if (ANY_RETURN_P (target_label)) ++ target_label = find_end_label (target_label); + + if (target_label + && redirect_with_delay_slots_safe_p (delay_insn, target_label, +@@ -3622,16 +3644,15 @@ + a RETURN here. */ + if (! INSN_ANNULLED_BRANCH_P (delay_insn) + && any_condjump_p (delay_insn) +- && next && JUMP_P (next) +- && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN) ++ && next && simplejump_or_return_p (next) + && next_active_insn (target_label) == next_active_insn (next) + && no_labels_between_p (insn, next)) + { + rtx label = JUMP_LABEL (next); + rtx old_label = JUMP_LABEL (delay_insn); + +- if (label == 0) +- label = find_end_label (); ++ if (ANY_RETURN_P (label)) ++ label = find_end_label (label); + + /* find_end_label can generate a new label. Check this first. */ + if (label +@@ -3692,7 +3713,8 @@ + make_return_insns (rtx first) + { + rtx insn, jump_insn, pat; +- rtx real_return_label = end_of_function_label; ++ rtx real_return_label = function_return_label; ++ rtx real_simple_return_label = function_simple_return_label; + int slots, i; + + #ifdef DELAY_SLOTS_FOR_EPILOGUE +@@ -3707,18 +3729,25 @@ + #endif + + /* See if there is a RETURN insn in the function other than the one we +- made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change ++ made for FUNCTION_RETURN_LABEL. If so, set up anything we can't change + into a RETURN to jump to it. */ + for (insn = first; insn; insn = NEXT_INSN (insn)) +- if (JUMP_P (insn) && GET_CODE (PATTERN (insn)) == RETURN) ++ if (JUMP_P (insn) && ANY_RETURN_P (PATTERN (insn))) + { +- real_return_label = get_label_before (insn); ++ rtx t = get_label_before (insn); ++ if (PATTERN (insn) == ret_rtx) ++ real_return_label = t; ++ else ++ real_simple_return_label = t; + break; + } + + /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it +- was equal to END_OF_FUNCTION_LABEL. */ +- LABEL_NUSES (real_return_label)++; ++ was equal to FUNCTION_RETURN_LABEL. */ ++ if (real_return_label) ++ LABEL_NUSES (real_return_label)++; ++ if (real_simple_return_label) ++ LABEL_NUSES (real_simple_return_label)++; + + /* Clear the list of insns to fill so we can use it. */ + obstack_free (&unfilled_slots_obstack, unfilled_firstobj); +@@ -3726,13 +3755,27 @@ + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + int flags; ++ rtx kind, real_label; + + /* Only look at filled JUMP_INSNs that go to the end of function + label. */ + if (!NONJUMP_INSN_P (insn) + || GET_CODE (PATTERN (insn)) != SEQUENCE +- || !JUMP_P (XVECEXP (PATTERN (insn), 0, 0)) +- || JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) != end_of_function_label) ++ || !JUMP_P (XVECEXP (PATTERN (insn), 0, 0))) ++ continue; ++ ++ if (JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) == function_return_label) ++ { ++ kind = ret_rtx; ++ real_label = real_return_label; ++ } ++ else if (JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) ++ == function_simple_return_label) ++ { ++ kind = simple_return_rtx; ++ real_label = real_simple_return_label; ++ } ++ else + continue; + + pat = PATTERN (insn); +@@ -3740,14 +3783,12 @@ + + /* If we can't make the jump into a RETURN, try to redirect it to the best + RETURN and go on to the next insn. */ +- if (! reorg_redirect_jump (jump_insn, NULL_RTX)) ++ if (! reorg_redirect_jump (jump_insn, kind)) + { + /* Make sure redirecting the jump will not invalidate the delay + slot insns. */ +- if (redirect_with_delay_slots_safe_p (jump_insn, +- real_return_label, +- insn)) +- reorg_redirect_jump (jump_insn, real_return_label); ++ if (redirect_with_delay_slots_safe_p (jump_insn, real_label, insn)) ++ reorg_redirect_jump (jump_insn, real_label); + continue; + } + +@@ -3787,7 +3828,7 @@ + RETURN, delete the SEQUENCE and output the individual insns, + followed by the RETURN. Then set things up so we try to find + insns for its delay slots, if it needs some. */ +- if (GET_CODE (PATTERN (jump_insn)) == RETURN) ++ if (ANY_RETURN_P (PATTERN (jump_insn))) + { + rtx prev = PREV_INSN (insn); + +@@ -3804,13 +3845,16 @@ + else + /* It is probably more efficient to keep this with its current + delay slot as a branch to a RETURN. */ +- reorg_redirect_jump (jump_insn, real_return_label); ++ reorg_redirect_jump (jump_insn, real_label); + } + + /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any + new delay slots we have created. */ +- if (--LABEL_NUSES (real_return_label) == 0) ++ if (real_return_label != NULL_RTX && --LABEL_NUSES (real_return_label) == 0) + delete_related_insns (real_return_label); ++ if (real_simple_return_label != NULL_RTX ++ && --LABEL_NUSES (real_simple_return_label) == 0) ++ delete_related_insns (real_simple_return_label); + + fill_simple_delay_slots (1); + fill_simple_delay_slots (0); +@@ -3878,7 +3922,7 @@ + init_resource_info (epilogue_insn); + + /* Show we haven't computed an end-of-function label yet. */ +- end_of_function_label = 0; ++ function_return_label = function_simple_return_label = NULL_RTX; + + /* Initialize the statistics for this function. */ + memset (num_insns_needing_delays, 0, sizeof num_insns_needing_delays); +@@ -3900,11 +3944,23 @@ + /* If we made an end of function label, indicate that it is now + safe to delete it by undoing our prior adjustment to LABEL_NUSES. + If it is now unused, delete it. */ +- if (end_of_function_label && --LABEL_NUSES (end_of_function_label) == 0) +- delete_related_insns (end_of_function_label); ++ if (function_return_label && --LABEL_NUSES (function_return_label) == 0) ++ delete_related_insns (function_return_label); ++ if (function_simple_return_label ++ && --LABEL_NUSES (function_simple_return_label) == 0) ++ delete_related_insns (function_simple_return_label); + ++#if defined HAVE_return || defined HAVE_simple_return ++ if ( + #ifdef HAVE_return +- if (HAVE_return && end_of_function_label != 0) ++ (HAVE_return && function_return_label != 0) ++#else ++ 0 ++#endif ++#ifdef HAVE_simple_return ++ || (HAVE_simple_return && function_simple_return_label != 0) ++#endif ++ ) + make_return_insns (first); + #endif + +--- a/src/gcc/resource.c ++++ b/src/gcc/resource.c +@@ -495,6 +495,8 @@ + || GET_CODE (PATTERN (this_jump_insn)) == RETURN) + { + next = JUMP_LABEL (this_jump_insn); ++ if (next && ANY_RETURN_P (next)) ++ next = NULL_RTX; + if (jump_insn == 0) + { + jump_insn = insn; +@@ -562,9 +564,10 @@ + AND_COMPL_HARD_REG_SET (scratch, needed.regs); + AND_COMPL_HARD_REG_SET (fallthrough_res.regs, scratch); + +- find_dead_or_set_registers (JUMP_LABEL (this_jump_insn), +- &target_res, 0, jump_count, +- target_set, needed); ++ if (!ANY_RETURN_P (JUMP_LABEL (this_jump_insn))) ++ find_dead_or_set_registers (JUMP_LABEL (this_jump_insn), ++ &target_res, 0, jump_count, ++ target_set, needed); + find_dead_or_set_registers (next, + &fallthrough_res, 0, jump_count, + set, needed); +@@ -1097,6 +1100,8 @@ + struct resources new_resources; + rtx stop_insn = next_active_insn (jump_insn); + ++ if (jump_target && ANY_RETURN_P (jump_target)) ++ jump_target = NULL_RTX; + mark_target_live_regs (insns, next_active_insn (jump_target), + &new_resources); + CLEAR_RESOURCE (&set); +--- a/src/gcc/rtl.c ++++ b/src/gcc/rtl.c +@@ -256,6 +256,8 @@ + case CODE_LABEL: + case PC: + case CC0: ++ case RETURN: ++ case SIMPLE_RETURN: + case SCRATCH: + /* SCRATCH must be shared because they represent distinct values. */ + return orig; +@@ -429,7 +431,15 @@ + case 'n': + case 'i': + if (XINT (x, i) != XINT (y, i)) +- return 0; ++ { ++#ifndef GENERATOR_FILE ++ if (((code == ASM_OPERANDS && i == 6) ++ || (code == ASM_INPUT && i == 1)) ++ && locator_eq (XINT (x, i), XINT (y, i))) ++ break; ++#endif ++ return 0; ++ } + break; + + case 'V': +@@ -549,7 +559,15 @@ + case 'n': + case 'i': + if (XINT (x, i) != XINT (y, i)) +- return 0; ++ { ++#ifndef GENERATOR_FILE ++ if (((code == ASM_OPERANDS && i == 6) ++ || (code == ASM_INPUT && i == 1)) ++ && locator_eq (XINT (x, i), XINT (y, i))) ++ break; ++#endif ++ return 0; ++ } + break; + + case 'V': +--- a/src/gcc/rtl.def ++++ b/src/gcc/rtl.def +@@ -296,6 +296,10 @@ + + DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA) + ++/* A plain return, to be used on paths that are reached without going ++ through the function prologue. */ ++DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA) ++ + /* Special for EH return from subroutine. */ + + DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA) +--- a/src/gcc/rtl.h ++++ b/src/gcc/rtl.h +@@ -411,6 +411,10 @@ + (JUMP_P (INSN) && (GET_CODE (PATTERN (INSN)) == ADDR_VEC || \ + GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC)) + ++/* Predicate yielding nonzero iff X is a return or simple_preturn. */ ++#define ANY_RETURN_P(X) \ ++ (GET_CODE (X) == RETURN || GET_CODE (X) == SIMPLE_RETURN) ++ + /* 1 if X is a unary operator. */ + + #define UNARY_P(X) \ +@@ -1998,6 +2002,8 @@ + { + GR_PC, + GR_CC0, ++ GR_RETURN, ++ GR_SIMPLE_RETURN, + GR_STACK_POINTER, + GR_FRAME_POINTER, + /* For register elimination to work properly these hard_frame_pointer_rtx, +@@ -2032,6 +2038,8 @@ + + /* Standard pieces of rtx, to be substituted directly into things. */ + #define pc_rtx (global_rtl[GR_PC]) ++#define ret_rtx (global_rtl[GR_RETURN]) ++#define simple_return_rtx (global_rtl[GR_SIMPLE_RETURN]) + #define cc0_rtx (global_rtl[GR_CC0]) + + /* All references to certain hard regs, except those created +--- a/src/gcc/rtlanal.c ++++ b/src/gcc/rtlanal.c +@@ -2673,6 +2673,7 @@ + + if (JUMP_P (insn) + && (label = JUMP_LABEL (insn)) != NULL_RTX ++ && !ANY_RETURN_P (label) + && (table = next_active_insn (label)) != NULL_RTX + && JUMP_TABLE_DATA_P (table)) + { +--- a/src/gcc/sched-int.h ++++ b/src/gcc/sched-int.h +@@ -199,7 +199,7 @@ + + extern void ebb_compute_jump_reg_dependencies (rtx, regset, regset, regset); + +-extern edge find_fallthru_edge (basic_block); ++extern edge find_fallthru_edge_from (basic_block); + + extern void (* sched_init_only_bb) (basic_block, basic_block); + extern basic_block (* sched_split_block) (basic_block, rtx); +--- a/src/gcc/sched-vis.c ++++ b/src/gcc/sched-vis.c +@@ -549,6 +549,9 @@ + case RETURN: + sprintf (buf, "return"); + break; ++ case SIMPLE_RETURN: ++ sprintf (buf, "simple_return"); ++ break; + case CALL: + print_exp (buf, x, verbose); + break; +--- a/src/gcc/sel-sched-ir.c ++++ b/src/gcc/sel-sched-ir.c +@@ -686,7 +686,7 @@ + + /* Find fallthrough edge. */ + gcc_assert (BLOCK_FOR_INSN (insn)->prev_bb); +- candidate = find_fallthru_edge (BLOCK_FOR_INSN (insn)->prev_bb); ++ candidate = find_fallthru_edge_from (BLOCK_FOR_INSN (insn)->prev_bb); + + if (!candidate + || (candidate->src != BLOCK_FOR_INSN (last_scheduled_insn) +--- a/src/gcc/sel-sched.c ++++ b/src/gcc/sel-sched.c +@@ -617,8 +617,8 @@ + if (bb == BLOCK_FOR_INSN (succ)) + return true; + +- if (find_fallthru_edge (bb)) +- bb = find_fallthru_edge (bb)->dest; ++ if (find_fallthru_edge_from (bb)) ++ bb = find_fallthru_edge_from (bb)->dest; + else + return false; + +@@ -4911,7 +4911,7 @@ + next = PREV_INSN (insn); + BND_TO (bnd) = insn; + +- ft_edge = find_fallthru_edge (block_from); ++ ft_edge = find_fallthru_edge_from (block_from); + block_next = ft_edge->dest; + /* There must be a fallthrough block (or where should go + control flow in case of false jump predicate otherwise?). */ +--- a/src/gcc/stmt.c ++++ b/src/gcc/stmt.c +@@ -117,7 +117,8 @@ + static int estimate_case_costs (case_node_ptr); + static bool lshift_cheap_p (void); + static int case_bit_test_cmp (const void *, const void *); +-static void emit_case_bit_tests (tree, tree, tree, tree, case_node_ptr, rtx); ++static void emit_case_bit_tests (tree, tree, tree, tree, case_node_ptr, tree, ++ rtx, basic_block); + static void balance_case_nodes (case_node_ptr *, case_node_ptr); + static int node_has_low_bound (case_node_ptr, tree); + static int node_has_high_bound (case_node_ptr, tree); +@@ -684,13 +685,14 @@ + for (tail = clobbers; tail; tail = TREE_CHAIN (tail)) + { + const char *regname; ++ int nregs; + + if (TREE_VALUE (tail) == error_mark_node) + return; + regname = TREE_STRING_POINTER (TREE_VALUE (tail)); + +- i = decode_reg_name (regname); +- if (i >= 0 || i == -4) ++ i = decode_reg_name_and_count (regname, &nregs); ++ if (i == -4) + ++nclobbers; + else if (i == -2) + error ("unknown register name %qs in %", regname); +@@ -698,14 +700,21 @@ + /* Mark clobbered registers. */ + if (i >= 0) + { +- /* Clobbering the PIC register is an error. */ +- if (i == (int) PIC_OFFSET_TABLE_REGNUM) ++ int reg; ++ ++ for (reg = i; reg < i + nregs; reg++) + { +- error ("PIC register %qs clobbered in %", regname); +- return; +- } ++ ++nclobbers; ++ ++ /* Clobbering the PIC register is an error. */ ++ if (reg == (int) PIC_OFFSET_TABLE_REGNUM) ++ { ++ error ("PIC register clobbered by %qs in %", regname); ++ return; ++ } + +- SET_HARD_REG_BIT (clobbered_regs, i); ++ SET_HARD_REG_BIT (clobbered_regs, reg); ++ } + } + } + +@@ -1030,7 +1039,8 @@ + for (tail = clobbers; tail; tail = TREE_CHAIN (tail)) + { + const char *regname = TREE_STRING_POINTER (TREE_VALUE (tail)); +- int j = decode_reg_name (regname); ++ int reg, nregs; ++ int j = decode_reg_name_and_count (regname, &nregs); + rtx clobbered_reg; + + if (j < 0) +@@ -1052,30 +1062,39 @@ + continue; + } + +- /* Use QImode since that's guaranteed to clobber just one reg. */ +- clobbered_reg = gen_rtx_REG (QImode, j); +- +- /* Do sanity check for overlap between clobbers and respectively +- input and outputs that hasn't been handled. Such overlap +- should have been detected and reported above. */ +- if (!clobber_conflict_found) ++ for (reg = j; reg < j + nregs; reg++) + { +- int opno; ++ /* Use QImode since that's guaranteed to clobber just ++ * one reg. */ ++ clobbered_reg = gen_rtx_REG (QImode, reg); ++ ++ /* Do sanity check for overlap between clobbers and ++ respectively input and outputs that hasn't been ++ handled. Such overlap should have been detected and ++ reported above. */ ++ if (!clobber_conflict_found) ++ { ++ int opno; + +- /* We test the old body (obody) contents to avoid tripping +- over the under-construction body. */ +- for (opno = 0; opno < noutputs; opno++) +- if (reg_overlap_mentioned_p (clobbered_reg, output_rtx[opno])) +- internal_error ("asm clobber conflict with output operand"); +- +- for (opno = 0; opno < ninputs - ninout; opno++) +- if (reg_overlap_mentioned_p (clobbered_reg, +- ASM_OPERANDS_INPUT (obody, opno))) +- internal_error ("asm clobber conflict with input operand"); +- } ++ /* We test the old body (obody) contents to avoid ++ tripping over the under-construction body. */ ++ for (opno = 0; opno < noutputs; opno++) ++ if (reg_overlap_mentioned_p (clobbered_reg, ++ output_rtx[opno])) ++ internal_error ++ ("asm clobber conflict with output operand"); ++ ++ for (opno = 0; opno < ninputs - ninout; opno++) ++ if (reg_overlap_mentioned_p (clobbered_reg, ++ ASM_OPERANDS_INPUT (obody, ++ opno))) ++ internal_error ++ ("asm clobber conflict with input operand"); ++ } + +- XVECEXP (body, 0, i++) +- = gen_rtx_CLOBBER (VOIDmode, clobbered_reg); ++ XVECEXP (body, 0, i++) ++ = gen_rtx_CLOBBER (VOIDmode, clobbered_reg); ++ } + } + + if (nlabels > 0) +@@ -1737,7 +1756,7 @@ + xbitpos for the destination store (right justified). */ + store_bit_field (dst, bitsize, xbitpos % BITS_PER_WORD, word_mode, + extract_bit_field (src, bitsize, +- bitpos % BITS_PER_WORD, 1, ++ bitpos % BITS_PER_WORD, 1, false, + NULL_RTX, word_mode, word_mode)); + } + +@@ -2089,8 +2108,11 @@ + { + HOST_WIDE_INT hi; + HOST_WIDE_INT lo; ++ HOST_WIDE_INT rev_hi; ++ HOST_WIDE_INT rev_lo; + rtx label; + int bits; ++ int prob; + }; + + /* Determine whether "1 << x" is relatively cheap in word_mode. */ +@@ -2130,10 +2152,193 @@ + return CODE_LABEL_NUMBER (d2->label) - CODE_LABEL_NUMBER (d1->label); + } + ++/* Emit a bit test and a conditional jump. */ ++ ++static void ++emit_case_bit_test_jump (unsigned int count, rtx index, rtx label, ++ unsigned int method, HOST_WIDE_INT hi, ++ HOST_WIDE_INT lo, HOST_WIDE_INT rev_hi, ++ HOST_WIDE_INT rev_lo) ++{ ++ rtx expr; ++ ++ if (method == 1) ++ { ++ /* (1 << index). */ ++ if (count == 0) ++ index = expand_binop (word_mode, ashl_optab, const1_rtx, ++ index, NULL_RTX, 1, OPTAB_WIDEN); ++ /* CST. */ ++ expr = immed_double_const (lo, hi, word_mode); ++ /* ((1 << index) & CST). */ ++ expr = expand_binop (word_mode, and_optab, index, expr, ++ NULL_RTX, 1, OPTAB_WIDEN); ++ /* if (((1 << index) & CST)). */ ++ emit_cmp_and_jump_insns (expr, const0_rtx, NE, NULL_RTX, ++ word_mode, 1, label); ++ } ++ else if (method == 2) ++ { ++ /* (bit_reverse (CST)) */ ++ expr = immed_double_const (rev_lo, rev_hi, word_mode); ++ /* ((bit_reverse (CST)) << index) */ ++ expr = expand_binop (word_mode, ashl_optab, expr, ++ index, NULL_RTX, 1, OPTAB_WIDEN); ++ /* if (((bit_reverse (CST)) << index) < 0). */ ++ emit_cmp_and_jump_insns (expr, const0_rtx, LT, NULL_RTX, ++ word_mode, 0, label); ++ } ++ else ++ gcc_unreachable (); ++} ++ ++/* Return the cost of rtx sequence SEQ. The sequence is supposed to contain one ++ jump, which has no effect in the cost. */ ++ ++static unsigned int ++rtx_seq_cost (rtx seq) ++{ ++ rtx one; ++ unsigned int nr_branches = 0; ++ unsigned int sum = 0, cost; ++ ++ for (one = seq; one != NULL_RTX; one = NEXT_INSN (one)) ++ if (JUMP_P (one)) ++ nr_branches++; ++ else ++ { ++ cost = insn_rtx_cost (PATTERN (one), optimize_insn_for_speed_p ()); ++ if (dump_file) ++ { ++ print_rtl_single (dump_file, one); ++ fprintf (dump_file, "cost: %u\n", cost); ++ } ++ sum += cost; ++ } ++ ++ gcc_assert (nr_branches == 1); ++ ++ if (dump_file) ++ fprintf (dump_file, "total cost: %u\n", sum); ++ return sum; ++} ++ ++/* Generate the rtx sequences for 2 bit test expansion methods, measure the cost ++ and choose the cheapest. */ ++ ++static unsigned int ++choose_case_bit_test_expand_method (rtx label) ++{ ++ rtx seq, index; ++ unsigned int cost[2]; ++ static bool method_known = false; ++ static unsigned int method; ++ ++ /* If already known, return the method. */ ++ if (method_known) ++ return method; ++ ++ index = gen_rtx_REG (word_mode, 10000); ++ ++ for (method = 1; method <= 2; ++method) ++ { ++ start_sequence (); ++ emit_case_bit_test_jump (0, index, label, method, 0, 0x0f0f0f0f, 0, ++ 0x0f0f0f0f); ++ seq = get_insns (); ++ end_sequence (); ++ cost[method - 1] = rtx_seq_cost (seq); ++ } ++ ++ /* Determine method based on heuristic. */ ++ method = ((cost[1] < cost[0]) ? 1 : 0) + 1; ++ ++ /* Save and return method. */ ++ method_known = true; ++ return method; ++} ++ ++/* Get the edge probability of the edge from SRC to LABEL_DECL. */ ++ ++static int ++get_label_prob (basic_block src, tree label_decl) ++{ ++ basic_block dest; ++ int prob = 0, nr_prob = 0; ++ unsigned int i; ++ edge e; ++ ++ if (label_decl == NULL_TREE) ++ return 0; ++ ++ dest = VEC_index (basic_block, label_to_block_map, ++ LABEL_DECL_UID (label_decl)); ++ ++ for (i = 0; i < EDGE_COUNT (src->succs); ++i) ++ { ++ e = EDGE_SUCC (src, i); ++ ++ if (e->dest != dest) ++ continue; ++ ++ prob += e->probability; ++ nr_prob++; ++ } ++ ++ gcc_assert (nr_prob == 1); ++ ++ return prob; ++} ++ ++/* Add probability note with scaled PROB to JUMP and update INV_SCALE. This ++ function is intended to be used with a series of conditional jumps to L[i] ++ where the probabilities p[i] to get to L[i] are known, and the jump ++ probabilities j[i] need to be computed. ++ ++ The algorithm to calculate the probabilities is ++ ++ scale = REG_BR_PROB_BASE; ++ for (i = 0; i < n; ++i) ++ { ++ j[i] = p[i] * scale / REG_BR_PROB_BASE; ++ f[i] = REG_BR_PROB_BASE - j[i]; ++ scale = scale / (f[i] / REG_BR_PROB_BASE); ++ } ++ ++ The implementation uses inv_scale (REG_BR_PROB_BASE / scale) instead of ++ scale, because scale tends to grow bigger than REG_BR_PROB_BASE. */ ++ ++static void ++set_jump_prob (rtx jump, int prob, int *inv_scale) ++{ ++ /* j[i] = p[i] * scale / REG_BR_PROB_BASE. */ ++ int jump_prob = prob * REG_BR_PROB_BASE / *inv_scale; ++ /* f[i] = REG_BR_PROB_BASE - j[i]. */ ++ int fallthrough_prob = REG_BR_PROB_BASE - jump_prob; ++ ++ gcc_assert (jump_prob <= REG_BR_PROB_BASE); ++ add_reg_note (jump, REG_BR_PROB, GEN_INT (jump_prob)); ++ ++ /* scale = scale / (f[i] / REG_BR_PROB_BASE). */ ++ *inv_scale = *inv_scale * fallthrough_prob / REG_BR_PROB_BASE; ++} ++ ++/* Set bit in hwi hi/lo pair. */ ++ ++static void ++set_bit (HOST_WIDE_INT *hi, HOST_WIDE_INT *lo, unsigned int j) ++{ ++ if (j >= HOST_BITS_PER_WIDE_INT) ++ *hi |= (HOST_WIDE_INT) 1 << (j - HOST_BITS_PER_INT); ++ else ++ *lo |= (HOST_WIDE_INT) 1 << j; ++} ++ + /* Expand a switch statement by a short sequence of bit-wise + comparisons. "switch(x)" is effectively converted into +- "if ((1 << (x-MINVAL)) & CST)" where CST and MINVAL are +- integer constants. ++ "if ((1 << (x-MINVAL)) & CST)" or ++ "if (((bit_reverse (CST)) << (x-MINVAL)) < 0)", where CST ++ and MINVAL are integer constants. + + INDEX_EXPR is the value being switched on, which is of + type INDEX_TYPE. MINVAL is the lowest case value of in +@@ -2147,14 +2352,17 @@ + + static void + emit_case_bit_tests (tree index_type, tree index_expr, tree minval, +- tree range, case_node_ptr nodes, rtx default_label) ++ tree range, case_node_ptr nodes, tree default_label_decl, ++ rtx default_label, basic_block bb) + { + struct case_bit_test test[MAX_CASE_BIT_TESTS]; + enum machine_mode mode; + rtx expr, index, label; + unsigned int i,j,lo,hi; + struct case_node *n; +- unsigned int count; ++ unsigned int count, method; ++ int inv_scale = REG_BR_PROB_BASE; ++ int default_prob = get_label_prob (bb, default_label_decl); + + count = 0; + for (n = nodes; n; n = n->right) +@@ -2169,8 +2377,11 @@ + gcc_assert (count < MAX_CASE_BIT_TESTS); + test[i].hi = 0; + test[i].lo = 0; ++ test[i].rev_hi = 0; ++ test[i].rev_lo = 0; + test[i].label = label; + test[i].bits = 1; ++ test[i].prob = get_label_prob (bb, n->code_label); + count++; + } + else +@@ -2181,10 +2392,11 @@ + hi = tree_low_cst (fold_build2 (MINUS_EXPR, index_type, + n->high, minval), 1); + for (j = lo; j <= hi; j++) +- if (j >= HOST_BITS_PER_WIDE_INT) +- test[i].hi |= (HOST_WIDE_INT) 1 << (j - HOST_BITS_PER_INT); +- else +- test[i].lo |= (HOST_WIDE_INT) 1 << j; ++ { ++ set_bit (&test[i].hi, &test[i].lo, j); ++ set_bit (&test[i].rev_hi, &test[i].rev_lo, ++ GET_MODE_BITSIZE (word_mode) - j - 1); ++ } + } + + qsort (test, count, sizeof(*test), case_bit_test_cmp); +@@ -2198,20 +2410,20 @@ + mode = TYPE_MODE (index_type); + expr = expand_normal (range); + if (default_label) +- emit_cmp_and_jump_insns (index, expr, GTU, NULL_RTX, mode, 1, +- default_label); ++ { ++ emit_cmp_and_jump_insns (index, expr, GTU, NULL_RTX, mode, 1, ++ default_label); ++ set_jump_prob (get_last_insn (), default_prob / 2, &inv_scale); ++ } + + index = convert_to_mode (word_mode, index, 0); +- index = expand_binop (word_mode, ashl_optab, const1_rtx, +- index, NULL_RTX, 1, OPTAB_WIDEN); + ++ method = choose_case_bit_test_expand_method (test[0].label); + for (i = 0; i < count; i++) + { +- expr = immed_double_const (test[i].lo, test[i].hi, word_mode); +- expr = expand_binop (word_mode, and_optab, index, expr, +- NULL_RTX, 1, OPTAB_WIDEN); +- emit_cmp_and_jump_insns (expr, const0_rtx, NE, NULL_RTX, +- word_mode, 1, test[i].label); ++ emit_case_bit_test_jump (i, index, test[i].label, method, test[i].hi, ++ test[i].lo, test[i].rev_hi, test[i].rev_lo); ++ set_jump_prob (get_last_insn (), test[i].prob, &inv_scale); + } + + if (default_label) +@@ -2382,7 +2594,8 @@ + range = maxval; + } + emit_case_bit_tests (index_type, index_expr, minval, range, +- case_list, default_label); ++ case_list, default_label_decl, default_label, ++ gimple_bb (stmt)); + } + + /* If range of values is much bigger than number of values, +--- a/src/gcc/stor-layout.c ++++ b/src/gcc/stor-layout.c +@@ -619,11 +619,15 @@ + } + + /* See if we can use an ordinary integer mode for a bit-field. +- Conditions are: a fixed size that is correct for another mode +- and occupying a complete byte or bytes on proper boundary. */ ++ Conditions are: a fixed size that is correct for another mode, ++ occupying a complete byte or bytes on proper boundary, ++ and not -fstrict-volatile-bitfields. If the latter is set, ++ we unfortunately can't check TREE_THIS_VOLATILE, as a cast ++ may make a volatile object later. */ + if (TYPE_SIZE (type) != 0 + && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST +- && GET_MODE_CLASS (TYPE_MODE (type)) == MODE_INT) ++ && GET_MODE_CLASS (TYPE_MODE (type)) == MODE_INT ++ && flag_strict_volatile_bitfields <= 0) + { + enum machine_mode xmode + = mode_for_size_tree (DECL_SIZE (decl), MODE_INT, 1); +--- a/src/gcc/system.h ++++ b/src/gcc/system.h +@@ -761,7 +761,8 @@ + TARGET_ASM_EXCEPTION_SECTION TARGET_ASM_EH_FRAME_SECTION \ + SMALL_ARG_MAX ASM_OUTPUT_SHARED_BSS ASM_OUTPUT_SHARED_COMMON \ + ASM_OUTPUT_SHARED_LOCAL ASM_MAKE_LABEL_LINKONCE \ +- STACK_CHECK_PROBE_INTERVAL STACK_CHECK_PROBE_LOAD ++ STACK_CHECK_PROBE_INTERVAL STACK_CHECK_PROBE_LOAD \ ++ ORDER_REGS_FOR_LOCAL_ALLOC + + /* Hooks that are no longer used. */ + #pragma GCC poison LANG_HOOKS_FUNCTION_MARK LANG_HOOKS_FUNCTION_FREE \ +--- a/src/gcc/target-def.h ++++ b/src/gcc/target-def.h +@@ -220,6 +220,10 @@ + #define TARGET_EXTRA_LIVE_ON_ENTRY hook_void_bitmap + #endif + ++#ifndef TARGET_WARN_FUNC_RESULT ++#define TARGET_WARN_FUNC_RESULT hook_bool_void_true ++#endif ++ + #ifndef TARGET_ASM_FILE_START_APP_OFF + #define TARGET_ASM_FILE_START_APP_OFF false + #endif +@@ -1030,6 +1034,7 @@ + TARGET_EMUTLS, \ + TARGET_OPTION_HOOKS, \ + TARGET_EXTRA_LIVE_ON_ENTRY, \ ++ TARGET_WARN_FUNC_RESULT, \ + TARGET_UNWIND_TABLES_DEFAULT, \ + TARGET_HAVE_NAMED_SECTIONS, \ + TARGET_HAVE_SWITCHABLE_BSS_SECTIONS, \ +--- a/src/gcc/target.h ++++ b/src/gcc/target.h +@@ -1179,6 +1179,10 @@ + bits in the bitmap passed in. */ + void (*live_on_entry) (bitmap); + ++ /* Return false if warnings about missing return statements or suspect ++ noreturn attributes should be suppressed for the current function. */ ++ bool (*warn_func_result) (void); ++ + /* True if unwinding tables should be generated by default. */ + bool unwind_tables_default; + +--- a/src/gcc/testsuite/ChangeLog ++++ b/src/gcc/testsuite/ChangeLog +@@ -1,3 +1,285 @@ ++2011-02-19 Alexandre Oliva ++ ++ PR tree-optimization/46620 ++ * gcc.dg/pr46620.c: New. ++ ++2011-02-19 Tobias Burnus ++ ++ PR fortran/47775 ++ * gfortran.dg/func_result_6.f90: New. ++ ++2011-02-17 Uros Bizjak ++ ++ PR target/43653 ++ * gcc.target/i386/pr43653.c: New test. ++ ++2011-02-14 Tobias Burnus ++ ++ * gfortran.dg/argument_checking_13.f90: Update dg-error. ++ * gfortran.dg/argument_checking_17.f90: New. ++ ++2011-02-10 Rainer Orth ++ ++ PR target/46610 ++ * gcc.target/mips/save-restore-1.c: Skip on mips-sgi-irix6*. ++ * gcc.target/mips/save-restore-3.c: Likewise. ++ * gcc.target/mips/save-restore-4.c: Likewise. ++ * gcc.target/mips/save-restore-5.c: Likewise. ++ ++ PR target/47683 ++ * g++.dg/tree-prof/partition1.C: Skip on mips-sgi-irix*. ++ * g++.dg/tree-prof/partition2.C: Likewise. ++ ++2011-02-07 Rainer Orth ++ ++ Backport from mainline: ++ 2010-07-23 Uros Bizjak ++ ++ * lib/target-supports.exp (check_avx_hw_available): New procedure. ++ (check_effective_target_avx_runtime): New procedure. ++ ++ * gcc.dg/compat/vector-1b_main.c: Use avx_runtime effective target. ++ Remove cpuid.h include and __get_cpuid test. ++ * gcc.dg/compat/vector-2b_main.c: Ditto. ++ ++ * gcc.target/i386/avx-check.h (main): Also check bit_OSXSAVE. ++ ++2011-02-03 Michael Meissner ++ ++ Backport from mainline: ++ 2011-02-02 Michael Meissner ++ PR target/47272 ++ * gcc.target/powerpc/vsx-builtin-8.c: New file, test vec_vsx_ld ++ and vec_vsx_st. ++ ++ * gcc.target/powerpc/avoid-indexed-addresses.c: Disable altivec ++ and vsx so a default --with-cpu=power7 doesn't give an error ++ when -mavoid-indexed-addresses is used. ++ ++ * gcc.target/powerpc/ppc32-abi-dfp-1.c: Rewrite to use an asm ++ wrapper function to save the arguments and then jump to the real ++ function, rather than depending on the compiler not to move stuff ++ before an asm. ++ * gcc.target/powerpc/ppc64-abi-dfp-2.c: Ditto. ++ ++2011-02-03 Jonathan Wakely ++ ++ PR c++/47589 ++ * g++.dg/pr47589.C: New test. ++ ++2011-02-01 Richard Guenther ++ ++ PR tree-optimization/47541 ++ * g++.dg/torture/pr47541.C: New testcase. ++ ++2011-01-31 Nathan Froyd ++ ++ Backport from mainline: ++ 2010-12-30 Nathan Froyd ++ ++ PR target/44606 ++ * gcc.dg/pr44606.c: New test. ++ ++2011-01-27 Andreas Krebbel ++ ++ * gcc.dg/tree-ssa/pr42585.c: Disable on power, arm, sh, s390 and ++ s390x. ++ ++2011-01-26 Eric Botcazou ++ ++ * gcc.c-torture/compile/20110126-1.c: New test. ++ ++2011-01-25 Tobias Burnus ++ ++ Backport from mainline ++ 2011-01-17 Jakub Jelinek ++ ++ PR fortran/47331 ++ * gfortran.dg/gomp/pr47331.f90: New test. ++ ++2011-01-25 Tobias Burnus ++ ++ PR fortran/47448 ++ * gfortran.dg/redefined_intrinsic_assignment_2.f90: New. ++ ++2011-01-25 Richard Guenther ++ ++ PR middle-end/47411 ++ * gcc.dg/torture/pr47411.c: New testcase. ++ ++2011-01-24 Rainer Orth ++ ++ * gfortran.dg/cray_pointers_2.f90: Avoid cycling through ++ optimization options. ++ ++2011-01-24 Rainer Orth ++ ++ * gfortran.dg/array_constructor_33.f90: Use dg-timeout-factor 4. ++ ++2011-01-21 Richard Guenther ++ ++ PR tree-optimization/47365 ++ * gcc.dg/torture/pr47365.c: New testcase. ++ * gcc.dg/tree-ssa/pr47392.c: Likewise. ++ ++2011-01-21 Rainer Orth ++ ++ * g++.dg/other/anon5.C: Skip on mips-sgi-irix*. ++ ++2011-01-17 Eric Botcazou ++ ++ Backport from mainline ++ 2010-11-22 Eric Botcazou ++ ++ * gcc.dg/pr28796-2.c: SKIP on SPARC/Solaris 8. ++ ++ PR rtl-optimization/46603 ++ * gcc.dg/vect/slp-multitypes-2.c: XFAIL execution on SPARC 32-bit. ++ ++ 2010-08-31 Bingfeng Mei ++ ++ * gcc.dg/vect/pr43430-1.c: Requires vect_condition target. ++ ++2011-01-17 Rainer Orth ++ ++ * g++.old-deja/g++.other/init19.C: Don't XFAIL on mips-sgi-irix*. ++ ++2011-01-17 H.J. Lu ++ ++ Backport from mainline ++ 2011-01-17 H.J. Lu ++ ++ PR target/47318 ++ * gcc.target/i386/avx-vmaskmovpd-1.c: New. ++ * gcc.target/i386/avx-vmaskmovpd-2.c: Likewise. ++ * gcc.target/i386/avx-vmaskmovps-1.c: Likewise. ++ * gcc.target/i386/avx-vmaskmovps-1.c: Likewise. ++ ++ * gcc.target/i386/avx-vmaskmovpd-256-1.c (avx_test): Load mask ++ as __m256i. ++ * gcc.target/i386/avx-vmaskmovpd-256-2.c (avx_test): Likewise. ++ * gcc.target/i386/avx-vmaskmovps-256-1.c (avx_test): Likewise. ++ * gcc.target/i386/avx-vmaskmovps-256-2.c (avx_test): Likewise. ++ ++2011-01-17 Richard Guenther ++ ++ Backport from mainline ++ PR tree-optimization/47286 ++ * gcc.dg/tree-ssa/pr47286.c: New testcase. ++ ++ PR tree-optimization/44592 ++ * gfortran.dg/pr44592.f90: New testcase. ++ ++2011-01-16 Jakub Jelinek ++ ++ Backport from mainline ++ 2011-01-07 Jakub Jelinek ++ ++ PR target/47201 ++ * gcc.dg/pr47201.c: New test. ++ ++ 2011-01-06 Jakub Jelinek ++ ++ PR c/47150 ++ * gcc.c-torture/compile/pr47150.c: New test. ++ ++ 2010-12-21 Jakub Jelinek ++ ++ PR target/46880 ++ * gcc.target/i386/pr46880.c: New test. ++ ++ PR middle-end/45852 ++ * gcc.target/i386/pr45852.c: New test. ++ ++ 2010-12-16 Jakub Jelinek ++ ++ PR tree-optimization/43655 ++ * g++.dg/opt/pr43655.C: New test. ++ ++ PR debug/46893 ++ * gcc.dg/pr46893.c: New test. ++ ++ 2010-12-10 Jakub Jelinek ++ ++ PR rtl-optimization/46804 ++ * gfortran.dg/pr46804.f90: New test. ++ ++ PR rtl-optimization/46865 ++ * gcc.target/i386/pr46865-1.c: New test. ++ * gcc.target/i386/pr46865-2.c: New test. ++ ++ PR tree-optimization/46864 ++ * g++.dg/opt/pr46864.C: New test. ++ ++2011-01-13 Rainer Orth ++ ++ * gfortran.dg/cray_pointers_2.f90: Use dg-timeout-factor 4. ++ ++2011-01-12 Eric Botcazou ++ ++ PR testsuite/33033 ++ * gcc.dg/20061124-1.c: Pass -mcpu=v9 on the SPARC. ++ ++2011-02-01 Thomas Koenig ++ ++ Backport from mainline ++ PR fortran/45338 ++ * gfortran.dg/userdef_operator_2.f90: New test case. ++ ++2010-12-27 Yao Qi ++ ++ Backport from mainline: ++ 2010-10-14 Yao Qi ++ ++ PR target/45447 ++ * gcc.target/arm/pr45447.c: New test. ++ ++2010-12-24 Eric Botcazou ++ ++ * gnat.dg/opt13_pkg.ad[sb]: Fix line ending. ++ ++2010-12-22 Sebastian Pop ++ ++ PR tree-optimization/46758 ++ * gcc.dg/graphite/run-id-pr46758.c: New. ++ ++2010-12-23 Sebastian Pop ++ ++ PR tree-optimization/45552 ++ * gcc.dg/graphite/pr45552.c ++ ++ ++2010-12-23 Sebastian Pop ++ ++ PR tree-optimization/43023 ++ * gfortran.dg/ldist-1.f90: Adjust pattern. ++ * gfortran.dg/ldist-pr43023.f90: New. ++ ++2010-12-21 Martin Jambor ++ ++ PR middle-end/46734 ++ * g++.dg/tree-ssa/pr46734.C: New test. ++ ++2010-12-18 Alexandre Oliva ++ ++ PR debug/46756 ++ * gfortran.dg/debug/pr46756.f: New. ++ ++2010-12-18 Alexandre Oliva ++ ++ PR debug/46782 ++ * gcc.dg/debug/pr46782.c: New. ++ ++2010-12-17 Daniel Kraft ++ ++ PR fortran/46794 ++ * gfortran.dg/power2.f90: Initialize variables. ++ ++2010-12-16 Eric Botcazou ++ ++ * gnat.dg/opt13.adb: New test. ++ * gnat.dg/opt13_pkg.ad[sb]: New helper. ++ + 2010-12-16 Release Manager + + * GCC 4.5.2 released. +@@ -11,7 +293,7 @@ + + Backport from mainline + 2010-12-06 Jakub Jelinek +- ++ + PR target/43897 + * gcc.target/ia64/pr43897.c: New test. + +@@ -30,7 +312,7 @@ + * gcc.dg/pr46499-2.c: New test. + + 2010-11-20 Jakub Jelinek +- ++ + PR c++/46538 + * g++.dg/other/error34.C: New test. + +--- a/src/gcc/testsuite/c-c++-common/abi-bf.c ++++ b/src/gcc/testsuite/c-c++-common/abi-bf.c +@@ -0,0 +1,3 @@ ++/* { dg-warning "incompatible" } */ ++/* { dg-do compile } */ ++/* { dg-options "-fstrict-volatile-bitfields -fabi-version=1" } */ +--- a/src/gcc/testsuite/c-c++-common/uninit-17.c ++++ b/src/gcc/testsuite/c-c++-common/uninit-17.c +@@ -0,0 +1,25 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -Wuninitialized -fno-ivopts" } */ ++ ++inline int foo(int x) ++{ ++ return x; ++} ++static void bar(int a, int *ptr) ++{ ++ do ++ { ++ int b; /* { dg-warning "may be used uninitialized" } */ ++ if (b < 40) { ++ ptr[0] = b; ++ } ++ b += 1; ++ ptr++; ++ } ++ while (--a != 0); ++} ++void foobar(int a, int *ptr) ++{ ++ bar(foo(a), ptr); ++} ++ +--- a/src/gcc/testsuite/g++.dg/abi/mangle-neon.C ++++ b/src/gcc/testsuite/g++.dg/abi/mangle-neon.C +@@ -2,7 +2,7 @@ + + // { dg-do compile } + // { dg-require-effective-target arm_neon_ok } +-// { dg-options "-mfpu=neon -mfloat-abi=softfp" } ++// { dg-add-options arm_neon } + + #include + +--- a/src/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-1.C ++++ b/src/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-1.C +@@ -0,0 +1,28 @@ ++// Origin: PR debug/45088 ++// { dg-do compile } ++// { dg-options "-g -dA" } ++// { dg-final { scan-assembler-times "\[^\n\r\]*\\(DIE\[^\n\r\]*DW_TAG_pointer_type\\)\[\n\r\]{1,2}\[^\n\r\]*DW_AT_byte_size\[\n\r\]{1,2}\[^\n\r\]*DW_AT_type" 4 } } ++ ++struct A ++{ ++ virtual ~A(); ++}; ++ ++struct B : public A ++{ ++ virtual ~B(){} ++}; ++ ++struct C : public B ++{ ++ A* a1; ++}; ++ ++int ++main() ++{ ++ C c; ++ c.a1 = 0; ++ return 0; ++} ++ +--- a/src/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-2.C ++++ b/src/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-2.C +@@ -0,0 +1,29 @@ ++// Origin: PR debug/45088 ++// { dg-do compile } ++// { dg-options "-g -dA" } ++// { dg-final { scan-assembler-times "\[^\n\r\]*\\(DIE\[^\n\r\]*DW_TAG_pointer_type\\)\[\n\r\]{1,2}\[^\n\r\]*DW_AT_byte_size\[\n\r\]{1,2}\[^\n\r\]*DW_AT_type" 4 } } ++ ++template ++struct A ++{ ++ virtual ~A(); ++}; ++ ++struct B : public A ++{ ++ virtual ~B(){} ++}; ++ ++struct C : public B ++{ ++ A* a1; ++}; ++ ++int ++main() ++{ ++ C c; ++ c.a1 = 0; ++ return 0; ++} ++ +--- a/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C ++++ b/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ +-/* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */ ++/* { dg-require-effective-target arm_neon_fp16_ok } */ ++/* { dg-options "-mfp16-format=ieee" } */ ++/* { dg-add-options arm_neon_fp16 } */ + + #include "arm-fp16-ops.h" + +@@ -12,3 +13,5 @@ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */ +--- a/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C ++++ b/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ +-/* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon-fp16 -mfloat-abi=softfp" } */ ++/* { dg-require-effective-target arm_neon_fp16_ok } */ ++/* { dg-options "-mfp16-format=ieee -ffast-math" } */ ++/* { dg-add-options arm_neon_fp16 } */ + + #include "arm-fp16-ops.h" + +@@ -12,3 +13,5 @@ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */ +--- a/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C ++++ b/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-mfp16-format=ieee" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm-fp16-ops.h" + +--- a/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C ++++ b/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-mfp16-format=ieee -ffast-math" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm-fp16-ops.h" + +--- a/src/gcc/testsuite/g++.dg/init/pr42556.C ++++ b/src/gcc/testsuite/g++.dg/init/pr42556.C +@@ -0,0 +1,10 @@ ++// { dg-do compile } ++// { dg-options "-fdump-tree-gimple" } ++ ++void foo (int a, int b, int c, int d) ++{ ++ int v[4] = {a, b, c, d}; ++} ++ ++// { dg-final { scan-tree-dump-not "v = {}" "gimple" } } ++// { dg-final { cleanup-tree-dump "gimple" } } +--- a/src/gcc/testsuite/g++.dg/opt/combine.C ++++ b/src/gcc/testsuite/g++.dg/opt/combine.C +@@ -0,0 +1,72 @@ ++// { dg-do assemble { target fpic } } ++// { dg-options "-O2 -fweb -fPIC -fvisibility=hidden" } ++ ++class QBasicAtomicInt ++{ ++public: ++ volatile int _q_value; ++ inline operator int () const {return _q_value;} ++}; ++class QVariant; ++class QScriptContext; ++class QScriptEngine; ++class QScriptValue ++{ ++public: ++ QVariant toVariant () const; ++}; ++class QScriptDebuggerBackendPrivate ++{ ++ static QScriptValue trace (QScriptContext *context); ++}; ++template struct QMetaTypeId { }; ++template struct QMetaTypeId2 ++{ ++ static inline int qt_metatype_id () ++ { ++ return QMetaTypeId::qt_metatype_id () ; ++ } ++}; ++template inline int qMetaTypeId (T * = 0) ++{ ++ return QMetaTypeId2::qt_metatype_id () ; ++} ++class QVariant { }; ++template inline T qvariant_cast (const QVariant &v) ++{ ++ const int vid = qMetaTypeId ((0)) ; ++}; ++class QScriptContext ++{ ++public: ++ QScriptValue callee () const; ++}; ++class QScriptEngine ++{ ++public: ++ static bool convertV2 (const QScriptValue &value , int type , void *ptr) ; ++}; ++inline bool qscriptvalue_cast_helper (const QScriptValue &value , int type , void *ptr) ++{ ++ return QScriptEngine::convertV2 (value, type, ptr) ; ++} ++template T qscriptvalue_cast (const QScriptValue &value) ++{ ++ T t; ++ const int id = qMetaTypeId () ; ++ if ( qscriptvalue_cast_helper (value, id, &t)) ++ return qvariant_cast (value.toVariant ()) ; ++} ++template <> struct QMetaTypeId< QScriptDebuggerBackendPrivate* > ++{ ++ static int qt_metatype_id () ++ { ++ static QBasicAtomicInt metatype_id = { (0) }; ++ return metatype_id; ++ } ++}; ++QScriptValue QScriptDebuggerBackendPrivate::trace (QScriptContext *context) ++{ ++ QScriptValue data = context->callee () ; ++ QScriptDebuggerBackendPrivate *self = qscriptvalue_cast (data) ; ++} +--- a/src/gcc/testsuite/g++.dg/opt/pr43655.C ++++ b/src/gcc/testsuite/g++.dg/opt/pr43655.C +@@ -0,0 +1,34 @@ ++// PR tree-optimization/43655 ++// { dg-do run } ++// { dg-options "-O0 -ftree-ter" } ++ ++extern "C" void abort (); ++ ++struct C ++{ ++ C (int i) : val(i) { } ++ C (const C& c) : val(c.val) { } ++ ~C (void) { val = 999; } ++ C& operator = (const C& c) { val = c.val; return *this; } ++ C& inc (int i) { val += i; return *this; } ++ int val; ++}; ++ ++C ++f () ++{ ++ return C (3); ++} ++ ++C ++f (int i) ++{ ++ return f ().inc (i); ++} ++ ++int ++main () ++{ ++ if (f (2).val != 5) ++ abort (); ++} +--- a/src/gcc/testsuite/g++.dg/opt/pr46864.C ++++ b/src/gcc/testsuite/g++.dg/opt/pr46864.C +@@ -0,0 +1,26 @@ ++// PR tree-optimization/46864 ++// { dg-do compile } ++// { dg-options "-O -fnon-call-exceptions" } ++ ++int baz (); ++ ++struct S ++{ ++ int k; ++ bool bar () throw () ++ { ++ int m = baz (); ++ for (int i = 0; i < m; i++) ++ k = i; ++ return m; ++ } ++}; ++ ++extern S *s; ++ ++void ++foo () ++{ ++ while (baz () && s->bar ()) ++ ; ++} +--- a/src/gcc/testsuite/g++.dg/other/anon5.C ++++ b/src/gcc/testsuite/g++.dg/other/anon5.C +@@ -1,5 +1,5 @@ + // PR c++/34094 +-// { dg-do link { target { ! { *-*-darwin* *-*-hpux* *-*-solaris2.* alpha*-dec-osf* } } } } ++// { dg-do link { target { ! { *-*-darwin* *-*-hpux* *-*-solaris2.* alpha*-dec-osf* mips-sgi-irix* } } } } + // { dg-options "-g" } + + namespace { +--- a/src/gcc/testsuite/g++.dg/other/armv7m-1.C ++++ b/src/gcc/testsuite/g++.dg/other/armv7m-1.C +@@ -0,0 +1,69 @@ ++/* { dg-do run { target arm*-*-* } } */ ++/* Test Armv7m interrupt routines. */ ++#include ++ ++#ifdef __ARM_ARCH_7M__ ++void __attribute__((interrupt)) ++foo(void) ++{ ++ long long n; ++ long p; ++ asm volatile ("" : "=r" (p) : "0" (&n)); ++ if (p & 4) ++ abort (); ++ return; ++} ++ ++void __attribute__((interrupt)) ++bar(void) ++{ ++ throw 42; ++} ++ ++int main() ++{ ++ int a; ++ int before; ++ int after; ++ volatile register int sp asm("sp"); ++ ++ asm volatile ("mov %0, sp\n" ++ "blx %2\n" ++ "mov %1, sp\n" ++ : "=&r" (before), "=r" (after) : "r" (foo) ++ : "memory", "cc", "r0", "r1", "r2", "r3", "ip", "lr"); ++ if (before != after) ++ abort(); ++ asm volatile ("mov %0, sp\n" ++ "sub sp, sp, #4\n" ++ "blx %2\n" ++ "add sp, sp, #4\n" ++ "mov %1, sp\n" ++ : "=&r" (before), "=r" (after) : "r" (foo) ++ : "memory", "cc", "r0", "r1", "r2", "r3", "ip", "lr"); ++ if (before != after) ++ abort(); ++ before = sp; ++ try ++ { ++ bar(); ++ } ++ catch (int i) ++ { ++ if (i != 42) ++ abort(); ++ } ++ catch (...) ++ { ++ abort(); ++ } ++ if (before != sp) ++ abort(); ++ exit(0); ++} ++#else ++int main() ++{ ++ exit (0); ++} ++#endif +--- a/src/gcc/testsuite/g++.dg/pr47589.C ++++ b/src/gcc/testsuite/g++.dg/pr47589.C +@@ -0,0 +1,26 @@ ++// PR c++/47589 ++// { dg-do compile } ++ ++struct F ++{ ++ typedef void(*Cb)(); ++ ++ F(Cb); ++}; ++ ++struct C ++{ ++ template static void f(); ++}; ++ ++template ++struct TF : F ++{ ++ TF() : F(C::f) { } ++}; ++ ++struct DTC : TF ++{ ++ DTC() { } ++}; ++ +--- a/src/gcc/testsuite/g++.dg/torture/pr47541.C ++++ b/src/gcc/testsuite/g++.dg/torture/pr47541.C +@@ -0,0 +1,27 @@ ++/* { dg-do run } */ ++ ++struct Dummy {}; ++struct RefCount : public Dummy { ++ ~RefCount(); /* Has to be non-pod. */ ++ int *a; ++ int *b; ++}; ++RefCount::~RefCount(){} ++struct Wrapper : public Dummy { RefCount ref; }; ++void __attribute__((noinline,noclone)) ++Push(Wrapper ptr) ++{ ++ *ptr.ref.b = 0; ++} ++extern "C" void abort (void); ++int main() ++{ ++ int a = 1, b = 1; ++ Wrapper x; ++ x.ref.a = &a; ++ x.ref.b = &b; ++ Push(x); ++ if (b != 0) ++ abort (); ++ return 0; ++} +--- a/src/gcc/testsuite/g++.dg/tree-prof/partition1.C ++++ b/src/gcc/testsuite/g++.dg/tree-prof/partition1.C +@@ -1,5 +1,6 @@ + /* { dg-require-effective-target freorder } */ + /* { dg-options "-O2 -freorder-blocks-and-partition" } */ ++/* { dg-skip-if "PR target/47683" { mips-sgi-irix* } } */ + + struct A { A () __attribute__((noinline)); ~A () __attribute__((noinline)); }; + A::A () { asm volatile ("" : : : "memory"); } +--- a/src/gcc/testsuite/g++.dg/tree-prof/partition2.C ++++ b/src/gcc/testsuite/g++.dg/tree-prof/partition2.C +@@ -1,6 +1,7 @@ + // PR middle-end/45458 + // { dg-require-effective-target freorder } + // { dg-options "-fnon-call-exceptions -freorder-blocks-and-partition" } ++// { dg-skip-if "PR target/47683" { mips-sgi-irix* } } + + int + main () +--- a/src/gcc/testsuite/g++.dg/tree-ssa/pr46734.C ++++ b/src/gcc/testsuite/g++.dg/tree-ssa/pr46734.C +@@ -0,0 +1,34 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O -fipa-sra" } */ ++ ++struct A ++{ ++ int *p; ++ A() {p = (int *) -1;} ++ ~A() {if (p && p != (int *) -1) *p = 0;} ++}; ++ ++struct B ++{ ++ A a; ++ char data[23]; ++ B() : a() {data[0] = 0;} ++}; ++ ++extern A ga; ++extern int *gi; ++extern void *gz; ++extern B *gb; ++ ++static int * __attribute__ ((noinline)) foo (B *b, void *z) ++{ ++ __builtin_memcpy (gz, z, 28); ++ ga = b->a; ++ return b->a.p; ++} ++ ++int *bar (B *b, void *z) ++{ ++ gb = b; ++ return foo (b, z); ++} +--- a/src/gcc/testsuite/g++.dg/tree-ssa/sink-1.C ++++ b/src/gcc/testsuite/g++.dg/tree-ssa/sink-1.C +@@ -0,0 +1,50 @@ ++/* { dg-do run } */ ++/* { dg-options "-O1" } */ ++ ++class A { ++ public: ++ A() {} ++ virtual ~A() {} ++ void * dostuff(); ++ ++ virtual int dovirtual() = 0; ++}; ++ ++ ++class B : public A { ++ public: ++ B() {} ++ int dovirtual() { return 0;} ++ virtual ~B() {}; ++}; ++ ++class C : public B { ++ public: ++ C() {} ++ virtual ~C() {}; ++}; ++ ++void* A::dostuff() ++{ ++ return (void*)dovirtual(); ++} ++ ++/* tree-ssa-sink was sinking the inlined destructor for STUFF out of ++ the first inner block and into the second one, where it was ending up ++ after the inlined constructor for STUFF2. This is bad because ++ cfgexpand aliases STUFF and STUFF2 to the same storage at -O1 ++ (i.e., without -fstrict-aliasing), with the result that STUFF2's ++ vtable was getting trashed. */ ++ ++int main() { ++ { ++ B stuff; ++ stuff.dostuff(); ++ } ++ { ++ C stuff2; ++ stuff2.dostuff(); ++ } ++ return 0; ++} ++ +--- a/src/gcc/testsuite/g++.dg/vect/vect.exp ++++ b/src/gcc/testsuite/g++.dg/vect/vect.exp +@@ -112,7 +112,7 @@ + } elseif [istarget "ia64-*-*"] { + set dg-do-what-default run + } elseif [is-effective-target arm_neon_ok] { +- lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp" ++ eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""] + if [is-effective-target arm_neon_hw] { + set dg-do-what-default run + } else { +--- a/src/gcc/testsuite/g++.dg/warn/Wdouble-promotion.C ++++ b/src/gcc/testsuite/g++.dg/warn/Wdouble-promotion.C +@@ -0,0 +1,99 @@ ++/* { dg-do compile } */ ++/* { dg-options "-Wdouble-promotion" } */ ++ ++#include ++ ++/* Some targets do not provide so we define I ourselves. */ ++#define I 1.0iF ++#define ID ((_Complex double)I) ++ ++float f; ++double d; ++int i; ++long double ld; ++_Complex float cf; ++_Complex double cd; ++_Complex long double cld; ++size_t s; ++ ++extern void varargs_fn (int, ...); ++extern void double_fn (double); ++extern float float_fn (void); ++ ++void ++usual_arithmetic_conversions(void) ++{ ++ float local_f; ++ _Complex float local_cf; ++ ++ /* Values of type "float" are implicitly converted to "double" or ++ "long double" due to use in arithmetic with "double" or "long ++ double" operands. */ ++ local_f = f + 1.0; /* { dg-warning "implicit" } */ ++ local_f = f - d; /* { dg-warning "implicit" } */ ++ local_f = 1.0f * 1.0; /* { dg-warning "implicit" } */ ++ local_f = 1.0f / d; /* { dg-warning "implicit" } */ ++ ++ local_cf = cf + 1.0; /* { dg-warning "implicit" } */ ++ local_cf = cf - d; /* { dg-warning "implicit" } */ ++ local_cf = cf + 1.0 * ID; /* { dg-warning "implicit" } */ ++ local_cf = cf - cd; /* { dg-warning "implicit" } */ ++ ++ local_f = i ? f : d; /* { dg-warning "implicit" } */ ++ i = f == d; /* { dg-warning "implicit" } */ ++ i = d != f; /* { dg-warning "implicit" } */ ++} ++ ++void ++default_argument_promotion (void) ++{ ++ /* Because "f" is part of the variable argument list, it is promoted ++ to "double". */ ++ varargs_fn (1, f); /* { dg-warning "implicit" } */ ++} ++ ++/* There is no warning when an explicit cast is used to perform the ++ conversion. */ ++ ++void ++casts (void) ++{ ++ float local_f; ++ _Complex float local_cf; ++ ++ local_f = (double)f + 1.0; /* { dg-bogus "implicit" } */ ++ local_f = (double)f - d; /* { dg-bogus "implicit" } */ ++ local_f = (double)1.0f + 1.0; /* { dg-bogus "implicit" } */ ++ local_f = (double)1.0f - d; /* { dg-bogus "implicit" } */ ++ ++ local_cf = (_Complex double)cf + 1.0; /* { dg-bogus "implicit" } */ ++ local_cf = (_Complex double)cf - d; /* { dg-bogus "implicit" } */ ++ local_cf = (_Complex double)cf + 1.0 * ID; /* { dg-bogus "implicit" } */ ++ local_cf = (_Complex double)cf - cd; /* { dg-bogus "implicit" } */ ++ ++ local_f = i ? (double)f : d; /* { dg-bogus "implicit" } */ ++ i = (double)f == d; /* { dg-bogus "implicit" } */ ++ i = d != (double)f; /* { dg-bogus "implicit" } */ ++} ++ ++/* There is no warning on conversions that occur in assignment (and ++ assignment-like) contexts. */ ++ ++void ++assignments (void) ++{ ++ d = f; /* { dg-bogus "implicit" } */ ++ double_fn (f); /* { dg-bogus "implicit" } */ ++ d = float_fn (); /* { dg-bogus "implicit" } */ ++} ++ ++/* There is no warning in non-evaluated contexts. */ ++ ++void ++non_evaluated (void) ++{ ++ s = sizeof (f + 1.0); /* { dg-bogus "implicit" } */ ++ s = __alignof__ (f + 1.0); /* { dg-bogus "implicit" } */ ++ d = (__typeof__(f + 1.0))f; /* { dg-bogus "implicit" } */ ++ s = sizeof (i ? f : d); /* { dg-bogus "implicit" } */ ++} +--- a/src/gcc/testsuite/g++.old-deja/g++.other/init19.C ++++ b/src/gcc/testsuite/g++.old-deja/g++.other/init19.C +@@ -1,4 +1,4 @@ +-// { dg-do run { xfail { { ! cxa_atexit } && { ! *-*-solaris2* } } } } ++// { dg-do run { xfail { { ! cxa_atexit } && { ! { mips-sgi-irix* *-*-solaris2* } } } } } + #include + + #define assert(x) do { if (! (x)) abort(); } while (0) +--- a/src/gcc/testsuite/gcc.c-torture/compile/20101217-1.c ++++ b/src/gcc/testsuite/gcc.c-torture/compile/20101217-1.c +@@ -0,0 +1,36 @@ ++/* Testcase provided by HUAWEI. */ ++#include ++int main() ++{ ++ int cur_k; ++ int cur_j=0; ++ int cur_i=28; ++ unsigned char temp_data[8]; ++ unsigned int Data_Size=20; ++ ++ for (cur_k=0;cur_j<7;cur_j++,cur_i++) { ++ if (cur_j%2==0) { ++ temp_data[cur_k++]=0; ++ } ++ if (cur_k==7) { ++ for (;cur_k>0;cur_k--) { ++ if (cur_k>2) { ++ if ((temp_data[7-cur_k]=='n' || temp_data[7-cur_k]=='N' ) && (temp_data[7-cur_k+1]=='a' || temp_data[7-cur_k+1]=='A' )) { ++ break; ++ } ++ } ++ if (cur_k==1) { ++ if (temp_data[7-cur_k]=='n' || temp_data[7-cur_k]=='N' ) { ++ break; ++ } ++ } ++ } ++ if (cur_k==7) { ++ } else { ++ if (cur_k>0) ++ printf("dfjk"); ++ } ++ } ++ } ++return 0; ++} +--- a/src/gcc/testsuite/gcc.c-torture/compile/20110126-1.c ++++ b/src/gcc/testsuite/gcc.c-torture/compile/20110126-1.c +@@ -0,0 +1,18 @@ ++/* PR rtl-optimization/44469 */ ++/* Testcase by Siarhei Siamashka */ ++ ++int a (int *t, const char *p) ++{ ++ if (*t == 0) ++ { ++ } ++ else if (*t == 1) ++ { ++ p = (const char *)t; ++ } ++ else ++ __builtin_unreachable(); ++ if (p[0]) ++ return 0; ++ return 1; ++} +--- a/src/gcc/testsuite/gcc.c-torture/compile/pr44788.c ++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr44788.c +@@ -0,0 +1,8 @@ ++void joint_decode(float* mlt_buffer1, int t) { ++ int i; ++ float decode_buffer[1060]; ++ foo(decode_buffer); ++ for (i=0; i<10 ; i++) { ++ mlt_buffer1[i] = i * decode_buffer[t]; ++ } ++} +--- a/src/gcc/testsuite/gcc.c-torture/compile/pr47150.c ++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr47150.c +@@ -0,0 +1,11 @@ ++/* PR c/47150 */ ++ ++float _Complex foo (float, float); ++ ++void ++bar () ++{ ++ float w = 2; ++ float _Complex b; ++ b = 0.5 * (foo (0, w) + foo (1, w) / w); ++} +--- a/src/gcc/testsuite/gcc.c-torture/execute/20100416-1.c ++++ b/src/gcc/testsuite/gcc.c-torture/execute/20100416-1.c +@@ -0,0 +1,40 @@ ++void abort(void); ++ ++int ++movegt(int x, int y, long long a) ++{ ++ int i; ++ int ret = 0; ++ for (i = 0; i < y; i++) ++ { ++ if (a >= (long long) 0xf000000000000000LL) ++ ret = x; ++ else ++ ret = y; ++ } ++ return ret; ++} ++ ++struct test ++{ ++ long long val; ++ int ret; ++} tests[] = { ++ { 0xf000000000000000LL, -1 }, ++ { 0xefffffffffffffffLL, 1 }, ++ { 0xf000000000000001LL, -1 }, ++ { 0x0000000000000000LL, -1 }, ++ { 0x8000000000000000LL, 1 }, ++}; ++ ++int ++main() ++{ ++ int i; ++ for (i = 0; i < sizeof (tests) / sizeof (tests[0]); i++) ++ { ++ if (movegt (-1, 1, tests[i].val) != tests[i].ret) ++ abort (); ++ } ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.c-torture/execute/postmod-1.c ++++ b/src/gcc/testsuite/gcc.c-torture/execute/postmod-1.c +@@ -0,0 +1,62 @@ ++#define DECLARE_ARRAY(A) array##A[0x10] ++#define DECLARE_COUNTER(A) counter##A = 0 ++#define DECLARE_POINTER(A) *pointer##A = array##A + x ++/* Create a loop that allows post-modification of pointerA, followed by ++ a use of the post-modified address. */ ++#define BEFORE(A) counter##A += *pointer##A, pointer##A += 3 ++#define AFTER(A) counter##A += pointer##A[x] ++ ++/* Set up the arrays so that one iteration of the loop sets the counter ++ to 3.0f. */ ++#define INIT_ARRAY(A) array##A[1] = 1.0f, array##A[5] = 2.0f ++ ++/* Check that the loop worked correctly for all values. */ ++#define CHECK_ARRAY(A) exit_code |= (counter##A != 3.0f) ++ ++/* Having 6 copies triggered the bug for ARM and Thumb. */ ++#define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5) ++ ++/* Each addendA should be allocated a register. */ ++#define INIT_VOLATILE(A) addend##A = vol ++#define ADD_VOLATILE(A) vol += addend##A ++ ++/* Having 5 copies triggered the bug for ARM and Thumb. */ ++#define MANY2(A) A (0), A (1), A (2), A (3), A (4) ++ ++float MANY (DECLARE_ARRAY); ++float MANY (DECLARE_COUNTER); ++ ++volatile int stop = 1; ++volatile int vol; ++ ++void __attribute__((noinline)) ++foo (int x) ++{ ++ float MANY (DECLARE_POINTER); ++ int i; ++ ++ do ++ { ++ MANY (BEFORE); ++ MANY (AFTER); ++ /* Create an inner loop that should ensure the code above ++ has registers free for reload inheritance. */ ++ { ++ int MANY2 (INIT_VOLATILE); ++ for (i = 0; i < 10; i++) ++ MANY2 (ADD_VOLATILE); ++ } ++ } ++ while (!stop); ++} ++ ++int ++main (void) ++{ ++ int exit_code = 0; ++ ++ MANY (INIT_ARRAY); ++ foo (1); ++ MANY (CHECK_ARRAY); ++ return exit_code; ++} +--- a/src/gcc/testsuite/gcc.c-torture/execute/pr40657.c ++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr40657.c +@@ -0,0 +1,23 @@ ++/* Verify that that Thumb-1 epilogue size optimization does not clobber the ++ return value. */ ++ ++long long v = 0x123456789abc; ++ ++__attribute__((noinline)) void bar (int *x) ++{ ++ asm volatile ("" : "=m" (x) ::); ++} ++ ++__attribute__((noinline)) long long foo() ++{ ++ int x; ++ bar(&x); ++ return v; ++} ++ ++int main () ++{ ++ if (foo () != v) ++ abort (); ++ exit (0); ++} +--- a/src/gcc/testsuite/gcc.c-torture/execute/pr46909-1.c ++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr46909-1.c +@@ -0,0 +1,22 @@ ++/* PR tree-optimization/46909 */ ++ ++extern void abort (); ++ ++int ++__attribute__ ((__noinline__)) ++foo (unsigned int x) ++{ ++ if (! (x == 4 || x == 6) || (x == 2 || x == 6)) ++ return 1; ++ return -1; ++} ++ ++int ++main () ++{ ++ int i; ++ for (i = -10; i < 10; i++) ++ if (foo (i) != 1 - 2 * (i == 4)) ++ abort (); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.c-torture/execute/pr46909-2.c ++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr46909-2.c +@@ -0,0 +1,22 @@ ++/* PR tree-optimization/46909 */ ++ ++extern void abort (void); ++ ++int ++__attribute__((noinline)) ++foo (int x) ++{ ++ if ((x != 0 && x != 13) || x == 5 || x == 20) ++ return 1; ++ return -1; ++} ++ ++int ++main (void) ++{ ++ int i; ++ for (i = -10; i < 30; i++) ++ if (foo (i) != 1 - 2 * (i == 0) - 2 * (i == 13)) ++ abort (); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.c-torture/execute/pr47299.c ++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr47299.c +@@ -0,0 +1,17 @@ ++/* PR rtl-optimization/47299 */ ++ ++extern void abort (void); ++ ++__attribute__ ((noinline, noclone)) unsigned short ++foo (unsigned char x) ++{ ++ return x * 255; ++} ++ ++int ++main () ++{ ++ if (foo (0x40) != 0x3fc0) ++ abort (); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.dg/20061124-1.c ++++ b/src/gcc/testsuite/gcc.dg/20061124-1.c +@@ -1,5 +1,6 @@ + /* { dg-do run } */ + /* { dg-require-effective-target sync_char_short } */ ++/* { dg-options "-mcpu=v9" { target sparc*-*-* } } */ + + /* This testcase failed on s390 because no compare instruction for + the check of FLAG was emitted. */ +--- a/src/gcc/testsuite/gcc.dg/20101010-1.c ++++ b/src/gcc/testsuite/gcc.dg/20101010-1.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fno-crossjumping" } */ ++ ++int foo (void) ++{ ++ int len; ++ if (bar1 (&len)) ++ { ++ char devpath [len]; ++ if (bar2 (devpath) == len) ++ return len; ++ } ++ return -1; ++} +--- a/src/gcc/testsuite/gcc.dg/Warray-bounds-3.c ++++ b/src/gcc/testsuite/gcc.dg/Warray-bounds-3.c +@@ -1,5 +1,7 @@ + /* { dg-do compile } */ + /* { dg-options "-O2 -Warray-bounds" } */ ++/* { dg-options "-O2 -Warray-bounds -fno-unroll-loops" { target arm*-*-* } } */ ++ + /* based on PR 31227 */ + + typedef __SIZE_TYPE__ size_t; +--- a/src/gcc/testsuite/gcc.dg/Wcxx-compat-12.c ++++ b/src/gcc/testsuite/gcc.dg/Wcxx-compat-12.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-Wc++-compat" } */ ++/* { dg-options "-fno-short-enums -Wc++-compat" } */ + + enum E { A }; + +--- a/src/gcc/testsuite/gcc.dg/Wdouble-promotion.c ++++ b/src/gcc/testsuite/gcc.dg/Wdouble-promotion.c +@@ -0,0 +1,104 @@ ++/* { dg-do compile } */ ++/* { dg-options "-Wdouble-promotion" } */ ++ ++#include ++ ++/* Some targets do not provide so we define I ourselves. */ ++#define I 1.0iF ++#define ID ((_Complex double)I) ++ ++float f; ++double d; ++int i; ++long double ld; ++_Complex float cf; ++_Complex double cd; ++_Complex long double cld; ++size_t s; ++ ++extern void unprototyped_fn (); ++extern void varargs_fn (int, ...); ++extern void double_fn (double); ++extern float float_fn (void); ++ ++void ++usual_arithmetic_conversions(void) ++{ ++ float local_f; ++ _Complex float local_cf; ++ ++ /* Values of type "float" are implicitly converted to "double" or ++ "long double" due to use in arithmetic with "double" or "long ++ double" operands. */ ++ local_f = f + 1.0; /* { dg-warning "implicit" } */ ++ local_f = f - d; /* { dg-warning "implicit" } */ ++ local_f = 1.0f * 1.0; /* { dg-warning "implicit" } */ ++ local_f = 1.0f / d; /* { dg-warning "implicit" } */ ++ ++ local_cf = cf + 1.0; /* { dg-warning "implicit" } */ ++ local_cf = cf - d; /* { dg-warning "implicit" } */ ++ local_cf = cf + 1.0 * ID; /* { dg-warning "implicit" } */ ++ local_cf = cf - cd; /* { dg-warning "implicit" } */ ++ ++ local_f = i ? f : d; /* { dg-warning "implicit" } */ ++ i = f == d; /* { dg-warning "implicit" } */ ++ i = d != f; /* { dg-warning "implicit" } */ ++} ++ ++void ++default_argument_promotion (void) ++{ ++ /* Because there is no prototype, "f" is promoted to "double". */ ++ unprototyped_fn (f); /* { dg-warning "implicit" } */ ++ undeclared_fn (f); /* { dg-warning "implicit" } */ ++ /* Because "f" is part of the variable argument list, it is promoted ++ to "double". */ ++ varargs_fn (1, f); /* { dg-warning "implicit" } */ ++} ++ ++/* There is no warning when an explicit cast is used to perform the ++ conversion. */ ++ ++void ++casts (void) ++{ ++ float local_f; ++ _Complex float local_cf; ++ ++ local_f = (double)f + 1.0; /* { dg-bogus "implicit" } */ ++ local_f = (double)f - d; /* { dg-bogus "implicit" } */ ++ local_f = (double)1.0f + 1.0; /* { dg-bogus "implicit" } */ ++ local_f = (double)1.0f - d; /* { dg-bogus "implicit" } */ ++ ++ local_cf = (_Complex double)cf + 1.0; /* { dg-bogus "implicit" } */ ++ local_cf = (_Complex double)cf - d; /* { dg-bogus "implicit" } */ ++ local_cf = (_Complex double)cf + 1.0 * ID; /* { dg-bogus "implicit" } */ ++ local_cf = (_Complex double)cf - cd; /* { dg-bogus "implicit" } */ ++ ++ local_f = i ? (double)f : d; /* { dg-bogus "implicit" } */ ++ i = (double)f == d; /* { dg-bogus "implicit" } */ ++ i = d != (double)f; /* { dg-bogus "implicit" } */ ++} ++ ++/* There is no warning on conversions that occur in assignment (and ++ assignment-like) contexts. */ ++ ++void ++assignments (void) ++{ ++ d = f; /* { dg-bogus "implicit" } */ ++ double_fn (f); /* { dg-bogus "implicit" } */ ++ d = float_fn (); /* { dg-bogus "implicit" } */ ++} ++ ++/* There is no warning in non-evaluated contexts. */ ++ ++void ++non_evaluated (void) ++{ ++ s = sizeof (f + 1.0); /* { dg-bogus "implicit" } */ ++ s = __alignof__ (f + 1.0); /* { dg-bogus "implicit" } */ ++ d = (__typeof__(f + 1.0))f; /* { dg-bogus "implicit" } */ ++ s = sizeof (i ? f : d); /* { dg-bogus "implicit" } */ ++ s = sizeof (unprototyped_fn (f)); /* { dg-bogus "implicit" } */ ++} +--- a/src/gcc/testsuite/gcc.dg/builtin-apply2.c ++++ b/src/gcc/testsuite/gcc.dg/builtin-apply2.c +@@ -8,10 +8,19 @@ + /* Verify that __builtin_apply behaves correctly on targets + with pre-pushed arguments (e.g. SPARC). */ + +- ++ + + #define INTEGER_ARG 5 + ++#ifdef __ARM_PCS ++/* For Base AAPCS, NAME is passed in r0. D is passed in r2 and r3. ++ E, F and G are passed on stack. So the size of the stack argument ++ data is 20. */ ++#define STACK_ARGUMENTS_SIZE 20 ++#else ++#define STACK_ARGUMENTS_SIZE 64 ++#endif ++ + extern void abort(void); + + void foo(char *name, double d, double e, double f, int g) +@@ -22,7 +31,7 @@ + + void bar(char *name, ...) + { +- __builtin_apply(foo, __builtin_apply_args(), 64); ++ __builtin_apply(foo, __builtin_apply_args(), STACK_ARGUMENTS_SIZE); + } + + int main(void) +--- a/src/gcc/testsuite/gcc.dg/compat/vector-1b_main.c ++++ b/src/gcc/testsuite/gcc.dg/compat/vector-1b_main.c +@@ -1,12 +1,10 @@ + /* { dg-skip-if "test AVX vector" { ! { i?86-*-* x86_64-*-* } } } */ +-/* { dg-require-effective-target avx } */ ++/* { dg-require-effective-target avx_runtime } */ + + /* Test compatibility of vector types: layout between separately-compiled + modules, parameter passing, and function return. This test uses + vectors of integer values. */ + +-#include "cpuid.h" +- + extern void vector_1_x (void); + extern void exit (int); + int fails; +@@ -14,14 +12,6 @@ + int + main () + { +- unsigned int eax, ebx, ecx, edx; +- +- if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) +- return 0; +- +- /* Run AVX vector test only if host has AVX support. */ +- if (ecx & bit_AVX) +- vector_1_x (); +- ++ vector_1_x (); + exit (0); + } +--- a/src/gcc/testsuite/gcc.dg/compat/vector-2b_main.c ++++ b/src/gcc/testsuite/gcc.dg/compat/vector-2b_main.c +@@ -1,12 +1,10 @@ + /* { dg-skip-if "test AVX support" { ! { i?86-*-* x86_64-*-* } } } */ +-/* { dg-require-effective-target avx } */ ++/* { dg-require-effective-target avx_runtime } */ + + /* Test compatibility of vector types: layout between separately-compiled + modules, parameter passing, and function return. This test uses + vectors of floating points values. */ + +-#include "cpuid.h" +- + extern void vector_2_x (void); + extern void exit (int); + int fails; +@@ -14,14 +12,6 @@ + int + main () + { +- unsigned int eax, ebx, ecx, edx; +- +- if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) +- return 0; +- +- /* Run AVX vector test only if host has AVX support. */ +- if (ecx & bit_AVX) +- vector_2_x (); +- ++ vector_2_x (); + exit (0); + } +--- a/src/gcc/testsuite/gcc.dg/debug/pr46782.c ++++ b/src/gcc/testsuite/gcc.dg/debug/pr46782.c +@@ -0,0 +1,11 @@ ++/* PR debug/46782 */ ++/* { dg-do compile } */ ++/* { dg-options "-w -O0 -fvar-tracking -fcompare-debug" } */ ++ ++void foo (int i) ++{ ++ if (i) ++ i++; ++ while (i) ++ ; ++} +--- a/src/gcc/testsuite/gcc.dg/extend-1.c ++++ b/src/gcc/testsuite/gcc.dg/extend-1.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-rtl-ee" } */ ++ ++void f(unsigned char * p, short s, int c, int *z) ++{ ++ if (c) ++ *z = 0; ++ *p ^= (unsigned char)s; ++} ++ ++/* { dg-final { scan-rtl-dump-times "sign_extend:" 0 "ee" { target mips*-*-* } } } */ ++/* { dg-final { scan-rtl-dump-times "superfluous extension \[0-9\]+ replaced" 1 "ee" { target mips*-*-* } } } */ ++/* { dg-final { cleanup-rtl-dump "ee" } } */ +--- a/src/gcc/testsuite/gcc.dg/extend-2-64.c ++++ b/src/gcc/testsuite/gcc.dg/extend-2-64.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-rtl-ee" } */ ++/* { dg-require-effective-target mips64 } */ ++ ++void f(unsigned char * p, short *s, int c) ++{ ++ short or = 0; ++ while (c) ++ { ++ or = or | s[c]; ++ c --; ++ } ++ *p = (unsigned char)or; ++} ++ ++/* { dg-final { scan-rtl-dump-times "zero_extend:" 1 "ee" { target mips*-*-* } } } */ ++/* { dg-final { scan-rtl-dump-times "sign_extend:" 0 "ee" { target mips*-*-* } } } */ ++/* { dg-final { scan-rtl-dump-times "superfluous extension \[0-9\]+ replaced" 3 "ee" { target mips*-*-* } } } */ ++/* { dg-final { cleanup-rtl-dump "ee" } } */ ++ +--- a/src/gcc/testsuite/gcc.dg/extend-2.c ++++ b/src/gcc/testsuite/gcc.dg/extend-2.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-rtl-ee" } */ ++/* { dg-require-effective-target ilp32 } */ ++ ++void f(unsigned char * p, short *s, int c) ++{ ++ short or = 0; ++ while (c) ++ { ++ or = or | s[c]; ++ c --; ++ } ++ *p = (unsigned char)or; ++} ++ ++/* { dg-final { scan-rtl-dump-times "zero_extend" 0 "ee" { target mips*-*-* } } } */ ++/* { dg-final { scan-rtl-dump-times "sign_extend" 0 "ee" { target mips*-*-* } } } */ ++/* { dg-final { scan-rtl-dump-times "superfluous extension \[0-9\]+ replaced" 2 "ee" { target mips*-*-* } } } */ ++/* { dg-final { cleanup-rtl-dump "ee" } } */ ++ +--- a/src/gcc/testsuite/gcc.dg/extend-3.c ++++ b/src/gcc/testsuite/gcc.dg/extend-3.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-rtl-ee" } */ ++ ++unsigned int f(unsigned char byte) ++{ ++ return byte << 25; ++} ++ ++/* { dg-final { scan-rtl-dump-times "zero_extend:" 0 "ee" { target mips*-*-* } } } */ ++/* { dg-final { scan-rtl-dump "superfluous extension \[0-9\]+ replaced" "ee" { target mips*-*-* } } } */ ++/* { dg-final { cleanup-rtl-dump "ee" } } */ ++ +--- a/src/gcc/testsuite/gcc.dg/extend-4.c ++++ b/src/gcc/testsuite/gcc.dg/extend-4.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-rtl-ee" } */ ++ ++unsigned char f(unsigned int a) ++{ ++ unsigned int b = a & 0x10ff; ++ return b; ++} ++ ++/* { dg-final { scan-rtl-dump-times "and:" 0 "ee" { target mips*-*-* } } } */ ++/* { dg-final { scan-rtl-dump-times "superfluous extension \[0-9\]+ replaced" 1 "ee" { target mips*-*-* } } } */ ++/* { dg-final { cleanup-rtl-dump "ee" } } */ ++ +--- a/src/gcc/testsuite/gcc.dg/graphite/interchange-9.c ++++ b/src/gcc/testsuite/gcc.dg/graphite/interchange-9.c +@@ -5,8 +5,8 @@ + #include + #endif + +-#define N 1111 +-#define M 1111 ++#define N 111 ++#define M 111 + + static int __attribute__((noinline)) + foo (int *x) +@@ -38,7 +38,7 @@ + fprintf (stderr, "res = %d \n", res); + #endif + +- if (res != 2468642) ++ if (res != 24642) + abort (); + + return 0; +--- a/src/gcc/testsuite/gcc.dg/graphite/pr45552.c ++++ b/src/gcc/testsuite/gcc.dg/graphite/pr45552.c +@@ -0,0 +1,46 @@ ++typedef struct ++{ ++ double z; ++} Vector; ++typedef struct ++{ ++ float *vertex; ++ float *normal; ++} VertexArray; ++typedef struct ++{ ++ Vector *vertex; ++ int num_vertex; ++} ObjectSmooth; ++typedef struct ++{ ++ int num_cells; ++} State; ++static void *array_from_ObjectSmooth( ObjectSmooth *obj ) ++{ ++ int i, j; ++ VertexArray *array = (VertexArray *) __builtin_malloc( sizeof( VertexArray ) ); ++ array->vertex = (float *) __builtin_malloc( 3*sizeof(float)*obj->num_vertex ); ++ array->normal = (float *) __builtin_malloc( 3*sizeof(float)*obj->num_vertex ); ++ for (i=0, j=0; inum_vertex; ++i) { ++ array->normal[j++] = 9; ++ array->vertex[j] = obj->vertex[i].z; ++ array->normal[j++] = 1; ++ } ++} ++static void draw_cell( void ) ++{ ++ glCallList( array_from_ObjectSmooth( (ObjectSmooth *) __builtin_malloc(10) )); ++} ++static int render( State *st) ++{ ++ int b; ++ for (b=0; bnum_cells; ++b) { ++ draw_cell(); ++ draw_cell(); ++ } ++} ++reshape_glcells( int width, int height ) ++{ ++ render( 0 ); ++} +--- a/src/gcc/testsuite/gcc.dg/graphite/run-id-pr46758.c ++++ b/src/gcc/testsuite/gcc.dg/graphite/run-id-pr46758.c +@@ -0,0 +1,18 @@ ++int ++movegt (int y, long long a) ++{ ++ int i; ++ int ret = 0; ++ for (i = 0; i < y; i++) ++ if (a == -1LL << 33) ++ ret = -1; ++ return ret; ++} ++ ++int ++main () ++{ ++ if (movegt (1, -1LL << 33) != -1) ++ __builtin_abort (); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.dg/memcpy-3.c ++++ b/src/gcc/testsuite/gcc.dg/memcpy-3.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-rtl-expand" } */ ++ ++void ++f1 (char *p) ++{ ++ __builtin_memcpy (p, "123", 3); ++} ++ ++/* { dg-final { scan-rtl-dump-times "mem/s/u:" 3 "expand" { target mips*-*-* } } } */ ++/* { dg-final { cleanup-rtl-dump "expand" } } */ +--- a/src/gcc/testsuite/gcc.dg/pr28685-1.c ++++ b/src/gcc/testsuite/gcc.dg/pr28685-1.c +@@ -0,0 +1,50 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-tree-optimized" } */ ++ ++/* Should produce <=. */ ++int test1 (int a, int b) ++{ ++ return (a < b || a == b); ++} ++ ++/* Should produce <=. */ ++int test2 (int a, int b) ++{ ++ int lt = a < b; ++ int eq = a == b; ++ ++ return (lt || eq); ++} ++ ++/* Should produce <= (just deleting redundant test). */ ++int test3 (int a, int b) ++{ ++ int lt = a <= b; ++ int eq = a == b; ++ ++ return (lt || eq); ++} ++ ++/* Should produce <= (operands reversed to test the swap logic). */ ++int test4 (int a, int b) ++{ ++ int lt = a < b; ++ int eq = b == a; ++ ++ return (lt || eq); ++} ++ ++/* Should produce constant 0. */ ++int test5 (int a, int b) ++{ ++ int lt = a < b; ++ int eq = a == b; ++ ++ return (lt && eq); ++} ++ ++/* { dg-final { scan-tree-dump-times " <= " 4 "optimized" } } */ ++/* { dg-final { scan-tree-dump-times "return 0" 1 "optimized" } } */ ++/* { dg-final { scan-tree-dump-not " < " "optimized" } } */ ++/* { dg-final { scan-tree-dump-not " == " "optimized" } } */ ++/* { dg-final { cleanup-tree-dump "optimized" } } */ +--- a/src/gcc/testsuite/gcc.dg/pr28796-2.c ++++ b/src/gcc/testsuite/gcc.dg/pr28796-2.c +@@ -2,6 +2,7 @@ + /* { dg-options "-O2 -funsafe-math-optimizations -fno-finite-math-only -DUNSAFE" } */ + /* { dg-add-options ieee } */ + /* { dg-skip-if "No Inf/NaN support" { spu-*-* } } */ ++/* { dg-skip-if "Bug in _Q_dtoq" { sparc*-sun-solaris2.8 } } */ + + #include "tg-tests.h" + +--- a/src/gcc/testsuite/gcc.dg/pr39874.c ++++ b/src/gcc/testsuite/gcc.dg/pr39874.c +@@ -0,0 +1,29 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-tree-optimized" } */ ++ ++extern void func(); ++ ++void test1(char *signature) ++{ ++ char ch = signature[0]; ++ if (ch == 15 || ch == 3) ++ { ++ if (ch == 15) func(); ++ } ++} ++ ++ ++void test2(char *signature) ++{ ++ char ch = signature[0]; ++ if (ch == 15 || ch == 3) ++ { ++ if (ch > 14) func(); ++ } ++} ++ ++/* { dg-final { scan-tree-dump-times " == 15" 2 "optimized" } } */ ++/* { dg-final { scan-tree-dump-not " == 3" "optimized" } } */ ++/* { dg-final { cleanup-tree-dump "optimized" } } */ ++ ++ +--- a/src/gcc/testsuite/gcc.dg/pr44290-1.c ++++ b/src/gcc/testsuite/gcc.dg/pr44290-1.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile { target arm*-*-* avr-*-* mcore-*-* rx-*-* spu-*-* } } */ ++/* { dg-options "-O2 -fdump-tree-optimized" } */ ++ ++static void __attribute__((naked)) ++foo(void *from, void *to) ++{ ++ asm volatile("dummy"::"r"(from), "r"(to)); ++} ++ ++unsigned int fie[2]; ++ ++void fum(void *to) ++{ ++ foo(fie, to); ++} ++ ++/* { dg-final { scan-tree-dump "foo \\\(void \\\* from, void \\\* to\\\)" "optimized" } } */ ++/* { dg-final { cleanup-tree-dump "optimized" } } */ +--- a/src/gcc/testsuite/gcc.dg/pr44290-2.c ++++ b/src/gcc/testsuite/gcc.dg/pr44290-2.c +@@ -0,0 +1,24 @@ ++/* { dg-do compile { target arm*-*-* avr-*-* mcore-*-* rx-*-* spu-*-* } } */ ++/* { dg-options "-O2 -fdump-tree-optimized" } */ ++ ++static unsigned long __attribute__((naked)) ++foo (unsigned long base) ++{ ++ asm volatile ("dummy"); ++} ++unsigned long ++bar (void) ++{ ++ static int start, set; ++ ++ if (!set) ++ { ++ set = 1; ++ start = foo (0); ++ } ++ ++ return foo (start); ++} ++ ++/* { dg-final { scan-tree-dump "foo \\\(long unsigned int base\\\)" "optimized" } } */ ++/* { dg-final { cleanup-tree-dump "optimized" } } */ +--- a/src/gcc/testsuite/gcc.dg/pr44404.c ++++ b/src/gcc/testsuite/gcc.dg/pr44404.c +@@ -0,0 +1,35 @@ ++/* PR rtl-optimization/44404 ++ foo() used to be miscompiled on ARM due to a bug in auto-inc-dec.c, ++ which resulted in "strb r1, [r1], #-36". */ ++ ++/* { dg-do run } */ ++/* { dg-options "-O2 -fno-unroll-loops" } */ ++ ++extern char *strcpy (char *, const char *); ++extern int strcmp (const char*, const char*); ++extern void abort (void); ++ ++char buf[128]; ++ ++void __attribute__((noinline)) ++bar (int a, const char *p) ++{ ++ if (strcmp (p, "0123456789abcdefghijklmnopqrstuvwxyz") != 0) ++ abort (); ++} ++ ++void __attribute__((noinline)) ++foo (int a) ++{ ++ if (a) ++ bar (0, buf); ++ strcpy (buf, "0123456789abcdefghijklmnopqrstuvwxyz"); ++ bar (0, buf); ++} ++ ++int ++main (void) ++{ ++ foo (0); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.dg/pr44606.c ++++ b/src/gcc/testsuite/gcc.dg/pr44606.c +@@ -0,0 +1,52 @@ ++/* PR target/44606 */ ++/* { dg-do run } */ ++/* { dg-options "-O2" } */ ++ ++#include ++ ++extern void abort (void); ++ ++ typedef struct _PixelPacket { unsigned char r, g, b; } ++ PixelPacket; ++#define ARRAYLEN(X) (sizeof(X)/sizeof(X[0])) ++PixelPacket q[6]; ++#define COLS (ARRAYLEN(q) - 1) ++PixelPacket p[2*COLS + 22]; ++#define Minify(POS, WEIGHT) do { \ ++ total_r += (WEIGHT)*(p[POS].r); \ ++ total_g += (WEIGHT)*(p[POS].g); \ ++ total_b += (WEIGHT)*(p[POS].b); \ ++} while (0) ++unsigned long columns = COLS; ++int main(void) ++{ ++ static const unsigned char answers[COLS] = { 31, 32, 34, 35, 36 }; ++ unsigned long x; ++ for (x = 0; x < sizeof(p)/sizeof(p[0]); x++) { ++ p[x].b = (x + 34) | 1; ++ } ++ for (x = 0; x < columns; x++) { ++ double total_r = 0, total_g = 0, total_b = 0; ++ double saved_r = 0, saved_g = 0, saved_b = 0; ++ Minify(2*x + 0, 3.0); ++ Minify(2*x + 1, 7.0); ++ Minify(2*x + 2, 7.0); ++ saved_r = total_r; ++ saved_g = total_g; ++ Minify(2*x + 11, 15.0); ++ Minify(2*x + 12, 7.0); ++ Minify(2*x + 18, 7.0); ++ Minify(2*x + 19, 15.0); ++ Minify(2*x + 20, 15.0); ++ Minify(2*x + 21, 7.0); ++ q[x].r = (unsigned char)(total_r/128.0 + 0.5); ++ q[x].g = (unsigned char)(total_g/128.0 + 0.5); ++ q[x].b = (unsigned char)(total_b/128.0 + 0.5); ++ fprintf(stderr, "r:%f g:%f b:%f\n", saved_r, saved_g, saved_b); ++ } ++ for (x = 0; x < COLS; x++) { ++ if (answers[x] != q[x].b) ++ abort(); ++ } ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.dg/pr45101.c ++++ b/src/gcc/testsuite/gcc.dg/pr45101.c +@@ -0,0 +1,15 @@ ++/* PR rtl-optimization/45101 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fgcse -fgcse-las" } */ ++ ++struct ++{ ++ int i; ++} *s; ++ ++extern void bar (void); ++ ++void foo () ++{ ++ !s ? s->i++ : bar (); ++} +--- a/src/gcc/testsuite/gcc.dg/pr45105.c ++++ b/src/gcc/testsuite/gcc.dg/pr45105.c +@@ -0,0 +1,27 @@ ++/* PR debug/45105 */ ++/* { dg-do compile } */ ++/* { dg-options "-Os -fcompare-debug" } */ ++ ++extern int *baz (int *, int *); ++ ++void ++bar (int *p1, int *p2) ++{ ++ int n = *baz (0, 0); ++ p1[n] = p2[n]; ++} ++ ++void ++foo (int *p, int l) ++{ ++ int a1[32]; ++ int a2[32]; ++ baz (a1, a2); ++ while (l) ++ { ++ if (l & 1) ++ p = baz (a2, p); ++ l--; ++ bar (a1, a2); ++ } ++} +--- a/src/gcc/testsuite/gcc.dg/pr45107.c ++++ b/src/gcc/testsuite/gcc.dg/pr45107.c +@@ -0,0 +1,13 @@ ++/* PR rtl-optimization/45107 */ ++/* { dg-do compile } */ ++/* { dg-options "-Os -fgcse-las" } */ ++ ++extern void bar(int *); ++ ++int foo (int *p) ++{ ++ int i = *p; ++ if (i != 1) ++ bar(&i); ++ *p = i; ++} +--- a/src/gcc/testsuite/gcc.dg/pr46620.c ++++ b/src/gcc/testsuite/gcc.dg/pr46620.c +@@ -0,0 +1,76 @@ ++/* PR tree-optimization/46620 */ ++/* SRA bitfield grouping used to lose track at padding bitfields in ++ the middle of a word. */ ++/* { dg-do run } */ ++/* { dg-options "-O2" } */ ++ ++#include ++ ++struct PCT ++{ ++ unsigned char pi1 : 4; ++ unsigned char pi2 : 3; ++ unsigned char pif : 5; ++ ++ unsigned char sl : 2; ++ unsigned char uc : 1; ++ unsigned char st : 1; ++ ++ unsigned char p : 1; ++ unsigned char cs : 1; ++ unsigned char ss : 1; ++ ++ unsigned char pc : 3; ++ unsigned char dmv : 4; ++ unsigned char cv : 4; ++}; ++ ++struct rt ++{ ++ struct rt* d; ++ void (*edo)(void * const); ++ short lId; ++ char dac; ++}; ++ ++struct pedr ++{ ++ struct rt re; ++ struct PCT pc; ++ unsigned char mid; ++} ; ++ ++void __attribute__((__noinline__)) ++rei(struct rt* const me, unsigned short anId, void *ad ) ++{ ++ asm volatile (""); ++} ++ ++void __attribute__((__noinline__)) ++pedrdo(void * const p) ++{ ++ asm volatile (""); ++} ++ ++void __attribute__((__noinline__)) ++pedri (struct pedr* const me, struct PCT ppc, unsigned char pmid) ++{ ++ rei(&(me->re), 0x7604, 0); ++ me->pc = ppc; ++ me->mid = pmid; ++ (me)->re.edo = pedrdo; ++} ++ ++int main() ++{ ++ struct PCT ps; ++ struct pedr pm; ++ ++ pm.pc.dmv = 0; ++ ps.dmv = 1; ++ pedri(&pm, ps, 32); ++ ++ if (pm.pc.dmv != 1) ++ abort (); ++ exit (0); ++} +--- a/src/gcc/testsuite/gcc.dg/pr46893.c ++++ b/src/gcc/testsuite/gcc.dg/pr46893.c +@@ -0,0 +1,13 @@ ++/* PR debug/46893 */ ++/* { dg-do compile } */ ++/* { dg-options "-O -g" } */ ++ ++void ++foo (void) ++{ ++ union { unsigned long long l; double d; } u = { 0x7ff0000000000000ULL }; ++ double v = 0, w = -u.d; ++ ++ if (w) ++ w = v; ++} +--- a/src/gcc/testsuite/gcc.dg/pr46909.c ++++ b/src/gcc/testsuite/gcc.dg/pr46909.c +@@ -0,0 +1,17 @@ ++/* PR tree-optimization/46909 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-tree-ifcombine" } */ ++ ++extern void abort (); ++ ++int ++__attribute__ ((__noinline__)) ++foo (unsigned int x) ++{ ++ if (! (x == 4 || x == 6) || (x == 2 || x == 6)) ++ return 1; ++ return -1; ++} ++ ++/* { dg-final { scan-tree-dump "optimizing two comparisons to x_\[0-9\]+\\(D\\) != 4" "ifcombine" } } */ ++/* { dg-final { cleanup-tree-dump "ifcombine" } } */ +--- a/src/gcc/testsuite/gcc.dg/pr47201.c ++++ b/src/gcc/testsuite/gcc.dg/pr47201.c +@@ -0,0 +1,18 @@ ++/* PR target/47201 */ ++/* { dg-do compile } */ ++/* { dg-options "-O -fpic -g" { target fpic } } */ ++ ++union U ++{ ++ __UINTPTR_TYPE__ m; ++ float d; ++} u; ++ ++int ++foo (void) ++{ ++ union U v = { ++ (__UINTPTR_TYPE__)&u ++ }; ++ return u.d == v.d; ++} +--- a/src/gcc/testsuite/gcc.dg/switch-bittest.c ++++ b/src/gcc/testsuite/gcc.dg/switch-bittest.c +@@ -0,0 +1,25 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-rtl-expand" } */ ++ ++const char * ++f (const char *p) ++{ ++ while (1) ++ { ++ switch (*p) ++ { ++ case 9: ++ case 10: ++ case 13: ++ case 32: ++ break; ++ default: ++ return p; ++ } ++ } ++} ++ ++/* { dg-final { scan-rtl-dump-times "jump_insn" 4 "expand" { target mips*-*-* } } } */ ++/* { dg-final { scan-rtl-dump-times "REG_BR_PROB" 2 "expand" { target mips*-*-* } } } */ ++/* { dg-final { scan-rtl-dump-times "lt " 1 "expand" { target mips*-*-* } } } */ ++/* { dg-final { cleanup-rtl-dump "expand" } } */ +--- a/src/gcc/testsuite/gcc.dg/switch-prob.c ++++ b/src/gcc/testsuite/gcc.dg/switch-prob.c +@@ -0,0 +1,25 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-rtl-expand" } */ ++ ++const char * ++f (const char *p) ++{ ++ while (1) ++ { ++ switch (*p) ++ { ++ case 9: ++ case 10: ++ case 13: ++ case 32: ++ break; ++ default: ++ return p; ++ } ++ } ++} ++ ++/* { dg-final { scan-rtl-dump-times "jump_insn" 4 "expand" { target mips*-*-* } } } */ ++/* { dg-final { scan-rtl-dump-times "REG_BR_PROB" 2 "expand" { target mips*-*-* } } } */ ++/* { dg-final { scan-rtl-dump-times "heuristics" 0 "expand" { target mips*-*-* } } } */ ++/* { dg-final { cleanup-rtl-dump "expand" } } */ +--- a/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c ++++ b/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ +-/* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */ ++/* { dg-require-effective-target arm_neon_fp16_ok } */ ++/* { dg-options "-mfp16-format=ieee" } */ ++/* { dg-add-options arm_neon_fp16 } */ + + #include "arm-fp16-ops.h" + +@@ -12,3 +13,5 @@ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */ +--- a/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c ++++ b/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ +-/* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon-fp16 -mfloat-abi=softfp" } */ ++/* { dg-require-effective-target arm_neon_fp16_ok } */ ++/* { dg-options "-mfp16-format=ieee -ffast-math" } */ ++/* { dg-add-options arm_neon_fp16 } */ + + #include "arm-fp16-ops.h" + +@@ -12,3 +13,5 @@ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */ + /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */ ++/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */ +--- a/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c ++++ b/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-mfp16-format=ieee" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm-fp16-ops.h" + +--- a/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c ++++ b/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c +@@ -1,7 +1,8 @@ + /* Test various operators on __fp16 and mixed __fp16/float operands. */ + /* { dg-do compile { target arm*-*-* } } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-mfp16-format=ieee -ffast-math" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm-fp16-ops.h" + +--- a/src/gcc/testsuite/gcc.dg/torture/pr47365.c ++++ b/src/gcc/testsuite/gcc.dg/torture/pr47365.c +@@ -0,0 +1,39 @@ ++/* { dg-do run } */ ++ ++struct A ++{ ++ int i; ++}; ++ ++struct B ++{ ++ struct A a[2]; ++}; ++ ++int i = 1; ++struct B b = { 0, 3 }; ++ ++static void ++test () ++{ ++ if (b.a[0].i != i) ++ { ++ int t = b.a[0].i; ++ b.a[0] = b.a[1]; ++ b.a[1].i = t; ++ } ++ ++ if (b.a[1].i == i) ++ __builtin_abort (); ++ ++ if (b.a[0].i == 0) ++ __builtin_abort (); ++} ++ ++int ++main () ++{ ++ test (); ++ return 0; ++} ++ +--- a/src/gcc/testsuite/gcc.dg/torture/pr47411.c ++++ b/src/gcc/testsuite/gcc.dg/torture/pr47411.c +@@ -0,0 +1,42 @@ ++/* { dg-do compile } */ ++ ++typedef long unsigned int size_t; ++ ++static __inline void * ++__inline_memcpy_chk (void *__dest, const void *__src, size_t __len) ++{ ++ return __builtin___memcpy_chk (__dest, __src, __len, __builtin_object_size (__dest, 0)); ++} ++ ++extern void *xmalloc (size_t) __attribute__ ((__malloc__)); ++ ++struct htab { void ** entries; }; ++ ++typedef struct htab *htab_t; ++ ++extern void ** htab_find_slot (htab_t, const void *); ++ ++enum mode_class { MODE_RANDOM, MODE_CC, MODE_INT, MAX_MODE_CLASS }; ++ ++struct mode_data ++{ ++ struct mode_data *next; ++ enum mode_class cl; ++}; ++ ++static const struct mode_data blank_mode = { 0, MAX_MODE_CLASS }; ++ ++static htab_t modes_by_name; ++ ++struct mode_data * ++new_mode (void) ++{ ++ struct mode_data *m ++ = ((struct mode_data *) xmalloc (sizeof (struct mode_data))); ++ ++ ((__builtin_object_size (m, 0) != (size_t) -1) ? __builtin___memcpy_chk (m, &blank_mode, sizeof (struct mode_data), __builtin_object_size (m, 0)) : __inline_memcpy_chk (m, &blank_mode, sizeof (struct mode_data))); ++ ++ *htab_find_slot (modes_by_name, m) = m; ++ ++ return m; ++} +--- a/src/gcc/testsuite/gcc.dg/torture/volatile-pic-1.c ++++ b/src/gcc/testsuite/gcc.dg/torture/volatile-pic-1.c +@@ -0,0 +1,20 @@ ++/* { dg-do run } */ ++/* { dg-require-visibility "" } */ ++/* { dg-require-effective-target fpic } */ ++/* { dg-options "-fPIC" } */ ++ ++volatile int x __attribute__((visibility("hidden"))); ++ ++void __attribute__((noinline)) bar (void) ++{ ++#if defined (__arm__) ++ asm volatile ("mov r3,%0" :: "r" (0xdeadbeef) : "r3"); ++#endif ++ (void) x; ++} ++ ++int main (void) ++{ ++ bar (); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr42585.c ++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr42585.c +@@ -32,6 +32,9 @@ + } + + /* The local aggregates . */ +-/* { dg-final { scan-tree-dump-times "struct _fat_ptr _ans" 0 "optimized"} } */ +-/* { dg-final { scan-tree-dump-times "struct _fat_ptr _T2" 0 "optimized"} } */ ++/* Whether the structs are totally scalarized or not depends on the ++ MOVE_RATIO macro defintion in the back end. The scalarization will ++ not take place when using small values for MOVE_RATIO. */ ++/* { dg-final { scan-tree-dump-times "struct _fat_ptr _ans" 0 "optimized" { target { ! "powerpc*-*-* arm-*-* sh*-*-* s390*-*-*" } } } } */ ++/* { dg-final { scan-tree-dump-times "struct _fat_ptr _T2" 0 "optimized" { target { ! "powerpc*-*-* arm-*-* sh*-*-* s390*-*-*" } } } } */ + /* { dg-final { cleanup-tree-dump "optimized" } } */ +--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr45144.c ++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr45144.c +@@ -0,0 +1,46 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-tree-optimized" } */ ++ ++void baz (unsigned); ++ ++extern unsigned buf[]; ++ ++struct A ++{ ++ unsigned a1:10; ++ unsigned a2:3; ++ unsigned:19; ++}; ++ ++union TMP ++{ ++ struct A a; ++ unsigned int b; ++}; ++ ++static unsigned ++foo (struct A *p) ++{ ++ union TMP t; ++ struct A x; ++ ++ x = *p; ++ t.a = x; ++ return t.b; ++} ++ ++void ++bar (unsigned orig, unsigned *new) ++{ ++ struct A a; ++ union TMP s; ++ ++ s.b = orig; ++ a = s.a; ++ if (a.a1) ++ baz (a.a2); ++ *new = foo (&a); ++} ++ ++/* { dg-final { scan-tree-dump "x = a;" "optimized"} } */ ++/* { dg-final { cleanup-tree-dump "optimized" } } */ +--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr47286.c ++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr47286.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } { "*" } { "" } } */ ++/* { dg-options "-O2 -fdump-tree-optimized" } */ ++ ++struct thread_info { int preempt_count; }; ++static inline struct thread_info *current_thread_info(void) ++{ ++ register struct thread_info *sp asm("esp"); ++ return sp; ++} ++void testcase(void) ++{ ++ current_thread_info()->preempt_count += 1; ++} ++ ++/* We have to make sure that alias analysis treats sp as pointing ++ to globals and thus the store not optimized away. */ ++ ++/* { dg-final { scan-tree-dump "->preempt_count =" "optimized" } } */ ++/* { dg-final { cleanup-tree-dump "optimized" } } */ +--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr47392.c ++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr47392.c +@@ -0,0 +1,42 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 -fdump-tree-pre-stats" } */ ++ ++struct A ++{ ++ int i; ++}; ++ ++struct B ++{ ++ struct A a[2]; ++}; ++ ++int i = 1; ++struct B b = { 0, 3 }; ++ ++static void ++test () ++{ ++ if (b.a[0].i != i) ++ { ++ int t = b.a[0].i; ++ b.a[0] = b.a[1]; ++ b.a[1].i = t; ++ } ++ ++ if (b.a[1].i == i) ++ __builtin_abort (); ++ ++ if (b.a[0].i == 0) ++ __builtin_abort (); ++} ++ ++int ++main () ++{ ++ test (); ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump "Eliminated: 1" "pre" } } */ ++/* { dg-final { cleanup-tree-dump "pre" } } */ +--- a/src/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c ++++ b/src/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c +@@ -46,5 +46,5 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { xfail { ! { vect_hw_misalign } } } } } */ ++/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { xfail { ! { vect_element_align } } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c ++++ b/src/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include "tree-vect.h" +--- a/src/gcc/testsuite/gcc.dg/vect/pr43430-1.c ++++ b/src/gcc/testsuite/gcc.dg/vect/pr43430-1.c +@@ -35,5 +35,5 @@ + return foo (data_ch1, data_ch2, 1); + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_condition } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.dg/vect/slp-25.c ++++ b/src/gcc/testsuite/gcc.dg/vect/slp-25.c +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include "tree-vect.h" +--- a/src/gcc/testsuite/gcc.dg/vect/slp-3.c ++++ b/src/gcc/testsuite/gcc.dg/vect/slp-3.c +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include +--- a/src/gcc/testsuite/gcc.dg/vect/slp-multitypes-2.c ++++ b/src/gcc/testsuite/gcc.dg/vect/slp-multitypes-2.c +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-do run { xfail { sparc*-*-* && ilp32 } } } PR rtl-opt/46603 */ + + #include + #include +--- a/src/gcc/testsuite/gcc.dg/vect/vect-109.c ++++ b/src/gcc/testsuite/gcc.dg/vect/vect-109.c +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include "tree-vect.h" +@@ -72,8 +73,8 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_hw_misalign } } } */ +-/* { dg-final { scan-tree-dump-times "not vectorized: unsupported unaligned store" 2 "vect" { xfail vect_hw_misalign } } } */ +-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 10 "vect" { target vect_hw_misalign } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_element_align } } } */ ++/* { dg-final { scan-tree-dump-times "not vectorized: unsupported unaligned store" 2 "vect" { xfail vect_element_align } } } */ ++/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 10 "vect" { target vect_element_align } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +--- a/src/gcc/testsuite/gcc.dg/vect/vect-42.c ++++ b/src/gcc/testsuite/gcc.dg/vect/vect-42.c +@@ -64,7 +64,7 @@ + + /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ + /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 3 "vect" { target vect_no_align } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { { ! vector_alignment_reachable } && { ! vect_hw_misalign } } } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { { ! vector_alignment_reachable } && { ! vect_element_align } } } } } */ + /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || { ! vector_alignment_reachable } } } } } */ + /* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || { ! vector_alignment_reachable } } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.dg/vect/vect-95.c ++++ b/src/gcc/testsuite/gcc.dg/vect/vect-95.c +@@ -56,14 +56,14 @@ + } + + /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { xfail {vect_hw_misalign} } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { xfail {vect_element_align} } } } */ + + /* For targets that support unaligned loads we version for the two unaligned + stores and generate misaligned accesses for the loads. For targets that + don't support unaligned loads we version for all four accesses. */ + +-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_hw_misalign} } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 2 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ ++/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align} } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */ + /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target vect_no_align } } } */ + /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 4 "vect" { target vect_no_align } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.dg/vect/vect-96.c ++++ b/src/gcc/testsuite/gcc.dg/vect/vect-96.c +@@ -45,5 +45,5 @@ + /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { target { {! vect_no_align} && vector_alignment_reachable } } } } */ + /* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { { vect_no_align } || {! vector_alignment_reachable} } } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 1 "vect" { target { vect_no_align || { {! vector_alignment_reachable} && {! vect_hw_misalign} } } } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 1 "vect" { target { vect_no_align || { {! vector_alignment_reachable} && {! vect_element_align} } } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c ++++ b/src/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include "tree-vect.h" +@@ -78,11 +79,11 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_hw_misalign} } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_hw_misalign} } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_element_align} } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_element_align} } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */ + /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail *-*-* } } } */ +-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ ++/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +--- a/src/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c ++++ b/src/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_int } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include "tree-vect.h" +@@ -85,11 +86,11 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_hw_misalign} } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_hw_misalign} } } } */ +-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_element_align} } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_element_align} } } } */ ++/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */ + /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 8 "vect" { xfail *-*-* } } } */ +-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ ++/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || vect_element_align } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +--- a/src/gcc/testsuite/gcc.dg/vect/vect-outer-5.c ++++ b/src/gcc/testsuite/gcc.dg/vect/vect-outer-5.c +@@ -1,4 +1,5 @@ + /* { dg-require-effective-target vect_float } */ ++/* { dg-add-options quad_vectors } */ + + #include + #include +--- a/src/gcc/testsuite/gcc.dg/vect/vect-reduc-6.c ++++ b/src/gcc/testsuite/gcc.dg/vect/vect-reduc-6.c +@@ -49,5 +49,6 @@ + } + + /* need -ffast-math to vectorizer these loops. */ +-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" } } */ ++/* ARM NEON passes -ffast-math to these tests, so expect this to fail. */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail arm_neon_ok } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.dg/vect/vect-shift-3.c ++++ b/src/gcc/testsuite/gcc.dg/vect/vect-shift-3.c +@@ -0,0 +1,37 @@ ++/* { dg-require-effective-target vect_shift } */ ++/* { dg-require-effective-target vect_int } */ ++ ++#include "tree-vect.h" ++ ++#define N 32 ++ ++unsigned short dst[N] __attribute__((aligned(N))); ++unsigned short src[N] __attribute__((aligned(N))); ++ ++__attribute__ ((noinline)) ++void array_shift(void) ++{ ++ int i; ++ for (i = 0; i < N; i++) ++ dst[i] = src[i] >> 3; ++} ++ ++int main() ++{ ++ volatile int i; ++ check_vect (); ++ ++ for (i = 0; i < N; i++) ++ src[i] = i << 3; ++ ++ array_shift (); ++ ++ for (i = 0; i < N; i++) ++ if (dst[i] != i) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.dg/vect/vect-shift-4.c ++++ b/src/gcc/testsuite/gcc.dg/vect/vect-shift-4.c +@@ -0,0 +1,37 @@ ++/* { dg-require-effective-target vect_shift_char } */ ++/* { dg-require-effective-target vect_int } */ ++ ++#include "tree-vect.h" ++ ++#define N 32 ++ ++unsigned char dst[N] __attribute__((aligned(N))); ++unsigned char src[N] __attribute__((aligned(N))); ++ ++__attribute__ ((noinline)) ++void array_shift(void) ++{ ++ int i; ++ for (i = 0; i < N; i++) ++ dst[i] = src[i] >> 3; ++} ++ ++int main() ++{ ++ volatile int i; ++ check_vect (); ++ ++ for (i = 0; i < N; i++) ++ src[i] = i << 3; ++ ++ array_shift (); ++ ++ for (i = 0; i < N; i++) ++ if (dst[i] != i) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.dg/vect/vect.exp ++++ b/src/gcc/testsuite/gcc.dg/vect/vect.exp +@@ -104,7 +104,12 @@ + } elseif [istarget "ia64-*-*"] { + set dg-do-what-default run + } elseif [is-effective-target arm_neon_ok] { +- lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp" ++ eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""] ++ # NEON does not support denormals, so is not used for vectorization by ++ # default to avoid loss of precision. We must pass -ffast-math to test ++ # vectorization of float operations. ++ lappend DEFAULT_VECTCFLAGS "-ffast-math" ++ lappend DEFAULT_VECTCFLAGS "-fno-unroll-loops" + if [is-effective-target arm_neon_hw] { + set dg-do-what-default run + } else { +--- a/src/gcc/testsuite/gcc.target/arm/eliminate.c ++++ b/src/gcc/testsuite/gcc.target/arm/eliminate.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++struct X ++{ ++ int c; ++}; ++ ++extern void bar(struct X *); ++ ++void foo () ++{ ++ struct X x; ++ bar (&x); ++ bar (&x); ++ bar (&x); ++} ++ ++/* { dg-final { scan-assembler-times "r0,\[\\t \]*sp" 3 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c ++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ +-/* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */ ++/* { dg-require-effective-target arm_neon_fp16_ok } */ ++/* { dg-options "-mfp16-format=ieee" } */ ++/* { dg-add-options arm_neon_fp16 } */ + + /* Test generation of VFP __fp16 instructions. */ + +--- a/src/gcc/testsuite/gcc.target/arm/frame-pointer-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/frame-pointer-1.c +@@ -0,0 +1,42 @@ ++/* Check local register variables using a register conventionally ++ used as the frame pointer aren't clobbered under high register pressure. */ ++/* { dg-do run } */ ++/* { dg-options "-Os -mthumb -fomit-frame-pointer" } */ ++ ++#include ++ ++int global=5; ++ ++void __attribute__((noinline)) foo(int p1, int p2, int p3, int p4) ++{ ++ if (global != 5 || p1 != 1 || p2 != 2 || p3 != 3 || p4 != 4) ++ abort(); ++} ++ ++int __attribute__((noinline)) test(int a, int b, int c, int d) ++{ ++ register unsigned long r __asm__("r7") = 0xdeadbeef; ++ int e; ++ ++ /* ABCD are live after the call which should be enough ++ to cause r7 to be used if it weren't for the register variable. */ ++ foo(a,b,c,d); ++ ++ e = 0; ++ __asm__ __volatile__ ("mov %0, %2" ++ : "=r" (e) ++ : "0" (e), "r" (r)); ++ ++ global = a+b+c+d; ++ ++ return e; ++} ++ ++int main() ++{ ++ if (test(1, 2, 3, 4) != 0xdeadbeef) ++ abort(); ++ if (global != 10) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/naked-3.c ++++ b/src/gcc/testsuite/gcc.target/arm/naked-3.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -Wall" } */ ++/* Check that we do not get warnings about missing return statements ++ or bogus looking noreturn functions. */ ++int __attribute__((naked)) ++foo(void) ++{ ++ __asm__ volatile ("mov r0, #1\r\nbx lr\n"); ++} ++ ++int __attribute__((naked,noreturn)) ++bar(void) ++{ ++ __asm__ volatile ("frob r0\n"); ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon/polytypes.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/polytypes.c +@@ -3,7 +3,7 @@ + + /* { dg-do compile } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-add-options arm_neon } */ + + #include + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshls64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshls64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); + } + +-/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); + } + +-/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); + } + +-/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabals16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabals16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vabal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabals32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabals32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vabal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabals8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabals8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vabal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabalu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabalu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vabal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabalu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabalu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vabal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabalu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabalu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vabal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabas16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabas16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabas32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabas32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabas8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabas8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabau16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabau16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabau32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabau32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabau8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabau8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vabdl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabdl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vabdl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabdl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vabdl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabdl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vabdl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabdl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vabdl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabdl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vabdl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabdl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabds16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabds16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabds32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabds32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabds8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabds8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabdu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vabsq_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vabsq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vabsq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vabsq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabsf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vabs_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabss16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabss16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vabs_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabss32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabss32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vabs_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vabss8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vabss8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vabs_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vadds16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vadds16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vadds32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vadds32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vadds64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vadds64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vadds8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vadds8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddws16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddws16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vaddw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddws32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddws32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vaddw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddws8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddws8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vaddw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vaddw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vaddw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vaddw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vaddw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vandQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vandQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vandQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vandQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vandQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vandQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vandQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vandQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vands16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vands16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vands32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vands32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vands64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vands64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vands8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vands8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vandu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vandu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vandu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vandu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vandu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vandu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vandu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vandu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbics16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbics16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbics32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbics32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbics64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbics64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbics8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbics8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbicu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbicu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbicu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbicu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbsls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbsls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbsls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbsls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbsls64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbsls64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbsls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbsls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vbslu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcagef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcagef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcalef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcalef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vceqs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcequ16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcequ16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcequ32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcequ32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcequ8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcequ8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcges16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcges16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcges32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcges32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcges8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcges8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgts16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgts16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgts32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgts32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgts8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgts8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcles16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcles16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcles32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcles32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcles8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcles8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcleu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcleu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcleu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vclsq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vclsq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vclsq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclss16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclss16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vcls_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclss32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclss32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vcls_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclss8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclss8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vcls_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcltf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclts16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclts16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclts32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclts32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclts8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclts8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcltu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcltu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcltu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vclzq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vclzq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vclzq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclzs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vclz_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclzs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vclz_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclzs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vclz_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclzu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vclz_u16 (arg0_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclzu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vclz_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vclzu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vclz_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vcntq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcntp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcnts8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcnts8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vcnt_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcntu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombines16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcombines16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombines32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcombines32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombines64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcombines64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombines8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcombines8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreates16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcreates16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreates32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcreates32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreates64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcreates64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreates8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcreates8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vdupq_n_f32 (arg0_float32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vdupq_n_s16 (arg0_int16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vdupq_n_s32 (arg0_int32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,4 @@ + out_int64x2_t = vdupq_n_s64 (arg0_int64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vdupq_n_s8 (arg0_int8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,4 @@ + out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vdup_n_f32 (arg0_float32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x4_t = vdup_n_p16 (arg0_poly16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8_t = vdup_n_p8 (arg0_poly8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vdup_n_s16 (arg0_int16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vdup_n_s32 (arg0_int32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,4 @@ + out_int64x1_t = vdup_n_s64 (arg0_int64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vdup_n_s8 (arg0_int8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vdup_n_u16 (arg0_uint16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vdup_n_u32 (arg0_uint32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,4 @@ + out_uint64x1_t = vdup_n_u64 (arg0_uint64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vdup_n_u8 (arg0_uint8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veorQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veorQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veorQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veorQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veorQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veorQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veorQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veorQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veors16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veors16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veors32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veors32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veors64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veors64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veors8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veors8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veoru16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veoru16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veoru32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veoru32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veoru64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veoru64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/veoru8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/veoru8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextQp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextQp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vexts16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vexts16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vexts32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vexts32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vexts64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vexts64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vexts8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vexts8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vextu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vextu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0); + } + +-/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c +@@ -2,7 +2,8 @@ + + /* { dg-do compile } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps" } */ ++/* { dg-add-options arm_neon } */ + + #include + +@@ -21,7 +22,7 @@ + return vshll_n_u32(a, 32); + } + +-/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,4 @@ + out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,4 @@ + out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vget_low_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vget_low_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vget_low_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vget_low_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhadds16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhadds16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhadds32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhadds32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhadds8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhadds8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_float32x4_t = vld1q_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly16x8_t = vld1q_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly8x16_t = vld1q_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int16x8_t = vld1q_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int32x4_t = vld1q_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int64x2_t = vld1q_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int8x16_t = vld1q_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint16x8_t = vld1q_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint32x4_t = vld1q_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint64x2_t = vld1q_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint8x16_t = vld1q_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_float32x4_t = vld1q_f32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly16x8_t = vld1q_p16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly8x16_t = vld1q_p8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int16x8_t = vld1q_s16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int32x4_t = vld1q_s32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int64x2_t = vld1q_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int8x16_t = vld1q_s8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint16x8_t = vld1q_u16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint32x4_t = vld1q_u32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint64x2_t = vld1q_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint8x16_t = vld1q_u8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_float32x2_t = vld1_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly16x4_t = vld1_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly8x8_t = vld1_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int16x4_t = vld1_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int32x2_t = vld1_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int64x1_t = vld1_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int8x8_t = vld1_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint16x4_t = vld1_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint32x2_t = vld1_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint64x1_t = vld1_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint8x8_t = vld1_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_float32x2_t = vld1_f32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly16x4_t = vld1_p16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly8x8_t = vld1_p8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int16x4_t = vld1_s16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int32x2_t = vld1_s32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int64x1_t = vld1_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int8x8_t = vld1_s8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint16x4_t = vld1_u16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint32x2_t = vld1_u32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint64x1_t = vld1_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld1u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint8x8_t = vld1_u8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_float32x4x2_t = vld2q_f32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_poly16x8x2_t = vld2q_p16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_poly8x16x2_t = vld2q_p8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_int16x8x2_t = vld2q_s16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_int32x4x2_t = vld2q_s32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_int8x16x2_t = vld2q_s8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_uint16x8x2_t = vld2q_u16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_uint32x4x2_t = vld2q_u32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_uint8x16x2_t = vld2q_u8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_float32x2x2_t = vld2_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly16x4x2_t = vld2_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly8x8x2_t = vld2_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int16x4x2_t = vld2_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int32x2x2_t = vld2_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int64x1x2_t = vld2_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int8x8x2_t = vld2_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint16x4x2_t = vld2_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint32x2x2_t = vld2_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint64x1x2_t = vld2_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint8x8x2_t = vld2_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_float32x2x2_t = vld2_f32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly16x4x2_t = vld2_p16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly8x8x2_t = vld2_p8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int16x4x2_t = vld2_s16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int32x2x2_t = vld2_s32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int64x1x2_t = vld2_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int8x8x2_t = vld2_s8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint16x4x2_t = vld2_u16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint32x2x2_t = vld2_u32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint64x1x2_t = vld2_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld2u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint8x8x2_t = vld2_u8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_float32x4x3_t = vld3q_f32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_poly16x8x3_t = vld3q_p16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_poly8x16x3_t = vld3q_p8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_int16x8x3_t = vld3q_s16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_int32x4x3_t = vld3q_s32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_int8x16x3_t = vld3q_s8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_uint16x8x3_t = vld3q_u16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_uint32x4x3_t = vld3q_u32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_uint8x16x3_t = vld3q_u8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_float32x2x3_t = vld3_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly16x4x3_t = vld3_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly8x8x3_t = vld3_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int16x4x3_t = vld3_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int32x2x3_t = vld3_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int64x1x3_t = vld3_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int8x8x3_t = vld3_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint16x4x3_t = vld3_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint32x2x3_t = vld3_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint64x1x3_t = vld3_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint8x8x3_t = vld3_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_float32x2x3_t = vld3_f32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly16x4x3_t = vld3_p16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly8x8x3_t = vld3_p8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int16x4x3_t = vld3_s16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int32x2x3_t = vld3_s32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int64x1x3_t = vld3_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int8x8x3_t = vld3_s8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint16x4x3_t = vld3_u16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint32x2x3_t = vld3_u32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint64x1x3_t = vld3_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld3u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint8x8x3_t = vld3_u8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_float32x4x4_t = vld4q_f32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_poly16x8x4_t = vld4q_p16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_poly8x16x4_t = vld4q_p8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_int16x8x4_t = vld4q_s16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_int32x4x4_t = vld4q_s32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_int8x16x4_t = vld4q_s8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_uint16x8x4_t = vld4q_u16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_uint32x4x4_t = vld4q_u32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,6 +15,6 @@ + out_uint8x16x4_t = vld4q_u8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_float32x2x4_t = vld4_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly16x4x4_t = vld4_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly8x8x4_t = vld4_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int16x4x4_t = vld4_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int32x2x4_t = vld4_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int64x1x4_t = vld4_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int8x8x4_t = vld4_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint16x4x4_t = vld4_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint32x2x4_t = vld4_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint64x1x4_t = vld4_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint8x8x4_t = vld4_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_float32x2x4_t = vld4_f32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly16x4x4_t = vld4_p16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_poly8x8x4_t = vld4_p8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int16x4x4_t = vld4_s16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int32x2x4_t = vld4_s32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int64x1x4_t = vld4_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_int8x8x4_t = vld4_s8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint16x4x4_t = vld4_u16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint32x2x4_t = vld4_u32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint64x1x4_t = vld4_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vld4u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -14,5 +15,5 @@ + out_uint8x8x4_t = vld4_u8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vminQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vminQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vminQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vminQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vminQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vminQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vminQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vminf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vminf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmins16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmins16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmins32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmins32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmins8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmins8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vminu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vminu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vminu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vminu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vminu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vminu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t); + } + +-/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); + } + +-/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t); + } + +-/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); + } + +-/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t); + } + +-/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t); + } + +-/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlals16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlals16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlals32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlals32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlals8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlals8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmlal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmlal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlas16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlas16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlas32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlas32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlas8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlas8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlau16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlau16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlau32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlau32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlau8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlau8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t); + } + +-/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); + } + +-/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t); + } + +-/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); + } + +-/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmlsl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmlsl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlss16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlss16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlss32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlss32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlss8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlss8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vmovq_n_f32 (arg0_float32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vmovq_n_s16 (arg0_int16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vmovq_n_s32 (arg0_int32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,4 @@ + out_int64x2_t = vmovq_n_s64 (arg0_int64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vmovq_n_s8 (arg0_int8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,4 @@ + out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vmov_n_f32 (arg0_float32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x4_t = vmov_n_p16 (arg0_poly16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8_t = vmov_n_p8 (arg0_poly8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vmov_n_s16 (arg0_int16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vmov_n_s32 (arg0_int32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,4 @@ + out_int64x1_t = vmov_n_s64 (arg0_int64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vmov_n_s8 (arg0_int8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vmov_n_u16 (arg0_uint16_t); + } + +-/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vmov_n_u32 (arg0_uint32_t); + } + +-/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,4 @@ + out_uint64x1_t = vmov_n_u64 (arg0_uint64_t); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vmov_n_u8 (arg0_uint8_t); + } + +-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vmovl_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmovl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x2_t = vmovl_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmovl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vmovl_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmovl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmovl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmovl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmovl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vmovn_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vmovn_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vmovn_s64 (arg0_int64x2_t); + } + +-/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t); + } + +-/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t); + } + +-/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t); + } + +-/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t); + } + +-/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmullp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmullp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vmull\.p8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.p8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmull\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmullu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmullu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmullu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmullu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmullu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmullu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmull\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmull\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmuls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmuls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmuls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmuls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmuls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmuls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmulu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vmvnq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vmvnq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vmvnq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vmvn_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vmvn_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vmvn_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vnegq_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vnegq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vnegq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vnegq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vnegf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vneg_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vnegs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vneg_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vnegs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vneg_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vnegs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vneg_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vornQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vornQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vornQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vornQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vornQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vornQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vornQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vornQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vornu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vornu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vornu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vornu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vornu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vornu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vornu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vornu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorrs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorrs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorrs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorrs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorru16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorru16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorru32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorru32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorru64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorru64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vorru8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vorru8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadals16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadals16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadals32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadals32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadals8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadals8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vpadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vpaddl_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x1_t = vpaddl_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vpaddl_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadds16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadds16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadds32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadds32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadds8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpadds8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vpmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vpmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vpmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vpmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vpmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vpmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vpmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpminf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpminf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vpmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmins16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpmins16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vpmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmins32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpmins32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vpmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmins8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpmins8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vpmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpminu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpminu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vpmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpminu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpminu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vpmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vpminu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vpminu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vpmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vpmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqrshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqrshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vqabsq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vqabsq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vqabsq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabss16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqabss16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vqabs_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabss32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqabss32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vqabs_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabss8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqabss8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vqabs_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqadds16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqadds16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqadds32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqadds32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqadds64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqadds64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqadds8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqadds8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); + } + +-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); + } + +-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t); + } + +-/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t); + } + +-/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vqmovn_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqmovn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vqmovn_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqmovn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vqmovn_s64 (arg0_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqmovn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vqmovn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vqmovn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vqmovn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqmovun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqmovun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqmovun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqmovun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vqnegq_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vqnegq_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vqnegq_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vqneg_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vqneg_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vqneg_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshls64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshls64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vqshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vrecpe_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vrev16q_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vrev16_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vrev32q_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vrev32q_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vrev32_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vrev32_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vrev64q_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vrev64q_s16 (arg0_int16x8_t); + } + +-/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vrev64q_s32 (arg0_int32x4_t); + } + +-/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vrev64q_s8 (arg0_int8x16_t); + } + +-/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vrev64_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vrev64_s16 (arg0_int16x4_t); + } + +-/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vrev64_s32 (arg0_int32x2_t); + } + +-/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vrev64_s8 (arg0_int8x8_t); + } + +-/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t); + } + +-/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t); + } + +-/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshll\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshll\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshll\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshls64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshls64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshlu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_f32 (arg0_float32_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_s16 (arg0_int16_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_s32 (arg0_int32_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_s64 (arg0_int64_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_s8 (arg0_int8_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_f32 (arg0_float32_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_p16 (arg0_poly16_t, arg1_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_p8 (arg0_poly8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_s16 (arg0_int16_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_s32 (arg0_int32_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_s64 (arg0_int64_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_s8 (arg0_int8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_u16 (arg0_uint16_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_u32 (arg0_uint32_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_u64 (arg0_uint64_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst1u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst1_u8 (arg0_uint8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_f32 (arg0_float32_t, arg1_float32x2x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_s16 (arg0_int16_t, arg1_int16x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_s32 (arg0_int32_t, arg1_int32x2x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_s64 (arg0_int64_t, arg1_int64x1x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_s8 (arg0_int8_t, arg1_int8x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst2u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_f32 (arg0_float32_t, arg1_float32x2x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_s16 (arg0_int16_t, arg1_int16x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_s32 (arg0_int32_t, arg1_int32x2x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_s64 (arg0_int64_t, arg1_int64x1x3_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_s8 (arg0_int8_t, arg1_int8x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst3u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,6 +16,6 @@ + vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4f32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_f32 (arg0_float32_t, arg1_float32x2x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4p16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4p16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4s16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_s16 (arg0_int16_t, arg1_int16x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4s32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_s32 (arg0_int32_t, arg1_int32x2x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4s64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_s64 (arg0_int64_t, arg1_int64x1x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_s8 (arg0_int8_t, arg1_int8x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4u16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4u32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4u64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vst4u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -15,5 +16,5 @@ + vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubls16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubls16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vsubl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubls32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubls32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vsubl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubls8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubls8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vsubl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsublu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsublu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vsubl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsublu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsublu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vsubl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsublu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsublu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vsubl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubs64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubu64.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,4 @@ + out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubws16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubws16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vsubw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubws32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubws32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vsubw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubws8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubws8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vsubw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vsubw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vsubw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vsubw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vsubw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -17,5 +18,5 @@ + out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrns16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrns16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrns32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrns32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrns8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrns8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtstp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtsts16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtsts16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtsts32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtsts32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtsts8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtsts8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtstu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtstu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vtstu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzps16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzps16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzps32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzps32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzps8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzps8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipf32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipf32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipp16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipp16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipp8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipp8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzips16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzips16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzips32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzips32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzips8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzips8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipu16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipu16.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipu32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipu32.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipu8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vzipu8.c +@@ -3,7 +3,8 @@ + + /* { dg-do assemble } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon } */ + + #include "arm_neon.h" + +@@ -16,5 +17,5 @@ + out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-cond-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-cond-1.c +@@ -1,6 +1,7 @@ + /* { dg-do run } */ + /* { dg-require-effective-target arm_neon_hw } */ +-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp" } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ + /* Check that the arm_final_prescan_insn ccfsm code does not try to + * conditionally execute NEON instructions. */ + #include +--- a/src/gcc/testsuite/gcc.target/arm/neon-modes-2.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-modes-2.c +@@ -0,0 +1,24 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O1" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++ ++#define SETUP(A) x##A = vld3_u32 (ptr + A * 0x20) ++#define MODIFY(A) x##A = vld3_lane_u32 (ptr + A * 0x20 + 0x10, x##A, 1) ++#define STORE(A) vst3_u32 (ptr + A * 0x20, x##A) ++ ++#define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5) ++ ++void ++bar (uint32_t *ptr, int y) ++{ ++ uint32x2x3_t MANY (SETUP); ++ int *x = __builtin_alloca (y); ++ int z[0x1000]; ++ foo (x, z); ++ MANY (MODIFY); ++ foo (x, z); ++ MANY (STORE); ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c +@@ -1,6 +1,8 @@ + /* { dg-do compile } */ + /* { dg-require-effective-target arm_neon_ok } */ +-/* { dg-options "-O2 -mthumb -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */ ++/* { dg-require-effective-target arm_thumb2_ok } */ ++/* { dg-options "-O2 -mthumb -march=armv7-a" } */ ++/* { dg-add-options arm_neon } */ + + #include + #include +--- a/src/gcc/testsuite/gcc.target/arm/neon-vadds64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vadds64.c +@@ -0,0 +1,21 @@ ++/* Test the `vadd_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)0x00000000deadbeefLL; ++ ++ out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0xdeadbeefdeadbeefLL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vaddu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vaddu64.c +@@ -0,0 +1,21 @@ ++/* Test the `vadd_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x00000000deadbeefLL; ++ ++ out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0xdeadbeefdeadbeefLL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vands64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vands64.c +@@ -0,0 +1,21 @@ ++/* Test the `vand_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; ++ ++ out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0xdead000000000000LL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vandu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vandu64.c +@@ -0,0 +1,21 @@ ++/* Test the `vand_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; ++ ++ out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vbics64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vbics64.c +@@ -0,0 +1,21 @@ ++/* Test the `vbic_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL); ++ ++ out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0xdead000000000000LL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vbicu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vbicu64.c +@@ -0,0 +1,21 @@ ++/* Test the `vbic_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL); ++ ++ out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-1.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++float32x4_t out_float32x4_t; ++void test_vdupq_nf32 (void) ++{ ++ out_float32x4_t = vdupq_n_f32 (0.0); ++} ++ ++/* { dg-final { scan-assembler "vmov\.f32\[ \]+\[qQ\]\[0-9\]+, #0\.0\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-10.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-10.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (~0x12000000); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #3992977407\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-11.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-11.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint16x8_t out_uint16x8_t; ++void test_vdupq_nu16 (void) ++{ ++ out_uint16x8_t = vdupq_n_u16 (0x12); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-12.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-12.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint16x8_t out_uint16x8_t; ++void test_vdupq_nu16 (void) ++{ ++ out_uint16x8_t = vdupq_n_u16 (0x1200); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-13.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-13.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint16x8_t out_uint16x8_t; ++void test_vdupq_nu16 (void) ++{ ++ out_uint16x8_t = vdupq_n_u16 (~0x12); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #65517\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-14.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-14.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint16x8_t out_uint16x8_t; ++void test_vdupq_nu16 (void) ++{ ++ out_uint16x8_t = vdupq_n_u16 (~0x1200); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #60927\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-15.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-15.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u8' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint8x16_t out_uint8x16_t; ++void test_vdupq_nu8 (void) ++{ ++ out_uint8x16_t = vdupq_n_u8 (0x12); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i8\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-16.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (0x12ff); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4863\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-17.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-17.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (0x12ffff); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #1245183\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-18.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-18.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (~0x12ff); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294962432\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-19.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-19.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (~0x12ffff); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4293722112\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-2.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-2.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++float32x4_t out_float32x4_t; ++void test_vdupq_nf32 (void) ++{ ++ out_float32x4_t = vdupq_n_f32 (0.125); ++} ++ ++/* { dg-final { scan-assembler "vmov\.f32\[ \]+\[qQ\]\[0-9\]+, #1\.25e-1\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-3.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-3.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (0x12); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-4.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-4.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (0x1200); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-5.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-5.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (0x120000); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #1179648\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-6.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-6.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (0x12000000); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #301989888\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-7.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-7.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (~0x12); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294967277\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-8.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-8.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (~0x1200); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294962687\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup-9.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup-9.c +@@ -0,0 +1,17 @@ ++/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint32x4_t out_uint32x4_t; ++void test_vdupq_nu32 (void) ++{ ++ out_uint32x4_t = vdupq_n_u32 (~0x120000); ++} ++ ++/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4293787647\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c +@@ -0,0 +1,22 @@ ++/* Test the `vdupq_lanes64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x2_t out_int64x2_t = {0, 0}; ++ int64_t arg0_int64_t = (int64_t) 0xdeadbeef; ++ ++ out_int64x2_t = vdupq_lane_s64 ((int64x1_t)arg0_int64_t, 0); ++ if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) ++ abort(); ++ if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c +@@ -0,0 +1,22 @@ ++/* Test the `vdupq_laneu64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x2_t out_uint64x2_t = {0, 0}; ++ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; ++ ++ out_uint64x2_t = vdupq_lane_u64 ((uint64x1_t)arg0_uint64_t, 0); ++ if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) ++ abort(); ++ if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c +@@ -0,0 +1,22 @@ ++/* Test the `vdupq_ns64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x2_t out_int64x2_t = {0, 0}; ++ int64_t arg0_int64_t = (int64_t) 0xdeadbeef; ++ ++ out_int64x2_t = vdupq_n_s64 (arg0_int64_t); ++ if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) ++ abort(); ++ if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c +@@ -0,0 +1,22 @@ ++/* Test the `vdupq_nu64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x2_t out_uint64x2_t = {0, 0}; ++ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; ++ ++ out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t); ++ if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) ++ abort(); ++ if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c +@@ -0,0 +1,20 @@ ++/* Test the `vdup_ns64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64_t arg0_int64_t = (int64_t) 0xdeadbeef; ++ ++ out_int64x1_t = vdup_n_s64 (arg0_int64_t); ++ if ((int64_t)out_int64x1_t != arg0_int64_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c +@@ -0,0 +1,20 @@ ++/* Test the `vdup_nu64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; ++ ++ out_uint64x1_t = vdup_n_u64 (arg0_uint64_t); ++ if ((uint64_t)out_uint64x1_t != arg0_uint64_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-veors64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-veors64.c +@@ -0,0 +1,21 @@ ++/* Test the `veor_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; ++ ++ out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0x0000beef0000beefLL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-veoru64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-veoru64.c +@@ -0,0 +1,21 @@ ++/* Test the `veor_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; ++ ++ out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0x0000beef0000beefLL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c +@@ -0,0 +1,20 @@ ++/* Test the `vget_lane_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64_t out_int64_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL; ++ ++ out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0); ++ if (out_int64_t != (int64_t)arg0_int64x1_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c +@@ -0,0 +1,20 @@ ++/* Test the `vget_lane_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64_t out_uint64_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL; ++ ++ out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0); ++ if (out_uint64_t != (uint64_t)arg0_uint64x1_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vld-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vld-1.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O1" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++uint8x16_t ++foo (uint8_t *a, uint8x16_t b) ++{ ++ vst1q_lane_u8 (a, b, 14); ++ return vld1q_lane_u8 (a + 0x100, b, 15); ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vmla-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vmla-1.c +@@ -1,5 +1,6 @@ + /* { dg-require-effective-target arm_neon_hw } */ +-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ ++/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ ++/* { dg-add-options arm_neon } */ + /* { dg-final { scan-assembler "vmla\\.f32" } } */ + + /* Verify that VMLA is used. */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vmls-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vmls-1.c +@@ -1,5 +1,6 @@ + /* { dg-require-effective-target arm_neon_hw } */ +-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ ++/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ ++/* { dg-add-options arm_neon } */ + /* { dg-final { scan-assembler "vmls\\.f32" } } */ + + /* Verify that VMLS is used. */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c +@@ -0,0 +1,22 @@ ++/* Test the `vmovq_ns64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x2_t out_int64x2_t = {0, 0}; ++ int64_t arg0_int64_t = (int64_t) 0xdeadbeef; ++ ++ out_int64x2_t = vmovq_n_s64 (arg0_int64_t); ++ if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) ++ abort(); ++ if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c +@@ -0,0 +1,23 @@ ++/* Test the `vmovq_nu64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x2_t out_uint64x2_t = {0, 0}; ++ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; ++ ++ out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t); ++ if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) ++ abort(); ++ if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) ++ abort(); ++ return 0; ++} ++ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c +@@ -0,0 +1,20 @@ ++/* Test the `vmov_ns64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64_t arg0_int64_t = (int64_t) 0xdeadbeef; ++ ++ out_int64x1_t = vmov_n_s64 (arg0_int64_t); ++ if ((int64_t)out_int64x1_t != arg0_int64_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c +@@ -0,0 +1,20 @@ ++/* Test the `vmov_nu64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; ++ ++ out_uint64x1_t = vmov_n_u64 (arg0_uint64_t); ++ if ((uint64_t)out_uint64x1_t != arg0_uint64_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vorns64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vorns64.c +@@ -0,0 +1,21 @@ ++/* Test the `vorn_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL); ++ ++ out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vornu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vornu64.c +@@ -0,0 +1,21 @@ ++/* Test the `vorn_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL); ++ ++ out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vorrs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vorrs64.c +@@ -0,0 +1,21 @@ ++/* Test the `vorr_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; ++ ++ out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vorru64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vorru64.c +@@ -0,0 +1,21 @@ ++/* Test the `vorr_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; ++ ++ out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c +@@ -0,0 +1,21 @@ ++/* Test the `vset_lane_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64_t arg0_int64_t = 0xf00f00f00LL; ++ int64x1_t arg1_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL; ++ ++ out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); ++ if ((int64_t)out_int64x1_t != arg0_int64_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c +@@ -0,0 +1,21 @@ ++/* Test the `vset_lane_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64_t arg0_uint64_t = 0xf00f00f00LL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL; ++ ++ out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); ++ if ((uint64_t)out_uint64x1_t != arg0_uint64_t) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vsubs64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vsubs64.c +@@ -0,0 +1,21 @@ ++/* Test the `vsub_s64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ int64x1_t out_int64x1_t = 0; ++ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeefdeadbeefLL; ++ int64x1_t arg1_int64x1_t = (int64x1_t)0x0000beefdead0000LL; ++ ++ out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t); ++ if (out_int64x1_t != (int64x1_t)0xdead00000000beefLL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vsubu64.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vsubu64.c +@@ -0,0 +1,21 @@ ++/* Test the `vsub_u64' ARM Neon intrinsic. */ ++ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O0" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++#include ++ ++int main (void) ++{ ++ uint64x1_t out_uint64x1_t = 0; ++ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeefdeadbeefLL; ++ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x0000beefdead0000LL; ++ ++ out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); ++ if (out_uint64x1_t != (uint64x1_t)0xdead00000000beefLL) ++ abort(); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/pr39839.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr39839.c +@@ -0,0 +1,24 @@ ++/* { dg-options "-mthumb -Os -march=armv5te -mthumb-interwork -fpic" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */ ++ ++struct S ++{ ++ int count; ++ char *addr; ++}; ++ ++void func(const char*, const char*, int, const char*); ++ ++/* This function should not need to spill to the stack. */ ++void test(struct S *p) ++{ ++ int off = p->count; ++ while (p->count >= 0) ++ { ++ const char *s = "xyz"; ++ if (*p->addr) s = "pqr"; ++ func("abcde", p->addr + off, off, s); ++ p->count--; ++ } ++} +--- a/src/gcc/testsuite/gcc.target/arm/pr40657-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr40657-1.c +@@ -0,0 +1,13 @@ ++/* { dg-options "-Os -march=armv5te -mthumb" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-final { scan-assembler "pop.*r1.*pc" } } */ ++/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */ ++/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */ ++ ++extern void bar(int*); ++int foo() ++{ ++ int x; ++ bar(&x); ++ return x; ++} +--- a/src/gcc/testsuite/gcc.target/arm/pr40657-2.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr40657-2.c +@@ -0,0 +1,20 @@ ++/* { dg-options "-Os -march=armv4t -mthumb" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */ ++/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */ ++ ++/* Here, we test that if there's a pop of r[4567] in the epilogue, ++ add sp,sp,#12 is removed and replaced by three additional pops ++ of lower-numbered regs. */ ++ ++extern void bar(int*); ++ ++int t1, t2, t3, t4, t5; ++int foo() ++{ ++ int i,j,k,x = 0; ++ for (i = 0; i < t1; i++) ++ for (j = 0; j < t2; j++) ++ bar(&x); ++ return x; ++} +--- a/src/gcc/testsuite/gcc.target/arm/pr40900.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr40900.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fno-optimize-sibling-calls" } */ ++ ++extern short shortv2(); ++short shortv1() ++{ ++ return shortv2(); ++} ++ ++/* { dg-final { scan-assembler-not "lsl" } } */ ++/* { dg-final { scan-assembler-not "asr" } } */ ++/* { dg-final { scan-assembler-not "sxth" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/pr40956.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr40956.c +@@ -0,0 +1,14 @@ ++/* { dg-options "-mthumb -Os -fpic -march=armv5te" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-require-effective-target fpic } */ ++/* Make sure the constant "0" is loaded into register only once. */ ++/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 } } */ ++ ++int foo(int p, int* q) ++{ ++ if (p!=9) ++ *q = 0; ++ else ++ *(q+1) = 0; ++ return 3; ++} +--- a/src/gcc/testsuite/gcc.target/arm/pr42172-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr42172-1.c +@@ -0,0 +1,19 @@ ++/* { dg-options "-O2" } */ ++ ++struct A { ++ unsigned int f1 : 3; ++ unsigned int f2 : 3; ++ unsigned int f3 : 1; ++ unsigned int f4 : 1; ++ ++}; ++ ++void init_A (struct A *this) ++{ ++ this->f1 = 0; ++ this->f2 = 1; ++ this->f3 = 0; ++ this->f4 = 0; ++} ++ ++/* { dg-final { scan-assembler-times "ldr" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/pr42235.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr42235.c +@@ -0,0 +1,11 @@ ++/* { dg-options "-mthumb -O2 -march=armv5te" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-final { scan-assembler-not "add\[\\t \]*r.,\[\\t \]*r.,\[\\t \]*\#1" } } */ ++/* { dg-final { scan-assembler-not "add\[\\t \]*r.,\[\\t \]*\#1" } } */ ++ ++#include ++ ++int foo (char *x) ++{ ++ memset (x, 0, 6); ++} +--- a/src/gcc/testsuite/gcc.target/arm/pr42495.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr42495.c +@@ -0,0 +1,31 @@ ++/* { dg-options "-mthumb -Os -fpic -march=armv5te -fdump-rtl-hoist" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-require-effective-target fpic } */ ++/* Make sure all calculations of gObj's address get hoisted to one location. */ ++/* { dg-final { scan-rtl-dump "PRE/HOIST: end of bb .* copying expression" "hoist" } } */ ++ ++struct st_a { ++ int data; ++}; ++ ++struct st_b { ++ struct st_a *p_a; ++ struct st_b *next; ++}; ++ ++extern struct st_b gObj; ++extern void foo(int, struct st_b*); ++ ++int goo(struct st_b * obj) { ++ struct st_a *pa; ++ if (gObj.p_a->data != 0) { ++ foo(gObj.p_a->data, obj); ++ } ++ pa = obj->p_a; ++ if (pa == 0) { ++ return 0; ++ } else if (pa == gObj.p_a) { ++ return 0; ++ } ++ return pa->data; ++} +--- a/src/gcc/testsuite/gcc.target/arm/pr42496.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr42496.c +@@ -0,0 +1,16 @@ ++/* { dg-options "-O2" } */ ++ ++void foo(int i) ++{ ++ extern int j; ++ ++ if (i) { ++ j = 10; ++ } ++ else { ++ j = 20; ++ } ++} ++ ++/* { dg-final { scan-assembler-not "strne" } } */ ++/* { dg-final { scan-assembler-not "streq" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/pr42505.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr42505.c +@@ -0,0 +1,23 @@ ++/* { dg-options "-mthumb -Os -march=armv5te" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */ ++ ++struct A { ++ int f1; ++ int f2; ++}; ++ ++int func(int c); ++ ++/* This function should not need to spill anything to the stack. */ ++int test(struct A* src, struct A* dst, int count) ++{ ++ while (count--) { ++ if (!func(src->f2)) { ++ return 0; ++ } ++ *dst++ = *src++; ++ } ++ ++ return 1; ++} +--- a/src/gcc/testsuite/gcc.target/arm/pr42574.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr42574.c +@@ -0,0 +1,24 @@ ++/* { dg-options "-mthumb -Os -fpic -march=armv5te" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++/* { dg-require-effective-target fpic } */ ++/* Make sure the address of glob.c is calculated only once and using ++ a logical shift for the offset (200<<1). */ ++/* { dg-final { scan-assembler-times "lsl" 1 } } */ ++ ++struct A { ++ char a[400]; ++ float* c; ++}; ++struct A glob; ++void func(); ++void func1(float*); ++int func2(float*, int*); ++void func3(float*); ++ ++void test(int *p) { ++ func1(glob.c); ++ if (func2(glob.c, p)) { ++ func(); ++ } ++ func3(glob.c); ++} +--- a/src/gcc/testsuite/gcc.target/arm/pr42835.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr42835.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mthumb -Os" } */ ++/* { dg-require-effective-target arm_thumb2_ok } */ ++ ++int foo(int *p, int i) ++{ ++ return( (i < 0 && *p == 1) ++ || (i > 0 && *p == 2) ); ++} ++ ++/* { dg-final { scan-assembler-times "movne\[\\t \]*r.,\[\\t \]*#" 1 } } */ ++/* { dg-final { scan-assembler-times "moveq\[\\t \]*r.,\[\\t \]*#" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/pr44788.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr44788.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_thumb2_ok } */ ++/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */ ++ ++void joint_decode(float* mlt_buffer1, int t) { ++ int i; ++ float decode_buffer[1060]; ++ foo(decode_buffer); ++ for (i=0; i<10 ; i++) { ++ mlt_buffer1[i] = i * decode_buffer[t]; ++ } ++} +--- a/src/gcc/testsuite/gcc.target/arm/pr45094.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr45094.c +@@ -0,0 +1,27 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O2 -mcpu=cortex-a8" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include ++ ++long long buffer[32]; ++ ++void __attribute__((noinline)) f(long long *p, int n) ++{ ++ while (--n >= 0) ++ { ++ *p = 1; ++ p += 32; ++ } ++} ++ ++int main(void) ++{ ++ f(buffer, 1); ++ ++ if (!buffer[0]) ++ abort(); ++ ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/pr45447.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr45447.c +@@ -0,0 +1,3 @@ ++/* { dg-do compile } */ ++/* { dg-options "-g -femit-struct-debug-baseonly" } */ ++typedef __builtin_va_list x; +--- a/src/gcc/testsuite/gcc.target/arm/pr46883.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr46883.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1 -march=armv5te" } */ ++ ++void bar (unsigned char *q, unsigned short *data16s, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++) ++ { ++ q[2 * i] = ++ (((data16s[i] & 0xFF) << 8) | ((data16s[i] >> 8) & 0xFF)) & 0xFF; ++ q[2 * i + 1] = ++ ((unsigned short) ++ (((data16s[i] & 0xFF) << 8) | ((data16s[i] >> 8) & 0xFF))) >> 8; ++ } ++} +--- a/src/gcc/testsuite/gcc.target/arm/sync-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/sync-1.c +@@ -0,0 +1,25 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 -march=armv7-a" } */ ++ ++volatile int mem; ++ ++int ++bar (int x, int y) ++{ ++ if (x) ++ __sync_fetch_and_add(&mem, y); ++ return 0; ++} ++ ++extern void abort (void); ++ ++int ++main (int argc, char *argv[]) ++{ ++ mem = 0; ++ bar (0, 1); ++ bar (1, 1); ++ if (mem != 1) ++ abort (); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/synchronize.c ++++ b/src/gcc/testsuite/gcc.target/arm/synchronize.c +@@ -1,4 +1,4 @@ +-/* { dg-final { scan-assembler "__sync_synchronize" { target arm*-*-linux-*eabi } } } */ ++/* { dg-final { scan-assembler "__sync_synchronize|dmb|mcr" { target arm*-*-linux-*eabi } } } */ + + void *foo (void) + { +--- a/src/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c ++++ b/src/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mthumb -Os" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++ ++int ldrb(unsigned char* p) ++{ ++ if (p[8] <= 0x7F) ++ return 2; ++ else ++ return 5; ++} ++ ++ ++/* { dg-final { scan-assembler "127" } } */ ++/* { dg-final { scan-assembler "bhi" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/thumb-comparisons.c ++++ b/src/gcc/testsuite/gcc.target/arm/thumb-comparisons.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mthumb -Os" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++ ++int foo(char ch) ++{ ++ switch (ch) { ++ case '-': ++ case '?': ++ case '/': ++ case 99: ++ return 1; ++ default: ++ return 0; ++ } ++} ++ ++/* { dg-final { scan-assembler-times "cmp\[\\t \]*r.,\[\\t \]*#63" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/thumb-stackframe.c ++++ b/src/gcc/testsuite/gcc.target/arm/thumb-stackframe.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mthumb -Os" } */ ++/* { dg-require-effective-target arm_thumb1_ok } */ ++ ++extern void bar(int*); ++int foo() ++{ ++ int x; ++ bar(&x); ++ return x; ++} ++ ++/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp," } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c ++++ b/src/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++extern void bar (double); ++ ++void ++foo (double *p, double a, int n) ++{ ++ do ++ bar (*--p + a); ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fldmdbd" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c ++++ b/src/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++extern void baz (float); ++ ++void ++foo (float *p, float a, int n) ++{ ++ do ++ bar (*--p + a); ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fldmdbs" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c ++++ b/src/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++extern void bar (double); ++ ++void ++foo (double *p, double a, int n) ++{ ++ do ++ bar (*p++ + a); ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fldmiad" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vfp-ldmias.c ++++ b/src/gcc/testsuite/gcc.target/arm/vfp-ldmias.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++extern void baz (float); ++ ++void ++foo (float *p, float a, int n) ++{ ++ do ++ bar (*p++ + a); ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fldmias" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c ++++ b/src/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++void ++foo (double *p, double a, double b, int n) ++{ ++ double c = a + b; ++ do ++ *--p = c; ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fstmdbd" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c ++++ b/src/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++void ++foo (float *p, float a, float b, int n) ++{ ++ float c = a + b; ++ do ++ *--p = c; ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fstmdbs" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vfp-stmiad.c ++++ b/src/gcc/testsuite/gcc.target/arm/vfp-stmiad.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++void ++foo (double *p, double a, double b, int n) ++{ ++ double c = a + b; ++ do ++ *p++ = c; ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fstmiad" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vfp-stmias.c ++++ b/src/gcc/testsuite/gcc.target/arm/vfp-stmias.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_vfp_ok } */ ++/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ ++ ++void ++foo (float *p, float a, float b, int n) ++{ ++ float c = a + b; ++ do ++ *p++ = c; ++ while (n--); ++} ++ ++/* { dg-final { scan-assembler "fstmias" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c +@@ -0,0 +1,18 @@ ++/* { dg-require-effective-target arm_eabi } */ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++typedef struct { ++ char a:1; ++ char b:7; ++ int c; ++} BitStruct; ++ ++volatile BitStruct bits; ++ ++int foo () ++{ ++ return bits.b; ++} ++ ++/* { dg-final { scan-assembler "ldrb\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c ++++ b/src/gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c +@@ -0,0 +1,18 @@ ++/* { dg-require-effective-target arm_eabi } */ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++typedef struct { ++ volatile unsigned long a:8; ++ volatile unsigned long b:8; ++ volatile unsigned long c:16; ++} BitStruct; ++ ++BitStruct bits; ++ ++unsigned long foo () ++{ ++ return bits.b; ++} ++ ++/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c ++++ b/src/gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c +@@ -0,0 +1,18 @@ ++/* { dg-require-effective-target arm_eabi } */ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++typedef struct { ++ volatile unsigned long a:8; ++ volatile unsigned long b:8; ++ volatile unsigned long c:16; ++} BitStruct; ++ ++BitStruct bits; ++ ++unsigned long foo () ++{ ++ return bits.c; ++} ++ ++/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c ++++ b/src/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c +@@ -0,0 +1,30 @@ ++/* { dg-require-effective-target arm_eabi } */ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++/* { dg-final { scan-assembler-times "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */ ++/* { dg-final { scan-assembler-times "str\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */ ++/* { dg-final { scan-assembler-not "strb" } } */ ++ ++struct thing { ++ unsigned a: 8; ++ unsigned b: 8; ++ unsigned c: 8; ++ unsigned d: 8; ++}; ++ ++struct thing2 { ++ volatile unsigned a: 8; ++ volatile unsigned b: 8; ++ volatile unsigned c: 8; ++ volatile unsigned d: 8; ++}; ++ ++void test1(volatile struct thing *t) ++{ ++ t->a = 5; ++} ++ ++void test2(struct thing2 *t) ++{ ++ t->a = 5; ++} +--- a/src/gcc/testsuite/gcc.target/arm/wmul-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/wmul-1.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=armv6t2 -fno-unroll-loops" } */ ++ ++int mac(const short *a, const short *b, int sqr, int *sum) ++{ ++ int i; ++ int dotp = *sum; ++ ++ for (i = 0; i < 150; i++) { ++ dotp += b[i] * a[i]; ++ sqr += b[i] * b[i]; ++ } ++ ++ *sum = dotp; ++ return sqr; ++} ++ ++/* { dg-final { scan-assembler-times "smlabb" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/wmul-2.c ++++ b/src/gcc/testsuite/gcc.target/arm/wmul-2.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=armv6t2 -fno-unroll-loops" } */ ++ ++void vec_mpy(int y[], const short x[], short scaler) ++{ ++ int i; ++ ++ for (i = 0; i < 150; i++) ++ y[i] += ((scaler * x[i]) >> 31); ++} ++ ++/* { dg-final { scan-assembler-times "smulbb" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/bfin/wmul-1.c ++++ b/src/gcc/testsuite/gcc.target/bfin/wmul-1.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++int mac(const short *a, const short *b, int sqr, int *sum) ++{ ++ int i; ++ int dotp = *sum; ++ ++ for (i = 0; i < 150; i++) { ++ dotp += b[i] * a[i]; ++ sqr += b[i] * b[i]; ++ } ++ ++ *sum = dotp; ++ return sqr; ++} ++ ++/* { dg-final { scan-assembler-times "\\(IS\\)" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/bfin/wmul-2.c ++++ b/src/gcc/testsuite/gcc.target/bfin/wmul-2.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++void vec_mpy(int y[], const short x[], short scaler) ++{ ++ int i; ++ ++ for (i = 0; i < 150; i++) ++ y[i] += ((scaler * x[i]) >> 31); ++} ++ ++/* { dg-final { scan-assembler-times "\\(IS\\)" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/i386/avx-check.h ++++ b/src/gcc/testsuite/gcc.target/i386/avx-check.h +@@ -20,7 +20,7 @@ + return 0; + + /* Run AVX test only if host has AVX support. */ +- if (ecx & bit_AVX) ++ if ((ecx & (bit_AVX | bit_OSXSAVE)) == (bit_AVX | bit_OSXSAVE)) + { + do_test (); + #ifdef DEBUG +--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c ++++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c +@@ -0,0 +1,31 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target avx } */ ++/* { dg-options "-O2 -mavx" } */ ++ ++#include "avx-check.h" ++ ++#ifndef MASK ++#define MASK 7 ++#endif ++ ++#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) ++ ++void static ++avx_test (void) ++{ ++ int i; ++ long long m[2] = {mask_v(0), mask_v(1)}; ++ double s[2] = {1.1, 2.2}; ++ union128d u; ++ union128i_q mask; ++ double e[2] = {0.0}; ++ ++ mask.x = _mm_loadu_si128 ((__m128i *)m); ++ u.x = _mm_maskload_pd (s, mask.x); ++ ++ for (i = 0 ; i < 2; i++) ++ e[i] = m[i] ? s[i] : 0; ++ ++ if (check_union128d (u, e)) ++ abort (); ++} +--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c ++++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c +@@ -0,0 +1,33 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target avx } */ ++/* { dg-options "-O2 -mavx" } */ ++ ++#include "avx-check.h" ++ ++#ifndef MASK ++#define MASK 6 ++#endif ++ ++#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) ++ ++void static ++avx_test (void) ++{ ++ int i; ++ long long m[2] = {mask_v(0), mask_v(1)}; ++ double s[2] = {1.1, 2.2}; ++ double e[2] = {0.0}; ++ double d[2] = {0.0}; ++ union128d src; ++ union128i_q mask; ++ ++ src.x = _mm_loadu_pd (s); ++ mask.x = _mm_loadu_si128 ((__m128i *)m); ++ _mm_maskstore_pd (d, mask.x, src.x); ++ ++ for (i = 0 ; i < 2; i++) ++ e[i] = m[i] ? s[i] : 0; ++ ++ if (checkVd (d, e, 2)) ++ abort (); ++} +--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c ++++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c +@@ -14,12 +14,13 @@ + avx_test (void) + { + int i; +- long long m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)}; ++ long long m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)}; + double s[4] = {1.1, 2.2, 3.3, 4.4}; +- union256d u, mask; ++ union256d u; ++ union256i_q mask; + double e [4] = {0.0}; + +- mask.x = _mm256_loadu_pd ((double*)m); ++ mask.x = _mm256_loadu_si256 ((__m256i *)m); + u.x = _mm256_maskload_pd (s, mask.x); + + for (i = 0 ; i < 4; i++) +--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c ++++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c +@@ -18,10 +18,11 @@ + double s[4] = {1.1, 2.2, 3.3, 4.4}; + double e [4] = {0.0}; + double d [4] = {0.0}; +- union256d src, mask; ++ union256d src; ++ union256i_q mask; + + src.x = _mm256_loadu_pd (s); +- mask.x = _mm256_loadu_pd ((double*)m); ++ mask.x = _mm256_loadu_si256 ((__m256i *)m); + _mm256_maskstore_pd (d, mask.x, src.x); + + for (i = 0 ; i < 4; i++) +--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c ++++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c +@@ -0,0 +1,31 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target avx } */ ++/* { dg-options "-O2 -mavx" } */ ++ ++#include "avx-check.h" ++ ++#ifndef MASK ++#define MASK 134 ++#endif ++ ++#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) ++ ++void static ++avx_test (void) ++{ ++ int i; ++ int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)}; ++ float s[4] = {1,2,3,4}; ++ union128 u; ++ union128i_d mask; ++ float e[4] = {0.0}; ++ ++ mask.x = _mm_loadu_si128 ((__m128i *)m); ++ u.x = _mm_maskload_ps (s, mask.x); ++ ++ for (i = 0 ; i < 4; i++) ++ e[i] = m[i] ? s[i] : 0; ++ ++ if (check_union128 (u, e)) ++ abort (); ++} +--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c ++++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c +@@ -0,0 +1,33 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target avx } */ ++/* { dg-options "-O2 -mavx" } */ ++ ++#include "avx-check.h" ++ ++#ifndef MASK ++#define MASK 214 ++#endif ++ ++#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) ++ ++void static ++avx_test (void) ++{ ++ int i; ++ int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)}; ++ float s[4] = {1,2,3,4}; ++ union128 src; ++ union128i_d mask; ++ float e[4] = {0.0}; ++ float d[4] = {0.0}; ++ ++ src.x = _mm_loadu_ps (s); ++ mask.x = _mm_loadu_si128 ((__m128i *)m); ++ _mm_maskstore_ps (d, mask.x, src.x); ++ ++ for (i = 0 ; i < 4; i++) ++ e[i] = m[i] ? s[i] : 0; ++ ++ if (checkVf (d, e, 4)) ++ abort (); ++} +--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c ++++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c +@@ -16,10 +16,11 @@ + int i; + int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)}; + float s[8] = {1,2,3,4,5,6,7,8}; +- union256 u, mask; ++ union256 u; ++ union256i_d mask; + float e [8] = {0.0}; + +- mask.x = _mm256_loadu_ps ((float*)m); ++ mask.x = _mm256_loadu_si256 ((__m256i *)m); + u.x = _mm256_maskload_ps (s, mask.x); + + for (i = 0 ; i < 8; i++) +--- a/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c ++++ b/src/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c +@@ -16,12 +16,13 @@ + int i; + int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)}; + float s[8] = {1,2,3,4,5,6,7,8}; +- union256 src, mask; ++ union256 src; ++ union256i_d mask; + float e [8] = {0.0}; + float d [8] = {0.0}; + + src.x = _mm256_loadu_ps (s); +- mask.x = _mm256_loadu_ps ((float *)m); ++ mask.x = _mm256_loadu_si256 ((__m256i *)m); + _mm256_maskstore_ps (d, mask.x, src.x); + + for (i = 0 ; i < 8; i++) +--- a/src/gcc/testsuite/gcc.target/i386/pr41442.c ++++ b/src/gcc/testsuite/gcc.target/i386/pr41442.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++typedef struct LINK link; ++struct LINK ++{ ++ link* next; ++}; ++ ++int haha(link* p1, link* p2) ++{ ++ if ((p1->next && !p2->next) || p2->next) ++ return 0; ++ ++ return 1; ++} ++ ++/* { dg-final { scan-assembler-times "test|cmp" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/i386/pr43653.c ++++ b/src/gcc/testsuite/gcc.target/i386/pr43653.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1 -ftree-vectorize -msse" } */ ++ ++typedef struct {} S; ++ ++void *foo() ++{ ++ S a[64], *p[64]; ++ int i; ++ ++ for (i = 0; i < 64; i++) ++ p[i] = &a[i]; ++ return p[0]; ++} +--- a/src/gcc/testsuite/gcc.target/i386/pr45852.c ++++ b/src/gcc/testsuite/gcc.target/i386/pr45852.c +@@ -0,0 +1,16 @@ ++/* PR middle-end/45852 */ ++/* { dg-options "-O2 -mcmodel=small" } */ ++/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && lp64 } } } */ ++/* { dg-require-visibility "" } */ ++ ++struct S { int s; }; ++ ++volatile struct S globvar __attribute__((visibility ("hidden"))) = { -6 }; ++ ++void ++foo (void) ++{ ++ globvar = globvar; ++} ++ ++/* { dg-final { scan-assembler-times "globvar.%?rip" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/i386/pr46865-1.c ++++ b/src/gcc/testsuite/gcc.target/i386/pr46865-1.c +@@ -0,0 +1,31 @@ ++/* PR rtl-optimization/46865 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++extern unsigned long f; ++ ++#define m1(f) \ ++ if (f & 1) \ ++ asm volatile ("nop /* asmnop */\n"); \ ++ else \ ++ asm volatile ("nop /* asmnop */\n"); ++ ++#define m2(f) \ ++ if (f & 1) \ ++ asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); \ ++ else \ ++ asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); ++ ++void ++foo (void) ++{ ++ m1 (f); ++} ++ ++void ++bar (void) ++{ ++ m2 (f); ++} ++ ++/* { dg-final { scan-assembler-times "asmnop" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/i386/pr46865-2.c ++++ b/src/gcc/testsuite/gcc.target/i386/pr46865-2.c +@@ -0,0 +1,32 @@ ++/* PR rtl-optimization/46865 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -save-temps" } */ ++ ++extern unsigned long f; ++ ++#define m1(f) \ ++ if (f & 1) \ ++ asm volatile ("nop /* asmnop */\n"); \ ++ else \ ++ asm volatile ("nop /* asmnop */\n"); ++ ++#define m2(f) \ ++ if (f & 1) \ ++ asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); \ ++ else \ ++ asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); ++ ++void ++foo (void) ++{ ++ m1 (f); ++} ++ ++void ++bar (void) ++{ ++ m2 (f); ++} ++ ++/* { dg-final { scan-assembler-times "asmnop" 2 } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/i386/pr46880.c ++++ b/src/gcc/testsuite/gcc.target/i386/pr46880.c +@@ -0,0 +1,28 @@ ++/* PR target/46880 */ ++/* { dg-do run } */ ++/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ ++/* { dg-require-effective-target sse2_runtime } */ ++ ++typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__)); ++typedef double (*T)[2]; ++ ++static __attribute__ ((noinline, noclone)) __m128d ++foo (__m128d c, __m128d d) ++{ ++ T cp = (T) &c; ++ T dp = (T) &d; ++ __m128d e = { (*cp)[1], (*dp)[1] }; ++ return e; ++} ++ ++int ++main () ++{ ++ __m128d c = { 1.0, 2.0 }; ++ __m128d d = { 3.0, 4.0 }; ++ union { __m128d x; double d[2]; } u; ++ u.x = foo (c, d); ++ if (u.d[0] != 2.0 || u.d[1] != 4.0) ++ __builtin_abort (); ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/i386/pr9771-1.c ++++ b/src/gcc/testsuite/gcc.target/i386/pr9771-1.c +@@ -28,7 +28,10 @@ + *adr = save; + } + +-int main() ++/* This must not be inlined becuase main() requires the frame pointer ++ for stack alignment. */ ++void test(void) __attribute__((noinline)); ++void test(void) + { + B = &x; + +@@ -42,3 +45,9 @@ + exit(0); + } + ++int main() ++{ ++ test(); ++ return 0; ++ ++} +--- a/src/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c ++++ b/src/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fstrict-volatile-bitfields" } */ ++ ++typedef struct { ++ char a:1; ++ char b:7; ++ int c; ++} BitStruct; ++ ++volatile BitStruct bits; ++ ++int foo () ++{ ++ return bits.b; ++} ++ ++/* { dg-final { scan-assembler "mov(b|zbl).*bits" } } */ +--- a/src/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c ++++ b/src/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fno-strict-volatile-bitfields" } */ ++ ++typedef struct { ++ char a:1; ++ char b:7; ++ int c; ++} BitStruct; ++ ++volatile BitStruct bits; ++ ++int foo () ++{ ++ return bits.b; ++} ++ ++/* { dg-final { scan-assembler "movl.*bits" } } */ +--- a/src/gcc/testsuite/gcc.target/i386/wmul-1.c ++++ b/src/gcc/testsuite/gcc.target/i386/wmul-1.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++long long mac(const int *a, const int *b, long long sqr, long long *sum) ++{ ++ int i; ++ long long dotp = *sum; ++ ++ for (i = 0; i < 150; i++) { ++ dotp += (long long)b[i] * a[i]; ++ sqr += (long long)b[i] * b[i]; ++ } ++ ++ *sum = dotp; ++ return sqr; ++} ++ ++/* { dg-final { scan-assembler-times "imull" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/i386/wmul-2.c ++++ b/src/gcc/testsuite/gcc.target/i386/wmul-2.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++void vec_mpy(int y[], const int x[], int scaler) ++{ ++ int i; ++ ++ for (i = 0; i < 150; i++) ++ y[i] += (((long long)scaler * x[i]) >> 31); ++} ++ ++/* { dg-final { scan-assembler-times "imull" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/mips/save-restore-1.c ++++ b/src/gcc/testsuite/gcc.target/mips/save-restore-1.c +@@ -1,5 +1,6 @@ + /* Check that we can use the save instruction to save varargs. */ + /* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */ ++/* { dg-skip-if "PR target/46610" { mips-sgi-irix6* } } */ + + #include + +--- a/src/gcc/testsuite/gcc.target/mips/save-restore-3.c ++++ b/src/gcc/testsuite/gcc.target/mips/save-restore-3.c +@@ -1,6 +1,7 @@ + /* Check that we can use the save instruction to save spilled arguments + when the argument save area is out of range of a direct load or store. */ + /* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */ ++/* { dg-skip-if "PR target/46610" { mips-sgi-irix6* } } */ + + void bar (int *); + +--- a/src/gcc/testsuite/gcc.target/mips/save-restore-4.c ++++ b/src/gcc/testsuite/gcc.target/mips/save-restore-4.c +@@ -1,5 +1,6 @@ + /* Check that we can use the save instruction to save $16, $17 and $31. */ + /* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */ ++/* { dg-skip-if "PR target/46610" { mips-sgi-irix6* } } */ + + void bar (void); + +--- a/src/gcc/testsuite/gcc.target/mips/save-restore-5.c ++++ b/src/gcc/testsuite/gcc.target/mips/save-restore-5.c +@@ -1,5 +1,6 @@ + /* Check that we don't try to save the same register twice. */ + /* { dg-options "(-mips16) isa_rev>=1 -mgp32 -O2" } */ ++/* { dg-skip-if "PR target/46610" { mips-sgi-irix6* } } */ + + int bar (int, int, int, int); + void frob (void); +--- a/src/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c +@@ -1,5 +1,5 @@ + /* { dg-do compile { target { powerpc*-*-* } } } */ +-/* { dg-options "-O2 -mavoid-indexed-addresses" } */ ++/* { dg-options "-O2 -mavoid-indexed-addresses -mno-altivec -mno-vsx" } */ + + /* { dg-final { scan-assembler-not "lbzx" } } + +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c +@@ -30,31 +30,6 @@ + + reg_parms_t gparms; + +- +-/* Testcase could break on future gcc's, if parameter regs +- are changed before this asm. */ +- +-#define save_parms(lparms) \ +- asm volatile ("lis 11,gparms@ha\n\t" \ +- "la 11,gparms@l(11)\n\t" \ +- "st 3,0(11)\n\t" \ +- "st 4,4(11)\n\t" \ +- "st 5,8(11)\n\t" \ +- "st 6,12(11)\n\t" \ +- "st 7,16(11)\n\t" \ +- "st 8,20(11)\n\t" \ +- "st 9,24(11)\n\t" \ +- "st 10,28(11)\n\t" \ +- "stfd 1,32(11)\n\t" \ +- "stfd 2,40(11)\n\t" \ +- "stfd 3,48(11)\n\t" \ +- "stfd 4,56(11)\n\t" \ +- "stfd 5,64(11)\n\t" \ +- "stfd 6,72(11)\n\t" \ +- "stfd 7,80(11)\n\t" \ +- "stfd 8,88(11)\n\t":::"11", "memory"); \ +- lparms = gparms; +- + typedef struct sf + { + struct sf *backchain; +@@ -62,115 +37,159 @@ + unsigned int slot[200]; + } stack_frame_t; + ++/* Wrapper to save the GPRs and FPRs and then jump to the real function. */ ++#define WRAPPER(NAME) \ ++__asm__ ("\t.globl\t" #NAME "_asm\n\t" \ ++ ".text\n\t" \ ++ ".type " #NAME "_asm, @function\n" \ ++ #NAME "_asm:\n\t" \ ++ "lis 11,gparms@ha\n\t" \ ++ "la 11,gparms@l(11)\n\t" \ ++ "st 3,0(11)\n\t" \ ++ "st 4,4(11)\n\t" \ ++ "st 5,8(11)\n\t" \ ++ "st 6,12(11)\n\t" \ ++ "st 7,16(11)\n\t" \ ++ "st 8,20(11)\n\t" \ ++ "st 9,24(11)\n\t" \ ++ "st 10,28(11)\n\t" \ ++ "stfd 1,32(11)\n\t" \ ++ "stfd 2,40(11)\n\t" \ ++ "stfd 3,48(11)\n\t" \ ++ "stfd 4,56(11)\n\t" \ ++ "stfd 5,64(11)\n\t" \ ++ "stfd 6,72(11)\n\t" \ ++ "stfd 7,80(11)\n\t" \ ++ "stfd 8,88(11)\n\t" \ ++ "b " #NAME "\n\t" \ ++ ".size " #NAME ",.-" #NAME "\n") ++ + /* Fill up floating point registers with double arguments, forcing + decimal float arguments into the parameter save area. */ ++extern void func0_asm (double, double, double, double, double, ++ double, double, double, _Decimal64, _Decimal128); ++ ++WRAPPER(func0); ++ + void __attribute__ ((noinline)) + func0 (double a1, double a2, double a3, double a4, double a5, + double a6, double a7, double a8, _Decimal64 a9, _Decimal128 a10) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + +- if (a1 != lparms.fprs[0]) FAILURE +- if (a2 != lparms.fprs[1]) FAILURE +- if (a3 != lparms.fprs[2]) FAILURE +- if (a4 != lparms.fprs[3]) FAILURE +- if (a5 != lparms.fprs[4]) FAILURE +- if (a6 != lparms.fprs[5]) FAILURE +- if (a7 != lparms.fprs[6]) FAILURE +- if (a8 != lparms.fprs[7]) FAILURE ++ if (a1 != gparms.fprs[0]) FAILURE ++ if (a2 != gparms.fprs[1]) FAILURE ++ if (a3 != gparms.fprs[2]) FAILURE ++ if (a4 != gparms.fprs[3]) FAILURE ++ if (a5 != gparms.fprs[4]) FAILURE ++ if (a6 != gparms.fprs[5]) FAILURE ++ if (a7 != gparms.fprs[6]) FAILURE ++ if (a8 != gparms.fprs[7]) FAILURE + if (a9 != *(_Decimal64 *)&sp->slot[0]) FAILURE + if (a10 != *(_Decimal128 *)&sp->slot[2]) FAILURE + } + + /* Alternate 64-bit and 128-bit decimal float arguments, checking that + _Decimal128 is always passed in even/odd register pairs. */ ++extern void func1_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128, ++ _Decimal64, _Decimal128, _Decimal64, _Decimal128); ++ ++WRAPPER(func1); ++ + void __attribute__ ((noinline)) + func1 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4, + _Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + +- if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE /* f1 */ +- if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */ +- if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */ +- if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */ +- if (a5 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */ ++ if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE /* f1 */ ++ if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */ ++ if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */ ++ if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */ ++ if (a5 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */ + if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE + if (a7 != *(_Decimal64 *)&sp->slot[4]) FAILURE + if (a8 != *(_Decimal128 *)&sp->slot[6]) FAILURE + } + ++extern void func2_asm (_Decimal128, _Decimal64, _Decimal128, _Decimal64, ++ _Decimal128, _Decimal64, _Decimal128, _Decimal64); ++ ++WRAPPER(func2); ++ + void __attribute__ ((noinline)) + func2 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4, + _Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + +- if (a1 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */ +- if (a2 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */ +- if (a3 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */ +- if (a4 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */ ++ if (a1 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */ ++ if (a2 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */ ++ if (a3 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */ ++ if (a4 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */ + if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE + if (a6 != *(_Decimal64 *)&sp->slot[4]) FAILURE + if (a7 != *(_Decimal128 *)&sp->slot[6]) FAILURE + if (a8 != *(_Decimal64 *)&sp->slot[10]) FAILURE + } + ++extern void func3_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128, ++ _Decimal64); ++ ++WRAPPER(func3); ++ + void __attribute__ ((noinline)) + func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4, + _Decimal64 a5) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + +- if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE /* f1 */ +- if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */ +- if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */ +- if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */ ++ if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE /* f1 */ ++ if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */ ++ if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */ ++ if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */ + if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE + } + ++extern void func4_asm (_Decimal32, _Decimal32, _Decimal32, _Decimal32, ++ _Decimal32, _Decimal32, _Decimal32, _Decimal32, ++ _Decimal32, _Decimal32, _Decimal32, _Decimal32, ++ _Decimal32, _Decimal32, _Decimal32, _Decimal32); ++ ++WRAPPER(func4); ++ + void __attribute__ ((noinline)) + func4 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4, + _Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8, + _Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12, + _Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + /* _Decimal32 is passed in the lower half of an FPR, or in parameter slot. */ +- if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */ +- if (a2 != ((d32parm_t *)&lparms.fprs[1])->d) FAILURE /* f2 */ +- if (a3 != ((d32parm_t *)&lparms.fprs[2])->d) FAILURE /* f3 */ +- if (a4 != ((d32parm_t *)&lparms.fprs[3])->d) FAILURE /* f4 */ +- if (a5 != ((d32parm_t *)&lparms.fprs[4])->d) FAILURE /* f5 */ +- if (a6 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */ +- if (a7 != ((d32parm_t *)&lparms.fprs[6])->d) FAILURE /* f7 */ +- if (a8 != ((d32parm_t *)&lparms.fprs[7])->d) FAILURE /* f8 */ ++ if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */ ++ if (a2 != ((d32parm_t *)&gparms.fprs[1])->d) FAILURE /* f2 */ ++ if (a3 != ((d32parm_t *)&gparms.fprs[2])->d) FAILURE /* f3 */ ++ if (a4 != ((d32parm_t *)&gparms.fprs[3])->d) FAILURE /* f4 */ ++ if (a5 != ((d32parm_t *)&gparms.fprs[4])->d) FAILURE /* f5 */ ++ if (a6 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */ ++ if (a7 != ((d32parm_t *)&gparms.fprs[6])->d) FAILURE /* f7 */ ++ if (a8 != ((d32parm_t *)&gparms.fprs[7])->d) FAILURE /* f8 */ + if (a9 != *(_Decimal32 *)&sp->slot[0]) FAILURE + if (a10 != *(_Decimal32 *)&sp->slot[1]) FAILURE + if (a11 != *(_Decimal32 *)&sp->slot[2]) FAILURE +@@ -181,24 +200,29 @@ + if (a16 != *(_Decimal32 *)&sp->slot[7]) FAILURE + } + ++extern void func5_asm (_Decimal32, _Decimal64, _Decimal128, ++ _Decimal32, _Decimal64, _Decimal128, ++ _Decimal32, _Decimal64, _Decimal128, ++ _Decimal32, _Decimal64, _Decimal128); ++ ++WRAPPER(func5); ++ + void __attribute__ ((noinline)) + func5 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3, + _Decimal32 a4, _Decimal64 a5, _Decimal128 a6, + _Decimal32 a7, _Decimal64 a8, _Decimal128 a9, + _Decimal32 a10, _Decimal64 a11, _Decimal128 a12) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + +- if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */ +- if (a2 != *(_Decimal64 *)&lparms.fprs[1]) FAILURE /* f2 */ +- if (a3 != *(_Decimal128 *)&lparms.fprs[3]) FAILURE /* f4 & f5 */ +- if (a4 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */ +- if (a5 != *(_Decimal64 *)&lparms.fprs[6]) FAILURE /* f7 */ ++ if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */ ++ if (a2 != *(_Decimal64 *)&gparms.fprs[1]) FAILURE /* f2 */ ++ if (a3 != *(_Decimal128 *)&gparms.fprs[3]) FAILURE /* f4 & f5 */ ++ if (a4 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */ ++ if (a5 != *(_Decimal64 *)&gparms.fprs[6]) FAILURE /* f7 */ + + if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE + if (a7 != *(_Decimal32 *)&sp->slot[4]) FAILURE +@@ -212,15 +236,15 @@ + int + main () + { +- func0 (1., 2., 3., 4., 5., 6., 7., 8., 9.dd, 10.dl); +- func1 (1.dd, 2.dl, 3.dd, 4.dl, 5.dd, 6.dl, 7.dd, 8.dl); +- func2 (1.dl, 2.dd, 3.dl, 4.dd, 5.dl, 6.dd, 7.dl, 8.dd); +- func3 (1.dd, 2.dl, 3.dd, 4.dl, 5.dl); +- func4 (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df, +- 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df, +- 515.2df, 516.2df); +- func5 (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl, +- 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl); ++ func0_asm (1., 2., 3., 4., 5., 6., 7., 8., 9.dd, 10.dl); ++ func1_asm (1.dd, 2.dl, 3.dd, 4.dl, 5.dd, 6.dl, 7.dd, 8.dl); ++ func2_asm (1.dl, 2.dd, 3.dl, 4.dd, 5.dl, 6.dd, 7.dl, 8.dd); ++ func3_asm (1.dd, 2.dl, 3.dd, 4.dl, 5.dl); ++ func4_asm (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df, ++ 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df, ++ 515.2df, 516.2df); ++ func5_asm (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl, ++ 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl); + + if (failcnt != 0) + abort (); +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c +@@ -1,4 +1,5 @@ + /* { dg-do run { target { powerpc64-*-* && { lp64 && dfprt } } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ + /* { dg-options "-std=gnu99 -O2 -fno-strict-aliasing" } */ + + /* Testcase to check for ABI compliance of parameter passing +@@ -31,60 +32,42 @@ + reg_parms_t gparms; + + +-/* Testcase could break on future gcc's, if parameter regs +- are changed before this asm. */ +- +-#ifndef __MACH__ +-#define save_parms(lparms) \ +- asm volatile ("ld 11,gparms@got(2)\n\t" \ +- "std 3,0(11)\n\t" \ +- "std 4,8(11)\n\t" \ +- "std 5,16(11)\n\t" \ +- "std 6,24(11)\n\t" \ +- "std 7,32(11)\n\t" \ +- "std 8,40(11)\n\t" \ +- "std 9,48(11)\n\t" \ +- "std 10,56(11)\n\t" \ +- "stfd 1,64(11)\n\t" \ +- "stfd 2,72(11)\n\t" \ +- "stfd 3,80(11)\n\t" \ +- "stfd 4,88(11)\n\t" \ +- "stfd 5,96(11)\n\t" \ +- "stfd 6,104(11)\n\t" \ +- "stfd 7,112(11)\n\t" \ +- "stfd 8,120(11)\n\t" \ +- "stfd 9,128(11)\n\t" \ +- "stfd 10,136(11)\n\t" \ +- "stfd 11,144(11)\n\t" \ +- "stfd 12,152(11)\n\t" \ +- "stfd 13,160(11)\n\t":::"11", "memory"); \ +- lparms = gparms; +-#else +-#define save_parms(lparms) \ +- asm volatile ("ld r11,gparms@got(r2)\n\t" \ +- "std r3,0(r11)\n\t" \ +- "std r4,8(r11)\n\t" \ +- "std r5,16(r11)\n\t" \ +- "std r6,24(r11)\n\t" \ +- "std r7,32(r11)\n\t" \ +- "std r8,40(r11)\n\t" \ +- "std r9,48(r11)\n\t" \ +- "std r10,56(r11)\n\t" \ +- "stfd f1,64(r11)\n\t" \ +- "stfd f2,72(r11)\n\t" \ +- "stfd f3,80(r11)\n\t" \ +- "stfd f4,88(r11)\n\t" \ +- "stfd f5,96(r11)\n\t" \ +- "stfd f6,104(r11)\n\t" \ +- "stfd f7,112(r11)\n\t" \ +- "stfd f8,120(r11)\n\t" \ +- "stfd f9,128(r11)\n\t" \ +- "stfd f10,136(r11)\n\t" \ +- "stfd f11,144(r11)\n\t" \ +- "stfd f12,152(r11)\n\t" \ +- "stfd f13,160(r11)\n\t":::"r11", "memory"); \ +- lparms = gparms; +-#endif ++/* Wrapper to save the GPRs and FPRs and then jump to the real function. */ ++#define WRAPPER(NAME) \ ++__asm__ ("\t.globl\t" #NAME "_asm\n\t" \ ++ ".section \".opd\",\"aw\"\n\t" \ ++ ".align 3\n" \ ++ #NAME "_asm:\n\t" \ ++ ".quad .L." #NAME "_asm,.TOC.@tocbase,0\n\t" \ ++ ".text\n\t" \ ++ ".type " #NAME "_asm, @function\n" \ ++ ".L." #NAME "_asm:\n\t" \ ++ "ld 11,gparms@got(2)\n\t" \ ++ "std 3,0(11)\n\t" \ ++ "std 4,8(11)\n\t" \ ++ "std 5,16(11)\n\t" \ ++ "std 6,24(11)\n\t" \ ++ "std 7,32(11)\n\t" \ ++ "std 8,40(11)\n\t" \ ++ "std 9,48(11)\n\t" \ ++ "std 10,56(11)\n\t" \ ++ "stfd 1,64(11)\n\t" \ ++ "stfd 2,72(11)\n\t" \ ++ "stfd 3,80(11)\n\t" \ ++ "stfd 4,88(11)\n\t" \ ++ "stfd 5,96(11)\n\t" \ ++ "stfd 6,104(11)\n\t" \ ++ "stfd 7,112(11)\n\t" \ ++ "stfd 8,120(11)\n\t" \ ++ "stfd 9,128(11)\n\t" \ ++ "stfd 10,136(11)\n\t" \ ++ "stfd 11,144(11)\n\t" \ ++ "stfd 12,152(11)\n\t" \ ++ "stfd 13,160(11)\n\t" \ ++ "b " #NAME "\n\t" \ ++ ".long 0\n\t" \ ++ ".byte 0,0,0,0,0,0,0,0\n\t" \ ++ ".size " #NAME ",.-" #NAME "\n") + + typedef struct sf + { +@@ -97,6 +80,13 @@ + unsigned long slot[100]; + } stack_frame_t; + ++extern void func0_asm (double, double, double, double, double, double, ++ double, double, double, double, double, double, ++ double, double, ++ _Decimal64, _Decimal128, _Decimal64); ++ ++WRAPPER(func0); ++ + /* Fill up floating point registers with double arguments, forcing + decimal float arguments into the parameter save area. */ + void __attribute__ ((noinline)) +@@ -105,186 +95,209 @@ + double a13, double a14, + _Decimal64 a15, _Decimal128 a16, _Decimal64 a17) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + +- if (a1 != lparms.fprs[0]) FAILURE +- if (a2 != lparms.fprs[1]) FAILURE +- if (a3 != lparms.fprs[2]) FAILURE +- if (a4 != lparms.fprs[3]) FAILURE +- if (a5 != lparms.fprs[4]) FAILURE +- if (a6 != lparms.fprs[5]) FAILURE +- if (a7 != lparms.fprs[6]) FAILURE +- if (a8 != lparms.fprs[7]) FAILURE +- if (a9 != lparms.fprs[8]) FAILURE +- if (a10 != lparms.fprs[9]) FAILURE +- if (a11 != lparms.fprs[10]) FAILURE +- if (a12 != lparms.fprs[11]) FAILURE +- if (a13 != lparms.fprs[12]) FAILURE ++ if (a1 != gparms.fprs[0]) FAILURE ++ if (a2 != gparms.fprs[1]) FAILURE ++ if (a3 != gparms.fprs[2]) FAILURE ++ if (a4 != gparms.fprs[3]) FAILURE ++ if (a5 != gparms.fprs[4]) FAILURE ++ if (a6 != gparms.fprs[5]) FAILURE ++ if (a7 != gparms.fprs[6]) FAILURE ++ if (a8 != gparms.fprs[7]) FAILURE ++ if (a9 != gparms.fprs[8]) FAILURE ++ if (a10 != gparms.fprs[9]) FAILURE ++ if (a11 != gparms.fprs[10]) FAILURE ++ if (a12 != gparms.fprs[11]) FAILURE ++ if (a13 != gparms.fprs[12]) FAILURE + if (a14 != *(double *)&sp->slot[13]) FAILURE + if (a15 != *(_Decimal64 *)&sp->slot[14]) FAILURE + if (a16 != *(_Decimal128 *)&sp->slot[15]) FAILURE + if (a17 != *(_Decimal64 *)&sp->slot[17]) FAILURE + } + ++extern void func1_asm (double, double, double, double, double, double, ++ double, double, double, double, double, double, ++ double, _Decimal128 ); ++ ++WRAPPER(func1); ++ + void __attribute__ ((noinline)) + func1 (double a1, double a2, double a3, double a4, double a5, double a6, + double a7, double a8, double a9, double a10, double a11, double a12, + double a13, _Decimal128 a14) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + +- if (a1 != lparms.fprs[0]) FAILURE +- if (a2 != lparms.fprs[1]) FAILURE +- if (a3 != lparms.fprs[2]) FAILURE +- if (a4 != lparms.fprs[3]) FAILURE +- if (a5 != lparms.fprs[4]) FAILURE +- if (a6 != lparms.fprs[5]) FAILURE +- if (a7 != lparms.fprs[6]) FAILURE +- if (a8 != lparms.fprs[7]) FAILURE +- if (a9 != lparms.fprs[8]) FAILURE +- if (a10 != lparms.fprs[9]) FAILURE +- if (a11 != lparms.fprs[10]) FAILURE +- if (a12 != lparms.fprs[11]) FAILURE +- if (a13 != lparms.fprs[12]) FAILURE ++ if (a1 != gparms.fprs[0]) FAILURE ++ if (a2 != gparms.fprs[1]) FAILURE ++ if (a3 != gparms.fprs[2]) FAILURE ++ if (a4 != gparms.fprs[3]) FAILURE ++ if (a5 != gparms.fprs[4]) FAILURE ++ if (a6 != gparms.fprs[5]) FAILURE ++ if (a7 != gparms.fprs[6]) FAILURE ++ if (a8 != gparms.fprs[7]) FAILURE ++ if (a9 != gparms.fprs[8]) FAILURE ++ if (a10 != gparms.fprs[9]) FAILURE ++ if (a11 != gparms.fprs[10]) FAILURE ++ if (a12 != gparms.fprs[11]) FAILURE ++ if (a13 != gparms.fprs[12]) FAILURE + if (a14 != *(_Decimal128 *)&sp->slot[13]) FAILURE + } + ++extern void func2_asm (double, double, double, double, double, double, ++ double, double, double, double, double, double, ++ _Decimal128); ++ ++WRAPPER(func2); ++ + void __attribute__ ((noinline)) + func2 (double a1, double a2, double a3, double a4, double a5, double a6, + double a7, double a8, double a9, double a10, double a11, double a12, + _Decimal128 a13) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + +- if (a1 != lparms.fprs[0]) FAILURE +- if (a2 != lparms.fprs[1]) FAILURE +- if (a3 != lparms.fprs[2]) FAILURE +- if (a4 != lparms.fprs[3]) FAILURE +- if (a5 != lparms.fprs[4]) FAILURE +- if (a6 != lparms.fprs[5]) FAILURE +- if (a7 != lparms.fprs[6]) FAILURE +- if (a8 != lparms.fprs[7]) FAILURE +- if (a9 != lparms.fprs[8]) FAILURE +- if (a10 != lparms.fprs[9]) FAILURE +- if (a11 != lparms.fprs[10]) FAILURE +- if (a12 != lparms.fprs[11]) FAILURE ++ if (a1 != gparms.fprs[0]) FAILURE ++ if (a2 != gparms.fprs[1]) FAILURE ++ if (a3 != gparms.fprs[2]) FAILURE ++ if (a4 != gparms.fprs[3]) FAILURE ++ if (a5 != gparms.fprs[4]) FAILURE ++ if (a6 != gparms.fprs[5]) FAILURE ++ if (a7 != gparms.fprs[6]) FAILURE ++ if (a8 != gparms.fprs[7]) FAILURE ++ if (a9 != gparms.fprs[8]) FAILURE ++ if (a10 != gparms.fprs[9]) FAILURE ++ if (a11 != gparms.fprs[10]) FAILURE ++ if (a12 != gparms.fprs[11]) FAILURE + if (a13 != *(_Decimal128 *)&sp->slot[12]) FAILURE + } + ++extern void func3_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128, ++ _Decimal64, _Decimal128, _Decimal64, _Decimal128, ++ _Decimal64, _Decimal128); ++ ++WRAPPER(func3); ++ + void __attribute__ ((noinline)) + func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4, + _Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8, + _Decimal64 a9, _Decimal128 a10) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + +- if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE /* f1 */ +- if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */ +- if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */ +- if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */ +- if (a5 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */ +- if (a6 != *(_Decimal128 *)&lparms.fprs[9]) FAILURE /* f10 & f11 */ +- if (a7 != *(_Decimal64 *)&lparms.fprs[11]) FAILURE /* f12 */ ++ if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE /* f1 */ ++ if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */ ++ if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */ ++ if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */ ++ if (a5 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */ ++ if (a6 != *(_Decimal128 *)&gparms.fprs[9]) FAILURE /* f10 & f11 */ ++ if (a7 != *(_Decimal64 *)&gparms.fprs[11]) FAILURE /* f12 */ + if (a8 != *(_Decimal128 *)&sp->slot[10]) FAILURE + if (a9 != *(_Decimal64 *)&sp->slot[12]) FAILURE + if (a10 != *(_Decimal128 *)&sp->slot[13]) FAILURE + } + ++extern void func4_asm (_Decimal128, _Decimal64, _Decimal128, _Decimal64, ++ _Decimal128, _Decimal64, _Decimal128, _Decimal64); ++ ++WRAPPER(func4); ++ + void __attribute__ ((noinline)) + func4 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4, + _Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + +- if (a1 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */ +- if (a2 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */ +- if (a3 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */ +- if (a4 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */ +- if (a5 != *(_Decimal128 *)&lparms.fprs[9]) FAILURE /* f10 & f11 */ +- if (a6 != *(_Decimal64 *)&lparms.fprs[11]) FAILURE /* f12 */ ++ if (a1 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */ ++ if (a2 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */ ++ if (a3 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */ ++ if (a4 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */ ++ if (a5 != *(_Decimal128 *)&gparms.fprs[9]) FAILURE /* f10 & f11 */ ++ if (a6 != *(_Decimal64 *)&gparms.fprs[11]) FAILURE /* f12 */ + if (a7 != *(_Decimal128 *)&sp->slot[9]) FAILURE + if (a8 != *(_Decimal64 *)&sp->slot[11]) FAILURE + } + ++extern void func5_asm (_Decimal32, _Decimal32, _Decimal32, _Decimal32, ++ _Decimal32, _Decimal32, _Decimal32, _Decimal32, ++ _Decimal32, _Decimal32, _Decimal32, _Decimal32, ++ _Decimal32, _Decimal32, _Decimal32, _Decimal32); ++ ++WRAPPER(func5); ++ + void __attribute__ ((noinline)) + func5 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4, + _Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8, + _Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12, + _Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + /* _Decimal32 is passed in the lower half of an FPR or parameter slot. */ +- if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */ +- if (a2 != ((d32parm_t *)&lparms.fprs[1])->d) FAILURE /* f2 */ +- if (a3 != ((d32parm_t *)&lparms.fprs[2])->d) FAILURE /* f3 */ +- if (a4 != ((d32parm_t *)&lparms.fprs[3])->d) FAILURE /* f4 */ +- if (a5 != ((d32parm_t *)&lparms.fprs[4])->d) FAILURE /* f5 */ +- if (a6 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */ +- if (a7 != ((d32parm_t *)&lparms.fprs[6])->d) FAILURE /* f7 */ +- if (a8 != ((d32parm_t *)&lparms.fprs[7])->d) FAILURE /* f8 */ +- if (a9 != ((d32parm_t *)&lparms.fprs[8])->d) FAILURE /* f9 */ +- if (a10 != ((d32parm_t *)&lparms.fprs[9])->d) FAILURE /* f10 */ +- if (a11 != ((d32parm_t *)&lparms.fprs[10])->d) FAILURE /* f11 */ +- if (a12 != ((d32parm_t *)&lparms.fprs[11])->d) FAILURE /* f12 */ +- if (a13 != ((d32parm_t *)&lparms.fprs[12])->d) FAILURE /* f13 */ ++ if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */ ++ if (a2 != ((d32parm_t *)&gparms.fprs[1])->d) FAILURE /* f2 */ ++ if (a3 != ((d32parm_t *)&gparms.fprs[2])->d) FAILURE /* f3 */ ++ if (a4 != ((d32parm_t *)&gparms.fprs[3])->d) FAILURE /* f4 */ ++ if (a5 != ((d32parm_t *)&gparms.fprs[4])->d) FAILURE /* f5 */ ++ if (a6 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */ ++ if (a7 != ((d32parm_t *)&gparms.fprs[6])->d) FAILURE /* f7 */ ++ if (a8 != ((d32parm_t *)&gparms.fprs[7])->d) FAILURE /* f8 */ ++ if (a9 != ((d32parm_t *)&gparms.fprs[8])->d) FAILURE /* f9 */ ++ if (a10 != ((d32parm_t *)&gparms.fprs[9])->d) FAILURE /* f10 */ ++ if (a11 != ((d32parm_t *)&gparms.fprs[10])->d) FAILURE /* f11 */ ++ if (a12 != ((d32parm_t *)&gparms.fprs[11])->d) FAILURE /* f12 */ ++ if (a13 != ((d32parm_t *)&gparms.fprs[12])->d) FAILURE /* f13 */ + if (a14 != ((d32parm_t *)&sp->slot[13])->d) FAILURE + if (a15 != ((d32parm_t *)&sp->slot[14])->d) FAILURE + if (a16 != ((d32parm_t *)&sp->slot[15])->d) FAILURE + } + ++extern void func6_asm (_Decimal32, _Decimal64, _Decimal128, ++ _Decimal32, _Decimal64, _Decimal128, ++ _Decimal32, _Decimal64, _Decimal128, ++ _Decimal32, _Decimal64, _Decimal128); ++ ++WRAPPER(func6); ++ + void __attribute__ ((noinline)) + func6 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3, + _Decimal32 a4, _Decimal64 a5, _Decimal128 a6, + _Decimal32 a7, _Decimal64 a8, _Decimal128 a9, + _Decimal32 a10, _Decimal64 a11, _Decimal128 a12) + { +- reg_parms_t lparms; + stack_frame_t *sp; + +- save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + +- if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */ +- if (a2 != *(_Decimal64 *)&lparms.fprs[1]) FAILURE /* f2 */ +- if (a3 != *(_Decimal128 *)&lparms.fprs[3]) FAILURE /* f4 & f5 */ +- if (a4 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */ +- if (a5 != *(_Decimal64 *)&lparms.fprs[6]) FAILURE /* f7 */ +- if (a6 != *(_Decimal128 *)&lparms.fprs[7]) FAILURE /* f8 & f9 */ +- if (a7 != ((d32parm_t *)&lparms.fprs[9])->d) FAILURE /* f10 */ +- if (a8 != *(_Decimal64 *)&lparms.fprs[10]) FAILURE /* f11 */ +- if (a9 != *(_Decimal128 *)&lparms.fprs[11]) FAILURE /* f12 & f13 */ ++ if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */ ++ if (a2 != *(_Decimal64 *)&gparms.fprs[1]) FAILURE /* f2 */ ++ if (a3 != *(_Decimal128 *)&gparms.fprs[3]) FAILURE /* f4 & f5 */ ++ if (a4 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */ ++ if (a5 != *(_Decimal64 *)&gparms.fprs[6]) FAILURE /* f7 */ ++ if (a6 != *(_Decimal128 *)&gparms.fprs[7]) FAILURE /* f8 & f9 */ ++ if (a7 != ((d32parm_t *)&gparms.fprs[9])->d) FAILURE /* f10 */ ++ if (a8 != *(_Decimal64 *)&gparms.fprs[10]) FAILURE /* f11 */ ++ if (a9 != *(_Decimal128 *)&gparms.fprs[11]) FAILURE /* f12 & f13 */ + if (a10 != ((d32parm_t *)&sp->slot[12])->d) FAILURE + if (a11 != *(_Decimal64 *)&sp->slot[13]) FAILURE + } +@@ -292,23 +305,23 @@ + int + main (void) + { +- func0 (1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5, 9.5, 10.5, 11.5, 12.5, 13.5, +- 14.5, 15.2dd, 16.2dl, 17.2dd); +- func1 (101.5, 102.5, 103.5, 104.5, 105.5, 106.5, 107.5, 108.5, 109.5, +- 110.5, 111.5, 112.5, 113.5, 114.2dd); +- func2 (201.5, 202.5, 203.5, 204.5, 205.5, 206.5, 207.5, 208.5, 209.5, +- 210.5, 211.5, 212.5, 213.2dd); +- func3 (301.2dd, 302.2dl, 303.2dd, 304.2dl, 305.2dd, 306.2dl, 307.2dd, +- 308.2dl, 309.2dd, 310.2dl); +- func4 (401.2dl, 402.2dd, 403.2dl, 404.2dd, 405.2dl, 406.2dd, 407.2dl, +- 408.2dd); ++ func0_asm (1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5, 9.5, 10.5, 11.5, 12.5, 13.5, ++ 14.5, 15.2dd, 16.2dl, 17.2dd); ++ func1_asm (101.5, 102.5, 103.5, 104.5, 105.5, 106.5, 107.5, 108.5, 109.5, ++ 110.5, 111.5, 112.5, 113.5, 114.2dd); ++ func2_asm (201.5, 202.5, 203.5, 204.5, 205.5, 206.5, 207.5, 208.5, 209.5, ++ 210.5, 211.5, 212.5, 213.2dd); ++ func3_asm (301.2dd, 302.2dl, 303.2dd, 304.2dl, 305.2dd, 306.2dl, 307.2dd, ++ 308.2dl, 309.2dd, 310.2dl); ++ func4_asm (401.2dl, 402.2dd, 403.2dl, 404.2dd, 405.2dl, 406.2dd, 407.2dl, ++ 408.2dd); + #if 0 + /* _Decimal32 doesn't yet follow the ABI; enable this when it does. */ +- func5 (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df, +- 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df, +- 515.2df, 516.2df); +- func6 (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl, +- 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl); ++ func5_asm (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df, ++ 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df, ++ 515.2df, 516.2df); ++ func6_asm (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl, ++ 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl); + #endif + + if (failcnt != 0) +--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c +@@ -0,0 +1,97 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O3 -mcpu=power7" } */ ++ ++/* Test the various load/store varients. */ ++ ++#include ++ ++#define TEST_COPY(NAME, TYPE) \ ++void NAME ## _copy_native (vector TYPE *a, vector TYPE *b) \ ++{ \ ++ *a = *b; \ ++} \ ++ \ ++void NAME ## _copy_vec (vector TYPE *a, vector TYPE *b) \ ++{ \ ++ vector TYPE x = vec_ld (0, b); \ ++ vec_st (x, 0, a); \ ++} \ ++ ++#define TEST_COPYL(NAME, TYPE) \ ++void NAME ## _lvxl (vector TYPE *a, vector TYPE *b) \ ++{ \ ++ vector TYPE x = vec_ldl (0, b); \ ++ vec_stl (x, 0, a); \ ++} \ ++ ++#define TEST_VSX_COPY(NAME, TYPE) \ ++void NAME ## _copy_vsx (vector TYPE *a, vector TYPE *b) \ ++{ \ ++ vector TYPE x = vec_vsx_ld (0, b); \ ++ vec_vsx_st (x, 0, a); \ ++} \ ++ ++#define TEST_ALIGN(NAME, TYPE) \ ++void NAME ## _align (vector unsigned char *a, TYPE *b) \ ++{ \ ++ vector unsigned char x = vec_lvsl (0, b); \ ++ vector unsigned char y = vec_lvsr (0, b); \ ++ vec_st (x, 0, a); \ ++ vec_st (y, 8, a); \ ++} ++ ++#ifndef NO_COPY ++TEST_COPY(uchar, unsigned char) ++TEST_COPY(schar, signed char) ++TEST_COPY(bchar, bool char) ++TEST_COPY(ushort, unsigned short) ++TEST_COPY(sshort, signed short) ++TEST_COPY(bshort, bool short) ++TEST_COPY(uint, unsigned int) ++TEST_COPY(sint, signed int) ++TEST_COPY(bint, bool int) ++TEST_COPY(float, float) ++TEST_COPY(double, double) ++#endif /* NO_COPY */ ++ ++#ifndef NO_COPYL ++TEST_COPYL(uchar, unsigned char) ++TEST_COPYL(schar, signed char) ++TEST_COPYL(bchar, bool char) ++TEST_COPYL(ushort, unsigned short) ++TEST_COPYL(sshort, signed short) ++TEST_COPYL(bshort, bool short) ++TEST_COPYL(uint, unsigned int) ++TEST_COPYL(sint, signed int) ++TEST_COPYL(bint, bool int) ++TEST_COPYL(float, float) ++TEST_COPYL(double, double) ++#endif /* NO_COPYL */ ++ ++#ifndef NO_ALIGN ++TEST_ALIGN(uchar, unsigned char) ++TEST_ALIGN(schar, signed char) ++TEST_ALIGN(ushort, unsigned short) ++TEST_ALIGN(sshort, signed short) ++TEST_ALIGN(uint, unsigned int) ++TEST_ALIGN(sint, signed int) ++TEST_ALIGN(float, float) ++TEST_ALIGN(double, double) ++#endif /* NO_ALIGN */ ++ ++ ++#ifndef NO_VSX_COPY ++TEST_VSX_COPY(uchar, unsigned char) ++TEST_VSX_COPY(schar, signed char) ++TEST_VSX_COPY(bchar, bool char) ++TEST_VSX_COPY(ushort, unsigned short) ++TEST_VSX_COPY(sshort, signed short) ++TEST_VSX_COPY(bshort, bool short) ++TEST_VSX_COPY(uint, unsigned int) ++TEST_VSX_COPY(sint, signed int) ++TEST_VSX_COPY(bint, bool int) ++TEST_VSX_COPY(float, float) ++TEST_VSX_COPY(double, double) ++#endif /* NO_VSX_COPY */ +--- a/src/gcc/testsuite/gfortran.dg/argument_checking_13.f90 ++++ b/src/gcc/testsuite/gfortran.dg/argument_checking_13.f90 +@@ -26,9 +26,9 @@ + real, allocatable :: deferred(:,:,:) + real, pointer :: ptr(:,:,:) + call rlv1(deferred(1,1,1)) ! valid since contiguous +-call rlv1(ptr(1,1,1)) ! { dg-error "Element of assumed-shaped array" } +-call rlv1(assumed_sh_dummy(1,1,1)) ! { dg-error "Element of assumed-shaped array" } +-call rlv1(pointer_dummy(1,1,1)) ! { dg-error "Element of assumed-shaped array" } ++call rlv1(ptr(1,1,1)) ! { dg-error "Element of assumed-shaped or pointer array" } ++call rlv1(assumed_sh_dummy(1,1,1)) ! { dg-error "Element of assumed-shaped or pointer array" } ++call rlv1(pointer_dummy(1,1,1)) ! { dg-error "Element of assumed-shaped or pointer array" } + end + + subroutine test2(assumed_sh_dummy, pointer_dummy) +--- a/src/gcc/testsuite/gfortran.dg/argument_checking_17.f90 ++++ b/src/gcc/testsuite/gfortran.dg/argument_checking_17.f90 +@@ -0,0 +1,26 @@ ++! { dg-do compile } ++! ++! PR fortran/47569 ++! ++! Contributed by Jos de Kloe ++! ++module teststr ++ implicit none ++ integer, parameter :: GRH_SIZE = 20, NMAX = 41624 ++ type strtype ++ integer :: size ++ character :: mdr(NMAX) ++ end type strtype ++contains ++ subroutine sub2(string,str_size) ++ integer,intent(in) :: str_size ++ character,intent(out) :: string(str_size) ++ string(:) = 'a' ++ end subroutine sub2 ++ subroutine sub1(a) ++ type(strtype),intent(inout) :: a ++ call sub2(a%mdr(GRH_SIZE+1),a%size-GRH_SIZE) ++ end subroutine sub1 ++end module teststr ++ ++! { dg-final { cleanup-modules "teststr" } } +--- a/src/gcc/testsuite/gfortran.dg/array_constructor_33.f90 ++++ b/src/gcc/testsuite/gfortran.dg/array_constructor_33.f90 +@@ -1,4 +1,5 @@ + ! { dg-do compile } ++! { dg-timeout-factor 4 } + ! PR20923 gfortran slow for large array constructors. + ! Test case prepared from PR by Jerry DeLisle + program sel +--- a/src/gcc/testsuite/gfortran.dg/cray_pointers_2.f90 ++++ b/src/gcc/testsuite/gfortran.dg/cray_pointers_2.f90 +@@ -1,5 +1,8 @@ +-! { dg-do run } +-! { dg-options "-fcray-pointer -fbounds-check" } ++! Using two spaces between dg-do and run is a hack to keep gfortran-dg-runtest ++! from cycling through optimization options for this expensive test. ++! { dg-do run } ++! { dg-options "-O3 -fcray-pointer -fbounds-check" } ++! { dg-timeout-factor 4 } + ! Series of routines for testing a Cray pointer implementation + program craytest + common /errors/errors(400) +--- a/src/gcc/testsuite/gfortran.dg/debug/pr46756.f ++++ b/src/gcc/testsuite/gfortran.dg/debug/pr46756.f +@@ -0,0 +1,29 @@ ++C PR debug/46756, reduced from ../20010519-1.f ++C { dg-do compile } ++C { dg-options "-O -fcompare-debug" } ++ LOGICAL QDISK,QDW,QCMPCT ++ LOGICAL LNOMA,LRAISE,LSCI,LBIG ++ ASSIGN 801 TO I800 ! { dg-warning "Deleted feature: ASSIGN" "Deleted feature: ASSIGN" } ++ GOTO 800 ++ 801 CONTINUE ++ ASSIGN 761 TO I760 ! { dg-warning "Deleted feature: ASSIGN" "Deleted feature: ASSIGN" } ++ 761 CONTINUE ++ IF(LSCI) THEN ++ DO I=1,LENCM ++ ENDDO ++ ENDIF ++ DO WHILE((CVGMX.GT.TOLDIM).AND.(ITER.LT.ITMX)) ++ IF(.NOT.QDW) THEN ++ ASSIGN 641 to I640 ! { dg-warning "Deleted feature: ASSIGN" "Deleted feature: ASSIGN" } ++ GOTO 640 ++ 641 CONTINUE ++ ENDIF ++ ENDDO ++ GOTO 700 ++ 640 CONTINUE ++ GOTO I640 ! { dg-warning "Deleted feature: Assigned" "Assigned GO TO" } ++ 700 CONTINUE ++ GOTO I760 ! { dg-warning "Deleted feature: Assigned" "Assigned GO TO" } ++ 800 CONTINUE ++ GOTO I800 ! { dg-warning "Deleted feature: Assigned" "Assigned GO TO" } ++ END +--- a/src/gcc/testsuite/gfortran.dg/dependency_39.f90 ++++ b/src/gcc/testsuite/gfortran.dg/dependency_39.f90 +@@ -0,0 +1,37 @@ ++! { dg-do run } ++! PR 45777 - component ref aliases when both are pointers ++module m1 ++ type t1 ++ integer, dimension(:), allocatable :: data ++ end type t1 ++contains ++ subroutine s1(t,d) ++ integer, dimension(:), pointer :: d ++ type(t1), pointer :: t ++ d(1:5)=t%data(3:7) ++ end subroutine s1 ++ subroutine s2(d,t) ++ integer, dimension(:), pointer :: d ++ type(t1), pointer :: t ++ t%data(3:7) = d(1:5) ++ end subroutine s2 ++end module m1 ++ ++program main ++ use m1 ++ type(t1), pointer :: t ++ integer, dimension(:), pointer :: d ++ allocate(t) ++ allocate(t%data(10)) ++ t%data=(/(i,i=1,10)/) ++ d=>t%data(5:9) ++ call s1(t,d) ++ if (any(d.ne.(/3,4,5,6,7/))) call abort() ++ t%data=(/(i,i=1,10)/) ++ d=>t%data(1:5) ++ call s2(d,t) ++ if (any(t%data.ne.(/1,2,1,2,3,4,5,8,9,10/))) call abort ++ deallocate(t%data) ++ deallocate(t) ++end program main ++! { dg-final { cleanup-modules "m1" } } +--- a/src/gcc/testsuite/gfortran.dg/func_result_6.f90 ++++ b/src/gcc/testsuite/gfortran.dg/func_result_6.f90 +@@ -0,0 +1,73 @@ ++! { dg-do run } ++! ++! PR fortran/47775 ++! ++! Contributed by Fran Martinez Fadrique ++! ++! Before, a temporary was missing for generic procedured (cf. test()) ++! as the allocatable attribute was ignored for the check whether a ++! temporary is required ++! ++module m ++type t ++contains ++ procedure, NOPASS :: foo => foo ++ generic :: gen => foo ++end type t ++contains ++ function foo(i) ++ integer, allocatable :: foo(:) ++ integer :: i ++ allocate(foo(2)) ++ foo(1) = i ++ foo(2) = i + 10 ++ end function foo ++end module m ++ ++use m ++type(t) :: x ++integer, pointer :: ptr1, ptr2 ++integer, target :: bar1(2) ++integer, target, allocatable :: bar2(:) ++ ++allocate(bar2(2)) ++ptr1 => bar1(2) ++ptr2 => bar2(2) ++ ++bar1 = x%gen(1) ++if (ptr1 /= 11) call abort() ++bar1 = x%foo(2) ++if (ptr1 /= 12) call abort() ++bar2 = x%gen(3) ++if (ptr2 /= 13) call abort() ++bar2 = x%foo(4) ++if (ptr2 /= 14) call abort() ++bar2(:) = x%gen(5) ++if (ptr2 /= 15) call abort() ++bar2(:) = x%foo(6) ++if (ptr2 /= 16) call abort() ++ ++call test() ++end ++ ++subroutine test ++interface gen ++ procedure foo ++end interface gen ++ ++integer, target :: bar(2) ++integer, pointer :: ptr ++bar = [1,2] ++ptr => bar(2) ++if (ptr /= 2) call abort() ++bar = gen() ++if (ptr /= 77) call abort() ++contains ++ function foo() ++ integer, allocatable :: foo(:) ++ allocate(foo(2)) ++ foo = [33, 77] ++ end function foo ++end subroutine test ++ ++! { dg-final { cleanup-modules "m" } } +--- a/src/gcc/testsuite/gfortran.dg/gomp/pr47331.f90 ++++ b/src/gcc/testsuite/gfortran.dg/gomp/pr47331.f90 +@@ -0,0 +1,24 @@ ++! PR fortran/47331 ++! { dg-do compile } ++! { dg-options "-fopenmp -fwhole-file" } ++ ++subroutine foo ++ !$omp parallel ++ call bar () ++ !$omp end parallel ++end subroutine foo ++ ++subroutine bar ++ integer :: k ++ do k=1,5 ++ call baz (k) ++ end do ++end subroutine bar ++ ++subroutine baz (k) ++ integer :: k ++end subroutine ++ ++program pr47331 ++ call foo ++end program pr47331 +--- a/src/gcc/testsuite/gfortran.dg/ldist-1.f90 ++++ b/src/gcc/testsuite/gfortran.dg/ldist-1.f90 +@@ -29,5 +29,8 @@ + return + end Subroutine PADEC + +-! { dg-final { scan-tree-dump-times "distributed: split to 4 loops" 1 "ldist" } } ++! There are 5 legal partitions in this code. Based on the data ++! locality heuristic, this loop should not be split. ++ ++! { dg-final { scan-tree-dump-not "distributed: split to" "ldist" } } + ! { dg-final { cleanup-tree-dump "ldist" } } +--- a/src/gcc/testsuite/gfortran.dg/ldist-pr43023.f90 ++++ b/src/gcc/testsuite/gfortran.dg/ldist-pr43023.f90 +@@ -0,0 +1,31 @@ ++! { dg-do compile } ++! { dg-options "-O2 -ftree-loop-distribution" } ++ ++MODULE NFT_mod ++ ++implicit none ++integer :: Nangle ++real:: Z0 ++real, dimension(:,:), allocatable :: Angle ++real, dimension(:), allocatable :: exth, ezth, hxth, hyth, hyphi ++ ++CONTAINS ++ ++SUBROUTINE NFT_Init() ++ ++real :: th, fi ++integer :: n ++ ++do n = 1,Nangle ++ th = Angle(n,1) ++ fi = Angle(n,2) ++ ++ exth(n) = cos(fi)*cos(th) ++ ezth(n) = -sin(th) ++ hxth(n) = -sin(fi) ++ hyth(n) = cos(fi) ++ hyphi(n) = -sin(fi) ++end do ++END SUBROUTINE NFT_Init ++ ++END MODULE NFT_mod +--- a/src/gcc/testsuite/gfortran.dg/power2.f90 ++++ b/src/gcc/testsuite/gfortran.dg/power2.f90 +@@ -13,6 +13,9 @@ + INTEGER(KIND=1) :: k1 + INTEGER(KIND=2) :: k2 + ++ k1 = 1_1 ++ k2 = 1_2 ++ + k1 = 1_1 + 1_1**k1 + k2 = 1_2 + 1_2**k2 + +--- a/src/gcc/testsuite/gfortran.dg/pr44592.f90 ++++ b/src/gcc/testsuite/gfortran.dg/pr44592.f90 +@@ -0,0 +1,20 @@ ++! { dg-do run } ++! { dg-options "-O3" } ++! From forall_12.f90 ++! Fails with loop reversal at -O3 ++! ++ character(len=1) :: b(4) = (/"1","2","3","4"/), c(4) ++ c = b ++ i = 1 ++ ! This statement must be here for the abort below ++ b(1:3)(i:i) = b(2:4)(i:i) ++ ++ b = c ++ b(4:2:-1)(i:i) = b(3:1:-1)(i:i) ++ ++ ! This fails. If the condition is printed, the result is F F F F ++ if (any (b .ne. (/"1","1","2","3"/))) i = 2 ++ print *, b ++ print *, b .ne. (/"1","1","2","3"/) ++ if (i == 2) call abort ++end +--- a/src/gcc/testsuite/gfortran.dg/pr46804.f90 ++++ b/src/gcc/testsuite/gfortran.dg/pr46804.f90 +@@ -0,0 +1,36 @@ ++! PR rtl-optimization/46804 ++! { dg-do run } ++! { dg-options "-O -fPIC -fexpensive-optimizations -fgcse -foptimize-register-move -fpeel-loops -fno-tree-loop-optimize" } ++ ++program main ++ integer, parameter :: n1 = 2, n2 = 3, n3 = 4, slen = 3 ++ character (len = slen), dimension (n1, n2, n3) :: a ++ integer (kind = 1), dimension (2, 4) :: shift1 ++ integer (kind = 2), dimension (2, 4) :: shift2 ++ integer (kind = 4), dimension (2, 4) :: shift3 ++ do i3 = 1, n3 ++ do i2 = 1, n2 ++ do i1 = 1, n1 ++ a (i1, i2, i3) = 'ab'(i1:i1) // 'cde'(i2:i2) // 'fghi'(i3:i3) ++ end do ++ end do ++ end do ++ shift1 (1, :) = (/ 4, 11, 19, 20 /) ++ shift1 (2, :) = (/ 55, 5, 1, 2 /) ++ shift2 = shift1 ++ shift3 = shift1 ++ call test (cshift (a, shift2, 2)) ++ call test (cshift (a, shift3, 2)) ++contains ++ subroutine test (b) ++ character (len = slen), dimension (n1, n2, n3) :: b ++ do i3 = 1, n3 ++ do i2 = 1, n2 ++ do i1 = 1, n1 ++ i2p = mod (shift1 (i1, i3) + i2 - 1, n2) + 1 ++ if (b (i1, i2, i3) .ne. a (i1, i2p, i3)) call abort ++ end do ++ end do ++ end do ++ end subroutine test ++end program main +--- a/src/gcc/testsuite/gfortran.dg/redefined_intrinsic_assignment_2.f90 ++++ b/src/gcc/testsuite/gfortran.dg/redefined_intrinsic_assignment_2.f90 +@@ -0,0 +1,68 @@ ++! { dg-do compile } ++! ++! PR fortran/47448 ++! ++! ASSIGNMENT(=) checks. Defined assignment is allowed if and only if ++! it does not override an intrinsic assignment. ++! ++ ++module test1 ++ interface assignment(=) ++ module procedure valid, valid2 ++ end interface ++contains ++ ! Valid: scalar = array ++ subroutine valid (lhs,rhs) ++ integer, intent(out) :: lhs ++ integer, intent(in) :: rhs(:) ++ lhs = rhs(1) ++ end subroutine valid ++ ++ ! Valid: array of different ranks ++ subroutine valid2 (lhs,rhs) ++ integer, intent(out) :: lhs(:) ++ integer, intent(in) :: rhs(:,:) ++ lhs(:) = rhs(:,1) ++ end subroutine valid2 ++end module test1 ++ ++module test2 ++ interface assignment(=) ++ module procedure invalid ++ end interface ++contains ++ ! Invalid: scalar = scalar ++ subroutine invalid (lhs,rhs) ! { dg-error "must not redefine an INTRINSIC type assignment" } ++ integer, intent(out) :: lhs ++ integer, intent(in) :: rhs ++ lhs = rhs ++ end subroutine invalid ++end module test2 ++ ++module test3 ++ interface assignment(=) ++ module procedure invalid2 ++ end interface ++contains ++ ! Invalid: array = scalar ++ subroutine invalid2 (lhs,rhs) ! { dg-error "must not redefine an INTRINSIC type assignment" } ++ integer, intent(out) :: lhs(:) ++ integer, intent(in) :: rhs ++ lhs(:) = rhs ++ end subroutine invalid2 ++end module test3 ++ ++module test4 ++ interface assignment(=) ++ module procedure invalid3 ++ end interface ++contains ++ ! Invalid: array = array for same rank ++ subroutine invalid3 (lhs,rhs) ! { dg-error "must not redefine an INTRINSIC type assignment" } ++ integer, intent(out) :: lhs(:) ++ integer, intent(in) :: rhs(:) ++ lhs(:) = rhs(:) ++ end subroutine invalid3 ++end module test4 ++ ++! { dg-final { cleanup-modules "test1" } } +--- a/src/gcc/testsuite/gfortran.dg/userdef_operator_2.f90 ++++ b/src/gcc/testsuite/gfortran.dg/userdef_operator_2.f90 +@@ -0,0 +1,17 @@ ++! { dg-do compile } ++! PR 45338 - no ICE when cmp is not used explicitly. ++! Test case by Simon Smart ++module test_mod ++ implicit none ++contains ++ subroutine test_fn (cmp) ++ interface operator(.myop.) ++ pure function cmp (a, b) result(ret) ++ integer, intent(in) :: a, b ++ logical ret ++ end function cmp ++ end interface ++ integer :: a, b ++ print*, a .myop. b ++ end subroutine test_fn ++end module test_mod +--- a/src/gcc/testsuite/gfortran.dg/vect/vect.exp ++++ b/src/gcc/testsuite/gfortran.dg/vect/vect.exp +@@ -105,7 +105,7 @@ + } elseif [istarget "ia64-*-*"] { + set dg-do-what-default run + } elseif [is-effective-target arm_neon_ok] { +- lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp" ++ eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""] + if [is-effective-target arm_neon_hw] { + set dg-do-what-default run + } else { +--- a/src/gcc/testsuite/gnat.dg/opt13.adb ++++ b/src/gcc/testsuite/gnat.dg/opt13.adb +@@ -0,0 +1,13 @@ ++-- { dg-do run } ++-- { dg-options "-O" } ++ ++with Opt13_Pkg; use Opt13_Pkg; ++ ++procedure Opt13 is ++ T : My_Type; ++begin ++ Allocate (T); ++ if N /= 1 then ++ raise Program_Error; ++ end if; ++end; +--- a/src/gcc/testsuite/gnat.dg/opt13_pkg.adb ++++ b/src/gcc/testsuite/gnat.dg/opt13_pkg.adb +@@ -0,0 +1,31 @@ ++package body Opt13_Pkg is ++ ++ subtype Index_Type is Natural range 0 .. 16; ++ ++ type Arr is array (Index_Type range <>) of Integer; ++ ++ type Rec is record ++ F1, F2, F3 : Float; ++ N : Natural; ++ B1, B2 : Boolean; ++ F4 : Float; ++ end record; ++ ++ type Data (D : Index_Type) is record ++ A : Arr (1 .. D); ++ R : Rec; ++ end record; ++ ++ Zero : constant Rec := (0.0, 0.0, 0.0, 0, False, False, 0.0); ++ ++ procedure Allocate (T : out My_Type) is ++ begin ++ T := new Data (Index_Type'last); ++ T.R := Zero; ++ ++ for I in 1 .. T.A'last loop ++ N := 1; ++ end loop; ++ end; ++ ++end Opt13_Pkg; +--- a/src/gcc/testsuite/gnat.dg/opt13_pkg.ads ++++ b/src/gcc/testsuite/gnat.dg/opt13_pkg.ads +@@ -0,0 +1,15 @@ ++package Opt13_Pkg is ++ ++ N : Natural := 0; ++ ++ type My_Type is private; ++ ++ procedure Allocate (T : out My_Type); ++ ++private ++ ++ type Data; ++ ++ type My_Type is access Data; ++ ++end Opt13_Pkg; +--- a/src/gcc/testsuite/lib/lto.exp ++++ b/src/gcc/testsuite/lib/lto.exp +@@ -156,6 +156,7 @@ + global testcase + global tool + global compile_type ++ global board_info + + # Check that all of the objects were built successfully. + foreach obj [split $objlist] { +@@ -170,10 +171,29 @@ + set options "" + lappend options "additional_flags=$optall $optfile" + ++ set target_board [target_info name] ++ set relocatable 0 ++ ++ # Some LTO tests do relocatable linking. Some target boards set ++ # a linker script which can't be used for relocatable linking. ++ # Use the default linker script instead. ++ if { [lsearch -exact [split "$optall $optfile"] "-r"] >= 0 } { ++ set relocatable 1 ++ } ++ ++ if { $relocatable } { ++ set saved_ldscript [board_info $target_board ldscript] ++ set board_info($target_board,ldscript) "" ++ } ++ + # Link the objects into an executable. + set comp_output [${tool}_target_compile "$objlist" $dest executable \ + "$options"] + ++ if { $relocatable } { ++ set board_info($target_board,ldscript) $saved_ldscript ++ } ++ + # Prune unimportant visibility warnings before checking output. + set comp_output [lto_prune_warns $comp_output] + +--- a/src/gcc/testsuite/lib/target-supports.exp ++++ b/src/gcc/testsuite/lib/target-supports.exp +@@ -1,5 +1,5 @@ +-# Copyright (C) 1999, 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +-# Free Software Foundation, Inc. ++# Copyright (C) 1999, 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, ++# 2011 Free Software Foundation, Inc. + + # This program is free software; you can redistribute it and/or modify + # it under the terms of the GNU General Public License as published by +@@ -1005,6 +1005,30 @@ + }] + } + ++# Return 1 if the target supports executing AVX instructions, 0 ++# otherwise. Cache the result. ++ ++proc check_avx_hw_available { } { ++ return [check_cached_effective_target avx_hw_available { ++ # If this is not the right target then we can skip the test. ++ if { !([istarget x86_64-*-*] || [istarget i?86-*-*]) } { ++ expr 0 ++ } else { ++ check_runtime_nocache avx_hw_available { ++ #include "cpuid.h" ++ int main () ++ { ++ unsigned int eax, ebx, ecx, edx; ++ if (__get_cpuid (1, &eax, &ebx, &ecx, &edx)) ++ return ((ecx & (bit_AVX | bit_OSXSAVE)) ++ != (bit_AVX | bit_OSXSAVE)); ++ return 1; ++ } ++ } "" ++ } ++ }] ++} ++ + # Return 1 if the target supports running SSE executables, 0 otherwise. + + proc check_effective_target_sse_runtime { } { +@@ -1025,6 +1049,16 @@ + } + } + ++# Return 1 if the target supports running AVX executables, 0 otherwise. ++ ++proc check_effective_target_avx_runtime { } { ++ if { [check_effective_target_avx] ++ && [check_avx_hw_available] } { ++ return 1 ++ } ++ return 0 ++} ++ + # Return 1 if the target supports executing VSX instructions, 0 + # otherwise. Cache the result. + +@@ -1667,6 +1701,18 @@ + }] + } + ++# Return 1 if this is an ARM target that only supports aligned vector accesses ++proc check_effective_target_arm_vect_no_misalign { } { ++ return [check_no_compiler_messages arm_vect_no_misalign assembly { ++ #if !defined(__arm__) \ ++ || (defined(__ARMEL__) \ ++ && (!defined(__thumb__) || defined(__thumb2__))) ++ #error FOO ++ #endif ++ }] ++} ++ ++ + # Return 1 if this is an ARM target supporting -mfpu=vfp + # -mfloat-abi=softfp. Some multilibs may be incompatible with these + # options. +@@ -1695,19 +1741,87 @@ + } + } + ++# Add the options needed for NEON. We need either -mfloat-abi=softfp ++# or -mfloat-abi=hard, but if one is already specified by the ++# multilib, use it. Similarly, if a -mfpu option already enables ++# NEON, do not add -mfpu=neon. ++ ++proc add_options_for_arm_neon { flags } { ++ if { ! [check_effective_target_arm_neon_ok] } { ++ return "$flags" ++ } ++ global et_arm_neon_flags ++ return "$flags $et_arm_neon_flags" ++} ++ + # Return 1 if this is an ARM target supporting -mfpu=neon +-# -mfloat-abi=softfp. Some multilibs may be incompatible with these +-# options. ++# -mfloat-abi=softfp or equivalent options. Some multilibs may be ++# incompatible with these options. Also set et_arm_neon_flags to the ++# best options to add. ++ ++proc check_effective_target_arm_neon_ok_nocache { } { ++ global et_arm_neon_flags ++ set et_arm_neon_flags "" ++ if { [check_effective_target_arm32] } { ++ foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp"} { ++ if { [check_no_compiler_messages_nocache arm_neon_ok object { ++ #include "arm_neon.h" ++ int dummy; ++ } "$flags"] } { ++ set et_arm_neon_flags $flags ++ return 1 ++ } ++ } ++ } ++ ++ return 0 ++} + + proc check_effective_target_arm_neon_ok { } { ++ return [check_cached_effective_target arm_neon_ok \ ++ check_effective_target_arm_neon_ok_nocache] ++} ++ ++# Add the options needed for NEON. We need either -mfloat-abi=softfp ++# or -mfloat-abi=hard, but if one is already specified by the ++# multilib, use it. ++ ++proc add_options_for_arm_neon_fp16 { flags } { ++ if { ! [check_effective_target_arm_neon_fp16_ok] } { ++ return "$flags" ++ } ++ global et_arm_neon_fp16_flags ++ return "$flags $et_arm_neon_fp16_flags" ++} ++ ++# Return 1 if this is an ARM target supporting -mfpu=neon-fp16 ++# -mfloat-abi=softfp or equivalent options. Some multilibs may be ++# incompatible with these options. Also set et_arm_neon_flags to the ++# best options to add. ++ ++proc check_effective_target_arm_neon_fp16_ok_nocache { } { ++ global et_arm_neon_fp16_flags ++ set et_arm_neon_fp16_flags "" + if { [check_effective_target_arm32] } { +- return [check_no_compiler_messages arm_neon_ok object { +- #include "arm_neon.h" +- int dummy; +- } "-mfpu=neon -mfloat-abi=softfp"] +- } else { +- return 0 ++ # Always add -mfpu=neon-fp16, since there is no preprocessor ++ # macro for FP16 support. ++ foreach flags {"-mfpu=neon-fp16" "-mfpu=neon-fp16 -mfloat-abi=softfp"} { ++ if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object { ++ #include "arm_neon.h" ++ int dummy; ++ } "$flags"] } { ++ set et_arm_neon_fp16_flags $flags ++ return 1 ++ } ++ } + } ++ ++ return 0 ++} ++ ++proc check_effective_target_arm_neon_fp16_ok { } { ++ return [check_cached_effective_target arm_neon_fp16_ok \ ++ check_effective_target_arm_neon_fp16_ok_nocache] + } + + # Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be +@@ -1746,7 +1860,7 @@ + : "0" (a), "w" (b)); + return (a != 1); + } +- } "-mfpu=neon -mfloat-abi=softfp"] ++ } [add_options_for_arm_neon ""]] + } + + # Return 1 if this is a ARM target with NEON enabled. +@@ -2025,6 +2139,26 @@ + return $et_vect_shift_saved + } + ++# Return 1 if the target supports hardware vector shift operation for char. ++ ++proc check_effective_target_vect_shift_char { } { ++ global et_vect_shift_char_saved ++ ++ if [info exists et_vect_shift_char_saved] { ++ verbose "check_effective_target_vect_shift_char: using cached result" 2 ++ } else { ++ set et_vect_shift_char_saved 0 ++ if { ([istarget powerpc*-*-*] ++ && ![istarget powerpc-*-linux*paired*]) ++ || [check_effective_target_arm32] } { ++ set et_vect_shift_char_saved 1 ++ } ++ } ++ ++ verbose "check_effective_target_vect_shift_char: returning $et_vect_shift_char_saved" 2 ++ return $et_vect_shift_char_saved ++} ++ + # Return 1 if the target supports hardware vectors of long, 0 otherwise. + # + # This can change for different subtargets so do not cache the result. +@@ -2444,7 +2578,8 @@ + if { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*]) + || [istarget i?86-*-*] + || [istarget x86_64-*-*] +- || [istarget spu-*-*] } { ++ || [istarget spu-*-*] ++ || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } { + set et_vect_unpack_saved 1 + } + } +@@ -2484,7 +2619,7 @@ + if { [istarget mipsisa64*-*-*] + || [istarget sparc*-*-*] + || [istarget ia64-*-*] +- || [check_effective_target_arm32] } { ++ || [check_effective_target_arm_vect_no_misalign] } { + set et_vect_no_align_saved 1 + } + } +@@ -2619,6 +2754,25 @@ + return $et_vector_alignment_reachable_for_64bit_saved + } + ++# Return 1 if the target only requires element alignment for vector accesses ++ ++proc check_effective_target_vect_element_align { } { ++ global et_vect_element_align ++ ++ if [info exists et_vect_element_align] { ++ verbose "check_effective_target_vect_element_align: using cached result" 2 ++ } else { ++ set et_vect_element_align 0 ++ if { [istarget arm*-*-*] ++ || [check_effective_target_vect_hw_misalign] } { ++ set et_vect_element_align 1 ++ } ++ } ++ ++ verbose "check_effective_target_vect_element_align: returning $et_vect_element_align" 2 ++ return $et_vect_element_align ++} ++ + # Return 1 if the target supports vector conditional operations, 0 otherwise. + + proc check_effective_target_vect_condition { } { +@@ -3176,6 +3330,16 @@ + } + + return $flags ++} ++ ++# Add to FLAGS the flags needed to enable 128-bit vectors. ++ ++proc add_options_for_quad_vectors { flags } { ++ if [is-effective-target arm_neon_ok] { ++ return "$flags -mvectorize-with-neon-quad" ++ } ++ ++ return $flags + } + + # Return 1 if the target provides a full C99 runtime. +--- a/src/gcc/testsuite/objc/execute/forward-1.x ++++ b/src/gcc/testsuite/objc/execute/forward-1.x +@@ -4,6 +4,7 @@ + + if { ([istarget x86_64-*-linux*] && [check_effective_target_lp64] ) + || [istarget powerpc*-*-linux*] ++ || [istarget arm*] + || [istarget powerpc*-*-aix*] + || [istarget s390*-*-*-linux*] + || [istarget sh4-*-linux*] +--- a/src/gcc/timevar.def ++++ b/src/gcc/timevar.def +@@ -162,6 +162,7 @@ + DEFTIMEVAR (TV_VARCONST , "varconst") + DEFTIMEVAR (TV_LOWER_SUBREG , "lower subreg") + DEFTIMEVAR (TV_JUMP , "jump") ++DEFTIMEVAR (TV_EE , "extension elimination") + DEFTIMEVAR (TV_FWPROP , "forward prop") + DEFTIMEVAR (TV_CSE , "CSE") + DEFTIMEVAR (TV_DCE , "dead code elimination") +--- a/src/gcc/toplev.c ++++ b/src/gcc/toplev.c +@@ -1851,6 +1851,13 @@ + sorry ("Graphite loop optimizations cannot be used"); + #endif + ++ if (flag_strict_volatile_bitfields > 0 && !abi_version_at_least (2)) ++ { ++ warning (0, "-fstrict-volatile-bitfield disabled; " ++ "it is incompatible with ABI versions < 2"); ++ flag_strict_volatile_bitfields = 0; ++ } ++ + /* Unrolling all loops implies that standard loop unrolling must also + be done. */ + if (flag_unroll_all_loops) +--- a/src/gcc/tree-cfg.c ++++ b/src/gcc/tree-cfg.c +@@ -47,6 +47,7 @@ + #include "value-prof.h" + #include "pointer-set.h" + #include "tree-inline.h" ++#include "target.h" + + /* This file contains functions for building the Control Flow Graph (CFG) + for a function tree. */ +@@ -3428,8 +3429,13 @@ + connected to the operand types. */ + return verify_gimple_comparison (lhs_type, rhs1, rhs2); + +- case WIDEN_SUM_EXPR: + case WIDEN_MULT_EXPR: ++ if (TREE_CODE (lhs_type) != INTEGER_TYPE) ++ return true; ++ return ((2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type)) ++ || (TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type))); ++ ++ case WIDEN_SUM_EXPR: + case VEC_WIDEN_MULT_HI_EXPR: + case VEC_WIDEN_MULT_LO_EXPR: + case VEC_PACK_TRUNC_EXPR: +@@ -3478,6 +3484,65 @@ + return false; + } + ++/* Verify a gimple assignment statement STMT with a ternary rhs. ++ Returns true if anything is wrong. */ ++ ++static bool ++verify_gimple_assign_ternary (gimple stmt) ++{ ++ enum tree_code rhs_code = gimple_assign_rhs_code (stmt); ++ tree lhs = gimple_assign_lhs (stmt); ++ tree lhs_type = TREE_TYPE (lhs); ++ tree rhs1 = gimple_assign_rhs1 (stmt); ++ tree rhs1_type = TREE_TYPE (rhs1); ++ tree rhs2 = gimple_assign_rhs2 (stmt); ++ tree rhs2_type = TREE_TYPE (rhs2); ++ tree rhs3 = gimple_assign_rhs3 (stmt); ++ tree rhs3_type = TREE_TYPE (rhs3); ++ ++ if (!is_gimple_reg (lhs) ++ && !(optimize == 0 ++ && TREE_CODE (lhs_type) == COMPLEX_TYPE)) ++ { ++ error ("non-register as LHS of ternary operation"); ++ return true; ++ } ++ ++ if (!is_gimple_val (rhs1) ++ || !is_gimple_val (rhs2) ++ || !is_gimple_val (rhs3)) ++ { ++ error ("invalid operands in ternary operation"); ++ return true; ++ } ++ ++ /* First handle operations that involve different types. */ ++ switch (rhs_code) ++ { ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ if ((!INTEGRAL_TYPE_P (rhs1_type) ++ && !FIXED_POINT_TYPE_P (rhs1_type)) ++ || !useless_type_conversion_p (rhs1_type, rhs2_type) ++ || !useless_type_conversion_p (lhs_type, rhs3_type) ++ || 2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type) ++ || TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type)) ++ { ++ error ("type mismatch in widening multiply-accumulate expression"); ++ debug_generic_expr (lhs_type); ++ debug_generic_expr (rhs1_type); ++ debug_generic_expr (rhs2_type); ++ debug_generic_expr (rhs3_type); ++ return true; ++ } ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ return false; ++} ++ + /* Verify a gimple assignment statement STMT with a single rhs. + Returns true if anything is wrong. */ + +@@ -3610,6 +3675,9 @@ + case GIMPLE_BINARY_RHS: + return verify_gimple_assign_binary (stmt); + ++ case GIMPLE_TERNARY_RHS: ++ return verify_gimple_assign_ternary (stmt); ++ + default: + gcc_unreachable (); + } +@@ -7078,6 +7146,9 @@ + edge e; + edge_iterator ei; + ++ if (!targetm.warn_func_result()) ++ return 0; ++ + /* If we have a path to EXIT, then we do return. */ + if (TREE_THIS_VOLATILE (cfun->decl) + && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0) +--- a/src/gcc/tree-data-ref.c ++++ b/src/gcc/tree-data-ref.c +@@ -4594,7 +4594,7 @@ + for (e = v->succ; e; e = e->succ_next) + fprintf (file, " %d", e->dest); + +- fprintf (file, ") \n"); ++ fprintf (file, ")\n"); + print_gimple_stmt (file, RDGV_STMT (v), 0, TDF_VOPS|TDF_MEMSYMS); + fprintf (file, ")\n"); + } +@@ -4991,6 +4991,38 @@ + free (bbs); + } + ++/* Returns true when the statement at STMT is of the form "A[i] = 0" ++ that contains a data reference on its LHS with a stride of the same ++ size as its unit type. */ ++ ++bool ++stmt_with_adjacent_zero_store_dr_p (gimple stmt) ++{ ++ tree op0, op1; ++ bool res; ++ struct data_reference *dr; ++ ++ if (!stmt ++ || !gimple_vdef (stmt) ++ || !is_gimple_assign (stmt) ++ || !gimple_assign_single_p (stmt) ++ || !(op1 = gimple_assign_rhs1 (stmt)) ++ || !(integer_zerop (op1) || real_zerop (op1))) ++ return false; ++ ++ dr = XCNEW (struct data_reference); ++ op0 = gimple_assign_lhs (stmt); ++ ++ DR_STMT (dr) = stmt; ++ DR_REF (dr) = op0; ++ ++ res = dr_analyze_innermost (dr) ++ && stride_of_unit_type_p (DR_STEP (dr), TREE_TYPE (op0)); ++ ++ free_data_ref (dr); ++ return res; ++} ++ + /* For a data reference REF, return the declaration of its base + address or NULL_TREE if the base is not determined. */ + +--- a/src/gcc/tree-data-ref.h ++++ b/src/gcc/tree-data-ref.h +@@ -567,6 +567,18 @@ + void remove_similar_memory_refs (VEC (gimple, heap) **); + bool rdg_defs_used_in_other_loops_p (struct graph *, int); + bool have_similar_memory_accesses (gimple, gimple); ++bool stmt_with_adjacent_zero_store_dr_p (gimple); ++ ++/* Returns true when STRIDE is equal in absolute value to the size of ++ the unit type of TYPE. */ ++ ++static inline bool ++stride_of_unit_type_p (tree stride, tree type) ++{ ++ return tree_int_cst_equal (fold_unary (ABS_EXPR, TREE_TYPE (stride), ++ stride), ++ TYPE_SIZE_UNIT (type)); ++} + + /* Determines whether RDG vertices V1 and V2 access to similar memory + locations, in which case they have to be in the same partition. */ +--- a/src/gcc/tree-if-switch-conversion.c ++++ b/src/gcc/tree-if-switch-conversion.c +@@ -0,0 +1,643 @@ ++/* Convert a chain of ifs into a switch. ++ Copyright (C) 2010 Free Software Foundation, Inc. ++ Contributed by Tom de Vries ++ ++This file is part of GCC. ++ ++GCC is free software; you can redistribute it and/or modify it ++under the terms of the GNU General Public License as published by the ++Free Software Foundation; either version 3, or (at your option) any ++later version. ++ ++GCC is distributed in the hope that it will be useful, but WITHOUT ++ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++for more details. ++ ++You should have received a copy of the GNU General Public License ++along with GCC; see the file COPYING3. If not, write to the Free ++Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA ++02110-1301, USA. */ ++ ++ ++/* The following pass converts a chain of ifs into a switch. ++ ++ The if-chain has the following properties: ++ - all bbs end in a GIMPLE_COND. ++ - all but the first bb are empty, apart from the GIMPLE_COND. ++ - the GIMPLE_CONDs compare the same variable against integer constants. ++ - the true gotos all target the same bb. ++ - the false gotos target the next in the if-chain. ++ ++ F.i., consider the following if-chain: ++ ... ++ : ++ ... ++ if (D.1993_3 == 32) ++ goto ; ++ else ++ goto ; ++ ++ : ++ if (D.1993_3 == 13) ++ goto ; ++ else ++ goto ; ++ ++ : ++ if (D.1993_3 == 10) ++ goto ; ++ else ++ goto ; ++ ++ : ++ if (D.1993_3 == 9) ++ goto ; ++ else ++ goto ; ++ ... ++ ++ The pass will report this if-chain like this: ++ ... ++ var: D.1993_3 ++ first: ++ true: ++ last: ++ constants: 9 10 13 32 ++ ... ++ ++ and then convert the if-chain into a switch: ++ ... ++ : ++ ... ++ switch (D.1993_3) , ++ case 9: , ++ case 10: , ++ case 13: , ++ case 32: > ++ ... ++ ++ The conversion does not happen if the chain is too short. The threshold is ++ determined by the parameter PARAM_IF_TO_SWITCH_THRESHOLD. ++ ++ The pass will try to construct a chain for each bb, unless the bb it is ++ already contained in a chain. This ensures that all chains will be found, ++ and that no chain will be constructed twice. The pass constructs and ++ converts the chains one-by-one, rather than first calculating all the chains ++ and then doing the conversions. ++ ++ The pass could detect range-checks in analyze_bb as well, and handle them. ++ Simple ones, like 'c <= 5', and more complex ones, like ++ '(unsigned char) c + 247 <= 1', which is generated by the C front-end from ++ code like '(c == 9 || c == 10)' or '(9 <= c && c <= 10)'. */ ++ ++#include "config.h" ++#include "system.h" ++#include "coretypes.h" ++#include "tm.h" ++ ++#include "params.h" ++#include "flags.h" ++#include "tree.h" ++#include "basic-block.h" ++#include "tree-flow.h" ++#include "tree-flow-inline.h" ++#include "tree-ssa-operands.h" ++#include "diagnostic.h" ++#include "tree-pass.h" ++#include "tree-dump.h" ++#include "timevar.h" ++ ++/* Information we've collected about a single bb. */ ++ ++struct ifsc_info ++{ ++ /* The variable of the bb's ending GIMPLE_COND, NULL_TREE if not present. */ ++ tree var; ++ /* The cond_code of the bb's ending GIMPLE_COND. */ ++ enum tree_code cond_code; ++ /* The constant of the bb's ending GIMPLE_COND. */ ++ tree constant; ++ /* Successor edge of the bb if its GIMPLE_COND is true. */ ++ edge true_edge; ++ /* Successor edge of the bb if its GIMPLE_COND is false. */ ++ edge false_edge; ++ /* Set if the bb has valid ifsc_info. */ ++ bool valid; ++ /* Set if the bb is part of a chain. */ ++ bool chained; ++}; ++ ++/* Macros to access the fields of struct ifsc_info. */ ++ ++#define BB_IFSC_VAR(bb) (((struct ifsc_info *)bb->aux)->var) ++#define BB_IFSC_COND_CODE(bb) (((struct ifsc_info *)bb->aux)->cond_code) ++#define BB_IFSC_CONSTANT(bb) (((struct ifsc_info *)bb->aux)->constant) ++#define BB_IFSC_TRUE_EDGE(bb) (((struct ifsc_info *)bb->aux)->true_edge) ++#define BB_IFSC_FALSE_EDGE(bb) (((struct ifsc_info *)bb->aux)->false_edge) ++#define BB_IFSC_VALID(bb) (((struct ifsc_info *)bb->aux)->valid) ++#define BB_IFSC_CHAINED(bb) (((struct ifsc_info *)bb->aux)->chained) ++ ++/* Data-type describing an if-chain. */ ++ ++struct if_chain ++{ ++ /* First bb in the chain. */ ++ basic_block first; ++ /* Last bb in the chain. */ ++ basic_block last; ++ /* Variable that GIMPLE_CONDs of all bbs in chain compare against. */ ++ tree var; ++ /* bb that all GIMPLE_CONDs jump to if comparison succeeds. */ ++ basic_block true_dest; ++ /* Constants that GIMPLE_CONDs of all bbs in chain compare var against. */ ++ VEC (tree, heap) *constants; ++ /* Same as previous, but sorted and with duplicates removed. */ ++ VEC (tree, heap) *unique_constants; ++}; ++ ++/* Utility macro. */ ++ ++#define SWAP(T, X, Y) do { T tmp = (X); (X) = (Y); (Y) = tmp; } while (0) ++ ++/* Helper function for sort_constants. */ ++ ++static int ++compare_constants (const void *p1, const void *p2) ++{ ++ const_tree const c1 = *(const_tree const*)p1; ++ const_tree const c2 = *(const_tree const*)p2; ++ ++ return tree_int_cst_compare (c1, c2); ++} ++ ++/* Sort constants in constants and copy to unique_constants, while skipping ++ duplicates. */ ++ ++static void ++sort_constants (VEC (tree,heap) *constants, VEC (tree,heap) **unique_constants) ++{ ++ size_t len = VEC_length (tree, constants); ++ unsigned int ix; ++ tree prev = NULL_TREE, constant; ++ ++ /* Sort constants. */ ++ qsort (VEC_address (tree, constants), len, sizeof (tree), ++ compare_constants); ++ ++ /* Copy to unique_constants, while skipping duplicates. */ ++ for (ix = 0; VEC_iterate (tree, constants, ix, constant); ix++) ++ { ++ if (prev != NULL_TREE && tree_int_cst_compare (prev, constant) == 0) ++ continue; ++ prev = constant; ++ ++ VEC_safe_push (tree, heap, *unique_constants, constant); ++ } ++} ++ ++/* Get true_edge and false_edge of a bb ending in a conditional jump. */ ++ ++static void ++get_edges (basic_block bb, edge *true_edge, edge *false_edge) ++{ ++ edge e0, e1; ++ int e0_true; ++ int n = EDGE_COUNT (bb->succs); ++ gcc_assert (n == 2); ++ ++ e0 = EDGE_SUCC (bb, 0); ++ e1 = EDGE_SUCC (bb, 1); ++ ++ e0_true = e0->flags & EDGE_TRUE_VALUE; ++ ++ *true_edge = e0_true ? e0 : e1; ++ *false_edge = e0_true ? e1 : e0; ++ ++ gcc_assert ((*true_edge)->flags & EDGE_TRUE_VALUE); ++ gcc_assert ((*false_edge)->flags & EDGE_FALSE_VALUE); ++ ++ gcc_assert (((*true_edge)->flags & EDGE_FALLTHRU) == 0); ++ gcc_assert (((*false_edge)->flags & EDGE_FALLTHRU) == 0); ++} ++ ++/* Analyze bb and store results in ifsc_info struct. */ ++ ++static void ++analyze_bb (basic_block bb) ++{ ++ gimple stmt = last_stmt (bb); ++ tree lhs, rhs, var, constant; ++ edge true_edge, false_edge; ++ enum tree_code cond_code; ++ ++ /* Don't redo analysis. */ ++ if (BB_IFSC_VALID (bb)) ++ return; ++ BB_IFSC_VALID (bb) = true; ++ ++ ++ /* bb needs to end in GIMPLE_COND. */ ++ if (!stmt || gimple_code (stmt) != GIMPLE_COND) ++ return; ++ ++ /* bb needs to end in EQ_EXPR or NE_EXPR. */ ++ cond_code = gimple_cond_code (stmt); ++ if (cond_code != EQ_EXPR && cond_code != NE_EXPR) ++ return; ++ ++ lhs = gimple_cond_lhs (stmt); ++ rhs = gimple_cond_rhs (stmt); ++ ++ /* GIMPLE_COND needs to compare variable to constant. */ ++ if ((TREE_CONSTANT (lhs) == 0) ++ == (TREE_CONSTANT (rhs) == 0)) ++ return; ++ ++ var = TREE_CONSTANT (lhs) ? rhs : lhs; ++ constant = TREE_CONSTANT (lhs)? lhs : rhs; ++ ++ /* Switches cannot handle non-integral types. */ ++ if (!INTEGRAL_TYPE_P(TREE_TYPE (var))) ++ return; ++ ++ get_edges (bb, &true_edge, &false_edge); ++ ++ if (cond_code == NE_EXPR) ++ SWAP (edge, true_edge, false_edge); ++ ++ /* TODO: loosen this constraint. In principle it's ok if true_edge->dest has ++ phis, as long as for each phi all the edges coming from the chain have the ++ same value. */ ++ if (!gimple_seq_empty_p (phi_nodes (true_edge->dest))) ++ return; ++ ++ /* Store analysis in ifsc_info struct. */ ++ BB_IFSC_VAR (bb) = var; ++ BB_IFSC_COND_CODE (bb) = cond_code; ++ BB_IFSC_CONSTANT (bb) = constant; ++ BB_IFSC_TRUE_EDGE (bb) = true_edge; ++ BB_IFSC_FALSE_EDGE (bb) = false_edge; ++} ++ ++/* Grow if-chain forward. */ ++ ++static void ++grow_if_chain_forward (struct if_chain *chain) ++{ ++ basic_block next_bb; ++ ++ while (1) ++ { ++ next_bb = BB_IFSC_FALSE_EDGE (chain->last)->dest; ++ ++ /* next_bb is already part of another chain. */ ++ if (BB_IFSC_CHAINED (next_bb)) ++ break; ++ ++ /* next_bb needs to be dominated by the last bb. */ ++ if (!single_pred_p (next_bb)) ++ break; ++ ++ analyze_bb (next_bb); ++ ++ /* Does next_bb fit in chain? */ ++ if (BB_IFSC_VAR (next_bb) != chain->var ++ || BB_IFSC_TRUE_EDGE (next_bb)->dest != chain->true_dest) ++ break; ++ ++ /* We can only add empty bbs at the end of the chain. */ ++ if (first_stmt (next_bb) != last_stmt (next_bb)) ++ break; ++ ++ /* Add next_bb at end of chain. */ ++ VEC_safe_push (tree, heap, chain->constants, BB_IFSC_CONSTANT (next_bb)); ++ BB_IFSC_CHAINED (next_bb) = true; ++ chain->last = next_bb; ++ } ++} ++ ++/* Grow if-chain backward. */ ++ ++static void ++grow_if_chain_backward (struct if_chain *chain) ++{ ++ basic_block prev_bb; ++ ++ while (1) ++ { ++ /* First bb is not empty, cannot grow backwards. */ ++ if (first_stmt (chain->first) != last_stmt (chain->first)) ++ break; ++ ++ /* First bb has no single predecessor, cannot grow backwards. */ ++ if (!single_pred_p (chain->first)) ++ break; ++ ++ prev_bb = single_pred (chain->first); ++ ++ /* prev_bb is already part of another chain. */ ++ if (BB_IFSC_CHAINED (prev_bb)) ++ break; ++ ++ analyze_bb (prev_bb); ++ ++ /* Does prev_bb fit in chain? */ ++ if (BB_IFSC_VAR (prev_bb) != chain->var ++ || BB_IFSC_TRUE_EDGE (prev_bb)->dest != chain->true_dest) ++ break; ++ ++ /* Add prev_bb at beginning of chain. */ ++ VEC_safe_push (tree, heap, chain->constants, BB_IFSC_CONSTANT (prev_bb)); ++ BB_IFSC_CHAINED (prev_bb) = true; ++ chain->first = prev_bb; ++ } ++} ++ ++/* Grow if-chain containing bb. */ ++ ++static void ++grow_if_chain (basic_block bb, struct if_chain *chain) ++{ ++ /* Initialize chain to empty. */ ++ VEC_truncate (tree, chain->constants, 0); ++ VEC_truncate (tree, chain->unique_constants, 0); ++ ++ /* bb is already part of another chain. */ ++ if (BB_IFSC_CHAINED (bb)) ++ return; ++ ++ analyze_bb (bb); ++ ++ /* bb is not fit to be part of a chain. */ ++ if (BB_IFSC_VAR (bb) == NULL_TREE) ++ return; ++ ++ /* Set bb as initial part of the chain. */ ++ VEC_safe_push (tree, heap, chain->constants, BB_IFSC_CONSTANT (bb)); ++ chain->first = chain->last = bb; ++ chain->var = BB_IFSC_VAR (bb); ++ chain->true_dest = BB_IFSC_TRUE_EDGE (bb)->dest; ++ ++ /* bb is part of a chain now. */ ++ BB_IFSC_CHAINED (bb) = true; ++ ++ /* Grow chain to its maximum size. */ ++ grow_if_chain_forward (chain); ++ grow_if_chain_backward (chain); ++ ++ /* Sort constants and skip duplicates. */ ++ sort_constants (chain->constants, &chain->unique_constants); ++} ++ ++static void ++dump_tree_vector (VEC (tree, heap) *vec) ++{ ++ unsigned int ix; ++ tree constant; ++ ++ for (ix = 0; VEC_iterate (tree, vec, ix, constant); ix++) ++ { ++ if (ix != 0) ++ fprintf (dump_file, " "); ++ print_generic_expr (dump_file, constant, 0); ++ } ++ fprintf (dump_file, "\n"); ++} ++ ++/* Dump if-chain to dump_file. */ ++ ++static void ++dump_if_chain (struct if_chain *chain) ++{ ++ if (!dump_file) ++ return; ++ ++ fprintf (dump_file, "var: "); ++ print_generic_expr (dump_file, chain->var, 0); ++ fprintf (dump_file, "\n"); ++ fprintf (dump_file, "first: \n", chain->first->index); ++ fprintf (dump_file, "true: \n", chain->true_dest->index); ++ fprintf (dump_file, "last: \n",chain->last->index); ++ ++ fprintf (dump_file, "constants: "); ++ dump_tree_vector (chain->constants); ++ ++ if (VEC_length (tree, chain->unique_constants) ++ != VEC_length (tree, chain->constants)) ++ { ++ fprintf (dump_file, "unique_constants: "); ++ dump_tree_vector (chain->unique_constants); ++ } ++} ++ ++/* Remove redundant bbs and edges. */ ++ ++static void ++remove_redundant_bbs_and_edges (struct if_chain *chain, int *false_prob) ++{ ++ basic_block bb, next; ++ edge true_edge, false_edge; ++ ++ for (bb = chain->first;; bb = next) ++ { ++ true_edge = BB_IFSC_TRUE_EDGE (bb); ++ false_edge = BB_IFSC_FALSE_EDGE (bb); ++ ++ /* Determine next, before we delete false_edge. */ ++ next = false_edge->dest; ++ ++ /* Accumulate probability. */ ++ *false_prob = (*false_prob * false_edge->probability) / REG_BR_PROB_BASE; ++ ++ /* Don't remove the new true_edge. */ ++ if (bb != chain->first) ++ remove_edge (true_edge); ++ ++ /* Don't remove the new false_edge. */ ++ if (bb != chain->last) ++ remove_edge (false_edge); ++ ++ /* Don't remove the first bb. */ ++ if (bb != chain->first) ++ delete_basic_block (bb); ++ ++ /* Stop after last. */ ++ if (bb == chain->last) ++ break; ++ } ++} ++ ++/* Update control flow graph. */ ++ ++static void ++update_cfg (struct if_chain *chain) ++{ ++ edge true_edge, false_edge; ++ int false_prob; ++ int flags_mask = ~(EDGE_FALLTHRU|EDGE_TRUE_VALUE|EDGE_FALSE_VALUE); ++ ++ /* We keep these 2 edges, and remove the rest. We need this specific ++ false_edge, because a phi in chain->last->dest might reference (the index ++ of) this edge. For true_edge, we could pick any of them. */ ++ true_edge = BB_IFSC_TRUE_EDGE (chain->first); ++ false_edge = BB_IFSC_FALSE_EDGE (chain->last); ++ ++ /* Update true edge. */ ++ true_edge->flags &= flags_mask; ++ ++ /* Update false edge. */ ++ redirect_edge_pred (false_edge, chain->first); ++ false_edge->flags &= flags_mask; ++ ++ false_prob = REG_BR_PROB_BASE; ++ remove_redundant_bbs_and_edges (chain, &false_prob); ++ ++ /* Repair probabilities. */ ++ true_edge->probability = REG_BR_PROB_BASE - false_prob; ++ false_edge->probability = false_prob; ++ ++ /* Force recalculation of dominance info. */ ++ free_dominance_info (CDI_DOMINATORS); ++ free_dominance_info (CDI_POST_DOMINATORS); ++} ++ ++/* Create switch statement. Borrows from gimplify_switch_expr. */ ++ ++static void ++convert_if_chain_to_switch (struct if_chain *chain) ++{ ++ tree label_decl_true, label_decl_false; ++ gimple label_true, label_false, gimple_switch; ++ gimple_stmt_iterator gsi; ++ tree default_case, other_case, constant; ++ unsigned int ix; ++ VEC (tree, heap) *labels; ++ ++ labels = VEC_alloc (tree, heap, 8); ++ ++ /* Create and insert true jump label. */ ++ label_decl_true = create_artificial_label (UNKNOWN_LOCATION); ++ label_true = gimple_build_label (label_decl_true); ++ gsi = gsi_start_bb (chain->true_dest); ++ gsi_insert_before (&gsi, label_true, GSI_SAME_STMT); ++ ++ /* Create and insert false jump label. */ ++ label_decl_false = create_artificial_label (UNKNOWN_LOCATION); ++ label_false = gimple_build_label (label_decl_false); ++ gsi = gsi_start_bb (BB_IFSC_FALSE_EDGE (chain->last)->dest); ++ gsi_insert_before (&gsi, label_false, GSI_SAME_STMT); ++ ++ /* Create default case label. */ ++ default_case = build3 (CASE_LABEL_EXPR, void_type_node, ++ NULL_TREE, NULL_TREE, ++ label_decl_false); ++ ++ /* Create case labels. */ ++ for (ix = 0; VEC_iterate (tree, chain->unique_constants, ix, constant); ix++) ++ { ++ /* TODO: use ranges, as in gimplify_switch_expr. */ ++ other_case = build3 (CASE_LABEL_EXPR, void_type_node, ++ constant, NULL_TREE, ++ label_decl_true); ++ VEC_safe_push (tree, heap, labels, other_case); ++ } ++ ++ /* Create and insert switch. */ ++ gimple_switch = gimple_build_switch_vec (chain->var, default_case, labels); ++ gsi = gsi_for_stmt (last_stmt (chain->first)); ++ gsi_insert_before (&gsi, gimple_switch, GSI_SAME_STMT); ++ ++ /* Remove now obsolete if. */ ++ gsi_remove (&gsi, true); ++ ++ VEC_free (tree, heap, labels); ++} ++ ++/* Allocation and initialization. */ ++ ++static void ++init_pass (struct if_chain *chain) ++{ ++ alloc_aux_for_blocks (sizeof (struct ifsc_info)); ++ ++ chain->constants = VEC_alloc (tree, heap, 8); ++ chain->unique_constants = VEC_alloc (tree, heap, 8); ++} ++ ++/* Deallocation. */ ++ ++static void ++finish_pass (struct if_chain *chain) ++{ ++ free_aux_for_blocks (); ++ ++ VEC_free (tree, heap, chain->constants); ++ VEC_free (tree, heap, chain->unique_constants); ++} ++ ++/* Find if-chains and convert them to switches. */ ++ ++static unsigned int ++do_if_to_switch (void) ++{ ++ basic_block bb; ++ struct if_chain chain; ++ unsigned int convert_threshold = PARAM_VALUE (PARAM_IF_TO_SWITCH_THRESHOLD); ++ ++ init_pass (&chain); ++ ++ for (bb = cfun->cfg->x_entry_block_ptr->next_bb; ++ bb != cfun->cfg->x_exit_block_ptr;) ++ { ++ grow_if_chain (bb, &chain); ++ ++ do ++ bb = bb->next_bb; ++ while (BB_IFSC_CHAINED (bb)); ++ ++ /* Determine if the chain is long enough. */ ++ if (VEC_length (tree, chain.unique_constants) < convert_threshold) ++ continue; ++ ++ dump_if_chain (&chain); ++ ++ convert_if_chain_to_switch (&chain); ++ ++ update_cfg (&chain); ++ } ++ ++ finish_pass (&chain); ++ ++ return 0; ++} ++ ++/* The pass gate. */ ++ ++static bool ++if_to_switch_gate (void) ++{ ++ return flag_tree_if_to_switch_conversion; ++} ++ ++/* The pass definition. */ ++ ++struct gimple_opt_pass pass_if_to_switch = ++{ ++ { ++ GIMPLE_PASS, ++ "iftoswitch", /* name */ ++ if_to_switch_gate, /* gate */ ++ do_if_to_switch, /* execute */ ++ NULL, /* sub */ ++ NULL, /* next */ ++ 0, /* static_pass_number */ ++ TV_TREE_SWITCH_CONVERSION, /* tv_id */ ++ PROP_cfg | PROP_ssa, /* properties_required */ ++ 0, /* properties_provided */ ++ 0, /* properties_destroyed */ ++ 0, /* todo_flags_start */ ++ TODO_update_ssa | TODO_dump_func ++ | TODO_ggc_collect | TODO_verify_ssa /* todo_flags_finish */ ++ } ++}; +--- a/src/gcc/tree-inline.c ++++ b/src/gcc/tree-inline.c +@@ -229,6 +229,7 @@ + regions of the CFG, but this is expensive to test. */ + if (id->entry_bb + && is_gimple_reg (SSA_NAME_VAR (name)) ++ && SSA_NAME_OCCURS_IN_ABNORMAL_PHI (name) + && TREE_CODE (SSA_NAME_VAR (name)) != PARM_DECL + && (id->entry_bb != EDGE_SUCC (ENTRY_BLOCK_PTR, 0)->dest + || EDGE_COUNT (id->entry_bb->preds) != 1)) +@@ -3206,6 +3207,8 @@ + case WIDEN_SUM_EXPR: + case WIDEN_MULT_EXPR: + case DOT_PROD_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: + + case VEC_WIDEN_MULT_HI_EXPR: + case VEC_WIDEN_MULT_LO_EXPR: +@@ -3342,34 +3345,13 @@ + if (POINTER_TYPE_P (funtype)) + funtype = TREE_TYPE (funtype); + +- if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_MD) ++ if (is_simple_builtin (decl)) ++ return 0; ++ else if (is_inexpensive_builtin (decl)) + cost = weights->target_builtin_call_cost; + else + cost = weights->call_cost; + +- if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL) +- switch (DECL_FUNCTION_CODE (decl)) +- { +- case BUILT_IN_CONSTANT_P: +- return 0; +- case BUILT_IN_EXPECT: +- return 0; +- +- /* Prefetch instruction is not expensive. */ +- case BUILT_IN_PREFETCH: +- cost = weights->target_builtin_call_cost; +- break; +- +- /* Exception state returns or moves registers around. */ +- case BUILT_IN_EH_FILTER: +- case BUILT_IN_EH_POINTER: +- case BUILT_IN_EH_COPY_VALUES: +- return 0; +- +- default: +- break; +- } +- + if (decl) + funtype = TREE_TYPE (decl); + +--- a/src/gcc/tree-inline.h ++++ b/src/gcc/tree-inline.h +@@ -187,6 +187,6 @@ + extern tree remap_type (tree type, copy_body_data *id); + extern gimple_seq copy_gimple_seq_and_replace_locals (gimple_seq seq); + +-extern HOST_WIDE_INT estimated_stack_frame_size (void); ++extern HOST_WIDE_INT estimated_stack_frame_size (tree); + + #endif /* GCC_TREE_INLINE_H */ +--- a/src/gcc/tree-loop-distribution.c ++++ b/src/gcc/tree-loop-distribution.c +@@ -251,7 +251,7 @@ + + /* Generate a call to memset. Return true when the operation succeeded. */ + +-static bool ++static void + generate_memset_zero (gimple stmt, tree op0, tree nb_iter, + gimple_stmt_iterator bsi) + { +@@ -265,45 +265,27 @@ + + DR_STMT (dr) = stmt; + DR_REF (dr) = op0; +- if (!dr_analyze_innermost (dr)) +- goto end; ++ res = dr_analyze_innermost (dr); ++ gcc_assert (res && stride_of_unit_type_p (DR_STEP (dr), TREE_TYPE (op0))); + +- /* Test for a positive stride, iterating over every element. */ +- if (integer_zerop (size_binop (MINUS_EXPR, +- fold_convert (sizetype, DR_STEP (dr)), +- TYPE_SIZE_UNIT (TREE_TYPE (op0))))) +- { +- addr_base = fold_convert_loc (loc, sizetype, +- size_binop_loc (loc, PLUS_EXPR, +- DR_OFFSET (dr), +- DR_INIT (dr))); +- addr_base = fold_build2_loc (loc, POINTER_PLUS_EXPR, +- TREE_TYPE (DR_BASE_ADDRESS (dr)), +- DR_BASE_ADDRESS (dr), addr_base); +- +- nb_bytes = build_size_arg_loc (loc, nb_iter, op0, &stmt_list); +- } ++ nb_bytes = build_size_arg_loc (loc, nb_iter, op0, &stmt_list); ++ addr_base = size_binop_loc (loc, PLUS_EXPR, DR_OFFSET (dr), DR_INIT (dr)); ++ addr_base = fold_convert_loc (loc, sizetype, addr_base); + + /* Test for a negative stride, iterating over every element. */ +- else if (integer_zerop (size_binop (PLUS_EXPR, +- TYPE_SIZE_UNIT (TREE_TYPE (op0)), +- fold_convert (sizetype, DR_STEP (dr))))) ++ if (integer_zerop (size_binop (PLUS_EXPR, ++ TYPE_SIZE_UNIT (TREE_TYPE (op0)), ++ fold_convert (sizetype, DR_STEP (dr))))) + { +- nb_bytes = build_size_arg_loc (loc, nb_iter, op0, &stmt_list); +- +- addr_base = size_binop_loc (loc, PLUS_EXPR, DR_OFFSET (dr), DR_INIT (dr)); +- addr_base = fold_convert_loc (loc, sizetype, addr_base); + addr_base = size_binop_loc (loc, MINUS_EXPR, addr_base, + fold_convert_loc (loc, sizetype, nb_bytes)); + addr_base = size_binop_loc (loc, PLUS_EXPR, addr_base, + TYPE_SIZE_UNIT (TREE_TYPE (op0))); +- addr_base = fold_build2_loc (loc, POINTER_PLUS_EXPR, +- TREE_TYPE (DR_BASE_ADDRESS (dr)), +- DR_BASE_ADDRESS (dr), addr_base); + } +- else +- goto end; + ++ addr_base = fold_build2_loc (loc, POINTER_PLUS_EXPR, ++ TREE_TYPE (DR_BASE_ADDRESS (dr)), ++ DR_BASE_ADDRESS (dr), addr_base); + mem = force_gimple_operand (addr_base, &stmts, true, NULL); + gimple_seq_add_seq (&stmt_list, stmts); + +@@ -311,14 +293,11 @@ + fn_call = gimple_build_call (fn, 3, mem, integer_zero_node, nb_bytes); + gimple_seq_add_stmt (&stmt_list, fn_call); + gsi_insert_seq_after (&bsi, stmt_list, GSI_CONTINUE_LINKING); +- res = true; + + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "generated memset zero\n"); + +- end: + free_data_ref (dr); +- return res; + } + + /* Tries to generate a builtin function for the instructions of LOOP +@@ -332,7 +311,6 @@ + unsigned i, x = 0; + basic_block *bbs; + gimple write = NULL; +- tree op0, op1; + gimple_stmt_iterator bsi; + tree nb_iter = number_of_exit_cond_executions (loop); + +@@ -368,26 +346,17 @@ + } + } + +- if (!write) +- goto end; +- +- op0 = gimple_assign_lhs (write); +- op1 = gimple_assign_rhs1 (write); +- +- if (!(TREE_CODE (op0) == ARRAY_REF +- || TREE_CODE (op0) == INDIRECT_REF)) ++ if (!stmt_with_adjacent_zero_store_dr_p (write)) + goto end; + + /* The new statements will be placed before LOOP. */ + bsi = gsi_last_bb (loop_preheader_edge (loop)->src); +- +- if (gimple_assign_rhs_code (write) == INTEGER_CST +- && (integer_zerop (op1) || real_zerop (op1))) +- res = generate_memset_zero (write, op0, nb_iter, bsi); ++ generate_memset_zero (write, gimple_assign_lhs (write), nb_iter, bsi); ++ res = true; + + /* If this is the last partition for which we generate code, we have + to destroy the loop. */ +- if (res && !copy_p) ++ if (!copy_p) + { + unsigned nbbs = loop->num_nodes; + edge exit = single_exit (loop); +@@ -531,24 +500,6 @@ + static void rdg_flag_vertex_and_dependent (struct graph *, int, bitmap, bitmap, + bitmap, bool *); + +-/* Flag all the uses of U. */ +- +-static void +-rdg_flag_all_uses (struct graph *rdg, int u, bitmap partition, bitmap loops, +- bitmap processed, bool *part_has_writes) +-{ +- struct graph_edge *e; +- +- for (e = rdg->vertices[u].succ; e; e = e->succ_next) +- if (!bitmap_bit_p (processed, e->dest)) +- { +- rdg_flag_vertex_and_dependent (rdg, e->dest, partition, loops, +- processed, part_has_writes); +- rdg_flag_all_uses (rdg, e->dest, partition, loops, processed, +- part_has_writes); +- } +-} +- + /* Flag the uses of U stopping following the information from + upstream_mem_writes. */ + +@@ -720,68 +671,13 @@ + } + } + +-/* Flag all the nodes of RDG containing memory accesses that could +- potentially belong to arrays already accessed in the current +- PARTITION. */ +- +-static void +-rdg_flag_similar_memory_accesses (struct graph *rdg, bitmap partition, +- bitmap loops, bitmap processed, +- VEC (int, heap) **other_stores) +-{ +- bool foo; +- unsigned i, n; +- int j, k, kk; +- bitmap_iterator ii; +- struct graph_edge *e; +- +- EXECUTE_IF_SET_IN_BITMAP (partition, 0, i, ii) +- if (RDG_MEM_WRITE_STMT (rdg, i) +- || RDG_MEM_READS_STMT (rdg, i)) +- { +- for (j = 0; j < rdg->n_vertices; j++) +- if (!bitmap_bit_p (processed, j) +- && (RDG_MEM_WRITE_STMT (rdg, j) +- || RDG_MEM_READS_STMT (rdg, j)) +- && rdg_has_similar_memory_accesses (rdg, i, j)) +- { +- /* Flag first the node J itself, and all the nodes that +- are needed to compute J. */ +- rdg_flag_vertex_and_dependent (rdg, j, partition, loops, +- processed, &foo); +- +- /* When J is a read, we want to coalesce in the same +- PARTITION all the nodes that are using J: this is +- needed for better cache locality. */ +- rdg_flag_all_uses (rdg, j, partition, loops, processed, &foo); +- +- /* Remove from OTHER_STORES the vertex that we flagged. */ +- if (RDG_MEM_WRITE_STMT (rdg, j)) +- for (k = 0; VEC_iterate (int, *other_stores, k, kk); k++) +- if (kk == j) +- { +- VEC_unordered_remove (int, *other_stores, k); +- break; +- } +- } +- +- /* If the node I has two uses, then keep these together in the +- same PARTITION. */ +- for (n = 0, e = rdg->vertices[i].succ; e; e = e->succ_next, n++); +- +- if (n > 1) +- rdg_flag_all_uses (rdg, i, partition, loops, processed, &foo); +- } +-} +- + /* Returns a bitmap in which all the statements needed for computing + the strongly connected component C of the RDG are flagged, also + including the loop exit conditions. */ + + static bitmap + build_rdg_partition_for_component (struct graph *rdg, rdgc c, +- bool *part_has_writes, +- VEC (int, heap) **other_stores) ++ bool *part_has_writes) + { + int i, v; + bitmap partition = BITMAP_ALLOC (NULL); +@@ -793,13 +689,6 @@ + rdg_flag_vertex_and_dependent (rdg, v, partition, loops, processed, + part_has_writes); + +- /* Also iterate on the array of stores not in the starting vertices, +- and determine those vertices that have some memory affinity with +- the current nodes in the component: these are stores to the same +- arrays, i.e. we're taking care of cache locality. */ +- rdg_flag_similar_memory_accesses (rdg, partition, loops, processed, +- other_stores); +- + rdg_flag_loop_exits (rdg, loops, partition, processed, part_has_writes); + + BITMAP_FREE (processed); +@@ -863,6 +752,79 @@ + BITMAP_FREE (saved_components); + } + ++/* Returns true when it is possible to generate a builtin pattern for ++ the PARTITION of RDG. For the moment we detect only the memset ++ zero pattern. */ ++ ++static bool ++can_generate_builtin (struct graph *rdg, bitmap partition) ++{ ++ unsigned i; ++ bitmap_iterator bi; ++ int nb_reads = 0; ++ int nb_writes = 0; ++ int stores_zero = 0; ++ ++ EXECUTE_IF_SET_IN_BITMAP (partition, 0, i, bi) ++ if (RDG_MEM_READS_STMT (rdg, i)) ++ nb_reads++; ++ else if (RDG_MEM_WRITE_STMT (rdg, i)) ++ { ++ nb_writes++; ++ if (stmt_with_adjacent_zero_store_dr_p (RDG_STMT (rdg, i))) ++ stores_zero++; ++ } ++ ++ return stores_zero == 1 && nb_writes == 1 && nb_reads == 0; ++} ++ ++/* Returns true when PARTITION1 and PARTITION2 have similar memory ++ accesses in RDG. */ ++ ++static bool ++similar_memory_accesses (struct graph *rdg, bitmap partition1, ++ bitmap partition2) ++{ ++ unsigned i, j; ++ bitmap_iterator bi, bj; ++ ++ EXECUTE_IF_SET_IN_BITMAP (partition1, 0, i, bi) ++ if (RDG_MEM_WRITE_STMT (rdg, i) ++ || RDG_MEM_READS_STMT (rdg, i)) ++ EXECUTE_IF_SET_IN_BITMAP (partition2, 0, j, bj) ++ if (RDG_MEM_WRITE_STMT (rdg, j) ++ || RDG_MEM_READS_STMT (rdg, j)) ++ if (rdg_has_similar_memory_accesses (rdg, i, j)) ++ return true; ++ ++ return false; ++} ++ ++/* Fuse all the partitions from PARTITIONS that contain similar memory ++ references, i.e., we're taking care of cache locality. This ++ function does not fuse those partitions that contain patterns that ++ can be code generated with builtins. */ ++ ++static void ++fuse_partitions_with_similar_memory_accesses (struct graph *rdg, ++ VEC (bitmap, heap) **partitions) ++{ ++ int p1, p2; ++ bitmap partition1, partition2; ++ ++ for (p1 = 0; VEC_iterate (bitmap, *partitions, p1, partition1); p1++) ++ if (!can_generate_builtin (rdg, partition1)) ++ for (p2 = 0; VEC_iterate (bitmap, *partitions, p2, partition2); p2++) ++ if (p1 != p2 ++ && !can_generate_builtin (rdg, partition2) ++ && similar_memory_accesses (rdg, partition1, partition2)) ++ { ++ bitmap_ior_into (partition1, partition2); ++ VEC_ordered_remove (bitmap, *partitions, p2); ++ p2--; ++ } ++} ++ + /* Aggregate several components into a useful partition that is + registered in the PARTITIONS vector. Partitions will be + distributed in different loops. */ +@@ -885,8 +847,7 @@ + if (bitmap_bit_p (processed, v)) + continue; + +- np = build_rdg_partition_for_component (rdg, x, &part_has_writes, +- other_stores); ++ np = build_rdg_partition_for_component (rdg, x, &part_has_writes); + bitmap_ior_into (partition, np); + bitmap_ior_into (processed, np); + BITMAP_FREE (np); +@@ -932,6 +893,8 @@ + VEC_safe_push (bitmap, heap, *partitions, partition); + else + BITMAP_FREE (partition); ++ ++ fuse_partitions_with_similar_memory_accesses (rdg, partitions); + } + + /* Dump to FILE the PARTITIONS. */ +--- a/src/gcc/tree-pass.h ++++ b/src/gcc/tree-pass.h +@@ -407,6 +407,7 @@ + extern struct gimple_opt_pass pass_cse_reciprocals; + extern struct gimple_opt_pass pass_cse_sincos; + extern struct gimple_opt_pass pass_optimize_bswap; ++extern struct gimple_opt_pass pass_optimize_widening_mul; + extern struct gimple_opt_pass pass_warn_function_return; + extern struct gimple_opt_pass pass_warn_function_noreturn; + extern struct gimple_opt_pass pass_cselim; +@@ -467,6 +468,7 @@ + extern struct rtl_opt_pass pass_initial_value_sets; + extern struct rtl_opt_pass pass_unshare_all_rtl; + extern struct rtl_opt_pass pass_instantiate_virtual_regs; ++extern struct rtl_opt_pass pass_ee; + extern struct rtl_opt_pass pass_rtl_fwprop; + extern struct rtl_opt_pass pass_rtl_fwprop_addr; + extern struct rtl_opt_pass pass_jump2; +@@ -558,6 +560,7 @@ + extern struct gimple_opt_pass pass_all_early_optimizations; + extern struct gimple_opt_pass pass_update_address_taken; + extern struct gimple_opt_pass pass_convert_switch; ++extern struct gimple_opt_pass pass_if_to_switch; + + /* The root of the compilation pass tree, once constructed. */ + extern struct opt_pass *all_passes, *all_small_ipa_passes, *all_lowering_passes, +--- a/src/gcc/tree-pretty-print.c ++++ b/src/gcc/tree-pretty-print.c +@@ -1939,6 +1939,26 @@ + pp_string (buffer, " > "); + break; + ++ case WIDEN_MULT_PLUS_EXPR: ++ pp_string (buffer, " WIDEN_MULT_PLUS_EXPR < "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 2), spc, flags, false); ++ pp_string (buffer, " > "); ++ break; ++ ++ case WIDEN_MULT_MINUS_EXPR: ++ pp_string (buffer, " WIDEN_MULT_MINUS_EXPR < "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 2), spc, flags, false); ++ pp_string (buffer, " > "); ++ break; ++ + case OMP_PARALLEL: + pp_string (buffer, "#pragma omp parallel"); + dump_omp_clauses (buffer, OMP_PARALLEL_CLAUSES (node), spc, flags); +@@ -2432,6 +2452,8 @@ + case VEC_WIDEN_MULT_LO_EXPR: + case WIDEN_MULT_EXPR: + case DOT_PROD_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: + case MULT_EXPR: + case TRUNC_DIV_EXPR: + case CEIL_DIV_EXPR: +--- a/src/gcc/tree-sra.c ++++ b/src/gcc/tree-sra.c +@@ -809,7 +809,7 @@ + /* Return true iff TYPE is a RECORD_TYPE with fields that are either of gimple + register types or (recursively) records with only these two kinds of fields. + It also returns false if any of these records has a zero-size field as its +- last field. */ ++ last field or has a bit-field. */ + + static bool + type_consists_of_records_p (tree type) +@@ -825,6 +825,9 @@ + { + tree ft = TREE_TYPE (fld); + ++ if (DECL_BIT_FIELD (fld)) ++ return false; ++ + if (!is_gimple_reg_type (ft) + && !type_consists_of_records_p (ft)) + return false; +@@ -3413,7 +3416,10 @@ + else if (ac2->size != access->size) + return NULL; + +- if (access_precludes_ipa_sra_p (ac2)) ++ if (access_precludes_ipa_sra_p (ac2) ++ || (ac2->type != access->type ++ && (TREE_ADDRESSABLE (ac2->type) ++ || TREE_ADDRESSABLE (access->type)))) + return NULL; + + modification |= ac2->write; +@@ -4125,6 +4131,13 @@ + static bool + ipa_sra_preliminary_function_checks (struct cgraph_node *node) + { ++ if (!tree_versionable_function_p (current_function_decl)) ++ { ++ if (dump_file) ++ fprintf (dump_file, "Function isn't allowed to be versioned.\n"); ++ return false; ++ } ++ + if (!cgraph_node_can_be_local_p (node)) + { + if (dump_file) +--- a/src/gcc/tree-ssa-ccp.c ++++ b/src/gcc/tree-ssa-ccp.c +@@ -915,6 +915,23 @@ + TREE_TYPE (TREE_OPERAND (addr, 0)))); + } + ++/* Get operand number OPNR from the rhs of STMT. Before returning it, ++ simplify it to a constant if possible. */ ++ ++static tree ++get_rhs_assign_op_for_ccp (gimple stmt, int opnr) ++{ ++ tree op = gimple_op (stmt, opnr); ++ ++ if (TREE_CODE (op) == SSA_NAME) ++ { ++ prop_value_t *val = get_value (op); ++ if (val->lattice_val == CONSTANT) ++ op = get_value (op)->value; ++ } ++ return op; ++} ++ + /* CCP specific front-end to the non-destructive constant folding + routines. + +@@ -1037,15 +1054,7 @@ + Note that we know the single operand must be a constant, + so this should almost always return a simplified RHS. */ + tree lhs = gimple_assign_lhs (stmt); +- tree op0 = gimple_assign_rhs1 (stmt); +- +- /* Simplify the operand down to a constant. */ +- if (TREE_CODE (op0) == SSA_NAME) +- { +- prop_value_t *val = get_value (op0); +- if (val->lattice_val == CONSTANT) +- op0 = get_value (op0)->value; +- } ++ tree op0 = get_rhs_assign_op_for_ccp (stmt, 1); + + /* Conversions are useless for CCP purposes if they are + value-preserving. Thus the restrictions that +@@ -1082,23 +1091,8 @@ + case GIMPLE_BINARY_RHS: + { + /* Handle binary operators that can appear in GIMPLE form. */ +- tree op0 = gimple_assign_rhs1 (stmt); +- tree op1 = gimple_assign_rhs2 (stmt); +- +- /* Simplify the operands down to constants when appropriate. */ +- if (TREE_CODE (op0) == SSA_NAME) +- { +- prop_value_t *val = get_value (op0); +- if (val->lattice_val == CONSTANT) +- op0 = val->value; +- } +- +- if (TREE_CODE (op1) == SSA_NAME) +- { +- prop_value_t *val = get_value (op1); +- if (val->lattice_val == CONSTANT) +- op1 = val->value; +- } ++ tree op0 = get_rhs_assign_op_for_ccp (stmt, 1); ++ tree op1 = get_rhs_assign_op_for_ccp (stmt, 2); + + /* Fold &foo + CST into an invariant reference if possible. */ + if (gimple_assign_rhs_code (stmt) == POINTER_PLUS_EXPR +@@ -1115,6 +1109,17 @@ + gimple_expr_type (stmt), op0, op1); + } + ++ case GIMPLE_TERNARY_RHS: ++ { ++ /* Handle binary operators that can appear in GIMPLE form. */ ++ tree op0 = get_rhs_assign_op_for_ccp (stmt, 1); ++ tree op1 = get_rhs_assign_op_for_ccp (stmt, 2); ++ tree op2 = get_rhs_assign_op_for_ccp (stmt, 3); ++ ++ return fold_ternary_loc (loc, subcode, ++ gimple_expr_type (stmt), op0, op1, op2); ++ } ++ + default: + gcc_unreachable (); + } +@@ -2959,6 +2964,33 @@ + } + break; + ++ case GIMPLE_TERNARY_RHS: ++ result = fold_ternary_loc (loc, subcode, ++ TREE_TYPE (gimple_assign_lhs (stmt)), ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), ++ gimple_assign_rhs3 (stmt)); ++ ++ if (result) ++ { ++ STRIP_USELESS_TYPE_CONVERSION (result); ++ if (valid_gimple_rhs_p (result)) ++ return result; ++ ++ /* Fold might have produced non-GIMPLE, so if we trust it blindly ++ we lose canonicalization opportunities. Do not go again ++ through fold here though, or the same non-GIMPLE will be ++ produced. */ ++ if (commutative_ternary_tree_code (subcode) ++ && tree_swap_operands_p (gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), false)) ++ return build3 (subcode, TREE_TYPE (gimple_assign_lhs (stmt)), ++ gimple_assign_rhs2 (stmt), ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs3 (stmt)); ++ } ++ break; ++ + case GIMPLE_INVALID_RHS: + gcc_unreachable (); + } +@@ -3188,6 +3220,1059 @@ + return changed; + } + ++/* Canonicalize and possibly invert the boolean EXPR; return NULL_TREE ++ if EXPR is null or we don't know how. ++ If non-null, the result always has boolean type. */ ++ ++static tree ++canonicalize_bool (tree expr, bool invert) ++{ ++ if (!expr) ++ return NULL_TREE; ++ else if (invert) ++ { ++ if (integer_nonzerop (expr)) ++ return boolean_false_node; ++ else if (integer_zerop (expr)) ++ return boolean_true_node; ++ else if (TREE_CODE (expr) == SSA_NAME) ++ return fold_build2 (EQ_EXPR, boolean_type_node, expr, ++ build_int_cst (TREE_TYPE (expr), 0)); ++ else if (TREE_CODE_CLASS (TREE_CODE (expr)) == tcc_comparison) ++ return fold_build2 (invert_tree_comparison (TREE_CODE (expr), false), ++ boolean_type_node, ++ TREE_OPERAND (expr, 0), ++ TREE_OPERAND (expr, 1)); ++ else ++ return NULL_TREE; ++ } ++ else ++ { ++ if (TREE_CODE (TREE_TYPE (expr)) == BOOLEAN_TYPE) ++ return expr; ++ if (integer_nonzerop (expr)) ++ return boolean_true_node; ++ else if (integer_zerop (expr)) ++ return boolean_false_node; ++ else if (TREE_CODE (expr) == SSA_NAME) ++ return fold_build2 (NE_EXPR, boolean_type_node, expr, ++ build_int_cst (TREE_TYPE (expr), 0)); ++ else if (TREE_CODE_CLASS (TREE_CODE (expr)) == tcc_comparison) ++ return fold_build2 (TREE_CODE (expr), ++ boolean_type_node, ++ TREE_OPERAND (expr, 0), ++ TREE_OPERAND (expr, 1)); ++ else ++ return NULL_TREE; ++ } ++} ++ ++/* Check to see if a boolean expression EXPR is logically equivalent to the ++ comparison (OP1 CODE OP2). Check for various identities involving ++ SSA_NAMEs. */ ++ ++static bool ++same_bool_comparison_p (const_tree expr, enum tree_code code, ++ const_tree op1, const_tree op2) ++{ ++ gimple s; ++ ++ /* The obvious case. */ ++ if (TREE_CODE (expr) == code ++ && operand_equal_p (TREE_OPERAND (expr, 0), op1, 0) ++ && operand_equal_p (TREE_OPERAND (expr, 1), op2, 0)) ++ return true; ++ ++ /* Check for comparing (name, name != 0) and the case where expr ++ is an SSA_NAME with a definition matching the comparison. */ ++ if (TREE_CODE (expr) == SSA_NAME ++ && TREE_CODE (TREE_TYPE (expr)) == BOOLEAN_TYPE) ++ { ++ if (operand_equal_p (expr, op1, 0)) ++ return ((code == NE_EXPR && integer_zerop (op2)) ++ || (code == EQ_EXPR && integer_nonzerop (op2))); ++ s = SSA_NAME_DEF_STMT (expr); ++ if (is_gimple_assign (s) ++ && gimple_assign_rhs_code (s) == code ++ && operand_equal_p (gimple_assign_rhs1 (s), op1, 0) ++ && operand_equal_p (gimple_assign_rhs2 (s), op2, 0)) ++ return true; ++ } ++ ++ /* If op1 is of the form (name != 0) or (name == 0), and the definition ++ of name is a comparison, recurse. */ ++ if (TREE_CODE (op1) == SSA_NAME ++ && TREE_CODE (TREE_TYPE (op1)) == BOOLEAN_TYPE) ++ { ++ s = SSA_NAME_DEF_STMT (op1); ++ if (is_gimple_assign (s) ++ && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison) ++ { ++ enum tree_code c = gimple_assign_rhs_code (s); ++ if ((c == NE_EXPR && integer_zerop (op2)) ++ || (c == EQ_EXPR && integer_nonzerop (op2))) ++ return same_bool_comparison_p (expr, c, ++ gimple_assign_rhs1 (s), ++ gimple_assign_rhs2 (s)); ++ if ((c == EQ_EXPR && integer_zerop (op2)) ++ || (c == NE_EXPR && integer_nonzerop (op2))) ++ return same_bool_comparison_p (expr, ++ invert_tree_comparison (c, false), ++ gimple_assign_rhs1 (s), ++ gimple_assign_rhs2 (s)); ++ } ++ } ++ return false; ++} ++ ++/* Check to see if two boolean expressions OP1 and OP2 are logically ++ equivalent. */ ++ ++static bool ++same_bool_result_p (const_tree op1, const_tree op2) ++{ ++ /* Simple cases first. */ ++ if (operand_equal_p (op1, op2, 0)) ++ return true; ++ ++ /* Check the cases where at least one of the operands is a comparison. ++ These are a bit smarter than operand_equal_p in that they apply some ++ identifies on SSA_NAMEs. */ ++ if (TREE_CODE_CLASS (TREE_CODE (op2)) == tcc_comparison ++ && same_bool_comparison_p (op1, TREE_CODE (op2), ++ TREE_OPERAND (op2, 0), ++ TREE_OPERAND (op2, 1))) ++ return true; ++ if (TREE_CODE_CLASS (TREE_CODE (op1)) == tcc_comparison ++ && same_bool_comparison_p (op2, TREE_CODE (op1), ++ TREE_OPERAND (op1, 0), ++ TREE_OPERAND (op1, 1))) ++ return true; ++ ++ /* Default case. */ ++ return false; ++} ++ ++/* Forward declarations for some mutually recursive functions. */ ++ ++static tree ++and_comparisons_1 (enum tree_code code1, tree op1a, tree op1b, ++ enum tree_code code2, tree op2a, tree op2b); ++static tree ++and_var_with_comparison (tree var, bool invert, ++ enum tree_code code2, tree op2a, tree op2b); ++static tree ++and_var_with_comparison_1 (gimple stmt, ++ enum tree_code code2, tree op2a, tree op2b); ++static tree ++or_comparisons_1 (enum tree_code code1, tree op1a, tree op1b, ++ enum tree_code code2, tree op2a, tree op2b); ++static tree ++or_var_with_comparison (tree var, bool invert, ++ enum tree_code code2, tree op2a, tree op2b); ++static tree ++or_var_with_comparison_1 (gimple stmt, ++ enum tree_code code2, tree op2a, tree op2b); ++ ++/* Helper function for and_comparisons_1: try to simplify the AND of the ++ ssa variable VAR with the comparison specified by (OP2A CODE2 OP2B). ++ If INVERT is true, invert the value of the VAR before doing the AND. ++ Return NULL_EXPR if we can't simplify this to a single expression. */ ++ ++static tree ++and_var_with_comparison (tree var, bool invert, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ tree t; ++ gimple stmt = SSA_NAME_DEF_STMT (var); ++ ++ /* We can only deal with variables whose definitions are assignments. */ ++ if (!is_gimple_assign (stmt)) ++ return NULL_TREE; ++ ++ /* If we have an inverted comparison, apply DeMorgan's law and rewrite ++ !var AND (op2a code2 op2b) => !(var OR !(op2a code2 op2b)) ++ Then we only have to consider the simpler non-inverted cases. */ ++ if (invert) ++ t = or_var_with_comparison_1 (stmt, ++ invert_tree_comparison (code2, false), ++ op2a, op2b); ++ else ++ t = and_var_with_comparison_1 (stmt, code2, op2a, op2b); ++ return canonicalize_bool (t, invert); ++} ++ ++/* Try to simplify the AND of the ssa variable defined by the assignment ++ STMT with the comparison specified by (OP2A CODE2 OP2B). ++ Return NULL_EXPR if we can't simplify this to a single expression. */ ++ ++static tree ++and_var_with_comparison_1 (gimple stmt, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ tree var = gimple_assign_lhs (stmt); ++ tree true_test_var = NULL_TREE; ++ tree false_test_var = NULL_TREE; ++ enum tree_code innercode = gimple_assign_rhs_code (stmt); ++ ++ /* Check for identities like (var AND (var == 0)) => false. */ ++ if (TREE_CODE (op2a) == SSA_NAME ++ && TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE) ++ { ++ if ((code2 == NE_EXPR && integer_zerop (op2b)) ++ || (code2 == EQ_EXPR && integer_nonzerop (op2b))) ++ { ++ true_test_var = op2a; ++ if (var == true_test_var) ++ return var; ++ } ++ else if ((code2 == EQ_EXPR && integer_zerop (op2b)) ++ || (code2 == NE_EXPR && integer_nonzerop (op2b))) ++ { ++ false_test_var = op2a; ++ if (var == false_test_var) ++ return boolean_false_node; ++ } ++ } ++ ++ /* If the definition is a comparison, recurse on it. */ ++ if (TREE_CODE_CLASS (innercode) == tcc_comparison) ++ { ++ tree t = and_comparisons_1 (innercode, ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), ++ code2, ++ op2a, ++ op2b); ++ if (t) ++ return t; ++ } ++ ++ /* If the definition is an AND or OR expression, we may be able to ++ simplify by reassociating. */ ++ if (innercode == TRUTH_AND_EXPR ++ || innercode == TRUTH_OR_EXPR ++ || (TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE ++ && (innercode == BIT_AND_EXPR || innercode == BIT_IOR_EXPR))) ++ { ++ tree inner1 = gimple_assign_rhs1 (stmt); ++ tree inner2 = gimple_assign_rhs2 (stmt); ++ gimple s; ++ tree t; ++ tree partial = NULL_TREE; ++ bool is_and = (innercode == TRUTH_AND_EXPR || innercode == BIT_AND_EXPR); ++ ++ /* Check for boolean identities that don't require recursive examination ++ of inner1/inner2: ++ inner1 AND (inner1 AND inner2) => inner1 AND inner2 => var ++ inner1 AND (inner1 OR inner2) => inner1 ++ !inner1 AND (inner1 AND inner2) => false ++ !inner1 AND (inner1 OR inner2) => !inner1 AND inner2 ++ Likewise for similar cases involving inner2. */ ++ if (inner1 == true_test_var) ++ return (is_and ? var : inner1); ++ else if (inner2 == true_test_var) ++ return (is_and ? var : inner2); ++ else if (inner1 == false_test_var) ++ return (is_and ++ ? boolean_false_node ++ : and_var_with_comparison (inner2, false, code2, op2a, op2b)); ++ else if (inner2 == false_test_var) ++ return (is_and ++ ? boolean_false_node ++ : and_var_with_comparison (inner1, false, code2, op2a, op2b)); ++ ++ /* Next, redistribute/reassociate the AND across the inner tests. ++ Compute the first partial result, (inner1 AND (op2a code op2b)) */ ++ if (TREE_CODE (inner1) == SSA_NAME ++ && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner1)) ++ && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison ++ && (t = maybe_fold_and_comparisons (gimple_assign_rhs_code (s), ++ gimple_assign_rhs1 (s), ++ gimple_assign_rhs2 (s), ++ code2, op2a, op2b))) ++ { ++ /* Handle the AND case, where we are reassociating: ++ (inner1 AND inner2) AND (op2a code2 op2b) ++ => (t AND inner2) ++ If the partial result t is a constant, we win. Otherwise ++ continue on to try reassociating with the other inner test. */ ++ if (is_and) ++ { ++ if (integer_onep (t)) ++ return inner2; ++ else if (integer_zerop (t)) ++ return boolean_false_node; ++ } ++ ++ /* Handle the OR case, where we are redistributing: ++ (inner1 OR inner2) AND (op2a code2 op2b) ++ => (t OR (inner2 AND (op2a code2 op2b))) */ ++ else if (integer_onep (t)) ++ return boolean_true_node; ++ ++ /* Save partial result for later. */ ++ partial = t; ++ } ++ ++ /* Compute the second partial result, (inner2 AND (op2a code op2b)) */ ++ if (TREE_CODE (inner2) == SSA_NAME ++ && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner2)) ++ && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison ++ && (t = maybe_fold_and_comparisons (gimple_assign_rhs_code (s), ++ gimple_assign_rhs1 (s), ++ gimple_assign_rhs2 (s), ++ code2, op2a, op2b))) ++ { ++ /* Handle the AND case, where we are reassociating: ++ (inner1 AND inner2) AND (op2a code2 op2b) ++ => (inner1 AND t) */ ++ if (is_and) ++ { ++ if (integer_onep (t)) ++ return inner1; ++ else if (integer_zerop (t)) ++ return boolean_false_node; ++ /* If both are the same, we can apply the identity ++ (x AND x) == x. */ ++ else if (partial && same_bool_result_p (t, partial)) ++ return t; ++ } ++ ++ /* Handle the OR case. where we are redistributing: ++ (inner1 OR inner2) AND (op2a code2 op2b) ++ => (t OR (inner1 AND (op2a code2 op2b))) ++ => (t OR partial) */ ++ else ++ { ++ if (integer_onep (t)) ++ return boolean_true_node; ++ else if (partial) ++ { ++ /* We already got a simplification for the other ++ operand to the redistributed OR expression. The ++ interesting case is when at least one is false. ++ Or, if both are the same, we can apply the identity ++ (x OR x) == x. */ ++ if (integer_zerop (partial)) ++ return t; ++ else if (integer_zerop (t)) ++ return partial; ++ else if (same_bool_result_p (t, partial)) ++ return t; ++ } ++ } ++ } ++ } ++ return NULL_TREE; ++} ++ ++/* Try to simplify the AND of two comparisons defined by ++ (OP1A CODE1 OP1B) and (OP2A CODE2 OP2B), respectively. ++ If this can be done without constructing an intermediate value, ++ return the resulting tree; otherwise NULL_TREE is returned. ++ This function is deliberately asymmetric as it recurses on SSA_DEFs ++ in the first comparison but not the second. */ ++ ++static tree ++and_comparisons_1 (enum tree_code code1, tree op1a, tree op1b, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ /* First check for ((x CODE1 y) AND (x CODE2 y)). */ ++ if (operand_equal_p (op1a, op2a, 0) ++ && operand_equal_p (op1b, op2b, 0)) ++ { ++ tree t = combine_comparisons (UNKNOWN_LOCATION, ++ TRUTH_ANDIF_EXPR, code1, code2, ++ boolean_type_node, op1a, op1b); ++ if (t) ++ return t; ++ } ++ ++ /* Likewise the swapped case of the above. */ ++ if (operand_equal_p (op1a, op2b, 0) ++ && operand_equal_p (op1b, op2a, 0)) ++ { ++ tree t = combine_comparisons (UNKNOWN_LOCATION, ++ TRUTH_ANDIF_EXPR, code1, ++ swap_tree_comparison (code2), ++ boolean_type_node, op1a, op1b); ++ if (t) ++ return t; ++ } ++ ++ /* If both comparisons are of the same value against constants, we might ++ be able to merge them. */ ++ if (operand_equal_p (op1a, op2a, 0) ++ && TREE_CODE (op1b) == INTEGER_CST ++ && TREE_CODE (op2b) == INTEGER_CST) ++ { ++ int cmp = tree_int_cst_compare (op1b, op2b); ++ ++ /* If we have (op1a == op1b), we should either be able to ++ return that or FALSE, depending on whether the constant op1b ++ also satisfies the other comparison against op2b. */ ++ if (code1 == EQ_EXPR) ++ { ++ bool done = true; ++ bool val; ++ switch (code2) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp < 0); break; ++ case GT_EXPR: val = (cmp > 0); break; ++ case LE_EXPR: val = (cmp <= 0); break; ++ case GE_EXPR: val = (cmp >= 0); break; ++ default: done = false; ++ } ++ if (done) ++ { ++ if (val) ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ else ++ return boolean_false_node; ++ } ++ } ++ /* Likewise if the second comparison is an == comparison. */ ++ else if (code2 == EQ_EXPR) ++ { ++ bool done = true; ++ bool val; ++ switch (code1) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp > 0); break; ++ case GT_EXPR: val = (cmp < 0); break; ++ case LE_EXPR: val = (cmp >= 0); break; ++ case GE_EXPR: val = (cmp <= 0); break; ++ default: done = false; ++ } ++ if (done) ++ { ++ if (val) ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ else ++ return boolean_false_node; ++ } ++ } ++ ++ /* Same business with inequality tests. */ ++ else if (code1 == NE_EXPR) ++ { ++ bool val; ++ switch (code2) ++ { ++ case EQ_EXPR: val = (cmp != 0); break; ++ case NE_EXPR: val = (cmp == 0); break; ++ case LT_EXPR: val = (cmp >= 0); break; ++ case GT_EXPR: val = (cmp <= 0); break; ++ case LE_EXPR: val = (cmp > 0); break; ++ case GE_EXPR: val = (cmp < 0); break; ++ default: ++ val = false; ++ } ++ if (val) ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ } ++ else if (code2 == NE_EXPR) ++ { ++ bool val; ++ switch (code1) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp <= 0); break; ++ case GT_EXPR: val = (cmp >= 0); break; ++ case LE_EXPR: val = (cmp < 0); break; ++ case GE_EXPR: val = (cmp > 0); break; ++ default: ++ val = false; ++ } ++ if (val) ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ } ++ ++ /* Chose the more restrictive of two < or <= comparisons. */ ++ else if ((code1 == LT_EXPR || code1 == LE_EXPR) ++ && (code2 == LT_EXPR || code2 == LE_EXPR)) ++ { ++ if ((cmp < 0) || (cmp == 0 && code1 == LT_EXPR)) ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ else ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ } ++ ++ /* Likewise chose the more restrictive of two > or >= comparisons. */ ++ else if ((code1 == GT_EXPR || code1 == GE_EXPR) ++ && (code2 == GT_EXPR || code2 == GE_EXPR)) ++ { ++ if ((cmp > 0) || (cmp == 0 && code1 == GT_EXPR)) ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ else ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ } ++ ++ /* Check for singleton ranges. */ ++ else if (cmp == 0 ++ && ((code1 == LE_EXPR && code2 == GE_EXPR) ++ || (code1 == GE_EXPR && code2 == LE_EXPR))) ++ return fold_build2 (EQ_EXPR, boolean_type_node, op1a, op2b); ++ ++ /* Check for disjoint ranges. */ ++ else if (cmp <= 0 ++ && (code1 == LT_EXPR || code1 == LE_EXPR) ++ && (code2 == GT_EXPR || code2 == GE_EXPR)) ++ return boolean_false_node; ++ else if (cmp >= 0 ++ && (code1 == GT_EXPR || code1 == GE_EXPR) ++ && (code2 == LT_EXPR || code2 == LE_EXPR)) ++ return boolean_false_node; ++ } ++ ++ /* Perhaps the first comparison is (NAME != 0) or (NAME == 1) where ++ NAME's definition is a truth value. See if there are any simplifications ++ that can be done against the NAME's definition. */ ++ if (TREE_CODE (op1a) == SSA_NAME ++ && (code1 == NE_EXPR || code1 == EQ_EXPR) ++ && (integer_zerop (op1b) || integer_onep (op1b))) ++ { ++ bool invert = ((code1 == EQ_EXPR && integer_zerop (op1b)) ++ || (code1 == NE_EXPR && integer_onep (op1b))); ++ gimple stmt = SSA_NAME_DEF_STMT (op1a); ++ switch (gimple_code (stmt)) ++ { ++ case GIMPLE_ASSIGN: ++ /* Try to simplify by copy-propagating the definition. */ ++ return and_var_with_comparison (op1a, invert, code2, op2a, op2b); ++ ++ case GIMPLE_PHI: ++ /* If every argument to the PHI produces the same result when ++ ANDed with the second comparison, we win. ++ Do not do this unless the type is bool since we need a bool ++ result here anyway. */ ++ if (TREE_CODE (TREE_TYPE (op1a)) == BOOLEAN_TYPE) ++ { ++ tree result = NULL_TREE; ++ unsigned i; ++ for (i = 0; i < gimple_phi_num_args (stmt); i++) ++ { ++ tree arg = gimple_phi_arg_def (stmt, i); ++ ++ /* If this PHI has itself as an argument, ignore it. ++ If all the other args produce the same result, ++ we're still OK. */ ++ if (arg == gimple_phi_result (stmt)) ++ continue; ++ else if (TREE_CODE (arg) == INTEGER_CST) ++ { ++ if (invert ? integer_nonzerop (arg) : integer_zerop (arg)) ++ { ++ if (!result) ++ result = boolean_false_node; ++ else if (!integer_zerop (result)) ++ return NULL_TREE; ++ } ++ else if (!result) ++ result = fold_build2 (code2, boolean_type_node, ++ op2a, op2b); ++ else if (!same_bool_comparison_p (result, ++ code2, op2a, op2b)) ++ return NULL_TREE; ++ } ++ else if (TREE_CODE (arg) == SSA_NAME) ++ { ++ tree temp = and_var_with_comparison (arg, invert, ++ code2, op2a, op2b); ++ if (!temp) ++ return NULL_TREE; ++ else if (!result) ++ result = temp; ++ else if (!same_bool_result_p (result, temp)) ++ return NULL_TREE; ++ } ++ else ++ return NULL_TREE; ++ } ++ return result; ++ } ++ ++ default: ++ break; ++ } ++ } ++ return NULL_TREE; ++} ++ ++/* Try to simplify the AND of two comparisons, specified by ++ (OP1A CODE1 OP1B) and (OP2B CODE2 OP2B), respectively. ++ If this can be simplified to a single expression (without requiring ++ introducing more SSA variables to hold intermediate values), ++ return the resulting tree. Otherwise return NULL_TREE. ++ If the result expression is non-null, it has boolean type. */ ++ ++tree ++maybe_fold_and_comparisons (enum tree_code code1, tree op1a, tree op1b, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ tree t = and_comparisons_1 (code1, op1a, op1b, code2, op2a, op2b); ++ if (t) ++ return t; ++ else ++ return and_comparisons_1 (code2, op2a, op2b, code1, op1a, op1b); ++} ++ ++/* Helper function for or_comparisons_1: try to simplify the OR of the ++ ssa variable VAR with the comparison specified by (OP2A CODE2 OP2B). ++ If INVERT is true, invert the value of VAR before doing the OR. ++ Return NULL_EXPR if we can't simplify this to a single expression. */ ++ ++static tree ++or_var_with_comparison (tree var, bool invert, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ tree t; ++ gimple stmt = SSA_NAME_DEF_STMT (var); ++ ++ /* We can only deal with variables whose definitions are assignments. */ ++ if (!is_gimple_assign (stmt)) ++ return NULL_TREE; ++ ++ /* If we have an inverted comparison, apply DeMorgan's law and rewrite ++ !var OR (op2a code2 op2b) => !(var AND !(op2a code2 op2b)) ++ Then we only have to consider the simpler non-inverted cases. */ ++ if (invert) ++ t = and_var_with_comparison_1 (stmt, ++ invert_tree_comparison (code2, false), ++ op2a, op2b); ++ else ++ t = or_var_with_comparison_1 (stmt, code2, op2a, op2b); ++ return canonicalize_bool (t, invert); ++} ++ ++/* Try to simplify the OR of the ssa variable defined by the assignment ++ STMT with the comparison specified by (OP2A CODE2 OP2B). ++ Return NULL_EXPR if we can't simplify this to a single expression. */ ++ ++static tree ++or_var_with_comparison_1 (gimple stmt, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ tree var = gimple_assign_lhs (stmt); ++ tree true_test_var = NULL_TREE; ++ tree false_test_var = NULL_TREE; ++ enum tree_code innercode = gimple_assign_rhs_code (stmt); ++ ++ /* Check for identities like (var OR (var != 0)) => true . */ ++ if (TREE_CODE (op2a) == SSA_NAME ++ && TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE) ++ { ++ if ((code2 == NE_EXPR && integer_zerop (op2b)) ++ || (code2 == EQ_EXPR && integer_nonzerop (op2b))) ++ { ++ true_test_var = op2a; ++ if (var == true_test_var) ++ return var; ++ } ++ else if ((code2 == EQ_EXPR && integer_zerop (op2b)) ++ || (code2 == NE_EXPR && integer_nonzerop (op2b))) ++ { ++ false_test_var = op2a; ++ if (var == false_test_var) ++ return boolean_true_node; ++ } ++ } ++ ++ /* If the definition is a comparison, recurse on it. */ ++ if (TREE_CODE_CLASS (innercode) == tcc_comparison) ++ { ++ tree t = or_comparisons_1 (innercode, ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), ++ code2, ++ op2a, ++ op2b); ++ if (t) ++ return t; ++ } ++ ++ /* If the definition is an AND or OR expression, we may be able to ++ simplify by reassociating. */ ++ if (innercode == TRUTH_AND_EXPR ++ || innercode == TRUTH_OR_EXPR ++ || (TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE ++ && (innercode == BIT_AND_EXPR || innercode == BIT_IOR_EXPR))) ++ { ++ tree inner1 = gimple_assign_rhs1 (stmt); ++ tree inner2 = gimple_assign_rhs2 (stmt); ++ gimple s; ++ tree t; ++ tree partial = NULL_TREE; ++ bool is_or = (innercode == TRUTH_OR_EXPR || innercode == BIT_IOR_EXPR); ++ ++ /* Check for boolean identities that don't require recursive examination ++ of inner1/inner2: ++ inner1 OR (inner1 OR inner2) => inner1 OR inner2 => var ++ inner1 OR (inner1 AND inner2) => inner1 ++ !inner1 OR (inner1 OR inner2) => true ++ !inner1 OR (inner1 AND inner2) => !inner1 OR inner2 ++ */ ++ if (inner1 == true_test_var) ++ return (is_or ? var : inner1); ++ else if (inner2 == true_test_var) ++ return (is_or ? var : inner2); ++ else if (inner1 == false_test_var) ++ return (is_or ++ ? boolean_true_node ++ : or_var_with_comparison (inner2, false, code2, op2a, op2b)); ++ else if (inner2 == false_test_var) ++ return (is_or ++ ? boolean_true_node ++ : or_var_with_comparison (inner1, false, code2, op2a, op2b)); ++ ++ /* Next, redistribute/reassociate the OR across the inner tests. ++ Compute the first partial result, (inner1 OR (op2a code op2b)) */ ++ if (TREE_CODE (inner1) == SSA_NAME ++ && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner1)) ++ && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison ++ && (t = maybe_fold_or_comparisons (gimple_assign_rhs_code (s), ++ gimple_assign_rhs1 (s), ++ gimple_assign_rhs2 (s), ++ code2, op2a, op2b))) ++ { ++ /* Handle the OR case, where we are reassociating: ++ (inner1 OR inner2) OR (op2a code2 op2b) ++ => (t OR inner2) ++ If the partial result t is a constant, we win. Otherwise ++ continue on to try reassociating with the other inner test. */ ++ if (is_or) ++ { ++ if (integer_onep (t)) ++ return boolean_true_node; ++ else if (integer_zerop (t)) ++ return inner2; ++ } ++ ++ /* Handle the AND case, where we are redistributing: ++ (inner1 AND inner2) OR (op2a code2 op2b) ++ => (t AND (inner2 OR (op2a code op2b))) */ ++ else if (integer_zerop (t)) ++ return boolean_false_node; ++ ++ /* Save partial result for later. */ ++ partial = t; ++ } ++ ++ /* Compute the second partial result, (inner2 OR (op2a code op2b)) */ ++ if (TREE_CODE (inner2) == SSA_NAME ++ && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner2)) ++ && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison ++ && (t = maybe_fold_or_comparisons (gimple_assign_rhs_code (s), ++ gimple_assign_rhs1 (s), ++ gimple_assign_rhs2 (s), ++ code2, op2a, op2b))) ++ { ++ /* Handle the OR case, where we are reassociating: ++ (inner1 OR inner2) OR (op2a code2 op2b) ++ => (inner1 OR t) ++ => (t OR partial) */ ++ if (is_or) ++ { ++ if (integer_zerop (t)) ++ return inner1; ++ else if (integer_onep (t)) ++ return boolean_true_node; ++ /* If both are the same, we can apply the identity ++ (x OR x) == x. */ ++ else if (partial && same_bool_result_p (t, partial)) ++ return t; ++ } ++ ++ /* Handle the AND case, where we are redistributing: ++ (inner1 AND inner2) OR (op2a code2 op2b) ++ => (t AND (inner1 OR (op2a code2 op2b))) ++ => (t AND partial) */ ++ else ++ { ++ if (integer_zerop (t)) ++ return boolean_false_node; ++ else if (partial) ++ { ++ /* We already got a simplification for the other ++ operand to the redistributed AND expression. The ++ interesting case is when at least one is true. ++ Or, if both are the same, we can apply the identity ++ (x AND x) == x. */ ++ if (integer_onep (partial)) ++ return t; ++ else if (integer_onep (t)) ++ return partial; ++ else if (same_bool_result_p (t, partial)) ++ return t; ++ } ++ } ++ } ++ } ++ return NULL_TREE; ++} ++ ++/* Try to simplify the OR of two comparisons defined by ++ (OP1A CODE1 OP1B) and (OP2A CODE2 OP2B), respectively. ++ If this can be done without constructing an intermediate value, ++ return the resulting tree; otherwise NULL_TREE is returned. ++ This function is deliberately asymmetric as it recurses on SSA_DEFs ++ in the first comparison but not the second. */ ++ ++static tree ++or_comparisons_1 (enum tree_code code1, tree op1a, tree op1b, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ /* First check for ((x CODE1 y) OR (x CODE2 y)). */ ++ if (operand_equal_p (op1a, op2a, 0) ++ && operand_equal_p (op1b, op2b, 0)) ++ { ++ tree t = combine_comparisons (UNKNOWN_LOCATION, ++ TRUTH_ORIF_EXPR, code1, code2, ++ boolean_type_node, op1a, op1b); ++ if (t) ++ return t; ++ } ++ ++ /* Likewise the swapped case of the above. */ ++ if (operand_equal_p (op1a, op2b, 0) ++ && operand_equal_p (op1b, op2a, 0)) ++ { ++ tree t = combine_comparisons (UNKNOWN_LOCATION, ++ TRUTH_ORIF_EXPR, code1, ++ swap_tree_comparison (code2), ++ boolean_type_node, op1a, op1b); ++ if (t) ++ return t; ++ } ++ ++ /* If both comparisons are of the same value against constants, we might ++ be able to merge them. */ ++ if (operand_equal_p (op1a, op2a, 0) ++ && TREE_CODE (op1b) == INTEGER_CST ++ && TREE_CODE (op2b) == INTEGER_CST) ++ { ++ int cmp = tree_int_cst_compare (op1b, op2b); ++ ++ /* If we have (op1a != op1b), we should either be able to ++ return that or TRUE, depending on whether the constant op1b ++ also satisfies the other comparison against op2b. */ ++ if (code1 == NE_EXPR) ++ { ++ bool done = true; ++ bool val; ++ switch (code2) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp < 0); break; ++ case GT_EXPR: val = (cmp > 0); break; ++ case LE_EXPR: val = (cmp <= 0); break; ++ case GE_EXPR: val = (cmp >= 0); break; ++ default: done = false; ++ } ++ if (done) ++ { ++ if (val) ++ return boolean_true_node; ++ else ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ } ++ } ++ /* Likewise if the second comparison is a != comparison. */ ++ else if (code2 == NE_EXPR) ++ { ++ bool done = true; ++ bool val; ++ switch (code1) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp > 0); break; ++ case GT_EXPR: val = (cmp < 0); break; ++ case LE_EXPR: val = (cmp >= 0); break; ++ case GE_EXPR: val = (cmp <= 0); break; ++ default: done = false; ++ } ++ if (done) ++ { ++ if (val) ++ return boolean_true_node; ++ else ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ } ++ } ++ ++ /* See if an equality test is redundant with the other comparison. */ ++ else if (code1 == EQ_EXPR) ++ { ++ bool val; ++ switch (code2) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp < 0); break; ++ case GT_EXPR: val = (cmp > 0); break; ++ case LE_EXPR: val = (cmp <= 0); break; ++ case GE_EXPR: val = (cmp >= 0); break; ++ default: ++ val = false; ++ } ++ if (val) ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ } ++ else if (code2 == EQ_EXPR) ++ { ++ bool val; ++ switch (code1) ++ { ++ case EQ_EXPR: val = (cmp == 0); break; ++ case NE_EXPR: val = (cmp != 0); break; ++ case LT_EXPR: val = (cmp > 0); break; ++ case GT_EXPR: val = (cmp < 0); break; ++ case LE_EXPR: val = (cmp >= 0); break; ++ case GE_EXPR: val = (cmp <= 0); break; ++ default: ++ val = false; ++ } ++ if (val) ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ } ++ ++ /* Chose the less restrictive of two < or <= comparisons. */ ++ else if ((code1 == LT_EXPR || code1 == LE_EXPR) ++ && (code2 == LT_EXPR || code2 == LE_EXPR)) ++ { ++ if ((cmp < 0) || (cmp == 0 && code1 == LT_EXPR)) ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ else ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ } ++ ++ /* Likewise chose the less restrictive of two > or >= comparisons. */ ++ else if ((code1 == GT_EXPR || code1 == GE_EXPR) ++ && (code2 == GT_EXPR || code2 == GE_EXPR)) ++ { ++ if ((cmp > 0) || (cmp == 0 && code1 == GT_EXPR)) ++ return fold_build2 (code2, boolean_type_node, op2a, op2b); ++ else ++ return fold_build2 (code1, boolean_type_node, op1a, op1b); ++ } ++ ++ /* Check for singleton ranges. */ ++ else if (cmp == 0 ++ && ((code1 == LT_EXPR && code2 == GT_EXPR) ++ || (code1 == GT_EXPR && code2 == LT_EXPR))) ++ return fold_build2 (NE_EXPR, boolean_type_node, op1a, op2b); ++ ++ /* Check for less/greater pairs that don't restrict the range at all. */ ++ else if (cmp >= 0 ++ && (code1 == LT_EXPR || code1 == LE_EXPR) ++ && (code2 == GT_EXPR || code2 == GE_EXPR)) ++ return boolean_true_node; ++ else if (cmp <= 0 ++ && (code1 == GT_EXPR || code1 == GE_EXPR) ++ && (code2 == LT_EXPR || code2 == LE_EXPR)) ++ return boolean_true_node; ++ } ++ ++ /* Perhaps the first comparison is (NAME != 0) or (NAME == 1) where ++ NAME's definition is a truth value. See if there are any simplifications ++ that can be done against the NAME's definition. */ ++ if (TREE_CODE (op1a) == SSA_NAME ++ && (code1 == NE_EXPR || code1 == EQ_EXPR) ++ && (integer_zerop (op1b) || integer_onep (op1b))) ++ { ++ bool invert = ((code1 == EQ_EXPR && integer_zerop (op1b)) ++ || (code1 == NE_EXPR && integer_onep (op1b))); ++ gimple stmt = SSA_NAME_DEF_STMT (op1a); ++ switch (gimple_code (stmt)) ++ { ++ case GIMPLE_ASSIGN: ++ /* Try to simplify by copy-propagating the definition. */ ++ return or_var_with_comparison (op1a, invert, code2, op2a, op2b); ++ ++ case GIMPLE_PHI: ++ /* If every argument to the PHI produces the same result when ++ ORed with the second comparison, we win. ++ Do not do this unless the type is bool since we need a bool ++ result here anyway. */ ++ if (TREE_CODE (TREE_TYPE (op1a)) == BOOLEAN_TYPE) ++ { ++ tree result = NULL_TREE; ++ unsigned i; ++ for (i = 0; i < gimple_phi_num_args (stmt); i++) ++ { ++ tree arg = gimple_phi_arg_def (stmt, i); ++ ++ /* If this PHI has itself as an argument, ignore it. ++ If all the other args produce the same result, ++ we're still OK. */ ++ if (arg == gimple_phi_result (stmt)) ++ continue; ++ else if (TREE_CODE (arg) == INTEGER_CST) ++ { ++ if (invert ? integer_zerop (arg) : integer_nonzerop (arg)) ++ { ++ if (!result) ++ result = boolean_true_node; ++ else if (!integer_onep (result)) ++ return NULL_TREE; ++ } ++ else if (!result) ++ result = fold_build2 (code2, boolean_type_node, ++ op2a, op2b); ++ else if (!same_bool_comparison_p (result, ++ code2, op2a, op2b)) ++ return NULL_TREE; ++ } ++ else if (TREE_CODE (arg) == SSA_NAME) ++ { ++ tree temp = or_var_with_comparison (arg, invert, ++ code2, op2a, op2b); ++ if (!temp) ++ return NULL_TREE; ++ else if (!result) ++ result = temp; ++ else if (!same_bool_result_p (result, temp)) ++ return NULL_TREE; ++ } ++ else ++ return NULL_TREE; ++ } ++ return result; ++ } ++ ++ default: ++ break; ++ } ++ } ++ return NULL_TREE; ++} ++ ++/* Try to simplify the OR of two comparisons, specified by ++ (OP1A CODE1 OP1B) and (OP2B CODE2 OP2B), respectively. ++ If this can be simplified to a single expression (without requiring ++ introducing more SSA variables to hold intermediate values), ++ return the resulting tree. Otherwise return NULL_TREE. ++ If the result expression is non-null, it has boolean type. */ ++ ++tree ++maybe_fold_or_comparisons (enum tree_code code1, tree op1a, tree op1b, ++ enum tree_code code2, tree op2a, tree op2b) ++{ ++ tree t = or_comparisons_1 (code1, op1a, op1b, code2, op2a, op2b); ++ if (t) ++ return t; ++ else ++ return or_comparisons_1 (code2, op2a, op2b, code1, op1a, op1b); ++} ++ + /* Try to optimize out __builtin_stack_restore. Optimize it out + if there is another __builtin_stack_restore in the same basic + block and no calls or ASM_EXPRs are in between, or if this block's +@@ -3355,7 +4440,9 @@ + is replaced. If the call is expected to produces a result, then it + is replaced by an assignment of the new RHS to the result variable. + If the result is to be ignored, then the call is replaced by a +- GIMPLE_NOP. */ ++ GIMPLE_NOP. A proper VDEF chain is retained by making the first ++ VUSE and the last VDEF of the whole sequence be the same as the replaced ++ statement and using new SSA names for stores in between. */ + + static void + gimplify_and_update_call_from_tree (gimple_stmt_iterator *si_p, tree expr) +@@ -3366,17 +4453,36 @@ + gimple_stmt_iterator i; + gimple_seq stmts = gimple_seq_alloc(); + struct gimplify_ctx gctx; ++ gimple last = NULL; ++ gimple laststore = NULL; ++ tree reaching_vuse; + + stmt = gsi_stmt (*si_p); + + gcc_assert (is_gimple_call (stmt)); + + lhs = gimple_call_lhs (stmt); ++ reaching_vuse = gimple_vuse (stmt); + + push_gimplify_context (&gctx); + + if (lhs == NULL_TREE) +- gimplify_and_add (expr, &stmts); ++ { ++ gimplify_and_add (expr, &stmts); ++ /* We can end up with folding a memcpy of an empty class assignment ++ which gets optimized away by C++ gimplification. */ ++ if (gimple_seq_empty_p (stmts)) ++ { ++ pop_gimplify_context (NULL); ++ if (gimple_in_ssa_p (cfun)) ++ { ++ unlink_stmt_vdef (stmt); ++ release_defs (stmt); ++ } ++ gsi_remove (si_p, true); ++ return; ++ } ++ } + else + tmp = get_initialized_tmp_var (expr, &stmts, NULL); + +@@ -3387,26 +4493,95 @@ + + /* The replacement can expose previously unreferenced variables. */ + for (i = gsi_start (stmts); !gsi_end_p (i); gsi_next (&i)) +- { +- new_stmt = gsi_stmt (i); +- find_new_referenced_vars (new_stmt); +- gsi_insert_before (si_p, new_stmt, GSI_NEW_STMT); +- mark_symbols_for_renaming (new_stmt); +- gsi_next (si_p); +- } ++ { ++ if (last) ++ { ++ gsi_insert_before (si_p, last, GSI_NEW_STMT); ++ gsi_next (si_p); ++ } ++ new_stmt = gsi_stmt (i); ++ if (gimple_in_ssa_p (cfun)) ++ { ++ find_new_referenced_vars (new_stmt); ++ mark_symbols_for_renaming (new_stmt); ++ } ++ /* If the new statement has a VUSE, update it with exact SSA name we ++ know will reach this one. */ ++ if (gimple_vuse (new_stmt)) ++ { ++ /* If we've also seen a previous store create a new VDEF for ++ the latter one, and make that the new reaching VUSE. */ ++ if (laststore) ++ { ++ reaching_vuse = make_ssa_name (gimple_vop (cfun), laststore); ++ gimple_set_vdef (laststore, reaching_vuse); ++ update_stmt (laststore); ++ laststore = NULL; ++ } ++ gimple_set_vuse (new_stmt, reaching_vuse); ++ gimple_set_modified (new_stmt, true); ++ } ++ if (gimple_assign_single_p (new_stmt) ++ && !is_gimple_reg (gimple_assign_lhs (new_stmt))) ++ { ++ laststore = new_stmt; ++ } ++ last = new_stmt; ++ } + + if (lhs == NULL_TREE) + { +- new_stmt = gimple_build_nop (); +- unlink_stmt_vdef (stmt); +- release_defs (stmt); ++ /* If we replace a call without LHS that has a VDEF and our new ++ sequence ends with a store we must make that store have the same ++ vdef in order not to break the sequencing. This can happen ++ for instance when folding memcpy calls into assignments. */ ++ if (gimple_vdef (stmt) && laststore) ++ { ++ gimple_set_vdef (laststore, gimple_vdef (stmt)); ++ if (TREE_CODE (gimple_vdef (stmt)) == SSA_NAME) ++ SSA_NAME_DEF_STMT (gimple_vdef (stmt)) = laststore; ++ update_stmt (laststore); ++ } ++ else if (gimple_in_ssa_p (cfun)) ++ { ++ unlink_stmt_vdef (stmt); ++ release_defs (stmt); ++ } ++ new_stmt = last; + } + else + { ++ if (last) ++ { ++ gsi_insert_before (si_p, last, GSI_NEW_STMT); ++ gsi_next (si_p); ++ } ++ if (laststore && is_gimple_reg (lhs)) ++ { ++ gimple_set_vdef (laststore, gimple_vdef (stmt)); ++ update_stmt (laststore); ++ if (TREE_CODE (gimple_vdef (stmt)) == SSA_NAME) ++ SSA_NAME_DEF_STMT (gimple_vdef (stmt)) = laststore; ++ laststore = NULL; ++ } ++ else if (laststore) ++ { ++ reaching_vuse = make_ssa_name (gimple_vop (cfun), laststore); ++ gimple_set_vdef (laststore, reaching_vuse); ++ update_stmt (laststore); ++ laststore = NULL; ++ } + new_stmt = gimple_build_assign (lhs, tmp); +- gimple_set_vuse (new_stmt, gimple_vuse (stmt)); +- gimple_set_vdef (new_stmt, gimple_vdef (stmt)); +- move_ssa_defining_stmt_for_defs (new_stmt, stmt); ++ if (!is_gimple_reg (tmp)) ++ gimple_set_vuse (new_stmt, reaching_vuse); ++ if (!is_gimple_reg (lhs)) ++ { ++ gimple_set_vdef (new_stmt, gimple_vdef (stmt)); ++ if (TREE_CODE (gimple_vdef (stmt)) == SSA_NAME) ++ SSA_NAME_DEF_STMT (gimple_vdef (stmt)) = new_stmt; ++ } ++ else if (reaching_vuse == gimple_vuse (stmt)) ++ unlink_stmt_vdef (stmt); + } + + gimple_set_location (new_stmt, gimple_location (stmt)); +--- a/src/gcc/tree-ssa-copyrename.c ++++ b/src/gcc/tree-ssa-copyrename.c +@@ -225,11 +225,16 @@ + ign2 = false; + } + +- /* Don't coalesce if the two variables are not of the same type. */ +- if (TREE_TYPE (root1) != TREE_TYPE (root2)) ++ /* Don't coalesce if the two variables aren't type compatible . */ ++ if (!types_compatible_p (TREE_TYPE (root1), TREE_TYPE (root2)) ++ /* There is a disconnect between the middle-end type-system and ++ VRP, avoid coalescing enum types with different bounds. */ ++ || ((TREE_CODE (TREE_TYPE (root1)) == ENUMERAL_TYPE ++ || TREE_CODE (TREE_TYPE (root2)) == ENUMERAL_TYPE) ++ && TREE_TYPE (root1) != TREE_TYPE (root2))) + { + if (debug) +- fprintf (debug, " : Different types. No coalesce.\n"); ++ fprintf (debug, " : Incompatible types. No coalesce.\n"); + return false; + } + +--- a/src/gcc/tree-ssa-dom.c ++++ b/src/gcc/tree-ssa-dom.c +@@ -54,6 +54,7 @@ + EXPR_SINGLE, + EXPR_UNARY, + EXPR_BINARY, ++ EXPR_TERNARY, + EXPR_CALL + }; + +@@ -64,7 +65,8 @@ + union { + struct { tree rhs; } single; + struct { enum tree_code op; tree opnd; } unary; +- struct { enum tree_code op; tree opnd0; tree opnd1; } binary; ++ struct { enum tree_code op; tree opnd0, opnd1; } binary; ++ struct { enum tree_code op; tree opnd0, opnd1, opnd2; } ternary; + struct { tree fn; bool pure; size_t nargs; tree *args; } call; + } ops; + }; +@@ -214,22 +216,30 @@ + switch (get_gimple_rhs_class (subcode)) + { + case GIMPLE_SINGLE_RHS: +- expr->kind = EXPR_SINGLE; +- expr->ops.single.rhs = gimple_assign_rhs1 (stmt); +- break; ++ expr->kind = EXPR_SINGLE; ++ expr->ops.single.rhs = gimple_assign_rhs1 (stmt); ++ break; + case GIMPLE_UNARY_RHS: +- expr->kind = EXPR_UNARY; ++ expr->kind = EXPR_UNARY; + expr->type = TREE_TYPE (gimple_assign_lhs (stmt)); +- expr->ops.unary.op = subcode; +- expr->ops.unary.opnd = gimple_assign_rhs1 (stmt); +- break; ++ expr->ops.unary.op = subcode; ++ expr->ops.unary.opnd = gimple_assign_rhs1 (stmt); ++ break; + case GIMPLE_BINARY_RHS: +- expr->kind = EXPR_BINARY; ++ expr->kind = EXPR_BINARY; + expr->type = TREE_TYPE (gimple_assign_lhs (stmt)); +- expr->ops.binary.op = subcode; +- expr->ops.binary.opnd0 = gimple_assign_rhs1 (stmt); +- expr->ops.binary.opnd1 = gimple_assign_rhs2 (stmt); +- break; ++ expr->ops.binary.op = subcode; ++ expr->ops.binary.opnd0 = gimple_assign_rhs1 (stmt); ++ expr->ops.binary.opnd1 = gimple_assign_rhs2 (stmt); ++ break; ++ case GIMPLE_TERNARY_RHS: ++ expr->kind = EXPR_TERNARY; ++ expr->type = TREE_TYPE (gimple_assign_lhs (stmt)); ++ expr->ops.ternary.op = subcode; ++ expr->ops.ternary.opnd0 = gimple_assign_rhs1 (stmt); ++ expr->ops.ternary.opnd1 = gimple_assign_rhs2 (stmt); ++ expr->ops.ternary.opnd2 = gimple_assign_rhs3 (stmt); ++ break; + default: + gcc_unreachable (); + } +@@ -374,23 +384,40 @@ + expr1->ops.unary.opnd, 0); + + case EXPR_BINARY: +- { +- if (expr0->ops.binary.op != expr1->ops.binary.op) +- return false; ++ if (expr0->ops.binary.op != expr1->ops.binary.op) ++ return false; + +- if (operand_equal_p (expr0->ops.binary.opnd0, +- expr1->ops.binary.opnd0, 0) +- && operand_equal_p (expr0->ops.binary.opnd1, +- expr1->ops.binary.opnd1, 0)) +- return true; +- +- /* For commutative ops, allow the other order. */ +- return (commutative_tree_code (expr0->ops.binary.op) +- && operand_equal_p (expr0->ops.binary.opnd0, +- expr1->ops.binary.opnd1, 0) +- && operand_equal_p (expr0->ops.binary.opnd1, +- expr1->ops.binary.opnd0, 0)); +- } ++ if (operand_equal_p (expr0->ops.binary.opnd0, ++ expr1->ops.binary.opnd0, 0) ++ && operand_equal_p (expr0->ops.binary.opnd1, ++ expr1->ops.binary.opnd1, 0)) ++ return true; ++ ++ /* For commutative ops, allow the other order. */ ++ return (commutative_tree_code (expr0->ops.binary.op) ++ && operand_equal_p (expr0->ops.binary.opnd0, ++ expr1->ops.binary.opnd1, 0) ++ && operand_equal_p (expr0->ops.binary.opnd1, ++ expr1->ops.binary.opnd0, 0)); ++ ++ case EXPR_TERNARY: ++ if (expr0->ops.ternary.op != expr1->ops.ternary.op ++ || !operand_equal_p (expr0->ops.ternary.opnd2, ++ expr1->ops.ternary.opnd2, 0)) ++ return false; ++ ++ if (operand_equal_p (expr0->ops.ternary.opnd0, ++ expr1->ops.ternary.opnd0, 0) ++ && operand_equal_p (expr0->ops.ternary.opnd1, ++ expr1->ops.ternary.opnd1, 0)) ++ return true; ++ ++ /* For commutative ops, allow the other order. */ ++ return (commutative_ternary_tree_code (expr0->ops.ternary.op) ++ && operand_equal_p (expr0->ops.ternary.opnd0, ++ expr1->ops.ternary.opnd1, 0) ++ && operand_equal_p (expr0->ops.ternary.opnd1, ++ expr1->ops.ternary.opnd0, 0)); + + case EXPR_CALL: + { +@@ -453,8 +480,8 @@ + case EXPR_BINARY: + val = iterative_hash_object (expr->ops.binary.op, val); + if (commutative_tree_code (expr->ops.binary.op)) +- val = iterative_hash_exprs_commutative (expr->ops.binary.opnd0, +- expr->ops.binary.opnd1, val); ++ val = iterative_hash_exprs_commutative (expr->ops.binary.opnd0, ++ expr->ops.binary.opnd1, val); + else + { + val = iterative_hash_expr (expr->ops.binary.opnd0, val); +@@ -462,6 +489,19 @@ + } + break; + ++ case EXPR_TERNARY: ++ val = iterative_hash_object (expr->ops.ternary.op, val); ++ if (commutative_ternary_tree_code (expr->ops.ternary.op)) ++ val = iterative_hash_exprs_commutative (expr->ops.ternary.opnd0, ++ expr->ops.ternary.opnd1, val); ++ else ++ { ++ val = iterative_hash_expr (expr->ops.ternary.opnd0, val); ++ val = iterative_hash_expr (expr->ops.ternary.opnd1, val); ++ } ++ val = iterative_hash_expr (expr->ops.ternary.opnd2, val); ++ break; ++ + case EXPR_CALL: + { + size_t i; +@@ -514,6 +554,16 @@ + print_generic_expr (stream, element->expr.ops.binary.opnd1, 0); + break; + ++ case EXPR_TERNARY: ++ fprintf (stream, " %s <", tree_code_name[element->expr.ops.ternary.op]); ++ print_generic_expr (stream, element->expr.ops.ternary.opnd0, 0); ++ fputs (", ", stream); ++ print_generic_expr (stream, element->expr.ops.ternary.opnd1, 0); ++ fputs (", ", stream); ++ print_generic_expr (stream, element->expr.ops.ternary.opnd2, 0); ++ fputs (">", stream); ++ break; ++ + case EXPR_CALL: + { + size_t i; +--- a/src/gcc/tree-ssa-ifcombine.c ++++ b/src/gcc/tree-ssa-ifcombine.c +@@ -366,21 +366,16 @@ + + /* See if we have two comparisons that we can merge into one. */ + else if (TREE_CODE_CLASS (gimple_cond_code (inner_cond)) == tcc_comparison +- && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison +- && operand_equal_p (gimple_cond_lhs (inner_cond), +- gimple_cond_lhs (outer_cond), 0) +- && operand_equal_p (gimple_cond_rhs (inner_cond), +- gimple_cond_rhs (outer_cond), 0)) ++ && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison) + { +- enum tree_code code1 = gimple_cond_code (inner_cond); +- enum tree_code code2 = gimple_cond_code (outer_cond); + tree t; + +- if (!(t = combine_comparisons (UNKNOWN_LOCATION, +- TRUTH_ANDIF_EXPR, code1, code2, +- boolean_type_node, +- gimple_cond_lhs (outer_cond), +- gimple_cond_rhs (outer_cond)))) ++ if (!(t = maybe_fold_and_comparisons (gimple_cond_code (inner_cond), ++ gimple_cond_lhs (inner_cond), ++ gimple_cond_rhs (inner_cond), ++ gimple_cond_code (outer_cond), ++ gimple_cond_lhs (outer_cond), ++ gimple_cond_rhs (outer_cond)))) + return false; + t = canonicalize_cond_expr_cond (t); + if (!t) +@@ -518,22 +513,17 @@ + /* See if we have two comparisons that we can merge into one. + This happens for C++ operator overloading where for example + GE_EXPR is implemented as GT_EXPR || EQ_EXPR. */ +- else if (TREE_CODE_CLASS (gimple_cond_code (inner_cond)) == tcc_comparison +- && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison +- && operand_equal_p (gimple_cond_lhs (inner_cond), +- gimple_cond_lhs (outer_cond), 0) +- && operand_equal_p (gimple_cond_rhs (inner_cond), +- gimple_cond_rhs (outer_cond), 0)) ++ else if (TREE_CODE_CLASS (gimple_cond_code (inner_cond)) == tcc_comparison ++ && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison) + { +- enum tree_code code1 = gimple_cond_code (inner_cond); +- enum tree_code code2 = gimple_cond_code (outer_cond); + tree t; + +- if (!(t = combine_comparisons (UNKNOWN_LOCATION, +- TRUTH_ORIF_EXPR, code1, code2, +- boolean_type_node, +- gimple_cond_lhs (outer_cond), +- gimple_cond_rhs (outer_cond)))) ++ if (!(t = maybe_fold_or_comparisons (gimple_cond_code (inner_cond), ++ gimple_cond_lhs (inner_cond), ++ gimple_cond_rhs (inner_cond), ++ gimple_cond_code (outer_cond), ++ gimple_cond_lhs (outer_cond), ++ gimple_cond_rhs (outer_cond)))) + return false; + t = canonicalize_cond_expr_cond (t); + if (!t) +--- a/src/gcc/tree-ssa-loop-im.c ++++ b/src/gcc/tree-ssa-loop-im.c +@@ -2139,7 +2139,7 @@ + edge ex; + + for (i = 0; VEC_iterate (edge, exits, i, ex); i++) +- if (ex->flags & EDGE_ABNORMAL) ++ if (ex->flags & (EDGE_ABNORMAL | EDGE_EH)) + return false; + + return true; +--- a/src/gcc/tree-ssa-loop-ivopts.c ++++ b/src/gcc/tree-ssa-loop-ivopts.c +@@ -257,6 +257,9 @@ + + /* Are we optimizing for speed? */ + bool speed; ++ ++ /* Whether the loop body includes any function calls. */ ++ bool body_includes_call; + }; + + /* An assignment of iv candidates to uses. */ +@@ -2928,6 +2931,20 @@ + return get_computation_at (loop, use, cand, use->stmt); + } + ++/* Adjust the cost COST for being in loop setup rather than loop body. ++ If we're optimizing for space, the loop setup overhead is constant; ++ if we're optimizing for speed, amortize it over the per-iteration cost. */ ++static unsigned ++adjust_setup_cost (struct ivopts_data *data, unsigned cost) ++{ ++ if (cost == INFTY) ++ return cost; ++ else if (optimize_loop_for_speed_p (data->current_loop)) ++ return cost / AVG_LOOP_NITER (data->current_loop); ++ else ++ return cost; ++} ++ + /* Returns cost of addition in MODE. */ + + static unsigned +@@ -3840,8 +3857,8 @@ + /* Symbol + offset should be compile-time computable so consider that they + are added once to the variable, if present. */ + if (var_present && (symbol_present || offset)) +- cost.cost += add_cost (TYPE_MODE (ctype), speed) +- / AVG_LOOP_NITER (data->current_loop); ++ cost.cost += adjust_setup_cost (data, ++ add_cost (TYPE_MODE (ctype), speed)); + + /* Having offset does not affect runtime cost in case it is added to + symbol, but it increases complexity. */ +@@ -4107,7 +4124,7 @@ + elim_cost = force_var_cost (data, bound, &depends_on_elim); + /* The bound is a loop invariant, so it will be only computed + once. */ +- elim_cost.cost /= AVG_LOOP_NITER (data->current_loop); ++ elim_cost.cost = adjust_setup_cost (data, elim_cost.cost); + } + else + elim_cost = infinite_cost; +@@ -4354,7 +4371,7 @@ + cost_base = force_var_cost (data, base, NULL); + cost_step = add_cost (TYPE_MODE (TREE_TYPE (base)), data->speed); + +- cost = cost_step + cost_base.cost / AVG_LOOP_NITER (current_loop); ++ cost = cost_step + adjust_setup_cost (data, cost_base.cost); + + /* Prefer the original ivs unless we may gain something by replacing it. + The reason is to make debugging simpler; so this is not relevant for +@@ -4407,7 +4424,8 @@ + { + /* We add size to the cost, so that we prefer eliminating ivs + if possible. */ +- return size + estimate_reg_pressure_cost (size, data->regs_used, data->speed); ++ return size + estimate_reg_pressure_cost (size, data->regs_used, data->speed, ++ data->body_includes_call); + } + + /* For each size of the induction variable set determine the penalty. */ +@@ -4422,30 +4440,11 @@ + struct loop *loop = data->current_loop; + bitmap_iterator bi; + +- /* We use the following model (definitely improvable, especially the +- cost function -- TODO): +- +- We estimate the number of registers available (using MD data), name it A. +- +- We estimate the number of registers used by the loop, name it U. This +- number is obtained as the number of loop phi nodes (not counting virtual +- registers and bivs) + the number of variables from outside of the loop. +- +- We set a reserve R (free regs that are used for temporary computations, +- etc.). For now the reserve is a constant 3. +- +- Let I be the number of induction variables. +- +- -- if U + I + R <= A, the cost is I * SMALL_COST (just not to encourage +- make a lot of ivs without a reason). +- -- if A - R < U + I <= A, the cost is I * PRES_COST +- -- if U + I > A, the cost is I * PRES_COST and +- number of uses * SPILL_COST * (U + I - A) / (U + I) is added. */ +- + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Global costs:\n"); + fprintf (dump_file, " target_avail_regs %d\n", target_avail_regs); ++ fprintf (dump_file, " target_clobbered_regs %d\n", target_clobbered_regs); + fprintf (dump_file, " target_reg_cost %d\n", target_reg_cost[data->speed]); + fprintf (dump_file, " target_spill_cost %d\n", target_spill_cost[data->speed]); + } +@@ -5065,11 +5064,13 @@ + } + + /* Tries to extend the sets IVS in the best possible way in order +- to express the USE. */ ++ to express the USE. If ORIGINALP is true, prefer candidates from ++ the original set of IVs, otherwise favor important candidates not ++ based on any memory object. */ + + static bool + try_add_cand_for (struct ivopts_data *data, struct iv_ca *ivs, +- struct iv_use *use) ++ struct iv_use *use, bool originalp) + { + comp_cost best_cost, act_cost; + unsigned i; +@@ -5088,7 +5089,8 @@ + iv_ca_set_no_cp (data, ivs, use); + } + +- /* First try important candidates not based on any memory object. Only if ++ /* If ORIGINALP is true, try to find the original IV for the use. Otherwise ++ first try important candidates not based on any memory object. Only if + this fails, try the specific ones. Rationale -- in loops with many + variables the best choice often is to use just one generic biv. If we + added here many ivs specific to the uses, the optimization algorithm later +@@ -5100,7 +5102,10 @@ + { + cand = iv_cand (data, i); + +- if (cand->iv->base_object != NULL_TREE) ++ if (originalp && cand->pos !=IP_ORIGINAL) ++ continue; ++ ++ if (!originalp && cand->iv->base_object != NULL_TREE) + continue; + + if (iv_ca_cand_used_p (ivs, cand)) +@@ -5136,8 +5141,13 @@ + continue; + + /* Already tried this. */ +- if (cand->important && cand->iv->base_object == NULL_TREE) +- continue; ++ if (cand->important) ++ { ++ if (originalp && cand->pos == IP_ORIGINAL) ++ continue; ++ if (!originalp && cand->iv->base_object == NULL_TREE) ++ continue; ++ } + + if (iv_ca_cand_used_p (ivs, cand)) + continue; +@@ -5171,13 +5181,13 @@ + /* Finds an initial assignment of candidates to uses. */ + + static struct iv_ca * +-get_initial_solution (struct ivopts_data *data) ++get_initial_solution (struct ivopts_data *data, bool originalp) + { + struct iv_ca *ivs = iv_ca_new (data); + unsigned i; + + for (i = 0; i < n_iv_uses (data); i++) +- if (!try_add_cand_for (data, ivs, iv_use (data, i))) ++ if (!try_add_cand_for (data, ivs, iv_use (data, i), originalp)) + { + iv_ca_free (&ivs); + return NULL; +@@ -5249,14 +5259,12 @@ + solution and remove the unused ivs while this improves the cost. */ + + static struct iv_ca * +-find_optimal_iv_set (struct ivopts_data *data) ++find_optimal_iv_set_1 (struct ivopts_data *data, bool originalp) + { +- unsigned i; + struct iv_ca *set; +- struct iv_use *use; + + /* Get the initial solution. */ +- set = get_initial_solution (data); ++ set = get_initial_solution (data, originalp); + if (!set) + { + if (dump_file && (dump_flags & TDF_DETAILS)) +@@ -5279,11 +5287,46 @@ + } + } + ++ return set; ++} ++ ++static struct iv_ca * ++find_optimal_iv_set (struct ivopts_data *data) ++{ ++ unsigned i; ++ struct iv_ca *set, *origset; ++ struct iv_use *use; ++ comp_cost cost, origcost; ++ ++ /* Determine the cost based on a strategy that starts with original IVs, ++ and try again using a strategy that prefers candidates not based ++ on any IVs. */ ++ origset = find_optimal_iv_set_1 (data, true); ++ set = find_optimal_iv_set_1 (data, false); ++ ++ if (!origset && !set) ++ return NULL; ++ ++ origcost = origset ? iv_ca_cost (origset) : infinite_cost; ++ cost = set ? iv_ca_cost (set) : infinite_cost; ++ + if (dump_file && (dump_flags & TDF_DETAILS)) + { +- comp_cost cost = iv_ca_cost (set); +- fprintf (dump_file, "Final cost %d (complexity %d)\n\n", cost.cost, cost.complexity); ++ fprintf (dump_file, "Original cost %d (complexity %d)\n\n", ++ origcost.cost, origcost.complexity); ++ fprintf (dump_file, "Final cost %d (complexity %d)\n\n", ++ cost.cost, cost.complexity); ++ } ++ ++ /* Choose the one with the best cost. */ ++ if (compare_costs (origcost, cost) <= 0) ++ { ++ if (set) ++ iv_ca_free (&set); ++ set = origset; + } ++ else if (origset) ++ iv_ca_free (&origset); + + for (i = 0; i < n_iv_uses (data); i++) + { +@@ -5771,6 +5814,25 @@ + VEC_free (iv_cand_p, heap, data->iv_candidates); + } + ++/* Returns true if the loop body BODY includes any function calls. */ ++ ++static bool ++loop_body_includes_call (basic_block *body, unsigned num_nodes) ++{ ++ gimple_stmt_iterator gsi; ++ unsigned i; ++ ++ for (i = 0; i < num_nodes; i++) ++ for (gsi = gsi_start_bb (body[i]); !gsi_end_p (gsi); gsi_next (&gsi)) ++ { ++ gimple stmt = gsi_stmt (gsi); ++ if (is_gimple_call (stmt) ++ && !is_inexpensive_builtin (gimple_call_fndecl (stmt))) ++ return true; ++ } ++ return false; ++} ++ + /* Optimizes the LOOP. Returns true if anything changed. */ + + static bool +@@ -5802,6 +5864,7 @@ + } + + body = get_loop_body (loop); ++ data->body_includes_call = loop_body_includes_call (body, loop->num_nodes); + renumber_gimple_stmt_uids_in_blocks (body, loop->num_nodes); + free (body); + +--- a/src/gcc/tree-ssa-math-opts.c ++++ b/src/gcc/tree-ssa-math-opts.c +@@ -1269,3 +1269,291 @@ + 0 /* todo_flags_finish */ + } + }; ++ ++/* Return true if RHS is a suitable operand for a widening multiplication. ++ There are two cases: ++ ++ - RHS makes some value twice as wide. Store that value in *NEW_RHS_OUT ++ if so, and store its type in *TYPE_OUT. ++ ++ - RHS is an integer constant. Store that value in *NEW_RHS_OUT if so, ++ but leave *TYPE_OUT untouched. */ ++ ++static bool ++is_widening_mult_rhs_p (tree rhs, tree *type_out, tree *new_rhs_out) ++{ ++ gimple stmt; ++ tree type, type1, rhs1; ++ enum tree_code rhs_code; ++ ++ if (TREE_CODE (rhs) == SSA_NAME) ++ { ++ type = TREE_TYPE (rhs); ++ stmt = SSA_NAME_DEF_STMT (rhs); ++ if (!is_gimple_assign (stmt)) ++ return false; ++ ++ rhs_code = gimple_assign_rhs_code (stmt); ++ if (TREE_CODE (type) == INTEGER_TYPE ++ ? !CONVERT_EXPR_CODE_P (rhs_code) ++ : rhs_code != FIXED_CONVERT_EXPR) ++ return false; ++ ++ rhs1 = gimple_assign_rhs1 (stmt); ++ type1 = TREE_TYPE (rhs1); ++ if (TREE_CODE (type1) != TREE_CODE (type) ++ || TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type)) ++ return false; ++ ++ *new_rhs_out = rhs1; ++ *type_out = type1; ++ return true; ++ } ++ ++ if (TREE_CODE (rhs) == INTEGER_CST) ++ { ++ *new_rhs_out = rhs; ++ *type_out = NULL; ++ return true; ++ } ++ ++ return false; ++} ++ ++/* Return true if STMT performs a widening multiplication. If so, ++ store the unwidened types of the operands in *TYPE1_OUT and *TYPE2_OUT ++ respectively. Also fill *RHS1_OUT and *RHS2_OUT such that converting ++ those operands to types *TYPE1_OUT and *TYPE2_OUT would give the ++ operands of the multiplication. */ ++ ++static bool ++is_widening_mult_p (gimple stmt, ++ tree *type1_out, tree *rhs1_out, ++ tree *type2_out, tree *rhs2_out) ++{ ++ tree type; ++ ++ type = TREE_TYPE (gimple_assign_lhs (stmt)); ++ if (TREE_CODE (type) != INTEGER_TYPE ++ && TREE_CODE (type) != FIXED_POINT_TYPE) ++ return false; ++ ++ if (!is_widening_mult_rhs_p (gimple_assign_rhs1 (stmt), type1_out, rhs1_out)) ++ return false; ++ ++ if (!is_widening_mult_rhs_p (gimple_assign_rhs2 (stmt), type2_out, rhs2_out)) ++ return false; ++ ++ if (*type1_out == NULL) ++ { ++ if (*type2_out == NULL || !int_fits_type_p (*rhs1_out, *type2_out)) ++ return false; ++ *type1_out = *type2_out; ++ } ++ ++ if (*type2_out == NULL) ++ { ++ if (!int_fits_type_p (*rhs2_out, *type1_out)) ++ return false; ++ *type2_out = *type1_out; ++ } ++ ++ return true; ++} ++ ++/* Process a single gimple statement STMT, which has a MULT_EXPR as ++ its rhs, and try to convert it into a WIDEN_MULT_EXPR. The return ++ value is true iff we converted the statement. */ ++ ++static bool ++convert_mult_to_widen (gimple stmt) ++{ ++ tree lhs, rhs1, rhs2, type, type1, type2; ++ enum insn_code handler; ++ ++ lhs = gimple_assign_lhs (stmt); ++ type = TREE_TYPE (lhs); ++ if (TREE_CODE (type) != INTEGER_TYPE) ++ return false; ++ ++ if (!is_widening_mult_p (stmt, &type1, &rhs1, &type2, &rhs2)) ++ return false; ++ ++ if (TYPE_UNSIGNED (type1) && TYPE_UNSIGNED (type2)) ++ handler = optab_handler (umul_widen_optab, TYPE_MODE (type))->insn_code; ++ else if (!TYPE_UNSIGNED (type1) && !TYPE_UNSIGNED (type2)) ++ handler = optab_handler (smul_widen_optab, TYPE_MODE (type))->insn_code; ++ else ++ handler = optab_handler (usmul_widen_optab, TYPE_MODE (type))->insn_code; ++ ++ if (handler == CODE_FOR_nothing) ++ return false; ++ ++ gimple_assign_set_rhs1 (stmt, fold_convert (type1, rhs1)); ++ gimple_assign_set_rhs2 (stmt, fold_convert (type2, rhs2)); ++ gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR); ++ update_stmt (stmt); ++ return true; ++} ++ ++/* Process a single gimple statement STMT, which is found at the ++ iterator GSI and has a either a PLUS_EXPR or a MINUS_EXPR as its ++ rhs (given by CODE), and try to convert it into a ++ WIDEN_MULT_PLUS_EXPR or a WIDEN_MULT_MINUS_EXPR. The return value ++ is true iff we converted the statement. */ ++ ++static bool ++convert_plusminus_to_widen (gimple_stmt_iterator *gsi, gimple stmt, ++ enum tree_code code) ++{ ++ gimple rhs1_stmt = NULL, rhs2_stmt = NULL; ++ tree type, type1, type2; ++ tree lhs, rhs1, rhs2, mult_rhs1, mult_rhs2, add_rhs; ++ enum tree_code rhs1_code = ERROR_MARK, rhs2_code = ERROR_MARK; ++ optab this_optab; ++ enum tree_code wmult_code; ++ ++ lhs = gimple_assign_lhs (stmt); ++ type = TREE_TYPE (lhs); ++ if (TREE_CODE (type) != INTEGER_TYPE ++ && TREE_CODE (type) != FIXED_POINT_TYPE) ++ return false; ++ ++ if (code == MINUS_EXPR) ++ wmult_code = WIDEN_MULT_MINUS_EXPR; ++ else ++ wmult_code = WIDEN_MULT_PLUS_EXPR; ++ ++ rhs1 = gimple_assign_rhs1 (stmt); ++ rhs2 = gimple_assign_rhs2 (stmt); ++ ++ if (TREE_CODE (rhs1) == SSA_NAME) ++ { ++ rhs1_stmt = SSA_NAME_DEF_STMT (rhs1); ++ if (is_gimple_assign (rhs1_stmt)) ++ rhs1_code = gimple_assign_rhs_code (rhs1_stmt); ++ } ++ else ++ return false; ++ ++ if (TREE_CODE (rhs2) == SSA_NAME) ++ { ++ rhs2_stmt = SSA_NAME_DEF_STMT (rhs2); ++ if (is_gimple_assign (rhs2_stmt)) ++ rhs2_code = gimple_assign_rhs_code (rhs2_stmt); ++ } ++ else ++ return false; ++ ++ if (code == PLUS_EXPR && rhs1_code == MULT_EXPR) ++ { ++ if (!is_widening_mult_p (rhs1_stmt, &type1, &mult_rhs1, ++ &type2, &mult_rhs2)) ++ return false; ++ add_rhs = rhs2; ++ } ++ else if (rhs2_code == MULT_EXPR) ++ { ++ if (!is_widening_mult_p (rhs2_stmt, &type1, &mult_rhs1, ++ &type2, &mult_rhs2)) ++ return false; ++ add_rhs = rhs1; ++ } ++ else if (code == PLUS_EXPR && rhs1_code == WIDEN_MULT_EXPR) ++ { ++ mult_rhs1 = gimple_assign_rhs1 (rhs1_stmt); ++ mult_rhs2 = gimple_assign_rhs2 (rhs1_stmt); ++ type1 = TREE_TYPE (mult_rhs1); ++ type2 = TREE_TYPE (mult_rhs2); ++ add_rhs = rhs2; ++ } ++ else if (rhs2_code == WIDEN_MULT_EXPR) ++ { ++ mult_rhs1 = gimple_assign_rhs1 (rhs2_stmt); ++ mult_rhs2 = gimple_assign_rhs2 (rhs2_stmt); ++ type1 = TREE_TYPE (mult_rhs1); ++ type2 = TREE_TYPE (mult_rhs2); ++ add_rhs = rhs1; ++ } ++ else ++ return false; ++ ++ if (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2)) ++ return false; ++ ++ /* Verify that the machine can perform a widening multiply ++ accumulate in this mode/signedness combination, otherwise ++ this transformation is likely to pessimize code. */ ++ this_optab = optab_for_tree_code (wmult_code, type1, optab_default); ++ if (optab_handler (this_optab, TYPE_MODE (type))->insn_code ++ == CODE_FOR_nothing) ++ return false; ++ ++ /* ??? May need some type verification here? */ ++ ++ gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code, ++ fold_convert (type1, mult_rhs1), ++ fold_convert (type2, mult_rhs2), ++ add_rhs); ++ update_stmt (gsi_stmt (*gsi)); ++ return true; ++} ++ ++/* Find integer multiplications where the operands are extended from ++ smaller types, and replace the MULT_EXPR with a WIDEN_MULT_EXPR ++ where appropriate. */ ++ ++static unsigned int ++execute_optimize_widening_mul (void) ++{ ++ bool changed = false; ++ basic_block bb; ++ ++ FOR_EACH_BB (bb) ++ { ++ gimple_stmt_iterator gsi; ++ ++ for (gsi = gsi_after_labels (bb); !gsi_end_p (gsi); gsi_next (&gsi)) ++ { ++ gimple stmt = gsi_stmt (gsi); ++ enum tree_code code; ++ ++ if (!is_gimple_assign (stmt)) ++ continue; ++ ++ code = gimple_assign_rhs_code (stmt); ++ if (code == MULT_EXPR) ++ changed |= convert_mult_to_widen (stmt); ++ else if (code == PLUS_EXPR || code == MINUS_EXPR) ++ changed |= convert_plusminus_to_widen (&gsi, stmt, code); ++ } ++ } ++ ++ return (changed ? TODO_dump_func | TODO_update_ssa | TODO_verify_ssa ++ | TODO_verify_stmts : 0); ++} ++ ++static bool ++gate_optimize_widening_mul (void) ++{ ++ return flag_expensive_optimizations && optimize; ++} ++ ++struct gimple_opt_pass pass_optimize_widening_mul = ++{ ++ { ++ GIMPLE_PASS, ++ "widening_mul", /* name */ ++ gate_optimize_widening_mul, /* gate */ ++ execute_optimize_widening_mul, /* execute */ ++ NULL, /* sub */ ++ NULL, /* next */ ++ 0, /* static_pass_number */ ++ TV_NONE, /* tv_id */ ++ PROP_ssa, /* properties_required */ ++ 0, /* properties_provided */ ++ 0, /* properties_destroyed */ ++ 0, /* todo_flags_start */ ++ 0 /* todo_flags_finish */ ++ } ++}; +--- a/src/gcc/tree-ssa-operands.c ++++ b/src/gcc/tree-ssa-operands.c +@@ -994,11 +994,13 @@ + + case DOT_PROD_EXPR: + case REALIGN_LOAD_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: + { + get_expr_operands (stmt, &TREE_OPERAND (expr, 0), flags); +- get_expr_operands (stmt, &TREE_OPERAND (expr, 1), flags); +- get_expr_operands (stmt, &TREE_OPERAND (expr, 2), flags); +- return; ++ get_expr_operands (stmt, &TREE_OPERAND (expr, 1), flags); ++ get_expr_operands (stmt, &TREE_OPERAND (expr, 2), flags); ++ return; + } + + case FUNCTION_DECL: +--- a/src/gcc/tree-ssa-pre.c ++++ b/src/gcc/tree-ssa-pre.c +@@ -1701,7 +1701,7 @@ + tree result = vn_reference_lookup_pieces (newvuse, ref->set, + ref->type, + newoperands, +- &newref, true); ++ &newref, VN_WALK); + if (newref) + VEC_free (vn_reference_op_s, heap, newoperands); + +@@ -2558,6 +2558,10 @@ + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "Starting iteration %d\n", num_iterations); ++ /* ??? We need to clear our PHI translation cache here as the ++ ANTIC sets shrink and we restrict valid translations to ++ those having operands with leaders in ANTIC. Same below ++ for PA ANTIC computation. */ + num_iterations++; + changed = false; + for (i = n_basic_blocks - NUM_FIXED_BLOCKS - 1; i >= 0; i--) +@@ -3965,7 +3969,7 @@ + copy_reference_ops_from_call (stmt, &ops); + vn_reference_lookup_pieces (gimple_vuse (stmt), 0, + gimple_expr_type (stmt), +- ops, &ref, false); ++ ops, &ref, VN_NOWALK); + VEC_free (vn_reference_op_s, heap, ops); + if (!ref) + continue; +@@ -4035,7 +4039,7 @@ + + vn_reference_lookup (gimple_assign_rhs1 (stmt), + gimple_vuse (stmt), +- true, &ref); ++ VN_WALK, &ref); + if (!ref) + continue; + +@@ -4265,7 +4269,7 @@ + tree rhs = gimple_assign_rhs1 (stmt); + tree val; + val = vn_reference_lookup (gimple_assign_lhs (stmt), +- gimple_vuse (stmt), true, NULL); ++ gimple_vuse (stmt), VN_WALK, NULL); + if (TREE_CODE (rhs) == SSA_NAME) + rhs = VN_INFO (rhs)->valnum; + if (val +--- a/src/gcc/tree-ssa-reassoc.c ++++ b/src/gcc/tree-ssa-reassoc.c +@@ -1159,6 +1159,117 @@ + return changed; + } + ++/* If OPCODE is BIT_IOR_EXPR or BIT_AND_EXPR and CURR is a comparison ++ expression, examine the other OPS to see if any of them are comparisons ++ of the same values, which we may be able to combine or eliminate. ++ For example, we can rewrite (a < b) | (a == b) as (a <= b). */ ++ ++static bool ++eliminate_redundant_comparison (enum tree_code opcode, ++ VEC (operand_entry_t, heap) **ops, ++ unsigned int currindex, ++ operand_entry_t curr) ++{ ++ tree op1, op2; ++ enum tree_code lcode, rcode; ++ gimple def1, def2; ++ int i; ++ operand_entry_t oe; ++ ++ if (opcode != BIT_IOR_EXPR && opcode != BIT_AND_EXPR) ++ return false; ++ ++ /* Check that CURR is a comparison. */ ++ if (TREE_CODE (curr->op) != SSA_NAME) ++ return false; ++ def1 = SSA_NAME_DEF_STMT (curr->op); ++ if (!is_gimple_assign (def1)) ++ return false; ++ lcode = gimple_assign_rhs_code (def1); ++ if (TREE_CODE_CLASS (lcode) != tcc_comparison) ++ return false; ++ op1 = gimple_assign_rhs1 (def1); ++ op2 = gimple_assign_rhs2 (def1); ++ ++ /* Now look for a similar comparison in the remaining OPS. */ ++ for (i = currindex + 1; ++ VEC_iterate (operand_entry_t, *ops, i, oe); ++ i++) ++ { ++ tree t; ++ ++ if (TREE_CODE (oe->op) != SSA_NAME) ++ continue; ++ def2 = SSA_NAME_DEF_STMT (oe->op); ++ if (!is_gimple_assign (def2)) ++ continue; ++ rcode = gimple_assign_rhs_code (def2); ++ if (TREE_CODE_CLASS (rcode) != tcc_comparison) ++ continue; ++ ++ /* If we got here, we have a match. See if we can combine the ++ two comparisons. */ ++ if (opcode == BIT_IOR_EXPR) ++ t = maybe_fold_or_comparisons (lcode, op1, op2, ++ rcode, gimple_assign_rhs1 (def2), ++ gimple_assign_rhs2 (def2)); ++ else ++ t = maybe_fold_and_comparisons (lcode, op1, op2, ++ rcode, gimple_assign_rhs1 (def2), ++ gimple_assign_rhs2 (def2)); ++ if (!t) ++ continue; ++ ++ /* maybe_fold_and_comparisons and maybe_fold_or_comparisons ++ always give us a boolean_type_node value back. If the original ++ BIT_AND_EXPR or BIT_IOR_EXPR was of a wider integer type, ++ we need to convert. */ ++ if (!useless_type_conversion_p (TREE_TYPE (curr->op), TREE_TYPE (t))) ++ t = fold_convert (TREE_TYPE (curr->op), t); ++ ++ if (dump_file && (dump_flags & TDF_DETAILS)) ++ { ++ fprintf (dump_file, "Equivalence: "); ++ print_generic_expr (dump_file, curr->op, 0); ++ fprintf (dump_file, " %s ", op_symbol_code (opcode)); ++ print_generic_expr (dump_file, oe->op, 0); ++ fprintf (dump_file, " -> "); ++ print_generic_expr (dump_file, t, 0); ++ fprintf (dump_file, "\n"); ++ } ++ ++ /* Now we can delete oe, as it has been subsumed by the new combined ++ expression t. */ ++ VEC_ordered_remove (operand_entry_t, *ops, i); ++ reassociate_stats.ops_eliminated ++; ++ ++ /* If t is the same as curr->op, we're done. Otherwise we must ++ replace curr->op with t. Special case is if we got a constant ++ back, in which case we add it to the end instead of in place of ++ the current entry. */ ++ if (TREE_CODE (t) == INTEGER_CST) ++ { ++ VEC_ordered_remove (operand_entry_t, *ops, currindex); ++ add_to_ops_vec (ops, t); ++ } ++ else if (!operand_equal_p (t, curr->op, 0)) ++ { ++ tree tmpvar; ++ gimple sum; ++ enum tree_code subcode; ++ tree newop1; ++ tree newop2; ++ tmpvar = create_tmp_var (TREE_TYPE (t), NULL); ++ add_referenced_var (tmpvar); ++ extract_ops_from_tree (t, &subcode, &newop1, &newop2); ++ sum = build_and_add_sum (tmpvar, newop1, newop2, subcode); ++ curr->op = gimple_get_lhs (sum); ++ } ++ return true; ++ } ++ ++ return false; ++} + + /* Perform various identities and other optimizations on the list of + operand entries, stored in OPS. The tree code for the binary +@@ -1220,7 +1331,8 @@ + if (eliminate_not_pairs (opcode, ops, i, oe)) + return; + if (eliminate_duplicate_pair (opcode, ops, &done, i, oe, oelast) +- || (!done && eliminate_plus_minus_pair (opcode, ops, i, oe))) ++ || (!done && eliminate_plus_minus_pair (opcode, ops, i, oe)) ++ || (!done && eliminate_redundant_comparison (opcode, ops, i, oe))) + { + if (done) + return; +--- a/src/gcc/tree-ssa-sccvn.c ++++ b/src/gcc/tree-ssa-sccvn.c +@@ -988,6 +988,7 @@ + } + + static tree *last_vuse_ptr; ++static vn_lookup_kind vn_walk_kind; + + /* Callback for walk_non_aliased_vuses. Adjusts the vn_reference_t VR_ + with the current VUSE and performs the expression lookup. */ +@@ -1063,6 +1064,7 @@ + size2 = TREE_INT_CST_LOW (gimple_call_arg (def_stmt, 2)) * 8; + if ((unsigned HOST_WIDE_INT)size2 / 8 + == TREE_INT_CST_LOW (gimple_call_arg (def_stmt, 2)) ++ && maxsize2 != -1 + && operand_equal_p (base, base2, 0) + && offset2 <= offset + && offset2 + size2 >= offset + maxsize) +@@ -1086,7 +1088,8 @@ + HOST_WIDE_INT offset2, size2, maxsize2; + base2 = get_ref_base_and_extent (gimple_assign_lhs (def_stmt), + &offset2, &size2, &maxsize2); +- if (operand_equal_p (base, base2, 0) ++ if (maxsize2 != -1 ++ && operand_equal_p (base, base2, 0) + && offset2 <= offset + && offset2 + size2 >= offset + maxsize) + { +@@ -1101,7 +1104,8 @@ + + /* For aggregate copies translate the reference through them if + the copy kills ref. */ +- else if (gimple_assign_single_p (def_stmt) ++ else if (vn_walk_kind == VN_WALKREWRITE ++ && gimple_assign_single_p (def_stmt) + && (DECL_P (gimple_assign_rhs1 (def_stmt)) + || INDIRECT_REF_P (gimple_assign_rhs1 (def_stmt)) + || handled_component_p (gimple_assign_rhs1 (def_stmt)))) +@@ -1116,7 +1120,8 @@ + /* See if the assignment kills REF. */ + base2 = get_ref_base_and_extent (gimple_assign_lhs (def_stmt), + &offset2, &size2, &maxsize2); +- if (!operand_equal_p (base, base2, 0) ++ if (maxsize2 == -1 ++ || !operand_equal_p (base, base2, 0) + || offset2 > offset + || offset2 + size2 < offset + maxsize) + return (void *)-1; +@@ -1190,7 +1195,7 @@ + tree + vn_reference_lookup_pieces (tree vuse, alias_set_type set, tree type, + VEC (vn_reference_op_s, heap) *operands, +- vn_reference_t *vnresult, bool maywalk) ++ vn_reference_t *vnresult, vn_lookup_kind kind) + { + struct vn_reference_s vr1; + vn_reference_t tmp; +@@ -1215,10 +1220,11 @@ + vn_reference_lookup_1 (&vr1, vnresult); + + if (!*vnresult +- && maywalk ++ && kind != VN_NOWALK + && vr1.vuse) + { + ao_ref r; ++ vn_walk_kind = kind; + if (ao_ref_init_from_vn_reference (&r, set, type, vr1.operands)) + *vnresult = + (vn_reference_t)walk_non_aliased_vuses (&r, vr1.vuse, +@@ -1241,7 +1247,7 @@ + stored in the hashtable if one exists. */ + + tree +-vn_reference_lookup (tree op, tree vuse, bool maywalk, ++vn_reference_lookup (tree op, tree vuse, vn_lookup_kind kind, + vn_reference_t *vnresult) + { + VEC (vn_reference_op_s, heap) *operands; +@@ -1256,12 +1262,13 @@ + vr1.set = get_alias_set (op); + vr1.hashcode = vn_reference_compute_hash (&vr1); + +- if (maywalk ++ if (kind != VN_NOWALK + && vr1.vuse) + { + vn_reference_t wvnresult; + ao_ref r; + ao_ref_init (&r, op); ++ vn_walk_kind = kind; + wvnresult = + (vn_reference_t)walk_non_aliased_vuses (&r, vr1.vuse, + vn_reference_lookup_2, +@@ -1980,14 +1987,14 @@ + + last_vuse = gimple_vuse (stmt); + last_vuse_ptr = &last_vuse; +- result = vn_reference_lookup (op, gimple_vuse (stmt), true, NULL); ++ result = vn_reference_lookup (op, gimple_vuse (stmt), VN_WALKREWRITE, NULL); + last_vuse_ptr = NULL; + + /* If we have a VCE, try looking up its operand as it might be stored in + a different type. */ + if (!result && TREE_CODE (op) == VIEW_CONVERT_EXPR) + result = vn_reference_lookup (TREE_OPERAND (op, 0), gimple_vuse (stmt), +- true, NULL); ++ VN_WALKREWRITE, NULL); + + /* We handle type-punning through unions by value-numbering based + on offset and size of the access. Be prepared to handle a +@@ -2098,7 +2105,7 @@ + Otherwise, the vdefs for the store are used when inserting into + the table, since the store generates a new memory state. */ + +- result = vn_reference_lookup (lhs, gimple_vuse (stmt), false, NULL); ++ result = vn_reference_lookup (lhs, gimple_vuse (stmt), VN_NOWALK, NULL); + + if (result) + { +@@ -2277,6 +2284,10 @@ + case GIMPLE_BINARY_RHS: + return (is_gimple_min_invariant (gimple_assign_rhs1 (stmt)) + || is_gimple_min_invariant (gimple_assign_rhs2 (stmt))); ++ case GIMPLE_TERNARY_RHS: ++ return (is_gimple_min_invariant (gimple_assign_rhs1 (stmt)) ++ || is_gimple_min_invariant (gimple_assign_rhs2 (stmt)) ++ || is_gimple_min_invariant (gimple_assign_rhs3 (stmt))); + case GIMPLE_SINGLE_RHS: + /* Constants inside reference ops are rarely interesting, but + it can take a lot of looking to find them. */ +--- a/src/gcc/tree-ssa-sccvn.h ++++ b/src/gcc/tree-ssa-sccvn.h +@@ -185,10 +185,11 @@ + void copy_reference_ops_from_call (gimple, VEC(vn_reference_op_s, heap) **); + bool ao_ref_init_from_vn_reference (ao_ref *, alias_set_type, tree, + VEC (vn_reference_op_s, heap) *); ++typedef enum { VN_NOWALK, VN_WALK, VN_WALKREWRITE } vn_lookup_kind; + tree vn_reference_lookup_pieces (tree, alias_set_type, tree, + VEC (vn_reference_op_s, heap) *, +- vn_reference_t *, bool); +-tree vn_reference_lookup (tree, tree, bool, vn_reference_t *); ++ vn_reference_t *, vn_lookup_kind); ++tree vn_reference_lookup (tree, tree, vn_lookup_kind, vn_reference_t *); + vn_reference_t vn_reference_insert (tree, tree, tree); + vn_reference_t vn_reference_insert_pieces (tree, alias_set_type, tree, + VEC (vn_reference_op_s, heap) *, +--- a/src/gcc/tree-ssa-sink.c ++++ b/src/gcc/tree-ssa-sink.c +@@ -470,6 +470,47 @@ + last = false; + continue; + } ++ ++ /* We cannot move statements that contain references to block-scope ++ variables out of that block, as this may lead to incorrect aliasing ++ when we lay out the stack frame in cfgexpand.c. ++ In lieu of more sophisticated analysis, be very conservative here ++ and prohibit moving any statement that references memory out of a ++ block with variables. */ ++ if (gimple_references_memory_p (stmt)) ++ { ++ tree fromblock = gimple_block (stmt); ++ while (fromblock ++ && fromblock != current_function_decl ++ && !BLOCK_VARS (fromblock)) ++ fromblock = BLOCK_SUPERCONTEXT (fromblock); ++ if (fromblock && fromblock != current_function_decl) ++ { ++ gimple tostmt; ++ tree toblock; ++ ++ if (gsi_end_p (togsi)) ++ tostmt = gimple_seq_last_stmt (gsi_seq (togsi)); ++ else ++ tostmt = gsi_stmt (togsi); ++ if (tostmt) ++ toblock = gimple_block (tostmt); ++ else ++ toblock = NULL; ++ while (toblock ++ && toblock != current_function_decl ++ && toblock != fromblock) ++ toblock = BLOCK_SUPERCONTEXT (toblock); ++ if (!toblock || toblock != fromblock) ++ { ++ if (!gsi_end_p (gsi)) ++ gsi_prev (&gsi); ++ last = false; ++ continue; ++ } ++ } ++ } ++ + if (dump_file) + { + fprintf (dump_file, "Sinking "); +--- a/src/gcc/tree-ssa-structalias.c ++++ b/src/gcc/tree-ssa-structalias.c +@@ -369,7 +369,11 @@ + ret->may_have_pointers = true; + ret->is_global_var = (t == NULL_TREE); + if (t && DECL_P (t)) +- ret->is_global_var = is_global_var (t); ++ ret->is_global_var = (is_global_var (t) ++ /* We have to treat even local register variables ++ as escape points. */ ++ || (TREE_CODE (t) == VAR_DECL ++ && DECL_HARD_REGISTER (t))); + ret->solution = BITMAP_ALLOC (&pta_obstack); + ret->oldsolution = BITMAP_ALLOC (&oldpta_obstack); + ret->next = NULL; +@@ -4305,6 +4309,17 @@ + if (!VEC_empty (fieldoff_s, *fieldstack)) + pair = VEC_last (fieldoff_s, *fieldstack); + ++ if (!pair ++ && offset + foff != 0) ++ { ++ pair = VEC_safe_push (fieldoff_s, heap, *fieldstack, NULL); ++ pair->offset = 0; ++ pair->size = offset + foff; ++ pair->has_unknown_size = false; ++ pair->may_have_pointers = false; ++ pair->only_restrict_pointers = false; ++ } ++ + if (!DECL_SIZE (field) + || !host_integerp (DECL_SIZE (field), 1)) + has_unknown_size = true; +--- a/src/gcc/tree-ssa-ter.c ++++ b/src/gcc/tree-ssa-ter.c +@@ -416,7 +416,9 @@ + return false; + + /* Without alias info we can't move around loads. */ +- if (gimple_references_memory_p (stmt) && !optimize) ++ if (!optimize ++ && gimple_assign_single_p (stmt) ++ && !is_gimple_val (gimple_assign_rhs1 (stmt))) + return false; + + /* Float expressions must go through memory if float-store is on. */ +--- a/src/gcc/tree-ssa-threadedge.c ++++ b/src/gcc/tree-ssa-threadedge.c +@@ -247,14 +247,14 @@ + + return fold (rhs); + } +- break; ++ + case GIMPLE_UNARY_RHS: + { + tree lhs = gimple_assign_lhs (stmt); + tree op0 = gimple_assign_rhs1 (stmt); + return fold_unary (subcode, TREE_TYPE (lhs), op0); + } +- break; ++ + case GIMPLE_BINARY_RHS: + { + tree lhs = gimple_assign_lhs (stmt); +@@ -262,7 +262,16 @@ + tree op1 = gimple_assign_rhs2 (stmt); + return fold_binary (subcode, TREE_TYPE (lhs), op0, op1); + } +- break; ++ ++ case GIMPLE_TERNARY_RHS: ++ { ++ tree lhs = gimple_assign_lhs (stmt); ++ tree op0 = gimple_assign_rhs1 (stmt); ++ tree op1 = gimple_assign_rhs2 (stmt); ++ tree op2 = gimple_assign_rhs3 (stmt); ++ return fold_ternary (subcode, TREE_TYPE (lhs), op0, op1, op2); ++ } ++ + default: + gcc_unreachable (); + } +--- a/src/gcc/tree-ssa.c ++++ b/src/gcc/tree-ssa.c +@@ -1671,6 +1671,8 @@ + { + TREE_NO_WARNING (var) = 1; + ++ if (location == DECL_SOURCE_LOCATION (var)) ++ return; + if (xloc.file != floc.file + || xloc.line < floc.line + || xloc.line > LOCATION_LINE (cfun->function_end_locus)) +--- a/src/gcc/tree-vect-stmts.c ++++ b/src/gcc/tree-vect-stmts.c +@@ -4867,6 +4867,11 @@ + tree wide_vectype = get_vectype_for_scalar_type (type); + enum tree_code c1, c2; + ++ /* Check we have a valid vector type for the result. */ ++ if (!wide_vectype) ++ return false; ++ ++ + /* The result of a vectorized widening operation usually requires two vectors + (because the widened results do not fit int one vector). The generated + vector results would normally be expected to be generated in the same +--- a/src/gcc/tree-vrp.c ++++ b/src/gcc/tree-vrp.c +@@ -864,6 +864,8 @@ + gimple_assign_rhs1 (stmt), + gimple_assign_rhs2 (stmt), + strict_overflow_p); ++ case GIMPLE_TERNARY_RHS: ++ return false; + case GIMPLE_SINGLE_RHS: + return tree_single_nonnegative_warnv_p (gimple_assign_rhs1 (stmt), + strict_overflow_p); +@@ -935,6 +937,8 @@ + gimple_assign_rhs1 (stmt), + gimple_assign_rhs2 (stmt), + strict_overflow_p); ++ case GIMPLE_TERNARY_RHS: ++ return false; + case GIMPLE_SINGLE_RHS: + return tree_single_nonzero_warnv_p (gimple_assign_rhs1 (stmt), + strict_overflow_p); +@@ -7290,6 +7294,7 @@ + size_t i; + prop_value_t *single_val_range; + bool do_value_subst_p; ++ unsigned num = num_ssa_names; + + if (dump_file) + { +@@ -7301,10 +7306,10 @@ + /* We may have ended with ranges that have exactly one value. Those + values can be substituted as any other const propagated + value using substitute_and_fold. */ +- single_val_range = XCNEWVEC (prop_value_t, num_ssa_names); ++ single_val_range = XCNEWVEC (prop_value_t, num); + + do_value_subst_p = false; +- for (i = 0; i < num_ssa_names; i++) ++ for (i = 0; i < num; i++) + if (vr_value[i] + && vr_value[i]->type == VR_RANGE + && vr_value[i]->min == vr_value[i]->max +@@ -7332,7 +7337,7 @@ + identify_jump_threads (); + + /* Free allocated memory. */ +- for (i = 0; i < num_ssa_names; i++) ++ for (i = 0; i < num; i++) + if (vr_value[i]) + { + BITMAP_FREE (vr_value[i]->equiv); +--- a/src/gcc/tree.c ++++ b/src/gcc/tree.c +@@ -6538,6 +6538,23 @@ + return false; + } + ++/* Return true if CODE represents a ternary tree code for which the ++ first two operands are commutative. Otherwise return false. */ ++bool ++commutative_ternary_tree_code (enum tree_code code) ++{ ++ switch (code) ++ { ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ return true; ++ ++ default: ++ break; ++ } ++ return false; ++} ++ + /* Generate a hash value for an expression. This can be used iteratively + by passing a previous result as the VAL argument. + +@@ -9358,6 +9375,19 @@ + return true; + } + ++ case STRING_CST: ++ { ++ int i; ++ ++ /* We need to loop through all elements to handle cases like ++ "\0" and "\0foobar". */ ++ for (i = 0; i < TREE_STRING_LENGTH (init); ++i) ++ if (TREE_STRING_POINTER (init)[i] != '\0') ++ return false; ++ ++ return true; ++ } ++ + default: + return false; + } +--- a/src/gcc/tree.def ++++ b/src/gcc/tree.def +@@ -1083,6 +1083,18 @@ + the arguments from type t1 to type t2, and then multiplying them. */ + DEFTREECODE (WIDEN_MULT_EXPR, "widen_mult_expr", tcc_binary, 2) + ++/* Widening multiply-accumulate. ++ The first two arguments are of type t1. ++ The third argument and the result are of type t2, such as t2 is at least ++ twice the size of t1. t1 and t2 must be integral or fixed-point types. ++ The expression is equivalent to a WIDEN_MULT_EXPR operation ++ of the first two operands followed by an add or subtract of the third ++ operand. */ ++DEFTREECODE (WIDEN_MULT_PLUS_EXPR, "widen_mult_plus_expr", tcc_expression, 3) ++/* This is like the above, except in the final expression the multiply result ++ is subtracted from t3. */ ++DEFTREECODE (WIDEN_MULT_MINUS_EXPR, "widen_mult_plus_expr", tcc_expression, 3) ++ + /* Whole vector left/right shift in bits. + Operand 0 is a vector to be shifted. + Operand 1 is an integer shift amount in bits. */ +--- a/src/gcc/tree.h ++++ b/src/gcc/tree.h +@@ -4707,6 +4707,7 @@ + extern int type_num_arguments (const_tree); + extern bool associative_tree_code (enum tree_code); + extern bool commutative_tree_code (enum tree_code); ++extern bool commutative_ternary_tree_code (enum tree_code); + extern tree upper_bound_in_type (tree, tree); + extern tree lower_bound_in_type (tree, tree); + extern int operand_equal_for_phi_arg_p (const_tree, const_tree); +@@ -4963,6 +4964,8 @@ + extern bool merge_ranges (int *, tree *, tree *, int, tree, tree, int, + tree, tree); + extern void set_builtin_user_assembler_name (tree decl, const char *asmspec); ++extern bool is_simple_builtin (tree); ++extern bool is_inexpensive_builtin (tree); + + /* In convert.c */ + extern tree strip_float_extensions (tree); +--- a/src/gcc/unwind-dw2.c ++++ b/src/gcc/unwind-dw2.c +@@ -1414,16 +1414,12 @@ + /* Fill in CONTEXT for top-of-stack. The only valid registers at this + level will be the return address and the CFA. */ + +-#define uw_init_context(CONTEXT) \ +- do \ +- { \ +- /* Do any necessary initialization to access arbitrary stack frames. \ +- On the SPARC, this means flushing the register windows. */ \ +- __builtin_unwind_init (); \ +- uw_init_context_1 (CONTEXT, __builtin_dwarf_cfa (), \ +- __builtin_return_address (0)); \ +- } \ +- while (0) ++#define uw_init_context(CONTEXT) \ ++ /* Do any necessary initialization to access arbitrary stack frames. \ ++ On the SPARC, this means flushing the register windows. */ \ ++ (__builtin_unwind_init (), \ ++ uw_init_context_1 ((CONTEXT), __builtin_dwarf_cfa (), \ ++ __builtin_return_address (0))) + + static inline void + init_dwarf_reg_size_table (void) +@@ -1431,7 +1427,7 @@ + __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table); + } + +-static void __attribute__((noinline)) ++static _Unwind_Reason_Code __attribute__((noinline)) + uw_init_context_1 (struct _Unwind_Context *context, + void *outer_cfa, void *outer_ra) + { +@@ -1445,7 +1441,8 @@ + context->flags = EXTENDED_CONTEXT_BIT; + + code = uw_frame_state_for (context, &fs); +- gcc_assert (code == _URC_NO_REASON); ++ if (code != _URC_NO_REASON) ++ return code; + + #if __GTHREADS + { +@@ -1471,6 +1468,8 @@ + initialization context, then we can't see it in the given + call frame data. So have the initialization context tell us. */ + context->ra = __builtin_extract_return_addr (outer_ra); ++ ++ return _URC_NO_REASON; + } + + static void _Unwind_DebugHook (void *, void *) +--- a/src/gcc/unwind-sjlj.c ++++ b/src/gcc/unwind-sjlj.c +@@ -292,10 +292,11 @@ + uw_update_context (context, fs); + } + +-static inline void ++static inline _Unwind_Reason_Code + uw_init_context (struct _Unwind_Context *context) + { + context->fc = _Unwind_SjLj_GetContext (); ++ return _URC_NO_REASON; + } + + static void __attribute__((noreturn)) +--- a/src/gcc/unwind.inc ++++ b/src/gcc/unwind.inc +@@ -85,7 +85,8 @@ + _Unwind_Reason_Code code; + + /* Set up this_context to describe the current stack frame. */ +- uw_init_context (&this_context); ++ code = uw_init_context (&this_context); ++ gcc_assert (code == _URC_NO_REASON); + cur_context = this_context; + + /* Phase 1: Search. Unwind the stack, calling the personality routine +@@ -198,7 +199,8 @@ + struct _Unwind_Context this_context, cur_context; + _Unwind_Reason_Code code; + +- uw_init_context (&this_context); ++ code = uw_init_context (&this_context); ++ gcc_assert (code == _URC_NO_REASON); + cur_context = this_context; + + exc->private_1 = (_Unwind_Ptr) stop; +@@ -221,7 +223,8 @@ + struct _Unwind_Context this_context, cur_context; + _Unwind_Reason_Code code; + +- uw_init_context (&this_context); ++ code = uw_init_context (&this_context); ++ gcc_assert (code == _URC_NO_REASON); + cur_context = this_context; + + /* Choose between continuing to process _Unwind_RaiseException +@@ -251,7 +254,8 @@ + if (exc->private_1 == 0) + return _Unwind_RaiseException (exc); + +- uw_init_context (&this_context); ++ code = uw_init_context (&this_context); ++ gcc_assert (code == _URC_NO_REASON); + cur_context = this_context; + + code = _Unwind_ForcedUnwind_Phase2 (exc, &cur_context); +@@ -280,7 +284,9 @@ + struct _Unwind_Context context; + _Unwind_Reason_Code code; + +- uw_init_context (&context); ++ code = uw_init_context (&context); ++ if (code != _URC_NO_REASON) ++ return _URC_FATAL_PHASE1_ERROR; + + while (1) + { +--- a/src/gcc/varasm.c ++++ b/src/gcc/varasm.c +@@ -1043,8 +1043,11 @@ + Prefixes such as % are optional. */ + + int +-decode_reg_name (const char *asmspec) ++decode_reg_name_and_count (const char *asmspec, int *pnregs) + { ++ /* Presume just one register is clobbered. */ ++ *pnregs = 1; ++ + if (asmspec != 0) + { + int i; +@@ -1070,6 +1073,25 @@ + && ! strcmp (asmspec, strip_reg_name (reg_names[i]))) + return i; + ++#ifdef OVERLAPPING_REGISTER_NAMES ++ { ++ static const struct ++ { ++ const char *const name; ++ const int number; ++ const int nregs; ++ } table[] = OVERLAPPING_REGISTER_NAMES; ++ ++ for (i = 0; i < (int) ARRAY_SIZE (table); i++) ++ if (table[i].name[0] ++ && ! strcmp (asmspec, table[i].name)) ++ { ++ *pnregs = table[i].nregs; ++ return table[i].number; ++ } ++ } ++#endif /* OVERLAPPING_REGISTER_NAMES */ ++ + #ifdef ADDITIONAL_REGISTER_NAMES + { + static const struct { const char *const name; const int number; } table[] +@@ -1093,6 +1115,14 @@ + + return -1; + } ++ ++int ++decode_reg_name (const char *name) ++{ ++ int count; ++ return decode_reg_name_and_count (name, &count); ++} ++ + + /* Return true if DECL's initializer is suitable for a BSS section. */ + +--- a/src/gcc/vec.h ++++ b/src/gcc/vec.h +@@ -188,6 +188,18 @@ + + #define VEC_iterate(T,V,I,P) (VEC_OP(T,base,iterate)(VEC_BASE(V),I,&(P))) + ++/* Convenience macro for forward iteration. */ ++ ++#define FOR_EACH_VEC_ELT(T, V, I, P) \ ++ for (I = 0; VEC_iterate (T, (V), (I), (P)); ++(I)) ++ ++/* Convenience macro for reverse iteration. */ ++ ++#define FOR_EACH_VEC_ELT_REVERSE(T,V,I,P) \ ++ for (I = VEC_length (T, (V)) - 1; \ ++ VEC_iterate (T, (V), (I), (P)); \ ++ (I)--) ++ + /* Allocate new vector. + VEC(T,A) *VEC_T_A_alloc(int reserve); + +--- a/src/gcc/xcoffout.c ++++ b/src/gcc/xcoffout.c +@@ -81,8 +81,15 @@ + #define ASM_OUTPUT_LINE(FILE,LINENUM) \ + do \ + { \ ++ /* Make sure we're in a function and prevent output of .line 0, as \ ++ line # 0 is meant for symbol addresses in xcoff. Additionally, \ ++ line numbers are 'unsigned short' in 32-bit mode. */ \ + if (xcoff_begin_function_line >= 0) \ +- fprintf (FILE, "\t.line\t%d\n", ABS_OR_RELATIVE_LINENO (LINENUM)); \ ++ { \ ++ int lno = ABS_OR_RELATIVE_LINENO (LINENUM); \ ++ if (lno > 0 && (TARGET_64BIT || lno <= (int)USHRT_MAX)) \ ++ fprintf (FILE, "\t.line\t%d\n", lno); \ ++ } \ + } \ + while (0) + +--- a/src/libcpp/ChangeLog ++++ b/src/libcpp/ChangeLog +@@ -1,3 +1,10 @@ ++2011-11-04 Eric Botcazou ++ Jakub Jelinek ++ ++ PR preprocessor/39213 ++ * directives.c (end_directive): Call _cpp_remove_overlay for deferred ++ pragmas as well in traditional mode. ++ + 2010-12-16 Release Manager + + * GCC 4.5.2 released. +--- a/src/libcpp/directives.c ++++ b/src/libcpp/directives.c +@@ -280,16 +280,17 @@ + static void + end_directive (cpp_reader *pfile, int skip_line) + { +- if (pfile->state.in_deferred_pragma) +- ; +- else if (CPP_OPTION (pfile, traditional)) ++ if (CPP_OPTION (pfile, traditional)) + { + /* Revert change of prepare_directive_trad. */ +- pfile->state.prevent_expansion--; ++ if (!pfile->state.in_deferred_pragma) ++ pfile->state.prevent_expansion--; + + if (pfile->directive != &dtable[T_DEFINE]) + _cpp_remove_overlay (pfile); + } ++ else if (pfile->state.in_deferred_pragma) ++ ; + /* We don't skip for an assembler #. */ + else if (skip_line) + { +--- a/src/libffi/ChangeLog ++++ b/src/libffi/ChangeLog +@@ -1,3 +1,18 @@ ++2011-02-09 Rainer Orth ++ ++ PR libffi/46661 ++ * testsuite/libffi.call/cls_pointer.c (main): Cast void * to ++ uintptr_t first. ++ * testsuite/libffi.call/cls_pointer_stack.c (main): Likewise. ++ ++2010-12-17 Rainer Orth ++ ++ Backport from mainline: ++ 2010-12-01 Rainer Orth ++ ++ * testsuite/libffi.call/ffitest.h [__sgi] (PRId64, PRIu64): Define. ++ (PRIuPTR): Define. ++ + 2010-12-16 Release Manager + + * GCC 4.5.2 released. +--- a/src/libffi/testsuite/libffi.call/cls_pointer.c ++++ b/src/libffi/testsuite/libffi.call/cls_pointer.c +@@ -65,7 +65,7 @@ + + CHECK(ffi_prep_closure_loc(pcl, &cif, cls_pointer_gn, NULL, code) == FFI_OK); + +- res = (ffi_arg)((void*(*)(void*, void*))(code))(arg1, arg2); ++ res = (ffi_arg)(uintptr_t)((void*(*)(void*, void*))(code))(arg1, arg2); + /* { dg-output "\n0x12345678 0x89abcdef: 0x9be02467" } */ + printf("res: 0x%08x\n", (unsigned int) res); + /* { dg-output "\nres: 0x9be02467" } */ +--- a/src/libffi/testsuite/libffi.call/cls_pointer_stack.c ++++ b/src/libffi/testsuite/libffi.call/cls_pointer_stack.c +@@ -129,7 +129,7 @@ + + CHECK(ffi_prep_closure_loc(pcl, &cif, cls_pointer_gn, NULL, code) == FFI_OK); + +- res = (ffi_arg)((void*(*)(void*, void*))(code))(arg1, arg2); ++ res = (ffi_arg)(uintptr_t)((void*(*)(void*, void*))(code))(arg1, arg2); + + printf("res: 0x%08x\n", (unsigned int) res); + // { dg-output "\n0x01234567 0x89abcdef: 0x8acf1356" } +--- a/src/libffi/testsuite/libffi.call/ffitest.h ++++ b/src/libffi/testsuite/libffi.call/ffitest.h +@@ -77,6 +77,26 @@ + #define PRIuPTR "lu" + #endif + ++/* IRIX kludge. */ ++#if defined(__sgi) ++/* IRIX 6.5 provides all definitions, but only for C99 ++ compilations. */ ++#if (_MIPS_SZLONG == 32) ++#define PRId64 "lld" ++#define PRIu64 "llu" ++#endif ++/* This doesn't match , which always has "lld" here, but the ++ arguments are uint64_t, int64_t, which are unsigned long, long for ++ 64-bit in . */ ++#if (_MIPS_SZLONG == 64) ++#define PRId64 "ld" ++#define PRIu64 "lu" ++#endif ++/* This doesn't match , which has "u" here, but the arguments ++ are uintptr_t, which is always unsigned long. */ ++#define PRIuPTR "lu" ++#endif ++ + /* Solaris < 10 kludge. */ + #if defined(__sun__) && defined(__svr4__) && !defined(PRIuPTR) + #if defined(__arch64__) || defined (__x86_64__) +--- a/src/libgcc/Makefile.in ++++ b/src/libgcc/Makefile.in +@@ -400,18 +400,24 @@ + endif + endif + ++ifeq ($(LIB2_DIVMOD_EXCEPTION_FLAGS),) ++# Provide default flags for compiling divmod functions, if they haven't been ++# set already by a target-specific Makefile fragment. ++LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions -fnon-call-exceptions ++endif ++ + # Build LIB2_DIVMOD_FUNCS. + lib2-divmod-o = $(patsubst %,%$(objext),$(LIB2_DIVMOD_FUNCS)) + $(lib2-divmod-o): %$(objext): $(gcc_srcdir)/libgcc2.c + $(gcc_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \ +- -fexceptions -fnon-call-exceptions $(vis_hide) ++ $(LIB2_DIVMOD_EXCEPTION_FLAGS) $(vis_hide) + libgcc-objects += $(lib2-divmod-o) + + ifeq ($(enable_shared),yes) + lib2-divmod-s-o = $(patsubst %,%_s$(objext),$(LIB2_DIVMOD_FUNCS)) + $(lib2-divmod-s-o): %_s$(objext): $(gcc_srcdir)/libgcc2.c + $(gcc_s_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \ +- -fexceptions -fnon-call-exceptions ++ $(LIB2_DIVMOD_EXCEPTION_FLAGS) + libgcc-s-objects += $(lib2-divmod-s-o) + endif + +--- a/src/libgcc/config/arm/t-divmod-ef ++++ b/src/libgcc/config/arm/t-divmod-ef +@@ -0,0 +1,4 @@ ++# On ARM, specifying -fnon-call-exceptions will needlessly pull in ++# the unwinder in simple programs which use 64-bit division. Omitting ++# the option is safe. ++LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions +--- a/src/libgcc/config.host ++++ b/src/libgcc/config.host +@@ -208,12 +208,15 @@ + arm*-*-netbsd*) + ;; + arm*-*-linux*) # ARM GNU/Linux with ELF ++ tmake_file="${tmake_file} arm/t-divmod-ef" + ;; + arm*-*-uclinux*) # ARM ucLinux ++ tmake_file="${tmake_file} arm/t-divmod-ef" + ;; + arm*-*-ecos-elf) + ;; + arm*-*-eabi* | arm*-*-symbianelf* ) ++ tmake_file="${tmake_file} arm/t-divmod-ef" + ;; + arm*-*-rtems*) + ;; +--- a/src/libgcc/shared-object.mk ++++ b/src/libgcc/shared-object.mk +@@ -8,11 +8,13 @@ + + ifeq ($(suffix $o),.c) + ++c_flags-$(base)$(objext) := $(c_flags) + $(base)$(objext): $o +- $(gcc_compile) $(c_flags) -c $< $(vis_hide) ++ $(gcc_compile) $(c_flags-$@) -c $< $(vis_hide) + ++c_flags-$(base)_s$(objext) := $(c_flags) + $(base)_s$(objext): $o +- $(gcc_s_compile) $(c_flags) -c $< ++ $(gcc_s_compile) $(c_flags-$@) -c $< + + else + +--- a/src/libgcc/static-object.mk ++++ b/src/libgcc/static-object.mk +@@ -8,8 +8,9 @@ + + ifeq ($(suffix $o),.c) + ++c_flags-$(base)$(objext) := $(c_flags) + $(base)$(objext): $o +- $(gcc_compile) $(c_flags) -c $< $(vis_hide) ++ $(gcc_compile) $(c_flags-$@) -c $< $(vis_hide) + + else + +--- a/src/libgomp/ChangeLog ++++ b/src/libgomp/ChangeLog +@@ -1,3 +1,18 @@ ++2011-01-16 Jakub Jelinek ++ ++ Backport from mainline ++ 2010-12-14 Jakub Jelinek ++ ++ PR fortran/46874 ++ * libgomp.fortran/allocatable6.f90: New test. ++ ++2010-12-17 Rainer Orth ++ ++ Backport from mainline: ++ 2010-12-01 Rainer Orth ++ ++ * configure.tgt (mips-sgi-irix6*): Add -lpthread to XLDFLAGS. ++ + 2010-12-16 Release Manager + + * GCC 4.5.2 released. +--- a/src/libgomp/configure.tgt ++++ b/src/libgomp/configure.tgt +@@ -125,6 +125,10 @@ + config_path="bsd posix" + ;; + ++ mips-sgi-irix6*) ++ # Need to link with -lpthread so libgomp.so is self-contained. ++ XLDFLAGS="${XLDFLAGS} -lpthread" ++ ;; + *) + ;; + +--- a/src/libgomp/testsuite/libgomp.fortran/allocatable6.f90 ++++ b/src/libgomp/testsuite/libgomp.fortran/allocatable6.f90 +@@ -0,0 +1,45 @@ ++! PR fortran/46874 ++! { dg-do run } ++ ++ interface ++ subroutine sub (a, b, c, d, n) ++ integer :: n ++ integer, allocatable :: a(:), b(:), c(:), d(:) ++ end subroutine ++ end interface ++ ++ integer, allocatable :: a(:), b(:), c(:), d(:) ++ integer :: i, j ++ allocate (a(50), b(50), c(50), d(50)) ++ do i = 1, 50 ++ a(i) = 2 + modulo (i, 7) ++ b(i) = 179 - modulo (i, 11) ++ end do ++ c = 0 ++ d = 2147483647 ++ call sub (a, b, c, d, 50) ++ do i = 1, 50 ++ j = 0 ++ if (i .eq. 3) then ++ j = 8 ++ else if (i .gt. 1 .and. i .lt. 9) then ++ j = 7 ++ end if ++ if (c(i) .ne. j) call abort ++ j = 179 - modulo (i, 11) ++ if (i .gt. 1 .and. i .lt. 9) j = i ++ if (d(i) .ne. j) call abort ++ end do ++ deallocate (a, b, c, d) ++end ++ ++subroutine sub (a, b, c, d, n) ++ integer :: n ++ integer, allocatable :: a(:), b(:), c(:), d(:) ++!$omp parallel do shared(a, b) reduction(+:c) reduction(min:d) ++ do i = 1, n ++ c(a(i)) = c(a(i)) + 1 ++ d(i) = min(d(i), b(i)) ++ d(a(i)) = min(d(a(i)), a(i)) ++ end do ++end +--- a/src/libjava/ChangeLog ++++ b/src/libjava/ChangeLog +@@ -1,3 +1,24 @@ ++2011-01-07 Rainer Orth ++ ++ Backport from mainline: ++ 2011-01-06 Rainer Orth ++ ++ * testsuite/libjava.jni/jni.exp (gcj_jni_get_cxxflags_invocation): ++ Add -shared-libgcc to cxxflags for *-*-solaris*. ++ Remove -lsocket. ++ ++2010-12-13 Andrew John Hughes ++ ++ PR libgcj/46774 ++ * libjava/java/security/VMAccessController.java: ++ (DEFAULT_CONTEXT): Create ProtectionDomain with ++ four argument constructor (arguments are the same ++ as those implied by the two argument constructor). ++ (getContext()): Create ProtectionDomain instances ++ with four argument constructor using a null Principal ++ array (as before) but including the classloader, which ++ was always null before. ++ + 2010-12-16 Release Manager + + * GCC 4.5.2 released. +--- a/src/libjava/java/security/VMAccessController.java ++++ b/src/libjava/java/security/VMAccessController.java +@@ -56,7 +56,7 @@ + Permissions permissions = new Permissions(); + permissions.add(new AllPermission()); + ProtectionDomain[] domain = new ProtectionDomain[] { +- new ProtectionDomain(source, permissions) ++ new ProtectionDomain(source, permissions, null, null) + }; + DEFAULT_CONTEXT = new AccessControlContext(domain); + } +@@ -178,12 +178,13 @@ + for (int i = 3; i < classes.length; i++) + { + Class clazz = classes[i]; ++ ClassLoader loader = clazz.getClassLoader(); + + if (DEBUG) + { + debug("checking " + clazz); + // subject to getClassLoader RuntimePermission +- debug("loader = " + clazz.getClassLoader()); ++ debug("loader = " + loader); + } + + if (privileged && i == classes.length - 2) +@@ -208,7 +209,8 @@ + // Create a static snapshot of this domain, which may change over time + // if the current policy changes. + domains.add(new ProtectionDomain(domain.getCodeSource(), +- domain.getPermissions())); ++ domain.getPermissions(), ++ loader, null)); + } + + if (DEBUG) +--- a/src/libjava/testsuite/libjava.jni/jni.exp ++++ b/src/libjava/testsuite/libjava.jni/jni.exp +@@ -274,8 +274,10 @@ + eval lappend cxxflags "-shared-libgcc -lgcj $libiconv" + } + ++ # Make sure libgcc unwinder is used on 64-bit Solaris 10+/x86 rather than ++ # the libc one. + if { [istarget "*-*-solaris*"] } { +- lappend cxxflags "-lsocket" ++ lappend cxxflags "-shared-libgcc" + } + + return $cxxflags +--- a/src/libstdc++-v3/ChangeLog ++++ b/src/libstdc++-v3/ChangeLog +@@ -1,3 +1,54 @@ ++2011-02-13 Gerald Pfeifer ++ ++ * doc/xml/faq.xml: Adjust link to bug database. ++ Remove old item on broken header files. ++ ++2011-02-12 Paolo Carlini ++ ++ PR libstdc++/47709 ++ * include/ext/algorithm (is_heap): In C++0x mode import from ++ namespace std. ++ * testsuite/ext/is_heap/47709.cc: New. ++ ++2011-02-08 Jonathan Wakely ++ ++ * doc/xml/gnu/gpl-2.0.xml: Remove. ++ * doc/Makefile.am: Update. ++ * doc/Makefile.in: Regenerate. ++ ++2011-02-06 Gerald Pfeifer ++ ++ * doc/xml/manual/debug.xml: Use GDB instead of gdb. ++ Adjust link to GDB manual. ++ ++2011-02-01 Paolo Carlini ++ ++ PR libstdc++/46914 ++ * include/bits/atomic_0.h (_ATOMIC_STORE_, _ATOMIC_MODIFY_, ++ _ATOMIC_CMPEXCHNG_): Rename __v -> __w, and __m -> __n, to ++ avoid name conflicts. ++ ++2011-01-30 Gerald Pfeifer ++ ++ * doc/xml/manual/codecvt.xml: Fix link to The Austin Common ++ Standards Revision Group. ++ * doc/xml/manual/locale.xml: Ditto. ++ * doc/xml/manual/messages.xml: Ditto. ++ * doc/xml/manual/using_exceptions.xml: Ditto. ++ ++2011-01-19 Graham Reed ++ ++ PR libstdc++/47354 ++ * src/bitmap_allocator.cc (free_list::_M_get): Lock mutex. ++ ++2010-12-17 Rainer Orth ++ ++ Backport from mainline: ++ 2010-12-10 Rainer Orth ++ ++ * testsuite/lib/libstdc++.exp (v3-build_support): Delete ++ libtestc++.a before creation. ++ + 2010-12-16 Release Manager + + * GCC 4.5.2 released. +--- a/src/libstdc++-v3/acinclude.m4 ++++ b/src/libstdc++-v3/acinclude.m4 +@@ -1740,41 +1740,11 @@ + if test $enable_clocale_flag = gnu; then + AC_EGREP_CPP([_GLIBCXX_ok], [ + #include +- #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 2) ++ #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(__UCLIBC__) + _GLIBCXX_ok + #endif + ], enable_clocale_flag=gnu, enable_clocale_flag=generic) + +- if test $enable_clocale = auto; then +- # Test for bugs early in glibc-2.2.x series +- AC_TRY_RUN([ +- #define _GNU_SOURCE 1 +- #include +- #include +- #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 2) +- extern __typeof(newlocale) __newlocale; +- extern __typeof(duplocale) __duplocale; +- extern __typeof(strcoll_l) __strcoll_l; +- #endif +- int main() +- { +- const char __one[] = "Äuglein Augmen"; +- const char __two[] = "Äuglein"; +- int i; +- int j; +- __locale_t loc; +- __locale_t loc_dup; +- loc = __newlocale(1 << LC_ALL, "de_DE", 0); +- loc_dup = __duplocale(loc); +- i = __strcoll_l(__one, __two, loc); +- j = __strcoll_l(__one, __two, loc_dup); +- return 0; +- } +- ], +- [enable_clocale_flag=gnu],[enable_clocale_flag=generic], +- [enable_clocale_flag=generic]) +- fi +- + # Set it to scream when it hurts. + ac_save_CFLAGS="$CFLAGS" + CFLAGS="-Wimplicit-function-declaration -Werror" +--- a/src/libstdc++-v3/configure ++++ b/src/libstdc++-v3/configure +@@ -15627,7 +15627,7 @@ + /* end confdefs.h. */ + + #include +- #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 2) ++ #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(__UCLIBC__) + _GLIBCXX_ok + #endif + +@@ -15641,49 +15641,6 @@ + rm -f conftest* + + +- if test $enable_clocale = auto; then +- # Test for bugs early in glibc-2.2.x series +- if test "$cross_compiling" = yes; then : +- enable_clocale_flag=generic +-else +- cat confdefs.h - <<_ACEOF >conftest.$ac_ext +-/* end confdefs.h. */ +- +- #define _GNU_SOURCE 1 +- #include +- #include +- #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 2) +- extern __typeof(newlocale) __newlocale; +- extern __typeof(duplocale) __duplocale; +- extern __typeof(strcoll_l) __strcoll_l; +- #endif +- int main() +- { +- const char __one[] = "Äuglein Augmen"; +- const char __two[] = "Äuglein"; +- int i; +- int j; +- __locale_t loc; +- __locale_t loc_dup; +- loc = __newlocale(1 << LC_ALL, "de_DE", 0); +- loc_dup = __duplocale(loc); +- i = __strcoll_l(__one, __two, loc); +- j = __strcoll_l(__one, __two, loc_dup); +- return 0; +- } +- +-_ACEOF +-if ac_fn_c_try_run "$LINENO"; then : +- enable_clocale_flag=gnu +-else +- enable_clocale_flag=generic +-fi +-rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ +- conftest.$ac_objext conftest.beam conftest.$ac_ext +-fi +- +- fi +- + # Set it to scream when it hurts. + ac_save_CFLAGS="$CFLAGS" + CFLAGS="-Wimplicit-function-declaration -Werror" +--- a/src/libstdc++-v3/doc/Makefile.am ++++ b/src/libstdc++-v3/doc/Makefile.am +@@ -204,7 +204,6 @@ + + xml_sources_extra = \ + ${xml_dir}/gnu/fdl-1.2.xml \ +- ${xml_dir}/gnu/gpl-2.0.xml \ + ${xml_dir}/gnu/gpl-3.0.xml + + xml_sources = \ +--- a/src/libstdc++-v3/doc/Makefile.in ++++ b/src/libstdc++-v3/doc/Makefile.in +@@ -343,7 +343,6 @@ + + xml_sources_extra = \ + ${xml_dir}/gnu/fdl-1.2.xml \ +- ${xml_dir}/gnu/gpl-2.0.xml \ + ${xml_dir}/gnu/gpl-3.0.xml + + xml_sources = \ +--- a/src/libstdc++-v3/doc/xml/faq.xml ++++ b/src/libstdc++-v3/doc/xml/faq.xml +@@ -636,6 +636,8 @@ + C library (glibc) version 2.2.5. That version of glibc is over a + year old and contains necessary bugfixes. Many GNU/Linux distros make + glibc version 2.3.x available now. ++ libstdc++ 4.6.0 and later require glibc 2.3 or later for this ++ localization and formatting code. + + The guideline is simple: the more recent the C++ library, the + more recent the C library. (This is also documented in the main +@@ -745,7 +747,7 @@ + + + Before reporting a bug, please examine the +- bugs database with the ++ bugs database with the + category set to g++. + + +@@ -848,17 +850,9 @@ + + + +- If you have found an extremely broken header file which is +- causing problems for you, look carefully before submitting a +- "high" priority bug report (which you probably +- shouldn't do anyhow; see the last paragraph of the page +- describing the GCC +- bug database). +- +- +- If the headers are in ${prefix}/include/g++-3, or +- if the installed library's name looks like +- libstdc++-2.10.a or ++ If you are using headers in ++ ${prefix}/include/g++-3, or if the installed ++ library's name looks like libstdc++-2.10.a or + libstdc++-libc6-2.10.so, then you are using the + old libstdc++-v2 library, which is nonstandard and + unmaintained. Do not report problems with -v2 to the -v3 +--- a/src/libstdc++-v3/doc/xml/gnu/gpl-2.0.xml ++++ b/src/libstdc++-v3/doc/xml/gnu/gpl-2.0.xml +@@ -1,366 +0,0 @@ +- +- +- +- +- GNU General Public License +- Version 2, June 1991 +- +- 1989, 1991 +- Free Software Foundation, Inc. +- +- +- +-
Free Software Foundation, Inc. +- 51 Franklin Street, Fifth Floor, +- Boston, MA 02110-1301 +- USA +-
+- +- Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. +- +- Version 2, June 1991 +- +- GNU General Public License +-
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+- Section 2 +- You may modify your copy or copies of the Program or any portion of it, thus +- forming a work based on the Program, and copy and distribute such modifications +- or work under the terms of +- Section 1 above, provided +- that you also meet all of these conditions: +- +- +- You must cause the modified files to carry prominent notices stating that +- you changed the files and the date of any change. +- +- +- You must cause any work that you distribute or publish, that in whole or +- in part contains or is derived from the Program or any part thereof, to be +- licensed as a whole at no charge to all third parties under the terms of +- this License. +- +- +- If the modified program normally reads commands interactively when run, you +- must cause it, when started running for such interactive use in the most +- ordinary way, to print or display an announcement including an appropriate +- copyright notice and a notice that there is no warranty (or else, saying +- that you provide a warranty) and that users may redistribute the program +- under these conditions, and telling the user how to view a copy of this +- License. (Exception: If the Program itself is interactive but does not +- normally print such an announcement, your work based on the Program is not +- required to print an announcement.) +- +- +- +- +- These requirements apply to the modified work as a whole. If identifiable sections +- of that work are not derived from the Program, and can be reasonably considered +- independent and separate works in themselves, then this License, and its terms, +- do not apply to those sections when you distribute them as separate works. But when +- you distribute the same sections as part of a whole which is a work based on the +- Program, the distribution of the whole must be on the terms of this License, whose +- permissions for other licensees extend to the entire whole, and thus to each and +- every part regardless of who wrote it. +- +- Thus, it is not the intent of this section to claim rights or contest your rights +- to work written entirely by you; rather, the intent is to exercise the right to control +- the distribution of derivative or collective works based on the Program. +- +- In addition, mere aggregation of another work not based on the Program with the Program +- (or with a work based on the Program) on a volume of a storage or distribution medium +- does not bring the other work under the scope of this License. +-
+-
+- Section 3 +- You may copy and distribute the Program (or a work based on it, under +- Section 2 in object code or executable form under the terms of +- Sections 1 and +- 2 above provided that you also do one of the following: +- +- +- Accompany it with the complete corresponding machine-readable source code, which +- must be distributed under the terms of Sections 1 and 2 above on a medium +- customarily used for software interchange; or, +- +- +- Accompany it with a written offer, valid for at least three years, to give any +- third party, for a charge no more than your cost of physically performing source +- distribution, a complete machine-readable copy of the corresponding source code, +- to be distributed under the terms of Sections 1 and 2 above on a medium customarily +- used for software interchange; or, +- +- +- Accompany it with the information you received as to the offer to distribute +- corresponding source code. (This alternative is allowed only for noncommercial +- distribution and only if you received the program in object code or executable form +- with such an offer, in accord with Subsection b above.) +- +- +- +- +- The source code for a work means the preferred form of the work for making modifications +- to it. For an executable work, complete source code means all the source code for all modules +- it contains, plus any associated interface definition files, plus the scripts used to control +- compilation and installation of the executable. However, as a special exception, the source +- code distributed need not include anything that is normally distributed (in either source or +- binary form) with the major components (compiler, kernel, and so on) of the operating system +- on which the executable runs, unless that component itself accompanies the executable. +- +- If distribution of executable or object code is made by offering access to copy from a +- designated place, then offering equivalent access to copy the source code from the same place +- counts as distribution of the source code, even though third parties are not compelled to +- copy the source along with the object code. +-
+-
+- Section 4 +- You may not copy, modify, sublicense, or distribute the Program except as expressly provided +- under this License. Any attempt otherwise to copy, modify, sublicense or distribute the +- Program is void, and will automatically terminate your rights under this License. However, +- parties who have received copies, or rights, from you under this License will not have their +- licenses terminated so long as such parties remain in full compliance. +-
+-
+- Section 5 +- You are not required to accept this License, since you have not signed it. However, nothing +- else grants you permission to modify or distribute the Program or its derivative works. +- These actions are prohibited by law if you do not accept this License. Therefore, by modifying +- or distributing the Program (or any work based on the Program), you indicate your acceptance +- of this License to do so, and all its terms and conditions for copying, distributing or +- modifying the Program or works based on it. +-
+-
+- Section 6 +- Each time you redistribute the Program (or any work based on the Program), the recipient +- automatically receives a license from the original licensor to copy, distribute or modify +- the Program subject to these terms and conditions. You may not impose any further restrictions +- on the recipients' exercise of the rights granted herein. You are not responsible for enforcing +- compliance by third parties to this License. +-
+-
+- Section 7 +- If, as a consequence of a court judgment or allegation of patent infringement or for any other +- reason (not limited to patent issues), conditions are imposed on you (whether by court order, +- agreement or otherwise) that contradict the conditions of this License, they do not excuse you +- from the conditions of this License. If you cannot distribute so as to satisfy simultaneously +- your obligations under this License and any other pertinent obligations, then as a consequence +- you may not distribute the Program at all. For example, if a patent license would not permit +- royalty-free redistribution of the Program by all those who receive copies directly or +- indirectly through you, then the only way you could satisfy both it and this License would be +- to refrain entirely from distribution of the Program. +- +- If any portion of this section is held invalid or unenforceable under any particular circumstance, +- the balance of the section is intended to apply and the section as a whole is intended to apply +- in other circumstances. +- +- It is not the purpose of this section to induce you to infringe any patents or other property +- right claims or to contest validity of any such claims; this section has the sole purpose of +- protecting the integrity of the free software distribution system, which is implemented by public +- license practices. Many people have made generous contributions to the wide range of software +- distributed through that system in reliance on consistent application of that system; it is up +- to the author/donor to decide if he or she is willing to distribute software through any other +- system and a licensee cannot impose that choice. +- +- This section is intended to make thoroughly clear what is believed to be a consequence of the +- rest of this License. +-
+-
+- Section 8 +- If the distribution and/or use of the Program is restricted in certain countries either by patents +- or by copyrighted interfaces, the original copyright holder who places the Program under this License +- may add an explicit geographical distribution limitation excluding those countries, so that +- distribution is permitted only in or among countries not thus excluded. In such case, this License +- incorporates the limitation as if written in the body of this License. +-
+-
+- Section 9 +- The Free Software Foundation may publish revised and/or new versions of the General Public License +- from time to time. Such new versions will be similar in spirit to the present version, but may differ +- in detail to address new problems or concerns. +- +- Each version is given a distinguishing version number. If the Program specifies a version number of +- this License which applies to it and any later version, you have the option of following the terms +- and conditions either of that version or of any later version published by the Free Software +- Foundation. If the Program does not specify a version number of this License, you may choose any +- version ever published by the Free Software Foundation. +-
+-
+- Section 10 +- If you wish to incorporate parts of the Program into other free programs whose distribution +- conditions are different, write to the author to ask for permission. For software which is copyrighted +- by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions +- for this. Our decision will be guided by the two goals of preserving the free status of all +- derivatives of our free software and of promoting the sharing and reuse of software generally. +-
+-
+- NO WARRANTY Section 11 +- BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT +- PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR +- OTHER PARTIES PROVIDE THE PROGRAM AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, +- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +- PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +- PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. +-
+-
+- Section 12 +- IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR +- ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU +- FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE +- USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED +- INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH +- ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +- DAMAGES. +- +- END OF TERMS AND CONDITIONS +-
+-
+-
+- How to Apply These Terms to Your New Programs +- If you develop a new program, and you want it to be of the greatest +- possible use to the public, the best way to achieve this is to make it +- free software which everyone can redistribute and change under these terms. +- +- To do so, attach the following notices to the program. It is safest +- to attach them to the start of each source file to most effectively +- convey the exclusion of warranty; and each file should have at least +- the copyright line and a pointer to where the full notice is found. +- +- <one line to give the program's name and a brief idea of what it does.> +- Copyright (C) <year> <name of author> +- +- This program is free software; you can redistribute it and/or modify +- it under the terms of the GNU General Public License as published by +- the Free Software Foundation; either version 2 of the License, or +- (at your option) any later version. +- +- This program is distributed in the hope that it will be useful, +- but WITHOUT ANY WARRANTY; without even the implied warranty of +- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- GNU General Public License for more details. +- +- You should have received a copy of the GNU General Public License +- along with this program; if not, write to the Free Software +- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +- +- Also add information on how to contact you by electronic and paper mail. +- +- If the program is interactive, make it output a short notice like this +- when it starts in an interactive mode: +- +- Gnomovision version 69, Copyright (C) year name of author +- Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type show w. +- This is free software, and you are welcome to redistribute it +- under certain conditions; type show c for details. +- +- The hypothetical commands show w and show c should +- show the appropriate parts of the General Public License. Of course, the commands you +- use may be called something other than show w and show c; +- they could even be mouse-clicks or menu items--whatever suits your program. +- +- You should also get your employer (if you work as a programmer) or your +- school, if any, to sign a copyright disclaimer for the program, if +- necessary. Here is a sample; alter the names: +- +- Yoyodyne, Inc., hereby disclaims all copyright interest in the program +- Gnomovision (which makes passes at compilers) written by James Hacker. +- +- <signature of Ty Coon>, 1 April 1989 +- Ty Coon, President of Vice +- +- This General Public License does not permit incorporating your program into +- proprietary programs. If your program is a subroutine library, you may +- consider it more useful to permit linking proprietary applications with the +- library. If this is what you want to do, use the GNU Library General +- Public License instead of this License. +-
+- +--- a/src/libstdc++-v3/doc/xml/manual/codecvt.xml ++++ b/src/libstdc++-v3/doc/xml/manual/codecvt.xml +@@ -595,7 +595,7 @@ + + + +- ++ + + System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008) + +--- a/src/libstdc++-v3/doc/xml/manual/configure.xml ++++ b/src/libstdc++-v3/doc/xml/manual/configure.xml +@@ -113,8 +113,7 @@ + If not explicitly specified, the configure proccess tries + to guess the most suitable package from the choices above. The + default is 'generic'. On glibc-based systems of sufficient +- vintage (2.2.5 and newer) and capability (with installed DE and +- FR locale data), 'gnu' is automatically selected. This option ++ vintage (2.3 and newer), 'gnu' is automatically selected. This option + can change the library ABI. + + +--- a/src/libstdc++-v3/doc/xml/manual/debug.xml ++++ b/src/libstdc++-v3/doc/xml/manual/debug.xml +@@ -45,7 +45,7 @@ + communicate information about source constructs can be changed via + -gdwarf-2 or -gstabs flags: some debugging + formats permit more expressive type and scope information to be +- shown in gdb. Expressiveness can be enhanced by flags like ++ shown in GDB. Expressiveness can be enhanced by flags like + -g3. The default debug information for a particular + platform can be identified via the value set by the + PREFERRED_DEBUGGING_TYPE macro in the gcc sources. +@@ -197,14 +197,14 @@ + + + +- Many options are available for gdb itself: please see +- "GDB features for C++" in the gdb documentation. Also ++ Many options are available for GDB itself: please see ++ "GDB features for C++" in the GDB documentation. Also + recommended: the other parts of this manual. + + + +- These settings can either be switched on in at the gdb command line, ++ These settings can either be switched on in at the GDB command line, + or put into a .gdbint file to establish default debugging + characteristics, like so: + +--- a/src/libstdc++-v3/doc/xml/manual/locale.xml ++++ b/src/libstdc++-v3/doc/xml/manual/locale.xml +@@ -571,7 +571,7 @@ + + + +- ++ + + System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008) + +--- a/src/libstdc++-v3/doc/xml/manual/messages.xml ++++ b/src/libstdc++-v3/doc/xml/manual/messages.xml +@@ -498,7 +498,7 @@ + + + +- ++ + + System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008) + +--- a/src/libstdc++-v3/doc/xml/manual/prerequisites.xml ++++ b/src/libstdc++-v3/doc/xml/manual/prerequisites.xml +@@ -52,16 +52,8 @@ + + If gcc 3.1.0 or later on is being used on linux, an attempt + will be made to use "C" library functionality necessary for +- C++ named locale support. For gcc 3.2.1 and later, this +- means that glibc 2.2.5 or later is required and the "C" +- library de_DE locale information must be installed. +- +- +- +- Note however that the sanity checks involving the de_DE +- locale are skipped when an explicit --enable-clocale=gnu +- configure option is used: only the basic checks are carried +- out, defending against misconfigurations. ++ C++ named locale support. For gcc 4.6.0 and later, this ++ means that glibc 2.3 or later is required. + + + +--- a/src/libstdc++-v3/doc/xml/manual/using_exceptions.xml ++++ b/src/libstdc++-v3/doc/xml/manual/using_exceptions.xml +@@ -440,7 +440,7 @@ + + + +- ++ + + System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008) + +--- a/src/libstdc++-v3/include/bits/atomic_0.h ++++ b/src/libstdc++-v3/include/bits/atomic_0.h +@@ -1,6 +1,6 @@ + // -*- C++ -*- header. + +-// Copyright (C) 2008, 2009 ++// Copyright (C) 2008, 2009, 2010, 2011 + // Free Software Foundation, Inc. + // + // This file is part of the GNU ISO C++ Library. This library is free +@@ -49,34 +49,34 @@ + atomic_flag_clear_explicit(__g, __x); \ + __r; }) + +-#define _ATOMIC_STORE_(__a, __m, __x) \ ++#define _ATOMIC_STORE_(__a, __n, __x) \ + ({__typeof__ _ATOMIC_MEMBER_* __p = &_ATOMIC_MEMBER_; \ +- __typeof__(__m) __v = (__m); \ ++ __typeof__(__n) __w = (__n); \ + __atomic_flag_base* __g = __atomic_flag_for_address(__p); \ + __atomic_flag_wait_explicit(__g, __x); \ +- *__p = __v; \ ++ *__p = __w; \ + atomic_flag_clear_explicit(__g, __x); \ +- __v; }) ++ __w; }) + +-#define _ATOMIC_MODIFY_(__a, __o, __m, __x) \ ++#define _ATOMIC_MODIFY_(__a, __o, __n, __x) \ + ({__typeof__ _ATOMIC_MEMBER_* __p = &_ATOMIC_MEMBER_; \ +- __typeof__(__m) __v = (__m); \ ++ __typeof__(__n) __w = (__n); \ + __atomic_flag_base* __g = __atomic_flag_for_address(__p); \ + __atomic_flag_wait_explicit(__g, __x); \ + __typeof__ _ATOMIC_MEMBER_ __r = *__p; \ +- *__p __o __v; \ ++ *__p __o __w; \ + atomic_flag_clear_explicit(__g, __x); \ + __r; }) + +-#define _ATOMIC_CMPEXCHNG_(__a, __e, __m, __x) \ ++#define _ATOMIC_CMPEXCHNG_(__a, __e, __n, __x) \ + ({__typeof__ _ATOMIC_MEMBER_* __p = &_ATOMIC_MEMBER_; \ + __typeof__(__e) __q = (__e); \ +- __typeof__(__m) __v = (__m); \ ++ __typeof__(__n) __w = (__n); \ + bool __r; \ + __atomic_flag_base* __g = __atomic_flag_for_address(__p); \ + __atomic_flag_wait_explicit(__g, __x); \ + __typeof__ _ATOMIC_MEMBER_ __t__ = *__p; \ +- if (__t__ == *__q) { *__p = __v; __r = true; } \ ++ if (__t__ == *__q) { *__p = __w; __r = true; } \ + else { *__q = __t__; __r = false; } \ + atomic_flag_clear_explicit(__g, __x); \ + __r; }) +--- a/src/libstdc++-v3/include/ext/algorithm ++++ b/src/libstdc++-v3/include/ext/algorithm +@@ -1,6 +1,7 @@ + // Algorithm extensions -*- C++ -*- + +-// Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 ++// Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, ++// 2009, 2010, 2011 + // Free Software Foundation, Inc. + // + // This file is part of the GNU ISO C++ Library. This library is free +@@ -424,6 +425,9 @@ + __out_last - __out_first); + } + ++#ifdef __GXX_EXPERIMENTAL_CXX0X__ ++ using std::is_heap; ++#else + /** + * This is an SGI extension. + * @ingroup SGIextensions +@@ -463,6 +467,7 @@ + + return std::__is_heap(__first, __comp, __last - __first); + } ++#endif + + // is_sorted, a predicated testing whether a range is sorted in + // nondescending order. This is an extension, not part of the C++ +--- a/src/libstdc++-v3/libsupc++/eh_personality.cc ++++ b/src/libstdc++-v3/libsupc++/eh_personality.cc +@@ -383,6 +383,8 @@ + switch (state & _US_ACTION_MASK) + { + case _US_VIRTUAL_UNWIND_FRAME: ++ if (state & _US_FORCE_UNWIND) ++ CONTINUE_UNWINDING; + actions = _UA_SEARCH_PHASE; + break; + +--- a/src/libstdc++-v3/src/bitmap_allocator.cc ++++ b/src/libstdc++-v3/src/bitmap_allocator.cc +@@ -49,6 +49,7 @@ + { + #if defined __GTHREADS + __mutex_type& __bfl_mutex = _M_get_mutex(); ++ __bfl_mutex.lock(); + #endif + const vector_type& __free_list = _M_get_free_list(); + using __gnu_cxx::__detail::__lower_bound; +--- a/src/libstdc++-v3/testsuite/ext/is_heap/47709.cc ++++ b/src/libstdc++-v3/testsuite/ext/is_heap/47709.cc +@@ -0,0 +1,29 @@ ++// { dg-do compile } ++// { dg-options "-std=gnu++0x" } ++ ++// Copyright (C) 2011 Free Software Foundation, Inc. ++// ++// This file is part of the GNU ISO C++ Library. This library is free ++// software; you can redistribute it and/or modify it under the ++// terms of the GNU General Public License as published by the ++// Free Software Foundation; either version 3, or (at your option) ++// any later version. ++ ++// This library is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License along ++// with this library; see the file COPYING3. If not see ++// . ++ ++#include ++#include ++ ++// libstdc++/47709 ++void foo() ++{ ++ std::vector v; ++ is_heap(v.begin(), v.end()); ++} +--- a/src/libstdc++-v3/testsuite/lib/libstdc++.exp ++++ b/src/libstdc++-v3/testsuite/lib/libstdc++.exp +@@ -586,6 +586,15 @@ + } + + # Collect into libtestc++.a ++ # Delete libtestc++.a first. Mixed 32 and 64-bit archives cannot be ++ # linked on IRIX 6. ++ # Use same procedure as gcc-dg.exp (remove-build-file). ++ if [is_remote host] { ++ # Ensure the host knows the file is gone by deleting there ++ # first. ++ remote_file host delete "./libtestc++.a" ++ } ++ remote_file build delete "./libtestc++.a" + if [info exists env(AR)] { + set ar $env(AR) + } else { +--- a/src/maintainer-scripts/gcc_release ++++ b/src/maintainer-scripts/gcc_release +@@ -167,13 +167,17 @@ + error "Could not tag sources" + SVNBRANCH=${TAG} + fi +- SVNREV=`${SVN} info "${SVNROOT}/${SVNBRANCH}"|awk '/Revision:/ {print $2}'` ++ #XXXXX ++ #SVNREV=`${SVN} info "${SVNROOT}/${SVNBRANCH}"|awk '/Revision:/ {print $2}'` ++ SVNREV=165300 + + # Export the current sources. + inform "Retrieving sources (svn export -r ${SVNREV} ${SVNROOT}/${SVNBRANCH})" + +- ${SVN} -q export -r${SVNREV} "${SVNROOT}/${SVNBRANCH}" "`basename ${SOURCE_DIRECTORY}`" ||\ +- error "Could not retrieve sources" ++ #XXXXX ++ #${SVN} -q export -r${SVNREV} "${SVNROOT}/${SVNBRANCH}" "`basename ${SOURCE_DIRECTORY}`" ||\ ++ # error "Could not retrieve sources" ++ cp -a /scratch/packages/gcc/bzr/4.5 "`basename ${SOURCE_DIRECTORY}`" + + # Run gcc_update on them to set up the timestamps nicely, and (re)write + # the LAST_UPDATED file containing the SVN tag/revision used. +@@ -184,7 +188,7 @@ + # For a prerelease or real release, we need to generate additional + # files not present in SVN. + changedir "${SOURCE_DIRECTORY}" +- if [ $SNAPSHOT -ne 1 ]; then ++ if true || [ $SNAPSHOT -ne 1 ]; then + # Generate the documentation. + inform "Building install docs" + SOURCEDIR=${SOURCE_DIRECTORY}/gcc/doc +@@ -203,7 +207,7 @@ + # on at least one platform. + inform "Building compiler" + OBJECT_DIRECTORY=../objdir +- contrib/gcc_build -d ${SOURCE_DIRECTORY} -o ${OBJECT_DIRECTORY} \ ++ contrib/gcc_build -m -j4 -d ${SOURCE_DIRECTORY} -o ${OBJECT_DIRECTORY} \ + -c "--enable-generated-files-in-srcdir --disable-multilib" build || \ + error "Could not rebuild GCC" + fi --- gcc-4.5-4.5.2.orig/debian/patches/gcc-system-root.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-system-root.diff @@ -0,0 +1,17 @@ +# DP: Avoid include paths starting with a double slash + +--- a/src/gcc/configure.ac ++++ b/src/gcc/configure.ac +@@ -751,8 +751,10 @@ + yes) TARGET_SYSTEM_ROOT='${exec_prefix}/${target_noncanonical}/sys-root' ;; + *) TARGET_SYSTEM_ROOT=$with_sysroot ;; + esac +- +- TARGET_SYSTEM_ROOT_DEFINE='-DTARGET_SYSTEM_ROOT=\"$(TARGET_SYSTEM_ROOT)\"' ++ ++ if test "x$TARGET_SYSTEM_ROOT" != x/; then ++ TARGET_SYSTEM_ROOT_DEFINE='-DTARGET_SYSTEM_ROOT=\"$(TARGET_SYSTEM_ROOT)\"' ++ fi + CROSS_SYSTEM_HEADER_DIR='$(TARGET_SYSTEM_ROOT)$${sysroot_headers_suffix}$(NATIVE_SYSTEM_HEADER_DIR)' + + if test "x$prefix" = xNONE; then --- gcc-4.5-4.5.2.orig/debian/patches/ada-library-project-files-soname.diff +++ gcc-4.5-4.5.2/debian/patches/ada-library-project-files-soname.diff @@ -0,0 +1,77 @@ +# DP: - in project files, use the exact Library_Version provided, if any, as +# DP: the soname of libraries; do not strip minor version numbers +# DP: (PR ada/40025). + +Index: b/src/gcc/ada/mlib-tgt-specific-linux.adb +=================================================================== +--- a/src/gcc/ada/mlib-tgt-specific-linux.adb ++++ b/src/gcc/ada/mlib-tgt-specific-linux.adb +@@ -50,6 +50,8 @@ + + function Is_Archive_Ext (Ext : String) return Boolean; + ++ function Library_Major_Minor_Id_Supported return Boolean; ++ + --------------------------- + -- Build_Dynamic_Library -- + --------------------------- +@@ -142,7 +144,18 @@ + return Ext = ".a" or else Ext = ".so"; + end Is_Archive_Ext; + ++ -------------------------------------- ++ -- Library_Major_Minor_Id_Supported -- ++ -------------------------------------- ++ ++ function Library_Major_Minor_Id_Supported return Boolean is ++ begin ++ return False; ++ end Library_Major_Minor_Id_Supported; ++ + begin + Build_Dynamic_Library_Ptr := Build_Dynamic_Library'Access; + Is_Archive_Ext_Ptr := Is_Archive_Ext'Access; ++ Library_Major_Minor_Id_Supported_Ptr := ++ Library_Major_Minor_Id_Supported'Access; + end MLib.Tgt.Specific; +Index: b/src/gcc/ada/mlib.adb +=================================================================== +--- a/src/gcc/ada/mlib.adb ++++ b/src/gcc/ada/mlib.adb +@@ -31,6 +31,7 @@ + with Opt; + with Output; use Output; + ++with Mlib.Tgt; + with MLib.Utl; use MLib.Utl; + + with Prj.Com; +@@ -384,7 +385,7 @@ + -- Major_Id_Name -- + ------------------- + +- function Major_Id_Name ++ function Major_Id_Name_If_Supported + (Lib_Filename : String; + Lib_Version : String) + return String +@@ -438,6 +439,19 @@ + else + return ""; + end if; ++ end Major_Id_Name_If_Supported; ++ ++ function Major_Id_Name ++ (Lib_Filename : String; ++ Lib_Version : String) ++ return String ++ is ++ begin ++ if Mlib.Tgt.Library_Major_Minor_Id_Supported then ++ return Major_Id_Name_If_Supported (Lib_Filename, Lib_Version); ++ else ++ return ""; ++ end if; + end Major_Id_Name; + + -- Package elaboration --- gcc-4.5-4.5.2.orig/debian/patches/powerpc_remove_many.diff +++ gcc-4.5-4.5.2/debian/patches/powerpc_remove_many.diff @@ -0,0 +1,33 @@ +# DP: Subject: [PATCH] remove -many on __SPE__ target +# DP: this helps to to detect opcodes which are not part of the current +# DP: CPU because without -many gas won't touch them. This currently could +# DP: break the kernel build as the 603 on steroids cpus use performance +# DP: counter opcodes which are not available on the steroid less 603 core. + +Index: gcc-4.5.2/src/gcc/config/rs6000/rs6000.h +=================================================================== +--- gcc-4.5.2.orig/src/gcc/config/rs6000/rs6000.h 2009-12-07 16:34:21.000000000 +0100 ++++ gcc-4.5.2/src/gcc/config/rs6000/rs6000.h 2011-02-18 22:14:56.000000000 +0100 +@@ -89,6 +89,12 @@ + #define ASM_CPU_476_SPEC "-mpower4" + #endif + ++#ifndef __SPE__ ++#define ASM_CPU_SPU_MANY_NOT_SPE "-many" ++#else ++#define ASM_CPU_SPU_MANY_NOT_SPE ++#endif ++ + /* Common ASM definitions used by ASM_SPEC among the various targets for + handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to + provide the default assembler options if the user uses -mcpu=native, so if +@@ -160,7 +166,8 @@ + %{mcpu=e500mc: -me500mc} \ + %{mcpu=e500mc64: -me500mc64} \ + %{maltivec: -maltivec} \ +--many" ++" \ ++ASM_CPU_SPU_MANY_NOT_SPE + + #define CPP_DEFAULT_SPEC "" + --- gcc-4.5-4.5.2.orig/debian/patches/ada-polyorb-dsa.diff +++ gcc-4.5-4.5.2/debian/patches/ada-polyorb-dsa.diff @@ -0,0 +1,228 @@ +# DP: - backport support for PolyORB_DSA version 3 from the trunk. + +Index: b/src/gcc/ada/rtsfind.adb +=================================================================== +--- a/src/gcc/ada/rtsfind.adb ++++ b/src/gcc/ada/rtsfind.adb +@@ -298,6 +298,9 @@ + elsif U_Id in Ada_Streams_Child then + Name_Buffer (12) := '.'; + ++ elsif U_Id in Ada_Strings_Child then ++ Name_Buffer (12) := '.'; ++ + elsif U_Id in Ada_Text_IO_Child then + Name_Buffer (12) := '.'; + +Index: b/src/gcc/ada/rtsfind.ads +=================================================================== +--- a/src/gcc/ada/rtsfind.ads ++++ b/src/gcc/ada/rtsfind.ads +@@ -62,6 +62,9 @@ + -- Names of the form Ada_Streams_xxx are second level children + -- of Ada.Streams. + ++ -- Names of the form Ada_Strings_xxx are second level children ++ -- of Ada.Strings. ++ + -- Names of the form Ada_Text_IO_xxx are second level children + -- of Ada.Text_IO. + +@@ -121,6 +124,7 @@ + Ada_Interrupts, + Ada_Real_Time, + Ada_Streams, ++ Ada_Strings, + Ada_Tags, + Ada_Task_Identification, + Ada_Task_Termination, +@@ -150,6 +154,10 @@ + + Ada_Streams_Stream_IO, + ++ -- Children of Ada.Strings ++ ++ Ada_Strings_Unbounded, ++ + -- Children of Ada.Text_IO (for Text_IO_Kludge) + + Ada_Text_IO_Decimal_IO, +@@ -401,6 +409,11 @@ + + subtype Ada_Streams_Child is Ada_Child + range Ada_Streams_Stream_IO .. Ada_Streams_Stream_IO; ++ -- Range of values for children of Ada.Streams ++ ++ subtype Ada_Strings_Child is Ada_Child ++ range Ada_Strings_Unbounded .. Ada_Strings_Unbounded; ++ -- Range of values for children of Ada.Strings + + subtype Ada_Text_IO_Child is Ada_Child + range Ada_Text_IO_Decimal_IO .. Ada_Text_IO_Modular_IO; +@@ -526,6 +539,8 @@ + + RE_Stream_Access, -- Ada.Streams.Stream_IO + ++ RE_Unbounded_String, -- Ada.Strings.Unbounded ++ + RE_Access_Level, -- Ada.Tags + RE_Address_Array, -- Ada.Tags + RE_Addr_Ptr, -- Ada.Tags +@@ -1203,6 +1218,7 @@ + RE_TA_WWC, -- System.Partition_Interface + RE_TA_String, -- System.Partition_Interface + RE_TA_ObjRef, -- System.Partition_Interface ++ RE_TA_Std_String, -- System.Partition_Interface + RE_TA_TC, -- System.Partition_Interface + + RE_TC_Alias, -- System.Partition_Interface +@@ -1680,6 +1696,8 @@ + + RE_Stream_Access => Ada_Streams_Stream_IO, + ++ RE_Unbounded_String => Ada_Strings_Unbounded, ++ + RE_Access_Level => Ada_Tags, + RE_Address_Array => Ada_Tags, + RE_Addr_Ptr => Ada_Tags, +@@ -2348,6 +2366,7 @@ + RE_TA_WWC => System_Partition_Interface, + RE_TA_String => System_Partition_Interface, + RE_TA_ObjRef => System_Partition_Interface, ++ RE_TA_Std_String => System_Partition_Interface, + RE_TA_TC => System_Partition_Interface, + + RE_TC_Alias => System_Partition_Interface, +Index: b/src/gcc/ada/exp_dist.adb +=================================================================== +--- a/src/gcc/ada/exp_dist.adb ++++ b/src/gcc/ada/exp_dist.adb +@@ -6,7 +6,7 @@ + -- -- + -- B o d y -- + -- -- +--- Copyright (C) 1992-2008, Free Software Foundation, Inc. -- ++-- Copyright (C) 1992-2009, Free Software Foundation, Inc. -- + -- -- + -- GNAT is free software; you can redistribute it and/or modify it under -- + -- terms of the GNU General Public License as published by the Free Soft- -- +@@ -6638,13 +6638,13 @@ + Make_Function_Call (Loc, + Name => + New_Occurrence_Of +- (RTE (RE_TA_String), Loc), ++ (RTE (RE_TA_Std_String), Loc), + Parameter_Associations => New_List ( + Make_String_Literal (Loc, Name_String))), + Make_Function_Call (Loc, + Name => + New_Occurrence_Of +- (RTE (RE_TA_String), Loc), ++ (RTE (RE_TA_Std_String), Loc), + Parameter_Associations => New_List ( + Make_String_Literal (Loc, + Strval => Repo_Id_String)))))))))))); +@@ -8447,7 +8447,7 @@ + elsif U_Type = RTE (RE_Long_Long_Unsigned) then + Lib_RE := RE_FA_LLU; + +- elsif U_Type = Standard_String then ++ elsif Is_RTE (U_Type, RE_Unbounded_String) then + Lib_RE := RE_FA_String; + + -- Special DSA types +@@ -8944,7 +8944,11 @@ + for J in 1 .. Ndim loop + Lnam := New_External_Name ('L', J); + Hnam := New_External_Name ('H', J); +- Indt := Etype (Indx); ++ ++ -- Note, for empty arrays bounds may be out of ++ -- the range of Etype (Indx). ++ ++ Indt := Base_Type (Etype (Indx)); + + Append_To (Decls, + Make_Object_Declaration (Loc, +@@ -9217,6 +9221,7 @@ + + Typ : Entity_Id := Etype (N); + U_Type : Entity_Id; ++ C_Type : Entity_Id; + Fnam : Entity_Id := Empty; + Lib_RE : RE_Id := RE_Null; + +@@ -9312,7 +9317,7 @@ + elsif U_Type = RTE (RE_Long_Long_Unsigned) then + Lib_RE := RE_TA_LLU; + +- elsif U_Type = Standard_String then ++ elsif Is_RTE (U_Type, RE_Unbounded_String) then + Lib_RE := RE_TA_String; + + -- Special DSA types +@@ -9345,11 +9350,23 @@ + Fnam := RTE (Lib_RE); + end if; + ++ -- If Fnam is already analyzed, find the proper expected type, ++ -- else we have a newly constructed To_Any function and we know ++ -- that the expected type of its parameter is U_Type. ++ ++ if Ekind (Fnam) = E_Function ++ and then Present (First_Formal (Fnam)) ++ then ++ C_Type := Etype (First_Formal (Fnam)); ++ else ++ C_Type := U_Type; ++ end if; ++ + return + Make_Function_Call (Loc, + Name => New_Occurrence_Of (Fnam, Loc), + Parameter_Associations => +- New_List (Unchecked_Convert_To (U_Type, N))); ++ New_List (OK_Convert_To (C_Type, N))); + end Build_To_Any_Call; + + --------------------------- +@@ -10084,7 +10101,7 @@ + elsif U_Type = RTE (RE_Long_Long_Unsigned) then + Lib_RE := RE_TC_LLU; + +- elsif U_Type = Standard_String then ++ elsif Is_RTE (U_Type, RE_Unbounded_String) then + Lib_RE := RE_TC_String; + + -- Special DSA types +@@ -10184,7 +10201,7 @@ + begin + Append_To (Parameter_List, + Make_Function_Call (Loc, +- Name => New_Occurrence_Of (RTE (RE_TA_String), Loc), ++ Name => New_Occurrence_Of (RTE (RE_TA_Std_String), Loc), + Parameter_Associations => New_List ( + Make_String_Literal (Loc, S)))); + end Add_String_Parameter; +Index: b/src/gcc/ada/exp_dist.ads +=================================================================== +--- a/src/gcc/ada/exp_dist.ads ++++ b/src/gcc/ada/exp_dist.ads +@@ -6,7 +6,7 @@ + -- -- + -- S p e c -- + -- -- +--- Copyright (C) 1992-2008, Free Software Foundation, Inc. -- ++-- Copyright (C) 1992-2009, Free Software Foundation, Inc. -- + -- -- + -- GNAT is free software; you can redistribute it and/or modify it under -- + -- terms of the GNU General Public License as published by the Free Soft- -- +@@ -35,7 +35,7 @@ + PCS_Version_Number : constant array (PCS_Names) of Int := + (Name_No_DSA => 1, + Name_GARLIC_DSA => 1, +- Name_PolyORB_DSA => 2); ++ Name_PolyORB_DSA => 3); + -- PCS interface version. This is used to check for consistency between the + -- compiler used to generate distribution stubs and the PCS implementation. + -- It must be incremented whenever a change is made to the generated code --- gcc-4.5-4.5.2.orig/debian/patches/gcc-multiarch-trunk.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-multiarch-trunk.diff @@ -0,0 +1,322 @@ +--- ./src/gcc/incpath.c.orig 2009-11-30 16:46:01.000000000 +0100 ++++ ./src/gcc/incpath.c 2010-05-30 13:15:35.179823375 +0200 +@@ -30,6 +30,7 @@ + #include "intl.h" + #include "incpath.h" + #include "cppdefault.h" ++#include "multiarch.h" + + /* Microsoft Windows does not natively support inodes. + VMS has non-numeric inodes. */ +@@ -132,6 +133,9 @@ + const struct default_include *p; + int relocated = cpp_relocated(); + size_t len; ++#ifdef ENABLE_MULTIARCH ++ const char *multiarch; ++#endif + + if (iprefix && (len = cpp_GCC_INCLUDE_DIR_len) != 0) + { +@@ -150,8 +154,20 @@ + if (!strncmp (p->fname, cpp_GCC_INCLUDE_DIR, len)) + { + char *str = concat (iprefix, p->fname + len, NULL); ++#ifdef ENABLE_MULTIARCH ++ if (p->multilib == 1 && imultilib) ++ str = concat (str, dir_separator_str, imultilib, NULL); ++ else if (p->multilib == 2) ++ { ++ multiarch = multilib_to_multiarch (imultilib); ++ if (!multiarch) ++ continue; ++ str = concat (str, dir_separator_str, multiarch, NULL); ++ } ++#else + if (p->multilib && imultilib) + str = concat (str, dir_separator_str, imultilib, NULL); ++#endif + add_path (str, SYSTEM, p->cxx_aware, false); + } + } +@@ -195,8 +211,20 @@ + else + str = update_path (p->fname, p->component); + ++#ifdef ENABLE_MULTIARCH ++ if (p->multilib == 1 && imultilib) ++ str = concat (str, dir_separator_str, imultilib, NULL); ++ else if (p->multilib == 2) ++ { ++ multiarch = multilib_to_multiarch (imultilib); ++ if (!multiarch) ++ continue; ++ str = concat (str, dir_separator_str, multiarch, NULL); ++ } ++#else + if (p->multilib && imultilib) + str = concat (str, dir_separator_str, imultilib, NULL); ++#endif + + add_path (str, SYSTEM, p->cxx_aware, false); + } +--- ./src/gcc/cppdefault.c.orig 2008-07-21 18:06:19.000000000 +0200 ++++ ./src/gcc/cppdefault.c 2010-05-30 13:15:35.179823375 +0200 +@@ -60,6 +60,9 @@ + #endif + #ifdef LOCAL_INCLUDE_DIR + /* /usr/local/include comes before the fixincluded header files. */ ++# ifdef ENABLE_MULTIARCH ++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, ++# endif + { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 }, + #endif + #ifdef PREFIX_INCLUDE_DIR +@@ -95,6 +98,9 @@ + #endif + #ifdef STANDARD_INCLUDE_DIR + /* /usr/include comes dead last. */ ++# ifdef ENABLE_MULTIARCH ++ { STANDARD_INCLUDE_DIR, STANDARD_INCLUDE_COMPONENT, 0, 0, 1, 2 }, ++# endif + { STANDARD_INCLUDE_DIR, STANDARD_INCLUDE_COMPONENT, 0, 0, 1, 0 }, + #endif + { 0, 0, 0, 0, 0, 0 } +--- ./src/gcc/config.gcc.orig 2010-05-29 03:44:45.000000000 +0200 ++++ ./src/gcc/config.gcc 2010-05-30 13:15:35.179823375 +0200 +@@ -3559,3 +3559,12 @@ + target_cpu_default=$target_cpu_default2 + fi + fi ++ ++if test x${enable_multiarch} = xyes; then ++ multiarch_defaults=`echo ${target_noncanonical} | sed -e 's/unknown-//'` ++ multiarch_define="__`echo ${multiarch_defaults} | tr '-' '_'`__" ++ if test x${with_multiarch_defaults} != x; then ++ multiarch_defaults=${with_multiarch_defaults} ++ fi ++ tm_defines="${tm_defines} ${multiarch_define}=1 MULTIARCH_DEFAULTS=\\\"${multiarch_defaults}\\\"" ++fi +--- ./src/gcc/gcc.c.orig 2010-05-30 13:13:39.000000000 +0200 ++++ ./src/gcc/gcc.c 2010-05-30 13:15:35.169822547 +0200 +@@ -72,6 +72,7 @@ + #include "system.h" + #include "coretypes.h" + #include "multilib.h" /* before tm.h */ ++#include "multiarch.h" + #include "tm.h" + #include + #if ! defined( SIGCHLD ) && defined( SIGCLD ) +@@ -373,6 +374,9 @@ + static int used_arg (const char *, int); + static int default_arg (const char *, int); + static void set_multilib_dir (void); ++#ifdef ENABLE_MULTIARCH ++static void set_multiarch_dir (void); ++#endif + static void print_multilib_info (void); + static void perror_with_name (const char *); + static void display_help (void); +@@ -7314,6 +7318,11 @@ + xputenv (XOBFINISH (&collect_obstack, char *)); + } + ++#ifdef ENABLE_MULTIARCH ++ /* Add the multiarch directories to libraries path. */ ++ set_multiarch_dir (); ++#endif ++ + /* Warn about any switches that no pass was interested in. */ + + for (i = 0; (int) i < n_switches; i++) +@@ -8409,6 +8418,27 @@ + multilib_os_dir = multilib_dir; + } + ++#ifdef ENABLE_MULTIARCH ++/* Add the multiarch directories to libraries path. This uses the converted ++ multiarch triplet from the multilib value. ++ For example, if the target supports -m32/-m64 as multilib option and ++ defaults to 64, it will add /usr/lib/$triplet_target64/lib to library ++ path if either -m64 or no multilib option at all is set. And it will ++ add /usr/lib/$triplet_target32 if -m32 is set. Triplets are defined in ++ multiarch.def. */ ++ ++static void ++set_multiarch_dir (void) ++{ ++ const char *path; ++ ++ path = concat (STANDARD_STARTFILE_PREFIX_2, MULTIARCH_DEFAULTS, ++ dir_separator_str, NULL); ++ add_prefix (&startfile_prefixes, path, NULL, ++ PREFIX_PRIORITY_LAST, 0, 1); ++} ++#endif ++ + /* Print out the multiple library subdirectory selection + information. This prints out a series of lines. Each line looks + like SUBDIRECTORY;@OPTION@OPTION, with as many options as is +--- ./src/gcc/Makefile.in.orig 2010-07-14 01:54:35.000000000 +0200 ++++ ./src/gcc/Makefile.in 2010-07-14 02:34:22.260795585 +0200 +@@ -970,6 +970,7 @@ + PLUGIN_H = plugin.h $(GCC_PLUGIN_H) + PLUGIN_VERSION_H = plugin-version.h configargs.h + LIBFUNCS_H = libfuncs.h $(HASHTAB_H) ++MULTIARCH_H = multiarch.h + + # + # Now figure out from those variables how to compile and link. +@@ -2161,8 +2162,8 @@ + $(TARGET_H) langhooks.h $(CPPLIB_H) $(PLUGIN_H) + + incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \ +- intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \ +- $(MACHMODE_H) ++ intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(MULTIARCH_H) \ ++ $(TARGET_H) $(MACHMODE_H) + + prefix.o: prefix.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) prefix.h \ + Makefile $(BASEVER) +@@ -2187,7 +2188,7 @@ + + gcc.o: gcc.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) intl.h multilib.h \ + Makefile $(lang_specs_files) specs.h prefix.h $(GCC_H) $(FLAGS_H) \ +- configargs.h $(OBSTACK_H) $(OPTS_H) $(DIAGNOSTIC_H) $(VEC_H) ++ configargs.h $(OBSTACK_H) $(OPTS_H) $(DIAGNOSTIC_H) $(VEC_H) $(MULTIARCH_H) + (SHLIB_LINK='$(SHLIB_LINK)'; \ + $(COMPILER) $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) \ + $(DRIVER_DEFINES) \ +--- ./src/gcc/configure.ac.orig 2010-05-28 13:38:00.000000000 +0200 ++++ ./src/gcc/configure.ac 2010-05-30 13:15:35.169822547 +0200 +@@ -600,6 +600,19 @@ + [], [enable_multilib=yes]) + AC_SUBST(enable_multilib) + ++# Determine whether or not multiarch is enabled. ++AC_ARG_ENABLE(multiarch, ++[ --enable-multiarch enable multiarch support], ++[ ++ enable_multiarch=yes ++ AC_DEFINE(ENABLE_MULTIARCH, 1, ++ [Define if you want to use multiarch.]) ++],[]) ++AC_SUBST(enable_multiarch) ++ ++AC_ARG_WITH(multiarch-defaults, ++[ --with-multiarch-defaults set the default multiarch directory.],) ++ + # Enable __cxa_atexit for C++. + AC_ARG_ENABLE(__cxa_atexit, + [ --enable-__cxa_atexit enable __cxa_atexit for C++], +--- ./src/gcc/config.in.orig 2010-05-28 13:38:29.000000000 +0200 ++++ ./src/gcc/config.in 2010-05-30 13:15:35.169822547 +0200 +@@ -179,6 +179,10 @@ + #undef ENABLE_WIN32_REGISTRY + #endif + ++/* Define if you want to use multiarch. */ ++#ifndef USED_FOR_TARGET ++#undef ENABLE_MULTIARCH ++#endif + + /* Define to the name of a file containing a list of extra machine modes for + this architecture. */ +--- ./src/gcc/multiarch.h.orig 2010-05-30 13:15:35.179823375 +0200 ++++ ./src/gcc/multiarch.h 2010-05-30 13:15:35.179823375 +0200 +@@ -0,0 +1,95 @@ ++/* Header for multiarch handling (include directories, libraries path). ++ Copyright (C) 2009 Free Software Foundation, Inc. ++ Contributed by Arthur Loiret ++ ++This file is part of GCC. ++ ++GCC is free software; you can redistribute it and/or modify it under ++the terms of the GNU General Public License as published by the Free ++Software Foundation; either version 3, or (at your option) any later ++version. ++ ++GCC is distributed in the hope that it will be useful, but WITHOUT ANY ++WARRANTY; without even the implied warranty of MERCHANTABILITY or ++FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++for more details. ++ ++You should have received a copy of the GNU General Public License ++along with GCC; see the file COPYING3. If not see ++. */ ++ ++#ifndef GCC_MULTIARCH_H ++#define GCC_MULTIARCH_H ++ ++#include "tm.h" ++ ++struct multiarch_mapping ++{ ++ const char *const multilib; ++ const char *const multiarch; ++}; ++ ++const struct multiarch_mapping multiarch_mappings[] = { ++#ifdef ENABLE_MULTIARCH ++ { "", MULTIARCH_DEFAULTS }, ++# if defined(__x86_64_linux_gnu__) ++ { "32", "i386-linux-gnu" }, ++# endif ++# if defined(__i486_linux_gnu__) || defined(__i686_linux_gnu__) ++ { "64", "x86_64-linux-gnu" }, ++# endif ++# if defined(__powerpc64_linux_gnu__) ++ { "32", "powerpc-linux-gnu" }, ++# endif ++# if defined(__powerpc_linux_gnu__) ++ { "64", "powerpc64-linux-gnu" }, ++# endif ++# if defined(__sparc64_linux_gnu__) ++ { "32", "sparc-linux-gnu" }, ++# endif ++# if defined(__sparc_linux_gnu__) ++ { "64", "sparc64-linux-gnu" }, ++# endif ++# if defined(__s390x_linux_gnu__) ++ { "31", "s390-linux-gnu" }, ++# endif ++# if defined(__s390_linux_gnu__) ++ { "64", "s390x-linux-gnu" }, ++# endif ++# if defined(__mips_linux_gnu__) ++ { "n32", "mips64-linux-gnuabin32" }, ++ { "64", "mips64-linux-gnuabi64" }, ++# endif ++# if defined(__mipsel_linux_gnu__) ++ { "n32", "mips64el-linux-gnuabin32" }, ++ { "64", "mips64el-linux-gnuabi64" }, ++# endif ++# if defined(__x86_64_kfreebsd_gnu__) ++ { "32", "i386-kfreebsd-gnu" }, ++# endif ++# if defined(__sh4_linux_gnu__) ++ { "m4", "sh4-linux-gnu" }, ++ { "m4-nofpu", "sh4_nofpu-linux-gnu" }, ++# endif ++#endif /* ENABLE_MULTIARCH */ ++ { 0, 0 } ++}; ++ ++/* Convert the multilib option to the corresponding target triplet. ++ See multiarch.def and config.gcc for multilib/multiarch pairs. ++ When the default multilib is used, the corresponding multilib/multiarch ++ pair is { "", $target_tripplet }. */ ++static inline const char* ++multilib_to_multiarch (const char *imultilib) ++{ ++ const struct multiarch_mapping *p; ++ ++ for (p = multiarch_mappings; p->multiarch; p++) ++ { ++ if (!strcmp(p->multilib, imultilib ? imultilib : "")) ++ return p->multiarch; ++ } ++ return NULL; ++} ++ ++#endif /* GCC_MULTIARCH_H */ --- gcc-4.5-4.5.2.orig/debian/patches/pr45979.diff +++ gcc-4.5-4.5.2/debian/patches/pr45979.diff @@ -0,0 +1,11 @@ +--- a/src/gcc/config/host-linux.c ++++ b/src/gcc/config/host-linux.c +@@ -86,6 +86,8 @@ + # define TRY_EMPTY_VM_SPACE 0x60000000 + #elif defined(__mc68000__) + # define TRY_EMPTY_VM_SPACE 0x40000000 ++#elif defined(__ARM_EABI__) ++# define TRY_EMPTY_VM_SPACE 0xa0000000 + #else + # define TRY_EMPTY_VM_SPACE 0 + #endif --- gcc-4.5-4.5.2.orig/debian/patches/gcc-d-lang.diff +++ gcc-4.5-4.5.2/debian/patches/gcc-d-lang.diff @@ -0,0 +1,230 @@ +# DP: Add D options and specs for the gcc driver. + +--- + gcc/d/lang-specs.h | 53 +++++++++++++++++ + gcc/d/lang.opt | 160 ++++++++++++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 213 insertions(+), 0 deletions(-) + create mode 100644 gcc/d/lang-specs.h + create mode 100644 gcc/d/lang.opt + +new file mode 100644 +--- /dev/null ++++ b/src/gcc/d/lang-specs.h +@@ -0,0 +1,53 @@ ++/* GDC -- D front-end for GCC ++ Copyright (C) 2004 David Friedman ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 2 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++*/ ++ ++#ifndef D_D_SPEC ++#define D_D_SPEC 0 ++#endif ++ ++/* %{!M} probably doesn't make sense because we would need ++ to do that -- -MD and -MMD doesn't sound like a plan for D.... */ ++ ++/* %(d_options) ? */ ++ ++#if GCC_SPEC_FORMAT_4 ++#define D_D_SPEC_REST 0, 1, 0 ++#else ++#define D_D_SPEC_REST 0 ++#endif ++ ++#if D_DRIVER_ONLY ++{".html", "@d", D_D_SPEC_REST }, ++{".HTML", "@d", D_D_SPEC_REST }, ++{".htm", "@d", D_D_SPEC_REST }, ++{".HTM", "@d", D_D_SPEC_REST }, ++{".xhtml", "@d", D_D_SPEC_REST }, ++{".XHTML", "@d", D_D_SPEC_REST }, ++{".d", "@d", D_D_SPEC_REST }, ++{".D", "@d", D_D_SPEC_REST }, ++{"@d", ++ "%{!E:cc1d %i %:d-all-sources() %(cc1_options) %I %N %{nostdinc*} %{+e*} %{I*} %{J*}\ ++ %{M} %{MM} %{!fsyntax-only:%(invoke_as)}}", D_D_SPEC_REST }, ++#else ++{".d", "@d", D_D_SPEC_REST }, ++{".D", "@d", D_D_SPEC_REST }, ++{"@d", ++ "%{!E:cc1d %i %(cc1_options) %I %N %{nostdinc*} %{+e*} %{I*} %{J*}\ ++ %{M} %{MM} %{!fsyntax-only:%(invoke_as)}}", D_D_SPEC_REST }, ++#endif ++ +new file mode 100644 +--- /dev/null ++++ b/src/gcc/d/lang.opt +@@ -0,0 +1,160 @@ ++; GDC -- D front-end for GCC ++; Copyright (C) 2004 David Friedman ++; ++; This program is free software; you can redistribute it and/or modify ++; it under the terms of the GNU General Public License as published by ++; the Free Software Foundation; either version 2 of the License, or ++; (at your option) any later version. ++; ++; This program is distributed in the hope that it will be useful, ++; but WITHOUT ANY WARRANTY; without even the implied warranty of ++; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++; GNU General Public License for more details. ++; ++; You should have received a copy of the GNU General Public License ++; along with this program; if not, write to the Free Software ++; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ++; This is used in GCC 3.4+ ++ ++Language ++D ++ ++I ++D Joined Separate ++-I Add to the end of the main include path. ++ ++J ++D Joined Separate ++-J Add to the end of the string import path. ++ ++fdeprecated ++D ++Allow use of deprecated features ++ ++fassert ++D ++Generate runtime code for assert()'s ++ ++frelease ++D ++Compile release version ++ ++funittest ++D ++Compile in unittest code ++ ++fversion= ++D Joined RejectNegative ++-fversion= Compile in version code >= or identified by ++ ++fdebug= ++D Joined RejectNegative ++-fdebug,-fdebug=,-fdebug= Compile in debug code, code <= level, or code identified by ident ++ ++fdebug ++D ++Compile in debug code ++ ++fdebug-c ++D ++With -g, generate C debug information for debugger compatibility ++ ++fd-verbose ++D ++Print information about D language processing to stdout ++ ++fd-version=1 ++D RejectNegative ++Compile as D language version 1 ++ ++femit-templates= ++D Joined RejectNegative ++-femit-templates=[normal|private|all|none|auto] Control template emission ++ ++femit-templates ++D ++-femit-templates Emit templates code and data even if the linker cannot merge multiple copies ++ ++nostdinc ++D ++Do not search standard system include directories ++ ++fonly= ++D Joined RejectNegative ++Process all modules specified on the command line, but only generate code for the module specified by the argument. ++ ++fod= ++D Joined RejectNegative ++-fod= Specify the object output directory. Note: this is actually a driver option; the backend ignores it. ++ ++fop ++D ++Specify that the source file's parent directories should be appended to the object output directory. Note: this is actually a driver option; the backend ignores it. ++ ++fintfc ++Generate D interface files ++ ++fintfc-dir= ++D Joined RejectNegative ++-fintfc-dir= Write D interface files to directory ++ ++fintfc-file= ++D Joined RejectNegative ++-fintfc-file= Write D interface file to ++ ++fdoc ++D ++Generate documentation ++ ++fdoc-dir= ++D Joined RejectNegative ++-fdoc-dir= Write documentation file to docdir directory ++ ++fdoc-file= ++D Joined RejectNegative ++-fdoc-file= Write documentation file to filename ++ ++fdoc-inc= ++D Joined RejectNegative ++-fdoc-inc= Include a Ddoc macro file ++ ++fmultilib-dir= ++D Joined RejectNegative ++-fmultilib-dir= Select header multilib subdirectory ++ ++Wsign-compare ++D ++Warn about signed-unsigned comparisons ++ ++fdump-source ++D RejectNegative ++Dump decoded UTF-8 text and source from HTML ++ ++fbuiltin ++D ++Recognize built-in functions ++ ++funsigned-char ++D ++Make \"char\" unsigned by default (silently ignored in D) ++ ++fsigned-char ++D ++Make \"char\" signed by default (silently ignored in D) ++ ++iprefix ++D Joined Separate ++-iprefix Specify as a prefix for next two options ++ ++isysroot ++D Joined Separate ++-isysroot Set to be the system root directory ++ ++isystem ++D Joined Separate ++-isystem Add to the start of the system include path ++ ++Wall ++D ++Enable most warning messages --- gcc-4.5-4.5.2.orig/debian/patches/ibm-branch.diff +++ gcc-4.5-4.5.2/debian/patches/ibm-branch.diff @@ -0,0 +1,15829 @@ +# DP: updates from the ibm/4.5 branch upto 20110328 (r171599). + +svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_5-branch@171269 svn://gcc.gnu.org/svn/gcc/branches/ibm/gcc-4_5-branch \ + | sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \ + | awk '/^Index:.*\.(class|texi)/ {skip=1; next} /^Index:/ { skip=0 } skip==0' + +Index: gcc/tree-vrp.c +=================================================================== +--- a/src/gcc/tree-vrp.c (.../gcc-4_5-branch) ++++ b/src/gcc/tree-vrp.c (.../ibm/gcc-4_5-branch) +@@ -864,6 +864,8 @@ + gimple_assign_rhs1 (stmt), + gimple_assign_rhs2 (stmt), + strict_overflow_p); ++ case GIMPLE_TERNARY_RHS: ++ return false; + case GIMPLE_SINGLE_RHS: + return tree_single_nonnegative_warnv_p (gimple_assign_rhs1 (stmt), + strict_overflow_p); +@@ -938,6 +940,8 @@ + case GIMPLE_SINGLE_RHS: + return tree_single_nonzero_warnv_p (gimple_assign_rhs1 (stmt), + strict_overflow_p); ++ case GIMPLE_TERNARY_RHS: ++ return false; + case GIMPLE_INVALID_RHS: + gcc_unreachable (); + default: +Index: gcc/targhooks.h +=================================================================== +--- a/src/gcc/targhooks.h (.../gcc-4_5-branch) ++++ b/src/gcc/targhooks.h (.../ibm/gcc-4_5-branch) +@@ -132,3 +132,9 @@ + extern rtx default_addr_space_convert (rtx, tree, tree); + extern unsigned int default_case_values_threshold (void); + extern bool default_have_conditional_execution (void); ++ ++extern int default_label_align_after_barrier_max_skip (rtx); ++extern int default_loop_align_max_skip (rtx); ++extern int default_label_align_max_skip (rtx); ++extern int default_jump_align_max_skip (rtx); ++ +Index: gcc/flags.h +=================================================================== +--- a/src/gcc/flags.h (.../gcc-4_5-branch) ++++ b/src/gcc/flags.h (.../ibm/gcc-4_5-branch) +@@ -389,4 +389,12 @@ + /* Whether to emit an overflow warning whose code is C. */ + #define issue_strict_overflow_warning(c) (warn_strict_overflow >= (int) (c)) + ++/* Floating-point contraction mode. */ ++enum fp_contract_mode { ++ FP_CONTRACT_OFF = 0, ++ FP_CONTRACT_ON = 1, ++ FP_CONTRACT_FAST = 2 ++}; ++ ++extern enum fp_contract_mode flag_fp_contract_mode; + #endif /* ! GCC_FLAGS_H */ +Index: gcc/tree-pretty-print.c +=================================================================== +--- a/src/gcc/tree-pretty-print.c (.../gcc-4_5-branch) ++++ b/src/gcc/tree-pretty-print.c (.../ibm/gcc-4_5-branch) +@@ -1939,6 +1939,36 @@ + pp_string (buffer, " > "); + break; + ++ case WIDEN_MULT_PLUS_EXPR: ++ pp_string (buffer, " WIDEN_MULT_PLUS_EXPR < "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 2), spc, flags, false); ++ pp_string (buffer, " > "); ++ break; ++ ++ case WIDEN_MULT_MINUS_EXPR: ++ pp_string (buffer, " WIDEN_MULT_MINUS_EXPR < "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 2), spc, flags, false); ++ pp_string (buffer, " > "); ++ break; ++ ++ case FMA_EXPR: ++ pp_string (buffer, " FMA_EXPR < "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, TREE_OPERAND (node, 2), spc, flags, false); ++ pp_string (buffer, " > "); ++ break; ++ + case OMP_PARALLEL: + pp_string (buffer, "#pragma omp parallel"); + dump_omp_clauses (buffer, OMP_PARALLEL_CLAUSES (node), spc, flags); +@@ -2432,6 +2462,8 @@ + case VEC_WIDEN_MULT_LO_EXPR: + case WIDEN_MULT_EXPR: + case DOT_PROD_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: + case MULT_EXPR: + case TRUNC_DIV_EXPR: + case CEIL_DIV_EXPR: +@@ -2443,6 +2475,7 @@ + case CEIL_MOD_EXPR: + case FLOOR_MOD_EXPR: + case ROUND_MOD_EXPR: ++ case FMA_EXPR: + return 13; + + case TRUTH_NOT_EXPR: +Index: gcc/optabs.c +=================================================================== +--- a/src/gcc/optabs.c (.../gcc-4_5-branch) ++++ b/src/gcc/optabs.c (.../ibm/gcc-4_5-branch) +@@ -408,6 +408,23 @@ + case DOT_PROD_EXPR: + return TYPE_UNSIGNED (type) ? udot_prod_optab : sdot_prod_optab; + ++ case WIDEN_MULT_PLUS_EXPR: ++ return (TYPE_UNSIGNED (type) ++ ? (TYPE_SATURATING (type) ++ ? usmadd_widen_optab : umadd_widen_optab) ++ : (TYPE_SATURATING (type) ++ ? ssmadd_widen_optab : smadd_widen_optab)); ++ ++ case WIDEN_MULT_MINUS_EXPR: ++ return (TYPE_UNSIGNED (type) ++ ? (TYPE_SATURATING (type) ++ ? usmsub_widen_optab : umsub_widen_optab) ++ : (TYPE_SATURATING (type) ++ ? ssmsub_widen_optab : smsub_widen_optab)); ++ ++ case FMA_EXPR: ++ return fma_optab; ++ + case REDUC_MAX_EXPR: + return TYPE_UNSIGNED (type) ? reduc_umax_optab : reduc_smax_optab; + +@@ -547,7 +564,12 @@ + tmode0 = TYPE_MODE (TREE_TYPE (oprnd0)); + widen_pattern_optab = + optab_for_tree_code (ops->code, TREE_TYPE (oprnd0), optab_default); +- icode = (int) optab_handler (widen_pattern_optab, tmode0)->insn_code; ++ if (ops->code == WIDEN_MULT_PLUS_EXPR ++ || ops->code == WIDEN_MULT_MINUS_EXPR) ++ icode = (int) optab_handler (widen_pattern_optab, ++ TYPE_MODE (TREE_TYPE (ops->op2)))->insn_code; ++ else ++ icode = (int) optab_handler (widen_pattern_optab, tmode0)->insn_code; + gcc_assert (icode != CODE_FOR_nothing); + xmode0 = insn_data[icode].operand[1].mode; + +@@ -6268,6 +6290,10 @@ + init_optab (umax_optab, UMAX); + init_optab (pow_optab, UNKNOWN); + init_optab (atan2_optab, UNKNOWN); ++ init_optab (fma_optab, FMA); ++ init_optab (fms_optab, UNKNOWN); ++ init_optab (fnma_optab, UNKNOWN); ++ init_optab (fnms_optab, UNKNOWN); + + /* These three have codes assigned exclusively for the sake of + have_insn_for. */ +Index: gcc/optabs.h +=================================================================== +--- a/src/gcc/optabs.h (.../gcc-4_5-branch) ++++ b/src/gcc/optabs.h (.../ibm/gcc-4_5-branch) +@@ -191,6 +191,11 @@ + OTI_pow, + /* Arc tangent of y/x */ + OTI_atan2, ++ /* Floating multiply/add */ ++ OTI_fma, ++ OTI_fms, ++ OTI_fnma, ++ OTI_fnms, + + /* Move instruction. */ + OTI_mov, +@@ -435,6 +440,10 @@ + #define umax_optab (&optab_table[OTI_umax]) + #define pow_optab (&optab_table[OTI_pow]) + #define atan2_optab (&optab_table[OTI_atan2]) ++#define fma_optab (&optab_table[OTI_fma]) ++#define fms_optab (&optab_table[OTI_fms]) ++#define fnma_optab (&optab_table[OTI_fnma]) ++#define fnms_optab (&optab_table[OTI_fnms]) + + #define mov_optab (&optab_table[OTI_mov]) + #define movstrict_optab (&optab_table[OTI_movstrict]) +@@ -771,6 +780,9 @@ + /* Generate code for float to integral conversion. */ + extern bool expand_sfix_optab (rtx, rtx, convert_optab); + ++/* Generate code for a widening multiply. */ ++extern rtx expand_widening_mult (enum machine_mode, rtx, rtx, rtx, int, optab); ++ + /* Return tree if target supports vector operations for COND_EXPR. */ + bool expand_vec_cond_expr_p (tree, enum machine_mode); + +Index: gcc/genopinit.c +=================================================================== +--- a/src/gcc/genopinit.c (.../gcc-4_5-branch) ++++ b/src/gcc/genopinit.c (.../ibm/gcc-4_5-branch) +@@ -159,6 +159,10 @@ + "optab_handler (sqrt_optab, $A)->insn_code = CODE_FOR_$(sqrt$a2$)", + "optab_handler (floor_optab, $A)->insn_code = CODE_FOR_$(floor$a2$)", + "convert_optab_handler (lfloor_optab, $B, $A)->insn_code = CODE_FOR_$(lfloor$F$a$I$b2$)", ++ "optab_handler (fma_optab, $A)->insn_code = CODE_FOR_$(fma$a4$)", ++ "optab_handler (fms_optab, $A)->insn_code = CODE_FOR_$(fms$a4$)", ++ "optab_handler (fnma_optab, $A)->insn_code = CODE_FOR_$(fnma$a4$)", ++ "optab_handler (fnms_optab, $A)->insn_code = CODE_FOR_$(fnms$a4$)", + "optab_handler (ceil_optab, $A)->insn_code = CODE_FOR_$(ceil$a2$)", + "convert_optab_handler (lceil_optab, $B, $A)->insn_code = CODE_FOR_$(lceil$F$a$I$b2$)", + "optab_handler (round_optab, $A)->insn_code = CODE_FOR_$(round$a2$)", +Index: gcc/tree.c +=================================================================== +--- a/src/gcc/tree.c (.../gcc-4_5-branch) ++++ b/src/gcc/tree.c (.../ibm/gcc-4_5-branch) +@@ -6544,6 +6544,23 @@ + return false; + } + ++/* Return true if CODE represents a ternary tree code for which the ++ first two operands are commutative. Otherwise return false. */ ++bool ++commutative_ternary_tree_code (enum tree_code code) ++{ ++ switch (code) ++ { ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ return true; ++ ++ default: ++ break; ++ } ++ return false; ++} ++ + /* Generate a hash value for an expression. This can be used iteratively + by passing a previous result as the VAL argument. + +Index: gcc/tree.h +=================================================================== +--- a/src/gcc/tree.h (.../gcc-4_5-branch) ++++ b/src/gcc/tree.h (.../ibm/gcc-4_5-branch) +@@ -4687,6 +4687,7 @@ + extern int type_num_arguments (const_tree); + extern bool associative_tree_code (enum tree_code); + extern bool commutative_tree_code (enum tree_code); ++extern bool commutative_ternary_tree_code (enum tree_code); + extern tree upper_bound_in_type (tree, tree); + extern tree lower_bound_in_type (tree, tree); + extern int operand_equal_for_phi_arg_p (const_tree, const_tree); +@@ -4793,6 +4794,7 @@ + extern void fold_undefer_overflow_warnings (bool, const_gimple, int); + extern void fold_undefer_and_ignore_overflow_warnings (void); + extern bool fold_deferring_overflow_warnings_p (void); ++extern tree fold_fma (location_t, tree, tree, tree, tree); + + extern tree force_fit_type_double (tree, unsigned HOST_WIDE_INT, HOST_WIDE_INT, + int, bool); +Index: gcc/tree-pass.h +=================================================================== +--- a/src/gcc/tree-pass.h (.../gcc-4_5-branch) ++++ b/src/gcc/tree-pass.h (.../ibm/gcc-4_5-branch) +@@ -401,6 +401,7 @@ + extern struct gimple_opt_pass pass_expand_omp_ssa; + extern struct gimple_opt_pass pass_object_sizes; + extern struct gimple_opt_pass pass_fold_builtins; ++extern struct gimple_opt_pass pass_optimize_widening_mul; + extern struct gimple_opt_pass pass_stdarg; + extern struct gimple_opt_pass pass_early_warn_uninitialized; + extern struct gimple_opt_pass pass_late_warn_uninitialized; +Index: gcc/target.h +=================================================================== +--- a/src/gcc/target.h (.../gcc-4_5-branch) ++++ b/src/gcc/target.h (.../ibm/gcc-4_5-branch) +@@ -121,6 +121,18 @@ + const char *byte_op; + struct asm_int_op aligned_op, unaligned_op; + ++ /* The maximum number of bytes to skip when applying LABEL_ALIGN_AFTER_BARRIER. */ ++ int (* label_align_after_barrier_max_skip) (rtx label); ++ ++ /* The maximum number of bytes to skip when applying LOOP_ALIGN. */ ++ int (* loop_align_max_skip) (rtx label); ++ ++ /* The maximum number of bytes to skip when applying LABEL_ALIGN. */ ++ int (* label_align_max_skip) (rtx label); ++ ++ /* The maximum number of bytes to skip when applying JUMP_ALIGN. */ ++ int (* jump_align_max_skip) (rtx label); ++ + /* Try to output the assembler code for an integer object whose + value is given by X. SIZE is the size of the object in bytes and + ALIGNED_P indicates whether it is aligned. Return true if +Index: gcc/configure +=================================================================== +--- a/src/gcc/configure (.../gcc-4_5-branch) ++++ b/src/gcc/configure (.../ibm/gcc-4_5-branch) +@@ -24840,6 +24840,43 @@ + $as_echo "#define HAVE_LD_NO_DOT_SYMS 1" >>confdefs.h + + fi ++ ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking linker large toc support" >&5 ++$as_echo_n "checking linker large toc support... " >&6; } ++if test "${gcc_cv_ld_large_toc+set}" = set; then : ++ $as_echo_n "(cached) " >&6 ++else ++ gcc_cv_ld_large_toc=no ++ if test $in_tree_ld = yes ; then ++ if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 21 -o "$gcc_cv_gld_major_version" -gt 2; then ++ gcc_cv_ld_large_toc=yes ++ fi ++ elif test x$gcc_cv_as != x -a x$gcc_cv_ld != x ; then ++ cat > conftest.s < /dev/null 2>&1 \ ++ && $gcc_cv_ld -melf64ppc --no-toc-sort -o conftest conftest.o > /dev/null 2>&1; then ++ gcc_cv_ld_large_toc=yes ++ fi ++ rm -f conftest conftest.o conftest.s ++ fi ++ ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_ld_large_toc" >&5 ++$as_echo "$gcc_cv_ld_large_toc" >&6; } ++ if test x"$gcc_cv_ld_large_toc" = xyes; then ++ ++$as_echo "#define HAVE_LD_LARGE_TOC 1" >>confdefs.h ++ ++ fi + ;; + esac + +Index: gcc/final.c +=================================================================== +--- a/src/gcc/final.c (.../gcc-4_5-branch) ++++ b/src/gcc/final.c (.../ibm/gcc-4_5-branch) +@@ -68,6 +68,7 @@ + #include "intl.h" + #include "basic-block.h" + #include "target.h" ++#include "targhooks.h" + #include "debug.h" + #include "expr.h" + #include "cfglayout.h" +@@ -500,34 +501,42 @@ + #define LABEL_ALIGN(LABEL) align_labels_log + #endif + +-#ifndef LABEL_ALIGN_MAX_SKIP +-#define LABEL_ALIGN_MAX_SKIP align_labels_max_skip +-#endif +- + #ifndef LOOP_ALIGN + #define LOOP_ALIGN(LABEL) align_loops_log + #endif + +-#ifndef LOOP_ALIGN_MAX_SKIP +-#define LOOP_ALIGN_MAX_SKIP align_loops_max_skip +-#endif +- + #ifndef LABEL_ALIGN_AFTER_BARRIER + #define LABEL_ALIGN_AFTER_BARRIER(LABEL) 0 + #endif + +-#ifndef LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP +-#define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP 0 +-#endif +- + #ifndef JUMP_ALIGN + #define JUMP_ALIGN(LABEL) align_jumps_log + #endif + +-#ifndef JUMP_ALIGN_MAX_SKIP +-#define JUMP_ALIGN_MAX_SKIP align_jumps_max_skip +-#endif ++int ++default_label_align_after_barrier_max_skip (rtx insn ATTRIBUTE_UNUSED) ++{ ++ return 0; ++} + ++int ++default_loop_align_max_skip (rtx insn ATTRIBUTE_UNUSED) ++{ ++ return align_loops_max_skip; ++} ++ ++int ++default_label_align_max_skip (rtx insn ATTRIBUTE_UNUSED) ++{ ++ return align_labels_max_skip; ++} ++ ++int ++default_jump_align_max_skip (rtx insn ATTRIBUTE_UNUSED) ++{ ++ return align_jumps_max_skip; ++} ++ + #ifndef ADDR_VEC_ALIGN + static int + final_addr_vec_align (rtx addr_vec) +@@ -709,8 +718,8 @@ + { + dump_flow_info (dump_file, TDF_DETAILS); + flow_loops_dump (dump_file, NULL, 1); +- loop_optimizer_init (AVOID_CFG_MODIFICATIONS); + } ++ loop_optimizer_init (AVOID_CFG_MODIFICATIONS); + FOR_EACH_BB (bb) + if (bb->frequency > freq_max) + freq_max = bb->frequency; +@@ -734,7 +743,7 @@ + continue; + } + max_log = LABEL_ALIGN (label); +- max_skip = LABEL_ALIGN_MAX_SKIP; ++ max_skip = targetm.asm_out.label_align_max_skip (label); + + FOR_EACH_EDGE (e, ei, bb->preds) + { +@@ -778,7 +787,7 @@ + if (max_log < log) + { + max_log = log; +- max_skip = JUMP_ALIGN_MAX_SKIP; ++ max_skip = targetm.asm_out.jump_align_max_skip (label); + } + } + /* In case block is frequent and reached mostly by non-fallthru edge, +@@ -795,18 +804,15 @@ + if (max_log < log) + { + max_log = log; +- max_skip = LOOP_ALIGN_MAX_SKIP; ++ max_skip = targetm.asm_out.loop_align_max_skip (label); + } + } + LABEL_TO_ALIGNMENT (label) = max_log; + LABEL_TO_MAX_SKIP (label) = max_skip; + } + +- if (dump_file) +- { +- loop_optimizer_finalize (); +- free_dominance_info (CDI_DOMINATORS); +- } ++ loop_optimizer_finalize (); ++ free_dominance_info (CDI_DOMINATORS); + return 0; + } + +@@ -928,7 +934,7 @@ + if (max_log < log) + { + max_log = log; +- max_skip = LABEL_ALIGN_MAX_SKIP; ++ max_skip = targetm.asm_out.label_align_max_skip (insn); + } + } + /* ADDR_VECs only take room if read-only data goes into the text +@@ -941,7 +947,7 @@ + if (max_log < log) + { + max_log = log; +- max_skip = LABEL_ALIGN_MAX_SKIP; ++ max_skip = targetm.asm_out.label_align_max_skip (insn); + } + } + LABEL_TO_ALIGNMENT (insn) = max_log; +@@ -961,7 +967,7 @@ + if (max_log < log) + { + max_log = log; +- max_skip = LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP; ++ max_skip = targetm.asm_out.label_align_after_barrier_max_skip (label); + } + break; + } +Index: gcc/builtins.c +=================================================================== +--- a/src/gcc/builtins.c (.../gcc-4_5-branch) ++++ b/src/gcc/builtins.c (.../ibm/gcc-4_5-branch) +@@ -100,6 +100,7 @@ + static rtx expand_builtin_mathfn (tree, rtx, rtx); + static rtx expand_builtin_mathfn_2 (tree, rtx, rtx); + static rtx expand_builtin_mathfn_3 (tree, rtx, rtx); ++static rtx expand_builtin_mathfn_ternary (tree, rtx, rtx); + static rtx expand_builtin_interclass_mathfn (tree, rtx); + static rtx expand_builtin_sincos (tree); + static rtx expand_builtin_cexpi (tree, rtx); +@@ -2138,6 +2139,79 @@ + return target; + } + ++/* Expand a call to the builtin trinary math functions (fma). ++ Return NULL_RTX if a normal call should be emitted rather than expanding the ++ function in-line. EXP is the expression that is a call to the builtin ++ function; if convenient, the result should be placed in TARGET. ++ SUBTARGET may be used as the target for computing one of EXP's ++ operands. */ ++ ++static rtx ++expand_builtin_mathfn_ternary (tree exp, rtx target, rtx subtarget) ++{ ++ optab builtin_optab; ++ rtx op0, op1, op2, insns; ++ tree fndecl = get_callee_fndecl (exp); ++ tree arg0, arg1, arg2; ++ enum machine_mode mode; ++ ++ if (!validate_arglist (exp, REAL_TYPE, REAL_TYPE, REAL_TYPE, VOID_TYPE)) ++ return NULL_RTX; ++ ++ arg0 = CALL_EXPR_ARG (exp, 0); ++ arg1 = CALL_EXPR_ARG (exp, 1); ++ arg2 = CALL_EXPR_ARG (exp, 2); ++ ++ switch (DECL_FUNCTION_CODE (fndecl)) ++ { ++ CASE_FLT_FN (BUILT_IN_FMA): ++ builtin_optab = fma_optab; break; ++ default: ++ gcc_unreachable (); ++ } ++ ++ /* Make a suitable register to place result in. */ ++ mode = TYPE_MODE (TREE_TYPE (exp)); ++ ++ /* Before working hard, check whether the instruction is available. */ ++ if (optab_handler (builtin_optab, mode)->insn_code == CODE_FOR_nothing) ++ return NULL_RTX; ++ ++ target = gen_reg_rtx (mode); ++ ++ /* Always stabilize the argument list. */ ++ CALL_EXPR_ARG (exp, 0) = arg0 = builtin_save_expr (arg0); ++ CALL_EXPR_ARG (exp, 1) = arg1 = builtin_save_expr (arg1); ++ CALL_EXPR_ARG (exp, 2) = arg2 = builtin_save_expr (arg2); ++ ++ op0 = expand_expr (arg0, subtarget, VOIDmode, EXPAND_NORMAL); ++ op1 = expand_normal (arg1); ++ op2 = expand_normal (arg2); ++ ++ start_sequence (); ++ ++ /* Compute into TARGET. ++ Set TARGET to wherever the result comes back. */ ++ target = expand_ternary_op (mode, builtin_optab, op0, op1, op2, ++ target, 0); ++ ++ /* If we were unable to expand via the builtin, stop the sequence ++ (without outputting the insns) and call to the library function ++ with the stabilized argument list. */ ++ if (target == 0) ++ { ++ end_sequence (); ++ return expand_call (exp, target, target == const0_rtx); ++ } ++ ++ /* Output the entire sequence. */ ++ insns = get_insns (); ++ end_sequence (); ++ emit_insn (insns); ++ ++ return target; ++} ++ + /* Expand a call to the builtin sin and cos math functions. + Return NULL_RTX if a normal call should be emitted rather than expanding the + function in-line. EXP is the expression that is a call to the builtin +@@ -2919,6 +2993,99 @@ + return result; + } + ++/* Fold a builtin function call to pow, powf, or powl into a series of sqrts or ++ cbrts. Return NULL_RTX if no simplification can be made or expand the tree ++ if we can simplify it. */ ++static rtx ++expand_builtin_pow_root (location_t loc, tree arg0, tree arg1, tree type, ++ rtx subtarget) ++{ ++ if (TREE_CODE (arg1) == REAL_CST ++ && !TREE_OVERFLOW (arg1) ++ && flag_unsafe_math_optimizations) ++ { ++ enum machine_mode mode = TYPE_MODE (type); ++ tree sqrtfn = mathfn_built_in (type, BUILT_IN_SQRT); ++ tree cbrtfn = mathfn_built_in (type, BUILT_IN_CBRT); ++ REAL_VALUE_TYPE c = TREE_REAL_CST (arg1); ++ tree op = NULL_TREE; ++ ++ if (sqrtfn) ++ { ++ /* Optimize pow (x, 0.5) into sqrt. */ ++ if (REAL_VALUES_EQUAL (c, dconsthalf)) ++ op = build_call_nofold_loc (loc, sqrtfn, 1, arg0); ++ ++ /* Don't do this optimization if we don't have a sqrt insn. */ ++ else if (optab_handler (sqrt_optab, mode)->insn_code ++ != CODE_FOR_nothing) ++ { ++ REAL_VALUE_TYPE dconst1_4 = dconst1; ++ REAL_VALUE_TYPE dconst3_4; ++ SET_REAL_EXP (&dconst1_4, REAL_EXP (&dconst1_4) - 2); ++ ++ real_from_integer (&dconst3_4, VOIDmode, 3, 0, 0); ++ SET_REAL_EXP (&dconst3_4, REAL_EXP (&dconst3_4) - 2); ++ ++ /* Optimize pow (x, 0.25) into sqrt (sqrt (x)). Assume on most ++ machines that a builtin sqrt instruction is smaller than a ++ call to pow with 0.25, so do this optimization even if ++ -Os. */ ++ if (REAL_VALUES_EQUAL (c, dconst1_4)) ++ { ++ op = build_call_nofold_loc (loc, sqrtfn, 1, arg0); ++ op = build_call_nofold_loc (loc, sqrtfn, 1, op); ++ } ++ ++ /* Optimize pow (x, 0.75) = sqrt (x) * sqrt (sqrt (x)) unless we ++ are optimizing for space. */ ++ else if (optimize_insn_for_speed_p () ++ && !TREE_SIDE_EFFECTS (arg0) ++ && REAL_VALUES_EQUAL (c, dconst3_4)) ++ { ++ tree sqrt1 = build_call_expr_loc (loc, sqrtfn, 1, arg0); ++ tree sqrt2 = builtin_save_expr (sqrt1); ++ tree sqrt3 = build_call_expr_loc (loc, sqrtfn, 1, sqrt1); ++ op = fold_build2_loc (loc, MULT_EXPR, type, sqrt2, sqrt3); ++ } ++ } ++ } ++ ++ /* Check whether we can do cbrt insstead of pow (x, 1./3.) and ++ cbrt/sqrts instead of pow (x, 1./6.). */ ++ if (cbrtfn && ! op ++ && (tree_expr_nonnegative_p (arg0) || !HONOR_NANS (mode))) ++ { ++ /* First try 1/3. */ ++ REAL_VALUE_TYPE dconst1_3 ++ = real_value_truncate (mode, dconst_third ()); ++ ++ if (REAL_VALUES_EQUAL (c, dconst1_3)) ++ op = build_call_nofold_loc (loc, cbrtfn, 1, arg0); ++ ++ /* Now try 1/6. */ ++ else if (optimize_insn_for_speed_p () ++ && (optab_handler (sqrt_optab, mode)->insn_code ++ != CODE_FOR_nothing)) ++ { ++ REAL_VALUE_TYPE dconst1_6 = dconst1_3; ++ SET_REAL_EXP (&dconst1_6, REAL_EXP (&dconst1_6) - 1); ++ ++ if (REAL_VALUES_EQUAL (c, dconst1_6)) ++ { ++ op = build_call_nofold_loc (loc, sqrtfn, 1, arg0); ++ op = build_call_nofold_loc (loc, cbrtfn, 1, op); ++ } ++ } ++ } ++ ++ if (op) ++ return expand_expr (op, subtarget, mode, EXPAND_NORMAL); ++ } ++ ++ return NULL_RTX; ++} ++ + /* Expand a call to the pow built-in mathematical function. Return NULL_RTX if + a normal call should be emitted rather than expanding the function + in-line. EXP is the expression that is a call to the builtin +@@ -3014,6 +3181,13 @@ + } + } + ++ /* Check whether we can do a series of sqrt or cbrt's instead of the pow ++ call. */ ++ op = expand_builtin_pow_root (EXPR_LOCATION (exp), arg0, arg1, type, ++ subtarget); ++ if (op) ++ return op; ++ + /* Try if the exponent is a third of an integer. In this case + we can expand to x**(n/3) * cbrt(x)**(n%3). As cbrt (x) is + different from pow (x, 1./3.) due to rounding and behavior +@@ -5716,6 +5890,12 @@ + return target; + break; + ++ CASE_FLT_FN (BUILT_IN_FMA): ++ target = expand_builtin_mathfn_ternary (exp, target, subtarget); ++ if (target) ++ return target; ++ break; ++ + CASE_FLT_FN (BUILT_IN_ILOGB): + if (! flag_unsafe_math_optimizations) + break; +@@ -9004,6 +9184,41 @@ + return fold_build1_loc (loc, ABS_EXPR, type, arg); + } + ++/* Fold a fma operation with arguments ARG[012]. */ ++ ++tree ++fold_fma (location_t loc ATTRIBUTE_UNUSED, ++ tree type, tree arg0, tree arg1, tree arg2) ++{ ++ if (TREE_CODE (arg0) == REAL_CST ++ && TREE_CODE (arg1) == REAL_CST ++ && TREE_CODE (arg2) == REAL_CST) ++ return do_mpfr_arg3 (arg0, arg1, arg2, type, mpfr_fma); ++ ++ return NULL_TREE; ++} ++ ++/* Fold a call to fma, fmaf, or fmal with arguments ARG[012]. */ ++ ++static tree ++fold_builtin_fma (location_t loc, tree arg0, tree arg1, tree arg2, tree type) ++{ ++ if (validate_arg (arg0, REAL_TYPE) ++ && validate_arg(arg1, REAL_TYPE) ++ && validate_arg(arg2, REAL_TYPE)) ++ { ++ tree tem = fold_fma (loc, type, arg0, arg1, arg2); ++ if (tem) ++ return tem; ++ ++ /* ??? Only expand to FMA_EXPR if it's directly supported. */ ++ if (optab_handler (fma_optab, TYPE_MODE (type))->insn_code ++ != CODE_FOR_nothing) ++ return fold_build3_loc (loc, FMA_EXPR, type, arg0, arg1, arg2); ++ } ++ return NULL_TREE; ++} ++ + /* Fold a call to builtin fmin or fmax. */ + + static tree +@@ -10271,10 +10486,7 @@ + return fold_builtin_sincos (loc, arg0, arg1, arg2); + + CASE_FLT_FN (BUILT_IN_FMA): +- if (validate_arg (arg0, REAL_TYPE) +- && validate_arg(arg1, REAL_TYPE) +- && validate_arg(arg2, REAL_TYPE)) +- return do_mpfr_arg3 (arg0, arg1, arg2, type, mpfr_fma); ++ return fold_builtin_fma (loc, arg0, arg1, arg2, type); + break; + + CASE_FLT_FN (BUILT_IN_REMQUO): +Index: gcc/fold-const.c +=================================================================== +--- a/src/gcc/fold-const.c (.../gcc-4_5-branch) ++++ b/src/gcc/fold-const.c (.../ibm/gcc-4_5-branch) +@@ -3405,6 +3405,14 @@ + case TRUTH_ORIF_EXPR: + return OP_SAME (0) && OP_SAME (1); + ++ case FMA_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ if (!OP_SAME (2)) ++ return 0; ++ /* The multiplcation operands are commutative. */ ++ /* FALLTHRU */ ++ + case TRUTH_AND_EXPR: + case TRUTH_OR_EXPR: + case TRUTH_XOR_EXPR: +@@ -3418,6 +3426,8 @@ + TREE_OPERAND (arg1, 0), flags)); + + case COND_EXPR: ++ case VEC_COND_EXPR: ++ case DOT_PROD_EXPR: + return OP_SAME (0) && OP_SAME (1) && OP_SAME (2); + + default: +@@ -13740,10 +13750,10 @@ + + tree + fold_ternary_loc (location_t loc, enum tree_code code, tree type, +- tree op0, tree op1, tree op2) ++ tree op0, tree op1, tree op2) + { + tree tem; +- tree arg0 = NULL_TREE, arg1 = NULL_TREE; ++ tree arg0 = NULL_TREE, arg1 = NULL_TREE, arg2 = NULL_TREE; + enum tree_code_class kind = TREE_CODE_CLASS (code); + + gcc_assert (IS_EXPR_CODE_CLASS (kind) +@@ -13771,6 +13781,12 @@ + STRIP_NOPS (arg1); + } + ++ if (op2) ++ { ++ arg2 = op2; ++ STRIP_NOPS (arg2); ++ } ++ + switch (code) + { + case COMPONENT_REF: +@@ -14069,6 +14085,17 @@ + + return NULL_TREE; + ++ case FMA_EXPR: ++ /* For integers we can decompose the FMA if possible. */ ++ if (TREE_CODE (arg0) == INTEGER_CST ++ && TREE_CODE (arg1) == INTEGER_CST) ++ return fold_build2_loc (loc, PLUS_EXPR, type, ++ const_binop (MULT_EXPR, arg0, arg1, 0), arg2); ++ if (integer_zerop (arg2)) ++ return fold_build2_loc (loc, MULT_EXPR, type, arg0, arg1); ++ ++ return fold_fma (loc, type, arg0, arg1, arg2); ++ + default: + return NULL_TREE; + } /* switch (code) */ +Index: gcc/c-cppbuiltin.c +=================================================================== +--- a/src/gcc/c-cppbuiltin.c (.../gcc-4_5-branch) ++++ b/src/gcc/c-cppbuiltin.c (.../ibm/gcc-4_5-branch) +@@ -63,9 +63,47 @@ + static void builtin_define_float_constants (const char *, + const char *, + const char *, ++ const char *, + tree); + static void define__GNUC__ (void); + ++/* Return true if MODE provides a fast multiply/add (FMA) builtin function. ++ Originally this function used the fma optab, but that doesn't work with ++ -save-temps, so just rely on the HAVE_fma macros for the standard floating ++ point types. */ ++ ++static bool ++mode_has_fma (enum machine_mode mode) ++{ ++ switch (mode) ++ { ++#ifdef HAVE_fmasf4 ++ case SFmode: ++ return !!HAVE_fmasf4; ++#endif ++ ++#ifdef HAVE_fmadf4 ++ case DFmode: ++ return !!HAVE_fmadf4; ++#endif ++ ++#ifdef HAVE_fmaxf4 ++ case XFmode: ++ return !!HAVE_fmaxf4; ++#endif ++ ++#ifdef HAVE_fmatf4 ++ case TFmode: ++ return !!HAVE_fmatf4; ++#endif ++ ++ default: ++ break; ++ } ++ ++ return false; ++} ++ + /* Define NAME with value TYPE precision. */ + static void + builtin_define_type_precision (const char *name, tree type) +@@ -87,6 +125,7 @@ + builtin_define_float_constants (const char *name_prefix, + const char *fp_suffix, + const char *fp_cast, ++ const char *fma_suffix, + tree type) + { + /* Used to convert radix-based values to base 10 values in several cases. +@@ -256,6 +295,13 @@ + NaN has quiet NaNs. */ + sprintf (name, "__%s_HAS_QUIET_NAN__", name_prefix); + builtin_define_with_int_value (name, MODE_HAS_NANS (TYPE_MODE (type))); ++ ++ /* Note whether we have fast FMA. */ ++ if (mode_has_fma (TYPE_MODE (type))) ++ { ++ sprintf (name, "__FP_FAST_FMA%s", fma_suffix); ++ builtin_define_with_int_value (name, 1); ++ } + } + + /* Define __DECx__ constants for TYPE using NAME_PREFIX and SUFFIX. */ +@@ -618,13 +664,15 @@ + builtin_define_with_int_value ("__DEC_EVAL_METHOD__", + TARGET_DEC_EVAL_METHOD); + +- builtin_define_float_constants ("FLT", "F", "%s", float_type_node); ++ builtin_define_float_constants ("FLT", "F", "%s", "F", float_type_node); + /* Cast the double precision constants. This is needed when single + precision constants are specified or when pragma FLOAT_CONST_DECIMAL64 + is used. The correct result is computed by the compiler when using + macros that include a cast. */ +- builtin_define_float_constants ("DBL", "L", "((double)%s)", double_type_node); +- builtin_define_float_constants ("LDBL", "L", "%s", long_double_type_node); ++ builtin_define_float_constants ("DBL", "L", "((double)%s)", "", ++ double_type_node); ++ builtin_define_float_constants ("LDBL", "L", "%s", "L", ++ long_double_type_node); + + /* For decfloat.h. */ + builtin_define_decimal_float_constants ("DEC32", "DF", dfloat32_type_node); +Index: gcc/tree-ssa-sccvn.c +=================================================================== +--- a/src/gcc/tree-ssa-sccvn.c (.../gcc-4_5-branch) ++++ b/src/gcc/tree-ssa-sccvn.c (.../ibm/gcc-4_5-branch) +@@ -2286,6 +2286,10 @@ + case GIMPLE_BINARY_RHS: + return (is_gimple_min_invariant (gimple_assign_rhs1 (stmt)) + || is_gimple_min_invariant (gimple_assign_rhs2 (stmt))); ++ case GIMPLE_TERNARY_RHS: ++ return (is_gimple_min_invariant (gimple_assign_rhs1 (stmt)) ++ || is_gimple_min_invariant (gimple_assign_rhs2 (stmt)) ++ || is_gimple_min_invariant (gimple_assign_rhs3 (stmt))); + case GIMPLE_SINGLE_RHS: + /* Constants inside reference ops are rarely interesting, but + it can take a lot of looking to find them. */ +Index: gcc/ChangeLog +=================================================================== +--- a/src/gcc/ChangeLog (.../gcc-4_5-branch) ++++ b/src/gcc/ChangeLog (.../ibm/gcc-4_5-branch) +@@ -92,6 +92,12 @@ + * doc/cfg.texi: Remove "See" before @ref. + * doc/invoke.texi: Likewise. + ++2011-03-05 Alan Modra ++ ++ PR target/47986 ++ * config/rs6000/rs6000.c (rs6000_delegitimize_address): Handle ++ full cmodel medium/large lo_sum + high addresses. ++ + 2011-03-03 Uros Bizjak + + * config/i386/sse.md (*avx_pmaddubsw128): Fix mode of VEC_SELECT RTX. +Index: gcc/testsuite/gcc.c-torture/compile/pr44707.c +=================================================================== +--- a/src/gcc/testsuite/gcc.c-torture/compile/pr44707.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr44707.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,14 @@ ++extern struct { int a, b, c, d; } v; ++extern int w; ++ ++void ++foo (void) ++{ ++ int e1 = v.a; ++ int e2 = w; ++ int e3 = v.b; ++ int e4 = v.c; ++ int e5 = v.d; ++ __asm__ volatile ("/* %0 %1 %2 %3 %4 */" : : "nro" (e1), "nro" (e2), "nro" (e3), "nro" (e4), "nro" (e5)); ++} ++ +Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,22 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target ilp32 } */ ++/* { dg-options "-O3 -mcpu=power5 -ffast-math" } */ ++/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ ++/* { dg-final { scan-assembler-not "fctiwuz" } } */ ++/* { dg-final { scan-assembler-times "fctidz" 8 } } */ ++/* { dg-final { scan-assembler-not "fctiduz" } } */ ++/* { dg-final { scan-assembler-not "xscvdpsxds" } } */ ++/* { dg-final { scan-assembler-not "xscvdpuxds" } } */ ++ ++void float_to_int (int *dest, float src) { *dest = (int) src; } ++void double_to_int (int *dest, double src) { *dest = (int) src; } ++ ++void float_to_uint (int *dest, float src) { *dest = (unsigned int) src; } ++void double_to_uint (int *dest, double src) { *dest = (unsigned int) src; } ++ ++void float_to_llong (long long *dest, float src) { *dest = (long long) src; } ++void double_to_llong (long long *dest, double src) { *dest = (long long) src; } ++ ++void float_to_ullong (unsigned long long *dest, float src) { *dest = (unsigned long long) src; } ++void double_to_ullong (unsigned long long *dest, double src) { *dest = (unsigned long long) src; } +Index: gcc/testsuite/gcc.target/powerpc/recip-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-1.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-1.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,18 @@ ++/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ ++/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power6" } */ ++/* { dg-final { scan-assembler-times "frsqrte" 2 } } */ ++/* { dg-final { scan-assembler-times "fmsub" 2 } } */ ++/* { dg-final { scan-assembler-times "fmul" 8 } } */ ++/* { dg-final { scan-assembler-times "fnmsub" 4 } } */ ++ ++double ++rsqrt_d (double a) ++{ ++ return 1.0 / __builtin_sqrt (a); ++} ++ ++float ++rsqrt_f (float a) ++{ ++ return 1.0f / __builtin_sqrtf (a); ++} +Index: gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,183 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math -ffp-contract=off" } */ ++/* { dg-final { scan-assembler-times "xvmadd" 2 } } */ ++/* { dg-final { scan-assembler-times "xsmadd" 1 } } */ ++/* { dg-final { scan-assembler-times "fmadds" 1 } } */ ++/* { dg-final { scan-assembler-times "xvmsub" 2 } } */ ++/* { dg-final { scan-assembler-times "xsmsub" 1 } } */ ++/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ ++/* { dg-final { scan-assembler-times "xvnmadd" 2 } } */ ++/* { dg-final { scan-assembler-times "xsnmadd" 1 } } */ ++/* { dg-final { scan-assembler-times "fnmadds" 1 } } */ ++/* { dg-final { scan-assembler-times "xvnmsub" 2 } } */ ++/* { dg-final { scan-assembler-times "xsnmsub" 1 } } */ ++/* { dg-final { scan-assembler-times "fnmsubs" 1 } } */ ++ ++/* Only the functions calling the bulitin should generate an appropriate (a * ++ b) + c instruction. */ ++ ++double ++builtin_fma (double b, double c, double d) ++{ ++ return __builtin_fma (b, c, d); /* xsmadd{a,m}dp */ ++} ++ ++double ++builtin_fms (double b, double c, double d) ++{ ++ return __builtin_fma (b, c, -d); /* xsmsub{a,b}dp */ ++} ++ ++double ++builtin_fnma (double b, double c, double d) ++{ ++ return - __builtin_fma (b, c, d); /* xsnmadd{a,b}dp */ ++} ++ ++double ++builtin_fnms (double b, double c, double d) ++{ ++ return - __builtin_fma (b, c, -d); /* xsnmsub{a,b}dp */ ++} ++ ++float ++builtin_fmaf (float b, float c, float d) ++{ ++ return __builtin_fmaf (b, c, d); /* fmadds */ ++} ++ ++float ++builtin_fmsf (float b, float c, float d) ++{ ++ return __builtin_fmaf (b, c, -d); /* fmsubs */ ++} ++ ++float ++builtin_fnmaf (float b, float c, float d) ++{ ++ return - __builtin_fmaf (b, c, d); /* fnmadds */ ++} ++ ++float ++builtin_fnmsf (float b, float c, float d) ++{ ++ return - __builtin_fmaf (b, c, -d); /* fnmsubs */ ++} ++ ++double ++normal_fma (double b, double c, double d) ++{ ++ return (b * c) + d; /* fmul/fadd */ ++} ++ ++float ++normal_fmaf (float b, float c, float d) ++{ ++ return (b * c) + d; /* fmuls/fadds */ ++} ++ ++#ifndef SIZE ++#define SIZE 1024 ++#endif ++ ++double vda[SIZE] __attribute__((__aligned__(32))); ++double vdb[SIZE] __attribute__((__aligned__(32))); ++double vdc[SIZE] __attribute__((__aligned__(32))); ++double vdd[SIZE] __attribute__((__aligned__(32))); ++ ++float vfa[SIZE] __attribute__((__aligned__(32))); ++float vfb[SIZE] __attribute__((__aligned__(32))); ++float vfc[SIZE] __attribute__((__aligned__(32))); ++float vfd[SIZE] __attribute__((__aligned__(32))); ++ ++void ++vector_fma (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vda[i] = __builtin_fma (vdb[i], vdc[i], vdd[i]); /* xvmadd{a,m}dp */ ++} ++ ++void ++vector_fms (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vda[i] = __builtin_fma (vdb[i], vdc[i], -vdd[i]); /* xvmsub{a,m}dp */ ++} ++ ++void ++vector_fnma (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vda[i] = - __builtin_fma (vdb[i], vdc[i], vdd[i]); /* xvnmadd{a,m}dp */ ++} ++ ++void ++vector_fnms (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vda[i] = - __builtin_fma (vdb[i], vdc[i], -vdd[i]); /* xvnmsub{a,m}dp */ ++} ++ ++void ++vector_fmaf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]); /* xvmadd{a,m}sp */ ++} ++ ++void ++vector_fmsf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = __builtin_fmaf (vfb[i], vfc[i], -vfd[i]); /* xvmsub{a,m}sp */ ++} ++ ++void ++vector_fnmaf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = - __builtin_fmaf (vfb[i], vfc[i], vfd[i]); /* xvnmadd{a,m}sp */ ++} ++ ++void ++vector_fnmsf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = - __builtin_fmaf (vfb[i], vfc[i], -vfd[i]); /* xvnmsub{a,m}sp */ ++} ++ ++void ++vnormal_fma (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vda[i] = (vdb[i] * vdc[i]) + vdd[i]; /* xvmadd{a,m}dp */ ++} ++ ++void ++vnormal_fmaf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = (vfb[i] * vfc[i]) + vfd[i]; /* xvmadd{a,m}sp */ ++} +Index: gcc/testsuite/gcc.target/powerpc/altivec-types-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c (.../ibm/gcc-4_5-branch) +@@ -1,7 +1,7 @@ + /* { dg-do compile { target powerpc*-*-linux* } } */ + /* { dg-require-effective-target ilp32 } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-maltivec" } */ ++/* { dg-options "-maltivec -mno-vsx" } */ + + /* These should get warnings for 32-bit code. */ + +Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,10 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-options "-O2 -mcpu=power5+ -ffast-math" } */ ++/* { dg-final { scan-assembler-not "xsrdpiz" } } */ ++/* { dg-final { scan-assembler "friz" } } */ ++ ++double round_double_llong (double a) ++{ ++ return (double)(long long)a; ++} +Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,22 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target ilp32 } */ ++/* { dg-options "-O3 -mcpu=750 -ffast-math" } */ ++/* { dg-final { scan-assembler-times "fctiwz" 6 } } */ ++/* { dg-final { scan-assembler-not "fctiwuz" } } */ ++/* { dg-final { scan-assembler-not "fctidz" } } */ ++/* { dg-final { scan-assembler-not "fctiduz" } } */ ++/* { dg-final { scan-assembler-not "xscvdpsxds" } } */ ++/* { dg-final { scan-assembler-not "xscvdpuxds" } } */ ++ ++void float_to_int (int *dest, float src) { *dest = (int) src; } ++void double_to_int (int *dest, double src) { *dest = (int) src; } ++ ++void float_to_uint (int *dest, float src) { *dest = (unsigned int) src; } ++void double_to_uint (int *dest, double src) { *dest = (unsigned int) src; } ++ ++void float_to_llong (long long *dest, float src) { *dest = (long long) src; } ++void double_to_llong (long long *dest, double src) { *dest = (long long) src; } ++ ++void float_to_ullong (unsigned long long *dest, float src) { *dest = (unsigned long long) src; } ++void double_to_ullong (unsigned long long *dest, double src) { *dest = (unsigned long long) src; } +Index: gcc/testsuite/gcc.target/powerpc/recip-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-2.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-2.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,21 @@ ++/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ ++/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power5" } */ ++/* { dg-final { scan-assembler-times "frsqrtes" 1 } } */ ++/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ ++/* { dg-final { scan-assembler-times "fmuls" 6 } } */ ++/* { dg-final { scan-assembler-times "fnmsubs" 3 } } */ ++/* { dg-final { scan-assembler-times "fsqrt" 1 } } */ ++ ++/* power5 resqrte is not accurate enough, and should not be generated by ++ default for -mrecip. */ ++double ++rsqrt_d (double a) ++{ ++ return 1.0 / __builtin_sqrt (a); ++} ++ ++float ++rsqrt_f (float a) ++{ ++ return 1.0f / __builtin_sqrtf (a); ++} +Index: gcc/testsuite/gcc.target/powerpc/altivec-14.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-14.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-14.c (.../ibm/gcc-4_5-branch) +@@ -1,6 +1,6 @@ + /* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-maltivec" } */ ++/* { dg-options "-maltivec -mno-vsx" } */ + + #include + +Index: gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,103 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-options "-O3 -ftree-vectorize -mcpu=power6 -maltivec -ffast-math" } */ ++/* { dg-final { scan-assembler-times "vmaddfp" 2 } } */ ++/* { dg-final { scan-assembler-times "fmadd " 2 } } */ ++/* { dg-final { scan-assembler-times "fmadds" 2 } } */ ++/* { dg-final { scan-assembler-times "fmsub " 1 } } */ ++/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ ++/* { dg-final { scan-assembler-times "fnmadd " 1 } } */ ++/* { dg-final { scan-assembler-times "fnmadds" 1 } } */ ++/* { dg-final { scan-assembler-times "fnmsub " 1 } } */ ++/* { dg-final { scan-assembler-times "fnmsubs" 1 } } */ ++ ++/* All functions should generate an appropriate (a * b) + c instruction ++ since -mfused-madd is on by default. */ ++ ++double ++builtin_fma (double b, double c, double d) ++{ ++ return __builtin_fma (b, c, d); /* fmadd */ ++} ++ ++double ++builtin_fms (double b, double c, double d) ++{ ++ return __builtin_fma (b, c, -d); /* fmsub */ ++} ++ ++double ++builtin_fnma (double b, double c, double d) ++{ ++ return - __builtin_fma (b, c, d); /* fnmadd */ ++} ++ ++double ++builtin_fnms (double b, double c, double d) ++{ ++ return - __builtin_fma (b, c, -d); /* fnmsub */ ++} ++ ++float ++builtin_fmaf (float b, float c, float d) ++{ ++ return __builtin_fmaf (b, c, d); /* fmadds */ ++} ++ ++float ++builtin_fmsf (float b, float c, float d) ++{ ++ return __builtin_fmaf (b, c, -d); /* fmsubs */ ++} ++ ++float ++builtin_fnmaf (float b, float c, float d) ++{ ++ return - __builtin_fmaf (b, c, d); /* fnmadds */ ++} ++ ++float ++builtin_fnmsf (float b, float c, float d) ++{ ++ return - __builtin_fmaf (b, c, -d); /* fnmsubs */ ++} ++ ++double ++normal_fma (double b, double c, double d) ++{ ++ return (b * c) + d; /* fmadd */ ++} ++ ++float ++normal_fmaf (float b, float c, float d) ++{ ++ return (b * c) + d; /* fmadds */ ++} ++ ++#ifndef SIZE ++#define SIZE 1024 ++#endif ++ ++float vfa[SIZE] __attribute__((__aligned__(32))); ++float vfb[SIZE] __attribute__((__aligned__(32))); ++float vfc[SIZE] __attribute__((__aligned__(32))); ++float vfd[SIZE] __attribute__((__aligned__(32))); ++ ++void ++vector_fmaf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]); /* vaddfp */ ++} ++ ++void ++vnormal_fmaf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = (vfb[i] * vfc[i]) + vfd[i]; /* vaddfp */ ++} +Index: gcc/testsuite/gcc.target/powerpc/altivec-types-3.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c (.../ibm/gcc-4_5-branch) +@@ -1,7 +1,7 @@ + /* { dg-do compile { target powerpc*-*-linux* } } */ + /* { dg-require-effective-target lp64 } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-maltivec" } */ ++/* { dg-options "-maltivec -mno-vsx" } */ + + /* These should be rejected for 64-bit code. */ + +Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,50 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ ++/* { dg-final { scan-assembler-times "lfiwax" 2 } } */ ++/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ ++/* { dg-final { scan-assembler-times "fcfids" 3 } } */ ++/* { dg-final { scan-assembler-times "fcfidus" 1 } } */ ++/* { dg-final { scan-assembler-times "xscvsxddp" 3 } } */ ++/* { dg-final { scan-assembler-times "xscvuxddp" 1 } } */ ++ ++void int_to_float (float *dest, int *src) ++{ ++ *dest = (float) *src; ++} ++ ++void int_to_double (double *dest, int *src) ++{ ++ *dest = (double) *src; ++} ++ ++void uint_to_float (float *dest, unsigned int *src) ++{ ++ *dest = (float) *src; ++} ++ ++void uint_to_double (double *dest, unsigned int *src) ++{ ++ *dest = (double) *src; ++} ++ ++void llong_to_float (float *dest, long long *src) ++{ ++ *dest = (float) *src; ++} ++ ++void llong_to_double (double *dest, long long *src) ++{ ++ *dest = (double) *src; ++} ++ ++void ullong_to_float (float *dest, unsigned long long *src) ++{ ++ *dest = (float) *src; ++} ++ ++void ullong_to_double (double *dest, unsigned long long *src) ++{ ++ *dest = (double) *src; ++} +Index: gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,554 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math -mveclibabi=mass" } */ ++/* { dg-final { scan-assembler "bl atan2d2" } } */ ++/* { dg-final { scan-assembler "bl atan2f4" } } */ ++/* { dg-final { scan-assembler "bl hypotd2" } } */ ++/* { dg-final { scan-assembler "bl hypotf4" } } */ ++/* { dg-final { scan-assembler "bl powd2" } } */ ++/* { dg-final { scan-assembler "bl powf4" } } */ ++/* { dg-final { scan-assembler "bl acosd2" } } */ ++/* { dg-final { scan-assembler "bl acosf4" } } */ ++/* { dg-final { scan-assembler "bl acoshd2" } } */ ++/* { dg-final { scan-assembler "bl acoshf4" } } */ ++/* { dg-final { scan-assembler "bl asind2" } } */ ++/* { dg-final { scan-assembler "bl asinf4" } } */ ++/* { dg-final { scan-assembler "bl asinhd2" } } */ ++/* { dg-final { scan-assembler "bl asinhf4" } } */ ++/* { dg-final { scan-assembler "bl atand2" } } */ ++/* { dg-final { scan-assembler "bl atanf4" } } */ ++/* { dg-final { scan-assembler "bl atanhd2" } } */ ++/* { dg-final { scan-assembler "bl atanhf4" } } */ ++/* { dg-final { scan-assembler "bl cbrtd2" } } */ ++/* { dg-final { scan-assembler "bl cbrtf4" } } */ ++/* { dg-final { scan-assembler "bl cosd2" } } */ ++/* { dg-final { scan-assembler "bl cosf4" } } */ ++/* { dg-final { scan-assembler "bl coshd2" } } */ ++/* { dg-final { scan-assembler "bl coshf4" } } */ ++/* { dg-final { scan-assembler "bl erfd2" } } */ ++/* { dg-final { scan-assembler "bl erff4" } } */ ++/* { dg-final { scan-assembler "bl erfcd2" } } */ ++/* { dg-final { scan-assembler "bl erfcf4" } } */ ++/* { dg-final { scan-assembler "bl exp2d2" } } */ ++/* { dg-final { scan-assembler "bl exp2f4" } } */ ++/* { dg-final { scan-assembler "bl expd2" } } */ ++/* { dg-final { scan-assembler "bl expf4" } } */ ++/* { dg-final { scan-assembler "bl expm1d2" } } */ ++/* { dg-final { scan-assembler "bl expm1f4" } } */ ++/* { dg-final { scan-assembler "bl lgamma" } } */ ++/* { dg-final { scan-assembler "bl lgammaf" } } */ ++/* { dg-final { scan-assembler "bl log10d2" } } */ ++/* { dg-final { scan-assembler "bl log10f4" } } */ ++/* { dg-final { scan-assembler "bl log1pd2" } } */ ++/* { dg-final { scan-assembler "bl log1pf4" } } */ ++/* { dg-final { scan-assembler "bl log2d2" } } */ ++/* { dg-final { scan-assembler "bl log2f4" } } */ ++/* { dg-final { scan-assembler "bl logd2" } } */ ++/* { dg-final { scan-assembler "bl logf4" } } */ ++/* { dg-final { scan-assembler "bl sind2" } } */ ++/* { dg-final { scan-assembler "bl sinf4" } } */ ++/* { dg-final { scan-assembler "bl sinhd2" } } */ ++/* { dg-final { scan-assembler "bl sinhf4" } } */ ++/* { dg-final { scan-assembler "bl tand2" } } */ ++/* { dg-final { scan-assembler "bl tanf4" } } */ ++/* { dg-final { scan-assembler "bl tanhd2" } } */ ++/* { dg-final { scan-assembler "bl tanhf4" } } */ ++ ++#ifndef SIZE ++#define SIZE 1024 ++#endif ++ ++double d1[SIZE] __attribute__((__aligned__(32))); ++double d2[SIZE] __attribute__((__aligned__(32))); ++double d3[SIZE] __attribute__((__aligned__(32))); ++ ++float f1[SIZE] __attribute__((__aligned__(32))); ++float f2[SIZE] __attribute__((__aligned__(32))); ++float f3[SIZE] __attribute__((__aligned__(32))); ++ ++void ++test_double_atan2 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_atan2 (d2[i], d3[i]); ++} ++ ++void ++test_float_atan2 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_atan2f (f2[i], f3[i]); ++} ++ ++void ++test_double_hypot (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_hypot (d2[i], d3[i]); ++} ++ ++void ++test_float_hypot (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_hypotf (f2[i], f3[i]); ++} ++ ++void ++test_double_pow (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_pow (d2[i], d3[i]); ++} ++ ++void ++test_float_pow (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_powf (f2[i], f3[i]); ++} ++ ++void ++test_double_acos (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_acos (d2[i]); ++} ++ ++void ++test_float_acos (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_acosf (f2[i]); ++} ++ ++void ++test_double_acosh (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_acosh (d2[i]); ++} ++ ++void ++test_float_acosh (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_acoshf (f2[i]); ++} ++ ++void ++test_double_asin (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_asin (d2[i]); ++} ++ ++void ++test_float_asin (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_asinf (f2[i]); ++} ++ ++void ++test_double_asinh (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_asinh (d2[i]); ++} ++ ++void ++test_float_asinh (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_asinhf (f2[i]); ++} ++ ++void ++test_double_atan (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_atan (d2[i]); ++} ++ ++void ++test_float_atan (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_atanf (f2[i]); ++} ++ ++void ++test_double_atanh (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_atanh (d2[i]); ++} ++ ++void ++test_float_atanh (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_atanhf (f2[i]); ++} ++ ++void ++test_double_cbrt (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_cbrt (d2[i]); ++} ++ ++void ++test_float_cbrt (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_cbrtf (f2[i]); ++} ++ ++void ++test_double_cos (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_cos (d2[i]); ++} ++ ++void ++test_float_cos (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_cosf (f2[i]); ++} ++ ++void ++test_double_cosh (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_cosh (d2[i]); ++} ++ ++void ++test_float_cosh (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_coshf (f2[i]); ++} ++ ++void ++test_double_erf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_erf (d2[i]); ++} ++ ++void ++test_float_erf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_erff (f2[i]); ++} ++ ++void ++test_double_erfc (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_erfc (d2[i]); ++} ++ ++void ++test_float_erfc (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_erfcf (f2[i]); ++} ++ ++void ++test_double_exp2 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_exp2 (d2[i]); ++} ++ ++void ++test_float_exp2 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_exp2f (f2[i]); ++} ++ ++void ++test_double_exp (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_exp (d2[i]); ++} ++ ++void ++test_float_exp (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_expf (f2[i]); ++} ++ ++void ++test_double_expm1 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_expm1 (d2[i]); ++} ++ ++void ++test_float_expm1 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_expm1f (f2[i]); ++} ++ ++void ++test_double_lgamma (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_lgamma (d2[i]); ++} ++ ++void ++test_float_lgamma (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_lgammaf (f2[i]); ++} ++ ++void ++test_double_log10 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_log10 (d2[i]); ++} ++ ++void ++test_float_log10 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_log10f (f2[i]); ++} ++ ++void ++test_double_log1p (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_log1p (d2[i]); ++} ++ ++void ++test_float_log1p (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_log1pf (f2[i]); ++} ++ ++void ++test_double_log2 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_log2 (d2[i]); ++} ++ ++void ++test_float_log2 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_log2f (f2[i]); ++} ++ ++void ++test_double_log (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_log (d2[i]); ++} ++ ++void ++test_float_log (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_logf (f2[i]); ++} ++ ++void ++test_double_sin (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_sin (d2[i]); ++} ++ ++void ++test_float_sin (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_sinf (f2[i]); ++} ++ ++void ++test_double_sinh (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_sinh (d2[i]); ++} ++ ++void ++test_float_sinh (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_sinhf (f2[i]); ++} ++ ++void ++test_double_sqrt (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_sqrt (d2[i]); ++} ++ ++void ++test_float_sqrt (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_sqrtf (f2[i]); ++} ++ ++void ++test_double_tan (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_tan (d2[i]); ++} ++ ++void ++test_float_tan (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_tanf (f2[i]); ++} ++ ++void ++test_double_tanh (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d1[i] = __builtin_tanh (d2[i]); ++} ++ ++void ++test_float_tanh (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f1[i] = __builtin_tanhf (f2[i]); ++} +Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,11 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */ ++/* { dg-final { scan-assembler-not "lwz" } } */ ++/* { dg-final { scan-assembler-not "stw" } } */ ++/* { dg-final { scan-assembler-not "ld " } } */ ++/* { dg-final { scan-assembler-not "std" } } */ ++ ++void float_to_llong (long long *dest, float src) { *dest = (long long) src; } ++void double_to_llong (long long *dest, double src) { *dest = (long long) src; } +Index: gcc/testsuite/gcc.target/powerpc/loop_align.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/loop_align.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/loop_align.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,10 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-options "-O2 -mcpu=power7 -falign-functions=16" } */ ++/* { dg-final { scan-assembler ".p2align 5,,31" } } */ ++ ++void f(double *a, double *b, double *c, int n) { ++ int i; ++ for (i=0; i < n; i++) ++ a[i] = b[i] + c[i]; ++} +Index: gcc/testsuite/gcc.target/powerpc/recip-test.h +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-test.h (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-test.h (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,149 @@ ++/* Check reciprocal estimate functions for accuracy. */ ++ ++#ifdef _ARCH_PPC64 ++typedef unsigned long uns64_t; ++#define UNUM64(x) x ## L ++ ++#else ++typedef unsigned long long uns64_t; ++#define UNUM64(x) x ## LL ++#endif ++ ++typedef unsigned int uns32_t; ++ ++#define TNAME2(x) #x ++#define TNAME(x) TNAME2(x) ++ ++/* ++ * Float functions. ++ */ ++ ++#define TYPE float ++#define NAME(PREFIX) PREFIX ## _float ++#define UNS_TYPE uns32_t ++#define UNS_ABS __builtin_abs ++#define EXP_SIZE 8 ++#define MAN_SIZE 23 ++#define FABS __builtin_fabsf ++#define FMAX __builtin_fmaxf ++#define FMIN __builtin_fminf ++#define SQRT __builtin_sqrtf ++#define RMIN 1.0e-10 ++#define RMAX 1.0e+10 ++#define BDIV 1 ++#define BRSQRT 2 ++#define ASMDIV "fdivs" ++#define ASMSQRT "fsqrts" ++ ++#define INIT_DIV \ ++{ \ ++ { 0x4fffffff }, /* 8589934080 */ \ ++ { 0x4effffff }, /* 2147483520 */ \ ++ { 0x40ffffff }, /* 7.99999952316284 */ \ ++ { 0x3fffffff }, /* 1.99999988079071 */ \ ++ { 0x417fffff }, /* 15.9999990463257 */ \ ++ { 0x42ffffff }, /* 127.999992370605 */ \ ++ { 0x3dffffff }, /* 0.124999992549419 */ \ ++ { 0x3effffff }, /* 0.499999970197678 */ \ ++} ++ ++#define INIT_RSQRT \ ++{ \ ++ { 0x457ffffe }, /* 4096 - small amount */ \ ++ { 0x4c7fffff }, /* 6.71089e+07 */ \ ++ { 0x3d7fffff }, /* 0.0625 - small amount */ \ ++ { 0x307ffffe }, /* 9.31322e-10 */ \ ++ { 0x4c7ffffe }, /* 6.71089e+07 */ \ ++ { 0x397ffffe }, /* 0.000244141 */ \ ++ { 0x2e7fffff }, /* 5.82077e-11 */ \ ++ { 0x2f7fffff }, /* 2.32831e-10 */ \ ++} ++ ++ ++#include "recip-test2.h" ++ ++/* ++ * Double functions. ++ */ ++ ++#undef TYPE ++#undef NAME ++#undef UNS_TYPE ++#undef UNS_ABS ++#undef EXP_SIZE ++#undef MAN_SIZE ++#undef FABS ++#undef FMAX ++#undef FMIN ++#undef SQRT ++#undef RMIN ++#undef RMAX ++#undef BDIV ++#undef BRSQRT ++#undef ASMDIV ++#undef ASMSQRT ++#undef INIT_DIV ++#undef INIT_RSQRT ++ ++#define TYPE double ++#define NAME(PREFIX) PREFIX ## _double ++#define UNS_TYPE uns64_t ++#define UNS_ABS __builtin_imaxabs ++#define EXP_SIZE 11 ++#define MAN_SIZE 52 ++#define FABS __builtin_fabs ++#define FMAX __builtin_fmax ++#define FMIN __builtin_fmin ++#define SQRT __builtin_sqrt ++#define RMIN 1.0e-100 ++#define RMAX 1.0e+100 ++#define BDIV 1 ++#define BRSQRT 2 ++#define ASMDIV "fdiv" ++#define ASMSQRT "fsqrt" ++ ++#define INIT_DIV \ ++{ \ ++ { UNUM64 (0x2b57be53f2a2f3a0) }, /* 6.78462e-100 */ \ ++ { UNUM64 (0x2b35f8e8ea553e52) }, /* 1.56963e-100 */ \ ++ { UNUM64 (0x2b5b9d861d2fe4fb) }, /* 7.89099e-100 */ \ ++ { UNUM64 (0x2b45dc44a084e682) }, /* 3.12327e-100 */ \ ++ { UNUM64 (0x2b424ce16945d777) }, /* 2.61463e-100 */ \ ++ { UNUM64 (0x2b20b5023d496b50) }, /* 5.96749e-101 */ \ ++ { UNUM64 (0x2b61170547f57caa) }, /* 9.76678e-100 */ \ ++ { UNUM64 (0x2b543b9d498aac37) }, /* 5.78148e-100 */ \ ++} ++ ++#define INIT_RSQRT \ ++{ \ ++ { UNUM64 (0x2b616f2d8cbbc646) }, /* 9.96359e-100 */ \ ++ { UNUM64 (0x2b5c4db2da0a011d) }, /* 8.08764e-100 */ \ ++ { UNUM64 (0x2b55a82d5735b262) }, /* 6.1884e-100 */ \ ++ { UNUM64 (0x2b50b52908258cb8) }, /* 4.77416e-100 */ \ ++ { UNUM64 (0x2b363989a4fb29af) }, /* 1.58766e-100 */ \ ++ { UNUM64 (0x2b508b9f6f4180a9) }, /* 4.7278e-100 */ \ ++ { UNUM64 (0x2b4f7a1d48accb40) }, /* 4.49723e-100 */ \ ++ { UNUM64 (0x2b1146a37372a81f) }, /* 3.08534e-101 */ \ ++ { UNUM64 (0x2b33f876a8c48050) }, /* 1.42663e-100 */ \ ++} ++ ++#include "recip-test2.h" ++ ++int ++main (int argc __attribute__((__unused__)), ++ char *argv[] __attribute__((__unused__))) ++{ ++ srand48 (1); ++ run_float (); ++ ++#ifdef VERBOSE ++ printf ("\n"); ++#endif ++ ++ run_double (); ++ ++ if (error_count_float != 0 || error_count_double != 0) ++ abort (); ++ ++ return 0; ++} +Index: gcc/testsuite/gcc.target/powerpc/recip-3.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-3.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-3.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,22 @@ ++/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ ++/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power7" } */ ++/* { dg-final { scan-assembler-times "xsrsqrtedp" 1 } } */ ++/* { dg-final { scan-assembler-times "xsmsub.dp" 1 } } */ ++/* { dg-final { scan-assembler-times "xsmuldp" 4 } } */ ++/* { dg-final { scan-assembler-times "xsnmsub.dp" 2 } } */ ++/* { dg-final { scan-assembler-times "frsqrtes" 1 } } */ ++/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ ++/* { dg-final { scan-assembler-times "fmuls" 4 } } */ ++/* { dg-final { scan-assembler-times "fnmsubs" 2 } } */ ++ ++double ++rsqrt_d (double a) ++{ ++ return 1.0 / __builtin_sqrt (a); ++} ++ ++float ++rsqrt_f (float a) ++{ ++ return 1.0f / __builtin_sqrtf (a); ++} +Index: gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,94 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-options "-O3 -ftree-vectorize -mcpu=power6 -maltivec -ffast-math -ffp-contract=off" } */ ++/* { dg-final { scan-assembler-times "vmaddfp" 1 } } */ ++/* { dg-final { scan-assembler-times "fmadd " 1 } } */ ++/* { dg-final { scan-assembler-times "fmadds" 1 } } */ ++/* { dg-final { scan-assembler-times "fmsub " 1 } } */ ++/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ ++/* { dg-final { scan-assembler-times "fnmadd " 1 } } */ ++/* { dg-final { scan-assembler-times "fnmadds" 1 } } */ ++/* { dg-final { scan-assembler-times "fnmsub " 1 } } */ ++/* { dg-final { scan-assembler-times "fnmsubs" 1 } } */ ++ ++/* Only the functions calling the builtin should generate an appropriate ++ (a * b) + c instruction. */ ++ ++double ++builtin_fma (double b, double c, double d) ++{ ++ return __builtin_fma (b, c, d); /* fmadd */ ++} ++ ++double ++builtin_fms (double b, double c, double d) ++{ ++ return __builtin_fma (b, c, -d); /* fmsub */ ++} ++ ++double ++builtin_fnma (double b, double c, double d) ++{ ++ return - __builtin_fma (b, c, d); /* fnmadd */ ++} ++ ++double ++builtin_fnms (double b, double c, double d) ++{ ++ return - __builtin_fma (b, c, -d); /* fnmsub */ ++} ++ ++float ++builtin_fmaf (float b, float c, float d) ++{ ++ return __builtin_fmaf (b, c, d); /* fmadds */ ++} ++ ++float ++builtin_fmsf (float b, float c, float d) ++{ ++ return __builtin_fmaf (b, c, -d); /* fmsubs */ ++} ++ ++float ++builtin_fnmaf (float b, float c, float d) ++{ ++ return - __builtin_fmaf (b, c, d); /* fnmadds */ ++} ++ ++float ++builtin_fnmsf (float b, float c, float d) ++{ ++ return - __builtin_fmaf (b, c, -d); /* fnmsubs */ ++} ++ ++double ++normal_fma (double b, double c, double d) ++{ ++ return (b * c) + d; /* fmul/fadd */ ++} ++ ++float ++normal_fmaf (float b, float c, float d) ++{ ++ return (b * c) + d; /* fmuls/fadds */ ++} ++ ++#ifndef SIZE ++#define SIZE 1024 ++#endif ++ ++float vfa[SIZE] __attribute__((__aligned__(32))); ++float vfb[SIZE] __attribute__((__aligned__(32))); ++float vfc[SIZE] __attribute__((__aligned__(32))); ++float vfd[SIZE] __attribute__((__aligned__(32))); ++ ++void ++vector_fmaf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]); /* vaddfp */ ++} +Index: gcc/testsuite/gcc.target/powerpc/altivec-types-4.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c (.../ibm/gcc-4_5-branch) +@@ -1,7 +1,7 @@ + /* { dg-do compile { target powerpc*-*-linux* } } */ + /* { dg-require-effective-target ilp32 } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-maltivec -mno-warn-altivec-long" } */ ++/* { dg-options "-maltivec -mno-warn-altivec-long -mno-vsx" } */ + + /* These should not get warnings for 32-bit code when the warning is + disabled. */ +Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,51 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O2 -mcpu=power6 -ffast-math" } */ ++/* { dg-final { scan-assembler-times "lfiwax" 2 } } */ ++/* { dg-final { scan-assembler-not "lfiwzx" } } */ ++/* { dg-final { scan-assembler-times "fcfid " 10 } } */ ++/* { dg-final { scan-assembler-not "fcfids" } } */ ++/* { dg-final { scan-assembler-not "fcfidus" } } */ ++/* { dg-final { scan-assembler-not "xscvsxddp" } } */ ++/* { dg-final { scan-assembler-not "xscvuxddp" } } */ ++ ++void int_to_float (float *dest, int *src) ++{ ++ *dest = (float) *src; ++} ++ ++void int_to_double (double *dest, int *src) ++{ ++ *dest = (double) *src; ++} ++ ++void uint_to_float (float *dest, unsigned int *src) ++{ ++ *dest = (float) *src; ++} ++ ++void uint_to_double (double *dest, unsigned int *src) ++{ ++ *dest = (double) *src; ++} ++ ++void llong_to_float (float *dest, long long *src) ++{ ++ *dest = (float) *src; ++} ++ ++void llong_to_double (double *dest, long long *src) ++{ ++ *dest = (double) *src; ++} ++ ++void ullong_to_float (float *dest, unsigned long long *src) ++{ ++ *dest = (float) *src; ++} ++ ++void ullong_to_double (double *dest, unsigned long long *src) ++{ ++ *dest = (double) *src; ++} +Index: gcc/testsuite/gcc.target/powerpc/recip-4.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-4.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-4.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,36 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-options "-O3 -ftree-vectorize -mrecip -ffast-math -mcpu=power7 -fno-unroll-loops" } */ ++/* { dg-final { scan-assembler-times "xvrsqrtedp" 1 } } */ ++/* { dg-final { scan-assembler-times "xvmsub.dp" 1 } } */ ++/* { dg-final { scan-assembler-times "xvmuldp" 4 } } */ ++/* { dg-final { scan-assembler-times "xvnmsub.dp" 2 } } */ ++/* { dg-final { scan-assembler-times "xvrsqrtesp" 1 } } */ ++/* { dg-final { scan-assembler-times "xvmsub.sp" 1 } } */ ++/* { dg-final { scan-assembler-times "xvmulsp" 4 } } */ ++/* { dg-final { scan-assembler-times "xvnmsub.sp" 2 } } */ ++ ++#define SIZE 1024 ++ ++extern double a_d[SIZE] __attribute__((__aligned__(32))); ++extern double b_d[SIZE] __attribute__((__aligned__(32))); ++ ++void ++vectorize_rsqrt_d (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ a_d[i] = 1.0 / __builtin_sqrt (b_d[i]); ++} ++ ++extern float a_f[SIZE] __attribute__((__aligned__(32))); ++extern float b_f[SIZE] __attribute__((__aligned__(32))); ++ ++void ++vectorize_rsqrt_f (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ a_f[i] = 1.0f / __builtin_sqrtf (b_f[i]); ++} +Index: gcc/testsuite/gcc.target/powerpc/altivec-33.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-33.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-33.c (.../ibm/gcc-4_5-branch) +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-O2 -maltivec" } */ ++/* { dg-options "-O2 -maltivec -mno-vsx" } */ + + /* We should only produce one vspltw as we already splatted the value. */ + /* { dg-final { scan-assembler-times "vspltw" 1 } } */ +Index: gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,26 @@ ++/* { dg-do run { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-options "-O2 -mcpu=power5 -std=c99" } */ ++ ++#ifndef __FP_FAST_FMA ++#error "__FP_FAST_FMA should be defined" ++#endif ++ ++#ifndef __FP_FAST_FMAF ++#error "__FP_FAST_FMAF should be defined" ++#endif ++ ++double d_a = 2.0, d_b = 3.0, d_c = 4.0; ++float f_a = 2.0f, f_b = 3.0f, f_c = 4.0f; ++ ++int ++main (void) ++{ ++ if (__builtin_fma (d_a, d_b, d_c) != (2.0 * 3.0) + 4.0) ++ __builtin_abort (); ++ ++ if (__builtin_fmaf (f_a, f_b, f_c) != (2.0f * 3.0f) + 4.0f) ++ __builtin_abort (); ++ ++ return 0; ++} +Index: gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c (.../ibm/gcc-4_5-branch) +@@ -1,6 +1,6 @@ + /* { dg-do compile { target powerpc*-*-* } } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-O -maltivec" } */ ++/* { dg-options "-O -maltivec -mno-vsx" } */ + /* { dg-final { scan-assembler "lvx" } } */ + + void foo(void) +Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,51 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target ilp32 } */ ++/* { dg-options "-O2 -mcpu=power5 -ffast-math" } */ ++/* { dg-final { scan-assembler-not "lfiwax" } } */ ++/* { dg-final { scan-assembler-not "lfiwzx" } } */ ++/* { dg-final { scan-assembler-times "fcfid " 10 } } */ ++/* { dg-final { scan-assembler-not "fcfids" } } */ ++/* { dg-final { scan-assembler-not "fcfidus" } } */ ++/* { dg-final { scan-assembler-not "xscvsxddp" } } */ ++/* { dg-final { scan-assembler-not "xscvuxddp" } } */ ++ ++void int_to_float (float *dest, int *src) ++{ ++ *dest = (float) *src; ++} ++ ++void int_to_double (double *dest, int *src) ++{ ++ *dest = (double) *src; ++} ++ ++void uint_to_float (float *dest, unsigned int *src) ++{ ++ *dest = (float) *src; ++} ++ ++void uint_to_double (double *dest, unsigned int *src) ++{ ++ *dest = (double) *src; ++} ++ ++void llong_to_float (float *dest, long long *src) ++{ ++ *dest = (float) *src; ++} ++ ++void llong_to_double (double *dest, long long *src) ++{ ++ *dest = (double) *src; ++} ++ ++void ullong_to_float (float *dest, unsigned long long *src) ++{ ++ *dest = (float) *src; ++} ++ ++void ullong_to_double (double *dest, unsigned long long *src) ++{ ++ *dest = (double) *src; ++} +Index: gcc/testsuite/gcc.target/powerpc/recip-5.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-5.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-5.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,94 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-options "-O3 -ftree-vectorize -mrecip=all -ffast-math -mcpu=power7 -fno-unroll-loops" } */ ++/* { dg-final { scan-assembler-times "xvredp" 4 } } */ ++/* { dg-final { scan-assembler-times "xvresp" 5 } } */ ++/* { dg-final { scan-assembler-times "xsredp" 2 } } */ ++/* { dg-final { scan-assembler-times "fres" 2 } } */ ++ ++#include ++ ++float f_recip (float a, float b) { return __builtin_recipdivf (a, b); } ++double d_recip (double a, double b) { return __builtin_recipdiv (a, b); } ++ ++float f_div (float a, float b) { return a / b; } ++double d_div (double a, double b) { return a / b; } ++ ++#define SIZE 1024 ++ ++double d_a[SIZE] __attribute__((__aligned__(32))); ++double d_b[SIZE] __attribute__((__aligned__(32))); ++double d_c[SIZE] __attribute__((__aligned__(32))); ++ ++float f_a[SIZE] __attribute__((__aligned__(32))); ++float f_b[SIZE] __attribute__((__aligned__(32))); ++float f_c[SIZE] __attribute__((__aligned__(32))); ++ ++void vec_f_recip (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f_a[i] = __builtin_recipdivf (f_b[i], f_c[i]); ++} ++ ++void vec_d_recip (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d_a[i] = __builtin_recipdiv (d_b[i], d_c[i]); ++} ++ ++void vec_f_div (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f_a[i] = f_b[i] / f_c[i]; ++} ++ ++void vec_f_div2 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f_a[i] = f_b[i] / 2.0f; ++} ++ ++void vec_f_div53 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ f_a[i] = f_b[i] / 53.0f; ++} ++ ++void vec_d_div (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d_a[i] = d_b[i] / d_c[i]; ++} ++ ++void vec_d_div2 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d_a[i] = d_b[i] / 2.0; ++} ++ ++void vec_d_div53 (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ d_a[i] = d_b[i] / 53.0; ++} ++ ++vector float v4sf_recip1 (vector float a, vector float b) { return vec_recipdiv (a, b); } ++vector float v4sf_recip2 (vector float a, vector float b) { return __builtin_altivec_vrecipdivfp (a, b); } ++vector double v2df_recip1 (vector double a, vector double b) { return vec_recipdiv (a, b); } ++vector float v4sf_recip3 (vector float a, vector float b) { return __builtin_vsx_xvrecipdivsp (a, b); } ++vector double v2df_recip2 (vector double a, vector double b) { return __builtin_vsx_xvrecipdivdp (a, b); } +Index: gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,28 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target ilp32 } */ ++/* { dg-options "-O2 -mcpu=power5 -std=c99 -msoft-float" } */ ++/* { dg-final { scan-assembler-not "fmadd" } } */ ++/* { dg-final { scan-assembler-not "xsfmadd" } } */ ++ ++/* Test whether -msoft-float turns off the macros math.h uses for ++ FP_FAST_FMA{,F,L}. */ ++#ifdef __FP_FAST_FMA ++#error "__FP_FAST_FMA should not be defined" ++#endif ++ ++#ifdef __FP_FAST_FMAF ++#error "__FP_FAST_FMAF should not be defined" ++#endif ++ ++double ++builtin_fma (double b, double c, double d) ++{ ++ return __builtin_fma (b, c, d); /* bl fma */ ++} ++ ++float ++builtin_fmaf (float b, float c, float d) ++{ ++ return __builtin_fmaf (b, c, -d); /* bl fmaf */ ++} +Index: gcc/testsuite/gcc.target/powerpc/pr47755-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/pr47755-2.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr47755-2.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,134 @@ ++/* { dg-do run { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O3 -mcpu=power7" } */ ++ ++/* PR 47755: Make sure compiler generates correct code for various ++ V2DI constants. */ ++ ++#ifdef DEBUG ++#include ++ ++static int num_errors; ++#define FAIL_LL(A, B) \ ++ (num_errors++, printf ("Fail (%i, %i)\n", (int)(A), (int)(B))) ++#define FAIL_I(A, B, C, D) \ ++ (num_errors++, \ ++ printf ("Fail (%i, %i, %i, %i)\n", (int)(A), (int)(B), (int)(C), (int)(D))) ++ ++#else ++extern void abort (void) __attribute__((__noreturn__)); ++#define FAIL_LL(A, B) abort () ++#define FAIL_I(A, B, C, D) abort () ++#endif ++ ++static test_ll (vector long long, long long, long long) __attribute__((__noinline__)); ++ ++static ++test_ll (vector long long v, long long a, long long b) ++{ ++ union { ++ vector long long v; ++ long long ll[2]; ++ } u; ++ ++ u.v = v; ++ if (u.ll[0] != a && u.ll[1] != b) ++ FAIL_LL (a, b); ++} ++ ++#define TEST_LL(A,B) test_ll ((vector long long){ (A), (B) }, (A), (B)) ++ ++static test_i (vector int, int, int, int, int) __attribute__((__noinline__)); ++ ++static ++test_i (vector int v, int a, int b, int c, int d) ++{ ++ union { ++ vector int v; ++ int i[4]; ++ } u; ++ ++ u.v = v; ++ if (u.i[0] != a && u.i[1] != b && u.i[2] != c && u.i[3] != d) ++ FAIL_I (a, b, c, d); ++} ++ ++#define TEST_I(A,B,C,D) \ ++ test_i ((vector int){ (A), (B), (C), (D) }, (A), (B), (C), (D)) ++ ++int ++main (void) ++{ ++ TEST_LL (-2LL, -2LL); ++ TEST_LL (-2LL, -1LL); ++ TEST_LL (-2LL, 0LL); ++ TEST_LL (-2LL, 1LL); ++ TEST_LL (-2LL, 2LL); ++ ++ TEST_LL (-1LL, -2LL); ++ TEST_LL (-1LL, -1LL); ++ TEST_LL (-1LL, 0LL); ++ TEST_LL (-1LL, 1LL); ++ TEST_LL (-1LL, 2LL); ++ ++ TEST_LL (0LL, -2LL); ++ TEST_LL (0LL, -1LL); ++ TEST_LL (0LL, 0LL); ++ TEST_LL (0LL, 1LL); ++ TEST_LL (0LL, 2LL); ++ ++ TEST_LL (1LL, -2LL); ++ TEST_LL (1LL, -1LL); ++ TEST_LL (1LL, 0LL); ++ TEST_LL (1LL, 1LL); ++ TEST_LL (1LL, 2LL); ++ ++ TEST_LL (2LL, -2LL); ++ TEST_LL (2LL, -1LL); ++ TEST_LL (2LL, 0LL); ++ TEST_LL (2LL, 1LL); ++ TEST_LL (2LL, 2LL); ++ ++ /* We could use VSPLTI instructions for these tests. */ ++ TEST_LL (0x0101010101010101LL, 0x0101010101010101LL); ++ TEST_LL (0x0001000100010001LL, 0x0001000100010001LL); ++ TEST_LL (0x0000000100000001LL, 0x0000000100000001LL); ++ ++ TEST_LL (0x0404040404040404LL, 0x0404040404040404LL); ++ TEST_LL (0x0004000400040004LL, 0x0004000400040004LL); ++ TEST_LL (0x0000000400000004LL, 0x0000000400000004LL); ++ ++ TEST_LL (0xf8f8f8f8f8f8f8f8LL, 0xf8f8f8f8f8f8f8f8LL); ++ TEST_LL (0xfff8fff8fff8fff8LL, 0xfff8fff8fff8fff8LL); ++ TEST_LL (0xfffffff8fffffff8LL, 0xfffffff8fffffff8LL); ++ ++ /* We could use VSPLTI instructions for these tests. */ ++ TEST_I (-2, -2, -2, -2); ++ TEST_I (-1, -1, -1, -1); ++ TEST_I ( 0, 0, 0, 0); ++ TEST_I ( 1, 1, 1, 1); ++ TEST_I ( 2, 2, 2, 2); ++ ++ TEST_I (0x01010101, 0x01010101, 0x01010101, 0x01010101); ++ TEST_I (0x00010001, 0x00010001, 0x00010001, 0x00010001); ++ ++ TEST_I (0x02020202, 0x02020202, 0x02020202, 0x02020202); ++ TEST_I (0x00020002, 0x00020002, 0x00020002, 0x00020002); ++ ++ TEST_I (0xf8f8f8f8, 0xf8f8f8f8, 0xf8f8f8f8, 0xf8f8f8f8); ++ TEST_I (0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8); ++ ++ /* non-easy constants. */ ++ TEST_I (-2, -1, 0, 1); ++ TEST_I ( 1, 0, -1, -2); ++ ++ TEST_I (-1, -1, 0, 0); ++ TEST_I ( 0, 0, -1, -1); ++ ++#ifdef DEBUG ++ printf ("%d error%s\n", num_errors, (num_errors == 1) ? "" : "s"); ++#endif ++ ++ return 0; ++}; +Index: gcc/testsuite/gcc.target/powerpc/recip-test2.h +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-test2.h (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-test2.h (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,432 @@ ++/* ++ * Included file to common source float/double checking ++ * The following macros should be defined: ++ * TYPE -- floating point type ++ * NAME -- convert a name to include the type ++ * UNS_TYPE -- type to hold TYPE as an unsigned number ++ * EXP_SIZE -- size in bits of the exponent ++ * MAN_SIZE -- size in bits of the mantissa ++ * UNS_ABS -- absolute value for UNS_TYPE ++ * FABS -- absolute value function for TYPE ++ * FMAX -- maximum function for TYPE ++ * FMIN -- minimum function for TYPE ++ * SQRT -- square root function for TYPE ++ * RMIN -- minimum random number to generate ++ * RMAX -- maximum random number to generate ++ * ASMDIV -- assembler instruction to do divide ++ * ASMSQRT -- assembler instruction to do square root ++ * BDIV -- # of bits of inaccuracy to allow for division ++ * BRSQRT -- # of bits of inaccuracy to allow for 1/sqrt ++ * INIT_DIV -- Initial values to test 1/x against ++ * INIT_RSQRT -- Initial values to test 1/sqrt(x) against ++ */ ++ ++typedef union ++{ ++ UNS_TYPE i; ++ TYPE x; ++} NAME (union); ++ ++/* ++ * Input/output arrays. ++ */ ++ ++static NAME (union) NAME (div_input) [] __attribute__((__aligned__(32))) = INIT_DIV; ++static NAME (union) NAME (rsqrt_input)[] __attribute__((__aligned__(32))) = INIT_RSQRT; ++ ++#define DIV_SIZE (sizeof (NAME (div_input)) / sizeof (TYPE)) ++#define RSQRT_SIZE (sizeof (NAME (rsqrt_input)) / sizeof (TYPE)) ++ ++static TYPE NAME (div_expected)[DIV_SIZE] __attribute__((__aligned__(32))); ++static TYPE NAME (div_output) [DIV_SIZE] __attribute__((__aligned__(32))); ++ ++static TYPE NAME (rsqrt_expected)[RSQRT_SIZE] __attribute__((__aligned__(32))); ++static TYPE NAME (rsqrt_output) [RSQRT_SIZE] __attribute__((__aligned__(32))); ++ ++ ++/* ++ * Crack a floating point number into sign bit, exponent, and mantissa. ++ */ ++ ++static void ++NAME (crack) (TYPE number, unsigned int *p_sign, unsigned *p_exponent, UNS_TYPE *p_mantissa) ++{ ++ NAME (union) u; ++ UNS_TYPE bits; ++ ++ u.x = number; ++ bits = u.i; ++ ++ *p_sign = (unsigned int)((bits >> (EXP_SIZE + MAN_SIZE)) & 0x1); ++ *p_exponent = (unsigned int)((bits >> MAN_SIZE) & ((((UNS_TYPE)1) << EXP_SIZE) - 1)); ++ *p_mantissa = bits & ((((UNS_TYPE)1) << MAN_SIZE) - 1); ++ return; ++} ++ ++ ++/* ++ * Prevent optimizer from eliminating + 0.0 to remove -0.0. ++ */ ++ ++volatile TYPE NAME (math_diff_0) = ((TYPE) 0.0); ++ ++/* ++ * Return negative if two numbers are significanly different or return the ++ * number of bits that are different in the mantissa. ++ */ ++ ++static int ++NAME (math_diff) (TYPE a, TYPE b, int bits) ++{ ++ TYPE zero = NAME (math_diff_0); ++ unsigned int sign_a, sign_b; ++ unsigned int exponent_a, exponent_b; ++ UNS_TYPE mantissa_a, mantissa_b, diff; ++ int i; ++ ++ /* eliminate signed zero. */ ++ a += zero; ++ b += zero; ++ ++ /* special case Nan. */ ++ if (__builtin_isnan (a)) ++ return (__builtin_isnan (b) ? 0 : -1); ++ ++ if (a == b) ++ return 0; ++ ++ /* special case infinity. */ ++ if (__builtin_isinf (a)) ++ return (__builtin_isinf (b) ? 0 : -1); ++ ++ /* punt on denormal numbers. */ ++ if (!__builtin_isnormal (a) || !__builtin_isnormal (b)) ++ return -1; ++ ++ NAME (crack) (a, &sign_a, &exponent_a, &mantissa_a); ++ NAME (crack) (b, &sign_b, &exponent_b, &mantissa_b); ++ ++ /* If the sign is different, there is no hope. */ ++ if (sign_a != sign_b) ++ return -1; ++ ++ /* If the exponent is off by 1, see if the values straddle the power of two, ++ and adjust things to do the mantassa check if we can. */ ++ if ((exponent_a == (exponent_b+1)) || (exponent_a == (exponent_b-1))) ++ { ++ TYPE big = FMAX (a, b); ++ TYPE small = FMIN (a, b); ++ TYPE diff = FABS (a - b); ++ unsigned int sign_big, sign_small, sign_test; ++ unsigned int exponent_big, exponent_small, exponent_test; ++ UNS_TYPE mantissa_big, mantissa_small, mantissa_test; ++ ++ NAME (crack) (big, &sign_big, &exponent_big, &mantissa_big); ++ NAME (crack) (small, &sign_small, &exponent_small, &mantissa_small); ++ ++ NAME (crack) (small - diff, &sign_test, &exponent_test, &mantissa_test); ++ if ((sign_test == sign_small) && (exponent_test == exponent_small)) ++ { ++ mantissa_a = mantissa_small; ++ mantissa_b = mantissa_test; ++ } ++ ++ else ++ { ++ NAME (crack) (big + diff, &sign_test, &exponent_test, &mantissa_test); ++ if ((sign_test == sign_big) && (exponent_test == exponent_big)) ++ { ++ mantissa_a = mantissa_big; ++ mantissa_b = mantissa_test; ++ } ++ ++ else ++ return -1; ++ } ++ } ++ ++ else if (exponent_a != exponent_b) ++ return -1; ++ ++ diff = UNS_ABS (mantissa_a - mantissa_b); ++ for (i = MAN_SIZE; i > 0; i--) ++ { ++ if ((diff & ((UNS_TYPE)1) << (i-1)) != 0) ++ return i; ++ } ++ ++ return -1; ++} ++ ++ ++/* ++ * Turn off inlining to make code inspection easier. ++ */ ++ ++static void NAME (asm_div) (void) __attribute__((__noinline__)); ++static void NAME (vector_div) (void) __attribute__((__noinline__)); ++static void NAME (scalar_div) (void) __attribute__((__noinline__)); ++static void NAME (asm_rsqrt) (void) __attribute__((__noinline__)); ++static void NAME (vector_rsqrt) (void) __attribute__((__noinline__)); ++static void NAME (scalar_rsqrt) (void) __attribute__((__noinline__)); ++static void NAME (check_div) (const char *) __attribute__((__noinline__)); ++static void NAME (check_rsqrt) (const char *) __attribute__((__noinline__)); ++static void NAME (run) (void) __attribute__((__noinline__)); ++ ++ ++/* ++ * Division function that might be vectorized. ++ */ ++ ++static void ++NAME (vector_div) (void) ++{ ++ size_t i; ++ ++ for (i = 0; i < DIV_SIZE; i++) ++ NAME (div_output)[i] = ((TYPE) 1.0) / NAME (div_input)[i].x; ++} ++ ++/* ++ * Division function that is not vectorized. ++ */ ++ ++static void ++NAME (scalar_div) (void) ++{ ++ size_t i; ++ ++ for (i = 0; i < DIV_SIZE; i++) ++ { ++ TYPE x = ((TYPE) 1.0) / NAME (div_input)[i].x; ++ TYPE y; ++ __asm__ ("" : "=d" (y) : "0" (x)); ++ NAME (div_output)[i] = y; ++ } ++} ++ ++/* ++ * Generate the division instruction via asm. ++ */ ++ ++static void ++NAME (asm_div) (void) ++{ ++ size_t i; ++ ++ for (i = 0; i < DIV_SIZE; i++) ++ { ++ TYPE x; ++ __asm__ (ASMDIV " %0,%1,%2" ++ : "=d" (x) ++ : "d" ((TYPE) 1.0), "d" (NAME (div_input)[i].x)); ++ NAME (div_expected)[i] = x; ++ } ++} ++ ++/* ++ * Reciprocal square root function that might be vectorized. ++ */ ++ ++static void ++NAME (vector_rsqrt) (void) ++{ ++ size_t i; ++ ++ for (i = 0; i < RSQRT_SIZE; i++) ++ NAME (rsqrt_output)[i] = ((TYPE) 1.0) / SQRT (NAME (rsqrt_input)[i].x); ++} ++ ++/* ++ * Reciprocal square root function that is not vectorized. ++ */ ++ ++static void ++NAME (scalar_rsqrt) (void) ++{ ++ size_t i; ++ ++ for (i = 0; i < RSQRT_SIZE; i++) ++ { ++ TYPE x = ((TYPE) 1.0) / SQRT (NAME (rsqrt_input)[i].x); ++ TYPE y; ++ __asm__ ("" : "=d" (y) : "0" (x)); ++ NAME (rsqrt_output)[i] = y; ++ } ++} ++ ++/* ++ * Generate the 1/sqrt instructions via asm. ++ */ ++ ++static void ++NAME (asm_rsqrt) (void) ++{ ++ size_t i; ++ ++ for (i = 0; i < RSQRT_SIZE; i++) ++ { ++ TYPE x; ++ TYPE y; ++ __asm__ (ASMSQRT " %0,%1" : "=d" (x) : "d" (NAME (rsqrt_input)[i].x)); ++ __asm__ (ASMDIV " %0,%1,%2" : "=d" (y) : "d" ((TYPE) 1.0), "d" (x)); ++ NAME (rsqrt_expected)[i] = y; ++ } ++} ++ ++ ++/* ++ * Functions to abort or report errors. ++ */ ++ ++static int NAME (error_count) = 0; ++ ++#ifdef VERBOSE ++static int NAME (max_bits_div) = 0; ++static int NAME (max_bits_rsqrt) = 0; ++#endif ++ ++ ++/* ++ * Compare the expected value with the value we got. ++ */ ++ ++static void ++NAME (check_div) (const char *test) ++{ ++ size_t i; ++ int b; ++ ++ for (i = 0; i < DIV_SIZE; i++) ++ { ++ TYPE exp = NAME (div_expected)[i]; ++ TYPE out = NAME (div_output)[i]; ++ b = NAME (math_diff) (exp, out, BDIV); ++ ++#ifdef VERBOSE ++ if (b != 0) ++ { ++ NAME (union) u_in = NAME (div_input)[i]; ++ NAME (union) u_exp; ++ NAME (union) u_out; ++ char explanation[64]; ++ const char *p_exp; ++ ++ if (b < 0) ++ p_exp = "failed"; ++ else ++ { ++ p_exp = explanation; ++ sprintf (explanation, "%d bit error%s", b, (b > BDIV) ? ", failed" : ""); ++ } ++ ++ u_exp.x = exp; ++ u_out.x = out; ++ printf ("%s %s %s for 1.0 / %g [0x%llx], expected %g [0x%llx], got %g [0x%llx]\n", ++ TNAME (TYPE), test, p_exp, ++ (double) u_in.x, (unsigned long long) u_in.i, ++ (double) exp, (unsigned long long) u_exp.i, ++ (double) out, (unsigned long long) u_out.i); ++ } ++#endif ++ ++ if (b < 0 || b > BDIV) ++ NAME (error_count)++; ++ ++#ifdef VERBOSE ++ if (b > NAME (max_bits_div)) ++ NAME (max_bits_div) = b; ++#endif ++ } ++} ++ ++static void ++NAME (check_rsqrt) (const char *test) ++{ ++ size_t i; ++ int b; ++ ++ for (i = 0; i < RSQRT_SIZE; i++) ++ { ++ TYPE exp = NAME (rsqrt_expected)[i]; ++ TYPE out = NAME (rsqrt_output)[i]; ++ b = NAME (math_diff) (exp, out, BRSQRT); ++ ++#ifdef VERBOSE ++ if (b != 0) ++ { ++ NAME (union) u_in = NAME (rsqrt_input)[i]; ++ NAME (union) u_exp; ++ NAME (union) u_out; ++ char explanation[64]; ++ const char *p_exp; ++ ++ if (b < 0) ++ p_exp = "failed"; ++ else ++ { ++ p_exp = explanation; ++ sprintf (explanation, "%d bit error%s", b, (b > BDIV) ? ", failed" : ""); ++ } ++ ++ u_exp.x = exp; ++ u_out.x = out; ++ printf ("%s %s %s for 1 / sqrt (%g) [0x%llx], expected %g [0x%llx], got %g [0x%llx]\n", ++ TNAME (TYPE), test, p_exp, ++ (double) u_in.x, (unsigned long long) u_in.i, ++ (double) exp, (unsigned long long) u_exp.i, ++ (double) out, (unsigned long long) u_out.i); ++ } ++#endif ++ ++ if (b < 0 || b > BRSQRT) ++ NAME (error_count)++; ++ ++#ifdef VERBOSE ++ if (b > NAME (max_bits_rsqrt)) ++ NAME (max_bits_rsqrt) = b; ++#endif ++ } ++} ++ ++ ++/* ++ * Now do everything. ++ */ ++ ++static void ++NAME (run) (void) ++{ ++#ifdef VERBOSE ++ printf ("start run_%s, divide size = %ld, rsqrt size = %ld, %d bit%s for a/b, %d bit%s for 1/sqrt(a)\n", ++ TNAME (TYPE), ++ (long)DIV_SIZE, ++ (long)RSQRT_SIZE, ++ BDIV, (BDIV == 1) ? "" : "s", ++ BRSQRT, (BRSQRT == 1) ? "" : "s"); ++#endif ++ ++ NAME (asm_div) (); ++ ++ NAME (scalar_div) (); ++ NAME (check_div) ("scalar"); ++ ++ NAME (vector_div) (); ++ NAME (check_div) ("vector"); ++ ++ NAME (asm_rsqrt) (); ++ ++ NAME (scalar_rsqrt) (); ++ NAME (check_rsqrt) ("scalar"); ++ ++ NAME (vector_rsqrt) (); ++ NAME (check_rsqrt) ("vector"); ++ ++#ifdef VERBOSE ++ printf ("end run_%s, errors = %d, max div bits = %d, max rsqrt bits = %d\n", ++ TNAME (TYPE), ++ NAME (error_count), ++ NAME (max_bits_div), ++ NAME (max_bits_rsqrt)); ++#endif ++} +Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,51 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target ilp32 } */ ++/* { dg-options "-O2 -mcpu=750 -ffast-math" } */ ++/* { dg-final { scan-assembler-not "lfiwax" } } */ ++/* { dg-final { scan-assembler-not "lfiwzx" } } */ ++/* { dg-final { scan-assembler-not "fcfid " } } */ ++/* { dg-final { scan-assembler-not "fcfids" } } */ ++/* { dg-final { scan-assembler-not "fcfidus" } } */ ++/* { dg-final { scan-assembler-not "xscvsxddp" } } */ ++/* { dg-final { scan-assembler-not "xscvuxddp" } } */ ++ ++void int_to_float (float *dest, int *src) ++{ ++ *dest = (float) *src; ++} ++ ++void int_to_double (double *dest, int *src) ++{ ++ *dest = (double) *src; ++} ++ ++void uint_to_float (float *dest, unsigned int *src) ++{ ++ *dest = (float) *src; ++} ++ ++void uint_to_double (double *dest, unsigned int *src) ++{ ++ *dest = (double) *src; ++} ++ ++void llong_to_float (float *dest, long long *src) ++{ ++ *dest = (float) *src; ++} ++ ++void llong_to_double (double *dest, long long *src) ++{ ++ *dest = (double) *src; ++} ++ ++void ullong_to_float (float *dest, unsigned long long *src) ++{ ++ *dest = (float) *src; ++} ++ ++void ullong_to_double (double *dest, unsigned long long *src) ++{ ++ *dest = (double) *src; ++} +Index: gcc/testsuite/gcc.target/powerpc/recip-6.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-6.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-6.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,16 @@ ++/* { dg-do run { target { powerpc*-*-linux* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target vsx_hw } */ ++/* { dg-options "-mcpu=power7 -O3 -ftree-vectorize -ffast-math -mrecip=all -mrecip-precision" } */ ++ ++/* Check reciprocal estimate functions for accuracy. */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "recip-test.h" +Index: gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,18 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-options "-O3 -ftree-vectorize -mcpu=power6 -ffast-math" } */ ++/* { dg-final { scan-assembler-times "fmadd" 1 } } */ ++/* { dg-final { scan-assembler-times "fmsub " 1 } } */ ++/* { dg-final { scan-assembler-not "fmul" } } */ ++/* { dg-final { scan-assembler-not "fadd " } } */ ++ ++/* Check whether the common FFT idiom (a*b)+c and (a*b)-c generates two fma ++ instructions, instead of a multiply, add, and subtract. */ ++ ++void ++fft (double *result, double a, double b, double c) ++{ ++ result[0] = (a*b) + c; ++ result[1] = (a*b) - c; ++} +Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,22 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */ ++/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ ++/* { dg-final { scan-assembler-times "fctiwuz" 2 } } */ ++/* { dg-final { scan-assembler-times "fctidz" 1 } } */ ++/* { dg-final { scan-assembler-times "fctiduz" 1 } } */ ++/* { dg-final { scan-assembler-times "xscvdpsxds" 1 } } */ ++/* { dg-final { scan-assembler-times "xscvdpuxds" 1 } } */ ++ ++void float_to_int (int *dest, float src) { *dest = (int) src; } ++void double_to_int (int *dest, double src) { *dest = (int) src; } ++ ++void float_to_uint (int *dest, float src) { *dest = (unsigned int) src; } ++void double_to_uint (int *dest, double src) { *dest = (unsigned int) src; } ++ ++void float_to_llong (long long *dest, float src) { *dest = (long long) src; } ++void double_to_llong (long long *dest, double src) { *dest = (long long) src; } ++ ++void float_to_ullong (unsigned long long *dest, float src) { *dest = (unsigned long long) src; } ++void double_to_ullong (unsigned long long *dest, double src) { *dest = (unsigned long long) src; } +Index: gcc/testsuite/gcc.target/powerpc/pr48053-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/pr48053-1.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr48053-1.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,30 @@ ++/* Test for ICE arising from VSX code generation. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3 -mcpu=power7 -funroll-loops" } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++ ++int sourcenode; ++int ARCHelems; ++int *source_elms; ++void ++foo (int argc, char **argv) ++{ ++ int i, j; ++ int cor[4]; ++ double Ke[12][12], Me[12], Ce[12], Mexv[12], Cexv[12], v[12]; ++ for (i = 0; i < ARCHelems; i++) ++ { ++ for (j = 0; j < 12; j++) ++ Me[j] = 0.0; ++ if (cor[j] == sourcenode) ++ vv12x12 (Me, v, Mexv); ++ vv12x12 (Ce, v, Cexv); ++ if (source_elms[i] == 3) ++ for (j = 0; j < 12; j++) ++ { ++ v[j] = -v[j]; ++ Mexv[j] = -Mexv[j]; ++ Cexv[j] = -Cexv[j]; ++ } ++ } ++} +Index: gcc/testsuite/gcc.target/powerpc/recip-7.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-7.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-7.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,16 @@ ++/* { dg-do run { target { powerpc*-*-linux* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target ppc_recip_hw } */ ++/* { dg-options "-O3 -ftree-vectorize -ffast-math -mrecip -mpowerpc-gfxopt -mpowerpc-gpopt -mpopcntb" } */ ++ ++/* Check reciprocal estimate functions for accuracy. */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "recip-test.h" +Index: gcc/testsuite/gcc.target/powerpc/altivec-11.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-11.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-11.c (.../ibm/gcc-4_5-branch) +@@ -1,6 +1,6 @@ + /* { dg-do compile { target powerpc*-*-* } } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-O2 -maltivec -mabi=altivec" } */ ++/* { dg-options "-O2 -maltivec -mno-vsx -mabi=altivec" } */ + /* { dg-final { scan-assembler-not "lvx" } } */ + #include + +Index: gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c (.../ibm/gcc-4_5-branch) +@@ -1,6 +1,6 @@ + /* { dg-do compile { target powerpc*-*-* } } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-O -maltivec" } */ ++/* { dg-options "-O -maltivec -mno-vsx" } */ + /* { dg-final { scan-assembler "stvx" } } */ + + #include +Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,22 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O3 -mcpu=power6 -ffast-math" } */ ++/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ ++/* { dg-final { scan-assembler-not "fctiwuz" } } */ ++/* { dg-final { scan-assembler-times "fctidz" 8 } } */ ++/* { dg-final { scan-assembler-not "fctiduz" } } */ ++/* { dg-final { scan-assembler-not "xscvdpsxds" } } */ ++/* { dg-final { scan-assembler-not "xscvdpuxds" } } */ ++ ++void float_to_int (int *dest, float src) { *dest = (int) src; } ++void double_to_int (int *dest, double src) { *dest = (int) src; } ++ ++void float_to_uint (int *dest, float src) { *dest = (unsigned int) src; } ++void double_to_uint (int *dest, double src) { *dest = (unsigned int) src; } ++ ++void float_to_llong (long long *dest, float src) { *dest = (long long) src; } ++void double_to_llong (long long *dest, double src) { *dest = (long long) src; } ++ ++void float_to_ullong (unsigned long long *dest, float src) { *dest = (unsigned long long) src; } ++void double_to_ullong (unsigned long long *dest, double src) { *dest = (unsigned long long) src; } +Index: gcc/testsuite/gcc.target/powerpc/pr48053-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/pr48053-2.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr48053-2.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,38 @@ ++/* Test for ICE arising from VSX code generation. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3 -mcpu=power7" } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++ ++struct timeval ++{ ++ long tv_sec; ++ long tv_usec; ++}; ++ ++extern char *bar (struct timeval *); ++int *error; ++ ++void ++foo (void *ptr) ++{ ++ struct timeval tm; ++ long n1, n2; ++ ++ if (!ptr) ++ { ++ *error = 1; ++ n1 = -1; ++ n2 = -1; ++ } ++ else ++ { ++ n1 = 0; ++ n2 = *error; ++ } ++ ++ tm.tv_sec = n1; ++ tm.tv_usec = n2; ++ ++ if (*error) ++ bar (&tm); ++} +Index: gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,18 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ ++/* { dg-final { scan-assembler "xsmaxdp" } } */ ++/* { dg-final { scan-assembler "xsmindp" } } */ ++ ++float ++do_fmin (float a, float b) ++{ ++ return __builtin_fminf (a, b); ++} ++ ++float ++do_fmax (float a, float b) ++{ ++ return __builtin_fmaxf (a, b); ++} +Index: gcc/testsuite/gcc.target/powerpc/ppc-round.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-round.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-round.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,37 @@ ++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O2 -mcpu=power7" } */ ++/* { dg-final { scan-assembler-times "stfiwx" 4 } } */ ++/* { dg-final { scan-assembler-times "lfiwax" 2 } } */ ++/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ ++/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ ++/* { dg-final { scan-assembler-times "xscvsxddp" 2 } } */ ++/* { dg-final { scan-assembler-times "fcfids" 2 } } */ ++/* { dg-final { scan-assembler-not "lwz" } } */ ++/* { dg-final { scan-assembler-not "stw" } } */ ++ ++/* Make sure we don't have loads/stores to the GPR unit. */ ++double ++round_double_int (double a) ++{ ++ return (double)(int)a; ++} ++ ++float ++round_float_int (float a) ++{ ++ return (float)(int)a; ++} ++ ++double ++round_double_uint (double a) ++{ ++ return (double)(unsigned int)a; ++} ++ ++float ++round_float_uint (float a) ++{ ++ return (float)(unsigned int)a; ++} +Index: gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,183 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math" } */ ++/* { dg-final { scan-assembler-times "xvmadd" 4 } } */ ++/* { dg-final { scan-assembler-times "xsmadd" 2 } } */ ++/* { dg-final { scan-assembler-times "fmadds" 2 } } */ ++/* { dg-final { scan-assembler-times "xvmsub" 2 } } */ ++/* { dg-final { scan-assembler-times "xsmsub" 1 } } */ ++/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ ++/* { dg-final { scan-assembler-times "xvnmadd" 2 } } */ ++/* { dg-final { scan-assembler-times "xsnmadd" 1 } } */ ++/* { dg-final { scan-assembler-times "fnmadds" 1 } } */ ++/* { dg-final { scan-assembler-times "xvnmsub" 2 } } */ ++/* { dg-final { scan-assembler-times "xsnmsub" 1 } } */ ++/* { dg-final { scan-assembler-times "fnmsubs" 1 } } */ ++ ++/* All functions should generate an appropriate (a * b) + c instruction ++ since -mfused-madd is on by default. */ ++ ++double ++builtin_fma (double b, double c, double d) ++{ ++ return __builtin_fma (b, c, d); /* xsmadd{a,m}dp */ ++} ++ ++double ++builtin_fms (double b, double c, double d) ++{ ++ return __builtin_fma (b, c, -d); /* xsmsub{a,b}dp */ ++} ++ ++double ++builtin_fnma (double b, double c, double d) ++{ ++ return - __builtin_fma (b, c, d); /* xsnmadd{a,b}dp */ ++} ++ ++double ++builtin_fnms (double b, double c, double d) ++{ ++ return - __builtin_fma (b, c, -d); /* xsnmsub{a,b}dp */ ++} ++ ++float ++builtin_fmaf (float b, float c, float d) ++{ ++ return __builtin_fmaf (b, c, d); /* fmadds */ ++} ++ ++float ++builtin_fmsf (float b, float c, float d) ++{ ++ return __builtin_fmaf (b, c, -d); /* fmsubs */ ++} ++ ++float ++builtin_fnmaf (float b, float c, float d) ++{ ++ return - __builtin_fmaf (b, c, d); /* fnmadds */ ++} ++ ++float ++builtin_fnmsf (float b, float c, float d) ++{ ++ return - __builtin_fmaf (b, c, -d); /* fnmsubs */ ++} ++ ++double ++normal_fma (double b, double c, double d) ++{ ++ return (b * c) + d; /* xsmadd{a,m}dp */ ++} ++ ++float ++normal_fmaf (float b, float c, float d) ++{ ++ return (b * c) + d; /* fmadds */ ++} ++ ++#ifndef SIZE ++#define SIZE 1024 ++#endif ++ ++double vda[SIZE] __attribute__((__aligned__(32))); ++double vdb[SIZE] __attribute__((__aligned__(32))); ++double vdc[SIZE] __attribute__((__aligned__(32))); ++double vdd[SIZE] __attribute__((__aligned__(32))); ++ ++float vfa[SIZE] __attribute__((__aligned__(32))); ++float vfb[SIZE] __attribute__((__aligned__(32))); ++float vfc[SIZE] __attribute__((__aligned__(32))); ++float vfd[SIZE] __attribute__((__aligned__(32))); ++ ++void ++vector_fma (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vda[i] = __builtin_fma (vdb[i], vdc[i], vdd[i]); /* xvmadd{a,m}dp */ ++} ++ ++void ++vector_fms (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vda[i] = __builtin_fma (vdb[i], vdc[i], -vdd[i]); /* xvmsub{a,m}dp */ ++} ++ ++void ++vector_fnma (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vda[i] = - __builtin_fma (vdb[i], vdc[i], vdd[i]); /* xvnmadd{a,m}dp */ ++} ++ ++void ++vector_fnms (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vda[i] = - __builtin_fma (vdb[i], vdc[i], -vdd[i]); /* xvnmsub{a,m}dp */ ++} ++ ++void ++vector_fmaf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]); /* xvmadd{a,m}sp */ ++} ++ ++void ++vector_fmsf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = __builtin_fmaf (vfb[i], vfc[i], -vfd[i]); /* xvmsub{a,m}sp */ ++} ++ ++void ++vector_fnmaf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = - __builtin_fmaf (vfb[i], vfc[i], vfd[i]); /* xvnmadd{a,m}sp */ ++} ++ ++void ++vector_fnmsf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = - __builtin_fmaf (vfb[i], vfc[i], -vfd[i]); /* xvnmsub{a,m}sp */ ++} ++ ++void ++vnormal_fma (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vda[i] = (vdb[i] * vdc[i]) + vdd[i]; /* xvmadd{a,m}dp */ ++} ++ ++void ++vnormal_fmaf (void) ++{ ++ int i; ++ ++ for (i = 0; i < SIZE; i++) ++ vfa[i] = (vfb[i] * vfc[i]) + vfd[i]; /* xvmadd{a,m}sp */ ++} +Index: gcc/testsuite/gcc.target/powerpc/altivec-types-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c (.../ibm/gcc-4_5-branch) +@@ -1,6 +1,6 @@ + /* { dg-do compile { target powerpc*-*-linux* } } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-maltivec" } */ ++/* { dg-options "-maltivec -mno-vsx" } */ + + /* Valid AltiVec vector types should be accepted with no warnings. */ + +Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,11 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ ++/* { dg-final { scan-assembler "xsrdpiz" } } */ ++/* { dg-final { scan-assembler-not "friz" } } */ ++ ++double round_double_llong (double a) ++{ ++ return (double)(long long)a; ++} +Index: gcc/testsuite/gcc.target/powerpc/pr47755.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/pr47755.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr47755.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,16 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O3 -mcpu=power7" } */ ++/* { dg-final { scan-assembler "xxlxor" } } */ ++/* { dg-final { scan-assembler-not "lxvd2x" } } */ ++/* { dg-final { scan-assembler-not "lxvw4x" } } */ ++/* { dg-final { scan-assembler-not "lvx" } } */ ++ ++/* PR 47755: Compiler loads vector constant of 0 from TOC instead of using ++ xxlxor. */ ++void ++func (vector long long *p) ++{ ++ *p = (vector long long) { 0LL, 0LL }; ++} +Index: gcc/testsuite/gcc.target/i386/fma4-fma-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/i386/fma4-fma-2.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.target/i386/fma4-fma-2.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,67 @@ ++/* Test that the compiler properly optimizes floating point multiply ++ and add instructions into vfmaddss, vfmsubss, vfnmaddss, ++ vfnmsubss on FMA4 systems. */ ++ ++/* { dg-do compile } */ ++/* { dg-require-effective-target lp64 } */ ++/* { dg-options "-O2 -funsafe-math-optimizations -mfma4" } */ ++ ++extern void exit (int); ++ ++float ++flt_mul_add (float a, float c) ++{ ++ return (a * a) + c; ++} ++ ++double ++dbl_mul_add (double a, double c) ++{ ++ return (a * a) + c; ++} ++ ++float ++flt_mul_sub (float a, float c) ++{ ++ return (a * a) - c; ++} ++ ++double ++dbl_mul_sub (double a, double c) ++{ ++ return (a * a) - c; ++} ++ ++float ++flt_neg_mul_add (float a, float c) ++{ ++ return (-(a * a)) + c; ++} ++ ++double ++dbl_neg_mul_add (double a, double c) ++{ ++ return (-(a * a)) + c; ++} ++ ++float f[10] = { 2, 3, 4 }; ++double d[10] = { 2, 3, 4 }; ++ ++int main () ++{ ++ f[3] = flt_mul_add (f[0], f[2]); ++ f[4] = flt_mul_sub (f[0], f[2]); ++ f[5] = flt_neg_mul_add (f[0], f[2]); ++ ++ d[3] = dbl_mul_add (d[0], d[2]); ++ d[4] = dbl_mul_sub (d[0], d[2]); ++ d[5] = dbl_neg_mul_add (d[0], d[2]); ++ exit (0); ++} ++ ++/* { dg-final { scan-assembler "vfmaddss" } } */ ++/* { dg-final { scan-assembler "vfmaddsd" } } */ ++/* { dg-final { scan-assembler "vfmsubss" } } */ ++/* { dg-final { scan-assembler "vfmsubsd" } } */ ++/* { dg-final { scan-assembler "vfnmaddss" } } */ ++/* { dg-final { scan-assembler "vfnmaddsd" } } */ +Index: gcc/testsuite/gcc.dg/torture/builtin-math-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.dg/torture/builtin-math-2.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.dg/torture/builtin-math-2.c (.../ibm/gcc-4_5-branch) +@@ -184,18 +184,6 @@ + fool (__builtin_powl (__LDBL_MAX__, -3.5L)); + TESTIT2 (pow, 2.0, -0x1p50); + +- foof (__builtin_fmaf (__FLT_MAX__, __FLT_MAX__, 0.0F)); +- foof (__builtin_fmaf (__FLT_MAX__, 1.0F, __FLT_MAX__)); +- foof (__builtin_fmaf (__FLT_MIN__, __FLT_MIN__, 0.0F)); +- +- foo (__builtin_fma (__DBL_MAX__, __DBL_MAX__, 0.0)); +- foo (__builtin_fma (__DBL_MAX__, 1.0, __DBL_MAX__)); +- foo (__builtin_fma (__DBL_MIN__, __DBL_MIN__, 0.0)); +- +- fool (__builtin_fmal (__LDBL_MAX__, __LDBL_MAX__, 0.0L)); +- fool (__builtin_fmal (__LDBL_MAX__, 1.0L, __LDBL_MAX__)); +- fool (__builtin_fmal (__LDBL_MIN__, __LDBL_MIN__, 0.0L)); +- + /* The sqrt arg must be [0 ... Inf] inclusive. */ + TESTIT (sqrt, -0.5); + TESTIT (sqrt, -0.0); +@@ -351,9 +339,6 @@ + /* { dg-final { scan-tree-dump-times "powf" 13 "original" { target { ! { spu*-*-* } } } } } */ + /* { dg-final { scan-tree-dump-times "powf" 7 "original" { target { spu*-*-* } } } } */ + /* { dg-final { scan-tree-dump-times "powl" 13 "original" } } */ +-/* { dg-final { scan-tree-dump-times "fma " 3 "original" } } */ +-/* { dg-final { scan-tree-dump-times "fmaf" 3 "original" } } */ +-/* { dg-final { scan-tree-dump-times "fmal" 3 "original" } } */ + /* { dg-final { scan-tree-dump-times "sqrt " 1 "original" } } */ + /* { dg-final { scan-tree-dump-times "sqrtf" 1 "original" } } */ + /* { dg-final { scan-tree-dump-times "sqrtl" 1 "original" } } */ +Index: gcc/testsuite/gcc.dg/torture/builtin-math-8.c +=================================================================== +--- a/src/gcc/testsuite/gcc.dg/torture/builtin-math-8.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.dg/torture/builtin-math-8.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,34 @@ ++/* { dg-do link } */ ++ ++extern void link_error (void); ++ ++int main() ++{ ++ if (!__builtin_constant_p(1.0)) ++ link_error (); ++ if (!__builtin_constant_p(__builtin_fma (1.0, 1.0, 1.0))) ++ link_error (); ++ ++ if (__builtin_constant_p(__builtin_fmaf (__FLT_MAX__, __FLT_MAX__, 0.0F))) ++ link_error (); ++ if (__builtin_constant_p(__builtin_fmaf (__FLT_MAX__, 1.0F, __FLT_MAX__))) ++ link_error (); ++ if (__builtin_constant_p(__builtin_fmaf (__FLT_MIN__, __FLT_MIN__, 0.0F))) ++ link_error (); ++ ++ if (__builtin_constant_p(__builtin_fma (__DBL_MAX__, __DBL_MAX__, 0.0))) ++ link_error (); ++ if (__builtin_constant_p(__builtin_fma (__DBL_MAX__, 1.0, __DBL_MAX__))) ++ link_error (); ++ if (__builtin_constant_p(__builtin_fma (__DBL_MIN__, __DBL_MIN__, 0.0))) ++ link_error (); ++ ++ if (__builtin_constant_p(__builtin_fmal (__LDBL_MAX__, __LDBL_MAX__, 0.0L))) ++ link_error (); ++ if (__builtin_constant_p(__builtin_fmal (__LDBL_MAX__, 1.0L, __LDBL_MAX__))) ++ link_error (); ++ if (__builtin_constant_p(__builtin_fmal (__LDBL_MIN__, __LDBL_MIN__, 0.0L))) ++ link_error (); ++ ++ return 0; ++} +Index: gcc/testsuite/gcc.dg/pr48067.c +=================================================================== +--- a/src/gcc/testsuite/gcc.dg/pr48067.c (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gcc.dg/pr48067.c (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -ffast-math -fno-tree-forwprop -fno-tree-reassoc" } */ ++/* { dg-options "-O2 -ffast-math -fno-tree-forwprop -fno-tree-reassoc -mfma4" { target x86_64-*-* i?86-*-* } } */ ++ ++float ++foo (float x, float cim) ++{ ++ float c = x * cim; ++ float d = -c; ++ return c - d; ++} +Index: gcc/testsuite/ChangeLog.ibm +=================================================================== +--- a/src/gcc/testsuite/ChangeLog.ibm (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/ChangeLog.ibm (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,245 @@ ++2011-03-16 Bill Schmidt ++ ++ Backport from mainline: ++ 2010-09-19 Ira Rosen ++ ++ PR tree-optimization/45714 ++ * gfortran.dg/vect/pr45714-a.f: New test. ++ * gfortran.dg/vect/pr45714-b.f: New test. ++ ++2011-03-11 Peter Bergner ++ ++ Backport proposed mainline patch. ++ ++ PR target/48053 ++ * gcc/testsuite/gcc.target/powerpc/pr48053-1.c: New test. ++ * gcc/testsuite/gcc.target/powerpc/pr48053-2.c: Likewise. ++ ++2011-03-11 Michael Meissner ++ ++ Merge up to gcc-4_5-branch, subversion id 170880. ++ ++2011-03-09 Peter Bergner ++ ++ Backport from mainline ++ 2010-07-02 Ulrich Weigand ++ ++ PR target/44707 ++ * gcc.c-torture/compile/pr44707.c: New test. ++ ++2011-03-09 Michael Meissner ++ ++ Merge up to gcc-4_5-branch, subversion id 170820. ++ ++2011-03-08 Michael Meissner ++ ++ Backport from mainline ++ 2011-03-08 Michael Meissner ++ ++ PR target/47755 ++ * gcc.target/powerpc/pr47755-2.c: New file. ++ ++2011-03-07 Pat Haugen ++ ++ Backport from mainline ++ 2011-03-07 Pat Haugen ++ ++ PR target/47862 ++ * gcc.target/powerpc/pr47862.c: New. ++ ++2011-02-15 Michael Meissner ++ ++ Backport from mainline ++ 2011-02-15 Michael Meissner ++ ++ PR target/47755 ++ * gcc.target/powerpc/pr47755.c: New file, test all 0 vector ++ constant does not generate a load from memory. ++ ++2011-02-03 Michael Meissner ++ ++ Backport from the GCC 4.6 mainline: ++ 2011-02-02 Michael Meissner ++ ++ PR target/47272 ++ * gcc.target/powerpc/vsx-builtin-8.c: New file, test vec_vsx_ld ++ and vec_vsx_st. ++ ++ * gcc.target/powerpc/avoid-indexed-addresses.c: Disable altivec ++ and vsx so a default --with-cpu=power7 doesn't give an error ++ when -mavoid-indexed-addresses is used. ++ ++ * gcc.target/powerpc/ppc32-abi-dfp-1.c: Rewrite to use an asm ++ wrapper function to save the arguments and then jump to the real ++ function, rather than depending on the compiler not to move stuff ++ before an asm. ++ * gcc.target/powerpc/ppc64-abi-dfp-2.c: Ditto. ++ ++2011-01-24 Michael Meissner ++ ++ Backport from the GCC 4.6 mainline: ++ 2011-01-24 Michael Meissner ++ ++ PR target/47408 ++ * gcc.target/powerpc/altivec-11.c: Add explicit -mno-vsx. ++ * gcc.target/powerpc/altivec-14.c: Ditto. ++ * gcc.target/powerpc/altivec-33.c: Ditto. ++ * gcc.target/powerpc/altivec-types-1.c: Ditto. ++ * gcc.target/powerpc/altivec-types-2.c: Ditto. ++ * gcc.target/powerpc/altivec-types-3.c: Ditto. ++ * gcc.target/powerpc/altivec-types-4.c: Ditto. ++ * gcc.target/powerpc/ppc-vector-memcpy.c: Ditto. ++ * gcc.target/powerpc/ppc-vector-memset.c: Ditto. ++ * g++.dg/ext/altivec-15.C: Ditto. ++ * g++.dg/ext/altivec-types-1.C: Ditto. ++ * g++.dg/ext/altivec-types-2.C: Ditto. ++ * g++.dg/ext/altivec-types-3.C: Ditto. ++ * g++.dg/ext/altivec-types-4.C: Ditto. ++ ++2010-11-30 Michael Meissner ++ ++ Backport from the GCC 4.6 mainline: ++ 2010-11-30 Michael Meissner ++ ++ * gcc.target/powerpc/ppc-fma-7.c: New file, test that (a*b)+c and ++ (a*b)-c generates two fma instructions, instead of separate ++ multiply, add, and subtract. ++ ++ Backport from the GCC 4.6 mainline: ++ 2010-10-14 Michael Meissner ++ ++ * gcc.target/powerpc/ppc-fma-6.c: Ditto. ++ ++ Backport from the GCC 4.6 mainline: ++ 2010-11-30 Richard Guenther ++ ++ PR tree-optimization/46722 ++ * gcc.target/i386/fma4-fma-2.c: New testcase. ++ ++2010-11-24 Michael Meissner ++ ++ Backport from the GCC 4.6 mainline ++ 2010-11-09 Michael Meissner ++ ++ * gcc.target/powerpc/ppc-round.c: New file, test (double)(int) ++ optimization. ++ ++ * gcc.target/powerpc/ppc-fpconv-2.c: Update # times lfiwax is ++ expected. ++ ++ Backport from the GCC 4.6 mainline ++ 2010-11-15 Richard Henderson ++ ++ * gcc.dg/torture/builtin-math-2.c: Split out fma tests... ++ * gcc.dg/torture/builtin-math-8.c: ... here. New file. ++ Use builtin_constant_p rather than scanning for builtin name. ++ ++ Backport from the GCC 4.6 mainline ++ 2010-11-16 Richard Henderson ++ ++ * gcc.target/powerpc/ppc-fma-2.c: Use -ffp-contract=off. ++ * gcc.target/powerpc/ppc-fma-4.c: Likewise. ++ ++2010-11-23 Michael Meissner ++ ++ Merge up to gcc-4_5-branch revision 167090. ++ ++2010-11-15 Michael Meissner ++ ++ Backport from mainline ++ 2010-11-09 Michael Meissner ++ ++ * gcc.target/powerpc/ppc-fpconv-11.c: Use -mcpu=power5+, not ++ power5 to enable generation of FRIZ. ++ ++ Backport from mainline ++ 2010-06-02 Michael Meissner ++ ++ * lib/target-supports.exp (is-effective-target): Add vsx_hw, ++ ppc_recip_hw. ++ (is-effective-target-keyword): Ditto. ++ ++2010-11-08 Pat Haugen ++ Backport from mainline ++ 2010-11-04 Pat Haugen ++ ++ * gcc.target/powerpc/loop_align.c: New. ++ ++2010-11-03 Michael Meissner ++ ++ Backport from mainline ++ 2010-11-03 Michael Meissner ++ ++ * gcc.target/powerpc/vsx-sfminmax.c: New test for using double ++ precision min/max for single precision on VSX. ++ ++2010-10-19 Michael Meissner ++ ++ * gcc.target/powerpc/ppc-fma-6.c: Delete, we aren't supportting ++ -msoft-float in AT 4.0, at least at present. ++ ++2010-10-14 Michael Meissner ++ ++ Backport from mainline ++ 2010-10-14 Michael Meissner ++ ++ * gcc.target/powerpc/ppc-fma-1.c: New tests for powerpc FMA ++ builtin combiner patterns. ++ * gcc.target/powerpc/ppc-fma-2.c: Ditto. ++ * gcc.target/powerpc/ppc-fma-3.c: Ditto. ++ * gcc.target/powerpc/ppc-fma-4.c: Ditto. ++ * gcc.target/powerpc/ppc-fma-5.c: Ditto. ++ * gcc.target/powerpc/ppc-fma-6.c: Ditto. ++ ++2010-09-02 Michael Meissner ++ ++ Backport from mainline ++ 2010-09-02 Michael Meissner ++ ++ * gcc.target/powerpc/ppc-fpconv-10.c: New file to test generating ++ FRIZ/XSRIZ instruciton for (double)(long long)x. ++ * gcc.target/powerpc/ppc-fpconv-11.c: Ditto. ++ ++2010-08-31 Michael Meissner ++ ++ Backport from mainline: ++ 2010-08-23 Michael Meissner ++ ++ * gcc.target/powerpc/ppc-fpconv-1.c: New test for integer to ++ floating point conversion code generation. ++ * gcc.target/powerpc/ppc-fpconv-2.c: Ditto. ++ * gcc.target/powerpc/ppc-fpconv-3.c: Ditto. ++ * gcc.target/powerpc/ppc-fpconv-4.c: Ditto. ++ * gcc.target/powerpc/ppc-fpconv-5.c: New test for floating point ++ to integer conversion code generation. ++ * gcc.target/powerpc/ppc-fpconv-6.c: Ditto. ++ * gcc.target/powerpc/ppc-fpconv-7.c: Ditto. ++ * gcc.target/powerpc/ppc-fpconv-8.c: Ditto. ++ * gcc.target/powerpc/ppc-fpconv-9.c: Ditto. ++ ++ Backport from mainline: ++ 2010-08-18 Michael Meissner ++ ++ * gcc.target/powerpc/vsx-mass-1.c: New file, test ++ -mveclibabi=mass. ++ ++2010-08-26 Michael Meissner ++ ++ Backport from the mainline: ++ 2010-06-02 Michael Meissner ++ ++ PR target/44218 ++ * gcc.target/powerpc/recip-1.c: New test for -mrecip support. ++ * gcc.target/powerpc/recip-2.c: Ditto. ++ * gcc.target/powerpc/recip-3.c: Ditto. ++ * gcc.target/powerpc/recip-4.c: Ditto. ++ * gcc.target/powerpc/recip-5.c: Ditto. ++ * gcc.target/powerpc/recip-6.c: Ditto. ++ * gcc.target/powerpc/recip-7.c: Ditto. ++ * gcc.target/powerpc/recip-test.h: Ditto. ++ * gcc.target/powerpc/recip-test2.h: Ditto. ++ ++2010-08-12 Michael Meissner ++ ++ Clone from gcc-4_5-branch, subversion id 163203. ++ +Index: gcc/testsuite/g++.dg/ext/altivec-types-2.C +=================================================================== +--- a/src/gcc/testsuite/g++.dg/ext/altivec-types-2.C (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/g++.dg/ext/altivec-types-2.C (.../ibm/gcc-4_5-branch) +@@ -1,7 +1,7 @@ + /* { dg-do compile { target powerpc*-*-linux* } } */ + /* { dg-require-effective-target ilp32 } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-maltivec" } */ ++/* { dg-options "-maltivec -mno-vsx" } */ + + /* These should get warnings for 32-bit code. */ + +Index: gcc/testsuite/g++.dg/ext/altivec-types-3.C +=================================================================== +--- a/src/gcc/testsuite/g++.dg/ext/altivec-types-3.C (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/g++.dg/ext/altivec-types-3.C (.../ibm/gcc-4_5-branch) +@@ -1,7 +1,7 @@ + /* { dg-do compile { target powerpc*-*-linux* } } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ + /* { dg-require-effective-target lp64 } */ +-/* { dg-options "-maltivec" } */ ++/* { dg-options "-maltivec -mno-vsx" } */ + + /* These should be rejected for 64-bit code. */ + +Index: gcc/testsuite/g++.dg/ext/altivec-15.C +=================================================================== +--- a/src/gcc/testsuite/g++.dg/ext/altivec-15.C (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/g++.dg/ext/altivec-15.C (.../ibm/gcc-4_5-branch) +@@ -1,6 +1,6 @@ + /* { dg-do compile { target powerpc*-*-* } } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-maltivec" } */ ++/* { dg-options "-maltivec -mno-vsx" } */ + + /* This test was added for an internal compiler error. The number and + content of error messages is irrelevant. */ +Index: gcc/testsuite/g++.dg/ext/altivec-types-4.C +=================================================================== +--- a/src/gcc/testsuite/g++.dg/ext/altivec-types-4.C (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/g++.dg/ext/altivec-types-4.C (.../ibm/gcc-4_5-branch) +@@ -1,7 +1,7 @@ + /* { dg-do compile { target powerpc*-*-linux* } } */ + /* { dg-require-effective-target ilp32 } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-maltivec -mno-warn-altivec-long" } */ ++/* { dg-options "-maltivec -mno-vsx -mno-warn-altivec-long" } */ + + /* These should not get warnings for 32-bit code when the warning is + disabled. */ +Index: gcc/testsuite/g++.dg/ext/altivec-types-1.C +=================================================================== +--- a/src/gcc/testsuite/g++.dg/ext/altivec-types-1.C (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/g++.dg/ext/altivec-types-1.C (.../ibm/gcc-4_5-branch) +@@ -1,6 +1,6 @@ + /* { dg-do compile { target powerpc*-*-linux* } } */ + /* { dg-require-effective-target powerpc_altivec_ok } */ +-/* { dg-options "-maltivec -std=c++98" } */ ++/* { dg-options "-maltivec -mno-vsx -std=c++98" } */ + + /* Valid AltiVec vector types should be accepted with no warnings. */ + +Index: gcc/testsuite/lib/target-supports.exp +=================================================================== +--- a/src/gcc/testsuite/lib/target-supports.exp (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/lib/target-supports.exp (.../ibm/gcc-4_5-branch) +@@ -1118,6 +1118,30 @@ + }] + } + ++proc check_ppc_recip_hw_available { } { ++ return [check_cached_effective_target ppc_recip_hw_available { ++ # Some simulators may not support FRE/FRES/FRSQRTE/FRSQRTES ++ # For now, disable on Darwin ++ if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} { ++ expr 0 ++ } else { ++ set options "-mpowerpc-gfxopt -mpowerpc-gpopt -mpopcntb" ++ check_runtime_nocache ppc_recip_hw_available { ++ volatile double d_recip, d_rsqrt, d_four = 4.0; ++ volatile float f_recip, f_rsqrt, f_four = 4.0f; ++ int main() ++ { ++ asm volatile ("fres %0,%1" : "=f" (f_recip) : "f" (f_four)); ++ asm volatile ("fre %0,%1" : "=d" (d_recip) : "d" (d_four)); ++ asm volatile ("frsqrtes %0,%1" : "=f" (f_rsqrt) : "f" (f_four)); ++ asm volatile ("frsqrte %0,%1" : "=f" (d_rsqrt) : "d" (d_four)); ++ return 0; ++ } ++ } $options ++ } ++ }] ++} ++ + # Return 1 if the target supports executing AltiVec and Cell PPU + # instructions, 0 otherwise. Cache the result. + +@@ -3000,6 +3024,8 @@ + } else { + switch $arg { + "vmx_hw" { set selected [check_vmx_hw_available] } ++ "vsx_hw" { set selected [check_vsx_hw_available] } ++ "ppc_recip_hw" { set selected [check_ppc_recip_hw_available] } + "named_sections" { set selected [check_named_sections_available] } + "gc_sections" { set selected [check_gc_sections_available] } + "cxa_atexit" { set selected [check_cxa_atexit_available] } +@@ -3019,6 +3045,8 @@ + # These have different names for their check_* procs. + switch $arg { + "vmx_hw" { return 1 } ++ "vsx_hw" { return 1 } ++ "ppc_recip_hw" { return 1 } + "named_sections" { return 1 } + "gc_sections" { return 1 } + "cxa_atexit" { return 1 } +Index: gcc/testsuite/gfortran.dg/vect/pr45714-a.f +=================================================================== +--- a/src/gcc/testsuite/gfortran.dg/vect/pr45714-a.f (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gfortran.dg/vect/pr45714-a.f (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,27 @@ ++! { dg-do compile { target x86_64-*-* } } ++! { dg-options "-O3 -march=core2 -mavx -ffast-math -mveclibabi=svml" } ++ ++ integer index(18),i,j,k,l,ipiv(18),info,ichange,neq,lda,ldb, ++ & nrhs,iplas ++ real*8 ep0(6),al10(18),al20(18),dg0(18),ep(6),al1(18), ++ & al2(18),dg(18),ddg(18),xm(6,18),h(18,18),ck(18),cn(18), ++ & c(18),d(18),phi(18),delta(18),r0(18),q(18),b(18),cphi(18), ++ & q1(18),q2(18),stri(6),htri(18),sg(18),r(42),xmc(6,18),aux(18), ++ & t(42),gl(18,18),gr(18,18),ee(6),c1111,c1122,c1212,dd, ++ & skl(3,3),xmtran(3,3),ddsdde(6,6),xx(6,18) ++ do ++ do i=1,18 ++ htri(i)=dabs(sg(i))-r0(i)-ck(i)*(dg(i)/dtime)**(1.d0/cn(i)) ++ do j=1,18 ++ enddo ++ enddo ++ do ++ if(i.ne.j) then ++ gr(index(i),1)=htri(i) ++ endif ++ call dgesv(neq,nrhs,gl,lda,ipiv,gr,ldb,info) ++ enddo ++ enddo ++ end ++ ++! { dg-final { cleanup-tree-dump "vect" } } +Index: gcc/testsuite/gfortran.dg/vect/pr45714-b.f +=================================================================== +--- a/src/gcc/testsuite/gfortran.dg/vect/pr45714-b.f (.../gcc-4_5-branch) ++++ b/src/gcc/testsuite/gfortran.dg/vect/pr45714-b.f (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,27 @@ ++! { dg-do compile { target powerpc*-*-* } } ++! { dg-options "-O3 -mcpu=power7 -ffast-math -mveclibabi=mass" } ++ ++ integer index(18),i,j,k,l,ipiv(18),info,ichange,neq,lda,ldb, ++ & nrhs,iplas ++ real*8 ep0(6),al10(18),al20(18),dg0(18),ep(6),al1(18), ++ & al2(18),dg(18),ddg(18),xm(6,18),h(18,18),ck(18),cn(18), ++ & c(18),d(18),phi(18),delta(18),r0(18),q(18),b(18),cphi(18), ++ & q1(18),q2(18),stri(6),htri(18),sg(18),r(42),xmc(6,18),aux(18), ++ & t(42),gl(18,18),gr(18,18),ee(6),c1111,c1122,c1212,dd, ++ & skl(3,3),xmtran(3,3),ddsdde(6,6),xx(6,18) ++ do ++ do i=1,18 ++ htri(i)=dabs(sg(i))-r0(i)-ck(i)*(dg(i)/dtime)**(1.d0/cn(i)) ++ do j=1,18 ++ enddo ++ enddo ++ do ++ if(i.ne.j) then ++ gr(index(i),1)=htri(i) ++ endif ++ call dgesv(neq,nrhs,gl,lda,ipiv,gr,ldb,info) ++ enddo ++ enddo ++ end ++ ++! { dg-final { cleanup-tree-dump "vect" } } +Index: gcc/df-scan.c +=================================================================== +--- a/src/gcc/df-scan.c (.../gcc-4_5-branch) ++++ b/src/gcc/df-scan.c (.../ibm/gcc-4_5-branch) +@@ -1,6 +1,6 @@ + /* Scanning of rtl for dataflow analysis. + Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, +- 2008, 2009, 2010 Free Software Foundation, Inc. ++ 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + Originally contributed by Michael P. Hayes + (m.hayes@elec.canterbury.ac.nz, mhayes@redhat.com) + Major rewrite contributed by Danny Berlin (dberlin@dberlin.org) +@@ -3492,18 +3492,21 @@ + DF_REF_CALL_STACK_USAGE | flags, + -1, -1, VOIDmode); + +- /* Calls may also reference any of the global registers, +- so they are recorded as used. */ +- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) +- if (global_regs[i]) +- { +- df_ref_record (DF_REF_BASE, collection_rec, regno_reg_rtx[i], +- NULL, bb, insn_info, DF_REF_REG_USE, flags, -1, -1, +- VOIDmode); +- df_ref_record (DF_REF_BASE, collection_rec, regno_reg_rtx[i], +- NULL, bb, insn_info, DF_REF_REG_DEF, flags, -1, -1, +- VOIDmode); +- } ++ /* Calls to const functions cannot access any global registers and calls to ++ pure functions cannot set them. All other calls may reference any of the ++ global registers, so they are recorded as used. */ ++ if (!RTL_CONST_CALL_P (insn_info->insn)) ++ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) ++ if (global_regs[i]) ++ { ++ df_ref_record (DF_REF_BASE, collection_rec, regno_reg_rtx[i], ++ NULL, bb, insn_info, DF_REF_REG_USE, flags, -1, -1, ++ VOIDmode); ++ if (!RTL_PURE_CALL_P (insn_info->insn)) ++ df_ref_record (DF_REF_BASE, collection_rec, regno_reg_rtx[i], ++ NULL, bb, insn_info, DF_REF_REG_DEF, flags, -1, -1, ++ VOIDmode); ++ } + + is_sibling_call = SIBLING_CALL_P (insn_info->insn); + EXECUTE_IF_SET_IN_BITMAP (regs_invalidated_by_call_regset, 0, ui, bi) +Index: gcc/tree-ssa-ccp.c +=================================================================== +--- a/src/gcc/tree-ssa-ccp.c (.../gcc-4_5-branch) ++++ b/src/gcc/tree-ssa-ccp.c (.../ibm/gcc-4_5-branch) +@@ -1115,6 +1115,39 @@ + gimple_expr_type (stmt), op0, op1); + } + ++ case GIMPLE_TERNARY_RHS: ++ { ++ /* Handle ternary operators that can appear in GIMPLE form. */ ++ tree op0 = gimple_assign_rhs1 (stmt); ++ tree op1 = gimple_assign_rhs2 (stmt); ++ tree op2 = gimple_assign_rhs3 (stmt); ++ ++ /* Simplify the operands down to constants when appropriate. */ ++ if (TREE_CODE (op0) == SSA_NAME) ++ { ++ prop_value_t *val = get_value (op0); ++ if (val->lattice_val == CONSTANT) ++ op0 = val->value; ++ } ++ ++ if (TREE_CODE (op1) == SSA_NAME) ++ { ++ prop_value_t *val = get_value (op1); ++ if (val->lattice_val == CONSTANT) ++ op1 = val->value; ++ } ++ ++ if (TREE_CODE (op2) == SSA_NAME) ++ { ++ prop_value_t *val = get_value (op2); ++ if (val->lattice_val == CONSTANT) ++ op2 = val->value; ++ } ++ ++ return fold_ternary_loc (loc, subcode, ++ gimple_expr_type (stmt), op0, op1, op2); ++ } ++ + default: + gcc_unreachable (); + } +@@ -2959,6 +2992,34 @@ + } + break; + ++ ++ case GIMPLE_TERNARY_RHS: ++ result = fold_ternary_loc (loc, subcode, ++ TREE_TYPE (gimple_assign_lhs (stmt)), ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), ++ gimple_assign_rhs3 (stmt)); ++ ++ if (result) ++ { ++ STRIP_USELESS_TYPE_CONVERSION (result); ++ if (valid_gimple_rhs_p (result)) ++ return result; ++ ++ /* Fold might have produced non-GIMPLE, so if we trust it blindly ++ we lose canonicalization opportunities. Do not go again ++ through fold here though, or the same non-GIMPLE will be ++ produced. */ ++ if (commutative_ternary_tree_code (subcode) ++ && tree_swap_operands_p (gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), false)) ++ return build3 (subcode, TREE_TYPE (gimple_assign_lhs (stmt)), ++ gimple_assign_rhs2 (stmt), ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs3 (stmt)); ++ } ++ break; ++ + case GIMPLE_INVALID_RHS: + gcc_unreachable (); + } +Index: gcc/tree-ssa-math-opts.c +=================================================================== +--- a/src/gcc/tree-ssa-math-opts.c (.../gcc-4_5-branch) ++++ b/src/gcc/tree-ssa-math-opts.c (.../ibm/gcc-4_5-branch) +@@ -1,5 +1,5 @@ + /* Global, SSA-based optimizations using mathematical identities. +- Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 ++ Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + This file is part of GCC. +@@ -1266,6 +1266,526 @@ + 0, /* properties_provided */ + 0, /* properties_destroyed */ + 0, /* todo_flags_start */ +- 0 /* todo_flags_finish */ ++ TODO_verify_ssa ++ | TODO_verify_stmts ++ | TODO_dump_func ++ | TODO_update_ssa /* todo_flags_finish */ + } + }; ++ ++/* Return true if RHS is a suitable operand for a widening multiplication. ++ There are two cases: ++ ++ - RHS makes some value twice as wide. Store that value in *NEW_RHS_OUT ++ if so, and store its type in *TYPE_OUT. ++ ++ - RHS is an integer constant. Store that value in *NEW_RHS_OUT if so, ++ but leave *TYPE_OUT untouched. */ ++ ++static bool ++is_widening_mult_rhs_p (tree rhs, tree *type_out, tree *new_rhs_out) ++{ ++ gimple stmt; ++ tree type, type1, rhs1; ++ enum tree_code rhs_code; ++ ++ if (TREE_CODE (rhs) == SSA_NAME) ++ { ++ type = TREE_TYPE (rhs); ++ stmt = SSA_NAME_DEF_STMT (rhs); ++ if (!is_gimple_assign (stmt)) ++ return false; ++ ++ rhs_code = gimple_assign_rhs_code (stmt); ++ if (TREE_CODE (type) == INTEGER_TYPE ++ ? !CONVERT_EXPR_CODE_P (rhs_code) ++ : rhs_code != FIXED_CONVERT_EXPR) ++ return false; ++ ++ rhs1 = gimple_assign_rhs1 (stmt); ++ type1 = TREE_TYPE (rhs1); ++ if (TREE_CODE (type1) != TREE_CODE (type) ++ || TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type)) ++ return false; ++ ++ *new_rhs_out = rhs1; ++ *type_out = type1; ++ return true; ++ } ++ ++ if (TREE_CODE (rhs) == INTEGER_CST) ++ { ++ *new_rhs_out = rhs; ++ *type_out = NULL; ++ return true; ++ } ++ ++ return false; ++} ++ ++/* Return true if STMT performs a widening multiplication. If so, ++ store the unwidened types of the operands in *TYPE1_OUT and *TYPE2_OUT ++ respectively. Also fill *RHS1_OUT and *RHS2_OUT such that converting ++ those operands to types *TYPE1_OUT and *TYPE2_OUT would give the ++ operands of the multiplication. */ ++ ++static bool ++is_widening_mult_p (gimple stmt, ++ tree *type1_out, tree *rhs1_out, ++ tree *type2_out, tree *rhs2_out) ++{ ++ tree type; ++ ++ type = TREE_TYPE (gimple_assign_lhs (stmt)); ++ if (TREE_CODE (type) != INTEGER_TYPE ++ && TREE_CODE (type) != FIXED_POINT_TYPE) ++ return false; ++ ++ if (!is_widening_mult_rhs_p (gimple_assign_rhs1 (stmt), type1_out, rhs1_out)) ++ return false; ++ ++ if (!is_widening_mult_rhs_p (gimple_assign_rhs2 (stmt), type2_out, rhs2_out)) ++ return false; ++ ++ if (*type1_out == NULL) ++ { ++ if (*type2_out == NULL || !int_fits_type_p (*rhs1_out, *type2_out)) ++ return false; ++ *type1_out = *type2_out; ++ } ++ ++ if (*type2_out == NULL) ++ { ++ if (!int_fits_type_p (*rhs2_out, *type1_out)) ++ return false; ++ *type2_out = *type1_out; ++ } ++ ++ return true; ++} ++ ++/* Process a single gimple statement STMT, which has a MULT_EXPR as ++ its rhs, and try to convert it into a WIDEN_MULT_EXPR. The return ++ value is true iff we converted the statement. */ ++ ++static bool ++convert_mult_to_widen (gimple stmt) ++{ ++ tree lhs, rhs1, rhs2, type, type1, type2; ++ enum insn_code handler; ++ ++ lhs = gimple_assign_lhs (stmt); ++ type = TREE_TYPE (lhs); ++ if (TREE_CODE (type) != INTEGER_TYPE) ++ return false; ++ ++ if (!is_widening_mult_p (stmt, &type1, &rhs1, &type2, &rhs2)) ++ return false; ++ ++ if (TYPE_UNSIGNED (type1) && TYPE_UNSIGNED (type2)) ++ handler = optab_handler (umul_widen_optab, TYPE_MODE (type))->insn_code; ++ else if (!TYPE_UNSIGNED (type1) && !TYPE_UNSIGNED (type2)) ++ handler = optab_handler (smul_widen_optab, TYPE_MODE (type))->insn_code; ++ else ++ handler = optab_handler (usmul_widen_optab, TYPE_MODE (type))->insn_code; ++ ++ if (handler == CODE_FOR_nothing) ++ return false; ++ ++ gimple_assign_set_rhs1 (stmt, fold_convert (type1, rhs1)); ++ gimple_assign_set_rhs2 (stmt, fold_convert (type2, rhs2)); ++ gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR); ++ update_stmt (stmt); ++ return true; ++} ++ ++/* Process a single gimple statement STMT, which is found at the ++ iterator GSI and has a either a PLUS_EXPR or a MINUS_EXPR as its ++ rhs (given by CODE), and try to convert it into a ++ WIDEN_MULT_PLUS_EXPR or a WIDEN_MULT_MINUS_EXPR. The return value ++ is true iff we converted the statement. */ ++ ++static bool ++convert_plusminus_to_widen (gimple_stmt_iterator *gsi, gimple stmt, ++ enum tree_code code) ++{ ++ gimple rhs1_stmt = NULL, rhs2_stmt = NULL; ++ tree type, type1, type2; ++ tree lhs, rhs1, rhs2, mult_rhs1, mult_rhs2, add_rhs; ++ enum tree_code rhs1_code = ERROR_MARK, rhs2_code = ERROR_MARK; ++ optab this_optab; ++ enum tree_code wmult_code; ++ ++ lhs = gimple_assign_lhs (stmt); ++ type = TREE_TYPE (lhs); ++ if (TREE_CODE (type) != INTEGER_TYPE ++ && TREE_CODE (type) != FIXED_POINT_TYPE) ++ return false; ++ ++ if (code == MINUS_EXPR) ++ wmult_code = WIDEN_MULT_MINUS_EXPR; ++ else ++ wmult_code = WIDEN_MULT_PLUS_EXPR; ++ ++ rhs1 = gimple_assign_rhs1 (stmt); ++ rhs2 = gimple_assign_rhs2 (stmt); ++ ++ if (TREE_CODE (rhs1) == SSA_NAME) ++ { ++ rhs1_stmt = SSA_NAME_DEF_STMT (rhs1); ++ if (is_gimple_assign (rhs1_stmt)) ++ rhs1_code = gimple_assign_rhs_code (rhs1_stmt); ++ } ++ else ++ return false; ++ ++ if (TREE_CODE (rhs2) == SSA_NAME) ++ { ++ rhs2_stmt = SSA_NAME_DEF_STMT (rhs2); ++ if (is_gimple_assign (rhs2_stmt)) ++ rhs2_code = gimple_assign_rhs_code (rhs2_stmt); ++ } ++ else ++ return false; ++ ++ if (code == PLUS_EXPR && rhs1_code == MULT_EXPR) ++ { ++ if (!is_widening_mult_p (rhs1_stmt, &type1, &mult_rhs1, ++ &type2, &mult_rhs2)) ++ return false; ++ add_rhs = rhs2; ++ } ++ else if (rhs2_code == MULT_EXPR) ++ { ++ if (!is_widening_mult_p (rhs2_stmt, &type1, &mult_rhs1, ++ &type2, &mult_rhs2)) ++ return false; ++ add_rhs = rhs1; ++ } ++ else if (code == PLUS_EXPR && rhs1_code == WIDEN_MULT_EXPR) ++ { ++ mult_rhs1 = gimple_assign_rhs1 (rhs1_stmt); ++ mult_rhs2 = gimple_assign_rhs2 (rhs1_stmt); ++ type1 = TREE_TYPE (mult_rhs1); ++ type2 = TREE_TYPE (mult_rhs2); ++ add_rhs = rhs2; ++ } ++ else if (rhs2_code == WIDEN_MULT_EXPR) ++ { ++ mult_rhs1 = gimple_assign_rhs1 (rhs2_stmt); ++ mult_rhs2 = gimple_assign_rhs2 (rhs2_stmt); ++ type1 = TREE_TYPE (mult_rhs1); ++ type2 = TREE_TYPE (mult_rhs2); ++ add_rhs = rhs1; ++ } ++ else ++ return false; ++ ++ if (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2)) ++ return false; ++ ++ /* Verify that the machine can perform a widening multiply ++ accumulate in this mode/signedness combination, otherwise ++ this transformation is likely to pessimize code. */ ++ this_optab = optab_for_tree_code (wmult_code, type1, optab_default); ++ if (optab_handler (this_optab, TYPE_MODE (type))->insn_code ++ == CODE_FOR_nothing) ++ return false; ++ ++ /* ??? May need some type verification here? */ ++ ++ gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code, ++ fold_convert (type1, mult_rhs1), ++ fold_convert (type2, mult_rhs2), ++ add_rhs); ++ update_stmt (gsi_stmt (*gsi)); ++ return true; ++} ++ ++/* Combine the multiplication at MUL_STMT with operands MULOP1 and MULOP2 ++ with uses in additions and subtractions to form fused multiply-add ++ operations. Returns true if successful and MUL_STMT should be removed. */ ++ ++static bool ++convert_mult_to_fma (gimple mul_stmt, tree op1, tree op2) ++{ ++ tree mul_result = gimple_get_lhs (mul_stmt); ++ tree type = TREE_TYPE (mul_result); ++ gimple use_stmt, neguse_stmt, fma_stmt; ++ use_operand_p use_p; ++ imm_use_iterator imm_iter; ++ ++ if (FLOAT_TYPE_P (type) ++ && flag_fp_contract_mode == FP_CONTRACT_OFF) ++ return false; ++ ++ /* We don't want to do bitfield reduction ops. */ ++ if (INTEGRAL_TYPE_P (type) ++ && (TYPE_PRECISION (type) ++ != GET_MODE_PRECISION (TYPE_MODE (type)))) ++ return false; ++ ++ /* If the target doesn't support it, don't generate it. We assume that ++ if fma isn't available then fms, fnma or fnms are not either. */ ++ if (optab_handler (fma_optab, TYPE_MODE (type))->insn_code ++ == CODE_FOR_nothing) ++ return false; ++ ++ /* Make sure that the multiplication statement becomes dead after ++ the transformation, thus that all uses are transformed to FMAs. ++ This means we assume that an FMA operation has the same cost ++ as an addition. */ ++ FOR_EACH_IMM_USE_FAST (use_p, imm_iter, mul_result) ++ { ++ enum tree_code use_code; ++ tree result = mul_result; ++ bool negate_p = false; ++ ++ use_stmt = USE_STMT (use_p); ++ ++ if (is_gimple_debug (use_stmt)) ++ continue; ++ ++ /* For now restrict this operations to single basic blocks. In theory ++ we would want to support sinking the multiplication in ++ m = a*b; ++ if () ++ ma = m + c; ++ else ++ d = m; ++ to form a fma in the then block and sink the multiplication to the ++ else block. */ ++ if (gimple_bb (use_stmt) != gimple_bb (mul_stmt)) ++ return false; ++ ++ if (!is_gimple_assign (use_stmt)) ++ return false; ++ ++ use_code = gimple_assign_rhs_code (use_stmt); ++ ++ /* A negate on the multiplication leads to FNMA. */ ++ if (use_code == NEGATE_EXPR) ++ { ++ ssa_op_iter iter; ++ tree use; ++ ++ result = gimple_assign_lhs (use_stmt); ++ ++ /* Make sure the negate statement becomes dead with this ++ single transformation. */ ++ if (!single_imm_use (gimple_assign_lhs (use_stmt), ++ &use_p, &neguse_stmt)) ++ return false; ++ ++ /* Make sure the multiplication isn't also used on that stmt. */ ++ FOR_EACH_SSA_TREE_OPERAND (use, neguse_stmt, iter, SSA_OP_USE) ++ if (use == mul_result) ++ return false; ++ ++ /* Re-validate. */ ++ use_stmt = neguse_stmt; ++ if (gimple_bb (use_stmt) != gimple_bb (mul_stmt)) ++ return false; ++ if (!is_gimple_assign (use_stmt)) ++ return false; ++ ++ use_code = gimple_assign_rhs_code (use_stmt); ++ negate_p = true; ++ } ++ ++ switch (use_code) ++ { ++ case MINUS_EXPR: ++ if (gimple_assign_rhs2 (use_stmt) == result) ++ negate_p = !negate_p; ++ break; ++ case PLUS_EXPR: ++ break; ++ default: ++ /* FMA can only be formed from PLUS and MINUS. */ ++ return false; ++ } ++ ++ /* We can't handle a * b + a * b. */ ++ if (gimple_assign_rhs1 (use_stmt) == gimple_assign_rhs2 (use_stmt)) ++ return false; ++ ++ /* While it is possible to validate whether or not the exact form ++ that we've recognized is available in the backend, the assumption ++ is that the transformation is never a loss. For instance, suppose ++ the target only has the plain FMA pattern available. Consider ++ a*b-c -> fma(a,b,-c): we've exchanged MUL+SUB for FMA+NEG, which ++ is still two operations. Consider -(a*b)-c -> fma(-a,b,-c): we ++ still have 3 operations, but in the FMA form the two NEGs are ++ independant and could be run in parallel. */ ++ } ++ ++ FOR_EACH_IMM_USE_STMT (use_stmt, imm_iter, mul_result) ++ { ++ gimple_stmt_iterator gsi = gsi_for_stmt (use_stmt); ++ enum tree_code use_code; ++ tree addop, mulop1 = op1, result = mul_result; ++ bool negate_p = false; ++ ++ if (is_gimple_debug (use_stmt)) ++ continue; ++ ++ use_code = gimple_assign_rhs_code (use_stmt); ++ if (use_code == NEGATE_EXPR) ++ { ++ result = gimple_assign_lhs (use_stmt); ++ single_imm_use (gimple_assign_lhs (use_stmt), &use_p, &neguse_stmt); ++ gsi_remove (&gsi, true); ++ release_defs (use_stmt); ++ ++ use_stmt = neguse_stmt; ++ gsi = gsi_for_stmt (use_stmt); ++ use_code = gimple_assign_rhs_code (use_stmt); ++ negate_p = true; ++ } ++ ++ if (gimple_assign_rhs1 (use_stmt) == result) ++ { ++ addop = gimple_assign_rhs2 (use_stmt); ++ /* a * b - c -> a * b + (-c) */ ++ if (gimple_assign_rhs_code (use_stmt) == MINUS_EXPR) ++ addop = force_gimple_operand_gsi (&gsi, ++ build1 (NEGATE_EXPR, ++ type, addop), ++ true, NULL_TREE, true, ++ GSI_SAME_STMT); ++ } ++ else ++ { ++ addop = gimple_assign_rhs1 (use_stmt); ++ /* a - b * c -> (-b) * c + a */ ++ if (gimple_assign_rhs_code (use_stmt) == MINUS_EXPR) ++ negate_p = !negate_p; ++ } ++ ++ if (negate_p) ++ mulop1 = force_gimple_operand_gsi (&gsi, ++ build1 (NEGATE_EXPR, ++ type, mulop1), ++ true, NULL_TREE, true, ++ GSI_SAME_STMT); ++ ++ fma_stmt = gimple_build_assign_with_ops3 (FMA_EXPR, ++ gimple_assign_lhs (use_stmt), ++ mulop1, op2, ++ addop); ++ gsi_replace (&gsi, fma_stmt, true); ++ } ++ ++ return true; ++} ++ ++/* Find integer multiplications where the operands are extended from ++ smaller types, and replace the MULT_EXPR with a WIDEN_MULT_EXPR ++ where appropriate. */ ++ ++static unsigned int ++execute_optimize_widening_mul (void) ++{ ++ basic_block bb; ++ bool cfg_changed = false; ++ ++ FOR_EACH_BB (bb) ++ { ++ gimple_stmt_iterator gsi; ++ ++ for (gsi = gsi_after_labels (bb); !gsi_end_p (gsi);) ++ { ++ gimple stmt = gsi_stmt (gsi); ++ enum tree_code code; ++ ++ if (is_gimple_assign (stmt)) ++ { ++ code = gimple_assign_rhs_code (stmt); ++ switch (code) ++ { ++ case MULT_EXPR: ++ if (!convert_mult_to_widen (stmt) ++ && convert_mult_to_fma (stmt, ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt))) ++ { ++ gsi_remove (&gsi, true); ++ release_defs (stmt); ++ continue; ++ } ++ break; ++ ++ case PLUS_EXPR: ++ case MINUS_EXPR: ++ convert_plusminus_to_widen (&gsi, stmt, code); ++ break; ++ ++ default:; ++ } ++ } ++ else if (is_gimple_call (stmt) ++ && gimple_call_lhs (stmt)) ++ { ++ tree fndecl = gimple_call_fndecl (stmt); ++ if (fndecl ++ && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL) ++ { ++ switch (DECL_FUNCTION_CODE (fndecl)) ++ { ++ case BUILT_IN_POWF: ++ case BUILT_IN_POW: ++ case BUILT_IN_POWL: ++ if (TREE_CODE (gimple_call_arg (stmt, 1)) == REAL_CST ++ && REAL_VALUES_EQUAL (TREE_REAL_CST (gimple_call_arg (stmt, 1)), dconst2) ++ && convert_mult_to_fma (stmt, ++ gimple_call_arg (stmt, 0), ++ gimple_call_arg (stmt, 0))) ++ { ++ unlink_stmt_vdef (stmt); ++ gsi_remove (&gsi, true); ++ release_defs (stmt); ++ if (gimple_purge_dead_eh_edges (bb)) ++ cfg_changed = true; ++ continue; ++ } ++ break; ++ ++ default:; ++ } ++ } ++ } ++ gsi_next (&gsi); ++ } ++ } ++ ++ return cfg_changed ? TODO_cleanup_cfg : 0; ++} ++ ++static bool ++gate_optimize_widening_mul (void) ++{ ++ return flag_expensive_optimizations && optimize; ++} ++ ++struct gimple_opt_pass pass_optimize_widening_mul = ++{ ++ { ++ GIMPLE_PASS, ++ "widening_mul", /* name */ ++ gate_optimize_widening_mul, /* gate */ ++ execute_optimize_widening_mul, /* execute */ ++ NULL, /* sub */ ++ NULL, /* next */ ++ 0, /* static_pass_number */ ++ TV_NONE, /* tv_id */ ++ PROP_ssa, /* properties_required */ ++ 0, /* properties_provided */ ++ 0, /* properties_destroyed */ ++ 0, /* todo_flags_start */ ++ TODO_verify_ssa ++ | TODO_verify_stmts ++ | TODO_dump_func ++ | TODO_update_ssa /* todo_flags_finish */ ++ } ++}; +Index: gcc/tree-ssa-dom.c +=================================================================== +--- a/src/gcc/tree-ssa-dom.c (.../gcc-4_5-branch) ++++ b/src/gcc/tree-ssa-dom.c (.../ibm/gcc-4_5-branch) +@@ -54,6 +54,7 @@ + EXPR_SINGLE, + EXPR_UNARY, + EXPR_BINARY, ++ EXPR_TERNARY, + EXPR_CALL + }; + +@@ -65,6 +66,7 @@ + struct { tree rhs; } single; + struct { enum tree_code op; tree opnd; } unary; + struct { enum tree_code op; tree opnd0; tree opnd1; } binary; ++ struct { enum tree_code op; tree opnd0, opnd1, opnd2; } ternary; + struct { tree fn; bool pure; size_t nargs; tree *args; } call; + } ops; + }; +@@ -230,6 +232,14 @@ + expr->ops.binary.opnd0 = gimple_assign_rhs1 (stmt); + expr->ops.binary.opnd1 = gimple_assign_rhs2 (stmt); + break; ++ case GIMPLE_TERNARY_RHS: ++ expr->kind = EXPR_TERNARY; ++ expr->type = TREE_TYPE (gimple_assign_lhs (stmt)); ++ expr->ops.ternary.op = subcode; ++ expr->ops.ternary.opnd0 = gimple_assign_rhs1 (stmt); ++ expr->ops.ternary.opnd1 = gimple_assign_rhs2 (stmt); ++ expr->ops.ternary.opnd2 = gimple_assign_rhs3 (stmt); ++ break; + default: + gcc_unreachable (); + } +@@ -333,7 +343,7 @@ + + static bool + hashable_expr_equal_p (const struct hashable_expr *expr0, +- const struct hashable_expr *expr1) ++ const struct hashable_expr *expr1) + { + tree type0 = expr0->type; + tree type1 = expr1->type; +@@ -392,6 +402,25 @@ + expr1->ops.binary.opnd0, 0)); + } + ++ case EXPR_TERNARY: ++ if (expr0->ops.ternary.op != expr1->ops.ternary.op ++ || !operand_equal_p (expr0->ops.ternary.opnd2, ++ expr1->ops.ternary.opnd2, 0)) ++ return false; ++ ++ if (operand_equal_p (expr0->ops.ternary.opnd0, ++ expr1->ops.ternary.opnd0, 0) ++ && operand_equal_p (expr0->ops.ternary.opnd1, ++ expr1->ops.ternary.opnd1, 0)) ++ return true; ++ ++ /* For commutative ops, allow the other order. */ ++ return (commutative_ternary_tree_code (expr0->ops.ternary.op) ++ && operand_equal_p (expr0->ops.ternary.opnd0, ++ expr1->ops.ternary.opnd1, 0) ++ && operand_equal_p (expr0->ops.ternary.opnd1, ++ expr1->ops.ternary.opnd0, 0)); ++ + case EXPR_CALL: + { + size_t i; +@@ -462,6 +491,19 @@ + } + break; + ++ case EXPR_TERNARY: ++ val = iterative_hash_object (expr->ops.ternary.op, val); ++ if (commutative_ternary_tree_code (expr->ops.ternary.op)) ++ val = iterative_hash_exprs_commutative (expr->ops.ternary.opnd0, ++ expr->ops.ternary.opnd1, val); ++ else ++ { ++ val = iterative_hash_expr (expr->ops.ternary.opnd0, val); ++ val = iterative_hash_expr (expr->ops.ternary.opnd1, val); ++ } ++ val = iterative_hash_expr (expr->ops.ternary.opnd2, val); ++ break; ++ + case EXPR_CALL: + { + size_t i; +@@ -514,6 +556,16 @@ + print_generic_expr (stream, element->expr.ops.binary.opnd1, 0); + break; + ++ case EXPR_TERNARY: ++ fprintf (stream, " %s <", tree_code_name[element->expr.ops.ternary.op]); ++ print_generic_expr (stream, element->expr.ops.ternary.opnd0, 0); ++ fputs (", ", stream); ++ print_generic_expr (stream, element->expr.ops.ternary.opnd1, 0); ++ fputs (", ", stream); ++ print_generic_expr (stream, element->expr.ops.ternary.opnd2, 0); ++ fputs (">", stream); ++ break; ++ + case EXPR_CALL: + { + size_t i; +Index: gcc/rtl.def +=================================================================== +--- a/src/gcc/rtl.def (.../gcc-4_5-branch) ++++ b/src/gcc/rtl.def (.../ibm/gcc-4_5-branch) +@@ -706,6 +706,9 @@ + /* Unsigned saturating truncate. */ + DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY) + ++/* Floating point multiply/add combined instruction. */ ++DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY) ++ + /* Information about the variable and its location. */ + /* Changed 'te' to 'tei'; the 'i' field is for recording + initialization status of variables. */ +Index: gcc/config.in +=================================================================== +--- a/src/gcc/config.in (.../gcc-4_5-branch) ++++ b/src/gcc/config.in (.../ibm/gcc-4_5-branch) +@@ -1168,6 +1168,12 @@ + #endif + + ++/* Define if your PowerPC64 linker supports a large TOC. */ ++#ifndef USED_FOR_TARGET ++#undef HAVE_LD_LARGE_TOC ++#endif ++ ++ + /* Define if your PowerPC64 linker only needs function descriptor syms. */ + #ifndef USED_FOR_TARGET + #undef HAVE_LD_NO_DOT_SYMS +Index: gcc/expr.c +=================================================================== +--- a/src/gcc/expr.c (.../gcc-4_5-branch) ++++ b/src/gcc/expr.c (.../ibm/gcc-4_5-branch) +@@ -7229,7 +7229,7 @@ + gimple subexp0_def, subexp1_def; + tree top0, top1; + location_t loc = ops->location; +- tree treeop0, treeop1; ++ tree treeop0, treeop1, treeop2; + #define REDUCE_BIT_FIELD(expr) (reduce_bit_field \ + ? reduce_to_bit_field_precision ((expr), \ + target, \ +@@ -7242,12 +7242,14 @@ + + treeop0 = ops->op0; + treeop1 = ops->op1; ++ treeop2 = ops->op2; + + /* We should be called only on simple (binary or unary) expressions, + exactly those that are valid in gimple expressions that aren't + GIMPLE_SINGLE_RHS (or invalid). */ + gcc_assert (get_gimple_rhs_class (code) == GIMPLE_UNARY_RHS +- || get_gimple_rhs_class (code) == GIMPLE_BINARY_RHS); ++ || get_gimple_rhs_class (code) == GIMPLE_BINARY_RHS ++ || get_gimple_rhs_class (code) == GIMPLE_TERNARY_RHS); + + ignore = (target == const0_rtx + || ((CONVERT_EXPR_CODE_P (code) +@@ -7679,6 +7681,141 @@ + + goto binop2; + ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, EXPAND_NORMAL); ++ op2 = expand_normal (treeop2); ++ target = expand_widen_pattern_expr (ops, op0, op1, op2, ++ target, unsignedp); ++ return target; ++ ++ case WIDEN_MULT_EXPR: ++ /* If first operand is constant, swap them. ++ Thus the following special case checks need only ++ check the second operand. */ ++ if (TREE_CODE (treeop0) == INTEGER_CST) ++ { ++ tree t1 = treeop0; ++ treeop0 = treeop1; ++ treeop1 = t1; ++ } ++ ++ /* First, check if we have a multiplication of one signed and one ++ unsigned operand. */ ++ if (TREE_CODE (treeop1) != INTEGER_CST ++ && (TYPE_UNSIGNED (TREE_TYPE (treeop0)) ++ != TYPE_UNSIGNED (TREE_TYPE (treeop1)))) ++ { ++ enum machine_mode innermode = TYPE_MODE (TREE_TYPE (treeop0)); ++ this_optab = usmul_widen_optab; ++ if (mode == GET_MODE_2XWIDER_MODE (innermode)) ++ { ++ if (optab_handler (this_optab, mode)->insn_code ++ != CODE_FOR_nothing) ++ { ++ if (TYPE_UNSIGNED (TREE_TYPE (treeop0))) ++ expand_operands (treeop0, treeop1, subtarget, &op0, &op1, ++ EXPAND_NORMAL); ++ else ++ expand_operands (treeop0, treeop1, subtarget, &op1, &op0, ++ EXPAND_NORMAL); ++ goto binop3; ++ } ++ } ++ } ++ /* Check for a multiplication with matching signedness. */ ++ else if ((TREE_CODE (treeop1) == INTEGER_CST ++ && int_fits_type_p (treeop1, TREE_TYPE (treeop0))) ++ || (TYPE_UNSIGNED (TREE_TYPE (treeop1)) ++ == TYPE_UNSIGNED (TREE_TYPE (treeop0)))) ++ { ++ tree op0type = TREE_TYPE (treeop0); ++ enum machine_mode innermode = TYPE_MODE (op0type); ++ bool zextend_p = TYPE_UNSIGNED (op0type); ++ optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab; ++ this_optab = zextend_p ? umul_widen_optab : smul_widen_optab; ++ ++ if (mode == GET_MODE_2XWIDER_MODE (innermode)) ++ { ++ if (optab_handler (this_optab, mode)->insn_code ++ != CODE_FOR_nothing) ++ { ++ expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, ++ EXPAND_NORMAL); ++ temp = expand_widening_mult (mode, op0, op1, target, ++ unsignedp, this_optab); ++ return REDUCE_BIT_FIELD (temp); ++ } ++ if ((optab_handler (other_optab, mode)->insn_code ++ != CODE_FOR_nothing) ++ && innermode == word_mode) ++ { ++ rtx htem, hipart; ++ op0 = expand_normal (treeop0); ++ if (TREE_CODE (treeop1) == INTEGER_CST) ++ op1 = convert_modes (innermode, mode, ++ expand_normal (treeop1), unsignedp); ++ else ++ op1 = expand_normal (treeop1); ++ temp = expand_binop (mode, other_optab, op0, op1, target, ++ unsignedp, OPTAB_LIB_WIDEN); ++ hipart = gen_highpart (innermode, temp); ++ htem = expand_mult_highpart_adjust (innermode, hipart, ++ op0, op1, hipart, ++ zextend_p); ++ if (htem != hipart) ++ emit_move_insn (hipart, htem); ++ return REDUCE_BIT_FIELD (temp); ++ } ++ } ++ } ++ treeop0 = fold_build1 (CONVERT_EXPR, type, treeop0); ++ treeop1 = fold_build1 (CONVERT_EXPR, type, treeop1); ++ expand_operands (treeop0, treeop1, subtarget, &op0, &op1, EXPAND_NORMAL); ++ return REDUCE_BIT_FIELD (expand_mult (mode, op0, op1, target, unsignedp)); ++ ++ case FMA_EXPR: ++ { ++ optab opt = fma_optab; ++ gimple def0, def2; ++ ++ def0 = get_def_for_expr (treeop0, NEGATE_EXPR); ++ def2 = get_def_for_expr (treeop2, NEGATE_EXPR); ++ ++ op0 = op2 = NULL; ++ ++ if (def0 && def2 ++ && optab_handler (fnms_optab, mode)->insn_code != CODE_FOR_nothing) ++ { ++ opt = fnms_optab; ++ op0 = expand_normal (gimple_assign_rhs1 (def0)); ++ op2 = expand_normal (gimple_assign_rhs1 (def2)); ++ } ++ else if (def0 ++ && (optab_handler (fnma_optab, mode)->insn_code ++ != CODE_FOR_nothing)) ++ { ++ opt = fnma_optab; ++ op0 = expand_normal (gimple_assign_rhs1 (def0)); ++ } ++ else if (def2 ++ && (optab_handler (fms_optab, mode)->insn_code ++ != CODE_FOR_nothing)) ++ { ++ opt = fms_optab; ++ op2 = expand_normal (gimple_assign_rhs1 (def2)); ++ } ++ ++ if (op0 == NULL) ++ op0 = expand_expr (treeop0, subtarget, VOIDmode, EXPAND_NORMAL); ++ if (op2 == NULL) ++ op2 = expand_normal (treeop2); ++ op1 = expand_normal (treeop1); ++ ++ return expand_ternary_op (TYPE_MODE (type), opt, ++ op0, op1, op2, target, 0); ++ } ++ + case MULT_EXPR: + /* If this is a fixed-point operation, then we cannot use the code + below because "expand_mult" doesn't support sat/no-sat fixed-point +Index: gcc/opts.c +=================================================================== +--- a/src/gcc/opts.c (.../gcc-4_5-branch) ++++ b/src/gcc/opts.c (.../ibm/gcc-4_5-branch) +@@ -67,6 +67,9 @@ + bool warn_frame_larger_than; + HOST_WIDE_INT frame_larger_than_size; + ++/* Floating-point contraction mode, fast by default. */ ++enum fp_contract_mode flag_fp_contract_mode = FP_CONTRACT_FAST; ++ + /* Type(s) of debugging information we are producing (if any). See + flags.h for the definitions of the different possible types of + debugging information. */ +@@ -1773,6 +1776,18 @@ + return 0; + break; + ++ case OPT_ffp_contract_: ++ if (!strcmp (arg, "on")) ++ /* Not implemented, fall back to conservative FP_CONTRACT_OFF. */ ++ flag_fp_contract_mode = FP_CONTRACT_OFF; ++ else if (!strcmp (arg, "off")) ++ flag_fp_contract_mode = FP_CONTRACT_OFF; ++ else if (!strcmp (arg, "fast")) ++ flag_fp_contract_mode = FP_CONTRACT_FAST; ++ else ++ error ("unknown floating point contraction style \"%s\"", arg); ++ break; ++ + case OPT_fexcess_precision_: + if (!strcmp (arg, "fast")) + flag_excess_precision_cmdline = EXCESS_PRECISION_FAST; +Index: gcc/gimple-pretty-print.c +=================================================================== +--- a/src/gcc/gimple-pretty-print.c (.../gcc-4_5-branch) ++++ b/src/gcc/gimple-pretty-print.c (.../ibm/gcc-4_5-branch) +@@ -377,6 +377,43 @@ + } + + ++/* Helper for dump_gimple_assign. Print the ternary RHS of the ++ assignment GS. BUFFER, SPC and FLAGS are as in dump_gimple_stmt. */ ++ ++static void ++dump_ternary_rhs (pretty_printer *buffer, gimple gs, int spc, int flags) ++{ ++ const char *p; ++ enum tree_code code = gimple_assign_rhs_code (gs); ++ switch (code) ++ { ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ for (p = tree_code_name [(int) code]; *p; p++) ++ pp_character (buffer, TOUPPER (*p)); ++ pp_string (buffer, " <"); ++ dump_generic_node (buffer, gimple_assign_rhs1 (gs), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, gimple_assign_rhs2 (gs), spc, flags, false); ++ pp_string (buffer, ", "); ++ dump_generic_node (buffer, gimple_assign_rhs3 (gs), spc, flags, false); ++ pp_character (buffer, '>'); ++ break; ++ ++ case FMA_EXPR: ++ dump_generic_node (buffer, gimple_assign_rhs1 (gs), spc, flags, false); ++ pp_string (buffer, " * "); ++ dump_generic_node (buffer, gimple_assign_rhs2 (gs), spc, flags, false); ++ pp_string (buffer, " + "); ++ dump_generic_node (buffer, gimple_assign_rhs3 (gs), spc, flags, false); ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++} ++ ++ + /* Dump the gimple assignment GS. BUFFER, SPC and FLAGS are as in + dump_gimple_stmt. */ + +@@ -418,6 +455,8 @@ + dump_unary_rhs (buffer, gs, spc, flags); + else if (gimple_num_ops (gs) == 3) + dump_binary_rhs (buffer, gs, spc, flags); ++ else if (gimple_num_ops (gs) == 4) ++ dump_ternary_rhs (buffer, gs, spc, flags); + else + gcc_unreachable (); + if (!(flags & TDF_RHS_ONLY)) +@@ -831,6 +870,14 @@ + gimple_debug_bind_get_value (gs)); + break; + ++ case FMA_EXPR: ++ dump_generic_node (buffer, gimple_assign_rhs1 (gs), spc, flags, false); ++ pp_string (buffer, " * "); ++ dump_generic_node (buffer, gimple_assign_rhs2 (gs), spc, flags, false); ++ pp_string (buffer, " + "); ++ dump_generic_node (buffer, gimple_assign_rhs3 (gs), spc, flags, false); ++ break; ++ + default: + gcc_unreachable (); + } +Index: gcc/configure.ac +=================================================================== +--- a/src/gcc/configure.ac (.../gcc-4_5-branch) ++++ b/src/gcc/configure.ac (.../ibm/gcc-4_5-branch) +@@ -3993,6 +3993,36 @@ + AC_DEFINE(HAVE_LD_NO_DOT_SYMS, 1, + [Define if your PowerPC64 linker only needs function descriptor syms.]) + fi ++ ++ AC_CACHE_CHECK(linker large toc support, ++ gcc_cv_ld_large_toc, ++ [gcc_cv_ld_large_toc=no ++ if test $in_tree_ld = yes ; then ++ if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 21 -o "$gcc_cv_gld_major_version" -gt 2; then ++ gcc_cv_ld_large_toc=yes ++ fi ++ elif test x$gcc_cv_as != x -a x$gcc_cv_ld != x ; then ++ cat > conftest.s < /dev/null 2>&1 \ ++ && $gcc_cv_ld -melf64ppc --no-toc-sort -o conftest conftest.o > /dev/null 2>&1; then ++ gcc_cv_ld_large_toc=yes ++ fi ++ rm -f conftest conftest.o conftest.s ++ fi ++ ]) ++ if test x"$gcc_cv_ld_large_toc" = xyes; then ++ AC_DEFINE(HAVE_LD_LARGE_TOC, 1, ++ [Define if your PowerPC64 linker supports a large TOC.]) ++ fi + ;; + esac + +Index: gcc/ChangeLog.ibm +=================================================================== +--- a/src/gcc/ChangeLog.ibm (.../gcc-4_5-branch) ++++ b/src/gcc/ChangeLog.ibm (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,1277 @@ ++2011-03-26 Alan Modra ++ ++ * config/rs6000/predicates.md (word_offset_memref_op): Handle ++ cmodel medium addresses. ++ * config/rs6000/rs6000.c (rs6000_secondary_reload): Handle misaligned ++ 64-bit gpr loads and stores. ++ (rs6000_secondary_reload_ppc64): New function. ++ * config/rs6000/rs6000-protos.h: Declare it. ++ * config/rs6000/rs6000.md (reload_di_store, reload_di_load): New. ++ ++2011-03-26 Alan Modra ++ ++ PR target/47487 ++ * config/rs6000/rs6000.c (rs6000_output_function_epilogue): Support ++ GNU Go in traceback table. ++ ++2011-03-21 Michael Meissner ++ ++ Merge up to 171269 (includes fix for PR target/48192). ++ * REVISION: Update subversion id. ++ ++2011-03-21 Michael Meissner ++ ++ AT 4.0-1 submitted to UIUC. ++ ++2011-03-16 Bill Schmidt ++ ++ Backport from mainline: ++ 2010-09-19 Ira Rosen ++ ++ PR tree-optimization/45714 ++ * tree-vect-stmts.c (vect_transform_stmt): Use a dummy statement ++ created in vectorizable_call instead of the original statement in ++ def stmt updates. ++ ++ Backport from mainline: ++ 2011-03-16 Alan Modra ++ ++ PR target/45844 ++ * config/rs6000/rs6000.c (rs6000_legitimize_reload_address): Don't ++ create invalid offset address for vsx splat insn. ++ * config/rs6000/predicates.md (splat_input_operand): New. ++ * config/rs6000/vsx.md (vsx_splat_*): Use it. ++ ++2011-03-15 Pat Haugen ++ ++ PR target/47862 ++ * caller-save.c (insert_restore, insert_save): Use non-validate ++ form of adjust_address. ++ ++2011-03-15 Alan Modra ++ ++ PR target/48032 ++ * config/rs6000/rs6000.c (offsettable_ok_by_alignment): Return ++ false for BLKmode and VOIDmode. ++ ++2011-03-14 Michael Meissner ++ ++ Backport from mainline: ++ 2011-03-14 Michael Meissner ++ ++ PR target/48053 ++ * config/rs6000/rs6000.md (movdi split for 32-bit): Don't split up ++ 64-bit constants being loaded into registers other than GPRs such ++ as loading 0 into a VSX register. ++ ++2011-03-11 Peter Bergner ++ ++ Backport proposed mainline patch. ++ ++ PR target/48053 ++ * config/rs6000/predicates.md (easy_vector_constant_add_self, ++ easy_vector_constant_msb): Do not handle V2DImode and V2DFmode. ++ * config/rs6000/rs6000.c (const_vector_elt_as_int): Add assert that ++ mode is not V2DImode or V2DFmode. ++ (vspltis_constant): Do not handle V2DImode and V2DFmode. ++ (rs6000_expand_vector_init): Replace copy_to_reg with copy_to_mode_reg. ++ * config/rs6000/rs6000.md (movdi_internal32): Allow setting VSX ++ registers to 0. ++ (movdi_internal64): Likewise. ++ ++2011-03-11 Bill Schmidt ++ ++ Backport from mainline ++ 2011-03-11 Richard Guenther ++ ++ PR tree-optimization/48067 ++ * tree-ssa-math-opts.c (convert_mult_to_fma): Verify the ++ multiplication result will be only used once on the target stmt. ++ ++ * gcc.dg/pr48067.c: New testcase. ++ ++2011-03-11 Michael Meissner ++ ++ Merge up to gcc-4_5-branch, subversion id 170880. ++ * REVISION: Update subversion id. ++ ++2011-03-09 Peter Bergner ++ ++ Backport from mainline ++ 2010-07-02 Ulrich Weigand ++ ++ PR target/44707 ++ * config/rs6000/rs6000.c (rs6000_legitimize_reload_address): Recognize ++ (lo_sum (high ...) ...) patterns generated by earlier passes. ++ ++2011-03-09 Michael Meissner ++ ++ Merge up to gcc-4_5-branch, subversion id 170820. ++ * REVISION: Update subversion id. ++ ++2011-03-09 Alan Modra ++ ++ PR target/48032 ++ * config/rs6000/rs6000.c (offsettable_ok_by_alignment): Do not ++ presume symbol_refs without a symbol_ref_decl are suitably ++ aligned, nor other trees we may see here. Handle anchor symbols. ++ (legitimate_constant_pool_address_p): Comment. Add mode param. ++ Check cmodel=medium addresses. Adjust all calls. ++ (rs6000_emit_move): Don't call offsettable_ok_by_alignment on ++ creating cmodel=medium optimized access to locals. ++ * config/rs6000/constraints.md (R): Pass QImode to ++ legitimate_constant_pool_address_p. ++ * config/rs6000/predicates.md (input_operand): Pass mode to ++ legitimate_constant_pool_address_p. ++ * config/rs6000/rs6000-protos.h (legitimate_constant_pool_address_p): ++ Update prototype. ++ ++2011-03-08 Michael Meissner ++ ++ Merge up to gcc-4_5-branch, subversion id 170745. ++ * REVISION: Update subversion id. ++ ++2011-03-08 Michael Meissner ++ ++ Backport from mainline ++ 2011-03-08 Michael Meissner ++ ++ PR target/47755 ++ * config/rs6000/rs6000.c (easy_altivec_constant): Correctly handle ++ V2DI/V2DF constants. Only all 0's or all 1's are easy. ++ (output_vec_const_move): Ditto. ++ ++2011-03-09 Alan Modra ++ ++ * config/rs6000/linux.h (TARGET_ASM_FILE_END): Don't define. ++ * config/rs6000/linux64.h (TARGET_ASM_FILE_END): Don't define. ++ * config/rs6000/sysv4.h (TARGET_ASM_FILE_END): Define. ++ * config/rs6000/rs6000-protos.h (init_cumulative_args): Add fndecl and ++ return_mode args. ++ * config/rs6000/rs6000.h (CUMULATIVE_ARGS): Add "escapes". ++ (INIT_CUMULATIVE_ARGS): Pass FNDECL, VOIDmode. ++ (INIT_CUMULATIVE_INCOMING_ARGS): Pass current_function_decl, VOIDmode. ++ (INIT_CUMULATIVE_LIBCALL_ARGS): Pass NULL_TREE, MODE. ++ * config/rs6000/rs6000.c ++ (rs6000_elf_end_indicate_exec_stack): Rename to.. ++ (rs6000_elf_file_end): ..this. Only call file_end_indicate_exec_stack ++ for POWERPC_LINUX. Move code emitting .gnu_attribute to here, from.. ++ (rs6000_file_start): ..here. ++ (rs6000_passes_float, rs6000_passes_vector, rs6000_returns_struct): New ++ file scope variables. ++ (call_ABI_of_interest): New function. ++ (init_cumulative_args): Set above vars when function return value ++ is a float, vector, or small struct. ++ (rs6000_function_arg_advance_1): Likewise for function args. ++ (rs6000_va_start): Set rs6000_passes_float if variable arg function ++ references float args. ++ ++2011-03-07 Pat Haugen ++ ++ Backport from mainline ++ 2011-03-07 Pat Haugen ++ ++ PR target/47862 ++ * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Define. ++ ++2011-03-02 Bill Schmidt ++ ++ Backport 2010-12-07 changes by Richard Guenther to fix LTC ++ bugzilla 70276. ++ ++ * tree-ssa-math-opts.c (execute_optimize_widening_mul): Only ++ process calls with LHS present; unlink virtual definitions when ++ converting pow (n, 2.0) to n*n. ++ ++2011-03-02 Alan Modra ++ ++ PR target/47935 ++ * config/rs6000/predicates.md (lwa_operand): Check cmodel medium ++ toc relative addresses for valid offsets. ++ ++2011-02-21 Alan Modra ++ ++ * config/rs6000/rs6000.c (offsettable_ok_by_alignment): Return ++ false for STRING_CST. ++ ++2011-02-15 Michael Meissner ++ ++ Backport from mainline ++ 2011-02-15 Michael Meissner ++ ++ PR target/47755 ++ * config/rs6000/predicates.md (easy_vector_constant): Allow V2DI ++ mode for vector constants. Remove code that checks for TImode. ++ ++2011-02-15 Alan Modra ++ ++ Backport from mainline ++ 2010-11-01 Alan Modra ++ PR target/46030 ++ * config/rs6000/rs6000.c (struct rs6000_stack): Add reload_completed ++ and savres_strategy. ++ (stack_info): New file scope var. ++ (rs6000_init_machine_status): Init stack_info. ++ (SAVRES_INLINE_FPRS, SAVRES_INLINE_GPRS, ++ SAVRES_NOINLINE_GPRS_SAVES_LR, SAVRES_NOINLINE_FPRS_SAVES_LR, ++ SAVRES_NOINLINE_FPRS_DOESNT_RESTORE_LR): Replace with.. ++ (SAVE_INLINE_FPRS, SAVE_INLINE_GPRS, REST_INLINE_FPRS, REST_INLINE_GPRS, ++ SAVE_NOINLINE_GPRS_SAVES_LR, SAVE_NOINLINE_FPRS_SAVES_LR ++ REST_NOINLINE_FPRS_DOESNT_RESTORE_LR): ..this. Update all refs. ++ (rs6000_savres_strategy): Rewrite. ++ (rs6000_stack_info): Use "stack_info" in place of local "info". ++ Return cached stack info when reload_completed unless ENABLE_CHECKING ++ in which case confirm newly calculated stack info matches old info. ++ Delay calculation of lr_save_p, set it for out of line gp save/restore ++ as well as fp. Call rs6000_savres_strategy from here.. ++ (rs6000_emit_prologue, rs6000_emit_epilogue): ..rather than here. ++ (rs6000_output_function_prologue): Use info->savres_strategy to ++ determine whether fp save/restore externs need to be emitted. ++ ++2011-02-14 Peter Bergner ++ ++ Backport from mainline ++ 2011-01-21 Alan Modra ++ ++ * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Add ++ builtin_define __CMODEL_MEDIUM__ and __CMODEL_LARGE__. ++ ++2011-02-14 Peter Bergner ++ ++ Backport from mainline ++ 2011-02-02 Peter Bergner ++ ++ PR rtl-optimization/47525 ++ * df-scan.c: Update copyright years. ++ (df_get_call_refs): Do not mark global registers as DF_REF_REG_USE ++ and non-clobber DF_REF_REG_DEF for calls to const and pure functions. ++ ++2011-02-04 Michael Meissner ++ ++ Merge up to gcc-4_5-branch, subversion id 169837. ++ * REVISION: Update subversion id. ++ ++2011-02-03 Michael Meissner ++ ++ Backport from mainline: ++ 2011-01-31 Alan Modra ++ ++ * config/rs6000/rs6000.c (print_operand): Rearrange addends in ++ toc relative expressions as we do in print_operand_address. ++ ++2011-02-03 Michael Meissner ++ ++ Backport from mainline: ++ 2011-02-02 Michael Meissner ++ ++ PR target/47272 ++ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): ++ Document using vector double with the load/store builtins, and ++ that the load/store builtins always use Altivec instructions. ++ ++ * config/rs6000/vector.md (vector_altivec_load_): New insns ++ to use altivec memory instructions, even on VSX. ++ (vector_altivec_store_): Ditto. ++ ++ * config/rs6000/rs6000-protos.h (rs6000_address_for_altivec): New ++ function. ++ ++ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add ++ V2DF, V2DI support to load/store overloaded builtins. ++ ++ * config/rs6000/rs6000-builtin.def (ALTIVEC_BUILTIN_*): Add ++ altivec load/store builtins for V2DF/V2DI types. ++ ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't ++ set avoid indexed addresses on power6 if -maltivec. ++ (altivec_expand_ld_builtin): Add V2DF, V2DI support, use ++ vector_altivec_load/vector_altivec_store builtins. ++ (altivec_expand_st_builtin): Ditto. ++ (altivec_expand_builtin): Add VSX memory builtins. ++ (rs6000_init_builtins): Add V2DI types to internal types. ++ (altivec_init_builtins): Add support for V2DF/V2DI altivec ++ load/store builtins. ++ (rs6000_address_for_altivec): Insure memory address is appropriate ++ for Altivec. ++ ++ * config/rs6000/vsx.md (vsx_load_): New expanders for ++ vec_vsx_ld and vec_vsx_st. ++ (vsx_store_): Ditto. ++ ++ * config/rs6000/rs6000.h (RS6000_BTI_long_long): New type ++ variables to hold long long types for VSX vector memory builtins. ++ (RS6000_BTI_unsigned_long_long): Ditto. ++ (long_long_integer_type_internal_node): Ditti. ++ (long_long_unsigned_type_internal_node): Ditti. ++ ++ * config/rs6000/altivec.md (UNSPEC_LVX): New UNSPEC. ++ (altivec_lvx_): Make altivec_lvx use a mode iterator. ++ (altivec_stvx_): Make altivec_stvx use a mode iterator. ++ ++ * config/rs6000/altivec.h (vec_vsx_ld): Define VSX memory builtin ++ short cuts. ++ (vec_vsx_st): Ditto. ++ ++ Backport from mainline: ++ 2011-02-01 Michael Meissner ++ ++ PR target/47580 ++ * config/rs6000/vsx.md (vsx_float2): Use ++ gpc_reg_operand instead of vsx_register_operand to match rs6000.md ++ generator functions. ++ (vsx_floatuns2): Ditto. ++ (vsx_fix_trunc2): Ditto. ++ (vsx_fixuns_trunc2): Ditto. ++ ++ Backport from mainline: ++ 2011-01-13 Michael Meissner ++ ++ PR target/47251 ++ * config/rs6000/rs6000.md (floatunsdidf2): Add check for hardware ++ floating point. ++ (floatunsdidf2_fcfidu): Ditto. ++ ++2011-01-24 Michael Meissner ++ ++ Backport from the GCC 4.6 mainline: ++ 2011-01-24 Michael Meissner ++ ++ PR target/47385 ++ * config/rs6000/altivec.md (vector constant splitters): Add ++ support for creating vector single precision constants if -mvsx is ++ used and we would create the constant using Altivec primitives. ++ ++2010-12-08 Michael Meissner ++ ++ Backport from the GCC 4.6 mainline: ++ 2010-12-08 Michael Meissner ++ ++ PR middle-end/42694 ++ * builtins.c (expand_builtin_pow_root): Don't optimize pow(x,y) ++ where y is 0.25, 1./6., or 0.75 if the target does not have a sqrt ++ instruction, but do optimize if y is 0.5 or 1./3. since that ++ changes an expensive call into a cheaper one. ++ ++2010-12-01 Michael Meissner ++ ++ Backport from the GCC 4.6 mainline: ++ 2010-12-01 Michael Meissner ++ ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): Fix ++ thinko regarding setting -mno- debug switches. ++ (rs6000_rtx_costs): Add FMA. Delete old rtl based FMA costs. ++ ++2010-11-30 Michael Meissner ++ ++ Backport from the GCC 4.6 mainline: ++ 2010-11-30 Richard Guenther ++ ++ PR tree-optimization/46722 ++ * tree-ssa-math-opts.c (convert_mult_to_fma): Get multiplication ++ operands as arguments. ++ (execute_optimize_widening_mul): Also handle power of two as ++ multiplication. ++ ++2010-11-24 Michael Meissner ++ ++ Backport from the GCC 4.6 mainline: ++ 2010-11-09 Michael Meissner ++ ++ * config/rs6000/rs6000.md (floatsi2_lfiwax): Rewrite so ++ split occurs before reload, and we allocate memory at the time of ++ the split, not during expansion. Add attributes. ++ (floatsi2_lfiwax_mem): Ditto. ++ (floatunssi2_lfiwzx): Ditto. ++ (floatunssi2_lfiwzx_mem): Ditto. ++ (floatsidf2): Ditto. ++ (floatunssisf2): Ditto. ++ (floatunssidf2): Ditto. ++ (fix_truncsi2): Ditto. ++ (fix_truncsi2_stfiwx): Ditto. ++ (fix_truncsi2_internal): Ditto. ++ (fix_truncsi2): Ditto. ++ (fix_truncdi2): Ditto. ++ (fixuns_truncsi2_stfiwx): Ditto. ++ (floatsisf2): Ditto. ++ (floatdidf2_mem): Ditto. ++ (floatunsdidf2_mem): Ditto. ++ (floatunsdidf2): Ditto. ++ (floatdisf2_internal1): Ditto. ++ (floatdisf2_mem): Ditto. ++ (floatunsdisf2_mem): Ditto. ++ (floatsi2_lfiwax_mem2): Delete. ++ (floatunssi2_lfiwzx_mem2): Ditto. ++ (fix_truncsi2_mem): Ditto. ++ (fixuns_truncsi2_mem): Ditto. ++ (round322_fprs): New combiner insn to combine (double)(int) ++ type operations to reduce copying the values to multiple memory ++ slots. ++ (roundu322_fprs): Ditto. ++ ++ * config/rs6000/rs6000.c (rs6000_address_for_fpconvert): Handle ++ PRE_INC, PRE_DEC, PRE_MODIFY. ++ (rs6000_expand_convert_si_to_sfdf): Delete, no longer used. ++ ++ * config/rs6000/rs6000-protos.h (rs6000_expand_convert_si_to_sfdf): ++ Delete prototype. ++ ++ Backport from the GCC 4.6 mainline ++ 2010-11-16 Richard Henderson ++ ++ * config.gcc [powerpc*, rs6000*] (extra_options): Add fused-madd.opt. ++ * config/rs6000/rs6000.opt (mfused-madd): Remove. ++ * config/rs6000/altivec.md (altivec_vmaddfp): Remove. ++ (*altivec_vmaddfp_1): Remove. ++ (*altivec_fmav4sf4): Rename from altivec_vmaddfp_2; use FMA. ++ (altivec_mulv4sf3): Expand to FMA directly. ++ (*altivec_vnmsubfp): Rename from altivec_vnmsubfp. ++ (*altivec_vnmsubfp_1, *altivec_vnmsubfp_2): Remove. ++ * config/rs6000/paired.md (paired_madds0): Use FMA. ++ (paired_madds1): Likewise. ++ (*paired_madd): Rename from paired_madd; use FMA. ++ (*paired_msub, *paired_nmadd, *paired_nmsub): Similarly. ++ * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Do not ++ consider TARGET_FUSED_MADD wrt rs6000_recip_control. ++ (bdesc_3arg): Update CODE_FOR_* for pattern renames. ++ (rs6000_emit_madd): Use fma_optab. ++ (rs6000_emit_msub): Use fms_optab. ++ (rs6000_emit_nmsub): Expand the FMA pattern directly. ++ * config/rs6000/rs6000.md (FMA_F): New mode iterator. ++ (*fmasf4_fpr): Rename from fmasf4_fpr. ++ (*nfmasf4_fpr): Rename from *fnmasf4_fpr. ++ (*nfmssf4_fpr): Rename from *fnmssf4_fpr. ++ (*fmaddsf4_powerpc, *fmaddsf4_power, *fmsubsf4_powerpc): Remove. ++ (*fmsubsf4_power, *fnmaddsf4_powerpc_1, *fnmaddsf4_powerpc_2): Remove. ++ (*fnmaddsf4_power_1, *fnmaddsf4_power_2, *fnmsubsf4_powerpc_1): Remove. ++ (*fnmsubsf4_powerpc_2, *fnmsubsf4_power_1, *fnmsubsf4_power_2): Remove. ++ (*fmadf4_fpr): Rename from fmadf4_fpr. ++ (*nfmadf4_fpr): Rename from *fnmadf4_fpr. ++ (*nfmsdf4_fpr): Rename from *fnmsdf4_fpr. ++ (*fmadddf4_fpr, *fmsubdf4_fpr, *fnmadddf4_fpr_1): Remove. ++ (*fnmadddf4_fpr_2, *fnmsubdf4_fpr_1, *fnmsubdf4_fpr_2): Remove. ++ (fmasf4, fmadf4): Macroize into... ++ (fma4): ... here. ++ (fms4, fnma4, fnms4): New. ++ (nfma4, nfms4): New. ++ * config/rs6000/vector.md (mul3): Do not depend on ++ TARGET_FUSED_MADD. ++ * config/rs6000/vsx.md (vsx_fmadd4): Remove. ++ (*vsx_fmadd4_1): Remove. ++ (vsx_fmsub4, *vsx_fmsub4_1): Remove. ++ (vsx_fnmadd4_1, vsx_fnmadd4_2): Remove. ++ (vsx_fnmsub4_1, vsx_fnmsub4_2): Remove. ++ (*vsx_fma4): Rename from vsx_fmadd4_2. ++ (*vsx_fms4): Rename from vsx_fmsub4_2. ++ (*vsx_nfma4): Rename from vsx_fnmadd4. ++ (*vsx_nfms4): Rename from vsx_fnmsub4. ++ ++ Backport from the GCC 4.6 mainline ++ 2010-11-15 Richard Henderson ++ ++ * fold-const.c (operand_equal_for_comparison_p): Handle FMA_EXPR, ++ WIDEN_MULT_PLUS_EXPR, WIDEN_MULT_MINUS_EXPR, VEC_COND_EXPR, ++ DOT_PROD_EXPR. ++ ++ Backport from the GCC 4.6 mainline ++ 2010-11-11 Richard Henderson ++ ++ * config/fused-madd.opt: New file. ++ ++ Backport from the GCC 4.6 mainline ++ 2010-11-15 Richard Henderson ++ ++ * loop-unroll.c (analyze_insn_to_expand_var): Accept accumulation ++ via FMA if unsafe math. ++ (insert_var_expansion_initialization): Handle FMA. ++ (combine_var_copies_in_loop_exit): Likewise. ++ ++ Backport from the GCC 4.6 mainline ++ 2010-11-15 Richard Guenther ++ ++ PR bootstrap/46474 ++ * tree-ssa-math-opts.c (convert_mult_to_fma): Disregard debug stmts. ++ ++ Backport from the GCC 4.6 mainline ++ 2010-11-11 Richard Henderson ++ ++ * optabs.c (init_optabs): Init {fma,fms,fnma,fnms}_optab properly. ++ ++ Backport from the GCC 4.6 mainline ++ 2010-11-11 Richard Henderson ++ ++ * tree-ssa-math-opts.c (convert_mult_to_fma): Do not verify ++ that the target has the exact fma operation that we matched. ++ ++ Backport from the GCC 4.6 mainline ++ 2010-11-11 Richard Henderson ++ ++ * tree-ssa-math-opts.c (convert_mult_to_fma): Handle a NEGATE_EXPR ++ in between the MULT and the PLUS/MINUS. ++ ++ Backport from the GCC 4.6 mainline: ++ 2010-11-05 Jakub Jelinek ++ ++ PR debug/46307 ++ * tree-ssa-operands.c (get_expr_operands): Handle FMA_EXPR. ++ * tree-pretty-print.c (dump_generic_node): Likewise. ++ (op_code_prio): Likewise. ++ * cfgexpand.c (expand_debug_expr): Likewise. ++ ++ ++ Backport from the GCC 4.6 mainline: ++ 2010-11-04 Richard Guenther ++ Richard Henderson ++ ++ * tree.def (FMA_EXPR): New tree code. ++ * expr.c (expand_expr_real_2): Add FMA_EXPR expansion code. ++ * gimple.c (gimple_rhs_class_table): FMA_EXPR is a GIMPLE_TERNARY_RHS. ++ * tree-cfg.c (verify_gimple_assign_ternary): Verify FMA_EXPR types. ++ * tree-inline.c (estimate_operator_cost): Handle FMA_EXPR. ++ * gimple-pretty-print.c (dump_ternary_rhs): Likewise. ++ * tree-ssa-math-opts.c (convert_mult_to_fma): New function. ++ (execute_optimize_widening_mul): Call it. Reorganize to allow ++ dead stmt removal. Move TODO flags ... ++ (pass_optimize_widening_mul): ... here. ++ * flag-types.h (enum fp_contract_mode): New enum. ++ * common.opt (flag_fp_contract_mode): New variable. ++ (-ffp-contract): New option. ++ * opts.c (common_handle_option): Handle it. ++ * doc/invoke.texi (-ffp-contract): Document. ++ * tree.h (fold_fma): Declare. ++ * builtins.c (fold_fma): New function. ++ (fold_builtin_fma): Likewise. ++ (fold_builtin_3): Call it for fma. ++ * fold-const.c (fold_ternary_loc): Fold FMA_EXPR. ++ * optabs.c (optab_for_tree_code): Handle FMA_EXPR. ++ * config/i386/sse.md (fms4, fnma, fnms4): ++ New expanders. ++ * doc/md.texi (fms4, fnma, fnms4): Document new ++ named patterns. ++ * genopinit.c (optabs): Initialize fms_optab, fnma_optab and fnms_optab. ++ * optabs.h (enum optab_index): Add OTI_fms, OTI_fnma and OTI_fnms. ++ (fms_optab, fnma_optab, fnms_optab): New defines. ++ * gimplify.c (gimplify_expr): Handle binary truth expressions ++ explicitly. Handle FMA_EXPR. ++ * tree-vect-stmts.c (vectorizable_operation): Handle ternary ++ operations. ++ ++ Backport from the GCC 4.6 mainline: ++ 2010-10-18 Richard Henderson ++ ++ * simplify-rtx.c (simplify_ternary_operation) [FMA]: Simplify ++ (fma (neg a) (neg b) c) and (fma a (neg b) c). ++ ++ Backport from the GCC 4.6 mainline: ++ 2010-10-11 Eric Botcazou ++ ++ * simplify-rtx.c (simplify_unary_operation_1): Use unsigned arithmetics ++ in masking operations. ++ (simplify_const_unary_operation): Likewise. ++ (simplify_binary_operation_1): Likewise. ++ (simplify_const_binary_operation): Likewise. ++ (simplify_const_relational_operation): Likewise. ++ (simplify_ternary_operation): Likewise. ++ (simplify_immed_subreg): Likewise. ++ ++ Backport from the GCC 4.6 mainline: ++ 2010-06-25 Bernd Schmidt ++ ++ With large parts from Jim Wilson: ++ PR target/43902 ++ * tree-pretty-print.c (dump_generic_node, op_code_prio): Add ++ WIDEN_MULT_PLUS_EXPR and WIDEN_MULT_MINUS_EXPR. ++ * optabs.c (optab_for_tree_code): Likewise. ++ (expand_widen_pattern_expr): Likewise. ++ * tree-ssa-math-opts.c (convert_mult_to_widen): New function, broken ++ out of execute_optimize_widening_mul. ++ (convert_plusminus_to_widen): New function. ++ (execute_optimize_widening_mul): Use the two new functions. ++ * expr.c (expand_expr_real_2): Add support for GIMPLE_TERNARY_RHS. ++ Remove code to generate widening multiply-accumulate. Add support ++ for WIDEN_MULT_PLUS_EXPR and WIDEN_MULT_MINUS_EXPR. ++ * gimple-pretty-print.c (dump_ternary_rhs): New function. ++ (dump_gimple_assign): Call it when appropriate. ++ * tree.def (WIDEN_MULT_PLUS_EXPR, WIDEN_MULT_MINUS_EXPR): New codes. ++ * cfgexpand.c (gimple_assign_rhs_to_tree): Likewise. ++ (expand_gimple_stmt_1): Likewise. ++ (expand_debug_expr): Support WIDEN_MULT_PLUS_EXPR and ++ WIDEN_MULT_MINUS_EXPR. ++ * tree-ssa-operands.c (get_expr_operands): Likewise. ++ * tree-inline.c (estimate_operator_cost): Likewise. ++ * gimple.c (extract_ops_from_tree_1): Renamed from ++ extract_ops_from_tree. Add new arg for a third operand; fill it. ++ (gimple_build_assign_stat): Support operations with three operands. ++ (gimple_build_assign_with_ops_stat): Likewise. ++ (gimple_assign_set_rhs_from_tree): Likewise. ++ (gimple_assign_set_rhs_with_ops_1): Renamed from ++ gimple_assign_set_rhs_with_ops. Add new arg for a third operand. ++ (get_gimple_rhs_num_ops): Support GIMPLE_TERNARY_RHS. ++ (get_gimple_rhs_num_ops): Handle WIDEN_MULT_PLUS_EXPR and ++ WIDEN_MULT_MINUS_EXPR. ++ * gimple.h (enum gimple_rhs_class): Add GIMPLE_TERNARY_RHS. ++ (extract_ops_from_tree_1): Adjust declaration. ++ (gimple_assign_set_rhs_with_ops_1): Likewise. ++ (gimple_build_assign_with_ops): Pass NULL for last operand. ++ (gimple_build_assign_with_ops3): New macro. ++ (gimple_assign_rhs3, gimple_assign_rhs3_ptr, gimple_assign_set_rhs3, ++ gimple_assign_set_rhs_with_ops, extract_ops_from_tree): New inline ++ functions. ++ * tree-cfg.c (verify_gimple_assign_ternary): New static function. ++ (verify_gimple_assign): Call it. ++ * doc/gimple.texi (Manipulating operands): Document GIMPLE_TERNARY_RHS. ++ (Tuple specific accessors, subsection GIMPLE_ASSIGN): Document new ++ functions for dealing with three-operand statements. ++ * tree.c (commutative_ternary_tree_code): New function. ++ * tree.h (commutative_ternary_tree_code): Declare it. ++ * tree-vrp.c (gimple_assign_nonnegative_warnv_p): Return false for ++ ternary statements. ++ (gimple_assign_nonzero_warnv_p): Likewise. ++ * tree-ssa-sccvn.c (stmt_has_constants): Handle GIMPLE_TERNARY_RHS. ++ * tree-ssa-ccp.c (get_rhs_assign_op_for_ccp): New static function. ++ (ccp_fold): Use it. Handle GIMPLE_TERNARY_RHS. ++ * tree-ssa-dom.c (enum expr_kind): Add EXPR_TERNARY. ++ (struct hashtable_expr): New member ternary in the union. ++ (initialize_hash_element): Handle GIMPLE_TERNARY_RHS. ++ (hashable_expr_equal_p): Fix indentation. Handle EXPR_TERNARY. ++ (iterative_hash_hashable_expr): Likewise. ++ (print_expr_hash_elt): Handle EXPR_TERNARY. ++ * gimple-fold.c (fold_gimple_assign): Handle GIMPLE_TERNARY_RHS. ++ * tree-ssa-threadedge.c (fold_assignment_stmt): Remove useless break ++ statements. Handle GIMPLE_TERNARY_RHS. ++ ++ Backport from GCC 4.6 mainline ++ 2010-04-22 Bernd Schmidt ++ ++ PR middle-end/29274 ++ * tree-pass.h (pass_optimize_widening_mul): Declare. ++ * tree-ssa-math-opts.c (execute_optimize_widening_mul, ++ gate_optimize_widening_mul): New static functions. ++ (pass_optimize_widening_mul): New. ++ * expr.c (expand_expr_real_2) : New case. ++ : Remove support for widening multiplies. ++ * tree.def (WIDEN_MULT_EXPR): Tweak comment. ++ * cfgexpand.c (expand_debug_expr) : Use ++ simplify_gen_unary rather than directly building extensions. ++ * tree-cfg.c (verify_gimple_assign_binary): Add tests for ++ WIDEN_MULT_EXPR. ++ * expmed.c (expand_widening_mult): New function. ++ * passes.c (init_optimization_passes): Add pass_optimize_widening_mul. ++ ++2010-11-23 Michael Meissner ++ ++ Merge up to gcc-4_5-branch revision 167090. ++ * REVISION: Update subversion id. ++ ++2010-11-17 Peter Bergner ++ ++ Merge up to gcc-4_5-branch revision 166873. ++ * REVISION: Update subversion id. ++ ++2010-11-16 Michael Meissner ++ ++ * builtins.c (expand_builtin_mathfn_ternary): Fix backport issue ++ with GCC 4.5 with optab_handler being different in 4.6 than 4.5. ++ ++2010-11-15 Michael Meissner ++ ++ Backport from mainline ++ 2010-11-08 Michael Meissner ++ ++ PR target/46378 ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't ++ turn on ISA 2.04 rounding instructions for power5. ++ ++ * config/rs6000/rs6000.md (friz): Friz is an ISA 2.04 instruciton, ++ not ISA 2.02. ++ ++ PR target/45585 ++ * config/rs6000/darwin.md (movdi_low): Allow DImode values to be ++ in FPR registers. ++ (movdi_low_st): Ditto. ++ ++2010-11-15 Peter Bergner ++ ++ Merge up to gcc-4_5-branch revision 166755. ++ * REVISION: Update subversion id. ++ ++2010-11-08 Pat Haugen ++ ++ Backport from mainline ++ 2010-11-04 Pat Haugen ++ ++ * final.c (compute_alignments): Compute/free loop info all the time. ++ * config/rs6000/rs6000.h (LOOP_ALIGN): Define. ++ * config/rs6000/rs6000-protos.h (rs6000_loop_align): Declare. ++ * config/rs6000/t-rs6000 (rs6000.o): Add cfgloop.h. ++ * config/rs6000/rs6000.c (cfgloop.h): Include. ++ (can_override_loop_align): New. ++ (rs6000_option_override_internal): Set it. ++ (TARGET_ASM_LOOP_ALIGN_MAX_SKIP): Define target hook. ++ (rs6000_loop_align): New function. ++ (rs6000_loop_align_max_skip): Likewise. ++ ++ 2010-10-19 DJ Delorie ++ ++ * doc/tm.texi.in (TARGET_ASM_JUMP_ALIGN_MAX_SKIP): New. ++ (TARGET_ASM_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP): Change to hook. ++ (TARGET_ASM_LOOP_ALIGN_MAX_SKIP): Likewise. ++ (TARGET_ASM_LABEL_ALIGN_MAX_SKIP): Likewise. ++ * doc/tm.texi: Regenerate. ++ * targhooks.h (default_label_align_after_barrier_max_skip, ++ default_loop_align_max_skip, default_label_align_max_skip, ++ default_jump_align_max_skip): Declare. ++ * target.def (label_align_after_barrier_max_skip): New. ++ (loop_align_max_skip): New. ++ (label_align_max_skip): New. ++ (jump_align_max_skip): New. ++ * system.h (poison): Add those macros to the list. ++ * final.c (LABEL_ALIGN_MAX_SKIP): Remove. ++ (LOOP_ALIGN_MAX_SKIP): Remove. ++ (LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP): Remove. ++ (JUMP_ALIGN_MAX_SKIP): Remove. ++ (default_label_align_after_barrier_max_skip): New. ++ (default_loop_align_max_skip): New. ++ (default_label_align_max_skip): New. ++ (default_jump_align_max_skip): New. ++ (compute_alignments): Use the new hooks. ++ (shorten_branches): Likewise. ++ ++2010-11-03 Michael Meissner ++ ++ Backport from mainline ++ 2010-11-03 Michael Meissner ++ ++ * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support to use ++ xsmindp/xsmaxdp on VSX for single precision min/max. ++ * config/rs6000/vsx.md (vsx_smaxsf3): Ditto. ++ (vsx_sminsf3): Ditto. ++ ++2010-10-18 Michael Meissner ++ ++ Backport from mainline ++ 2010-10-18 Michael Meissner ++ ++ PR target/46041 ++ * tree.h (mode_has_fma): Delete, move to c-cppbuiltins.c. ++ * builtins.c (mode_has_fma): Ditto. ++ ++ * c-cppbuiltin.c (mode_has_fma): Move function here from ++ builtins.c. Don't use the fma optab, instead just use the ++ HAVE_fma* macros, so that __FP_FAST_FMA* will be defined when ++ using -save-temps. ++ ++2010-10-14 Michael Meissner ++ ++ Backport from mainline ++ 2010-10-14 Michael Meissner ++ ++ * doc/md.texi (Standard Names): Add fma@var{m}4 documentation. ++ ++ * doc/rtl.texi (RTX_TERNARY): Document FMA is ternary. Add ++ SIGN_EXTRACT and ZERO_EXTRACT which were missing. ++ (Standard names): Document fma. ++ ++ * doc/cpp.texi (Common Predefined Macros): Document __FP_FAST_FMA, ++ __FP_FAST_FMAF, __FP_FAST_FMAL. ++ ++ * builitns.c (expand_builtin_mathfn_ternary): New function for ++ expanding ternary math functions, like fma. ++ (expand_builtin): Call it for the fma builtins. ++ ++ * simplify-rtx.c (simplify_ternary_operation): Don't simplify FMA ++ ops at present. ++ ++ * tree-vect-stmts.c (vectorizable_call): Allow 3 argument ++ vectorizable functions to support vectorizing fma. ++ ++ * config/rs6000/rs6000.c (rs6000_builtin_vectorized_function): ++ Handle fma builtins. ++ ++ * config/rs6000/vsx.md (UNSPEC_VSX_MADD): Delete. ++ (UNSPEC_VSX_MSUB): Ditto. ++ (UNSPEC_VSX_NMADD): Ditto. ++ (UNSPEC_VSX_NMSUB): Ditto. ++ (vsx_fmadd4*): Rewrite to use FMA rtl in some cases instead ++ of UNSPEC. Renumber combiner patterns. ++ (vsx_fmsub4*): Ditto. ++ (vsx_fnmadd4*): Ditto. ++ (vsx_fnmsub4*): Ditto. ++ ++ * config/rs6000/altivec.md (UNSPEC_VNMSUBFP): Delete. ++ (altivec_vmaddfp): Rewrite to use FMA rtl if no fused ++ multiply/add. Rename combiner pattern, and add TARGET_FUSED_MADD ++ test. ++ (altivec_vmaddfp_1): Ditto. ++ (altivec_vmaddfp_2): Ditto. ++ (atlivec_mulv4sf3): Ditto. ++ (altivec_vnmsubfp): Ditto. ++ (altivec_vnmsubfp_1): Ditto. ++ (altivec_vnmsubfp_2): Ditto. ++ (altivec_vnmsubfp_3): Delete. ++ ++ * config/rs6000/rs6000.md (fmasf4): New insns for fma builtin ++ support. ++ (fmasf4_fpr): Ditto. ++ (fmssf4_fpr): Ditto. ++ (fnmasf4_fpr): Ditto. ++ (fnmssf4_fpr): Ditto. ++ (fmadf4): Ditto. ++ (fmadf4_fpr): Ditto. ++ (fmsdf4_fpr): Ditto. ++ (fnmadf4_fpr): Ditto. ++ (fnmsdf4_fpr): Ditto. ++ ++ * optabs.h (OTI_fma): Add fma optab. ++ (fma_optab): Ditto. ++ ++ * genopinit.c (optabs): Set fma optab. ++ ++ * rtl.def (FMA): Add FMA rtl. ++ ++ * tree.h (mode_has_fma): New function to return if MODE supports a ++ fast multiply and add instruction. ++ * builtins.c (mode_has_fma): Ditto. ++ ++ * c-cppbuiltin.c (builtin_define_float_constants): Emit ++ __FP_FAST_FMA, __FP_FAST_FMAF, and __FP_FAST_FMAL if the machine ++ has the appropriate fma builtins. ++ (c_cpp_builtins): Adjust call to builtin_define_float_constants. ++ ++2010-10-07 Peter Bergner ++ ++ * config/rs6000/t-linux64 (MULTILIB_OPTIONS): Remove soft-float support. ++ (MULTILIB_DIRNAMES): Likewise. ++ (MULTILIB_EXCEPTIONS): Likewise. ++ (MULTILIB_EXCLUSIONS): Likewise. ++ (MULTILIB_OSDIRNAMES): Likewise. ++ (MULTILIB_MATCHES): Likewise. ++ ++2010-09-27 Michael Meissner ++ ++ Merge up to 164656. ++ * REVISION: Update subversion id. ++ ++2010-09-23 Alan Modra ++ ++ * config/rs6000/rs6000.c (toc_relative_ok): Delete. ++ (rs6000_emit_move): Use SYMBOL_REF_LOCAL_P instead. ++ ++2010-09-08 Peter Bergner ++ ++ * config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Set ++ CMODEL_MEDIUM as default. ++ ++2010-09-06 Alan Modra ++ ++ * config/rs6000/rs6000.c (toc_relative_ok): New function. ++ (offsettable_ok_by_alignment): Don't segfault on NULL DECL_SIZE_UNIT. ++ (rs6000_emit_move): Use toc_relative_ok. ++ ++ Backport from mainline ++ 2010-06-18 Alan Modra ++ * config/rs6000/linux64.h (SET_CMODEL): Don't expand to empty. ++ ++ 2010-06-15 Alan Modra ++ * doc/invoke.texi: Add mcmodel to powerpc options. ++ * configure.ac: Add HAVE_LD_LARGE_TOC test. ++ * configure: Regenerate. ++ * config.in: Regenerate. ++ * config/rs6000/linux64.opt (mcmodel): New. ++ * config/rs6000/linux64.h (TARGET_USES_LINUX64_OPT): Define. ++ (TARGET_CMODEL, SET_CMODEL): Define. ++ (SUBSUBTARGET_OVERRIDE_OPTIONS): Check user -mcmodel choice, ++ select CMODEL_MEDIUM default. ++ * config/rs6000/rs6000.h (enum rs6000_cmodel): New. ++ (TARGET_CMODEL): Define default. ++ * config/rs6000/rs6000.c (cmodel): New variable. ++ (rs6000_explicit_options): Add cmodel field. ++ (rs6000_handle_option): Handle -mcmodel. ++ (create_TOC_reference): Add largetoc_reg param. Generate high, ++ lo_sum rtl for CMODEL_MEDIUM and CMODEL_LARGE. Update all callers. ++ (rs6000_delegitimize_address): Recognise new toc reference rtl ++ and minimal-toc rtl. ++ (rs6000_legitimize_reload_address): Handle new toc references. ++ (print_operand_address): Handle legitimate_constant_pool_address_p ++ match before lo_sum. ++ (rs6000_eliminate_indexed_memrefs): Tidy. ++ (rs6000_emit_move): Tweak threshold for inlining constants. ++ Keep rs6000_emit_allocate_stack large stack frame offsets ++ loaded into r0 inline. ++ (rs6000_generate_compare ): One more clobber. ++ (tocrel_base, tocrel_offset): New variables. ++ (toc_relative_expr_p): Set them here. ++ (print_operand_address): Skip over any offset on constant pool ++ address. ++ (rs6000_output_addr_const_extra): Print tocrel_offset before @toc. ++ (rs6000_mode_dependent_address ): False for new toc refs. ++ (offsettable_ok_by_alignment): New function. ++ (rs6000_emit_move): Address suitably aligned local symbol_refs ++ relative to the toc pointer for -mcmodel=medium. ++ (legitimate_constant_pool_address_p): Make param const_rtx. Add ++ strict param. Allow lo_sum version of addressing. Verify reg ++ used for -mminimal-toc and -mcmodel != small. Update all callers. ++ * config/rs6000/constraints.md: Update for above change. ++ * config/rs6000/predicates.md: Likewise. ++ * config/rs6000/rs6000.md (tls_gd_aix): Generate -mcmodel=medium/large ++ code. ++ (tls_gd): Split for -mcmodel=medium/large. ++ (tls_gd_high, tls_gd_low): New. ++ (tls_ld_aix, tls_ld, tls_ld_high, tls_ld_low): Similarly. ++ (tls_got_dtprel, tls_got_dtprel_high, tls_got_dtprel_low): Similarly. ++ (tls_got_tprel, tls_got_tprel_high, tls_got_tprel_low): Similarly. ++ (largetoc_high, largetoc_low): New. ++ (cmptf_internal2): Add clobber. ++ * config/rs6000/rs6000-protos.h: Update. ++ ++2010-09-02 Michael Meissner ++ ++ Backport from mainline ++ 2010-09-02 Michael Meissner ++ ++ * config/rs6000/rs6000.opt (-mfriz): New switch to control whether ++ to convert (double)(long) into a single FRIZ instruction or not ++ when -ffast-math is used. ++ ++ * config/rs6000/vsx.md (VSX_DF): New iterator for DF/V2DF modes. ++ (vsx_float_fix_2): Optimize (double)(long) into X{S,V}RDPIZ ++ or FRIZ instruction if -ffast-math. ++ * config/rs6000/rs6000.md (friz): Ditto. ++ ++ * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mfriz. ++ ++2010-08-31 Michael Meissner ++ ++ Backport from mainline: ++ 2010-08-23 Michael Meissner ++ ++ * config/rs6000/rs6000-protos.h (rs6000_address_for_fpconvert): ++ New declaration. ++ (rs6000_allocate_stack_temp): Ditto. ++ (rs6000_expand_convert_si_to_sfdf): Ditto. ++ ++ * config/rs6000/rs6000.c (rs6000_override_options): Adjust long ++ line. Update the options set if power6 or power7 server/embedded ++ type options are used. If we give a warning for no vsx under ++ -mcpu=power7 -mno-altivec, mark -mvsx as an explicit option. ++ (rs6000_allocate_stack_temp): New function to allocate a stack ++ tempoary and adjust the address so it meets either REG+OFFSET or ++ REG+REG addressing requirements. ++ (rs6000_address_for_fpconvert): Adjust REG+OFFSET addresses so ++ that they can be used with the LFIWAX/LFIWZX instrucitons. ++ (rs6000_expand_convert_si_to_sfdf): New helper funciton for ++ converting signed/unsigned SImode to either SFmode/DFmode. ++ ++ * config/rs6000/rs6000.h (TARGET_FCFID): New macros to determine ++ whether certain instructions can be generated. ++ (TARGET_FCTIDZ): Ditto. ++ (TARGET_STFIWX): Ditto. ++ (TARGET_LFIWAX): Ditto. ++ (TARGET_LFIWZX): Ditto. ++ (TARGET_FCFIDS): Ditto. ++ (TARGET_FCFIDU): Ditto. ++ (TARGET_FCFIDUS): Ditto. ++ (TARGET_FCTIDUZ): Ditto. ++ (TARGET_FCTIWUZ): Ditto. ++ ++ * config/rs6000/rs6000.md (UNSPEC_FCTIW): New unspec constants. ++ (UNSPEC_FCTID): Ditto. ++ (UNSPEC_LFIWAX): Ditto. ++ (UNSPEC_LFIWZX): Ditto. ++ (UNSPEC_FCTIWUZ): Ditto. ++ (rreg): Use correct constraints. ++ (SI_CONVERT_FP): New mode attribute for floating point conversion ++ tests. ++ (E500_CONVERT): Ditto. ++ (lfiwax): New insns for converting from integer to floating point ++ utilizing newer instructions. Attempt to optimize conversions ++ that come from memory so that we don't load the value into a GPR, ++ spill it to the stack and reload it into a FPR. ++ (floatsi2_lfiwax): Ditto. ++ (floatsi2_lfiwax_mem): Ditto. ++ (floatsi2_lfiwax_mem2): Ditto. ++ (lfiwzx): Ditto. ++ (floatunssi2_lfiwzx): Ditto. ++ (floatunssi2_lfiwzx_mem): Ditto. ++ (floatunssi2_lfiwzx_mem2): Ditto. ++ (floatdidf2_mem): Ditto. ++ (floatunsdidf2_fcfidu): Ditto. ++ (floatunsdidf2_mem): Ditto. ++ (floatunsdisf2): Ditto. ++ (floatunsdisf2_fcfidus): Ditto. ++ (floatunsdisf2_mem): Ditto. ++ (floatsidf2): Add support for LFIWAX/LFIWZX/FCFIDS/FCFIDU/FCFIDUS. ++ Use FCFID on 32-bit hosts that support it. ++ (floatsidf2_internal): Ditto. ++ (floatunssisf2): Ditto. ++ (floatunssidf2): Ditto. ++ (floatunssidf2_internal): Ditto. ++ (floatsisf2): Ditto. ++ (floatdidf2): Ditto. ++ (floatdidf2_fpr): Ditto. ++ (floatunsdidf2): Ditto. ++ (floatdisf2): Ditto. ++ (floatdisf2_fcfids): Ditto. ++ (floatdisf2_internal1): Ditto. ++ (fixuns_truncsfsi2): Delete, merge into common pattern for both ++ SF/DF. Add power7 support. ++ (fix_truncsfsi2): Ditto. ++ (fixuns_truncdfsi2): Ditto. ++ (fixuns_truncdfdi2): Ditto. ++ (fix_truncdfsi2): Ditto. ++ (fix_truncdfsi2_internal): Ditto. ++ (fix_truncdfsi2_internal_gfxopt): Ditto. ++ (fix_truncdfsi2_mfpgpr): Ditto. ++ (fctiwz): Ditto. ++ (btruncdf2): Ditto. ++ (btruncdf2_fpr): Ditto. ++ (btructsf2): Ditto. ++ (ceildf2): Ditto. ++ (ceildf2_fpr): Ditto. ++ (ceilsf2): Ditto. ++ (floordf2): Ditto. ++ (floordf2_fpr): Ditto. ++ (floorsf2): Ditto. ++ (rounddf2): Ditto. ++ (rounddf2_fpr): Ditto. ++ (roundsf2): Ditto. ++ (fix_truncsi2): Combine SF/DF conversion into one insn. ++ (fix_truncdi2): Ditto. ++ (fixuns_truncsi2): Ditto. ++ (fixuns_truncdi2): Ditto. ++ (fctiwz_): Ditto. ++ (btrunc2): Ditto. ++ (btrunc2_fpr): Ditto. ++ (ceil2): Ditto. ++ (ceil2_fpr): Ditto. ++ (floor2): Ditto. ++ (float2_fpr): Ditto. ++ (round2): Ditto. ++ (round2_fpr): Ditto. ++ (fix_truncsi2_stfiwx): New insn for machines with STFIWX. ++ (fixuns_truncsi2_stfiwx): Ditto. ++ (fix_truncdfsi2_internal): Ditto. ++ (fix_truncsi2_mem): Combiner pattern to eliminate storing ++ converted value on stack, loaded into GPR, and then stored into ++ the final destination. ++ (fix_truncdi2_fctidz): New pattern for targets supporting ++ FCTIDZ. ++ (lrintdi2): New insn, provide the lrint builtin functions. ++ (ftruncdf2): Delete, unused. ++ (fix_trunctfsi2_internal): Use gen_fctiwz_df, not gen_fctiwz. ++ ++ * config/rs6000/vsx.md (toplevel): Update copyright year. ++ (VSr2): Use "ws" contraint for DFmode, not "!r#r". ++ (VSr3): Ditto. ++ ++ Backport from mainline: ++ 2010-08-18 Michael Meissner ++ ++ * config/rs6000/rs6000.opt (-mveclibabi=mass): New option to ++ enable the compiler to autovectorize mathmetical functions for ++ power7 using the Mathematical Acceleration Subsystem library. ++ ++ * config/rs6000/rs6000.c (rs6000_veclib_handler): New variable to ++ handle which vector math library we have. ++ (rs6000_override_options): Add -mveclibabi=mass support. ++ (rs6000_builtin_vectorized_libmass): New function to handle auto ++ vectorizing math functions that are in the MASS library. ++ (rs6000_builtin_vectorized_function): Call it. ++ ++ * doc/invoke.texi (RS/6000 and PowerPC Options): Document ++ -mveclibabi=mass. ++ ++2010-08-26 Michael Meissner ++ ++ Merge up to 163570. ++ * REVISION: Update subvesion id. ++ ++2010-08-26 Michael Meissner ++ ++ Backport from the mainline: ++ 2010-07-28 Michael Meissner ++ ++ * config/rs6000/rs6000.c (rs6000_rtx_costs): Update costs for ++ popcount on power7 and parity on power6 systems. ++ (rs6000_emit_popcount): Rename gen_popcntwsi2 to gen_popcntddi2. ++ (rs6000_emit_parity): Add support for power6 prtyd/prtyw ++ instructions. ++ ++ * config/rs6000/rs6000.md (UNSPEC_COPYSIGN): New unspec. ++ (UNSPEC_PARITY): Ditto. ++ (SFDF): New iterator for SF/DF. ++ (rreg2): New mode attribute for floating register constraint. ++ (TARGET_FLOAT): New mode attribute for whether single/double float ++ is supported. ++ (popcntd2): Combine popcntwsi2 and popcntddi2 into one ++ pattern. ++ (parity2_cmpb): New insn for parity on power6 and newer ++ machines. ++ (copysign3): Combine copysignsf3, copysigndf3 into one ++ pattern. Add support for fcpsgn instruction added in power6. ++ (copysignsf3): Delete. ++ (copysigndf3): Delete. ++ (copysign3_fcpsgn): New insn to generate fcpsgn. Use UNSPEC ++ instead of if_then_else in RTL to avoid problems with -0. ++ ++ * config/rs6000/vsx.md (vsx_copysign3): Use UNSPEC instead ++ of if_then_else to mirror scalar code. ++ (vsx_copysignsf3): Delete, use copysign3_fcpsgn in ++ rs6000.md. ++ ++ * config/rs6000/vector.md (vector_copysign3): Use UNSPEC ++ instead of if_then_else. ++ ++2010-08-12 Michael Meissner ++ ++ Backport from the mainline: ++ 2010-07-20 Nathan Froyd ++ ++ * config/rs6000/rs6000.md (abs2_isel, nabs2_isel): ++ Reverse sense of if_then_else condition. ++ ++2010-08-12 Michael Meissner ++ ++ Backport from the mainline: ++ 2010-07-08 Michael Meissner ++ ++ PR target/44877 ++ * config/rs6000/rs6000.c (rs6000_expand_builtin): Use ++ POINTER_TYPE_P instead of checking only for POINTER_TYPE for the ++ builtin mask for load/store builtins. ++ ++2010-08-12 Michael Meissner ++ ++ Backport from the mainline: ++ 2010-06-02 Michael Meissner ++ ++ PR target/44218 ++ * doc/invoke.texi (RS/6000 and PowerPC Options): Delete obsolete ++ -mswdiv option. Add -mrecip, -mrecip=, -mrecip-precision options. ++ ++ * doc/extend.texi (powerpc builtins): Document vec_recip, ++ vec_rsqrt, vec_rsqrte altivec/vsx builtins. ++ ++ * config/rs6000/rs60000-protos.h (rs6000_emit_swdiv): New function. ++ (rs6000_emit_swrsqrt): Ditto. ++ (rs6000_emit_swdivsf): Delete. ++ (rs6000_emit_swdivdf): Ditto. ++ (rs6000_emit_swrsqrtsf): Ditto. ++ ++ * config/rs6000/rs6000.c (rs6000_recip_bits): New global to ++ describe the reciprocal estimate support for each type. ++ (recip_options): Map -mrecip= into option bits. ++ (gen_2arg_fn_t): New typedef for binary rtx gen function. ++ (rs6000_debug_reg_global): If -mdebug=reg, print the state of the ++ reciprocal estimate instructions. ++ (rs6000_init_hard_regno_mode_ok): Key ws constraint off of the ++ debug -mvsx-scalar-memory switch instead of -mvsx-scalar-double. ++ Set up rs6000_recip_bits based on the -mrecip* options. Print the ++ cost information if -mdebug=cost or -mdebug=reg. ++ (rs6000_override_options): Set -mrecip-precision for power6, and ++ power7 machines. If -mvsx or -mdfp, enable various options that ++ came in previous instruction set ISAs, unless the option was ++ explicitly disabled by the command line option. Parse ++ -mrecip= options. ++ (rs6000_builtin_vectorized_function): Add support for vectorizing ++ the reciprocal estimate builtins and expansions. ++ (rs6000_handle_option): Add -mrecip, -mrecip= support. ++ (bdesc_2arg): Add reciprocal estimate builtins. ++ (bdesc_1arg): Add reciprocal square root estimate builtins. ++ (rs6000_expand_builtin): Rewrite to use a switch statement, ++ instead of multiple if/then/elses. Add reciprocal estimate builtins. ++ (rs6000_init_builtins): Create declarations for reciprocal ++ estimate builtins. ++ (rs6000_preferred_reload_class): Simplify VSX preferences, if scalar ++ sized, prefer traditional floating point registers, if integer ++ vector types, prefer altivec registers. Don't actually look at ++ the memory address any more. ++ (rs6000_builtin_reciprocal): Add new builtin reciprocal estimate ++ builtins. ++ (rs6000_load_constant_and_splat): New helper function to load up ++ the constant for reciprocal estimate instructions. ++ (rs6000_emit_madd): New helper function for generating ++ multiply/add type instructions, based on the current switches. ++ (rs6000_emit_msub): Ditto. ++ (rs6000_emit_mnsub): Ditto. ++ (rs6000_emit_swdiv_high_precision): Replace rs6000_emit_swdivsf to ++ replace a divide with a reciprocal estimate and fixup, adding ++ support for machines with high precision and vectors. ++ (rs6000_emit_swdiv_low_precision): Rewrite rs6000_emit_swdivdf for ++ low precision machines. ++ (rs6000_emit_swdiv): New common function to be called to replace a ++ division with reciprocal estimate and fixup. ++ (rs6000_emit_swrsqrt): Replace rs6000_emit_swrsqrtsf. Add support ++ for double and vector types. Add support for high precision machines. ++ ++ * config/rs6000/rs6000.h (TARGET_FRES): New macro to say whether ++ the reciprocal estimate instructions can be generated. ++ (TARGET_FRE): Ditto. ++ (TARGET_FRSQRTES): Ditto. ++ (TARGET_FRSQRTE): Ditto. ++ (RS6000_RECIP_*): New macros for reciprocal estimate support. ++ ++ * config/rs6000/vector.md (rsqrte2): New insn for reciprocal ++ square root estimate on vectors. ++ (re2): New insn for reciprocal division estimate on vectors. ++ ++ * config/rs6000/rs6000-buitlins.def (ALTIVEC_BUILTIN_VRSQRTFP): ++ New builtin. ++ (ALTIVEC_BUILTIN_VRECIPFP): Ditto. ++ (ALTIVEC_BUITLIN_VEC_RE): Ditto. ++ (ALTIVEC_BUILTIN_VEC_RSQRT): Ditto. ++ (VSX_BUILTIN_RSQRT_V4SF): Ditto. ++ (VSX_BUITLIN_RSQRT_V2DF): Ditto. ++ (RS6000_BUILTIN_RSQRT): Ditto. ++ (ALTIVEC_BUILTIN_VEC_RSQRTE): Denote that the builtin is a ++ floating point builtin. ++ ++ * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define ++ macros __RECIP__, __RECIPF__, __RSQRTE__, __RSQRTEF__, ++ __RECIP_PRECISION__ based on the command line switches. ++ (altivec_overloaded_builtins): Add reciprocal estimate builtins. ++ ++ * config/rs6000/rs6000.opt (-mrecip): Document add support for ++ replacing division instructions with reciprocal estimate and fixup. ++ (-mrecip=): New option. ++ (-mrecip-precision): Ditto. ++ ++ * config/rs6000/vsx.md (UNSPEC_VSX_RSQRTE): Delete. ++ (vsx_rsqrte2): Use UNSPEC_RSQRT not UNSPEC_VSX_RSQRTE. ++ (vsx_copysignsf3): If -mvsx, use double precision cpsign on single ++ precision scalar. ++ ++ * config/rs6000/altivec.md (UNSPEC_RSQRTEFP): Delete. ++ (UNSPEC_VREFP): Ditto. ++ (altivec_vnmsubfp*): Make altivec nmsub mirror the scalar and VSX ++ conterparts with regard to support of -mno-fused-madd and -ffast-math. ++ (altivec_vrsqrtefp): Use common UNSPEC to allow scalar/vector ++ reciprocal estimate instructions to be generated. ++ (altivec_vrefp): Ditto. ++ ++ * config/rs6000/rs6000.md (RECIPF): New iterator for reciprocal ++ estimate support. ++ (rreg): New mode attribute for reciprocal estimate support. ++ (recip3): New insn for division using reciprocal estimate ++ and fixup builtins. ++ (divide define_split): New define_split to convert floating point ++ division to use reciprocal estimate if the user used the ++ appropriate options and the split is run when we can add new ++ pseudo registers for the fixup. ++ (rsqrt2): New insn for reciprocal square root support. ++ (recipsf3): Move into recip3. ++ (recipdf3): Ditto. ++ (fres): Use TARGET_FRES. ++ (rsqrtsf2): Move into rsqrt2. ++ (rsqrtsf_internal1): Use TARGET_FRSQRTSES. ++ (copysignsf3): Add support for VSX. ++ (fred): Use TARGET_FRE. ++ (fred_fpr): Ditto. ++ (rsqrtdf_internal1): New function for frsqrte instruciton. ++ ++ * config/rs6000/altivec.h (vec_recipdiv): Define new vector builtin. ++ (vec_rsqrt): Ditto. ++ ++2010-08-12 Michael Meissner ++ ++ Clone from gcc-4_5-branch, subversion id 163203. ++ * REVISION: New file, mark marge point revision. +Index: gcc/loop-unroll.c +=================================================================== +--- a/src/gcc/loop-unroll.c (.../gcc-4_5-branch) ++++ b/src/gcc/loop-unroll.c (.../ibm/gcc-4_5-branch) +@@ -1609,10 +1609,10 @@ + static struct var_to_expand * + analyze_insn_to_expand_var (struct loop *loop, rtx insn) + { +- rtx set, dest, src, op1, op2, something; ++ rtx set, dest, src; + struct var_to_expand *ves; +- enum machine_mode mode1, mode2; + unsigned accum_pos; ++ enum rtx_code code; + int debug_uses = 0; + + set = single_set (insn); +@@ -1621,12 +1621,20 @@ + + dest = SET_DEST (set); + src = SET_SRC (set); ++ code = GET_CODE (src); + +- if (GET_CODE (src) != PLUS +- && GET_CODE (src) != MINUS +- && GET_CODE (src) != MULT) ++ if (code != PLUS && code != MINUS && code != MULT && code != FMA) + return NULL; + ++ if (FLOAT_MODE_P (GET_MODE (dest))) ++ { ++ if (!flag_associative_math) ++ return NULL; ++ /* In the case of FMA, we're also changing the rounding. */ ++ if (code == FMA && !flag_unsafe_math_optimizations) ++ return NULL; ++ } ++ + /* Hmm, this is a bit paradoxical. We know that INSN is a valid insn + in MD. But if there is no optab to generate the insn, we can not + perform the variable expansion. This can happen if an MD provides +@@ -1636,54 +1644,57 @@ + So we check have_insn_for which looks for an optab for the operation + in SRC. If it doesn't exist, we can't perform the expansion even + though INSN is valid. */ +- if (!have_insn_for (GET_CODE (src), GET_MODE (src))) ++ if (!have_insn_for (code, GET_MODE (src))) + return NULL; + +- op1 = XEXP (src, 0); +- op2 = XEXP (src, 1); +- + if (!REG_P (dest) + && !(GET_CODE (dest) == SUBREG + && REG_P (SUBREG_REG (dest)))) + return NULL; + +- if (rtx_equal_p (dest, op1)) ++ /* Find the accumulator use within the operation. */ ++ if (code == FMA) ++ { ++ /* We only support accumulation via FMA in the ADD position. */ ++ if (!rtx_equal_p (dest, XEXP (src, 2))) ++ return NULL; ++ accum_pos = 2; ++ } ++ else if (rtx_equal_p (dest, XEXP (src, 0))) + accum_pos = 0; +- else if (rtx_equal_p (dest, op2)) +- accum_pos = 1; ++ else if (rtx_equal_p (dest, XEXP (src, 1))) ++ { ++ /* The method of expansion that we are using; which includes the ++ initialization of the expansions with zero and the summation of ++ the expansions at the end of the computation will yield wrong ++ results for (x = something - x) thus avoid using it in that case. */ ++ if (code == MINUS) ++ return NULL; ++ accum_pos = 1; ++ } + else + return NULL; + +- /* The method of expansion that we are using; which includes +- the initialization of the expansions with zero and the summation of +- the expansions at the end of the computation will yield wrong results +- for (x = something - x) thus avoid using it in that case. */ +- if (accum_pos == 1 +- && GET_CODE (src) == MINUS) +- return NULL; +- +- something = (accum_pos == 0) ? op2 : op1; +- +- if (rtx_referenced_p (dest, something)) ++ /* It must not otherwise be used. */ ++ if (code == FMA) ++ { ++ if (rtx_referenced_p (dest, XEXP (src, 0)) ++ || rtx_referenced_p (dest, XEXP (src, 1))) ++ return NULL; ++ } ++ else if (rtx_referenced_p (dest, XEXP (src, 1 - accum_pos))) + return NULL; + ++ /* It must be used in exactly one insn. */ + if (!referenced_in_one_insn_in_loop_p (loop, dest, &debug_uses)) + return NULL; + +- mode1 = GET_MODE (dest); +- mode2 = GET_MODE (something); +- if ((FLOAT_MODE_P (mode1) +- || FLOAT_MODE_P (mode2)) +- && !flag_associative_math) +- return NULL; +- + if (dump_file) +- { +- fprintf (dump_file, +- "\n;; Expanding Accumulator "); +- print_rtl (dump_file, dest); +- fprintf (dump_file, "\n"); +- } ++ { ++ fprintf (dump_file, "\n;; Expanding Accumulator "); ++ print_rtl (dump_file, dest); ++ fprintf (dump_file, "\n"); ++ } + + if (debug_uses) + /* Instead of resetting the debug insns, we could replace each +@@ -2116,7 +2127,8 @@ + return; + + start_sequence (); +- if (ve->op == PLUS || ve->op == MINUS) ++ /* Note that we only accumulate FMA via the ADD operand. */ ++ if (ve->op == PLUS || ve->op == MINUS || ve->op == FMA) + for (i = 0; VEC_iterate (rtx, ve->var_expansions, i, var); i++) + { + if (honor_signed_zero_p) +@@ -2132,6 +2144,12 @@ + zero_init = CONST1_RTX (GET_MODE (var)); + emit_move_insn (var, zero_init); + } ++ else if (ve->op == MULT) ++ for (i = 0; VEC_iterate (rtx, ve->var_expansions, i, var); i++) ++ { ++ zero_init = CONST1_RTX (GET_MODE (var)); ++ emit_move_insn (var, zero_init); ++ } + + seq = get_insns (); + end_sequence (); +@@ -2158,7 +2176,8 @@ + return; + + start_sequence (); +- if (ve->op == PLUS || ve->op == MINUS) ++ /* Note that we only accumulate FMA via the ADD operand. */ ++ if (ve->op == PLUS || ve->op == MINUS || ve->op == FMA) + for (i = 0; VEC_iterate (rtx, ve->var_expansions, i, var); i++) + { + sum = simplify_gen_binary (PLUS, GET_MODE (ve->reg), +Index: gcc/gimplify.c +=================================================================== +--- a/src/gcc/gimplify.c (.../gcc-4_5-branch) ++++ b/src/gcc/gimplify.c (.../ibm/gcc-4_5-branch) +@@ -7065,6 +7065,16 @@ + ret = gimplify_omp_atomic (expr_p, pre_p); + break; + ++ case TRUTH_AND_EXPR: ++ case TRUTH_OR_EXPR: ++ case TRUTH_XOR_EXPR: ++ /* Classified as tcc_expression. */ ++ goto expr_2; ++ ++ case FMA_EXPR: ++ /* Classified as tcc_expression. */ ++ goto expr_3; ++ + case POINTER_PLUS_EXPR: + /* Convert ((type *)A)+offset into &A->field_of_type_and_offset. + The second is gimple immediate saving a need for extra statement. +@@ -7142,16 +7152,28 @@ + break; + } + ++ expr_3: ++ { ++ enum gimplify_status r0, r1, r2; ++ ++ r0 = gimplify_expr (&TREE_OPERAND (*expr_p, 0), pre_p, ++ post_p, is_gimple_val, fb_rvalue); ++ r1 = gimplify_expr (&TREE_OPERAND (*expr_p, 1), pre_p, ++ post_p, is_gimple_val, fb_rvalue); ++ r2 = gimplify_expr (&TREE_OPERAND (*expr_p, 2), pre_p, ++ post_p, is_gimple_val, fb_rvalue); ++ ++ ret = MIN (MIN (r0, r1), r2); ++ break; ++ } ++ + case tcc_declaration: + case tcc_constant: + ret = GS_ALL_DONE; + goto dont_recalculate; + + default: +- gcc_assert (TREE_CODE (*expr_p) == TRUTH_AND_EXPR +- || TREE_CODE (*expr_p) == TRUTH_OR_EXPR +- || TREE_CODE (*expr_p) == TRUTH_XOR_EXPR); +- goto expr_2; ++ gcc_unreachable (); + } + + recalculate_side_effects (*expr_p); +Index: gcc/tree.def +=================================================================== +--- a/src/gcc/tree.def (.../gcc-4_5-branch) ++++ b/src/gcc/tree.def (.../ibm/gcc-4_5-branch) +@@ -1083,6 +1083,24 @@ + the arguments from type t1 to type t2, and then multiplying them. */ + DEFTREECODE (WIDEN_MULT_EXPR, "widen_mult_expr", tcc_binary, 2) + ++/* Widening multiply-accumulate. ++ The first two arguments are of type t1. ++ The third argument and the result are of type t2, such as t2 is at least ++ twice the size of t1. t1 and t2 must be integral or fixed-point types. ++ The expression is equivalent to a WIDEN_MULT_EXPR operation ++ of the first two operands followed by an add or subtract of the third ++ operand. */ ++DEFTREECODE (WIDEN_MULT_PLUS_EXPR, "widen_mult_plus_expr", tcc_expression, 3) ++/* This is like the above, except in the final expression the multiply result ++ is subtracted from t3. */ ++DEFTREECODE (WIDEN_MULT_MINUS_EXPR, "widen_mult_plus_expr", tcc_expression, 3) ++ ++/* Fused multiply-add. ++ All operands and the result are of the same type. No intermediate ++ rounding is performed after multiplying operand one with operand two ++ before adding operand three. */ ++DEFTREECODE (FMA_EXPR, "fma_expr", tcc_expression, 3) ++ + /* Whole vector left/right shift in bits. + Operand 0 is a vector to be shifted. + Operand 1 is an integer shift amount in bits. */ +Index: gcc/expmed.c +=================================================================== +--- a/src/gcc/expmed.c (.../gcc-4_5-branch) ++++ b/src/gcc/expmed.c (.../ibm/gcc-4_5-branch) +@@ -3255,6 +3255,54 @@ + gcc_assert (op0); + return op0; + } ++/* Perform a widening multiplication and return an rtx for the result. ++ MODE is mode of value; OP0 and OP1 are what to multiply (rtx's); ++ TARGET is a suggestion for where to store the result (an rtx). ++ THIS_OPTAB is the optab we should use, it must be either umul_widen_optab ++ or smul_widen_optab. ++ ++ We check specially for a constant integer as OP1, comparing the ++ cost of a widening multiply against the cost of a sequence of shifts ++ and adds. */ ++ ++rtx ++expand_widening_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, ++ int unsignedp, optab this_optab) ++{ ++ bool speed = optimize_insn_for_speed_p (); ++ ++ if (CONST_INT_P (op1) ++ && (INTVAL (op1) >= 0 ++ || GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)) ++ { ++ HOST_WIDE_INT coeff = INTVAL (op1); ++ int max_cost; ++ enum mult_variant variant; ++ struct algorithm algorithm; ++ ++ /* Special case powers of two. */ ++ if (EXACT_POWER_OF_2_OR_ZERO_P (coeff)) ++ { ++ op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab); ++ return expand_shift (LSHIFT_EXPR, mode, op0, ++ build_int_cst (NULL_TREE, floor_log2 (coeff)), ++ target, unsignedp); ++ } ++ ++ /* Exclude cost of op0 from max_cost to match the cost ++ calculation of the synth_mult. */ ++ max_cost = mul_widen_cost[speed][mode]; ++ if (choose_mult_variant (mode, coeff, &algorithm, &variant, ++ max_cost)) ++ { ++ op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab); ++ return expand_mult_const (mode, op0, coeff, target, ++ &algorithm, variant); ++ } ++ } ++ return expand_binop (mode, this_optab, op0, op1, target, ++ unsignedp, OPTAB_LIB_WIDEN); ++} + + /* Return the smallest n such that 2**n >= X. */ + +Index: gcc/cfgexpand.c +=================================================================== +--- a/src/gcc/cfgexpand.c (.../gcc-4_5-branch) ++++ b/src/gcc/cfgexpand.c (.../ibm/gcc-4_5-branch) +@@ -64,7 +64,13 @@ + + grhs_class = get_gimple_rhs_class (gimple_expr_code (stmt)); + +- if (grhs_class == GIMPLE_BINARY_RHS) ++ if (grhs_class == GIMPLE_TERNARY_RHS) ++ t = build3 (gimple_assign_rhs_code (stmt), ++ TREE_TYPE (gimple_assign_lhs (stmt)), ++ gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), ++ gimple_assign_rhs3 (stmt)); ++ else if (grhs_class == GIMPLE_BINARY_RHS) + t = build2 (gimple_assign_rhs_code (stmt), + TREE_TYPE (gimple_assign_lhs (stmt)), + gimple_assign_rhs1 (stmt), +@@ -1893,6 +1899,9 @@ + ops.type = TREE_TYPE (lhs); + switch (get_gimple_rhs_class (gimple_expr_code (stmt))) + { ++ case GIMPLE_TERNARY_RHS: ++ ops.op2 = gimple_assign_rhs3 (stmt); ++ /* Fallthru */ + case GIMPLE_BINARY_RHS: + ops.op1 = gimple_assign_rhs2 (stmt); + /* Fallthru */ +@@ -2243,6 +2252,9 @@ + { + case COND_EXPR: + case DOT_PROD_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ case FMA_EXPR: + goto ternary; + + case TRUTH_ANDIF_EXPR: +@@ -3057,6 +3069,9 @@ + } + return NULL; + ++ case FMA_EXPR: ++ return gen_rtx_FMA (mode, op0, op1, op2); ++ + default: + flag_unsupported: + #ifdef ENABLE_CHECKING +Index: gcc/simplify-rtx.c +=================================================================== +--- a/src/gcc/simplify-rtx.c (.../gcc-4_5-branch) ++++ b/src/gcc/simplify-rtx.c (.../ibm/gcc-4_5-branch) +@@ -813,7 +813,7 @@ + than HOST_BITS_PER_WIDE_INT. */ + if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT + && COMPARISON_P (op) +- && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0) ++ && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0) + return rtl_hooks.gen_lowpart_no_emit (mode, op); + break; + +@@ -912,7 +912,7 @@ + || ((GET_MODE_BITSIZE (GET_MODE (op)) + <= HOST_BITS_PER_WIDE_INT) + && ((nonzero_bits (op, GET_MODE (op)) +- & ((HOST_WIDE_INT) 1 ++ & ((unsigned HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (GET_MODE (op)) - 1))) + == 0))) + return op; +@@ -1010,6 +1010,42 @@ + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (XEXP (op, 0)))) + return rtl_hooks.gen_lowpart_no_emit (mode, op); + ++ /* (sign_extend:M (sign_extend:N )) is (sign_extend:M ). ++ (sign_extend:M (zero_extend:N )) is (zero_extend:M ). */ ++ if (GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND) ++ { ++ gcc_assert (GET_MODE_BITSIZE (mode) ++ > GET_MODE_BITSIZE (GET_MODE (op))); ++ return simplify_gen_unary (GET_CODE (op), mode, XEXP (op, 0), ++ GET_MODE (XEXP (op, 0))); ++ } ++ ++ /* (sign_extend:M (ashiftrt:N (ashift (const_int I)) (const_int I))) ++ is (sign_extend:M (subreg:O )) if there is mode with ++ GET_MODE_BITSIZE (N) - I bits. ++ (sign_extend:M (lshiftrt:N (ashift (const_int I)) (const_int I))) ++ is similarly (zero_extend:M (subreg:O )). */ ++ if ((GET_CODE (op) == ASHIFTRT || GET_CODE (op) == LSHIFTRT) ++ && GET_CODE (XEXP (op, 0)) == ASHIFT ++ && CONST_INT_P (XEXP (op, 1)) ++ && XEXP (XEXP (op, 0), 1) == XEXP (op, 1) ++ && GET_MODE_BITSIZE (GET_MODE (op)) > INTVAL (XEXP (op, 1))) ++ { ++ enum machine_mode tmode ++ = mode_for_size (GET_MODE_BITSIZE (GET_MODE (op)) ++ - INTVAL (XEXP (op, 1)), MODE_INT, 1); ++ gcc_assert (GET_MODE_BITSIZE (mode) ++ > GET_MODE_BITSIZE (GET_MODE (op))); ++ if (tmode != BLKmode) ++ { ++ rtx inner = ++ rtl_hooks.gen_lowpart_no_emit (tmode, XEXP (XEXP (op, 0), 0)); ++ return simplify_gen_unary (GET_CODE (op) == ASHIFTRT ++ ? SIGN_EXTEND : ZERO_EXTEND, ++ mode, inner, tmode); ++ } ++ } ++ + #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) + /* As we do not know which address space the pointer is refering to, + we can do this only if the target does not support different pointer +@@ -1036,6 +1072,31 @@ + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (XEXP (op, 0)))) + return rtl_hooks.gen_lowpart_no_emit (mode, op); + ++ /* (zero_extend:M (zero_extend:N )) is (zero_extend:M ). */ ++ if (GET_CODE (op) == ZERO_EXTEND) ++ return simplify_gen_unary (ZERO_EXTEND, mode, XEXP (op, 0), ++ GET_MODE (XEXP (op, 0))); ++ ++ /* (zero_extend:M (lshiftrt:N (ashift (const_int I)) (const_int I))) ++ is (zero_extend:M (subreg:O )) if there is mode with ++ GET_MODE_BITSIZE (N) - I bits. */ ++ if (GET_CODE (op) == LSHIFTRT ++ && GET_CODE (XEXP (op, 0)) == ASHIFT ++ && CONST_INT_P (XEXP (op, 1)) ++ && XEXP (XEXP (op, 0), 1) == XEXP (op, 1) ++ && GET_MODE_BITSIZE (GET_MODE (op)) > INTVAL (XEXP (op, 1))) ++ { ++ enum machine_mode tmode ++ = mode_for_size (GET_MODE_BITSIZE (GET_MODE (op)) ++ - INTVAL (XEXP (op, 1)), MODE_INT, 1); ++ if (tmode != BLKmode) ++ { ++ rtx inner = ++ rtl_hooks.gen_lowpart_no_emit (tmode, XEXP (XEXP (op, 0), 0)); ++ return simplify_gen_unary (ZERO_EXTEND, mode, inner, tmode); ++ } ++ } ++ + #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) + /* As we do not know which address space the pointer is refering to, + we can do this only if the target does not support different pointer +@@ -1261,7 +1322,8 @@ + case ZERO_EXTEND: + /* When zero-extending a CONST_INT, we need to know its + original mode. */ +- gcc_assert (op_mode != VOIDmode); ++ if (op_mode == VOIDmode) ++ return 0; + if (GET_MODE_BITSIZE (op_mode) == HOST_BITS_PER_WIDE_INT) + { + /* If we were really extending the mode, +@@ -1271,7 +1333,8 @@ + val = arg0; + } + else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT) +- val = arg0 & ~((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (op_mode)); ++ val = arg0 & ~((unsigned HOST_WIDE_INT) (-1) ++ << GET_MODE_BITSIZE (op_mode)); + else + return 0; + break; +@@ -1290,10 +1353,12 @@ + else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT) + { + val +- = arg0 & ~((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (op_mode)); +- if (val +- & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (op_mode) - 1))) +- val -= (HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode); ++ = arg0 & ~((unsigned HOST_WIDE_INT) (-1) ++ << GET_MODE_BITSIZE (op_mode)); ++ if (val & ((unsigned HOST_WIDE_INT) 1 ++ << (GET_MODE_BITSIZE (op_mode) - 1))) ++ val ++ -= (unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode); + } + else + return 0; +@@ -1449,9 +1514,9 @@ + { + lv = l1 & GET_MODE_MASK (op_mode); + if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT +- && (lv & ((HOST_WIDE_INT) 1 ++ && (lv & ((unsigned HOST_WIDE_INT) 1 + << (GET_MODE_BITSIZE (op_mode) - 1))) != 0) +- lv -= (HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode); ++ lv -= (unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode); + + hv = HWI_SIGN_EXTEND (lv); + } +@@ -1557,13 +1622,14 @@ + /* Test against the signed lower bound. */ + if (width > HOST_BITS_PER_WIDE_INT) + { +- th = (HOST_WIDE_INT) -1 << (width - HOST_BITS_PER_WIDE_INT - 1); ++ th = (unsigned HOST_WIDE_INT) (-1) ++ << (width - HOST_BITS_PER_WIDE_INT - 1); + tl = 0; + } + else + { + th = -1; +- tl = (HOST_WIDE_INT) -1 << (width - 1); ++ tl = (unsigned HOST_WIDE_INT) (-1) << (width - 1); + } + real_from_integer (&t, VOIDmode, tl, th, 0); + if (REAL_VALUES_LESS (x, t)) +@@ -2133,7 +2199,7 @@ + /* Convert multiply by constant power of two into shift unless + we are still generating RTL. This test is a kludge. */ + if (CONST_INT_P (trueop1) +- && (val = exact_log2 (INTVAL (trueop1))) >= 0 ++ && (val = exact_log2 (UINTVAL (trueop1))) >= 0 + /* If the mode is larger than the host word size, and the + uppermost bit is set, then this isn't a power of two due + to implicit sign extension. */ +@@ -2199,7 +2265,7 @@ + if (trueop1 == const0_rtx) + return op0; + if (CONST_INT_P (trueop1) +- && ((INTVAL (trueop1) & GET_MODE_MASK (mode)) ++ && ((UINTVAL (trueop1) & GET_MODE_MASK (mode)) + == GET_MODE_MASK (mode))) + return op1; + if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0)) +@@ -2214,7 +2280,7 @@ + /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ + if (CONST_INT_P (op1) + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT +- && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0) ++ && (nonzero_bits (op0, mode) & ~UINTVAL (op1)) == 0) + return op1; + + /* Canonicalize (X & C1) | C2. */ +@@ -2303,12 +2369,12 @@ + && GET_CODE (op0) == AND + && CONST_INT_P (XEXP (op0, 1)) + && CONST_INT_P (op1) +- && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0) ++ && (UINTVAL (XEXP (op0, 1)) & UINTVAL (op1)) != 0) + return simplify_gen_binary (IOR, mode, + simplify_gen_binary + (AND, mode, XEXP (op0, 0), +- GEN_INT (INTVAL (XEXP (op0, 1)) +- & ~INTVAL (op1))), ++ GEN_INT (UINTVAL (XEXP (op0, 1)) ++ & ~UINTVAL (op1))), + op1); + + /* If OP0 is (ashiftrt (plus ...) C), it might actually be +@@ -2341,7 +2407,7 @@ + if (trueop1 == const0_rtx) + return op0; + if (CONST_INT_P (trueop1) +- && ((INTVAL (trueop1) & GET_MODE_MASK (mode)) ++ && ((UINTVAL (trueop1) & GET_MODE_MASK (mode)) + == GET_MODE_MASK (mode))) + return simplify_gen_unary (NOT, mode, op0, mode); + if (rtx_equal_p (trueop0, trueop1) +@@ -2485,7 +2551,7 @@ + && CONST_INT_P (trueop1) + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT + && (~GET_MODE_MASK (GET_MODE (XEXP (op0, 0))) +- & INTVAL (trueop1)) == 0) ++ & UINTVAL (trueop1)) == 0) + { + enum machine_mode imode = GET_MODE (XEXP (op0, 0)); + tem = simplify_gen_binary (AND, imode, XEXP (op0, 0), +@@ -2566,8 +2632,8 @@ + (A +- N) & M -> A & M. */ + if (CONST_INT_P (trueop1) + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT +- && ~INTVAL (trueop1) +- && (INTVAL (trueop1) & (INTVAL (trueop1) + 1)) == 0 ++ && ~UINTVAL (trueop1) ++ && (UINTVAL (trueop1) & (UINTVAL (trueop1) + 1)) == 0 + && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS)) + { + rtx pmop[2]; +@@ -2577,7 +2643,7 @@ + pmop[1] = XEXP (op0, 1); + + if (CONST_INT_P (pmop[1]) +- && (INTVAL (pmop[1]) & INTVAL (trueop1)) == 0) ++ && (UINTVAL (pmop[1]) & UINTVAL (trueop1)) == 0) + return simplify_gen_binary (AND, mode, pmop[0], op1); + + for (which = 0; which < 2; which++) +@@ -2587,14 +2653,14 @@ + { + case AND: + if (CONST_INT_P (XEXP (tem, 1)) +- && (INTVAL (XEXP (tem, 1)) & INTVAL (trueop1)) +- == INTVAL (trueop1)) ++ && (UINTVAL (XEXP (tem, 1)) & UINTVAL (trueop1)) ++ == UINTVAL (trueop1)) + pmop[which] = XEXP (tem, 0); + break; + case IOR: + case XOR: + if (CONST_INT_P (XEXP (tem, 1)) +- && (INTVAL (XEXP (tem, 1)) & INTVAL (trueop1)) == 0) ++ && (UINTVAL (XEXP (tem, 1)) & UINTVAL (trueop1)) == 0) + pmop[which] = XEXP (tem, 0); + break; + default: +@@ -2640,7 +2706,7 @@ + return rtl_hooks.gen_lowpart_no_emit (mode, op0); + /* Convert divide by power of two into shift. */ + if (CONST_INT_P (trueop1) +- && (val = exact_log2 (INTVAL (trueop1))) > 0) ++ && (val = exact_log2 (UINTVAL (trueop1))) > 0) + return simplify_gen_binary (LSHIFTRT, mode, op0, GEN_INT (val)); + break; + +@@ -2722,7 +2788,7 @@ + } + /* Implement modulus by power of two as AND. */ + if (CONST_INT_P (trueop1) +- && exact_log2 (INTVAL (trueop1)) > 0) ++ && exact_log2 (UINTVAL (trueop1)) > 0) + return simplify_gen_binary (AND, mode, op0, + GEN_INT (INTVAL (op1) - 1)); + break; +@@ -2753,7 +2819,7 @@ + return op0; + /* Rotating ~0 always results in ~0. */ + if (CONST_INT_P (trueop0) && width <= HOST_BITS_PER_WIDE_INT +- && (unsigned HOST_WIDE_INT) INTVAL (trueop0) == GET_MODE_MASK (mode) ++ && UINTVAL (trueop0) == GET_MODE_MASK (mode) + && ! side_effects_p (op1)) + return op0; + canonicalize_shift: +@@ -2799,7 +2865,7 @@ + case SMIN: + if (width <= HOST_BITS_PER_WIDE_INT + && CONST_INT_P (trueop1) +- && INTVAL (trueop1) == (HOST_WIDE_INT) 1 << (width -1) ++ && UINTVAL (trueop1) == (unsigned HOST_WIDE_INT) 1 << (width -1) + && ! side_effects_p (op0)) + return op1; + if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0)) +@@ -2812,8 +2878,7 @@ + case SMAX: + if (width <= HOST_BITS_PER_WIDE_INT + && CONST_INT_P (trueop1) +- && ((unsigned HOST_WIDE_INT) INTVAL (trueop1) +- == (unsigned HOST_WIDE_INT) GET_MODE_MASK (mode) >> 1) ++ && (UINTVAL (trueop1) == GET_MODE_MASK (mode) >> 1) + && ! side_effects_p (op0)) + return op1; + if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0)) +@@ -3422,16 +3487,16 @@ + + if (width < HOST_BITS_PER_WIDE_INT) + { +- arg0 &= ((HOST_WIDE_INT) 1 << width) - 1; +- arg1 &= ((HOST_WIDE_INT) 1 << width) - 1; ++ arg0 &= ((unsigned HOST_WIDE_INT) 1 << width) - 1; ++ arg1 &= ((unsigned HOST_WIDE_INT) 1 << width) - 1; + + arg0s = arg0; +- if (arg0s & ((HOST_WIDE_INT) 1 << (width - 1))) +- arg0s |= ((HOST_WIDE_INT) (-1) << width); ++ if (arg0s & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) ++ arg0s |= ((unsigned HOST_WIDE_INT) (-1) << width); + + arg1s = arg1; +- if (arg1s & ((HOST_WIDE_INT) 1 << (width - 1))) +- arg1s |= ((HOST_WIDE_INT) (-1) << width); ++ if (arg1s & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) ++ arg1s |= ((unsigned HOST_WIDE_INT) (-1) << width); + } + else + { +@@ -3457,7 +3522,8 @@ + + case DIV: + if (arg1s == 0 +- || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1) ++ || ((unsigned HOST_WIDE_INT) arg0s ++ == (unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1) + && arg1s == -1)) + return 0; + val = arg0s / arg1s; +@@ -3465,7 +3531,8 @@ + + case MOD: + if (arg1s == 0 +- || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1) ++ || ((unsigned HOST_WIDE_INT) arg0s ++ == (unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1) + && arg1s == -1)) + return 0; + val = arg0s % arg1s; +@@ -3473,7 +3540,8 @@ + + case UDIV: + if (arg1 == 0 +- || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1) ++ || ((unsigned HOST_WIDE_INT) arg0s ++ == (unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1) + && arg1s == -1)) + return 0; + val = (unsigned HOST_WIDE_INT) arg0 / arg1; +@@ -3481,7 +3549,8 @@ + + case UMOD: + if (arg1 == 0 +- || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1) ++ || ((unsigned HOST_WIDE_INT) arg0s ++ == (unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1) + && arg1s == -1)) + return 0; + val = (unsigned HOST_WIDE_INT) arg0 % arg1; +@@ -3520,7 +3589,7 @@ + + /* Sign-extend the result for arithmetic right shifts. */ + if (code == ASHIFTRT && arg0s < 0 && arg1 > 0) +- val |= ((HOST_WIDE_INT) -1) << (width - arg1); ++ val |= ((unsigned HOST_WIDE_INT) (-1)) << (width - arg1); + break; + + case ROTATERT: +@@ -4400,14 +4469,14 @@ + we have to sign or zero-extend the values. */ + if (width != 0 && width < HOST_BITS_PER_WIDE_INT) + { +- l0u &= ((HOST_WIDE_INT) 1 << width) - 1; +- l1u &= ((HOST_WIDE_INT) 1 << width) - 1; ++ l0u &= ((unsigned HOST_WIDE_INT) 1 << width) - 1; ++ l1u &= ((unsigned HOST_WIDE_INT) 1 << width) - 1; + +- if (l0s & ((HOST_WIDE_INT) 1 << (width - 1))) +- l0s |= ((HOST_WIDE_INT) (-1) << width); ++ if (l0s & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) ++ l0s |= ((unsigned HOST_WIDE_INT) (-1) << width); + +- if (l1s & ((HOST_WIDE_INT) 1 << (width - 1))) +- l1s |= ((HOST_WIDE_INT) (-1) << width); ++ if (l1s & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) ++ l1s |= ((unsigned HOST_WIDE_INT) (-1) << width); + } + if (width != 0 && width <= HOST_BITS_PER_WIDE_INT) + h0u = h1u = 0, h0s = HWI_SIGN_EXTEND (l0s), h1s = HWI_SIGN_EXTEND (l1s); +@@ -4560,8 +4629,9 @@ + { + int sign_bitnum = GET_MODE_BITSIZE (mode) - 1; + int has_sign = (HOST_BITS_PER_WIDE_INT >= sign_bitnum +- && (INTVAL (inner_const) +- & ((HOST_WIDE_INT) 1 << sign_bitnum))); ++ && (UINTVAL (inner_const) ++ & ((unsigned HOST_WIDE_INT) 1 ++ << sign_bitnum))); + + switch (code) + { +@@ -4650,6 +4720,8 @@ + rtx op2) + { + unsigned int width = GET_MODE_BITSIZE (mode); ++ bool any_change = false; ++ rtx tem; + + /* VOIDmode means "infinite" precision. */ + if (width == 0) +@@ -4657,6 +4729,31 @@ + + switch (code) + { ++ case FMA: ++ /* Simplify negations around the multiplication. */ ++ /* -a * -b + c => a * b + c. */ ++ if (GET_CODE (op0) == NEG) ++ { ++ tem = simplify_unary_operation (NEG, mode, op1, mode); ++ if (tem) ++ op1 = tem, op0 = XEXP (op0, 0), any_change = true; ++ } ++ else if (GET_CODE (op1) == NEG) ++ { ++ tem = simplify_unary_operation (NEG, mode, op0, mode); ++ if (tem) ++ op0 = tem, op1 = XEXP (op1, 0), any_change = true; ++ } ++ ++ /* Canonicalize the two multiplication operands. */ ++ /* a * -b + c => -b * a + c. */ ++ if (swap_commutative_operands_p (op0, op1)) ++ tem = op0, op0 = op1, op1 = tem, any_change = true; ++ ++ if (any_change) ++ return gen_rtx_FMA (mode, op0, op1, op2); ++ return NULL_RTX; ++ + case SIGN_EXTRACT: + case ZERO_EXTRACT: + if (CONST_INT_P (op0) +@@ -4666,22 +4763,22 @@ + && width <= (unsigned) HOST_BITS_PER_WIDE_INT) + { + /* Extracting a bit-field from a constant */ +- HOST_WIDE_INT val = INTVAL (op0); ++ unsigned HOST_WIDE_INT val = UINTVAL (op0); + + if (BITS_BIG_ENDIAN) +- val >>= (GET_MODE_BITSIZE (op0_mode) +- - INTVAL (op2) - INTVAL (op1)); ++ val >>= GET_MODE_BITSIZE (op0_mode) - INTVAL (op2) - INTVAL (op1); + else + val >>= INTVAL (op2); + + if (HOST_BITS_PER_WIDE_INT != INTVAL (op1)) + { + /* First zero-extend. */ +- val &= ((HOST_WIDE_INT) 1 << INTVAL (op1)) - 1; ++ val &= ((unsigned HOST_WIDE_INT) 1 << INTVAL (op1)) - 1; + /* If desired, propagate sign bit. */ + if (code == SIGN_EXTRACT +- && (val & ((HOST_WIDE_INT) 1 << (INTVAL (op1) - 1)))) +- val |= ~ (((HOST_WIDE_INT) 1 << INTVAL (op1)) - 1); ++ && (val & ((unsigned HOST_WIDE_INT) 1 << (INTVAL (op1) - 1))) ++ != 0) ++ val |= ~ (((unsigned HOST_WIDE_INT) 1 << INTVAL (op1)) - 1); + } + + /* Clear the bits that don't belong in our mode, +@@ -4689,9 +4786,9 @@ + So we get either a reasonable negative value or a reasonable + unsigned value for this mode. */ + if (width < HOST_BITS_PER_WIDE_INT +- && ((val & ((HOST_WIDE_INT) (-1) << (width - 1))) +- != ((HOST_WIDE_INT) (-1) << (width - 1)))) +- val &= ((HOST_WIDE_INT) 1 << width) - 1; ++ && ((val & ((unsigned HOST_WIDE_INT) (-1) << (width - 1))) ++ != ((unsigned HOST_WIDE_INT) (-1) << (width - 1)))) ++ val &= ((unsigned HOST_WIDE_INT) 1 << width) - 1; + + return gen_int_mode (val, mode); + } +@@ -5049,10 +5146,10 @@ + for (i = 0; + i < HOST_BITS_PER_WIDE_INT && i < elem_bitsize; + i += value_bit) +- lo |= (HOST_WIDE_INT)(*vp++ & value_mask) << i; ++ lo |= (unsigned HOST_WIDE_INT)(*vp++ & value_mask) << i; + for (; i < elem_bitsize; i += value_bit) +- hi |= ((HOST_WIDE_INT)(*vp++ & value_mask) +- << (i - HOST_BITS_PER_WIDE_INT)); ++ hi |= (unsigned HOST_WIDE_INT)(*vp++ & value_mask) ++ << (i - HOST_BITS_PER_WIDE_INT); + + /* immed_double_const doesn't call trunc_int_for_mode. I don't + know why. */ +@@ -5105,9 +5202,9 @@ + for (i = 0; + i < HOST_BITS_PER_WIDE_INT && i < elem_bitsize; + i += value_bit) +- f.data.low |= (HOST_WIDE_INT)(*vp++ & value_mask) << i; ++ f.data.low |= (unsigned HOST_WIDE_INT)(*vp++ & value_mask) << i; + for (; i < elem_bitsize; i += value_bit) +- f.data.high |= ((HOST_WIDE_INT)(*vp++ & value_mask) ++ f.data.high |= ((unsigned HOST_WIDE_INT)(*vp++ & value_mask) + << (i - HOST_BITS_PER_WIDE_INT)); + + elems[elem] = CONST_FIXED_FROM_FIXED_VALUE (f, outer_submode); +Index: gcc/tree-ssa-forwprop.c +=================================================================== +--- a/src/gcc/tree-ssa-forwprop.c (.../gcc-4_5-branch) ++++ b/src/gcc/tree-ssa-forwprop.c (.../ibm/gcc-4_5-branch) +@@ -341,7 +341,11 @@ + { + location_t loc = gimple_location (stmt); + enum tree_code code = gimple_assign_rhs_code (stmt); +- if (get_gimple_rhs_class (code) == GIMPLE_BINARY_RHS) ++ if (get_gimple_rhs_class (code) == GIMPLE_TERNARY_RHS) ++ return fold_build3_loc (loc, code, type, gimple_assign_rhs1 (stmt), ++ gimple_assign_rhs2 (stmt), ++ gimple_assign_rhs3 (stmt)); ++ else if (get_gimple_rhs_class (code) == GIMPLE_BINARY_RHS) + return fold_build2_loc (loc, code, type, gimple_assign_rhs1 (stmt), + gimple_assign_rhs2 (stmt)); + else if (get_gimple_rhs_class (code) == GIMPLE_UNARY_RHS) +Index: gcc/common.opt +=================================================================== +--- a/src/gcc/common.opt (.../gcc-4_5-branch) ++++ b/src/gcc/common.opt (.../ibm/gcc-4_5-branch) +@@ -551,6 +551,10 @@ + Common Report Var(flag_forward_propagate) Optimization + Perform a forward propagation pass on RTL + ++ffp-contract= ++Common Joined RejectNegative ++-ffp-contract=[off|on|fast] Perform floating-point expression contraction. ++ + ; Nonzero means don't put addresses of constant functions in registers. + ; Used for compiling the Unix kernel, where strange substitutions are + ; done on the assembly output. +Index: gcc/target-def.h +=================================================================== +--- a/src/gcc/target-def.h (.../gcc-4_5-branch) ++++ b/src/gcc/target-def.h (.../ibm/gcc-4_5-branch) +@@ -60,6 +60,22 @@ + + #define TARGET_ASM_INTEGER default_assemble_integer + ++#ifndef TARGET_ASM_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP ++#define TARGET_ASM_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP default_label_align_after_barrier_max_skip ++#endif ++ ++#ifndef TARGET_ASM_LOOP_ALIGN_MAX_SKIP ++#define TARGET_ASM_LOOP_ALIGN_MAX_SKIP default_loop_align_max_skip ++#endif ++ ++#ifndef TARGET_ASM_LABEL_ALIGN_MAX_SKIP ++#define TARGET_ASM_LABEL_ALIGN_MAX_SKIP default_label_align_max_skip ++#endif ++ ++#ifndef TARGET_ASM_JUMP_ALIGN_MAX_SKIP ++#define TARGET_ASM_JUMP_ALIGN_MAX_SKIP default_jump_align_max_skip ++#endif ++ + #ifndef TARGET_ASM_GLOBALIZE_LABEL + #define TARGET_ASM_GLOBALIZE_LABEL default_globalize_label + #endif +@@ -278,6 +294,10 @@ + TARGET_ASM_BYTE_OP, \ + TARGET_ASM_ALIGNED_INT_OP, \ + TARGET_ASM_UNALIGNED_INT_OP, \ ++ TARGET_ASM_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP, \ ++ TARGET_ASM_LOOP_ALIGN_MAX_SKIP, \ ++ TARGET_ASM_LABEL_ALIGN_MAX_SKIP, \ ++ TARGET_ASM_JUMP_ALIGN_MAX_SKIP, \ + TARGET_ASM_INTEGER, \ + TARGET_ASM_GLOBALIZE_LABEL, \ + TARGET_ASM_GLOBALIZE_DECL_NAME, \ +Index: gcc/tree-vect-stmts.c +=================================================================== +--- a/src/gcc/tree-vect-stmts.c (.../gcc-4_5-branch) ++++ b/src/gcc/tree-vect-stmts.c (.../ibm/gcc-4_5-branch) +@@ -1259,10 +1259,10 @@ + rhs_type = NULL_TREE; + nargs = gimple_call_num_args (stmt); + +- /* Bail out if the function has more than two arguments, we +- do not have interesting builtin functions to vectorize with +- more than two arguments. No arguments is also not good. */ +- if (nargs == 0 || nargs > 2) ++ /* Bail out if the function has more than three arguments, we do not have ++ interesting builtin functions to vectorize with more than two arguments ++ except for fma. No arguments is also not good. */ ++ if (nargs == 0 || nargs > 3) + return false; + + for (i = 0; i < nargs; i++) +@@ -2217,7 +2217,8 @@ + + /* Function vectorizable_operation. + +- Check if STMT performs a binary or unary operation that can be vectorized. ++ Check if STMT performs a binary, unary or ternary operation that can ++ be vectorized. + If VEC_STMT is also passed, vectorize the STMT: create a vectorized + stmt to replace it, put it in VEC_STMT, and insert it at BSI. + Return FALSE if not a vectorizable STMT, TRUE otherwise. */ +@@ -2228,7 +2229,7 @@ + { + tree vec_dest; + tree scalar_dest; +- tree op0, op1 = NULL; ++ tree op0, op1 = NULL_TREE, op2 = NULL_TREE; + stmt_vec_info stmt_info = vinfo_for_stmt (stmt); + tree vectype = STMT_VINFO_VECTYPE (stmt_info); + loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info); +@@ -2240,7 +2241,8 @@ + int icode; + tree def; + gimple def_stmt; +- enum vect_def_type dt[2] = {vect_unknown_def_type, vect_unknown_def_type}; ++ enum vect_def_type dt[3] ++ = {vect_unknown_def_type, vect_unknown_def_type, vect_unknown_def_type}; + gimple new_stmt = NULL; + stmt_vec_info prev_stmt_info; + int nunits_in = TYPE_VECTOR_SUBPARTS (vectype); +@@ -2248,8 +2250,8 @@ + tree vectype_out; + int ncopies; + int j, i; +- VEC(tree,heap) *vec_oprnds0 = NULL, *vec_oprnds1 = NULL; +- tree vop0, vop1; ++ VEC(tree,heap) *vec_oprnds0 = NULL, *vec_oprnds1 = NULL, *vec_oprnds2 = NULL; ++ tree vop0, vop1, vop2; + bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info); + int vf; + +@@ -2298,10 +2300,11 @@ + + /* Support only unary or binary operations. */ + op_type = TREE_CODE_LENGTH (code); +- if (op_type != unary_op && op_type != binary_op) ++ if (op_type != unary_op && op_type != binary_op && op_type != ternary_op) + { + if (vect_print_dump_info (REPORT_DETAILS)) +- fprintf (vect_dump, "num. args = %d (not unary/binary op).", op_type); ++ fprintf (vect_dump, "num. args = %d (not unary/binary/ternary op).", ++ op_type); + return false; + } + +@@ -2313,7 +2316,7 @@ + return false; + } + +- if (op_type == binary_op) ++ if (op_type == binary_op || op_type == ternary_op) + { + op1 = gimple_assign_rhs2 (stmt); + if (!vect_is_simple_use (op1, loop_vinfo, bb_vinfo, &def_stmt, &def, +@@ -2324,6 +2327,17 @@ + return false; + } + } ++ if (op_type == ternary_op) ++ { ++ op2 = gimple_assign_rhs3 (stmt); ++ if (!vect_is_simple_use (op2, loop_vinfo, bb_vinfo, &def_stmt, &def, ++ &dt[2])) ++ { ++ if (vect_print_dump_info (REPORT_DETAILS)) ++ fprintf (vect_dump, "use not simple."); ++ return false; ++ } ++ } + + /* Shifts are handled in vectorizable_shift (). */ + if (code == LSHIFT_EXPR || code == RSHIFT_EXPR || code == LROTATE_EXPR +@@ -2391,8 +2405,10 @@ + if (!slp_node) + { + vec_oprnds0 = VEC_alloc (tree, heap, 1); +- if (op_type == binary_op) ++ if (op_type == binary_op || op_type == ternary_op) + vec_oprnds1 = VEC_alloc (tree, heap, 1); ++ if (op_type == ternary_op) ++ vec_oprnds2 = VEC_alloc (tree, heap, 1); + } + + /* In case the vectorization factor (VF) is bigger than the number +@@ -2454,22 +2470,40 @@ + /* Handle uses. */ + if (j == 0) + { +- if (op_type == binary_op) ++ if (op_type == binary_op || op_type == ternary_op) + vect_get_vec_defs (op0, op1, stmt, &vec_oprnds0, &vec_oprnds1, + slp_node); + else + vect_get_vec_defs (op0, NULL_TREE, stmt, &vec_oprnds0, NULL, + slp_node); ++ if (op_type == ternary_op) ++ { ++ vec_oprnds2 = VEC_alloc (tree, heap, 1); ++ VEC_quick_push (tree, vec_oprnds2, ++ vect_get_vec_def_for_operand (op2, stmt, NULL)); ++ } + } + else +- vect_get_vec_defs_for_stmt_copy (dt, &vec_oprnds0, &vec_oprnds1); ++ { ++ vect_get_vec_defs_for_stmt_copy (dt, &vec_oprnds0, &vec_oprnds1); ++ if (op_type == ternary_op) ++ { ++ tree vec_oprnd = VEC_pop (tree, vec_oprnds2); ++ VEC_quick_push (tree, vec_oprnds2, ++ vect_get_vec_def_for_stmt_copy (dt[2], ++ vec_oprnd)); ++ } ++ } + + /* Arguments are ready. Create the new vector stmt. */ + for (i = 0; VEC_iterate (tree, vec_oprnds0, i, vop0); i++) + { +- vop1 = ((op_type == binary_op) +- ? VEC_index (tree, vec_oprnds1, i) : NULL); +- new_stmt = gimple_build_assign_with_ops (code, vec_dest, vop0, vop1); ++ vop1 = ((op_type == binary_op || op_type == ternary_op) ++ ? VEC_index (tree, vec_oprnds1, i) : NULL_TREE); ++ vop2 = ((op_type == ternary_op) ++ ? VEC_index (tree, vec_oprnds2, i) : NULL_TREE); ++ new_stmt = gimple_build_assign_with_ops3 (code, vec_dest, ++ vop0, vop1, vop2); + new_temp = make_ssa_name (vec_dest, new_stmt); + gimple_assign_set_lhs (new_stmt, new_temp); + vect_finish_stmt_generation (stmt, new_stmt, gsi); +@@ -2490,6 +2524,8 @@ + VEC_free (tree, heap, vec_oprnds0); + if (vec_oprnds1) + VEC_free (tree, heap, vec_oprnds1); ++ if (vec_oprnds2) ++ VEC_free (tree, heap, vec_oprnds2); + + return true; + } +@@ -4360,7 +4396,7 @@ + bool is_store = false; + gimple vec_stmt = NULL; + stmt_vec_info stmt_info = vinfo_for_stmt (stmt); +- gimple orig_stmt_in_pattern; ++ gimple orig_stmt_in_pattern, orig_scalar_stmt = stmt; + bool done; + + switch (STMT_VINFO_TYPE (stmt_info)) +@@ -4433,6 +4469,7 @@ + case call_vec_info_type: + gcc_assert (!slp_node); + done = vectorizable_call (stmt, gsi, &vec_stmt); ++ stmt = gsi_stmt (*gsi); + break; + + case reduc_vec_info_type: +@@ -4512,7 +4549,8 @@ + documentation of vect_pattern_recog. */ + if (STMT_VINFO_IN_PATTERN_P (stmt_vinfo)) + { +- gcc_assert (STMT_VINFO_RELATED_STMT (stmt_vinfo) == stmt); ++ gcc_assert (STMT_VINFO_RELATED_STMT (stmt_vinfo) ++ == orig_scalar_stmt); + STMT_VINFO_VEC_STMT (stmt_vinfo) = vec_stmt; + } + } +Index: gcc/tree-inline.c +=================================================================== +--- a/src/gcc/tree-inline.c (.../gcc-4_5-branch) ++++ b/src/gcc/tree-inline.c (.../ibm/gcc-4_5-branch) +@@ -3145,6 +3145,7 @@ + case POINTER_PLUS_EXPR: + case MINUS_EXPR: + case MULT_EXPR: ++ case FMA_EXPR: + + case ADDR_SPACE_CONVERT_EXPR: + case FIXED_CONVERT_EXPR: +@@ -3206,6 +3207,8 @@ + case WIDEN_SUM_EXPR: + case WIDEN_MULT_EXPR: + case DOT_PROD_EXPR: ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: + + case VEC_WIDEN_MULT_HI_EXPR: + case VEC_WIDEN_MULT_LO_EXPR: +Index: gcc/system.h +=================================================================== +--- a/src/gcc/system.h (.../gcc-4_5-branch) ++++ b/src/gcc/system.h (.../ibm/gcc-4_5-branch) +@@ -708,7 +708,9 @@ + FUNCTION_ARG_PARTIAL_NREGS ASM_OUTPUT_DWARF_DTPREL \ + ALLOCATE_INITIAL_VALUE LEGITIMIZE_ADDRESS FRAME_POINTER_REQUIRED \ + CAN_ELIMINATE TRAMPOLINE_TEMPLATE INITIALIZE_TRAMPOLINE \ +- TRAMPOLINE_ADJUST_ADDRESS STATIC_CHAIN STATIC_CHAIN_INCOMING ++ TRAMPOLINE_ADJUST_ADDRESS STATIC_CHAIN STATIC_CHAIN_INCOMING \ ++ LABEL_ALIGN_MAX_SKIP LOOP_ALIGN_MAX_SKIP \ ++ LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP JUMP_ALIGN_MAX_SKIP + + /* Other obsolete target macros, or macros that used to be in target + headers and were not used, and may be obsolete or may never have +Index: gcc/REVISION +=================================================================== +--- a/src/gcc/REVISION (.../gcc-4_5-branch) ++++ b/src/gcc/REVISION (.../ibm/gcc-4_5-branch) +@@ -0,0 +1 @@ ++Advanced Toolchain 4.xx [merged from gcc-4_5-branch, 171269] +Index: gcc/config.gcc +=================================================================== +--- a/src/gcc/config.gcc (.../gcc-4_5-branch) ++++ b/src/gcc/config.gcc (.../ibm/gcc-4_5-branch) +@@ -346,9 +346,11 @@ + cpu_is_64bit=yes + ;; + esac ++ extra_options="${extra_options} fused-madd.opt" + ;; + rs6000*-*-*) + need_64bit_hwint=yes ++ extra_options="${extra_options} fused-madd.opt" + ;; + score*-*-*) + cpu_type=score +Index: gcc/gimple.c +=================================================================== +--- a/src/gcc/gimple.c (.../gcc-4_5-branch) ++++ b/src/gcc/gimple.c (.../ibm/gcc-4_5-branch) +@@ -289,31 +289,40 @@ + + + /* Extract the operands and code for expression EXPR into *SUBCODE_P, +- *OP1_P and *OP2_P respectively. */ ++ *OP1_P, *OP2_P and *OP3_P respectively. */ + + void +-extract_ops_from_tree (tree expr, enum tree_code *subcode_p, tree *op1_p, +- tree *op2_p) ++extract_ops_from_tree_1 (tree expr, enum tree_code *subcode_p, tree *op1_p, ++ tree *op2_p, tree *op3_p) + { + enum gimple_rhs_class grhs_class; + + *subcode_p = TREE_CODE (expr); + grhs_class = get_gimple_rhs_class (*subcode_p); + +- if (grhs_class == GIMPLE_BINARY_RHS) ++ if (grhs_class == GIMPLE_TERNARY_RHS) + { + *op1_p = TREE_OPERAND (expr, 0); + *op2_p = TREE_OPERAND (expr, 1); ++ *op3_p = TREE_OPERAND (expr, 2); + } ++ else if (grhs_class == GIMPLE_BINARY_RHS) ++ { ++ *op1_p = TREE_OPERAND (expr, 0); ++ *op2_p = TREE_OPERAND (expr, 1); ++ *op3_p = NULL_TREE; ++ } + else if (grhs_class == GIMPLE_UNARY_RHS) + { + *op1_p = TREE_OPERAND (expr, 0); + *op2_p = NULL_TREE; ++ *op3_p = NULL_TREE; + } + else if (grhs_class == GIMPLE_SINGLE_RHS) + { + *op1_p = expr; + *op2_p = NULL_TREE; ++ *op3_p = NULL_TREE; + } + else + gcc_unreachable (); +@@ -329,10 +338,10 @@ + gimple_build_assign_stat (tree lhs, tree rhs MEM_STAT_DECL) + { + enum tree_code subcode; +- tree op1, op2; ++ tree op1, op2, op3; + +- extract_ops_from_tree (rhs, &subcode, &op1, &op2); +- return gimple_build_assign_with_ops_stat (subcode, lhs, op1, op2 ++ extract_ops_from_tree_1 (rhs, &subcode, &op1, &op2, &op3); ++ return gimple_build_assign_with_ops_stat (subcode, lhs, op1, op2, op3 + PASS_MEM_STAT); + } + +@@ -343,7 +352,7 @@ + + gimple + gimple_build_assign_with_ops_stat (enum tree_code subcode, tree lhs, tree op1, +- tree op2 MEM_STAT_DECL) ++ tree op2, tree op3 MEM_STAT_DECL) + { + unsigned num_ops; + gimple p; +@@ -362,6 +371,12 @@ + gimple_assign_set_rhs2 (p, op2); + } + ++ if (op3) ++ { ++ gcc_assert (num_ops > 3); ++ gimple_assign_set_rhs3 (p, op3); ++ } ++ + return p; + } + +@@ -1860,10 +1875,10 @@ + gimple_assign_set_rhs_from_tree (gimple_stmt_iterator *gsi, tree expr) + { + enum tree_code subcode; +- tree op1, op2; ++ tree op1, op2, op3; + +- extract_ops_from_tree (expr, &subcode, &op1, &op2); +- gimple_assign_set_rhs_with_ops (gsi, subcode, op1, op2); ++ extract_ops_from_tree_1 (expr, &subcode, &op1, &op2, &op3); ++ gimple_assign_set_rhs_with_ops_1 (gsi, subcode, op1, op2, op3); + } + + +@@ -1874,8 +1889,8 @@ + did not have enough operand slots. */ + + void +-gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *gsi, enum tree_code code, +- tree op1, tree op2) ++gimple_assign_set_rhs_with_ops_1 (gimple_stmt_iterator *gsi, enum tree_code code, ++ tree op1, tree op2, tree op3) + { + unsigned new_rhs_ops = get_gimple_rhs_num_ops (code); + gimple stmt = gsi_stmt (*gsi); +@@ -1899,6 +1914,8 @@ + gimple_assign_set_rhs1 (stmt, op1); + if (new_rhs_ops > 1) + gimple_assign_set_rhs2 (stmt, op2); ++ if (new_rhs_ops > 2) ++ gimple_assign_set_rhs3 (stmt, op3); + } + + +@@ -2378,6 +2395,8 @@ + return 1; + else if (rhs_class == GIMPLE_BINARY_RHS) + return 2; ++ else if (rhs_class == GIMPLE_TERNARY_RHS) ++ return 3; + else + gcc_unreachable (); + } +@@ -2394,6 +2413,9 @@ + || (SYM) == TRUTH_OR_EXPR \ + || (SYM) == TRUTH_XOR_EXPR) ? GIMPLE_BINARY_RHS \ + : (SYM) == TRUTH_NOT_EXPR ? GIMPLE_UNARY_RHS \ ++ : ((SYM) == WIDEN_MULT_PLUS_EXPR \ ++ || (SYM) == WIDEN_MULT_MINUS_EXPR \ ++ || (SYM) == FMA_EXPR) ? GIMPLE_TERNARY_RHS \ + : ((SYM) == COND_EXPR \ + || (SYM) == CONSTRUCTOR \ + || (SYM) == OBJ_TYPE_REF \ +Index: gcc/gimple.h +=================================================================== +--- a/src/gcc/gimple.h (.../gcc-4_5-branch) ++++ b/src/gcc/gimple.h (.../ibm/gcc-4_5-branch) +@@ -80,6 +80,7 @@ + enum gimple_rhs_class + { + GIMPLE_INVALID_RHS, /* The expression cannot be used on the RHS. */ ++ GIMPLE_TERNARY_RHS, /* The expression is a ternary operation. */ + GIMPLE_BINARY_RHS, /* The expression is a binary operation. */ + GIMPLE_UNARY_RHS, /* The expression is a unary operation. */ + GIMPLE_SINGLE_RHS /* The expression is a single object (an SSA +@@ -786,12 +787,14 @@ + gimple gimple_build_assign_stat (tree, tree MEM_STAT_DECL); + #define gimple_build_assign(l,r) gimple_build_assign_stat (l, r MEM_STAT_INFO) + +-void extract_ops_from_tree (tree, enum tree_code *, tree *, tree *); ++void extract_ops_from_tree_1 (tree, enum tree_code *, tree *, tree *, tree *); + + gimple gimple_build_assign_with_ops_stat (enum tree_code, tree, tree, +- tree MEM_STAT_DECL); +-#define gimple_build_assign_with_ops(c,o1,o2,o3) \ +- gimple_build_assign_with_ops_stat (c, o1, o2, o3 MEM_STAT_INFO) ++ tree, tree MEM_STAT_DECL); ++#define gimple_build_assign_with_ops(c,o1,o2,o3) \ ++ gimple_build_assign_with_ops_stat (c, o1, o2, o3, NULL_TREE MEM_STAT_INFO) ++#define gimple_build_assign_with_ops3(c,o1,o2,o3,o4) \ ++ gimple_build_assign_with_ops_stat (c, o1, o2, o3, o4 MEM_STAT_INFO) + + gimple gimple_build_debug_bind_stat (tree, tree, gimple MEM_STAT_DECL); + #define gimple_build_debug_bind(var,val,stmt) \ +@@ -850,8 +853,8 @@ + bool gimple_assign_unary_nop_p (gimple); + void gimple_set_bb (gimple, struct basic_block_def *); + void gimple_assign_set_rhs_from_tree (gimple_stmt_iterator *, tree); +-void gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *, enum tree_code, +- tree, tree); ++void gimple_assign_set_rhs_with_ops_1 (gimple_stmt_iterator *, enum tree_code, ++ tree, tree, tree); + tree gimple_get_lhs (const_gimple); + void gimple_set_lhs (gimple, tree); + void gimple_replace_lhs (gimple, tree); +@@ -1793,6 +1796,56 @@ + gimple_set_op (gs, 2, rhs); + } + ++ ++/* Return the third operand on the RHS of assignment statement GS. ++ If GS does not have two operands, NULL is returned instead. */ ++ ++static inline tree ++gimple_assign_rhs3 (const_gimple gs) ++{ ++ GIMPLE_CHECK (gs, GIMPLE_ASSIGN); ++ ++ if (gimple_num_ops (gs) >= 4) ++ return gimple_op (gs, 3); ++ else ++ return NULL_TREE; ++} ++ ++ ++/* Set RHS to be the third operand on the RHS of assignment statement GS. */ ++ ++static inline void ++gimple_assign_set_rhs3 (gimple gs, tree rhs) ++{ ++ GIMPLE_CHECK (gs, GIMPLE_ASSIGN); ++ ++ gimple_set_op (gs, 3, rhs); ++} ++ ++ ++/* A wrapper around gimple_assign_set_rhs_with_ops_1, for callers which expect ++ to see only a maximum of two operands. */ ++ ++static inline void ++gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *gsi, enum tree_code code, ++ tree op1, tree op2) ++{ ++ gimple_assign_set_rhs_with_ops_1 (gsi, code, op1, op2, NULL); ++} ++ ++/* A wrapper around extract_ops_from_tree_1, for callers which expect ++ to see only a maximum of two operands. */ ++ ++static inline void ++extract_ops_from_tree (tree expr, enum tree_code *code, tree *op0, ++ tree *op1) ++{ ++ tree op2; ++ extract_ops_from_tree_1 (expr, code, op0, op1, &op2); ++ gcc_assert (op2 == NULL_TREE); ++} ++ ++ + /* Returns true if GS is a nontemporal move. */ + + static inline bool +Index: gcc/tree-cfg.c +=================================================================== +--- a/src/gcc/tree-cfg.c (.../gcc-4_5-branch) ++++ b/src/gcc/tree-cfg.c (.../ibm/gcc-4_5-branch) +@@ -3478,6 +3478,79 @@ + return false; + } + ++/* Verify a gimple assignment statement STMT with a ternary rhs. ++ Returns true if anything is wrong. */ ++ ++static bool ++verify_gimple_assign_ternary (gimple stmt) ++{ ++ enum tree_code rhs_code = gimple_assign_rhs_code (stmt); ++ tree lhs = gimple_assign_lhs (stmt); ++ tree lhs_type = TREE_TYPE (lhs); ++ tree rhs1 = gimple_assign_rhs1 (stmt); ++ tree rhs1_type = TREE_TYPE (rhs1); ++ tree rhs2 = gimple_assign_rhs2 (stmt); ++ tree rhs2_type = TREE_TYPE (rhs2); ++ tree rhs3 = gimple_assign_rhs3 (stmt); ++ tree rhs3_type = TREE_TYPE (rhs3); ++ ++ if (!is_gimple_reg (lhs) ++ && !(optimize == 0 ++ && TREE_CODE (lhs_type) == COMPLEX_TYPE)) ++ { ++ error ("non-register as LHS of ternary operation"); ++ return true; ++ } ++ ++ if (!is_gimple_val (rhs1) ++ || !is_gimple_val (rhs2) ++ || !is_gimple_val (rhs3)) ++ { ++ error ("invalid operands in ternary operation"); ++ return true; ++ } ++ ++ /* First handle operations that involve different types. */ ++ switch (rhs_code) ++ { ++ case WIDEN_MULT_PLUS_EXPR: ++ case WIDEN_MULT_MINUS_EXPR: ++ if ((!INTEGRAL_TYPE_P (rhs1_type) ++ && !FIXED_POINT_TYPE_P (rhs1_type)) ++ || !useless_type_conversion_p (rhs1_type, rhs2_type) ++ || !useless_type_conversion_p (lhs_type, rhs3_type) ++ || 2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type) ++ || TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type)) ++ { ++ error ("type mismatch in widening multiply-accumulate expression"); ++ debug_generic_expr (lhs_type); ++ debug_generic_expr (rhs1_type); ++ debug_generic_expr (rhs2_type); ++ debug_generic_expr (rhs3_type); ++ return true; ++ } ++ break; ++ ++ case FMA_EXPR: ++ if (!useless_type_conversion_p (lhs_type, rhs1_type) ++ || !useless_type_conversion_p (lhs_type, rhs2_type) ++ || !useless_type_conversion_p (lhs_type, rhs3_type)) ++ { ++ error ("type mismatch in fused multiply-add expression"); ++ debug_generic_expr (lhs_type); ++ debug_generic_expr (rhs1_type); ++ debug_generic_expr (rhs2_type); ++ debug_generic_expr (rhs3_type); ++ return true; ++ } ++ break; ++ ++ default: ++ gcc_unreachable (); ++ } ++ return false; ++} ++ + /* Verify a gimple assignment statement STMT with a single rhs. + Returns true if anything is wrong. */ + +@@ -3610,6 +3683,9 @@ + case GIMPLE_BINARY_RHS: + return verify_gimple_assign_binary (stmt); + ++ case GIMPLE_TERNARY_RHS: ++ return verify_gimple_assign_ternary (stmt); ++ + default: + gcc_unreachable (); + } +Index: gcc/passes.c +=================================================================== +--- a/src/gcc/passes.c (.../gcc-4_5-branch) ++++ b/src/gcc/passes.c (.../ibm/gcc-4_5-branch) +@@ -944,6 +944,7 @@ + NEXT_PASS (pass_forwprop); + NEXT_PASS (pass_phiopt); + NEXT_PASS (pass_fold_builtins); ++ NEXT_PASS (pass_optimize_widening_mul); + NEXT_PASS (pass_tail_calls); + NEXT_PASS (pass_rename_ssa_copies); + NEXT_PASS (pass_uncprop); +Index: gcc/config/fused-madd.opt +=================================================================== +--- a/src/gcc/config/fused-madd.opt (.../gcc-4_5-branch) ++++ b/src/gcc/config/fused-madd.opt (.../ibm/gcc-4_5-branch) +@@ -0,0 +1,25 @@ ++; -mfused-madd option (some targets only). ++; ++; Copyright (C) 2010 ++; Free Software Foundation, Inc. ++; ++; This file is part of GCC. ++; ++; GCC is free software; you can redistribute it and/or modify it under ++; the terms of the GNU General Public License as published by the Free ++; Software Foundation; either version 3, or (at your option) any later ++; version. ++; ++; GCC is distributed in the hope that it will be useful, but WITHOUT ANY ++; WARRANTY; without even the implied warranty of MERCHANTABILITY or ++; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++; for more details. ++; ++; You should have received a copy of the GNU General Public License ++; along with GCC; see the file COPYING3. If not see ++; . ++ ++mfused-madd ++Target Undocumented Alias(ffp-contract=, fast, off) Warn(%<-mfused-madd%> is deprecated; use %<-ffp-contract=%> instead) ++ ++; This comment is to ensure we retain the blank line above. +Index: gcc/config/rs6000/linux.h +=================================================================== +--- a/src/gcc/config/rs6000/linux.h (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/linux.h (.../ibm/gcc-4_5-branch) +@@ -111,8 +111,6 @@ + #define RELOCATABLE_NEEDS_FIXUP \ + (target_flags & target_flags_explicit & MASK_RELOCATABLE) + +-#define TARGET_ASM_FILE_END file_end_indicate_exec_stack +- + #define TARGET_POSIX_IO + + #define MD_UNWIND_SUPPORT "config/rs6000/linux-unwind.h" +Index: gcc/config/rs6000/vector.md +=================================================================== +--- a/src/gcc/config/rs6000/vector.md (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/vector.md (.../ibm/gcc-4_5-branch) +@@ -239,16 +239,14 @@ + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] +- "(VECTOR_UNIT_VSX_P (mode) +- || (VECTOR_UNIT_ALTIVEC_P (mode) && TARGET_FUSED_MADD))" +- " ++ "VECTOR_UNIT_VSX_P (mode) || VECTOR_UNIT_ALTIVEC_P (mode)" + { + if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode)) + { + emit_insn (gen_altivec_mulv4sf3 (operands[0], operands[1], operands[2])); + DONE; + } +-}") ++}) + + (define_expand "div3" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") +@@ -304,6 +302,20 @@ + "VECTOR_UNIT_VSX_P (mode)" + "") + ++(define_expand "rsqrte2" ++ [(set (match_operand:VEC_F 0 "vfloat_operand" "") ++ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")] ++ UNSPEC_RSQRT))] ++ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" ++ "") ++ ++(define_expand "re2" ++ [(set (match_operand:VEC_F 0 "vfloat_operand" "") ++ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "f")] ++ UNSPEC_FRES))] ++ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" ++ "") ++ + (define_expand "ftrunc2" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] +@@ -332,11 +344,8 @@ + + (define_expand "vector_copysign3" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") +- (if_then_else:VEC_F +- (ge:VEC_F (match_operand:VEC_F 2 "vfloat_operand" "") +- (match_dup 3)) +- (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")) +- (neg:VEC_F (abs:VEC_F (match_dup 1)))))] ++ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "") ++ (match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + " + { +@@ -346,8 +355,6 @@ + operands[2])); + DONE; + } +- +- operands[3] = CONST0_RTX (mode); + }") + + +Index: gcc/config/rs6000/darwin.md +=================================================================== +--- a/src/gcc/config/rs6000/darwin.md (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/darwin.md (.../ibm/gcc-4_5-branch) +@@ -141,11 +141,13 @@ + + ;; 64-bit MachO load/store support + (define_insn "movdi_low" +- [(set (match_operand:DI 0 "gpc_reg_operand" "=r") +- (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") ++ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d") ++ (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") + (match_operand 2 "" ""))))] + "TARGET_MACHO && TARGET_64BIT" +- "{l|ld} %0,lo16(%2)(%1)" ++ "@ ++ {l|ld} %0,lo16(%2)(%1) ++ lfd %0,lo16(%2)(%1)" + [(set_attr "type" "load") + (set_attr "length" "4")]) + +@@ -159,11 +161,13 @@ + (set_attr "length" "4")]) + + (define_insn "movdi_low_st" +- [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") ++ [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") + (match_operand 2 "" ""))) +- (match_operand:DI 0 "gpc_reg_operand" "r"))] ++ (match_operand:DI 0 "gpc_reg_operand" "r,*!d"))] + "TARGET_MACHO && TARGET_64BIT" +- "{st|std} %0,lo16(%2)(%1)" ++ "@ ++ {st|std} %0,lo16(%2)(%1) ++ stfd %0,lo16(%2)(%1)" + [(set_attr "type" "store") + (set_attr "length" "4")]) + +Index: gcc/config/rs6000/constraints.md +=================================================================== +--- a/src/gcc/config/rs6000/constraints.md (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/constraints.md (.../ibm/gcc-4_5-branch) +@@ -166,7 +166,7 @@ + + (define_constraint "R" + "AIX TOC entry" +- (match_test "legitimate_constant_pool_address_p (op)")) ++ (match_test "legitimate_constant_pool_address_p (op, QImode, false)")) + + ;; General constraints + +Index: gcc/config/rs6000/predicates.md +=================================================================== +--- a/src/gcc/config/rs6000/predicates.md (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/predicates.md (.../ibm/gcc-4_5-branch) +@@ -327,13 +327,11 @@ + if (TARGET_PAIRED_FLOAT) + return false; + +- if ((VSX_VECTOR_MODE (mode) || mode == TImode) && zero_constant (op, mode)) +- return true; +- +- if (ALTIVEC_VECTOR_MODE (mode)) ++ if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) + { + if (zero_constant (op, mode)) +- return true; ++ return true; ++ + return easy_altivec_constant (op, mode); + } + +@@ -372,7 +370,10 @@ + (and (match_test "TARGET_ALTIVEC") + (match_test "easy_altivec_constant (op, mode)"))) + { +- HOST_WIDE_INT val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1); ++ HOST_WIDE_INT val; ++ if (mode == V2DImode || mode == V2DFmode) ++ return 0; ++ val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1); + val = ((val & 0xff) ^ 0x80) - 0x80; + return EASY_VECTOR_15_ADD_SELF (val); + }) +@@ -383,7 +384,10 @@ + (and (match_test "TARGET_ALTIVEC") + (match_test "easy_altivec_constant (op, mode)"))) + { +- HOST_WIDE_INT val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1); ++ HOST_WIDE_INT val; ++ if (mode == V2DImode || mode == V2DFmode) ++ return 0; ++ val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1); + return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode)); + }) + +@@ -430,9 +434,12 @@ + op = XEXP (op, 0); + else if (GET_CODE (op) == PRE_MODIFY) + op = XEXP (op, 1); ++ else if (GET_CODE (op) == LO_SUM ++ && GET_CODE (XEXP (op, 0)) == REG ++ && GET_CODE (XEXP (op, 1)) == CONST) ++ op = XEXP (XEXP (op, 1), 0); + + return (GET_CODE (op) != PLUS +- || ! REG_P (XEXP (op, 0)) + || GET_CODE (XEXP (op, 1)) != CONST_INT + || INTVAL (XEXP (op, 1)) % 4 == 0); + }) +@@ -735,20 +742,32 @@ + (define_predicate "lwa_operand" + (match_code "reg,subreg,mem") + { +- rtx inner = op; ++ rtx inner, addr, offset; + ++ inner = op; + if (reload_completed && GET_CODE (inner) == SUBREG) + inner = SUBREG_REG (inner); + +- return gpc_reg_operand (inner, mode) +- || (memory_operand (inner, mode) +- && GET_CODE (XEXP (inner, 0)) != PRE_INC +- && GET_CODE (XEXP (inner, 0)) != PRE_DEC +- && (GET_CODE (XEXP (inner, 0)) != PRE_MODIFY +- || legitimate_indexed_address_p (XEXP (XEXP (inner, 0), 1), 0)) +- && (GET_CODE (XEXP (inner, 0)) != PLUS +- || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT +- || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); ++ if (gpc_reg_operand (inner, mode)) ++ return true; ++ if (!memory_operand (inner, mode)) ++ return false; ++ addr = XEXP (inner, 0); ++ if (GET_CODE (addr) == PRE_INC ++ || GET_CODE (addr) == PRE_DEC ++ || (GET_CODE (addr) == PRE_MODIFY ++ && !legitimate_indexed_address_p (XEXP (addr, 1), 0))) ++ return false; ++ if (GET_CODE (addr) == LO_SUM ++ && GET_CODE (XEXP (addr, 0)) == REG ++ && GET_CODE (XEXP (addr, 1)) == CONST) ++ addr = XEXP (XEXP (addr, 1), 0); ++ if (GET_CODE (addr) != PLUS) ++ return true; ++ offset = XEXP (addr, 1); ++ if (GET_CODE (offset) != CONST_INT) ++ return true; ++ return INTVAL (offset) % 4 == 0; + }) + + ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. +@@ -837,7 +856,7 @@ + return 1; + + /* A SYMBOL_REF referring to the TOC is valid. */ +- if (legitimate_constant_pool_address_p (op)) ++ if (legitimate_constant_pool_address_p (op, mode, false)) + return 1; + + /* A constant pool expression (relative to the TOC) is valid */ +@@ -854,6 +873,23 @@ + return 0; + }) + ++;; Return 1 if this operand is a valid input for a vsx_splat insn. ++(define_predicate "splat_input_operand" ++ (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem, ++ const_double,const_vector,const_int,plus") ++{ ++ if (MEM_P (op)) ++ { ++ if (mode == DFmode) ++ mode = V2DFmode; ++ else if (mode == DImode) ++ mode = V2DImode; ++ else ++ gcc_unreachable (); ++ } ++ return input_operand (op, mode); ++}) ++ + ;; Return true if OP is an invalid SUBREG operation on the e500. + (define_predicate "rs6000_nonimmediate_operand" + (match_code "reg,subreg,mem") +Index: gcc/config/rs6000/linux64.opt +=================================================================== +--- a/src/gcc/config/rs6000/linux64.opt (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/linux64.opt (.../ibm/gcc-4_5-branch) +@@ -22,3 +22,7 @@ + mprofile-kernel + Target Report Var(profile_kernel) + Call mcount for profiling before a function prologue ++ ++mcmodel= ++Target RejectNegative Joined ++Select code model +Index: gcc/config/rs6000/paired.md +=================================================================== +--- a/src/gcc/config/rs6000/paired.md (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/paired.md (.../ibm/gcc-4_5-branch) +@@ -96,77 +96,85 @@ + + (define_insn "paired_madds0" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") +- (vec_concat:V2SF +- (plus:SF (mult:SF (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f") +- (parallel [(const_int 0)])) +- (vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f") +- (parallel [(const_int 0)]))) +- (vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f") +- (parallel [(const_int 0)]))) +- (plus:SF (mult:SF (vec_select:SF (match_dup 1) +- (parallel [(const_int 1)])) +- (vec_select:SF (match_dup 2) +- (parallel [(const_int 0)]))) +- (vec_select:SF (match_dup 3) +- (parallel [(const_int 1)])))))] +- "TARGET_PAIRED_FLOAT && TARGET_FUSED_MADD" ++ (vec_concat:V2SF ++ (fma:SF ++ (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f") ++ (parallel [(const_int 0)])) ++ (vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f") ++ (parallel [(const_int 0)])) ++ (vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f") ++ (parallel [(const_int 0)]))) ++ (fma:SF ++ (vec_select:SF (match_dup 1) ++ (parallel [(const_int 1)])) ++ (vec_select:SF (match_dup 2) ++ (parallel [(const_int 0)])) ++ (vec_select:SF (match_dup 3) ++ (parallel [(const_int 1)])))))] ++ "TARGET_PAIRED_FLOAT" + "ps_madds0 %0,%1,%2,%3" + [(set_attr "type" "fp")]) + + (define_insn "paired_madds1" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") +- (vec_concat:V2SF +- (plus:SF (mult:SF (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f") +- (parallel [(const_int 0)])) +- (vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f") +- (parallel [(const_int 1)]))) +- (vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f") +- (parallel [(const_int 0)]))) +- (plus:SF (mult:SF (vec_select:SF (match_dup 1) +- (parallel [(const_int 1)])) +- (vec_select:SF (match_dup 2) +- (parallel [(const_int 1)]))) +- (vec_select:SF (match_dup 3) +- (parallel [(const_int 1)])))))] +- "TARGET_PAIRED_FLOAT && TARGET_FUSED_MADD" ++ (vec_concat:V2SF ++ (fma:SF ++ (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f") ++ (parallel [(const_int 0)])) ++ (vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f") ++ (parallel [(const_int 1)])) ++ (vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f") ++ (parallel [(const_int 0)]))) ++ (fma:SF ++ (vec_select:SF (match_dup 1) ++ (parallel [(const_int 1)])) ++ (vec_select:SF (match_dup 2) ++ (parallel [(const_int 1)])) ++ (vec_select:SF (match_dup 3) ++ (parallel [(const_int 1)])))))] ++ "TARGET_PAIRED_FLOAT" + "ps_madds1 %0,%1,%2,%3" + [(set_attr "type" "fp")]) + +-(define_insn "paired_madd" ++(define_insn "*paired_madd" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") +- (plus:V2SF (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f") +- (match_operand:V2SF 2 "gpc_reg_operand" "f")) +- (match_operand:V2SF 3 "gpc_reg_operand" "f")))] +- "TARGET_PAIRED_FLOAT && TARGET_FUSED_MADD" ++ (fma:V2SF ++ (match_operand:V2SF 1 "gpc_reg_operand" "f") ++ (match_operand:V2SF 2 "gpc_reg_operand" "f") ++ (match_operand:V2SF 3 "gpc_reg_operand" "f")))] ++ "TARGET_PAIRED_FLOAT" + "ps_madd %0,%1,%2,%3" + [(set_attr "type" "fp")]) + +-(define_insn "paired_msub" ++(define_insn "*paired_msub" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") +- (minus:V2SF (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f") +- (match_operand:V2SF 2 "gpc_reg_operand" "f")) +- (match_operand:V2SF 3 "gpc_reg_operand" "f")))] +- "TARGET_PAIRED_FLOAT && TARGET_FUSED_MADD" ++ (fma:V2SF ++ (match_operand:V2SF 1 "gpc_reg_operand" "f") ++ (match_operand:V2SF 2 "gpc_reg_operand" "f") ++ (neg:V2SF (match_operand:V2SF 3 "gpc_reg_operand" "f"))))] ++ "TARGET_PAIRED_FLOAT" + "ps_msub %0,%1,%2,%3" + [(set_attr "type" "fp")]) + +-(define_insn "paired_nmadd" ++(define_insn "*paired_nmadd" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") +- (neg:V2SF (plus:V2SF (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f") +- (match_operand:V2SF 2 "gpc_reg_operand" "f")) +- (match_operand:V2SF 3 "gpc_reg_operand" "f"))))] +- "TARGET_PAIRED_FLOAT && TARGET_FUSED_MADD +- && HONOR_SIGNED_ZEROS (SFmode)" ++ (neg:V2SF ++ (fma:V2SF ++ (match_operand:V2SF 1 "gpc_reg_operand" "f") ++ (match_operand:V2SF 2 "gpc_reg_operand" "f") ++ (match_operand:V2SF 3 "gpc_reg_operand" "f"))))] ++ "TARGET_PAIRED_FLOAT" + "ps_nmadd %0,%1,%2,%3" + [(set_attr "type" "fp")]) + +-(define_insn "paired_nmsub" ++(define_insn "*paired_nmsub" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") +- (neg:V2SF (minus:V2SF (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f") +- (match_operand:V2SF 2 "gpc_reg_operand" "f")) +- (match_operand:V2SF 3 "gpc_reg_operand" "f"))))] +- "TARGET_PAIRED_FLOAT && TARGET_FUSED_MADD +- && HONOR_SIGNED_ZEROS (DFmode)" ++ (neg:V2SF ++ (fma:V2SF ++ (match_operand:V2SF 1 "gpc_reg_operand" "f") ++ (match_operand:V2SF 2 "gpc_reg_operand" "f") ++ (neg:V2SF (match_operand:V2SF 3 "gpc_reg_operand" "f")))))] ++ "TARGET_PAIRED_FLOAT" + "ps_nmsub %0,%1,%2,%3" + [(set_attr "type" "dmul")]) + +Index: gcc/config/rs6000/rs6000-protos.h +=================================================================== +--- a/src/gcc/config/rs6000/rs6000-protos.h (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/rs6000-protos.h (.../ibm/gcc-4_5-branch) +@@ -28,7 +28,8 @@ + #ifdef RTX_CODE + + #ifdef TREE_CODE +-extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int); ++extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int, ++ tree, enum machine_mode); + #endif /* TREE_CODE */ + + extern bool easy_altivec_constant (rtx, enum machine_mode); +@@ -40,7 +41,8 @@ + extern bool toc_relative_expr_p (rtx); + extern bool invalid_e500_subreg (rtx, enum machine_mode); + extern void validate_condition_mode (enum rtx_code, enum machine_mode); +-extern bool legitimate_constant_pool_address_p (rtx); ++extern bool legitimate_constant_pool_address_p (const_rtx, enum machine_mode, ++ bool); + extern bool legitimate_indirect_address_p (rtx, int); + extern bool legitimate_indexed_address_p (rtx, int); + extern bool avoiding_indexed_address_p (enum machine_mode); +@@ -77,6 +79,7 @@ + enum machine_mode, + enum reg_class); + extern void rs6000_secondary_reload_inner (rtx, rtx, rtx, bool); ++extern void rs6000_secondary_reload_ppc64 (rtx, rtx, rtx, bool); + extern int paired_emit_vector_cond_expr (rtx, rtx, rtx, + rtx, rtx, rtx); + extern void paired_expand_vector_move (rtx operands[]); +@@ -107,13 +110,12 @@ + extern void rs6000_expand_compare_and_swapqhi (rtx, rtx, rtx, rtx); + extern void rs6000_split_compare_and_swapqhi (rtx, rtx, rtx, rtx, rtx, rtx); + extern void rs6000_split_lock_test_and_set (rtx, rtx, rtx, rtx); +-extern void rs6000_emit_swdivsf (rtx, rtx, rtx); +-extern void rs6000_emit_swdivdf (rtx, rtx, rtx); +-extern void rs6000_emit_swrsqrtsf (rtx, rtx); ++extern void rs6000_emit_swdiv (rtx, rtx, rtx, bool); ++extern void rs6000_emit_swrsqrt (rtx, rtx); + extern void output_toc (FILE *, rtx, int, enum machine_mode); + extern rtx rs6000_longcall_ref (rtx); + extern void rs6000_fatal_bad_address (rtx); +-extern rtx create_TOC_reference (rtx); ++extern rtx create_TOC_reference (rtx, rtx); + extern void rs6000_split_multireg_move (rtx, rtx); + extern void rs6000_emit_move (rtx, rtx, enum machine_mode); + extern rtx rs6000_secondary_memory_needed_rtx (enum machine_mode); +@@ -131,7 +133,10 @@ + + extern rtx rs6000_machopic_legitimize_pic_address (rtx, enum machine_mode, + rtx); ++extern rtx rs6000_address_for_fpconvert (rtx); + extern rtx rs6000_address_for_altivec (rtx); ++extern rtx rs6000_allocate_stack_temp (enum machine_mode, bool, bool); ++extern int rs6000_loop_align (rtx); + #endif /* RTX_CODE */ + + #ifdef TREE_CODE +Index: gcc/config/rs6000/t-rs6000 +=================================================================== +--- a/src/gcc/config/rs6000/t-rs6000 (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/t-rs6000 (.../ibm/gcc-4_5-branch) +@@ -27,7 +27,7 @@ + $(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \ + output.h $(BASIC_BLOCK_H) $(INTEGRATE_H) toplev.h $(GGC_H) $(HASHTAB_H) \ + $(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h gt-rs6000.h \ +- cfglayout.h ++ cfglayout.h cfgloop.h + + rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c \ + $(srcdir)/config/rs6000/rs6000-protos.h \ +Index: gcc/config/rs6000/rs6000-builtin.def +=================================================================== +--- a/src/gcc/config/rs6000/rs6000-builtin.def (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/rs6000-builtin.def (.../ibm/gcc-4_5-branch) +@@ -163,6 +163,7 @@ + RS6000_BUILTIN(ALTIVEC_BUILTIN_VRLB, RS6000_BTC_CONST) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VRLH, RS6000_BTC_CONST) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VRLW, RS6000_BTC_CONST) ++RS6000_BUILTIN(ALTIVEC_BUILTIN_VRSQRTFP, RS6000_BTC_FP_PURE) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VRSQRTEFP, RS6000_BTC_FP_PURE) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLB, RS6000_BTC_CONST) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLH, RS6000_BTC_CONST) +@@ -273,6 +274,7 @@ + RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V16QI, RS6000_BTC_CONST) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V4SF, RS6000_BTC_CONST) + RS6000_BUILTIN(ALTIVEC_BUILTIN_COPYSIGN_V4SF, RS6000_BTC_CONST) ++RS6000_BUILTIN(ALTIVEC_BUILTIN_VRECIPFP, RS6000_BTC_FP_PURE) + + /* Altivec overloaded builtins. */ + /* For now, don't set the classification for overloaded functions. +@@ -355,10 +357,12 @@ + RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PACKSU, RS6000_BTC_MISC) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PERM, RS6000_BTC_MISC) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RE, RS6000_BTC_MISC) ++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RECIP, RS6000_BTC_FP_PURE) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RL, RS6000_BTC_MISC) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RINT, RS6000_BTC_MISC) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ROUND, RS6000_BTC_MISC) +-RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RSQRTE, RS6000_BTC_MISC) ++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RSQRT, RS6000_BTC_FP_PURE) ++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RSQRTE, RS6000_BTC_FP_PURE) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SEL, RS6000_BTC_MISC) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SL, RS6000_BTC_MISC) + RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SLD, RS6000_BTC_MISC) +@@ -971,6 +975,10 @@ + RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEL_V2DI, RS6000_BTC_CONST) + RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEH_V2DF, RS6000_BTC_CONST) + RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEH_V2DI, RS6000_BTC_CONST) ++RS6000_BUILTIN(VSX_BUILTIN_VEC_RSQRT_V4SF, RS6000_BTC_FP_PURE) ++RS6000_BUILTIN(VSX_BUILTIN_VEC_RSQRT_V2DF, RS6000_BTC_FP_PURE) ++RS6000_BUILTIN(VSX_BUILTIN_RECIP_V4SF, RS6000_BTC_FP_PURE) ++RS6000_BUILTIN(VSX_BUILTIN_RECIP_V2DF, RS6000_BTC_FP_PURE) + + /* VSX overloaded builtins, add the overloaded functions not present in + Altivec. */ +@@ -1005,4 +1013,5 @@ + RS6000_BUILTIN(RS6000_BUILTIN_RECIP, RS6000_BTC_FP_PURE) + RS6000_BUILTIN(RS6000_BUILTIN_RECIPF, RS6000_BTC_FP_PURE) + RS6000_BUILTIN(RS6000_BUILTIN_RSQRTF, RS6000_BTC_FP_PURE) ++RS6000_BUILTIN(RS6000_BUILTIN_RSQRT, RS6000_BTC_FP_PURE) + RS6000_BUILTIN(RS6000_BUILTIN_BSWAP_HI, RS6000_BTC_CONST) +Index: gcc/config/rs6000/rs6000-c.c +=================================================================== +--- a/src/gcc/config/rs6000/rs6000-c.c (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/rs6000-c.c (.../ibm/gcc-4_5-branch) +@@ -1,5 +1,5 @@ + /* Subroutines for the C front end on the POWER and PowerPC architectures. +- Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 ++ Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + Contributed by Zack Weinberg +@@ -363,6 +363,16 @@ + builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp"); + builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp"); + } ++ if (RS6000_RECIP_HAVE_RE_P (DFmode)) ++ builtin_define ("__RECIP__"); ++ if (RS6000_RECIP_HAVE_RE_P (SFmode)) ++ builtin_define ("__RECIPF__"); ++ if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)) ++ builtin_define ("__RSQRTE__"); ++ if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)) ++ builtin_define ("__RSQRTEF__"); ++ if (TARGET_RECIP_PRECISION) ++ builtin_define ("__RECIP_PRECISION__"); + + /* Tell users they can use __builtin_bswap{16,64}. */ + builtin_define ("__HAVE_BSWAP__"); +@@ -376,6 +386,20 @@ + builtin_define ("__LONGDOUBLE128"); + } + ++ switch (TARGET_CMODEL) ++ { ++ /* Deliberately omit __CMODEL_SMALL__ since that was the default ++ before --mcmodel support was added. */ ++ case CMODEL_MEDIUM: ++ builtin_define ("__CMODEL_MEDIUM__"); ++ break; ++ case CMODEL_LARGE: ++ builtin_define ("__CMODEL_LARGE__"); ++ break; ++ default: ++ break; ++ } ++ + switch (rs6000_current_abi) + { + case ABI_V4: +@@ -480,10 +504,22 @@ + RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP, ++ RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP, ++ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, ++ { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF, ++ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, ++ { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP, ++ RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_VEC_RSQRT_V2DF, ++ RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP, ++ RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ, +Index: gcc/config/rs6000/rs6000.opt +=================================================================== +--- a/src/gcc/config/rs6000/rs6000.opt (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/rs6000.opt (.../ibm/gcc-4_5-branch) +@@ -1,6 +1,7 @@ + ; Options for the rs6000 port of the compiler + ; +-; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. ++; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 ++; Free Software Foundation, Inc. + ; Contributed by Aldy Hernandez . + ; + ; This file is part of GCC. +@@ -115,6 +116,14 @@ + Target Report Mask(POPCNTD) + Use PowerPC V2.06 popcntd instruction + ++mfriz ++Target Report Var(TARGET_FRIZ) Init(-1) ++Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions ++ ++mveclibabi= ++Target RejectNegative Joined Var(rs6000_veclibabi_name) ++Vector library ABI to use ++ + mvsx + Target Report Mask(VSX) + Use vector/scalar (VSX) instructions +@@ -167,10 +176,6 @@ + Target Report Var(TARGET_AVOID_XFORM) Init(-1) + Avoid generation of indexed load/store instructions when possible + +-mfused-madd +-Target Report Var(TARGET_FUSED_MADD) Init(1) +-Generate fused multiply/add instructions +- + mtls-markers + Target Report Var(tls_markers) Init(1) + Mark __tls_get_addr calls with argument info +@@ -195,9 +200,17 @@ + Conform more closely to IBM XLC semantics + + mrecip +-Target Report Var(TARGET_RECIP) +-Generate software reciprocal sqrt for better throughput ++Target Report ++Generate software reciprocal divide and square root for better throughput. + ++mrecip= ++Target Report RejectNegative Joined ++Generate software reciprocal divide and square root for better throughput. ++ ++mrecip-precision ++Target Report Mask(RECIP_PRECISION) ++Assume that the reciprocal estimate instructions provide more accuracy. ++ + mno-fp-in-toc + Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) + Do not place floating point constants in TOC +Index: gcc/config/rs6000/linux64.h +=================================================================== +--- a/src/gcc/config/rs6000/linux64.h (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/linux64.h (.../ibm/gcc-4_5-branch) +@@ -63,6 +63,16 @@ + + #define TARGET_PROFILE_KERNEL profile_kernel + ++#define TARGET_USES_LINUX64_OPT 1 ++#ifdef HAVE_LD_LARGE_TOC ++extern enum rs6000_cmodel cmodel; ++#undef TARGET_CMODEL ++#define TARGET_CMODEL cmodel ++#define SET_CMODEL(opt) cmodel = opt ++#else ++#define SET_CMODEL(opt) do {} while (0) ++#endif ++ + #undef PROCESSOR_DEFAULT + #define PROCESSOR_DEFAULT PROCESSOR_POWER6 + #undef PROCESSOR_DEFAULT64 +@@ -114,6 +124,23 @@ + target_flags |= MASK_POWERPC64; \ + error ("-m64 requires a PowerPC64 cpu"); \ + } \ ++ if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ ++ { \ ++ if (rs6000_explicit_options.cmodel \ ++ && cmodel != CMODEL_SMALL) \ ++ error ("-mcmodel incompatible with other toc options"); \ ++ SET_CMODEL (CMODEL_SMALL); \ ++ } \ ++ else \ ++ { \ ++ if (!rs6000_explicit_options.cmodel) \ ++ SET_CMODEL (CMODEL_MEDIUM); \ ++ if (cmodel != CMODEL_SMALL) \ ++ { \ ++ TARGET_NO_FP_IN_TOC = 0; \ ++ TARGET_NO_SUM_IN_TOC = 0; \ ++ } \ ++ } \ + } \ + else \ + { \ +@@ -124,6 +151,11 @@ + TARGET_PROFILE_KERNEL = 0; \ + error (INVALID_32BIT, "profile-kernel"); \ + } \ ++ if (rs6000_explicit_options.cmodel) \ ++ { \ ++ SET_CMODEL (CMODEL_SMALL); \ ++ error (INVALID_32BIT, "cmodel"); \ ++ } \ + } \ + } \ + while (0) +@@ -503,8 +535,6 @@ + #undef DRAFT_V4_STRUCT_RET + #define DRAFT_V4_STRUCT_RET (!TARGET_64BIT) + +-#define TARGET_ASM_FILE_END rs6000_elf_end_indicate_exec_stack +- + #define TARGET_POSIX_IO + + #define LINK_GCC_C_SEQUENCE_SPEC \ +Index: gcc/config/rs6000/rs6000.c +=================================================================== +--- a/src/gcc/config/rs6000/rs6000.c (.../gcc-4_5-branch) ++++ b/src/gcc/config/rs6000/rs6000.c (.../ibm/gcc-4_5-branch) +@@ -1,6 +1,6 @@ + /* Subroutines used for code generation on IBM RS/6000. + Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 ++ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) + +@@ -51,6 +51,7 @@ + #include "langhooks.h" + #include "reload.h" + #include "cfglayout.h" ++#include "cfgloop.h" + #include "sched-int.h" + #include "gimple.h" + #include "tree-flow.h" +@@ -73,6 +74,7 @@ + + /* Structure used to define the rs6000 stack */ + typedef struct rs6000_stack { ++ int reload_completed; /* stack info won't change from here on */ + int first_gp_reg_save; /* first callee saved GP register used */ + int first_fp_reg_save; /* first callee saved FP register used */ + int first_altivec_reg_save; /* first callee saved AltiVec register used */ +@@ -109,6 +111,7 @@ + int spe_padding_size; + HOST_WIDE_INT total_size; /* total bytes allocated for stack */ + int spe_64bit_regs_used; ++ int savres_strategy; + } rs6000_stack_t; + + /* A C structure for machine-specific, per-function data. +@@ -154,6 +157,9 @@ + /* Align branch targets. */ + static GTY(()) bool rs6000_align_branch_targets; + ++/* Non-zero to allow overriding loop alignment. */ ++static int can_override_loop_align = 0; ++ + /* Support for -msched-costly-dep option. */ + const char *rs6000_sched_costly_dep_str; + enum rs6000_dependence_cost rs6000_sched_costly_dep; +@@ -234,6 +240,14 @@ + /* Width in bits of a pointer. */ + unsigned rs6000_pointer_size; + ++#ifdef HAVE_AS_GNU_ATTRIBUTE ++/* Flag whether floating point values have been passed/returned. */ ++static bool rs6000_passes_float; ++/* Flag whether vector values have been passed/returned. */ ++static bool rs6000_passes_vector; ++/* Flag whether small (<= 8 byte) structures have been returned. */ ++static bool rs6000_returns_struct; ++#endif + + /* Value is TRUE if register/mode pair is acceptable. */ + bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; +@@ -280,6 +294,9 @@ + /* String from -malign-XXXXX. */ + int rs6000_alignment_flags; + ++/* Code model for 64-bit linux. */ ++enum rs6000_cmodel cmodel; ++ + /* True for any options that were explicitly set. */ + static struct { + bool aix_struct_ret; /* True if -maix-struct-ret was used. */ +@@ -291,6 +308,7 @@ + bool long_double; /* True if -mlong-double- was used. */ + bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */ + bool vrsave; /* True if -mvrsave was used. */ ++ bool cmodel; /* True if -mcmodel was used. */ + } rs6000_explicit_options; + + struct builtin_description +@@ -317,6 +335,61 @@ + + /* Map selected modes to types for builtins. */ + static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2]; ++ ++/* What modes to automatically generate reciprocal divide estimate (fre) and ++ reciprocal sqrt (frsqrte) for. */ ++unsigned char rs6000_recip_bits[MAX_MACHINE_MODE]; ++ ++/* Masks to determine which reciprocal esitmate instructions to generate ++ automatically. */ ++enum rs6000_recip_mask { ++ RECIP_SF_DIV = 0x001, /* Use divide estimate */ ++ RECIP_DF_DIV = 0x002, ++ RECIP_V4SF_DIV = 0x004, ++ RECIP_V2DF_DIV = 0x008, ++ ++ RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */ ++ RECIP_DF_RSQRT = 0x020, ++ RECIP_V4SF_RSQRT = 0x040, ++ RECIP_V2DF_RSQRT = 0x080, ++ ++ /* Various combination of flags for -mrecip=xxx. */ ++ RECIP_NONE = 0, ++ RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV ++ | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT ++ | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT), ++ ++ RECIP_HIGH_PRECISION = RECIP_ALL, ++ ++ /* On low precision machines like the power5, don't enable double precision ++ reciprocal square root estimate, since it isn't accurate enough. */ ++ RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT)) ++}; ++ ++static unsigned int rs6000_recip_control; ++static const char *rs6000_recip_name; ++ ++/* -mrecip options. */ ++static struct ++{ ++ const char *string; /* option name */ ++ unsigned int mask; /* mask bits to set */ ++} recip_options[] = { ++ { "all", RECIP_ALL }, ++ { "none", RECIP_NONE }, ++ { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV ++ | RECIP_V2DF_DIV) }, ++ { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) }, ++ { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) }, ++ { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT ++ | RECIP_V2DF_RSQRT) }, ++ { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) }, ++ { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) }, ++}; ++ ++/* 2 argument gen function typedef. */ ++typedef rtx (*gen_2arg_fn_t) (rtx, rtx, rtx); ++ + + /* Target cpu costs. */ + +@@ -871,6 +944,9 @@ + #undef RS6000_BUILTIN + #undef RS6000_BUILTIN_EQUATE + ++/* Support for -mveclibabi= to control which vector library to use. */ ++static tree (*rs6000_veclib_handler) (tree, tree, tree); ++ + + static bool rs6000_function_ok_for_sibcall (tree, tree); + static const char *rs6000_invalid_within_doloop (const_rtx); +@@ -910,8 +986,8 @@ + static rtx rs6000_make_savres_rtx (rs6000_stack_t *, rtx, int, + enum machine_mode, bool, bool, bool); + static bool rs6000_reg_live_or_pic_offset_p (int); ++static tree rs6000_builtin_vectorized_libmass (tree, tree, tree); + static tree rs6000_builtin_vectorized_function (tree, tree, tree); +-static int rs6000_savres_strategy (rs6000_stack_t *, bool, int, int); + static void rs6000_restore_saved_cr (rtx, int); + static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT); + static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT); +@@ -925,7 +1001,7 @@ + static int rs6000_elf_reloc_rw_mask (void); + static void rs6000_elf_asm_out_constructor (rtx, int); + static void rs6000_elf_asm_out_destructor (rtx, int); +-static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED; ++static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED; + static void rs6000_elf_asm_init_sections (void); + static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx, + unsigned HOST_WIDE_INT); +@@ -1046,6 +1122,7 @@ + static rtx altivec_expand_vec_ext_builtin (tree, rtx); + static int get_element_number (tree, tree); + static bool rs6000_handle_option (size_t, const char *, int); ++static int rs6000_loop_align_max_skip (rtx); + static void rs6000_parse_tls_size_option (void); + static void rs6000_parse_yes_no_option (const char *, const char *, int *); + static int first_altivec_reg_to_save (void); +@@ -1549,6 +1626,9 @@ + #undef TARGET_FUNCTION_VALUE + #define TARGET_FUNCTION_VALUE rs6000_function_value + ++#undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP ++#define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip ++ + struct gcc_target targetm = TARGET_INITIALIZER; + + /* Return number of consecutive hard regs needed starting at reg REGNO +@@ -1801,6 +1881,27 @@ + if (nl) + fputs (nl, stderr); + ++ if (rs6000_recip_control) ++ { ++ fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control); ++ ++ for (m = 0; m < NUM_MACHINE_MODES; ++m) ++ if (rs6000_recip_bits[m]) ++ { ++ fprintf (stderr, ++ "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n", ++ GET_MODE_NAME (m), ++ (RS6000_RECIP_AUTO_RE_P (m) ++ ? "auto" ++ : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")), ++ (RS6000_RECIP_AUTO_RSQRTE_P (m) ++ ? "auto" ++ : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none"))); ++ } ++ ++ fputs ("\n", stderr); ++ } ++ + switch (rs6000_sched_costly_dep) + { + case max_dep_latency: +@@ -2008,8 +2109,9 @@ + rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; +- if (TARGET_VSX_SCALAR_DOUBLE) +- rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; ++ rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY ++ ? VSX_REGS ++ : FLOAT_REGS); + } + + if (TARGET_ALTIVEC) +@@ -2087,8 +2189,108 @@ + if (TARGET_E500_DOUBLE) + rs6000_class_max_nregs[DFmode][GENERAL_REGS] = 1; + ++ /* Calculate which modes to automatically generate code to use a the ++ reciprocal divide and square root instructions. In the future, possibly ++ automatically generate the instructions even if the user did not specify ++ -mrecip. The older machines double precision reciprocal sqrt estimate is ++ not accurate enough. */ ++ memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits)); ++ if (TARGET_FRES) ++ rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE; ++ if (TARGET_FRE) ++ rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE; ++ if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)) ++ rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE; ++ if (VECTOR_UNIT_VSX_P (V2DFmode)) ++ rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE; ++ ++ if (TARGET_FRSQRTES) ++ rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE; ++ if (TARGET_FRSQRTE) ++ rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE; ++ if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)) ++ rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE; ++ if (VECTOR_UNIT_VSX_P (V2DFmode)) ++ rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE; ++ ++ if (rs6000_recip_control) ++ { ++ if (!flag_finite_math_only) ++ warning (0, "-mrecip requires -ffinite-math or -ffast-math"); ++ if (flag_trapping_math) ++ warning (0, "-mrecip requires -fno-trapping-math or -ffast-math"); ++ if (!flag_reciprocal_math) ++ warning (0, "-mrecip requires -freciprocal-math or -ffast-math"); ++ if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math) ++ { ++ if (RS6000_RECIP_HAVE_RE_P (SFmode) ++ && (rs6000_recip_control & RECIP_SF_DIV) != 0) ++ rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE; ++ ++ if (RS6000_RECIP_HAVE_RE_P (DFmode) ++ && (rs6000_recip_control & RECIP_DF_DIV) != 0) ++ rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE; ++ ++ if (RS6000_RECIP_HAVE_RE_P (V4SFmode) ++ && (rs6000_recip_control & RECIP_V4SF_DIV) != 0) ++ rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE; ++ ++ if (RS6000_RECIP_HAVE_RE_P (V2DFmode) ++ && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) ++ rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE; ++ ++ if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode) ++ && (rs6000_recip_control & RECIP_SF_RSQRT) != 0) ++ rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE; ++ ++ if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode) ++ && (rs6000_recip_control & RECIP_DF_RSQRT) != 0) ++ rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE; ++ ++ if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode) ++ && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0) ++ rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE; ++ ++ if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode) ++ && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0) ++ rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE; ++ } ++ } ++ + if (TARGET_DEBUG_REG) + rs6000_debug_reg_global (); ++ ++ if (TARGET_DEBUG_COST || TARGET_DEBUG_REG) ++ fprintf (stderr, ++ "SImode variable mult cost = %d\n" ++ "SImode constant mult cost = %d\n" ++ "SImode short constant mult cost = %d\n" ++ "DImode multipliciation cost = %d\n" ++ "SImode division cost = %d\n" ++ "DImode division cost = %d\n" ++ "Simple fp operation cost = %d\n" ++ "DFmode multiplication cost = %d\n" ++ "SFmode division cost = %d\n" ++ "DFmode division cost = %d\n" ++ "cache line size = %d\n" ++ "l1 cache size = %d\n" ++ "l2 cache size = %d\n" ++ "simultaneous prefetches = %d\n" ++ "\n", ++ rs6000_cost->mulsi, ++ rs6000_cost->mulsi_const, ++ rs6000_cost->mulsi_const9, ++ rs6000_cost->muldi, ++ rs6000_cost->divsi, ++ rs6000_cost->divdi, ++ rs6000_cost->fp, ++ rs6000_cost->dmul, ++ rs6000_cost->sdiv, ++ rs6000_cost->ddiv, ++ rs6000_cost->cache_line_size, ++ rs6000_cost->l1_cache_size, ++ rs6000_cost->l2_cache_size, ++ rs6000_cost->simultaneous_prefetches); + } + + #if TARGET_MACHO +@@ -2265,15 +2467,16 @@ + | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND}, + {"power6", PROCESSOR_POWER6, + POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT +- | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP}, ++ | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP ++ | MASK_RECIP_PRECISION}, + {"power6x", PROCESSOR_POWER6, + POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT + | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP +- | MASK_MFPGPR}, +- {"power7", PROCESSOR_POWER7, ++ | MASK_MFPGPR | MASK_RECIP_PRECISION}, ++ {"power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */ + POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF + | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD +- | MASK_VSX}, /* Don't add MASK_ISEL by default */ ++ | MASK_VSX | MASK_RECIP_PRECISION}, + {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, + {"powerpc64", PROCESSOR_POWERPC64, + POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, +@@ -2301,9 +2504,31 @@ + | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC + | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW + | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP +- | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE) ++ | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE ++ | MASK_RECIP_PRECISION) + }; + ++ /* Masks for instructions set at various powerpc ISAs. */ ++ enum { ++ ISA_2_1_MASKS = MASK_MFCRF, ++ ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB), ++ ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND), ++ ++ /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't ++ add ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, ++ fsel, fre, fsqrt, etc. were no longer documented as optional. Group ++ masks by server and embedded. */ ++ ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION ++ | MASK_PPC_GFXOPT | MASK_PPC_GPOPT), ++ ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP), ++ ++ /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but ++ altivec is a win so enable it. */ ++ ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD), ++ ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC ++ | MASK_VSX) ++ }; ++ + /* Numerous experiment shows that IRA based loop pressure + calculation works better for RTL loop invariant motion on targets + with enough (>= 32) registers. It is an expensive optimization. +@@ -2442,11 +2667,27 @@ + { + warning (0, msg); + target_flags &= ~ MASK_VSX; ++ target_flags_explicit |= MASK_VSX; + } +- else if (TARGET_VSX && !TARGET_ALTIVEC) +- target_flags |= MASK_ALTIVEC; + } + ++ /* For the newer switches (vsx, dfp, etc.) set some of the older options, ++ unless the user explicitly used the -mno-