diff -Nru golang-golang-x-arch-0.0~git20200511.f7c7858/arm64/arm64asm/inst.go golang-golang-x-arch-0.0~git20201207.1e68675/arm64/arm64asm/inst.go --- golang-golang-x-arch-0.0~git20200511.f7c7858/arm64/arm64asm/inst.go 2020-07-07 17:19:54.000000000 +0000 +++ golang-golang-x-arch-0.0~git20201207.1e68675/arm64/arm64asm/inst.go 2020-12-17 16:24:41.000000000 +0000 @@ -538,10 +538,12 @@ Extend ExtShift // Amount indicates the index shift amount (but also see ShiftMustBeZero field below). Amount uint8 - // ShiftMustBeZero is set to true when the shift amount must be 0, even if the - // Amount field is not 0. In GNU syntax, a #0 shift amount is printed if Amount - // is not 0 but ShiftMustBeZero is true; #0 is not printed if Amount is 0 and - // ShiftMustBeZero is true. Both cases represent shift by 0 bit. + // Refer to ARM reference manual, for byte load/store(register), the index + // shift amount must be 0, encoded in "S" as 0 if omitted, or as 1 if present. + // a.ShiftMustBeZero is set true indicates the index shift amount must be 0. + // In GNU syntax, a #0 shift amount is printed if Amount is 1 but ShiftMustBeZero + // is true; #0 is not printed if Amount is 0 and ShiftMustBeZero is true. + // Both cases represent shift by 0 bit. ShiftMustBeZero bool } diff -Nru golang-golang-x-arch-0.0~git20200511.f7c7858/arm64/arm64asm/plan9x.go golang-golang-x-arch-0.0~git20201207.1e68675/arm64/arm64asm/plan9x.go --- golang-golang-x-arch-0.0~git20200511.f7c7858/arm64/arm64asm/plan9x.go 2020-07-07 17:19:54.000000000 +0000 +++ golang-golang-x-arch-0.0~git20201207.1e68675/arm64/arm64asm/plan9x.go 2020-12-17 16:24:41.000000000 +0000 @@ -595,14 +595,18 @@ } if a.Extend == lsl { + // Refer to ARM reference manual, for byte load/store(register), the index + // shift amount must be 0, encoded in "S" as 0 if omitted, or as 1 if present. // a.Amount indicates the index shift amount, encoded in "S" field. - // a.ShiftMustBeZero is set true when the index shift amount must be 0, - // even if the a.Amount field is not 0. - // When a.ShiftMustBeZero is ture, GNU syntax prints #0 shift amount if - // "S" equals to 1, or does not print #0 shift amount if "S" equals to 0. - // Go syntax should never print a zero index shift amount. + // a.ShiftMustBeZero is set true indicates the index shift amount must be 0. + // When a.ShiftMustBeZero is true, GNU syntax prints "[Xn, Xm lsl #0]" if "S" + // equals to 1, or prints "[Xn, Xm]" if "S" equals to 0. if a.Amount != 0 && !a.ShiftMustBeZero { index = fmt.Sprintf("(%s<<%d)", indexreg, a.Amount) + } else if a.ShiftMustBeZero && a.Amount == 1 { + // When a.ShiftMustBeZero is ture, Go syntax prints "(Rm<<0)" if "a.Amount" + // equals to 1. + index = fmt.Sprintf("(%s<<0)", indexreg) } else { index = fmt.Sprintf("(%s)", indexreg) } diff -Nru golang-golang-x-arch-0.0~git20200511.f7c7858/arm64/arm64asm/testdata/plan9cases.txt golang-golang-x-arch-0.0~git20201207.1e68675/arm64/arm64asm/testdata/plan9cases.txt --- golang-golang-x-arch-0.0~git20200511.f7c7858/arm64/arm64asm/testdata/plan9cases.txt 2020-07-07 17:19:55.000000000 +0000 +++ golang-golang-x-arch-0.0~git20201207.1e68675/arm64/arm64asm/testdata/plan9cases.txt 2020-12-17 16:24:41.000000000 +0000 @@ -137,7 +137,7 @@ 8ca74238| MOVBU.P 42(R28), R12 4e5c5e38| MOVBU.W -27(R2), R14 03936d39| MOVBU 2916(R24), R3 -577a6e38| MOVBU (R18)(R14), R23 +577a6e38| MOVBU (R18)(R14<<0), R23 adb54678| MOVHU.P 107(R13), R13 820f4c78| MOVHU.W 192(R28), R2 92787579| MOVHU 6844(R4), R18 @@ -147,7 +147,7 @@ 18ee9438| MOVB.W -178(R16), R24 16b9c639| MOVBW 430(R8), R22 37958f39| MOVB 997(R9), R23 -af7ae238| MOVBW (R21)(R2), R15 +af7ae238| MOVBW (R21)(R2<<0), R15 1568fa38| MOVBW (R0)(R26), R21 744bbf38| MOVB (R27)(ZR.UXTW), R20 f069a538| MOVB (R15)(R5), R16 @@ -696,7 +696,7 @@ 8e8a7bbd| FMOVS 15240(R20), F14 8e3c7afd| FMOVD 29816(R4), F14 f2aeff3d| MOVD 65200(R23), V18 -1d78793c| MOVD (R0)(R25), V29 +1d78793c| MOVD (R0)(R25<<0), V29 b8f15d3c| VLDUR -33(R13), V24 95635c7c| VLDUR -58(R28), V21 27d046bc| VLDUR 109(R1), V7 @@ -1143,7 +1143,7 @@ 0c554b38| MOVBU.P 181(R8), R12 054f5938| MOVBU.W -108(R24), R5 1f206539| MOVBU 2376(R0), ZR -73796a38| MOVBU (R11)(R10), R19 +73796a38| MOVBU (R11)(R10<<0), R19 a8b74f78| MOVHU.P 251(R29), R8 021e5e78| MOVHU.W -31(R16), R2 ec126b79| MOVHU 5512(R23), R12 @@ -1155,7 +1155,7 @@ 7d74c039| MOVBW 29(R3), R29 7d1f8539| MOVB 327(R27), R29 225bff38| MOVBW (R25)(ZR.UXTW), R2 -6a7bed38| MOVBW (R27)(R13), R10 +6a7bed38| MOVBW (R27)(R13<<0), R10 0f69b538| MOVB (R8)(R21), R15 c796cc78| MOVHW.P 201(R22), R7 50268e78| MOVH.P 226(R18), R16 @@ -1701,7 +1701,7 @@ 0cc4e93d| MOVD 42768(R0), V12 e1c4211c| FMOVS 69159(PC), F1 2071c35c| FMOVD -124023(PC), F0 -ae79703c| MOVD (R13)(R16), V14 +ae79703c| MOVD (R13)(R16<<0), V14 38fb67bc| FMOVS (R25)(R7.SXTX<<2), F24 3e6b6dfc| FMOVD (R25)(R13), F30 a278ff3c| MOVD (R5)(ZR<<4), V2 @@ -1925,7 +1925,7 @@ b84f30fd| FMOVD F24, 24728(R29) 3cee993d| MOVD V28, 26544(R17) 4348293c| MOVD V3, (R2)(R9.UXTW) -ed7b253c| MOVD V13, (RSP)(R5) +ed7b253c| MOVD V13, (RSP)(R5<<0) 8fc9357c| MOVD V15, (R12)(R21.SXTW) 87f832bc| FMOVS F7, (R4)(R18.SXTX<<2) f1ea38fc| FMOVD F17, (R23)(R24.SXTX) @@ -2164,7 +2164,7 @@ 4491c939| MOVBW 612(R10), R4 497e8039| MOVB 31(R18), R9 7d6bf638| MOVBW (R27)(R22), R29 -e578ba38| MOVB (R7)(R26), R5 +e578ba38| MOVB (R7)(R26<<0), R5 9f06ca78| MOVHW.P 160(R20), ZR 15c59d78| MOVH.P -36(R8), R21 c07fd278| MOVHW.W -217(R30), R0 @@ -2309,7 +2309,7 @@ 1b441b38| MOVB.P R27, -76(R0) d69c0f38| MOVB.W R22, 249(R6) b7ce0d39| MOVB R23, 883(R21) -2b7b3938| MOVB R11, (R25)(R25) +2b7b3938| MOVB R11, (R25)(R25<<0) 4e771d78| MOVH.P R14, -41(R26) 64cc0b78| MOVH.W R4, 188(R3) 07b90279| MOVH R7, 348(R8) @@ -2940,7 +2940,7 @@ 409503fd| FMOVD F0, 1832(R10) 58a1963d| MOVD V24, 23168(R10) 51c8253c| MOVD V17, (R2)(R5.SXTW) -967b313c| MOVD V22, (R28)(R17) +967b313c| MOVD V22, (R28)(R17<<0) b4683e7c| MOVD V20, (R5)(R30) 64d9a33c| MOVD V4, (R11)(R3.SXTW<<4) e5e1143c| MOVD V5, -178(R15) @@ -3950,7 +3950,7 @@ aeb813fd| FMOVD F14, 10096(R5) 2cc4943d| MOVD V12, 21264(R1) e2f8263c| MOVD V2, (R7)(R6.SXTX) -1d79373c| MOVD V29, (R8)(R23) +1d79373c| MOVD V29, (R8)(R23<<0) bc70003c| MOVD V28, 7(R5) 7190157c| MOVD V17, -167(R3) 073309bc| FMOVS F7, 147(R24) @@ -4562,3 +4562,17 @@ 0b3c030e| VMOV V0.B[1], R11 2c3c0e0e| VMOV V1.H[3], R12 d7061a6f| VUSHR $6, V22.H8, V23.H8 +44f82638| MOVB R4, (R2)(R6.SXTX) +44e82638| MOVB R4, (R2)(R6.SXTX) +44682638| MOVB R4, (R2)(R6) +44782638| MOVB R4, (R2)(R6<<0) +44e8a638| MOVB (R2)(R6.SXTX), R4 +44f8a638| MOVB (R2)(R6.SXTX), R4 +4468a638| MOVB (R2)(R6), R4 +4478a638| MOVB (R2)(R6<<0), R4 +44e86638| MOVBU (R2)(R6.SXTX), R4 +44f86638| MOVBU (R2)(R6.SXTX), R4 +44686638| MOVBU (R2)(R6), R4 +44786638| MOVBU (R2)(R6<<0), R4 +ae7bbe38| MOVB (R29)(R30<<0), R14 +ae6bbe38| MOVB (R29)(R30), R14 diff -Nru golang-golang-x-arch-0.0~git20200511.f7c7858/debian/changelog golang-golang-x-arch-0.0~git20201207.1e68675/debian/changelog --- golang-golang-x-arch-0.0~git20200511.f7c7858/debian/changelog 2020-07-26 10:36:02.000000000 +0000 +++ golang-golang-x-arch-0.0~git20201207.1e68675/debian/changelog 2020-12-17 16:27:22.000000000 +0000 @@ -1,3 +1,15 @@ +golang-golang-x-arch (0.0~git20201207.1e68675-1) unstable; urgency=medium + + * Team upload. + * New upstream version 0.0~git20201207.1e68675 + * Backport patch to fix ppc64el test (Closes: #976939) + * Update debian/control + + Section -> golang + + debhelper-compat -> 13 + + Standards-Version -> 4.5.1 (no changes) + + -- Shengjing Zhu Fri, 18 Dec 2020 00:27:22 +0800 + golang-golang-x-arch (0.0~git20200511.f7c7858-3) unstable; urgency=medium * debian/control: diff -Nru golang-golang-x-arch-0.0~git20200511.f7c7858/debian/control golang-golang-x-arch-0.0~git20201207.1e68675/debian/control --- golang-golang-x-arch-0.0~git20200511.f7c7858/debian/control 2020-07-26 10:36:02.000000000 +0000 +++ golang-golang-x-arch-0.0~git20201207.1e68675/debian/control 2020-12-17 16:27:22.000000000 +0000 @@ -1,15 +1,15 @@ Source: golang-golang-x-arch -Section: devel +Section: golang Priority: optional Maintainer: Debian Go Packaging Team Uploaders: Emanuel Krivoy , Roger Shimizu Build-Depends: - debhelper-compat (= 12), + debhelper-compat (= 13), dh-golang, golang-any -Standards-Version: 4.5.0 +Standards-Version: 4.5.1 Homepage: https://github.com/golang/arch Vcs-Browser: https://salsa.debian.org/go-team/packages/golang-golang-x-arch Vcs-Git: https://salsa.debian.org/go-team/packages/golang-golang-x-arch.git diff -Nru golang-golang-x-arch-0.0~git20200511.f7c7858/debian/patches/0001-ppc64asm-ignore-m-tf-vsr-objdump-decoding-mismatches.patch golang-golang-x-arch-0.0~git20201207.1e68675/debian/patches/0001-ppc64asm-ignore-m-tf-vsr-objdump-decoding-mismatches.patch --- golang-golang-x-arch-0.0~git20200511.f7c7858/debian/patches/0001-ppc64asm-ignore-m-tf-vsr-objdump-decoding-mismatches.patch 1970-01-01 00:00:00.000000000 +0000 +++ golang-golang-x-arch-0.0~git20201207.1e68675/debian/patches/0001-ppc64asm-ignore-m-tf-vsr-objdump-decoding-mismatches.patch 2020-12-17 16:27:22.000000000 +0000 @@ -0,0 +1,28 @@ +From: "Paul E. Murphy" +Date: Thu, 17 Dec 2020 09:49:15 -0600 +Subject: ppc64asm: ignore m[tf]vsr* objdump decoding mismatches + +A recent binutils change prioritized extended mnemonics of these +instructions. These mismatches can be safely ignored. + +Fixes golang/go#43222 +Change-Id: Id94c228be6d45577ba9d4dd59730f88e785d2cb0 + +Change-Id: Ie3df612aad7aaba4798e13bab56b04291c703d48 +--- + ppc64/ppc64asm/objdump_test.go | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/ppc64/ppc64asm/objdump_test.go b/ppc64/ppc64asm/objdump_test.go +index b886f7b..5d48619 100644 +--- a/ppc64/ppc64asm/objdump_test.go ++++ b/ppc64/ppc64asm/objdump_test.go +@@ -57,6 +57,8 @@ func allowedMismatchObjdump(text string, size int, inst *Inst, dec ExtInst) bool + return true + case VSPLTB, VSPLTH, VSPLTW: // objdump generates unreasonable result "vspltw v6,v19,4" for 10c49a8c, the last 4 should be 0. + return true ++ case MTVSRWA, MTVSRWZ, MFVSRWZ, MFVSRD, MTVSRD: // We don't support extended mnemonics using VRs or FPRs ++ return true + } + if hasPrefix(text, "evm", "evl", "efs") { // objdump will disassemble them wrong (e.g. evmhoumia as vsldoi) + return true diff -Nru golang-golang-x-arch-0.0~git20200511.f7c7858/debian/patches/series golang-golang-x-arch-0.0~git20201207.1e68675/debian/patches/series --- golang-golang-x-arch-0.0~git20200511.f7c7858/debian/patches/series 1970-01-01 00:00:00.000000000 +0000 +++ golang-golang-x-arch-0.0~git20201207.1e68675/debian/patches/series 2020-12-17 16:27:22.000000000 +0000 @@ -0,0 +1 @@ +0001-ppc64asm-ignore-m-tf-vsr-objdump-decoding-mismatches.patch diff -Nru golang-golang-x-arch-0.0~git20200511.f7c7858/ppc64/pp64.csv golang-golang-x-arch-0.0~git20201207.1e68675/ppc64/pp64.csv --- golang-golang-x-arch-0.0~git20200511.f7c7858/ppc64/pp64.csv 2020-07-07 17:19:55.000000000 +0000 +++ golang-golang-x-arch-0.0~git20201207.1e68675/ppc64/pp64.csv 2020-12-17 16:24:41.000000000 +0000 @@ -530,17 +530,23 @@ "Load VSX Vector Doubleword*2 Indexed XX1-form","lxvd2x XT,RA,RB","31@0|T@6|RA@11|RB@16|844@21|TX@31|","" "Load VSX Vector Doubleword & Splat Indexed XX1-form","lxvdsx XT,RA,RB ( 0x7C00_0298 )","31@0|T@6|RA@11|RB@16|332@21|TX@31|","" "Load VSX Vector Word*4 Indexed XX1-form","lxvw4x XT,RA,RB","31@0|T@6|RA@11|RB@16|780@21|TX@31|","" +"Load VSX Vector Halfword*8 Indexed XX1-form","lxvh8x XT,RA,RB","31@0|T@6|RA@11|RB@16|812@21|TX@31|","" +"Load VSX Vector Byte*16 Indexed XX1-form","lxvb16x XT,RA,RB","31@0|T@6|RA@11|RB@16|876@21|TX@31|","" "Load VSX Vector DQ-form","lxv XT,DQ(RA)","61@0|T@6|RA@11|DQ@16|TX@28|1@29|","" "Load VSX Vector with Length X-form","lxvl XT,RA,RB","31@0|T@6|RA@11|RB@16|269@21|TX@31|","" "Load VSX Vector Left-justified with Length X-form","lxvll XT,RA,RB","31@0|T@6|RA@11|RB@16|301@21|TX@31|","" +"Load VSX Vector Indexed X-form","lxvx XT,RA,RB","31@0|T@6|RA@11|RB@16|4@21|///@25|12@26|TX@31|","" "Store VSX Scalar Doubleword Indexed XX1-form","stxsdx XS,RA,RB","31@0|S@6|RA@11|RB@16|716@21|SX@31|","" "Store VSX Scalar as Integer Word Indexed XX1-form","stxsiwx XS,RA,RB","31@0|S@6|RA@11|RB@16|140@21|SX@31|","" "Store VSX Scalar Single-Precision Indexed XX1-form","stxsspx XS,RA,RB","31@0|S@6|RA@11|RB@16|652@21|SX@31|","" "Store VSX Vector Doubleword*2 Indexed XX1-form","stxvd2x XS,RA,RB","31@0|S@6|RA@11|RB@16|972@21|SX@31|","" "Store VSX Vector Word*4 Indexed XX1-form","stxvw4x XS,RA,RB","31@0|S@6|RA@11|RB@16|908@21|SX@31|","" +"Store VSX Vector Halfword*4 Indexed XX1-form","stxvh8x XS,RA,RB","31@0|S@6|RA@11|RB@16|940@21|SX@31|","" +"Store VSX Vector Byte*16 Indexed XX1-form","stxvb16x XS,RA,RB","31@0|S@6|RA@11|RB@16|1004@21|SX@31|","" "Store VSX Vector DQ-form","stxv XS,DQ(RA)","61@0|S@6|RA@11|DQ@16|SX@28|5@29|","" "Store VSX Vector with Length X-form","stxvl XS,RA,RB","31@0|S@6|RA@11|RB@16|397@21|SX@31|","" "Store VSX Vector Left-justified with Length X-form","stxvll XS,RA,RB","31@0|S@6|RA@11|RB@16|429@21|SX@31|","" +"Store VSX Vector Indexed X-form","stxvx XS,RA,RB","31@0|S@6|RA@11|RB@16|396@21|SX@31|","" "VSX Scalar Absolute Value Double-Precision XX2-form","xsabsdp XT,XB","60@0|T@6|///@11|B@16|345@21|BX@30|TX@31|","" "VSX Scalar Add Double-Precision XX3-form","xsadddp XT,XA,XB","60@0|T@6|A@11|B@16|32@21|AX@29|BX@30|TX@31|","" "VSX Scalar Add Single-Precision XX3-form","xsaddsp XT,XA,XB","60@0|T@6|A@11|B@16|0@21|AX@29|BX@30|TX@31|","" @@ -678,6 +684,9 @@ "VSX Select XX4-form","xxsel XT,XA,XB,XC","60@0|T@6|A@11|B@16|C@21|3@26|CX@28|AX@29|BX@30|TX@31|","" "VSX Shift Left Double by Word Immediate XX3-form","xxsldwi XT,XA,XB,SHW","60@0|T@6|A@11|B@16|0@21|SHW@22|2@24|AX@29|BX@30|TX@31|","" "VSX Splat Word XX2-form","xxspltw XT,XB,UIM","60@0|T@6|///@11|UIM@14|B@16|164@21|BX@30|TX@31|","" +"VSX Vector Byte-Reverse Doubleword XX2-form","xxbrd XT,XB","60@0|T@6|23@11|B@16|475@21|BX@30|TX@31|","" +"VSX Vector Byte-Reverse Word XX2-form","xxbrw XT,XB","60@0|T@6|15@11|B@16|475@21|BX@30|TX@31|","" +"VSX Vector Byte-Reverse Halfword XX2-form","xxbrh XT,XB","60@0|T@6|7@11|B@16|475@21|BX@30|TX@31|","" "Bit Reversed Increment EVX-form","brinc RT,RA,RB","4@0|RT@6|RA@11|RB@16|527@21|","" "Vector Absolute Value EVX-form","evabs RT,RA","4@0|RT@6|RA@11|///@16|520@21|","" "Vector Add Immediate Word EVX-form","evaddiw RT,RB,UI","4@0|RT@6|UI@11|RB@16|514@21|","" diff -Nru golang-golang-x-arch-0.0~git20200511.f7c7858/ppc64/ppc64asm/plan9.go golang-golang-x-arch-0.0~git20201207.1e68675/ppc64/ppc64asm/plan9.go --- golang-golang-x-arch-0.0~git20200511.f7c7858/ppc64/ppc64asm/plan9.go 2020-07-07 17:19:55.000000000 +0000 +++ golang-golang-x-arch-0.0~git20201207.1e68675/ppc64/ppc64asm/plan9.go 2020-12-17 16:24:41.000000000 +0000 @@ -112,7 +112,7 @@ case STDCXCC, STWCXCC, STHCXCC, STBCXCC: return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")" - case STXVD2X, STXVW4X, STXSDX, STVX, STVXL, STVEBX, STVEHX, STVEWX, STXSIWX, STFDX, STFDUX, STFDPX, STFSX, STFSUX: + case STXVX, STXVD2X, STXVW4X, STXVH8X, STXVB16X, STXSDX, STVX, STVXL, STVEBX, STVEHX, STVEWX, STXSIWX, STFDX, STFDUX, STFDPX, STFSX, STFSUX: return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")" case STXV: @@ -127,7 +127,7 @@ } return op + " (" + args[2] + ")(" + args[1] + ")," + args[0] - case LXVD2X, LXVW4X, LVX, LVXL, LVSR, LVSL, LVEBX, LVEHX, LVEWX, LXSDX, LXSIWAX: + case LXVX, LXVD2X, LXVW4X, LXVH8X, LXVB16X, LVX, LVXL, LVSR, LVSL, LVEBX, LVEHX, LVEWX, LXSDX, LXSIWAX: return op + " (" + args[2] + ")(" + args[1] + ")," + args[0] case LXV: @@ -332,6 +332,7 @@ DIVDUO: "DIVDUV", DIVDUOCC: "DIVDUVCC", ADDI: "ADD", + MULLI: "MULLD", SRADI: "SRAD", SUBF: "SUB", STBCXCC: "STBCCC", diff -Nru golang-golang-x-arch-0.0~git20200511.f7c7858/ppc64/ppc64asm/tables.go golang-golang-x-arch-0.0~git20201207.1e68675/ppc64/ppc64asm/tables.go --- golang-golang-x-arch-0.0~git20200511.f7c7858/ppc64/ppc64asm/tables.go 2020-07-07 17:19:55.000000000 +0000 +++ golang-golang-x-arch-0.0~git20201207.1e68675/ppc64/ppc64asm/tables.go 2020-12-17 16:24:41.000000000 +0000 @@ -1,5 +1,5 @@ // DO NOT EDIT -// generated by: ppc64map -fmt=decoder ../pp64.csv +// generated by: ppc64map -fmt=decoder pp64.csv package ppc64asm @@ -727,17 +727,23 @@ LXVD2X LXVDSX LXVW4X + LXVH8X + LXVB16X LXV LXVL LXVLL + LXVX STXSDX STXSIWX STXSSPX STXVD2X STXVW4X + STXVH8X + STXVB16X STXV STXVL STXVLL + STXVX XSABSDP XSADDDP XSADDSP @@ -881,6 +887,9 @@ XXSEL XXSLDWI XXSPLTW + XXBRD + XXBRW + XXBRH BRINC EVABS EVADDIW @@ -2095,17 +2104,23 @@ LXVD2X: "lxvd2x", LXVDSX: "lxvdsx", LXVW4X: "lxvw4x", + LXVH8X: "lxvh8x", + LXVB16X: "lxvb16x", LXV: "lxv", LXVL: "lxvl", LXVLL: "lxvll", + LXVX: "lxvx", STXSDX: "stxsdx", STXSIWX: "stxsiwx", STXSSPX: "stxsspx", STXVD2X: "stxvd2x", STXVW4X: "stxvw4x", + STXVH8X: "stxvh8x", + STXVB16X: "stxvb16x", STXV: "stxv", STXVL: "stxvl", STXVLL: "stxvll", + STXVX: "stxvx", XSABSDP: "xsabsdp", XSADDDP: "xsadddp", XSADDSP: "xsaddsp", @@ -2249,6 +2264,9 @@ XXSEL: "xxsel", XXSLDWI: "xxsldwi", XXSPLTW: "xxspltw", + XXBRD: "xxbrd", + XXBRW: "xxbrw", + XXBRH: "xxbrh", BRINC: "brinc", EVABS: "evabs", EVADDIW: "evaddiw", @@ -4260,12 +4278,18 @@ [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, {LXVW4X, 0xfc0007fe, 0x7c000618, 0x0, // Load VSX Vector Word*4 Indexed XX1-form (lxvw4x XT,RA,RB) [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXVH8X, 0xfc0007fe, 0x7c000658, 0x0, // Load VSX Vector Halfword*8 Indexed XX1-form (lxvh8x XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXVB16X, 0xfc0007fe, 0x7c0006d8, 0x0, // Load VSX Vector Byte*16 Indexed XX1-form (lxvb16x XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, {LXV, 0xfc000007, 0xf4000001, 0x0, // Load VSX Vector DQ-form (lxv XT,DQ(RA)) [5]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}}, {LXVL, 0xfc0007fe, 0x7c00021a, 0x0, // Load VSX Vector with Length X-form (lxvl XT,RA,RB) [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, {LXVLL, 0xfc0007fe, 0x7c00025a, 0x0, // Load VSX Vector Left-justified with Length X-form (lxvll XT,RA,RB) [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {LXVX, 0xfc0007be, 0x7c000218, 0x40, // Load VSX Vector Indexed X-form (lxvx XT,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, {STXSDX, 0xfc0007fe, 0x7c000598, 0x0, // Store VSX Scalar Doubleword Indexed XX1-form (stxsdx XS,RA,RB) [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, {STXSIWX, 0xfc0007fe, 0x7c000118, 0x0, // Store VSX Scalar as Integer Word Indexed XX1-form (stxsiwx XS,RA,RB) @@ -4276,12 +4300,18 @@ [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, {STXVW4X, 0xfc0007fe, 0x7c000718, 0x0, // Store VSX Vector Word*4 Indexed XX1-form (stxvw4x XS,RA,RB) [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXVH8X, 0xfc0007fe, 0x7c000758, 0x0, // Store VSX Vector Halfword*4 Indexed XX1-form (stxvh8x XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXVB16X, 0xfc0007fe, 0x7c0007d8, 0x0, // Store VSX Vector Byte*16 Indexed XX1-form (stxvb16x XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, {STXV, 0xfc000007, 0xf4000005, 0x0, // Store VSX Vector DQ-form (stxv XS,DQ(RA)) [5]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}}, {STXVL, 0xfc0007fe, 0x7c00031a, 0x0, // Store VSX Vector with Length X-form (stxvl XS,RA,RB) [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, {STXVLL, 0xfc0007fe, 0x7c00035a, 0x0, // Store VSX Vector Left-justified with Length X-form (stxvll XS,RA,RB) [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, + {STXVX, 0xfc0007fe, 0x7c000318, 0x0, // Store VSX Vector Indexed X-form (stxvx XS,RA,RB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, {XSABSDP, 0xfc0007fc, 0xf0000564, 0x1f0000, // VSX Scalar Absolute Value Double-Precision XX2-form (xsabsdp XT,XB) [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, {XSADDDP, 0xfc0007f8, 0xf0000100, 0x0, // VSX Scalar Add Double-Precision XX3-form (xsadddp XT,XA,XB) @@ -4568,6 +4598,12 @@ [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}}, {XXSPLTW, 0xfc0007fc, 0xf0000290, 0x1c0000, // VSX Splat Word XX2-form (xxspltw XT,XB,UIM) [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_14_15}}, + {XXBRD, 0xfc1f07fc, 0xf017076c, 0x0, // VSX Vector Byte-Reverse Doubleword XX2-form (xxbrd XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XXBRW, 0xfc1f07fc, 0xf00f076c, 0x0, // VSX Vector Byte-Reverse Word XX2-form (xxbrw XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, + {XXBRH, 0xfc1f07fc, 0xf007076c, 0x0, // VSX Vector Byte-Reverse Halfword XX2-form (xxbrh XT,XB) + [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, {BRINC, 0xfc0007ff, 0x1000020f, 0x0, // Bit Reversed Increment EVX-form (brinc RT,RA,RB) [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, {EVABS, 0xfc0007ff, 0x10000208, 0xf800, // Vector Absolute Value EVX-form (evabs RT,RA) diff -Nru golang-golang-x-arch-0.0~git20200511.f7c7858/ppc64/ppc64asm/testdata/decode.txt golang-golang-x-arch-0.0~git20201207.1e68675/ppc64/ppc64asm/testdata/decode.txt --- golang-golang-x-arch-0.0~git20200511.f7c7858/ppc64/ppc64asm/testdata/decode.txt 2020-07-07 17:19:55.000000000 +0000 +++ golang-golang-x-arch-0.0~git20201207.1e68675/ppc64/ppc64asm/testdata/decode.txt 2020-12-17 16:24:41.000000000 +0000 @@ -52,6 +52,10 @@ fbe1ffd1| plan9 MOVDU R31,-48(R1) 7c941f19| gnu stxvw4x vs36,r20,r3 7c941f19| plan9 STXVW4X VS36,(R3)(R20) +7c941f59| gnu stxvh8x vs36,r20,r3 +7c941f59| plan9 STXVH8X VS36,(R3)(R20) +7c941fd9| gnu stxvb16x vs36,r20,r3 +7c941fd9| plan9 STXVB16X VS36,(R3)(R20) 7c6520a8| gnu ldarx r3,r5,r4 7c6520a8| plan9 LDAR (R4)(R5),R3 7c6803a6| plan9 MOVD R3,LR @@ -145,6 +149,7 @@ 7ca41896| plan9 MULHW R3,R4,R5 7ca41816| plan9 MULHWU R3,R4,R5 7ca421d2| plan9 MULLD R4,R4,R5 +1c63000a| plan9 MULLD R3,$10,R3 7ca419d3| plan9 MULLDCC R3,R4,R5 7ca41892| plan9 MULHD R3,R4,R5 7ca41893| plan9 MULHDCC R3,R4,R5 @@ -175,6 +180,7 @@ 7c851e30| plan9 SRAW R3,R4,R5 7c851c36| plan9 SRD R3,R4,R5 7c851e34| plan9 SRAD R3,R4,R5 +7c631ef4| plan9 EXTSWSLI R3,$3,R3 7c6400f4| plan9 POPCNTB R3,R4 7c6402f4| plan9 POPCNTW R3,R4 7c6403f4| plan9 POPCNTD R3,R4 @@ -417,14 +423,19 @@ 10611549| plan9 VNCIPHERLAST V1,V2,V3 104105c8| plan9 VSBOX V1,V2 7c241e98| plan9 LXVD2X (R3)(R4),VS1 +7c241e18| plan9 LXVW4X (R3)(R4),VS1 +7c241e58| plan9 LXVH8X (R3)(R4),VS1 +7c241ed8| plan9 LXVB16X (R3)(R4),VS1 f4230011| plan9 LXV 16(R3),VS1 7c23221a| plan9 LXVL R3,R4,VS1 7c23225a| plan9 LXVLL R3,R4,VS1 +7c241a18| plan9 LXVX (R3)(R4),VS1 7c241c98| plan9 LXSDX (R3)(R4),VS1 7c241f98| plan9 STXVD2X VS1,(R3)(R4) f4230015| plan9 STXV VS1,16(R3) 7c23231a| plan9 STXVL VS1,R3,R4 7c23235a| plan9 STXVLL VS1,R3,R4 +7c241b18| plan9 STXVX VS1,(R3)(R4) 7c241d98| plan9 STXSDX VS1,(R3)(R4) 7c241898| plan9 LXSIWAX (R3)(R4),VS1 7c241918| plan9 STXSIWX VS1,(R3)(R4) @@ -435,6 +446,9 @@ f0611550| plan9 XXLORC VS1,VS2,VS3 f06114d0| plan9 XXLXOR VS1,VS2,VS3 f08110f0| plan9 XXSEL VS1,VS2,VS3,VS4 +f0570f6c| plan9 XXBRD VS1,VS2 +f04f0f6c| plan9 XXBRW VS1,VS2 +f0470f6c| plan9 XXBRH VS1,VS2 f0611090| plan9 XXMRGHW VS1,VS2,VS3 f0410a90| plan9 XXSPLTW VS1,$1,VS2 f06110d0| plan9 XXPERM VS1,VS2,VS3 @@ -802,6 +816,8 @@ 7c23221a| gnu lxvl vs1,r3,r4 7c23225a| gnu lxvll vs1,r3,r4 7c241c98| gnu lxsdx vs1,r4,r3 +7c241a18| gnu lxvx vs1,r4,r3 +7c241b18| gnu stxvx vs1,r4,r3 7c241f98| gnu stxvd2x vs1,r4,r3 f4230015| gnu stxv vs1,16(r3) 7c23231a| gnu stxvl vs1,r3,r4 diff -Nru golang-golang-x-arch-0.0~git20200511.f7c7858/README.md golang-golang-x-arch-0.0~git20201207.1e68675/README.md --- golang-golang-x-arch-0.0~git20200511.f7c7858/README.md 2020-07-07 17:19:54.000000000 +0000 +++ golang-golang-x-arch-0.0~git20201207.1e68675/README.md 2020-12-17 16:24:41.000000000 +0000 @@ -1,5 +1,7 @@ # arch +[![Go Reference](https://pkg.go.dev/badge/golang.org/x/arch.svg)](https://pkg.go.dev/golang.org/x/arch) + This repository holds machine architecture information used by the Go toolchain. The parts needed in the main Go repository are copied in.